LG Innotek TWFMB001T Wi-Fi Module User Manual Op Desc

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SPECIFICATIONS
PRODUCT NAME :
Dual Band 2T2R MIMO Wi-Fi Module
MODEL NAME
TWFM-B001T
The information contained herein is the exclusive property of LG Innotek
and shall not be distributed, reproduced or disclosed in whole or no in part
without prior written permission of LG Innotek.
Designed
Checked
Approved
LG Innotek Co., Ltd.
S.C.Lee
2010.11.16
S.C.Lee
2010.11.16
D.S.Oh
2010.11.17
DOCUMENT No.
HC40645
PAGE
16
(00)-0073
DOCUMENT No :
REG. DATE : 2010.11.16
SPECIFICATION
REV. DATE : 2010.11.16
MODEL NAME : TWFM-B001T
HC40645
REV.NO : 1.0
PAGE : 1 / 16
1. Features
TWFM-B001T is the small size and low power module for IEEE 802.11a/b/g/n wireless
LAN. TWFM-B001T is based on Broadcom BCM43236 solution.
 IEEE 802.11 a/b/g/n Dual Band WLAN infrastructure
 Size : 42mm x 29mm x 6mm
 2.4GHz and 5GHz internal PA
 Two stream spatial multiplexing up to 300Mbps
 Monopole ANT (2T2R MIMO)
 Use on-chip OTP (One-Time Programmable)
 USB 2.0
 Supports drivers for Windows Vista, 2000, XP, Linux
 Security : WPA,WPA2,AES(TKIP) ,IEEE 802.1X
• Application: DTV, DVR, HD DVD Player, Blue-ray Disk Player, STB
2. Ordering Information
Model
Description
TWFM-B001T
Wi-Fi Module, Dual Band 2T2R MIMO
3. Label marking
①
TWFM-B001T
②
③
001EB2B00339 15351616
1009A2901
① Model No
④
⑤
④ Product Lot No. : 1009A2901
② MAC Address BAR Code
-10 : Year
③ MAC Address No.
- 09: Month
⑤ PIN Code
- Revision No. : A
©2010 LGIT. All rights reserved.
- 29 : Date
- 01 : Manufactured
Process
DOCUMENT No :
REG. DATE : 2010.11.16
SPECIFICATION
REV. DATE : 2010.11.16
MODEL NAME : TWFM-B001T
HC40645
REV.NO : 1.0
PAGE : 2 / 16
4. Block Diagram
BCM43236
RF
Switch+
diplexer
2.4GHz PA
5GHz PA
2x2
Radio
802.11n
PHY
In
nternal Bus
802.11n MAC
ANT
Security
OTP(2K bits)
USB 2
2.0
0 or
HSIC
USB Connector
ANT
GPIO
3.3V
1.2V
DC-DC
Main Clock(20MHz)
5V
< Fig.1 Hardware Block Diagram >
5. Absolute Maximum Ratings
Caution : The specifications
in Table 1 define levels at which p
permanent damage
g to the
device can occur. Function operation is not guaranteed under these conditions.
Operating at absolute maximum conditions for extend periods can adversely affect the
long-term reliability of the device.
Parameter
Min
Max
Unit
Storage Temperature
-10
+80
℃
Storage Humidity
90
6.0
Vdc
Supply Voltage
VDD_5V
< Table 1 Absolute Maximum Ratings >
. Other conditions
1) Do not use or store modules in the corrosive atmosphere, especially where chloride
gas, sulfide gas, acid, alkali, salt or the like are contained.
Also, avoid exposure to moisture.
2) Store the modules where the temperature
and relative humidity do not exceed 5 to 40℃ and 20 to 60%.
3) Assemble the modules within 6 months.
Check the soldering ability in case of 6 months over.
©2010 LGIT. All rights reserved.
DOCUMENT No :
REG. DATE : 2010.11.16
SPECIFICATION
REV. DATE : 2010.11.16
MODEL NAME : TWFM-B001T
HC40645
REV.NO : 1.0
PAGE : 3 / 16
6. Operating Conditions
Parameter
Min
Typ
Max
Unit
Operating Temperature
+60
℃
Operating Humidity
85
4.5
5.5
Vdc
Supply
Voltage
VDD_5V
7. Standard Test Conditions
The Test
Th
T t for
f electrical
l t i l specification
ifi ti shall
h ll be
b performed
d under
d the
th following
f ll i condition
diti
unless otherwise specified.
1). Ambient condition
. Temperature
. Humidity
25℃ ± 5℃
65% ± 5% R.H.
2) Power supply voltages
2).
. 5V (±5%) input power at the Module
3). Current consumption over recommended range of supply voltage and operating
conditions is like below.
When it’s tested, it must be supplied more than 2 times of maximal current.
FCC (Federal Communications Commission)
WARNING Thi
WARNING:
This equipment
t may generate
t or use radio
di ffrequency energy.
Changes or modifications to this equipment may cause harmful interference unless the modifications are expressly
approved in the instruction manual. The user could lose the authority to operate this equipment if an unauthorized
change or modification is made.
This device complies with Part 15 of the FCC`s Rules. Operation is subject to the following two Conditions:
1. This device may not cause harmful interference, and
2. This device must accept ant interference received, including interference that may cause undesirable operation.
To satisfy FCC exterior labeling requirements
requirements, the following text must be placed on the exterior of the end product
product.
Contains Transmitter module FCC ID: YZP-TWFMB001T
The antenna must be installed such that 20 cm is maintained between the antenna and users, and the transmitter
module may not be co-located with any other transmitter or antenna. End users cannot modify this transmitter
device. Any Unauthorized modification could void the user‘s authority to operate this device.
©2010 LGIT. All rights reserved.
DOCUMENT No :
REG. DATE : 2010.11.16
SPECIFICATION
REV. DATE : 2010.11.16
MODEL NAME : TWFM-B001T
HC40645
REV.NO : 1.0
PAGE : 4 / 16
8. Electrical Specifications
1) DC Characteristics
Current Consumption
Min.
Typ.
Max.
TX Mode ( MCS7)
470
Idle and Associated state
210
Radio disabled state
60
Unit
mA
2) RF Characteristics for IEEE802.11b ( 11Mbps mode unless otherwise specified)
Items
Contents
Specification
IEEE802.11b
Mode
DSSS/CCK
Channel frequency
2400 ~ 2483 MHz
Data rate
1,2,5.5,11Mbps
TX Characteristics
Min.
Typ.
Max.
Unit
13
15
17
dBm
1st side lobes
-38
-30
dBr
2nd side lobes
-54
-50
dBr
Modulation Accuracy (EVM)
35
Power On/Off ramp
2.0
Usec
30-1000MHz
-36
dBm
1000-12750MHz
-30
dBm
Min.
Typ.
Max.
Unit
-88
-78
dBm
dBm
Power Level
Spectrum Mask
Spurious Emissions (BW=100kHz)
RX Characteristics
Minimum Input Level Sens. (FER ≤ 8%)
Maximum Input Level (FER ≤ 8%)
* Normal Condition : 25℃, VDD=5V.
©2010 LGIT. All rights reserved.
-10
DOCUMENT No :
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SPECIFICATION
REV. DATE : 2010.11.16
MODEL NAME : TWFM-B001T
HC40645
REV.NO : 1.0
PAGE : 5 / 16
3) RF Characteristics for IEEE802.11g ( 54Mbps mode unless otherwise specified)
Items
Contents
Specification
IEEE802.11g
Mode
OFDM
Channel frequency
2400 ~ 2483 MHz
Data rate
6,9,12,18,24,36,48,54Mbps
TX Characteristics
Min.
Typ.
Max.
Unit
13
15
17
dBm
att fc
f +/-11MHz
/ 11MH
-32
32
-21
21
dB
dBr
at fc +/-20MHz
-35
-29
dBr
at fc ≥ +/- 30MHz
-45
-41
dBr
Constellation Error (EVM)
-28
-25
dB
30-1000MHz
-36
dBm
1000-12750MHz
-30
dBm
RX Characteristics
Min.
Typ.
Max.
Unit
Minimum Input Level Sens. (PER ≤ 10%)
-73
-65
dBm
-20
dBm
Power Level
Spectrum Mask
Spurious Emissions (BW=100kHz)
Maximum Input Level (PER ≤ 10%)
* Normal Condition : 25℃, VDD=5V.
©2010 LGIT. All rights reserved.
DOCUMENT No :
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SPECIFICATION
REV. DATE : 2010.11.16
MODEL NAME : TWFM-B001T
HC40645
REV.NO : 1.0
PAGE : 6 / 16
4) RF Characteristics for IEEE802.11a ( 54Mbps mode unless otherwise specified)
Items
Contents
Specification
IEEE802.11a
Mode
OFDM
Channel frequency
5150~5250MHz, 5725 ~ 5850 MHz
Data rate
6,9,12,18,24,36,48,54Mbps
TX Characteristics
Min.
Typ.
Max.
Unit
11
13
15
dBm
at fc +/-11MHz
-32
-21
dBr
at fc +/-20MHz
-35
-29
dBr
at fc ≥ +/- 30MHz
-45
-41
dBr
Constellation Error (EVM)
-28
-25
dB
30-1000MHz
-36
dBm
1000-12750MHz
-30
dBm
RX Characteristics
Min.
Typ.
Max.
Unit
Minimum Input Level Sens. (PER ≤ 10%)
-73
-65
dBm
-20
dBm
Power Level
Spectrum Mask
Spurious Emissions (BW=100kHz)
Maximum Input Level (PER ≤ 10%)
* Normal Condition : 25℃, VDD=5V.
©2010 LGIT. All rights reserved.
DOCUMENT No :
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SPECIFICATION
REV. DATE : 2010.11.16
MODEL NAME : TWFM-B001T
HC40645
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PAGE : 7 / 16
5) RF Characteristics for IEEE802.11an
( MCS7 mode unless otherwise specified)
Items
Contents
Specification
IEEE802.11n – 5GHz
Mode
OFDM
Channel frequency
5150~5250MHz, 5725 ~ 5850 MHz
Data rate
6.5,13,19.5,26,39,52,58.5,65Mbps
TX Characteristics
Min
Min.
Typ
Typ.
Max
Max.
Unit
11
13
15
dBm
at fc +/-11MHz
-32
-21
dBr
at fc +/-20MHz
-35
-29
dBr
at fc ≥ +/- 30MHz
-45
-41
dBr
Constellation Error (EVM)
-29
-28
dB
30-1000MHz
-36
dBm
1000-12750MHz
-30
dBm
Min.
Typ.
Max.
Unit
Minimum Input Level Sens.
(HT20,PER ≤ 10%)
-70
-64
dBm
Minimum Input Level Sens.
(HT40,PER ≤ 10%)
-66
-62
dBm
-20
dBm
Power Level (HT20 / HT40 : MCS7)
Spectrum Mask
Spurious Emissions (BW=100kHz)
RX Characteristics
Maximum Input Level (PER
≤ 10%)
%)
* Normal Condition : 25℃, VDD=5V.
©2010 LGIT. All rights reserved.
DOCUMENT No :
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SPECIFICATION
REV. DATE : 2010.11.16
MODEL NAME : TWFM-B001T
HC40645
REV.NO : 1.0
PAGE : 8 / 16
6) RF Characteristics for IEEE802.11gn
( MCS7 mode unless otherwise specified)
Items
Contents
Specification
IEEE802.11n – 2.4GHz
Mode
OFDM
Channel frequency
2400 ~ 2483 MHz
Data rate
6.5,13,19.5,26,39,52,58.5,65Mbps
, ,
, , , ,
TX Characteristics
Min.
Typ.
Max.
Unit
13
15
17
dBm
at fc +/
+/-11MHz
11MHz
-32
32
-21
21
dBr
at fc +/-20MHz
-35
-29
dBr
at fc ≥ +/- 30MHz
-45
dBr
Constellation Error (EVM)
-29
-28
dB
30-1000MHz
-36
dBm
1000-12750MHz
-30
dBm
Min.
Typ.
Max.
Unit
Minimum Input Level Sens.
(HT20,PER ≤ 10%)
-68
-64
dBm
Minimum Input Level Sens.
(HT40,PER ≤ 10%)
-66
-62
dBm
-20
20
dB
dBm
Power Level (HT20/HT40 : MCS7)
Spectrum Mask
S i
Spurious
Emissions
i i
(BW
(BW=100kHz)
100kH )
RX Characteristics
M i
Maximum
IInputt Level
l (PER ≤ 10%)
* Normal Condition : 25℃, VDD=5V.
©2010 LGIT. All rights reserved.
DOCUMENT No :
REG. DATE : 2010.11.16
SPECIFICATION
REV. DATE : 2010.11.16
MODEL NAME : TWFM-B001T
HC40645
REV.NO : 1.0
PAGE : 9 / 16
9. Environment Tests
Item
Test Conditions
Specifications
Initial values are measured at standard test condition.
Heat Load
Test
Leave samples in 60℃±2℃ for 96 ±5 hours, and in
standard test condition for 30 minutes, then take
measurements within 1 hour.
- Supply voltage : standard ± 5%
- Supply voltage cycle : 1.5h on, 0.5h off
Initial values are measured at standard test condition.
Humidity
Load Test
Leave samples in 40℃±5℃, 90 ~ 95% RH for 96 ±5
hours, and in standard test condition for 30 minutes,
then take measurements within 1 hour.
- Supply voltage : standard + 5%
- Supply voltage cycle : 1
1.5h
5h on
on, 0
0.5h
5h off
High
Temperature
Test
Initial values are measured at standard test condition.
Leave samples in 80℃ ±2℃ for 96 ±5 hours, and
in standard ambient for 1 hour with standard power
Supply then take measurements within 1 hour.
Initial values are measured at standard test condition.
Cold Test
Leave samples in －40℃ ±2℃ for 96 ±5 hours, and
in standard ambient for 1 hour with standard power
Supply then take measurements within 1 hour
hour.
Take measurements in standard test condition.
Temperature
Shock
•TX Power
: ±4dB Max
Temp. : -40℃ ~ +85℃
Duration : 30 min
Ramp-up & Ramp-down for 5 min
Cycle : 200cycle.
©2010 LGIT. All rights reserved.
• Min Input
Level
: ±4dB M
Max
DOCUMENT No :
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SPECIFICATION
REV. DATE : 2010.11.16
MODEL NAME : TWFM-B001T
HC40645
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PAGE : 10 / 16
10. Pin Description
Pin No.
Pin Name
I/O
Pin Description
Wake-up
Wake up
Control signal for wake
wake-up
up
GND
GND
USB_DP
I/O
USB Communication signal USB_DP
USB_DN
I/O
USB Communication signal USB_DN
VDD
VDD 5V
< TOP View >
①
⑤
TWFM-B001T 1009A2901
001EB2B00339
15351616
Note.
. Recommend a Module install sequence for prevent USB device failure
1) Supply 5V power
2) Connect to data signal (USB_DP, USB_DN)
. If remove the module, proceed in reveres sequence
©2010 LGIT. All rights reserved.
DOCUMENT No :
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SPECIFICATION
REV. DATE : 2010.11.16
MODEL NAME : TWFM-B001T
HC40645
REV.NO : 1.0
PAGE : 11 / 16
11. S/W
The module is controlled by wl command. It is intended for those evaluating
and/or testing Broadcom’s IC, describes a subset of the commands available in wl,
the Broadcom ® WLAN client utility.
1) Command Syntax
The syntax is as follows:
wl  [-h] [-d|u|x]  [arguments]
where
-h
this message and command descriptions
-d
output format signed integer
-u
output format unsigned integer
-x
output format hexdecimal
The [h,u] option is only to print help.
Other syntax specifics are as follows:
• Entries within square brackets, such as [arguments], are optional. In the above example,
switches within brackets, such as –h, are typed as shown. The |symbol should not be
typed,
it represents the word or.
• Entries within angle brackets, such as , are required and indicate that a value
must
be inserted in place of the item contained within the angle brackets.
• Entries shown outside of either square or angle brackets are to be typed as shown
shown.
2) Command List and Version
• CMDS
Syntax:
wl cmds
Purpose:
Generates a list of available commands.
Parameters:None
Returns:
All commands available to the attached 43XX chip.
• VER
Syntax:
wl ver
Purpose: Generates a list of available commands.
Parameters:None
Returns:
All commands available to the attached 43XX chip.
• Please refer to ‘80211-TI201-R’ technical document of Broadcom to other
commands.
©2010 LGIT. All rights reserved.
LT
Preliminary Data Sheet
BCM43236
GE N ER A L DE S CR I P TI O N
F E A T U RE S
The BCM43236 is a dual-band (2.4 GHz and 5 GHz)
IEEE 802.11n-compliant MAC/PHY/Radio complete
system-on-a-chip with 2.4 GHz and 5 GHz internal
PAs. The device enables the development of USB
2.0- or HSIC-based IEEE 802.11n WLAN client and
router subsystem solutions. The BCM43236 is
targeted for all WLAN markets that can take
advantage of the high throughput and extended
range of the Broadcom second-generation MIMO
solution. With MIMO, information is sent and
received over two or more antennas simultaneously
using the same frequency band thus providing
greater range and increasing throughput, while
maintaining compatibility with legacy IEEE 802.11a/
b/g devices. This is accomplished through a
combination of enhanced MAC and PHY
implementations including spatial multiplexing
modes in the transmitter and receiver and advanced
digital signal processing techniques to improve
receive sensitivity.
•
•
•
•
•
•
•
LG
•
OT
EK
•
IEEE 802.11n-compliant
2.4 GHz and 5 GHz internal PA
Two-stream spatial multiplexing up to 300 Mbps
Uses on-chip OTP (One-Time Programmable)
memory instead of SROM for substantial RBOM
savings.
Supports MCS 0–15 and MCS 32 modulation and
coding rates.
Supports 20 MHz and 40 MHz channels with optional
SGI.
Support for STBC in both TX and RX
Greenfield, mixed mode, and legacy modes
supported
Full IEEE 802.11a/b/g legacy compatibility with
enhanced performance.
Supports one USB 2.0 host port or one 480 MHz HSIC
port.
UART and JTAG interface, up to eight GPIOs.
Supports up to 32 MB of serial Flash™ memory.
ARM® Cortex-M3™ CPU core plus 256 KB ROM and
448 KB RAM.
Supports Broadcom’s OneDriver™ software.
Supports WHQL certified drivers for Windows® Vista
32- and 64-bit, Windows® XP, and Windows 2000
operating systems for client applications.
Supports Linux® and VxWorks® for access point and
router applications.
Comprehensive wireless network security support
that includes WPA, WPA2, and AES encryption/
decryption coupled with TKIP and IEEE 802.1X
support.
BCM43236 package: 10 mm x 10 mm 88-pin QFN
IN
•
CO
2.4 GHz/5 GHz IEEE802.11n MAC/PHY/Radio Chip
FO
The BCM43236 architecture with its fully integrated
dual-band radio transceiver supports
2 × 2 antennas for Layer 2 throughput of over
200 Mbps.
•
•
•
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State-of-the-art security is provided by industry
standardized system support for WPA™, WPA2™
(IEEE 802.11i), and hardware-accelerated AES
encryption/decryption, coupled with TKIP and IEEE
802.1X support. Embedded hardware acceleration
enables increased system performance and
significant reduction in host-CPU utilization in both
client and access point configurations. The
BCM43236 also supports Broadcom’s widely
accepted and deployed WPS for ease-of-use
wireless secured networks.
•
•
•
•
•
A P P L IC A TI O NS
• USB 2.0 dongles
• HSIC media modules
43236-DS04-R
5300 California Avenue • Irvine, CA 92617 • Phone: 949-926-5000 • Fax: 949-926-5203
12/20/2010 CTJ5M
December 17, 2010
Revision History
LT
BCM43236 Preliminary Data Sheet
BCM43236
RF
Front
End
2×2
Radio
(Switches)
Security
5-Ghz PA
OTP (2 Kbits)
GPIO
IEEE
802.11n
PHY
Serial Flash
Interface
LED
Flash Memory
OT
EK
USB 2.0 Device
or HSIC
Internal Bus
802.11n MAC
CO
2.4-Ghz PA
JTAG
CO
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LG
IN
Figure 1: BCM43236 Block Diagram
BROADCOM
December 17, 2010 • 43236-DS04-R
2.4 GHz/5 GHz 802.11n MAC/PHY/Radio Chip
Page 2
®
12/20/2010 CTJ5M
Revision History
LT
BCM43236 Preliminary Data Sheet
Revision History
Date
Change Description
43236-DS04-R
12/17/10
Updated:
• Table 7: “Current Consumption from 3.3V Supply,” on page 28
• Table 8: “Current Consumption from 1.2V Supply,” on page 28
• Figure 11: “BCM43236 Mechanical Drawing,” on page 39
43236-DS03-R
07/19/10
Updated:
• Section 3: “Pin Assignments,” on page 20.
• Table 3: “Signal Descriptions,” on page 22.
• Table 5: “Absolute Maximum Ratings,” on page 27.
• Section 8: “Thermal Information,” on page 38.
• Section 10: “Ordering Information,” on page 40.
Added:
• “HSIC Characteristics” on page 29.
43236-DS02-R
07/05/10
Updated:
• Figure 8: “BCM43236 88-Pin QFN Package,” on page 19.
• Table 2: “Pin Assignments,” on page 20.
• Table 3: “Signal Descriptions,” on page 21.
43236-DS01-R
04/30/10
Updated:
• Table 2: “Pin Assignments,” on page 19.
• Figure 7: “BCM43236 88-Pin QFN Package,” on page 18.
• Table 3: “Signal Descriptions,” on page 20.
• Table 4: “Strapping Options,” on page 24.
• Table 5: “Absolute Maximum Ratings,” on page 25.
• Table 6: “Recommended Operating Conditions and DC Characteristics,”
on page 26.
• Table 10: “2.4 GHz Band Receiver RF Specifications,” on page 27.
• Table 11: “2.4 GHz Band Transmitter RF Specifications,” on page 29.
• Table 13: “5 GHz Band Receiver RF Specifications,” on page 30.
• Table 14: “5 GHz Band Transmitter RF Specifications,” on page 31.
• Table 19: “88-Pin QFN Thermal Characteristics,” on page 35.
• Table 20: “Ordering Information,” on page 37.
Added:
• Table 7: “Current Consumption from 3.3V Supply,” on page 26.
• Table 8: “Current Consumption from 1.2V Supply,” on page 26.
CO
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FO
LG
IN
OT
EK
CO
Revision
43236-DS00-R
10/20/09
Initial release
BROADCOM
December 17, 2010 • 43236-DS04-R
2.4 GHz/5 GHz 802.11n MAC/PHY/Radio Chip
Page 3
®
12/20/2010 CTJ5M
LT
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LG
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Broadcom Corporation
5300 California Avenue
Irvine, CA 92617
© 2010 by Broadcom Corporation
All rights reserved
Printed in the U.S.A.
Broadcom®, the pulse logo, Connecting everything®, and the Connecting everything logo are among the
trademarks of Broadcom Corporation and/or its affiliates in the United States, certain other countries and/
or the EU. Any other trademarks or trade names mentioned are the property of their respective owners.
Any recommendations or changes to this document can be submitted to MCBUMktg@broadcom.com.
This data sheet (including, without limitation, the Broadcom component(s) identified herein) is not designed,
intended, or certified for use in any military, nuclear, medical, mass transportation, aviation, navigations,
pollution control, hazardous substances management, or other high risk application. BROADCOM PROVIDES
THIS DATA SHEET "AS-IS", WITHOUT WARRANTY OF ANY KIND. BROADCOM DISCLAIMS ALL WARRANTIES,
EXPRESSED AND IMPLIED, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT.
12/20/2010 CTJ5M
Table of Contents
LT
BCM43236 Preliminary Data Sheet
Table of Contents
CO
Section 1: Introduction...................................................................................................... 9
Section 2: Functional Description .................................................................................... 11
Global Functions...........................................................................................................................................11
OT
EK
Power Management ..............................................................................................................................11
Voltage Regulators.................................................................................................................................11
Reset ......................................................................................................................................................11
GPIO Interface........................................................................................................................................11
Bluetooth Coexistence Interface ...........................................................................................................12
OTP.........................................................................................................................................................12
IN
JTAG Interface........................................................................................................................................12
UART Interface.......................................................................................................................................12
Serial Flash™ Interface...........................................................................................................................12
USB/HSIC Interface ................................................................................................................................13
LG
Crystal Oscillator ....................................................................................................................................14
IEEE 802.11n MAC Description.....................................................................................................................15
IEEE 802.11n PHY Description ......................................................................................................................17
Dual-Band Radio Transceiver .......................................................................................................................19
FO
Receiver Path .........................................................................................................................................19
Transmitter Path ....................................................................................................................................19
Calibration..............................................................................................................................................19
Section 3: Pin Assignments.............................................................................................. 20
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BCM43236 88-Pin QFN Assignments ...........................................................................................................20
Signals by Pin Number ...........................................................................................................................21
Section 4: Signal and Pin Descriptions ............................................................................. 22
Package Signal Descriptions.........................................................................................................................22
Strapping Options.........................................................................................................................................26
Section 5: Electrical Characteristics.................................................................................. 27
Absolute Maximum Ratings .........................................................................................................................27
Recommended Operating Conditions and DC Characteristics....................................................................28
Current Consumption from the 3.3V Supply ...............................................................................................28
Current Consumption from the 1.2V Supply ...............................................................................................28
BROADCOM
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Table of Contents
LT
BCM43236 Preliminary Data Sheet
HSIC Characteristics......................................................................................................................................29
Section 6: RF Specifications ............................................................................................. 30
CO
2.4 GHz Band General RF Specifications ......................................................................................................30
2.4 GHz Band Receiver RF Specifications .....................................................................................................31
2.4 GHz Band Transmitter RF Specifications................................................................................................32
2.4 GHz Band Local Oscillator Specifications ...............................................................................................32
OT
EK
5 GHz Band Receiver RF Specifications ........................................................................................................33
5 GHz Band Transmitter RF Specifications...................................................................................................34
5 GHz Band Local Oscillator Frequency Generator Specifications ..............................................................34
On-Chip Regulator Power Supply Characteristics .......................................................................................35
Section 7: Timing Characteristics ..................................................................................... 36
IN
Reset and Clock Timing Diagram..................................................................................................................36
Serial Flash Timing Diagram .........................................................................................................................37
Section 8: Thermal Information....................................................................................... 38
Junction Temperature Estimation and PSIJT Versus ThetaJC .......................................................................38
LG
Section 9: Package Information ....................................................................................... 39
CO
NF
ID
EN
TI
AL
FO
Section 10: Ordering Information .................................................................................... 40
BROADCOM
December 17, 2010 • 43236-DS04-R
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List of Figures
LT
BCM43236 Preliminary Data Sheet
List of Figures
CO
Figure 1: BCM43236 Block Diagram ...................................................................................................................2
Figure 2: MIMO System Diagram Showing 2 × 2 Antenna Configuration ..........................................................9
Figure 3: Functional Block Diagram..................................................................................................................10
Figure 4: USB 2.0 Device/HSIC Core Block Diagram .........................................................................................13
OT
EK
Figure 5: Recommended Oscillator Configuration ...........................................................................................15
Figure 6: Enhanced MAC Block Diagram ..........................................................................................................16
Figure 7: PHY Block Diagram ............................................................................................................................18
Figure 8: BCM43236 88-Pin QFN Package........................................................................................................20
Figure 9: Timing for the Optional External Power-On Reset ............................................................................36
IN
Figure 10: Serial Flash Timing Diagram (STMicroelectronics-Compatible).......................................................37
CO
NF
ID
EN
TI
AL
FO
LG
Figure 11: BCM43236 Mechanical Drawing .....................................................................................................39
BROADCOM
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List of Tables
LT
BCM43236 Preliminary Data Sheet
List of Tables
CO
Table 1: Crystal Oscillator Requirements .........................................................................................................14
Table 2: Pin Assignments..................................................................................................................................21
Table 3: Signal Descriptions..............................................................................................................................22
Table 4: Strapping Options ...............................................................................................................................26
OT
EK
Table 5: Absolute Maximum Ratings................................................................................................................27
Table 6: Recommended Operating Conditions and DC Characteristics ...........................................................28
Table 7: Current Consumption from 3.3V Supply.............................................................................................28
Table 8: Current Consumption from 1.2V Supply.............................................................................................28
Table 9: HSIC Characteristics ............................................................................................................................29
IN
Table 10: 2.4 GHz Band General RF Specifications...........................................................................................30
Table 11: 2.4 GHz Band Receiver RF Specifications..........................................................................................31
Table 12: 2.4 GHz Band Transmitter RF Specifications.....................................................................................32
Table 13: 2.4 GHz Band Local Oscillator Specifications ....................................................................................32
Table 14: 5 GHz Band Receiver RF Specifications.............................................................................................33
LG
Table 15: 5 GHz Band Transmitter RF Specifications........................................................................................34
Table 16: 5 GHz Band Local Oscillator Frequency Generator Specifications....................................................34
Table 17: On-Chip Regulator Power Supply Characteristics.............................................................................35
FO
Table 18: Ext_por and Clock Timing .................................................................................................................36
Table 19: Serial Flash Timing ............................................................................................................................37
Table 20: 88-Pin QFN Thermal Characteristics .................................................................................................38
CO
NF
ID
EN
TI
AL
Table 21: Ordering Information .......................................................................................................................40
BROADCOM
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Introduction
LT
BCM43236 Preliminary Data Sheet
CO
Section 1: Introduction
BCM43236
IEEE
802.11n
MAC/PHY
BCM43236
IEEE 802.11n
2.4-/5-GHz
Radio
Transceiver
with
Integrated
PAs
RF
Switches
RF
Switches
IEEE 802.11n
2.4-/5-GHz
Radio
Transceiver
with
Integrated
PAs
IEEE
802.11n
MAC/PHY
Host
I/F
IN
Host
I/F
OT
EK
The BCM43236 is the latest innovative chip from Broadcom® based on IEEE 802.11n. The chip is designed to
take current WLAN systems to the next level of higher performance and greater range with Multiple Input
Multiple Output (MIMO) technology as shown in Figure 2. The IEEE 802.11n standard more than doubles the
spectral efficiency compared to that of current IEEE 802.11a/g WLANs.
Figure 2: MIMO System Diagram Showing 2 × 2 Antenna Configuration
LG
Employing a native 32-bit bus with Direct Memory Access (DMA) architecture, the BCM43236 offers significant
performance improvements in transfer rates, CPU utilization, and flexible support for USB 2.0 devices.
CO
NF
ID
EN
TI
AL
FO
Figure 3 on page 10 shows a block diagram of the device.
BROADCOM
December 17, 2010 • 43236-DS04-R
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USB20_DEV_DPLS
USB20_DEV_DMNS
HSIC Data
HSIC Strobe
RAM
ROM
(448 KB) (256 KB)
IEEE
802.11n
PHY
IEEE 802.11n
MAC
USB 2.0
Device
or HSIC
Security
LT
2.4/5 GHz
Radio
IN
Internal Bus System
ARMCortexM3
JTAG
Interface
antenna switch controls (10)
ext_lna_2g controls (4)
ext_lna_5g controls (4)
pa_2g controls (2)
pa_5g controls (2)
GPIO[0:7]
UART_TX
GPIO
FO
UART_RX
tssiln_0
tssiln_1
lna_p_a_0
lna_p_a_1
lna_p_g_0
lna_p_g_0
pa_p_a_0
pa_p_a_1
pa_p_g_0
pa_p_g_1
LG
RF
Control
UART
TCLK
TDI
TDO
TMS
TRST#
CO
PLL
20 MHz
Ref.
Clock
OT
EK
SFLASH Interface
xtal_in
sflash_d
extif_flash_cs_l
sflash_c
sflash_q
BCM43236
xtal_out
Introduction
xtal_buf_out
BCM43236 Preliminary Data Sheet
CO
NF
ID
EN
TI
AL
Figure 3: Functional Block Diagram
BROADCOM
December 17, 2010 • 43236-DS04-R
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®
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Functional Description
CO
Section 2: Functional Description
LT
BCM43236 Preliminary Data Sheet
OT
EK
Global Functions
Power Management
The BCM43236 has been designed with the stringent power consumption requirements of battery-powered
hosts in mind. All areas of the chip design were scrutinized to help reduce power consumption. Silicon
processes and cell libraries were chosen to reduce leakage current and supply voltages.
LG
IN
Additionally, the BCM43236 includes an advanced Power Management Unit (PMU). The PMU provides
significant power savings by putting the BCM43236 into various power management states appropriate to the
current environment and activities that are being performed. The power management unit enables and
disables internal regulators, switches, and other blocks based on a computation of the required resources and
a table that describes the relationship between resources and the time needed to enable and disable them.
Power-up sequences are fully programmable. Configurable, free-running counters in the PMU are used to turn
on/off individual regulators and power switches. Clock speeds are dynamically changed (or gated altogether)
for the current mode. Slower clock speeds are used wherever possible.
Voltage Regulators
FO
Three Low-Dropout (LDO) regulators and a PMU are integrated into the BCM43236. All regulators are
programmable via the PMU.
Reset
CO
NF
ID
EN
TI
AL
Resets are generated internally by the BCM43236. An optional external power-on reset circuit can be
connected to the active-low Ext_por input pin. A 50 ms low pulse is recommended to guarantee that a
sufficiently long reset is applied to all internal circuits, including integrated PHYs. The initialization process loads
all pin-configurable modes, resets all internal processes, and puts the device in the idle state. During
initialization, the clock source input signal must be active, and the 3.3V power supply to the device must be
stable. The external power-on reset overrides the BCM43236 internal reset.
GPIO Interface
There are eight General-Purpose I/O (GPIO) pins provided on the BCM43236. They are multiplexed with the
control signals. These pins can be used to attach to various external devices. Upon power-up and reset, these
pins become tristated. Subsequently, they can be programmed to be either input or output pins via the GPIO
control register. A programmable internal pull-up/pull-down resistor is included on each GPIO. If a GPIO output
enable is not asserted, and the corresponding GPIO signal is not being driven externally, the GPIO state is
determined by its programmable resistor.
BROADCOM
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Global Functions
LT
BCM43236 Preliminary Data Sheet
Bluetooth Coexistence Interface
Note: These five pins are muxed with the JTAG interface.
IN
OTP
OT
EK
CO
A 5-wire handshake interface is provided to enable signalling between the device and an external Bluetooth
device host to manage sharing of the wireless medium for optimum performance. The signals provided are:
• btcx_tx_conf
• btcx_rf_active
• btcx_status
• btcx_prisel
• btcx_freq
LG
The BCM43236 contains an on-chip One-Time-Programmable (OTP) area that can be used for nonvolatile
storage of WLAN information such as a MAC address and other hardware-specific parameters. The total area
available for programming is 2 Kbits.
JTAG Interface
UART Interface
FO
The BCM43236 supports the IEEE 1149.1 JTAG boundary-scan standard for testing the device packaging and
PCB manufacturing.
CO
NF
ID
EN
TI
AL
One UART interface is provided that can be attached to RS-232 Data Termination Equipment (DTE) for
exchanging and managing data with other serial devices. The UART interface is primarily used for debugging
and development.
Serial Flash™ Interface
Serial Flash™ is available regardless of whether USB 2.0 operation is enabled or disabled. The Flash interface is
an STMicroelectronics®-compatible 4-pin interface.
BROADCOM
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Global Functions
LT
BCM43236 Preliminary Data Sheet
USB/HSIC Interface
OT
EK
CO
The BCM43236 USB/HSIC interface can be set to operate as a USB 2.0 port or a High-Speed Inter-Chip (HSIC)
port. Features of the interface are:
• USB 2.0 protocol engine:
– Parallel Interface Engine (PIE) between packet buffers and USB transceiver
– Supports up to nine endpoints, including Configurable Control Endpoint 0
• Separate endpoint packet buffers with a 512-byte FIFO buffer each
• Host-to-device communication for bulk, control, and interrupt transfers
• Configuration/status registers
• The HSIC port can communicate with an external HSIC host, such as the BCM5357 and BCM5358.
IN
The various blocks in the USB 2.0 device/HSIC core are shown in Figure 4.
32-bit On-Chip Communication System
USB 2.0 Device
or HSIC
LG
DMA Engines
TX
TX
TX
TX
TX
FIFOs
FIFO
FIFO
FIFO
FIFO
FO
RX
FIFO
Endpoint Management Unit
USB 2.0
Protocol Engine
CO
NF
ID
EN
TI
AL
HSIC PHY
Data
USB 2.0 PHY
Strobe
D+
D-
Figure 4: USB 2.0 Device/HSIC Core Block Diagram
The USB 2.0 PHY handles the USB protocol and the serial signaling interface between the host and device. It is
primarily responsible for data transmission and recovery. On the transmit side, data is encoded, along with a
clock, using the NRZI scheme with bit stuffing to ensure that the receiver detects a transition in the data
stream. A SYNC field that precedes each packet enables the receiver to synchronize the data and clock recovery
circuits. On the receive side, the serial data is deserialized, unstuffed, and checked for errors. The recovered
data and clock are then shifted to the clock domain that is compatible with the internal bus logic.
BROADCOM
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Global Functions
LT
BCM43236 Preliminary Data Sheet
CO
The endpoint management unit contains the PIE control logic and the endpoint logic. The PIE interfaces
between the packet buffers and the USB transceiver. It handles packet identification (PID), USB packets, and
transactions.
OT
EK
The endpoint logic contains nine uniquely-addressable endpoints. These endpoints are the source or sink of
communication flow between the host and the device. Endpoint zero is used as a default control port for both
the input and output directions. The USB system software uses this default control method to initialize and
configure the device information, and allows USB status and control access. Endpoint zero is always accessible
after a device is attached, powered, and reset.
Endpoints are supported by 512-byte FIFO buffers, one for each IN endpoint and one shared by all OUT
endpoints. Both TX and RX data transfers support a DMA burst of 4, which guarantees low latency and
maximum throughput performance. The RX FIFO can never overflow by design. The maximum USB packet size
cannot be more than 512 bytes.
Crystal Oscillator
LG
Table 1 lists the requirements for the crystal oscillator.
IN
Finally, the BCM43236 is either configured as a USB 2.0 device or as a PHY-less HSIC by selecting the
appropriate strapping option. See Table 4 on page 26 for information on how to select the strapping options.
Table 1: Crystal Oscillator Requirements
Value
Frequency
Mode
Load capacitance
ESR
Frequency stability
20 MHz
AT cut, fundamental
16 pF
50Ω maximum
±10 ppm at 25°C
±10 ppm at 0°C to +85°C
±3 ppm/year max first year, ±1 ppm thereafter
300 µW maximum
40,000 minimum
< 5 pF
FO
Parameter
CO
NF
ID
EN
TI
AL
Aging
Drive level
Q-factor
Shunt capacitance
BROADCOM
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Page 14
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IEEE 802.11n MAC Description
LT
BCM43236 Preliminary Data Sheet
OCS IN
27 pF
1M
CO
Figure 5 shows the recommended oscillator configuration.
221
NOTE: See Reference Schematics
OT
EK
OCS OUT
27 pF
IEEE 802.11n MAC Description
IN
Figure 5: Recommended Oscillator Configuration
CO
NF
ID
EN
TI
AL
FO
LG
The IEEE 802.11n MAC features include:
• Enhanced MAC for supporting IEEE 802.11n features
• Programmable Access Point (AP) or Station (STA) functionality
• Programmable Independent Basic Service Set (IBSS) or infrastructure mode
• Aggregated MPDU (MAC Protocol Data Unit) support for High-throughput (HT)
• Passive scanning
• Network Allocation Vector (NAV), Interframe Space (IFS), and Timing Synchronization Function (TSF)
functionality
• RTS/CTS procedure
• Transmission of response frames (ACK/CTS)
• Address filtering of receive frames as specified by IBSS rules
• Multirate support
• Programmable Target Beacon Transmission Time (TBTT), beacon transmission/cancellation and
programmable Announcement Traffic Indication Message (ATIM) window
• CF conformance: Setting NAV for neighborhood Point Coordination Function (PCF) operation
• Security through a variety of encryption schemes including WEP, TKIP, AES, WPA™, WAP2™, and
IEEE 802.1X
• Power management
• Statistics counters for MIB support
The MAC core supports the transmission and reception of sequences of packets, together with related timing,
without any packet-by-packet driver interaction. Time-critical tasks requiring response times of only a few
milliseconds are handled in the MAC core. This achieves the required timing on the medium while keeping the
host driver easier to write and maintain. Also, incoming packets are buffered in the MAC core, which allows the
MAC driver to process them in bursts, enabling high bandwidth performance.
BROADCOM
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IEEE 802.11n MAC Description
LT
BCM43236 Preliminary Data Sheet
CO
The MAC driver interacts with the MAC core to prepare queues of packets to transmit and to analyze and
forward received packets to upper software layers. The internal blocks of the MAC core are connected to a
Programmable State Machine (PSM) through the host interface that connects to the internal bus (see
Figure 6).
Host Interface
Six TX FIFOs
Template
TX Status FIFO
Power
Management
RX FIFO
Wireless Security Engine
OT
EK
(Host Registers)
Code Memory
Programmable
State Machine
(PSM)
Timing and
Control
TX Engine
RX Engine
IN
Data Memory
PHY Interface
Figure 6: Enhanced MAC Block Diagram
FO
LG
The host interface consists of registers for controlling and monitoring the status of the MAC core and
interfacing with the TX/RX FIFOs. For transmit, a total of 128 KB FIFO buffering is available that can be
dynamically allocated to six transmit queues plus template space for beacons, ACKs, and probe responses.
Whenever the host has a frame to transmit, the host queues the frame into one of the transmit FIFOs with a
TX descriptor containing TX control information. The PSM schedules the transmission on the medium
depending on the frame type, transmission rules in IEEE 802.11 protocol, and the current medium occupancy
scenario. After the transmission is completed, a TX status is returned to the host, informing the host of the
result that got transmitted.
The MAC contains a single 10 KB RX FIFO. When a frame is received, it is sent to the host along with an RX
descriptor that contains additional information about the frame reception conditions.
CO
NF
ID
EN
TI
AL
The power management block maintains the information regarding the power management state of the core
(and the associated STAs in case of an AP) to help in dynamic decisions by the core regarding frame
transmission.
The wireless security engine performs the required encryption/decryption on the TX/RX frames. This block
supports separate transmit and receive keys with four shared keys and 50 link-specific keys. The link-specific
keys are used to establish a secure link between any two STAs, with the required key being shared between
only those two STAs, hence excluding all of the other STAs in the same network from deciphering the
communication between those two STAs. The wireless security engine supports the following encryption
schemes that can be selected on a per-destination basis:
• None: The wireless security engine acts as a pass-through
• WEP: 40-bit secure key and 24-bit IV as defined in IEEE Std. 802.11-2007
• WEP128: 104-bit secure key and 24-bit IV
• TKIP: IEEE Std. 802.11-2007
• AES: IEEE Std. 802.11-2007
BROADCOM
December 17, 2010 • 43236-DS04-R
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IEEE 802.11n PHY Description
LT
BCM43236 Preliminary Data Sheet
CO
The transmit engine is responsible for the byte flow from the TX FIFO to the PHY interface through the
encryption engine and the addition of an FCS (CRC-32) as required by IEEE 802.11-2007. Similarly, the receive
engine is responsible for byte flow from the PHY interface to the RX FIFO through the decryption engine and
for detection of errors in the RX frame.
The timing block performs the TSF, NAV, and IFS functionality as described in IEEE Std. 802.11-2007.
OT
EK
The Programmable State Machine (PSM) coordinates the operation of different hardware blocks required for
both transmission and reception. The PSM also maintains the statistics counters required for MIB support.
IEEE 802.11n PHY Description
FO
LG
IN
The PHY features include:
• Programmable data rates from MCS 0–15 in 20 MHz and 40 MHz channels, as specified in IEEE 802.11n.
• Support for Short Guard Interval (SGI) and Space-Time Block Coding (STBC)
• All scrambling, encoding, forward error correction, and modulation in the transmit direction, and inverse
operations in the receive direction
• Advanced digital signal processing technology for best-in-class receive sensitivity
• Both mixed-mode and optional greenfield preamble of IEEE 802.11n
• Both long and optional short preambles of IEEE 802.11b
• Resistance to multipath (>250 nanoseconds RMS delay spread) with maximal ratio combining for high
throughput and range performance, including improved performance in legacy mode over existing IEEE
802.11a/b/g solutions.
• Automatic Gain Control (AGC)
• Available per-packet channel quality and signal strength measurements
CO
NF
ID
EN
TI
AL
The dual PHYs integrated in the BCM43236 provide baseband processing at all mandatory data rates specified
in IEEE 802.11n up to 300 Mbps, and the legacy rates specified in IEEE 802.11a/b/g including 1, 2, 5.5, 6, 9, 11,
12, 18, 24, 36, 48, and 54 Mbps. This core acts as an intermediary between the MAC and the dual-band
2.4/5 GHz radio, converting back and forth between packets and baseband waveforms.
BROADCOM
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IEEE 802.11n PHY Description
LT
BCM43236 Preliminary Data Sheet
Descramble and
Deframe
Frame and Scramble
RX FSM
Modulate/Spread
OT
EK
TX FSM
CO
MAC Interface
Rake Receiver and
DPSK Demodulation
PHY Registers
Equalizer and CCK
Demodulation
Timing and Frequency Correction
MIMO
OFDM
DAC
DAC
IN
TX
Filter
TX Filter
Sync/AGC
ADC
ADC
LG
PHY-to-Radio Interface
CO
NF
ID
EN
TI
AL
FO
Figure 7: PHY Block Diagram
BROADCOM
December 17, 2010 • 43236-DS04-R
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Dual-Band Radio Transceiver
LT
BCM43236 Preliminary Data Sheet
Dual-Band Radio Transceiver
CO
Integrated into the BCM43236 is Broadcom's world-class dual-band radio transceiver that ensures low power
consumption and robust communications for low-cost applications operating in the 2.4 GHz and 5 GHz bands.
Channel bandwidths of 20 MHz and 40 MHz are supported as specified in IEEE 802.11n.
OT
EK
Receiver Path
The BCM43236 has a wide dynamic range, direct conversion receiver. It employs high order on-chip channel
filtering to ensure reliable operation in the noisy 2.4 GHz ISM band or the entire 5 GHz U-NII band. The
excellent noise figure of the receiver makes an external LNA unnecessary.
IN
Transmitter Path
LG
Baseband data is modulated and upconverted to the 2.4 GHz ISM band or the 5 GHz U-NII bands, respectively.
Linear on-chip Power Amplifiers are included, which are capable of delivering a nominal output power
exceeding +15 dBm while meeting the IEEE 802.11a and 802.11g specifications. The TX gain has a 78 dB range
with a resolution of 0.25 dB.
Calibration
CO
NF
ID
EN
TI
AL
FO
The BCM43236 features dynamic on-chip calibration, eliminating process variation across components. This
enables the device to be used in high-volume applications because calibration routines are not required during
manufacturing testing. These calibration routines are performed periodically in the course of normal radio
operation.
BROADCOM
December 17, 2010 • 43236-DS04-R
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Page 19
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Pin Assignments
LT
BCM43236 Preliminary Data Sheet
CO
Section 3: Pin Assignments
BCM43236 88-Pin QFN Assignments
OT
EK
This sections contains pin assignments and ballout information for the BCM43236 (88-pin) packages.
IN
LG
FO
VDDIO
sflash_cs_l
sflash_q
sflash_c
sflash_d
mimophy_core0_ant0_tx
mimophy_core0_ant0_rx
VDD
mimophy_core1_ant0_tx
mimophy_core1_ant0_rx
VDDIO
VDD
gpio_7
jtag_trst_l
jtag_tdi
jtag_tck
analog_wlan_iqtest_VDD1p2
jtag_tms
jtag_tdo
analog_wlan_iqtest_qp
analog_wlan_iqtest_qn
analog_wlan_iqtest_in
CO
NF
ID
EN
TI
AL
10
11
12
13
14
15
16
17
18
19
20
21
22
VDD
mimophy_core0_ant1_rx
mimophy_core0_ant1_tx
gpio_6
gpio_5
VDDIO
gpio_4
gpio_3
gpio_2
gpio_1
gpio_0
VDD
VDDIO/OTP_VDD
USB_RREF
HSIC_STRB
HSIC_DATA
USB AVDD 1p2
USB_DMNS
USB_DPLS
USB_AVDD3p3
USB_MONCDR
USBAVDD2p5
88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
analog_wlan_iqtest_ip
Gnd
pa_5g_core1_VDD3p3
PA_5g_core1
tx_5g_core1_VDD1p2
rf_5g_antenna_core1
core1_VDD1p2
rf_2g_antenna_core1
tx_2g_core1_VDD1p2
pa_2g_core1_VDD3p3
PA_2g_core1
pa_5g_core0_VDD3p3
PA_5g_core0
tx_5g_core0_VDD1p2
rf_5g_antenna_core0
core0_VDD1p2
rf_2g_antenna_core0
tx_2g_core0_VDD1p2
pa_2g_core0_VDD3p3
PA_2g_core0
gpiao_GPIO_PAD
rcal_res_ext_core
BCM43236 10 x 10 QFN
VDD
mimophy_core1_ant1_rx
mimophy_core1_ant1_tx
VDDIO
UART_RX
UART_TX
VDD
VDDPLL/RF_AVDD_1p2
USBLDO_2p5_out
LDO_3p3_in
VREF
PAREF
PAREF_CTL1
PAREF_CTL2
Ext_por
xtal_buf_out
i_xtal_VDD2p5/o_xtal_VDD2p5
xtal_in
xtal_out
synth_VDD1p2
synth_vco_VDD1p2
vreg3p3_VDD3p3
23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
Figure 8: BCM43236 88-Pin QFN Package
BROADCOM
December 17, 2010 • 43236-DS04-R
2.4 GHz/5 GHz 802.11n MAC/PHY/Radio Chip
Page 20
®
12/20/2010 CTJ5M
BCM43236 88-Pin QFN Assignments
LT
BCM43236 Preliminary Data Sheet
Signals by Pin Number
Table 2: Pin Assignments
Pin Signal Name
Pin Signal Name
Pin Signal Name
VDDIO
23 analog_wlan_iqtest_ip
46 synth_vco_VDD1p2
68 USB_MONCDR
sflash_cs_l
24 Gnd
47 synth_VDD1p2
69 USB_AVDD3p3
sflash_q
25 pa_5g_core1_VDD3p3
48 xtal_out
70 USB_DPLS
sflash_c
26 PA_5g_core1
49 xtal_in
71 USB_DMNS
sflash_d
27
72 USB AVDD 1p2
mimophy_core0_ant0_tx
28 rf_5g_antenna_core1
50 i_xtal_VDD2p5/
o_xtal_VDD2p5
mimophy_core0_ant0_rx
29 core1_VDD1p2
51 xtal_buf_out
74 HSIC_STRB
VDD
30 rf_2g_antenna_core1
52 Ext_por
75 USB_RREF
mimophy_core1_ant0_tx
31 tx_2g_core1_VDD1p2
53 PAREF_CTL2
76 VDDIO/OTP_VDD
10 mimophy_core1_ant0_rx
32 pa_2g_core1_VDD3p3
54 PAREF_CTL1
77 VDD
11 VDDIO
33 PA_2g_core1
55 PAREF
78 gpio_0
12 VDD
34 pa_5g_core0_VDD3p3
56 VREF
79 gpio_1
13 gpio_7
35 PA_5g_core0
57 LDO_3p3_in
80 gpio_2
14 jtag_trst_l
36 tx_5g_core0_VDD1p2
58 USBLDO_2p5_out
81 gpio_3
15 jtag_tdi
37
59 VDDPLL/RF_AVDD_1p2
82 gpio_4
16 jtag_tck
38 core0_VDD1p2
60 VDD
83 VDDIO
17 analog_wlan_iqtest_VDD
1p2
39 rf_2g_antenna_core0
61 UART_TX
84 gpio_5
40 tx_2g_core0_VDD1p2
62 UART_RX
85 gpio_6
18 jtag_tms
41 pa_2g_core0_VDD3p3
63 VDDIO
86 mimophy_core0_ant1_tx
19 jtag_tdo
42 PA_2g_core0
64 mimophy_core1_ant1_tx
87 mimophy_core0_ant1_rx
20 analog_wlan_iqtest_qp
43 gpiao_GPIO_PAD
65 mimophy_core1_ant1_rx
88 VDD
21 analog_wlan_iqtest_qn
44 rcal_res_ext_core
66 VDD
22 analog_wlan_iqtest_in
45 vreg3p3_VDD3p3
67 USBAVDD2p5
OT
EK
IN
FO
LG
rf_5g_antenna_core0
CO
NF
ID
EN
TI
AL
tx_5g_core1_VDD1p2
BROADCOM
December 17, 2010 • 43236-DS04-R
CO
Pin Signal Name
73 HSIC_DATA
2.4 GHz/5 GHz 802.11n MAC/PHY/Radio Chip
Page 21
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12/20/2010 CTJ5M
Signal and Pin Descriptions
CO
Section 4: Signal and Pin Descriptions
LT
BCM43236 Preliminary Data Sheet
Package Signal Descriptions
Table 3: Signal Descriptions
Signal
OT
EK
The signal name, type, and description of each pin in the BCM43236 88-pin QFN package is listed in Table 3.
The symbols shown under Type indicate pin directions (I/O = bidirectional, I = input, O = output) and the
internal pull-up/pull-down characteristics (PU = weak internal pull-up resistor and PD = weak internal pulldown resistor), if any. See also Table 4 on page 26 for resistor strapping options.
BCM43236
Type
xtal_in
49
xtal_out
xtal_buf_out
48
51
O (8 mA-PU)
I (8mA-PU)
O (8 mA-PD)
O (8 mA)
Serial Flash chip select
Serial Flash data input
Serial Flash clock
Serial Flash data output
USB interface port D–
USB interface port D+
During USB mode, tie this pin in parallel through
a 100 pF capacitor and a 4 kΩ resistor to ground.
During HSIC mode, tie this pin to a 50Ω resistor
to ground.
USB HSIC strobe
USB HSIC data
For test/diagnostic purposes only.
USB Interface
LG
sflash_cs_l
sflash_q
sflash_c
sflash_d
XTAL oscillator input. Connect a 20 MHz, 10 ppm
crystal between the xtal_in and xtal_out pins.
XTAL oscillator output
Buffered XTAL output
FO
Serial Flash Interface
IN
Crystal Oscillator
Description
71
70
75
I/O
I/O
hsic_strb
hsic_data
usb_moncdr
74
73
68
I/O
–
rcal_res_ext_core
44
ext_por
52
analog_wlan_iqtest_qp
20
–
CO
NF
ID
EN
TI
AL
usb_dmns
usb_dpls
usb_rref
Miscellaneous Signals
Reference output, connect to ground via 15k 1%
resistor.
External power-on reset (POR) input. Active low.
Allows an optional external power-on reset
circuit to be connected. If installed, the external
POR will override the internal POR.
IQ test pin
BROADCOM
December 17, 2010 • 43236-DS04-R
2.4 GHz/5 GHz 802.11n MAC/PHY/Radio Chip
Page 22
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12/20/2010 CTJ5M
Package Signal Descriptions
LT
BCM43236 Preliminary Data Sheet
Table 3: Signal Descriptions (Cont.)
BCM43236
Type
Description
analog_wlan_iqtest_qn
analog_wlan_iqtest_in
analog_wlan_iqtest_ip
21
22
23
–
–
–
IQ test pin
IQ test pin
IQ test pin
mimophy_core0_ant0_tx
mimophy_core0_ant0_rx
mimophy_core0_ant1_tx
mimophy_core0_ant1_rx
86
87
mimophy_core1_ant0_tx
mimophy_core1_ant0_rx
10
mimophy_core1_ant1_tx
mimophy_core1_ant1_rx
64
65
Antenna0 TR Switch controls for core 0. These
pins are also used as strapping options, see
Table 4 on page 26.
Antenna1 TR Switch controls for core 0. These
pins are also used as strapping options, see
Table 4 on page 26.
Antenna0 TR Switch controls for core 1. These
pins are also used as strapping options, see
Table 4.
Antenna1 TR Switch controls for core 1. These
pins are also used as strapping options, see
Table 4.
37
28
39
30
35
26
42
33
IN
OT
EK
RF Control Interface
FO
CO
NF
ID
EN
TI
AL
JTAG Interface
LG
RF Signal Interface
rf_5g_antenna_core0
rf_5g_antenna_core1
rf_2g_antenna_core0
rf_2g_antenna_core1
pa_5g_core0
pa_5g_core1
pa_2g_core0
pa_2g_core1
jtag_trst_l
14
I/O
jtag_tck
16
I/O
jtag_tdi
15
I/O
CO
Signal
Chain 0 RF receive input, 5 GHz band
Chain 1 RF receive input, 5 GHz band
Chain 0 RF receive input, 2.4 GHz band
Chain 1 RF receive input, 2.4 GHz band
Chain 0 RF transmit output, 5 GHz band
Chain 1 RF transmit output, 5 GHz band
Chain 0 RF transmit output, 2.4 GHz band
Chain 1 RF transmit output, 2.4 GHz band
JTAG Reset Input. Resets the JTAG Controller. If
not used, this pin should be pulled low by a 1 kΩ
resistor. This pin is muxed with gpio0.
JTAG Test Clock Input. Used to synchronize JTAG
control and data transfers. If not used, this pin
should be pulled low by a 1 kΩ resistor. This pin
is muxed with btcx_rf_active (Bluetooth
coexistence output, RF active).
JTAG Test Data Input. Serial data input to the
JTAG TAP controller. Sampled on the rising edge
of TCK. If not used, it may be left unconnected.
This pin is muxed with btcx_tx_conf (Bluetooth
coexistence output, WLAN transmit).
BROADCOM
December 17, 2010 • 43236-DS04-R
2.4 GHz/5 GHz 802.11n MAC/PHY/Radio Chip
Page 23
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Package Signal Descriptions
LT
BCM43236 Preliminary Data Sheet
Table 3: Signal Descriptions (Cont.)
BCM43236
Type
Description
jtag_tdo
19
I/O
jtag_tms
18
I/O
JTAG Test Data Output. Serial data output from
the JTAG TAP controller. Sampled on the rising
edge of TCK. If not used, it may be left
unconnected. This pin is muxed with btcx_prisel
(Bluetooth coexistence output, antenna select).
JTAG Mode Select Input. Single control input to
the JTAG TAP controller used to traverse the test
logic state machine. Sampled on the rising edge
of TCK. If not used, it may be left unconnected.
This pin is muxed with btcx_status (Bluetooth
coexistence output, status).
gpio_0
78
I/O
(8 mA)
gpio_1
79
I/O
gpio_2
80
I/O
gpio_3
gpio_4
81
82
I/O
I/O
gpio_5
84
I/O
OT
EK
CO
Signal
GPIO Interface
IN
LG
FO
CO
NF
ID
EN
TI
AL
General Purpose I/O pin. This pin is tristated on
power-up and reset. Subsequently, it becomes
an input or an output through software control.
A programmable PU or PD resistor is available
for each GPIO pin. This pin is muxed with
wlan_led (WLAN LED output).
General Purpose I/O pin. This pin is muxed with
mimophy_core0_ant_shd (antenna switch
control for the shared [middle] antenna of a 2 of
3 design
[core 0]).
General Purpose I/O pin. This pin is muxed with:
• mimophy_core1_ant_shd: antenna switch
control for the shared (middle) antenna of a
2 of 3 design
(core 1).
• btcx_freq: Bluetooth coexistence RF
frequency
General Purpose I/O pin.
General Purpose I/O pin. This pin is muxed with:
• ext_lna_2g_pu_0: 2.4 GHz band core 0
power amplifier control
• ext_pa_2g_0: 2.4 GHz band core 0 power
amplifier control
• CS: SPI select
General Purpose I/O pin. This pin is muxed with:
• ext_lna_2g_pu_1: 2.4 GHz band core 1
power amplifier control
• ext_pa_2g_1: 2.4 GHz band core 1 power
amplifier control
• SCLK: SPI clock
• I2C_SCL: I2C clock
BROADCOM
December 17, 2010 • 43236-DS04-R
2.4 GHz/5 GHz 802.11n MAC/PHY/Radio Chip
Page 24
®
12/20/2010 CTJ5M
Package Signal Descriptions
LT
BCM43236 Preliminary Data Sheet
Table 3: Signal Descriptions (Cont.)
BCM43236
Type
Description
gpio_6
85
I/O
gpio_7
13
I/O
gpiao_gpio_pad
43
–
General Purpose I/O pin. This pin is muxed with:
• ext_lna_5g_pu_0: 5 GHz band core 0 power
amplifier control
• ext_pa_5g_0: 5 GHz band core 0 power
amplifier control)
• SDI: SPI data input
General Purpose I/O pin. This pin is muxed with:
• ext_lna_5g_pu_1: 5 GHz band core 1 power
amplifier control
• ext_pa_5g_1: 5 GHz band core 1 power
amplifier control
• SDO: SPI data output
• I2C_SDA: I2C data
No connect; test only
62
61
I/O (4 mA PU) UART receive data
I/O (4 mA)
UART transmit data
IN
OT
EK
CO
Signal
UART_RX
UART_TX
Power and Ground
8, 12, 60, 66,
77, 88
vddio
1, 11, 63, 83
vddio/otp_vdd
76
usbavdd2p5
67
usbldo_2p5_out
58
usb_avdd3p3
69
usbavdd1p2
72
synth_vdd1p2
47
synth_vco_vdd1p2
46
core0_vdd1p2
38
core1_vdd1p2
29
tx_5g_core0_vdd1p2
36
tx_5g_core1_vdd1p2
27
tx_2g_core0_vdd1p2
40
tx_2g_core1_vdd1p2
31
pa_5g_core0_vdd3p3
34
pa_5g_core1_vdd3p3
25
pa_2g_core0_vdd3p3
41
pa_2g_core1_vdd3p3
32
analog_wlan_iqtest_vdd_1p2 17
PWR
1.2V supply input for the core logic.
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
3.3V supply input for I/O logic
3.3V supply input for I/O logic
USB analog power supply
USB LDO output; decouple to ground.
3.3V supply input to USB interface
1.2V supply input to USB interface
Analog 1.2V supply input
Analog 1.2V supply input
Analog 1.2V supply input
Analog 1.2V supply input
Analog 1.2V supply input
Analog 1.2V supply input
Analog 1.2V supply input
Analog 1.2V supply input
Filtered 3.3V input to internal PA
Filtered 3.3V input to internal PA
Filtered 3.3V input to internal PA
Filtered 3.3V input to internal PA
1.2V power supply for IQ test.
CO
NF
ID
EN
TI
AL
FO
vdd
LG
UART Interface
BROADCOM
December 17, 2010 • 43236-DS04-R
2.4 GHz/5 GHz 802.11n MAC/PHY/Radio Chip
Page 25
®
12/20/2010 CTJ5M
Strapping Options
LT
BCM43236 Preliminary Data Sheet
Table 3: Signal Descriptions (Cont.)
BCM43236
Type
Description
ldo_3p3_in
vddpll/rf_avdd_1p2
vreg3p3_vdd3p3
i_xtal_vdd2p5/o_xtal_vdd2p5
vref
paref
paref_ctl1
paref_ctl2
gnd_slug
gnd
57
59
45
50
56
55
54
53
24
PWR
PWR
PWR
–
–
–
–
GND
GND
3.3V input to RF LDO
XTAL power reference; decouple to ground.
Analog 3.3V supply
3.3V supply input for I/O logic
VREF; decouple to ground.
PA reference; decouple to ground.
PA reference control 1
PA reference control 2
Ground
Ground
IN
OT
EK
CO
Signal
Strapping Options
FO
LG
The pins listed in Table 4 are sampled at Power-on Reset (POR) to determine the various operating modes.
Sampling occurs within a few milliseconds following internal POR or deassertion of external POR. After POR,
each pin assumes the function specified in the signal descriptions table. Each pin has an internal pull-up (PU)
or pull-down (PD) resistor that determines the default mode. To change the mode, connect an external PU
resistor to VDDIO or a PD resistor to GND; use 10 kΩ or less (refer to the reference board schematics for further
details).
Signal Name
Mode
Default
Description
mimophy_core0_ant0_tx
OTP select
PU
CO
NF
ID
EN
TI
AL
Table 4: Strapping Options
0: No OTP
1: OTP present
0: SFLASH not present
1: SFLASH present
0: SFLASH type is STMicroelectronics
1: SFLASH type is Atmel®
0: HSIC mode
1: USB PHY mode
0: Backplane at 96 (98.4) MHz
1: Backplane at 120 (123) MHz
00: Remap to RAM; ARM processor to be held at
reset.
01: Boot from ROM unless the ARM needs to be
held at reset.
mimophy_core1_ant0_tx
SFLASH not
present
PD
mimophy_core0_ant0_rx
ST SFLASH
PD
mimophy_core0_ant1_tx
USB PHY
PU
mimophy_core0_ant1_rx
120 MHz
PU
gpio[7:6]
Boot from ROM
No pull
BROADCOM
December 17, 2010 • 43236-DS04-R
2.4 GHz/5 GHz 802.11n MAC/PHY/Radio Chip
Page 26
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Electrical Characteristics
LT
BCM43236 Preliminary Data Sheet
CO
Section 5: Electrical Characteristics
OT
EK
Note: Values in this data sheet are design goals and are subject to change based on the results of device
characterization.
Absolute Maximum Ratings
IN
Caution! The specifications in Table 5 define levels at which permanent damage to the device can
occur. Functional operation is not guaranteed under these conditions. Operation at absolute
maximum conditions for extended periods can adversely affect the long-term reliability of the device.
Table 5: Absolute Maximum Ratings
Symbol
DC supply voltage for core
DC supply voltage for I/O
Voltage on any input or output pin
Ambient Temperature (Operating)
Operating Junction Temperature 125°C
Operating Humidity
Storage Temperature
Storage Humidity
ESD Protection (HBM)
VDDC
VDDO
VIMAX, VIMIN
TA
TJ
–
TSTG
–
VESD
FO
CO
NF
ID
EN
TI
AL
Minimum
LG
Rating
–0.5
–0.5
–0.5
–
–
–40
–
–
Maximum
Unit
+1.4
+3.8
+3.8a
+65b
125
85
+125
60
2000
°C
°C
°C
a. The max voltage requirement is to not exceed VDDO + 0.5V when VDDO < 3.3V.
b. The temperature above the shield is 65°C for the TJ to be less than 125°C with a Pout of 15 dBm.
BROADCOM
December 17, 2010 • 43236-DS04-R
2.4 GHz/5 GHz 802.11n MAC/PHY/Radio Chip
Page 27
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Recommended Operating Conditions and DC Characteristics
LT
BCM43236 Preliminary Data Sheet
CO
Recommended Operating Conditions and DC Characteristics
Table 6: Recommended Operating Conditions and DC Characteristics
Value
Symbol
Minimum
Typical
Maximum
Unit
DC supply voltage for I/O
DC supply voltage for core and 1.2V analog
Input low voltage (VDDO = 3.3V)
Input high voltage (VDDO = 3.3V)
Output low voltage
Output high voltage
VDDO
VDD12
VIL
VIH
VOL
VOH
2.97
1.14
–
2.0
–
VDDO – 0.4V
3.3
1.2
–
–
–
–
3.63
1.26
0.8
–
0.4
–
IN
OT
EK
Element
Current Consumption from the 3.3V Supply
LG
Table 7: Current Consumption from 3.3V Supply
Item
Maximum
Units
29
120
462
48
148
716
mA
mA
mA
FO
Radio disabled state
Idle and associated state, PM2 mode
Active state, TX or RX, 40 MHz channel, maximum
throughput, PM2 mode
Typical
CO
NF
ID
EN
TI
AL
Current Consumption from the 1.2V Supply
Table 8: Current Consumption from 1.2V Supply
Item
Typical
Maximum
Units
Radio disabled state
Idle and associated state, PM2 mode
Active state, TX or RX, 40 MHz channel, maximum
throughput, PM2 mode
47
228
510
68
296
708
mA
mA
mA
BROADCOM
December 17, 2010 • 43236-DS04-R
2.4 GHz/5 GHz 802.11n MAC/PHY/Radio Chip
Page 28
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HSIC Characteristics
LT
BCM43236 Preliminary Data Sheet
Table 9: HSIC Characteristics
CO
HSIC Characteristics
Symbol
Minimum
Typical
Maximum
Unit
HSIC signaling voltage
I/O voltage input low
I/O Voltage input high
I/O voltage output low
I/O voltage output high
I/O pad drive strength
VDD
VIL
VIH
VOL
VOH
OD
1.1
–0.3
0.65 × VDD
–
0.75 × VDD
40
1.2
–
–
–
–
–
1.3
0.35 × VDD
VDD + 0.3
0.25 × VDD
–
60
Ω
I/O weak keepers
I/O input impedance
Total capacitive loada
Characteristic trace
impedance
Circuit board trace length
Circuit board trace
propagation skewb
STROBE frequencyc
Slew rate (rise and fall)
STROBE and DATAC
Receiver data setup time
(with respect to STROBE)c
Receiver data hold time
(with respect to STROBE)c
IL
ZI
CL
TI
20
100
45
–
–
–
50
70
–
14
55
mA
kΩ
pF
Ω
–
–
–
–
–
Controlled output
impedance driver
–
–
–
–
TL
TS
–
–
–
–
10
15
cm
ps
–
–
FSTROBE
Tslew
239.988
0.60 × VDD
240
1.0
240.012
1.2
MHz
V/ns
Ts
300
–
–
ps
300
–
–
ps
± 500 ppm
Averaged from
30% ~ 70% points
Measured at the
50% point
Measured at the
50% point
IN
LG
FO
Tb
Comments
OT
EK
Parameter
CO
NF
ID
EN
TI
AL
a. Total Capacitive Load (CL), includes device Input/Output capacitance, and capacitance of a 50Ω PCB trace with
a length of 10 cm.
b. Maximum propagation delay skew in STROBE or DATA with respect to each other. The trace delay should be
matched between STROBE and DATA to ensure that the signal timing is within specification limits at the
receiver.
c. Jitter and duty cycle are not separately specified parameters: they are incorporated into the values in the table
above.
BROADCOM
December 17, 2010 • 43236-DS04-R
2.4 GHz/5 GHz 802.11n MAC/PHY/Radio Chip
Page 29
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RF Specifications
LT
BCM43236 Preliminary Data Sheet
CO
Section 6: RF Specifications
2.4 GHz Band General RF Specifications
OT
EK
Note: Values in this data sheet are design goals and are subject to change based on the results of device
characterization.
Table 10: 2.4 GHz Band General RF Specifications
Minimum Typical
aRxTxTurnaroundTime
Including switch time
IN
Condition
–
–
Maximum
Unit
μs
CO
NF
ID
EN
TI
AL
FO
LG
Item
BROADCOM
December 17, 2010 • 43236-DS04-R
2.4 GHz/5 GHz 802.11n MAC/PHY/Radio Chip
Page 30
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12/20/2010 CTJ5M
2.4 GHz Band Receiver RF Specifications
LT
BCM43236 Preliminary Data Sheet
CO
2.4 GHz Band Receiver RF Specifications
Table 11: 2.4 GHz Band Receiver RF Specifications
Condition
Cascaded Noise Figure
Maximum Receive Levela
–
–
4.5
@ 1, 2 Mbps
–4
–
@ 5.5, 11 Mbps
–10
–
@ 54 Mbps
–10
–
Maximum gain
–
–16
Minimum gain
–
–2
–
8.5
WB mode
–
NB mode
120 Hz
–
WB mode
–
500
NB mode
120 Hz
–
–
–
88
–
–
20 MHz channel spacing for all MCS rates
MCS0 OFDM
–
–91
MCS7 OFDM
–
–74
MCS8 OFDM
–
–88.5
MCS15 OFDM
–
–69
40 MHz channel spacing for all MCS rates
MCS0 OFDM
–
–88
MCS7 OFDM
–
–71
MCS8 OFDM
–
–85.5
MCS15 OFDM
–
–66
LPF DC Rejection Servo Loop Bandwidth
CO
NF
ID
EN
TI
AL
FO
Maximum Receiver Gain
Gain Control Step
Rx Sensitivity
(10% PER for 4096 octet PSDU) at WLAN
RF port. Defined for default parameters:
GF, 800 ns GI, and non-STBC.
IN
LPF 3 dB Bandwidth
PGA DC Rejection Servo Loop Bandwidth
LG
Input IP3
Minimum Typical
Maximum
Unit
–
–
–
–
–
–
–
230 kHz
–
230 kHz
–
–
dB
dBm
dBm
dBm
dBm
dBm
MHz
MHz
–
kHz
–
dB
dB/step
–
–
–
–
dBm
dBm
dBm
dBm
–
–
–
–
dBm
dBm
dBm
dBm
OT
EK
Characteristic
a. When using a suitable external switch.
BROADCOM
December 17, 2010 • 43236-DS04-R
2.4 GHz/5 GHz 802.11n MAC/PHY/Radio Chip
Page 31
®
12/20/2010 CTJ5M
2.4 GHz Band Transmitter RF Specifications
LT
BCM43236 Preliminary Data Sheet
Table 12: 2.4 GHz Band Transmitter RF Specifications
CO
2.4 GHz Band Transmitter RF Specifications
Characteristic
Condition
Minimum Typical
Maximum Unit
RF Output Frequency Range
G band
–
20 MHz BW
40 MHz BW
–
fc – 22 MHz < f < fc – 11 MHz
fc + 11 MHz < f < fc + 22 MHz
f < fc – 22 MHz; and f > fc + 22
MHz
IEEE 802.11b mode
IEEE 802.11g mode
–
IEEE 802.11b mode
IEEE 802.11g mode
DC input
DC input
Shaped pulse
2400
–
–
15
–
–
–
2500
16
14.5
–
–30
–30
–50
MHz
dBm
dBm
dBr
dBr
dBr
dBr
35%
5%
–
–
–
1.5
–
–
–
dB/step
MHz
MHz
dB
°C
Vpp
OT
EK
IN
Carrier Suppression
TX Spectrum mask @
maximum gain
–
–
–
–
–
–
–
Amplitude Balancea
Phase Balancea
Baseband Differential Input
Voltage
–
–
0.25
12
12
–
–
0.6
LG
Gain Control Step Size
I/Q Baseband Bandwidth
–
–
–
–
–
–1
–1.5
–
FO
TX Modulation Accuracy
(EVM) at maximum gain
a. At a 3 MHz offset from the carrier frequency.
CO
NF
ID
EN
TI
AL
2.4 GHz Band Local Oscillator Specifications
Table 13: 2.4 GHz Band Local Oscillator Specifications
Characteristic
Condition Minimum Typical
Maximum Unit
VCO Frequency Range
Reference Input Frequency Range
Clock Frequency Tolerance
Reference Spurs
Local Oscillator Phase Noise, single-sided from
1 kHz–300 kHz offset
–
–
–
–
–
2484
–
±20
–34
–86.5
BROADCOM
December 17, 2010 • 43236-DS04-R
2412
–
–
–
–
–
20
–
–
–
MHz
MHz
ppm
dBc
dBc/Hz
2.4 GHz/5 GHz 802.11n MAC/PHY/Radio Chip
Page 32
®
12/20/2010 CTJ5M
5 GHz Band Receiver RF Specifications
LT
BCM43236 Preliminary Data Sheet
5 GHz Band Receiver RF Specifications
CO
Table 14: 5 GHz Band Receiver RF Specificationsa
Characteristic
Condition
Minimum Typical
Maximum Unit
Cascaded Noise Figure
Maximum Receive Levela (5.24 GHz)
Maximum Receive Levela (5.24 GHz)
Input IP3
Maximum RX gain
@ 6 Mbps
@ 54 Mbps
Maximum LNA gain
Minimum LNA gain
–
WB mode
NB mode
–
–
–
–
–
–
–10 (TBV)
–15 (TBV)
–
–
–
–
120 Hz
–
–
–
–
–
–
–
–
–
–
–
–
230 kHz
–
–
–
–
–
OT
EK
IN
Minimum RX Gain
Maximum RX Gain
Gain Control Step
IQ Amplitude Balance
IQ Phase Balance
LG
LPF 3 dB Bandwidth
DC Rejection Servo Loop Bandwidth
(normal operation)
4.5
–
–
–5
–4
8.5
500
–
15
92
0.5
1.5
dB
dBm
dBm
dBm
dBm
MHz
kHz
–
dB
dB
dB/step
dB
°C
Out-of-Band Blocking Performance without RF Band-Pass Filter (–1 dB desensitization):
30 MHz–4300 MHz
–10 (TBV) –
4300 MHz–4800 MHz –25 (TBV) –
5900 MHz–6400 MHz –25 (TBV) –
20 MHz channel spacing for all MCS rates
MCS0 OFDM
–
–90
MCS7 OFDM
–
–74
MCS8 OFDM
–
–88.5
MCS15 OFDM
–
–69
40 MHz channel spacing for all MCS rates
MCS0 OFDM
–
–87
MCS7 OFDM
–
–71
MCS8 OFDM
–
–86
MCS15 OFDM
–
–66
CO
NF
ID
EN
TI
AL
FO
CW
CW
CW
Rx Sensitivity
(10% PER for 4096 octet PSDU) at
WLAN RF port. Defined for default
parameters: GF, 800 ns GI, and nonSTBC.
–
–
–
dBm
dBm
dBm
–
–
–
–
dBm
dBm
dBm
dBm
–
–
–
–
dBm
dBm
dBm
dBm
a. With minimum RF gain.
BROADCOM
December 17, 2010 • 43236-DS04-R
2.4 GHz/5 GHz 802.11n MAC/PHY/Radio Chip
Page 33
®
12/20/2010 CTJ5M
5 GHz Band Transmitter RF Specifications
LT
BCM43236 Preliminary Data Sheet
CO
5 GHz Band Transmitter RF Specifications
Table 15: 5 GHz Band Transmitter RF Specifications
Characteristic
Condition
Minimum Typical Maximum Unit
–
4920
20 MHz BW
–
40 MHz BW
–
Carrier Suppression
–
–
TX Spectrum mask
f < fc – 11 MHz and f > fc + 11 MHz –
(chip output power = 11 dBm) f < fc – 20 MHz and f > fc + 20 MHz –
f < fc – 30 MHz and f > fc + 30 MHz –
TX Modulation Accuracy (EVM) Po = 11 dBm
–
TX Modulation Accuracy (EVM) Po = 6 dBm
–
Gain Control Step Size
–
–
I/Q Baseband 3 dB Bandwidth –
–
Amplitude Balance
DC Input
–0.5
Phase Balance
DC Input
–1.5
Baseband Differential Input
–
–
Voltage
TX Power Ramp Up
90% of final power
–
TX Power Ramp Down
10% of final power
–
–
–
–
–
–
–
–
–25
–33
12
–
–
0.7
5805
15
14
TBD
–26
–35
–40
–
–
–
–
0.5
1.5
–
MHz
dBm
dBm
dBr
dBc
dBr
dBr
dB
dB
dB/step
MHz
dB
°C
Vpp
–
–
µsec
µsec
FO
LG
IN
OT
EK
RF Output Frequency Range
Output Power (EVMcompliant)
CO
NF
ID
EN
TI
AL
5 GHz Band Local Oscillator Frequency Generator
Specifications
Table 16: 5 GHz Band Local Oscillator Frequency Generator Specifications
Characteristic
Condition
Minimum Typical
Maximum
Unit
VCO Frequency Range
Reference Input Frequency Range
Clock Frequency Tolerance
Reference Spurs
Local Oscillator Integrated Phase
Noise (1 kHz–300 kHz)
–
–
–
–
4.920 GHz–5.700 GHz
5.725 GHz–5.805 GHz
4920
–
–
–
–
–
5805
–
±20
–30
–
–
MHz
MHz
ppm
dBc
°C
BROADCOM
December 17, 2010 • 43236-DS04-R
–
20
–
–
0.7
1.4
2.4 GHz/5 GHz 802.11n MAC/PHY/Radio Chip
Page 34
®
12/20/2010 CTJ5M
On-Chip Regulator Power Supply Characteristics
LT
BCM43236 Preliminary Data Sheet
CO
On-Chip Regulator Power Supply Characteristics
Table 17: On-Chip Regulator Power Supply Characteristics
Value
Minimum
2.5V–3.1V PA Reference LDO (default: off)
Vout: 2.5V to 3.1V when output A, B, C and/or D is enabled.
Control Step: 50 mV/step
FO
3.3V–1.2V RF LDO
CO
NF
ID
EN
TI
AL
Input power supply, Vbat
Vout (Note 1) Programmable, 50 mV/step
Absolute Accuracy
Dropout Voltage
Maximum Output Current
Startup time with 100 µs VDD
Ramp
Maximum Unit
3.3
2.85
–
–
–
–
–
30
3.63
3.1
+4
40
10
–
100
100
mA
mA
mV
µs
ns
1.3
ns
2.97
1.2
–4
150
–
–
3.30
–
–
–
–
–
3.63
3.0
+4
–
120
50
mV
mA
µs
IN
2.97
2.5
–4
–
–
150
–
20
LG
Input Power Supply
Vout (Note 1) Programmable, 50 mV/step
Absolute Accuracy
Maximum Output Current: A, B, C and D all enabled
Maximum Output Current: any output A, B, C, or D
Dropout Voltage
Startup Time
Switching ON Time (either A or G)
Note: LDO is already powered.
Switching OFF Time (either A or G)
Note: LDO is already powered.
Typical
OT
EK
Element
3.3V–2.5V USB LDO
Input power supply
2.97
3.30
3.63
Vout
2.3
2.5
2.65
Absolute accuracy
–4
–
+4
Dropout voltage
150
–
–
mV
Maximum output current
–
–
30
mA
Start-up time
–
–
50
µs
Note: It is required that the input supply be at least 200 mV higher than the output. More headroom is better
for PSRR performance.
BROADCOM
December 17, 2010 • 43236-DS04-R
2.4 GHz/5 GHz 802.11n MAC/PHY/Radio Chip
Page 35
®
12/20/2010 CTJ5M
Timing Characteristics
CO
Section 7: T iming Characteristics
LT
BCM43236 Preliminary Data Sheet
Reset and Clock Timing Diagram
OT
EK
Resets are generated internally by the BCM43236. An optional external Power-On Reset (POR) circuit can be
connected to the active-low Ext_por input pin. The BCM43236 is reset automatically as long as the power
supplies are turned on in the following sequence. 3.3V first, 2.5V second, and 1.2V last.
t210
Vcc
t206
t201
WPLL_CLK25
(20 MHz)
IN
t204
t203
t202
t207
LG
Ext_por
FO
Configuration
Strap Signals
t208
t205
t209
Valid
Figure 9: Timing for the Optional External Power-On Reset
Table 18: Ext_por and Clock Timing
Parameter Description
OSCIN frequency
OSCIN high time
OSCIN low time
EXT_POR_L low pulse duration
Configuration valid setup to EXT_POR_L rising
Configuration valid hold from EXT_POR_L rising
EXT_POR_L deassertion to normal switch
operation
Reset low hold time after power supplies
stabilize
CO
NF
ID
EN
TI
AL
t201
t202
t203
t204
t207
t208
t209
t210
BROADCOM
December 17, 2010 • 43236-DS04-R
Minimum Typical
Maximum Units
19.9995
–
–
50
50
1.7
–
20.0000
20
20
–
–
–
20.0005
–
–
–
–
2.8
–
MHz
ns
ns
ms
μs
ms
ms
50
–
–
ms
2.4 GHz/5 GHz 802.11n MAC/PHY/Radio Chip
Page 36
®
12/20/2010 CTJ5M
Serial Flash Timing Diagram
LT
BCM43236 Preliminary Data Sheet
CO
Serial Flash Timing Diagram
tCS
SFLASH_CS_L
tCSH
tR
tWL
tWH
OT
EK
tCSS
tF
SFLASH_C
tSU
tH
SFLASH_Q
tV
tHO
High Impedance
SFLASH_D
High Impedance
LG
VALID ON
IN
VALID IN
Figure 10: Serial Flash Timing Diagram (STMicroelectronics-Compatible)
FO
Table 19: Serial Flash Timing
Descriptions
fSCK
tWH
tWL
tR, tFa
tCSS
tCS
tCSH
tSU
tH
tHO
tV
Serial flash clock frequency
Serial flash clock high time
Serial flash clock low time
Clock rise and fall timesb
Chip select active setup time
Chip select deselect time
Chip select hold time
Data input setup time
Data input hold time
Data output hold time
Clock low to output valid
CO
NF
ID
EN
TI
AL
Parameter
Minimum Typical
Maximum
Units
–
TBD
100
–
66
–
–
–
–
–
–
–
–
–
MHz
ns
ns
V/ns
ns
ns
ns
ns
ns
ns
ns
12.5
–
–
–
–
–
–
–
–
–
–
a. tR and tF are expressed as a slew-rate.
b. Peak-to-peak
BROADCOM
December 17, 2010 • 43236-DS04-R
2.4 GHz/5 GHz 802.11n MAC/PHY/Radio Chip
Page 37
®
12/20/2010 CTJ5M
Thermal Information
Table 20: 88-Pin QFN Thermal Characteristics
θJA (°C/W)
θJB (°C/W)
θJC (°C/W)
100 fpm,
0.508 mps
200 fpm,
1.016 mps
20.79
3.95
12.44
3.51
17.55
–
–
3.50
16.24
–
–
3.55
400 fpm,
2.032 mps
600 fpm,
3.048 mps
15.00
–
–
3.59
14.34
–
–
3.61
IN
ΨJT (°C/W)
0 fpm,
0 mps
OT
EK
Airflow
CO
Section 8: Thermal Information
LT
BCM43236 Preliminary Data Sheet
LG
Note:
• In the thermal characterizations that were done on the BCM43236 using a 4-layer board, the
temperature at 1 mm above the shield must be no higher than 65°C in order to keep the junction
temperature (TJ) from exceeding 125°C.
• The BCM43236 is designed and rated for operation at a maximum TJ of 125°C.
FO
Junction Temperature Estimation and PSIJT Versus ThetaJC
CO
NF
ID
EN
TI
AL
Package thermal characterization parameter Psi-JT (ΨJT) yields a better estimation of actual junction
temperature (TJ) versus using the junction-to-case thermal resistance parameter Theta-JC (θJC). The reason for
this is θJC assumes that all the power is dissipated through the top surface of the package case. In actual
applications, some of the power is dissipated through the bottom and sides of the package. ΨJT takes into
account power dissipated through the top, bottom, and sides of the package. The equation for calculating the
device junction temperature is as follows:
TJ = TT + P ×ΨJT
Where:
• TJ = junction temperature at steady-state condition, °C
• TT = package case top center temperature at steady-state condition, °C
• P = device power dissipation, Watts
• ΨJT = package thermal characteristics (no airflow), °C/W
Package thermal characterization measurements: The temperature above the shield is 65°C for the TJ to be less
than 125°C with a Pout of 15 dBm.
BROADCOM
December 17, 2010 • 43236-DS04-R
2.4 GHz/5 GHz 802.11n MAC/PHY/Radio Chip
Page 38
®
12/20/2010 CTJ5M
Package Information
CO
NF
ID
EN
TI
AL
FO
LG
IN
OT
EK
CO
Section 9: Package Information
LT
BCM43236 Preliminary Data Sheet
Figure 11: BCM43236 Mechanical Drawing
BROADCOM
December 17, 2010 • 43236-DS04-R
2.4 GHz/5 GHz 802.11n MAC/PHY/Radio Chip
Page 39
®
12/20/2010 CTJ5M
Ordering Information
Table 21: Ordering Information
CO
Section 10: Ordering Information
LT
BCM43236 Preliminary Data Sheet
Package
Temperature @ 1 mm Above the Shield
BCM43236KMLG
10 × 10, 88-pin QFN (RoHs compliant)
0°C to 65°C (32°F to 149°F)
CO
NF
ID
EN
TI
AL
FO
LG
IN
OT
EK
Part Number
BROADCOM
December 17, 2010 • 43236-DS04-R
2.4 GHz/5 GHz 802.11n MAC/PHY/Radio Chip
Page 40
®
12/20/2010 CTJ5M
CO
NF
ID
EN
TI
AL
FO
LG
IN
OT
EK
CO
LT
BCM43236 Preliminary Data Sheet
Broadcom® Corporation reserves the right to make changes without further notice to any products
or data herein to improve reliability, function, or design.
Information furnished by Broadcom Corporation is believed to be accurate and reliable. However,
Broadcom Corporation does not assume any liability arising out of the application or use of this
information, nor the application or use of any product or circuit described herein, neither does it
convey any license under its patent rights nor the rights of others.
®
BROADCOM CORPORATION
5300 California Avenue
Irvine, CA 92617
© 2010 by BROADCOM CORPORATION. All rights reserved.
43236-DS04-R
December 17, 2010
12/20/2010 CTJ5M
Phone: 949-926-5000
Fax: 949-926-5203
E-mail: info@broadcom.com
Web: www.broadcom.com

---

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