96523_1_13_CSFB_SKY77754_05161406 HUAWEI G620 Schematic
User Manual: Manual Huawei - Schematics & Service Manuals PDF
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W20 U20 V20 V21 U21 W21 Y20 Y21 AA21 AB21 U17 U18 A2 R24 VIO18_PMU VIO18_PMU C112 100nF C108 C109 C110 100nF 100nF 100nF N12 N13 N14 N15 N16 N17 P14 R15 P15 R14 R13 R12 R16 R17 T14 T15 U15 U16 V15 V16 DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS M15 N21 P10 P11 P12 P13 P16 P17 L18 M14 M13 M12 AVDD18_MD AE19 AVDD18_AP AE22 AE18 A3 AVDD28_DAC DVDD18_PLLGP AVDD18_MEMPLL AC21 AD22 AG26 V17 V18 AA18 AB19 AVSS18_MD AVSS18_MD AVSS18_MD DVSS DVSS AVSS18_AP AVSS18_AP AVSS18_WBG AVSS18_WBG MT6592 DVDD18_MIPITX L2 DVDD18_MIPIIO G1 AVDD33_USB AVDD18_USB DVSS18_MIPIIO DVSS18_MIPIIO DVSS18_MIPIIO DVSS18_MIPIIO DVSS18_MIPITX DVSS18_MIPITX DVSS18_MIPITX DVSS18_MIPITX C125 10uF Bottom cap/1st cap group check MSDC1/2 IO power 100nF VM12_SW_PMU 100nF C115 C116 C117 100nF 1.0uF C123 100nF C127 C122 100nF 0 0 0 R104 0 VMC_PMU VIO18_PMU VIO18_PMU VIO18_PMU C128 100nF 100nF R101 R102 R103 100nF VCORE_SW_FB [4] VCCK C104 100nF C124 100nF C140 C131 100nF C152 C153 C129 C136 C137 10uF 10uF 22uF 1.0uF Bottom cap 1st cap group VCCK_VPROC VPROC_PMU C156 100nF C157 100nF C158 C148 100nF C155 C154 C132 C133 C134 22uF 22uF 22uF Bottom cap 1st cap group HT107 GND_VPROC_FB HT103 VPROC_FB [3] To MT6323 GND_VPROC_FB pin To MT6323 VPROC_FB pin [3,4] (1)VPROC_BB, GND pin of 1st cap group should be laid differential pair with ground shielding remote sense to PMIC (2)R107 & R103 must be close to 1st cap group. If you want to remove them, please make sure the VPROC_FB/GND_VPROC_FB must connect from 1st cap. group of VPROC R105 C111 T24 P26 VUSB_PMU VIO18_PMU R106 H4 H5 J5 J7 L4 M7 M8 N3 check MSDC1/2 IO power C115 close to pin E1 (150mil) C125 close to pin G26 (150mil) 1.0uF VCCK_VPROC VCCK_VPROC VCCK_VPROC VCCK_VPROC VCCK_VPROC VCCK_VPROC VCCK_VPROC VCCK_VPROC VCCK_VPROC VCCK_VPROC VCCK_VPROC VCCK_VPROC VCCK_VPROC VCCK_VPROC VCCK_VPROC VCCK_VPROC VCCK_VPROC VCCK_VPROC VCCK_VPROC VCCK_VPROC AVSS18_MEMPLL AVSS33_USB AE21 AF3 AG1 R10 P9 L11 L12 L13 L14 L15 L16 L17 M10 M18 N10 N18 P18 R9 R18 T10 U10 V10 C130 C151 100nF 100nF C120 100nF C119 100nF C113 100nF 0 VIO18_PMU For low-power testing proposal. It can be cancel for cost-down proposal 0 For low-power testing proposal. It can be cancel for cost-down proposal 1uF DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS VIO18_PMU VTCXO_PMU DVSS DVSS DVSS DVSS DVSS DVSS AVSS18_MD AVSS18_MD AVSS18_MD AVSS18_MD DVSS DVSS VM_PMU C144 C143 C142 100nF E1 V1 AD26 U25 G26 L26 Y26 D1 W1 AG13 VCCK VCCK VCCK VCCK VCCK VCCK VCCK VCCK VCCK VCCK VCCK VCCK VCCK VCCK VCCK VCCK VCCK VCCK VCCK [4] T12 M16 K21 M17 H12 J21 H20 H17 H14 V14 For low-power testing proposal. It can be cancel for cost-down proposal DVDD28_MSDC1 DVDD28_MSDC2 DVDD28_BPI DVDD28_MD DVDD18_MSDC0 DVDD18_IO0 DVDD18_IO1 DVDD18_IO2 DVDD18_IO3 DVDD18_IO4 H18 H16 H15 G9 G11 G13 G15 G16 G18 H8 E7 F7 F8 G8 H11 H13 1.0uF AVSS18_WBG DVSS DVSS DVSS AVSS18_WBG AVSS18_WBG AVSS18_WBG AVSS18_WBG AVSS18_WBG AVSS18_WBG AVSS18_WBG AVSS18_WBG 1.2V IO for DDR2 DVDD12_EMI DVDD12_EMI DVDD12_EMI DVDD12_EMI DVDD12_EMI DVDD12_EMI DVDD12_EMI DVDD12_EMI DVDD12_EMI DVDD12_EMI DVDD12_EMI DVDD12_EMI DVDD12_EMI DVDD12_EMI DVDD12_EMI DVDD12_EMI 1.0uF AE5 V7 U7 W7 Y7 AB6 AB8 AC3 AC5 AC7 AD4 AE3 BUCK1_FB For low-power testing proposal. It can be cancel for cost-down proposal 1.0uF DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS T11 R11 R2 G6 G7 G14 G17 G20 H10 M20 N11 A19 A26 B4 B10 E21 F6 B12 B14 B17 B22 B24 C4 C8 C11 C12 C16 C17 C18 C20 C21 C22 C23 C25 D4 D5 D7 D9 D11 D13 D15 D17 D21 D24 E5 E8 E10 E18 F18 P21 L10 1.0uF U201-B T13 T16 T17 T18 T21 M11 U11 U12 V11 V12 V13 DVDD12_EMI MT6582 R119=NF, R101=0, R102=NF, R120=NF, R110=0 MT6592 R119=0, R101=NF, R102=0, R120=0, R110=NF MT6582 C135, C137, 可以NF MT6592 C135=22uF, C137=22uFTITLE: DOCUMENT NO.: REV: 01_MT6582_POWER <REV> SIZED: A1 Hardware DEPT. DEPARTMENT: COMPANY: DESIGNER: <DESIGNER> Last Saved Date: 2014-7-30 SHEET: 1 OF 33 U201-D ED31 ED30 ED29 ED28 ED27 ED26 ED25 ED24 ED23 ED22 ED21 ED20 ED19 ED18 ED17 ED16 ED15 ED14 ED13 ED12 ED11 ED10 ED9 ED8 ED7 ED6 ED5 ED4 ED3 ED2 ED1 ED0 U201-A WG_GGE_PA_VRAMP DCOC_FLAG AF25 AE24 VBIAS APC AE14 TXBPI TD_PA_B40_EN SP3T_A SP3T_B [25] RTC32K_BPI_BUS14 2 C205 100nF EVREF BSI-A_EN BSI-A_CK BSI-A_DAT0 BSI-A_DAT1 2 2 C207 1 C206 100nF VM1 1 VM0 1.0uF [2,6] 1 AD14 Y14 AB14 AA14 AC14 2 BSI_EN BSI_CLK BSI_DATA0 BSI_DATA1 BSI_DATA2 W_PA_B1_EN W_PA_B2_EN W_PA_B5_EN W_PA_B8_EN 8.2K AG14 AF14 ASM_VCTRL_B ASM_VCTRL_C WG_GGE_PA_ENABLE 1 VM0 VM1 DVDD12_EMI ASM_VCTRL_A R209 DL_I_P DL_I_N DL_Q_P DL_Q_N AB24 AB23 AD25 AC24 AC23 AE25 AD24 AF16 AA17 AD16 AC16 AF15 AC17 AB17 AC15 Y15 2 AG25 AG24 AG22 AG23 BPI_BUS0 BPI_BUS1 DVDD28_BPI BPI_BUS2 BPI_BUS3 BPI_BUS4 BPI_BUS5 BPI_BUS6 BPI_BUS7 BPI_BUS8 BPI_BUS9 BPI_BUS10 BPI_BUS11 BPI_BUS12 BPI_BUS13 BPI_BUS14 BPI_BUS15 DVDD18_IO4 8.2K UL_I_P UL_I_N UL_Q_P UL_Q_N 1 RX_BBIP RX_BBIN RX_BBQP RX_BBQN AF22 AF21 AG20 AF20 R211 TX_BBIP TX_BBIN TX_BBQP TX_BBQN BSI-A_DAT2 [2,6] EVREF RDQ31 RDQ30 RDQ29 RDQ28 RDQ27 RDQ26 RDQ25 RDQ24 RDQ23 RDQ22 RDQ21 RDQ20 RDQ19 RDQ18 RDQ17 RDQ16 RDQ15 RDQ14 RDQ13 RDQ12 RDQ11 RDQ10 RDQ9 RDQ8 RDQ7 RDQ6 RDQ5 RDQ4 RDQ3 RDQ2 RDQ1 RDQ0 F16 VREF T250 MT6592 C26 C24 A25 B25 B26 B23 A23 D25 A11 A14 A13 D12 A10 B13 C10 B11 D22 B20 D20 A22 C19 B19 A20 B21 B16 A17 B18 A16 B15 C15 D14 C14 A1 B7 B6 RCKE B5 RDQM0 RDQM1 RDQM2 RDQM3 D16 D18 D10 D23 RDQS0 RDQS1 RDQS2 RDQS3 F15 F17 F12 E20 RDQS0_B RDQS1_B RDQS2_B RDQS3_B E15 E17 E12 F20 RCLK0_B RCLK0 F9 E9 RA0 RA1 RA2 RA3 RA4 RA5 RA6 RA7 RA8 RA9 B8 B9 D8 A8 A7 C7 A5 D6 C6 A4 REXTDN B3 ECS0_B [6] ECS1_B ECKE EDQM0 EDQM1 EDQM2 EDQM3 [6] [6] [6] [6] [6] [6] EDQS0 [6] EDQS1 [6] EDQS2 [6] EDQS3 [6] EDQS0_B [6] EDQS1_B EDQS2_B EDQS3_B [6] [6] [6] EDCLK_B [6] EDCLK [6] EA0 EA1 EA2 EA3 EA4 EA5 EA6 EA7 EA8 EA9 1 TP_MEMPLL RCS0_B RCS1_B 2 MT6592 R221 54.9欧姆，1%，0402 54.9 SCL0 [2,12] SDA0 [2,12] SCL1 [2,4,13] SDA1 [2,4,13] SCL2 [2,18] SDA2 [2,18] VIO18_PMU U201-E LTE_AP_RSTB T205 [12] [12] [12] [12] [12] [12] [21,25] LTE_PMU_EN_P [21,22] MIPI_TCP MIPI_TCN MIPI_TDP0 MIPI_TDN0 MIPI_TDP1 MIPI_TDN1 MIPI_TDP2 MIPI_TDN2 UTXD3 EINT14_CTP_RST URXD2 UTXD2 [21] URXD2 [21] UTXD2 EINT_ACC GPIO_CHG_EN URXD1 T203 EINT20_GY UTXD1 URXD0 UTXD0 T202 T211 5.1K 2 1 90 Ohm differential 1 [14] USB_DP [14] USB_DM [3] CHD_DP SCL0 SDA0 [3] CHD_DM AF12 AE12 JTCK JTDO JTDI AF13 JTMS USB_DP USB_DM N23 N24 CHD_DP CHD_DM J23 H23 J24 H22 H24 AUD_CLK_MOSI AUD_DAT_MISO AUD_DAT_MOSI K26 K25 J25 AUD_CLK AUD_DAT_MISO AG10 AF9 GPIO12 GPIO13 SIM1_SCLK SIM1_SIO SIM1_SRST SIM2_SCLK SIM2_SIO SIM2_SRST 10K C210 区分硬件配置 MT6592 注意ADC的最大输入电压为1.5V HT201 10K 10k [2] AUX_IN1_NTC NTC201 AUX_IN0_NTC C213 Close to MT6582 AF19 should connect to C213.2 first, than connect to GND by via RCP_A_ RCN_A_ RDP0_A RDN0_A RDP1_A RDN1_A CMMCLK CMPCLK B2 B1 CMDAT0 CMDAT1 E2 F2 LRSTB [12] LPTE [12] PWM [12] CMMCLK [13] CMPCLK [13] CMDAT0 CMDAT1 [13] [13] 1 VRT [2,3] SRCLKENAI SRCLKENA [21] [3,4,21,29] PMIC_SPI_CS [3] PMIC_SPI_SCK PMIC_SPI_MISO PMIC_SPI_MOSI EINT_PMIC [3] [3] [3] [3] AUD_DAT_MOSI 1.5K Close to MT6582 C208 are for ESD ehnhace proposal. It can be cancel for cost-down proposal [3] [3] [3] L21 K23 L23 L20 L24 K24 <Parallel Cam./MIPI CSI Mux Table> W22 V22 AA24 V24 W25 Y25 AA23 AA26 AA25 Y23 Y22 EINT0_MT6333 [4] EINT1_A EINT2_CTP [12] EINT3_SUB_CMRST EINT4_SUB_CMPDN EINT5_RSTB_FROM_LTE BAT_ID EINT7_SDIO_INTB_LTE EINT8_AGPS_OUT_LTE [21,23] [18] [24] EINT9_MAINCAM_RST EINT10_CMPDN [13] [13] AP_PCM_CK [21,24] AP_PCM_RX [21,24] AP_PCM_FSYNC [21,24] [21,24] AP_PCM_TX For earpohne & MSDC hotplug EINT, plase choose EINT[0:15] with HW de-bounce function. Notice : Please choose EINT[0:15] with HW debouce for mechanism plug in/out related application. Ex: earphone, MSDC, SIM hot-plug MSDC0_DAT7 MSDC0_DAT6 MSDC0_DAT5 MSDC0_DAT4 MSDC0_DAT3 MSDC0_DAT2 MSDC0_DAT1 MSDC0_DAT0 MSDC0_CLK MSDC0_CMD MSDC0_RSTB DVDD18_MSDC0 MIPI CSI IF Port Parallel Camera IF Port RDP2 RDN2 RDP3 RDN3 [21,25] EINT6_M V23 V26 V25 U24 BAT_ID [2] CMDAT9 CMDAT8 CMDAT5 CMDAT4 RCP_A RCN_A RDP0_A RDN0_A CMDAT7 CMDAT6 CMVSYNC CMHSYNC RDP1_A RDN1_A CMDAT3 CMDAT2 CMDAT1 CMDAT0 CMDAT1 CMDAT0 CMMCLK CMPCLK CMMCLK CMPCLK F22 E23 F24 G24 E26 E25 G23 G22 D26 E24 G25 1uF [2] DVDD28_MSDC1 MSDC1_DAT3 MSDC1_DAT2 MSDC1_DAT1 MSDC1_DAT0 MSDC1_CLK MSDC1_CMD REFP AVSS_REFN DVDD28_MSDC2 D3 C2 D2 E4 C3 E3 AUX_XP AUX_XM AUX_YP AUX_YM REFP AG19 AF19 100PF 39K R222 AF18 AG17 AF17 AG16 EINT0 EINT1 EINT2 EINT3 EINT4 EINT5 EINT6 EINT7 EINT8 EINT9 EINT10 PCM_CLK PCM_RX PCM_SYNC PCM_TX MSDC2_DAT3 MSDC2_DAT2 MSDC2_DAT1 MSDC2_DAT0 MSDC2_CLK MSDC2_CMD 100PF [3] BAT_ID_ADC DVDD28_MD T2 T1 T5 T6 R7 T3 C203 C202 100PF 100PF C204 KPCOL2 KPROW2 KPCOL1 KPROW1 M24 N25 GPIO12 GPIO13 DVDD18_IO3 AUX_IN0 AUX_IN1 F5 G5 G4 G3 J3 H3 N1 MIPI_VRT SYSRST_B SRCLKENAI SRCLKENA I2S_BCK I2S_LRCK I2S_DATA_IN AC19 AD19 RCP RCN RDP0 RDN0 RDP1 RDN1 RDP2_ RDN2_ RDP3_ RDN3_ U3 Y3 AD9 R203 M25 USB_VRT R26 R25 V5 U5 W5 [12] LCD_ID_ADC C213 MT6605 OSC_EN (SRCLKENAI) need to default low for MT6605 TESTMODE boot-strap SYSRSTB PWRAP_SPI0_CSN PWRAP_SPI0_CK PWRAP_SPI0_MI PWRAP_SPI0_MO PWRAP_INT [2] AUX_IN1_NTC VIO18_PMU Y13 AA13 AD13 AE13 AB13 AC13 KPCOL0 KPROW0 AF10 AF8 AG8 AE10 AC11 AD10 AE9 AC10 EINT14 EINT15 EINT16 EINT17 EINT18 EINT19 EINT20 EINT11 AC8 AC9 AB9 AD7 SPI_CS SPI_MO SPI_MI SPI_CK AA3 AB3 AD8 AE7 AA1 AA2 SCL0 SDA0 SCL1 SDA1 SCL2 SDA2 P23 P22 T23 R23 UTXD3 URXD3 UTXD2 URXD2 U2 V2 Y2 W2 TESTMODE FSOURCE_P DVDD18_EFUSE WATCHDOG [2] AUX_IN0_NTC VIO18_PMU CMDAT7 CMDAT6 CMVSYNC CMHSYNC CMDAT3 CMDAT2 K6 K5 L3 K3 K1 K2 J1 J2 G2 H2 LCM_RST DSI_TE DISP_PWM MT6592 DVDD28_MD [21,24] AP_WAKEMD_INT Plasse reservr R336/NTC301 & R339/NTC302 for thermal protection option [4] RTC32K_CK AG11 P25 USB_VRT Close to MT6582 R220 2.2K 1 T212 R201 [2,3] SYSRST_B GPIO93_DRVVBUS 2 AF11 R5 R4 N26 TESTMODE FSOURCE_P T210 VIO18_PMU [13] [13] [13] [13] [13] [13] [17] [17] KCOL2 TCP TCN TDP0 TDN0 TDP1 TDN1 TDP2 TDN2 TDP3 TDN3 NF 0 0 T209 R219 2.2K 2 CLK26M DVDD18_IO3 L25 RTC32K_CK R223 R224 2 UTXD1 URXD1 AF26 [3] WATCHDOG_B [2,12] [2,12] UTXD0 URXD0 1K 2 R210 2 R212 1K 1 1 U201-C [2,4,13] SCL1 [2,4,13] SDA1 [17] KCOL0 KROW1 [29] CLK1_BB RTC32K_CK [18] MIPI_RDP2 MIPI_RDN2 [13] CMDAT5 [13] CMDAT4 [14] [4] KROW0 KCOL1 T201 [3] EINT17_IDDIG MC1INSI [15] T204 VIO18_PMU [12] [18] MT6290_GPIO17 [24] [2,18] SCL2 [2,18] SDA2 MIPI_RCP MIPI_RCN MIPI_RDP0 MIPI_RDN0 MIPI_RDP1 MIPI_RDN1 C208 1 1 EINT18_HP [5] R218 2.2K R217 2.2K 2 2 MIPI_TDP3 MIPI_TDN3 T206 M3 M4 M1 M2 P2 N2 P1 R1 N5 M5 EMMC_RST EMMC_CMD EMMC_CLK EMMC_DAT0 EMMC_DAT1 EMMC_DAT2 EMMC_DAT3 EMMC_DAT4 EMMC_DAT5 EMMC_DAT6 EMMC_DAT7 MC1CM MC1CK [15] [15] MC1DA0 MC1DA1 MC1DA2 [15] [15] [15] [6] [6] [6] [6] [6] [6] [6] [6] [6] [6] [6] MC1DA3 [15] MC2CM [21,23] MC2CK [21,23] MC2DA0 [21,23] <TITLE> TITLE: MC2DA1 [21,23] MC2DA2 [21,23] DOCUMENT NO.: MC2DA3 [21,23] DEPARTMENT: REV: 02_MT6582_BASEBAND <REV> SIZED: A1 Hardware DEPT. COMPANY: DESIGNER: <DESIGNER> Last Saved Date: 2014-7-30 SHEET: 2 OF 33 Regulator Output Voltage(V) Input Decoupling Output Decoupling VPROC 0.7~1.4 2800 >10uF L=0.68uH,C=10uF*4 VSYS 2.2 1200 >10uF L=0.68uH,C=10uF*2 Total outptu cap>20uF VPA 0.5~3.4 600 >4.7uF L=2.2uH,C=2.2uF+2.2uF Output cap range 4.4uF +/-20% LDO Output Voltage(V) VM 1.24 VRF18 1.825 VIO18 1.8 VCN18 1.8 VCAMD 1.2 VCAM_IO 1.8 VGP3 1.2 VA VTCXO VCN28 Output Current(mA) Total outptu cap>40uF Input Decoupling Output Decoupling 700 10uF -20%~+20% Far-end bypass cap 200 1uF -20%~+200% Far-end bypass cap -20%~+200% Far-end bypass cap Output Current(mA) /1.39/1.54/1.84 Notes 300 4.7uF Notes 120 1uF -20%~+20% 150 1uF -20%~+20% Far-end bypass cap 100 1uF -20%~+20% Far-end bypass cap 200 1uF -20%~+20% Far-end bypass cap 2.8 150 1uF -20%~+20% Far-end bypass cap 2.8 40 1uF -20%~+20% Far-end bypass cap 2.8 30 1uF -20%~+20% Far-end bypass cap VCAMA 2.8 -20%~+20% 1uF near-end 3.3/3.4/3.5/3.6 150 240(MT6323) 350(MT6322) 3.2uF VCN33 4.7uF -20%~+20% Far-end bypass cap VIO28 2.8 200 2.2uF -20%~+200% Far-end bypass cap /1.3/1.5/1.8 /1.3/1.5/1.8 Far-end bypass cap ,2.2uF Far-end bypass cap 20 1uF -20%~+20% Far-end bypass cap VMC 1.8 /3.3 100 1uF -20%~+20% Far-end bypass cap VMCH 3.0 /3.3 400 2.2uF -20%~+20% Far-end bypass cap VEMC_3V3 3.0 /3.3 1.2/1.3/1.5/1.8 2.8/3.0/3.3 400 4.7uF -20%~+20% 100 1uF -20%~+20% Far-end bypass cap 50 1uF -20%~+20% Far-end bypass cap 50 1uF -20%~+20% Far-end bypass cap VUSB VCAM_AF 3.3 /2.0 VSIM1 1.8 VSIM2 1.8 /3.0 1.2/1.3/1.5/1.8/2.0 2.8 /3.0/3.3 1.2/1.3/1.5/1.8/2.0 2.5 /2.8/3.0 1.2 /1.3/1.5/1.8/2.0 2.8/3.0/3.3 1.8 2.8 VGP1 VGP2 VIBR VDIG18 VRTC /3.0 Far-end bypass cap 100 1uF -20%~+20% Far-end bypass cap 100 1uF -20%~+20% Far-end bypass cap 100 1uF -20%~+20% Far-end bypass cap 20 2 1uF 0.1uF to 1000uF -20%~+20% -20%~+20% Far-end bypass cap Far-end bypass cap U301 Before you select BJT , please take power dissipation into consideration. Refer to MT6323 design notice BGA145-5.8X5.8-0.4E0.25B(MT6323) C313 VBAT_SPK L2 GND_SPK F2 G2 AU_MICBIAS0 AU_MICBIAS1 [5] AU_VIN0_P [5] AU_VIN0_N E4 F4 AU_VIN0_P AU_VIN0_N [5] AU_VIN1_P [5] AU_VIN1_N G3 G4 AU_VIN1_P AU_VIN1_N D2 D1 AU_VIN2_P AU_VIN2_N J2 D3 H2 AVDD28_ABB AVDD28_AUXADC GND_ABB E2 ACCDET E1 CLK26M P13 P12 K3 A12 M13 BATSNS ISENSE BATON VCDT VDRV 2.2uF MICBIAS0 C312 1.0uF MICBIAS1 VBUS VA_PMU 1.0uF C327 CHR_LDO [2,4,21,29] SRCLKENA FCHR_ENB[3] FCHR_ENB[3] A2 M1 SRCLKEN FCHR_ENB D9 B7 D8 B8 SPI_CLK SPI_CSN SPI_MOSI SPI_MISO T301 [2] [2] [2] [2] 16.9K PMIC_SPI_SCK PMIC_SPI_CS PMIC_SPI_MOSI PMIC_SPI_MISO 40mil 30mil (4mil if VPA no use) VBAT C330 10uF_NF 22uF C310 20mil VBAT VBAT VBAT 20mil 20mil VSYS_PMU AUXADC_REF AUXADC_TSX GND_AUXADC GND_AUXADC C323 100nF 1.0uF AUXADC_TSX HT301 1uF C308 1uF C307 10uF 10uF 1.0uF C304 Connect TSX/XTAL GND to AUXADC_GND first than connect to main GND HT302 C306 L303 0.68UH VSYS_PMU H13 P8 P6 P5 P2 VBAT_VSYS VBAT_LDOS3 VBAT_LDOS3 VBAT_LDOS2 VBAT_LDOS1 VA M3 VA_PMU N3 L4 VCN_2V8_PMU VTCXO_PMU P3 M6 C3 VCAMA_PMU VCN_3V3_PMU VRTC DVDD18_DIG A5 DVDD18_IO J13 H11 L12 M4 J12 K14 L13 1.0uF DVDD12_EMI VRF18_PMU VIO18_PMU VIO28_PMU P7 L6 P4 N6 P9 N9 L8 VEMC_3V3_PMU VMC_PMU VMCH_PMU VUSB_PMU VSIM1_PMU VSIM2_PMU VGP1_PMU VIBR VGP2 VGP3 VCAM_AF M7 N8 L14 N7 VGP3_PMU VCAM_AF_PMU VIBR_PMU VREF P14 GND_VREF N14 RTC_32K1V8 RTC_32K2V8 XIN XOUT D5 C4 A3 A4 GND_ISINK GND_VSYS GND_VPA GND_VPROC GND_VPROC GND_VPROC B10 G11 E13 E11 F11 F10 CHG_DM CHG_DP SIM LVS B5 M11 E6 SIM1_AP_SCLK SIMLS1_AP_SIO SIM1_AP_SRST C5 K11 D6 SIM2_AP_SCLK SIMLS2_AP_SIO SIM2_AP_SRST SCLK SIO SRST M9 N11 M10 SIMLS1_SCLK SIMLS1_SIO SIMLS1_SRST SCLK2 SIO2 SRST2 K9 L11 K10 SIMLS2_SCLK SIMLS2_SIO SIMLS2_SRST VGP2_PMU VREF AUXADC_VREF18 AUXADC_AUXIN_GPS AVSS28_AUXADC SIM2_SCLK SIM2_SIO SIM2_SRST 0.47uF VCN18_PMU VCAMD_PMU VCAMD_IO_PMU VEMC_3V3 VMC VMCH VUSB VSIM1 VSIM2 VGP1 AUXADC SIM1_SCLK SIM1_SIO SIM1_SRST DVDD12_EMI VA_PMU dedicate VSS ball, must return to cap then to main GND: 1. GND_VREF(N14) => C320 RTC GND_LDO GND_LDO K6 K8 GND_LDO GND_LDO GND_LDO GND_LDO GND_LDO GND_LDO GND_LDO F5 F6 F7 F8 F9 G5 G6 HT305 RTC32K_CK 32K_IN 32K_OUT RTC X301 [2] RTC 32K : X301+C324+C319=> mount, R333=> NC 32K-less: X301+C324=> remove, C319+R333=> 0R 1 2 XTAL-32.768K-KYOCERA Close to chip DCXO_32K J10 J9 J8 J7 J6 H10 H9 H8 H7 H6 H5 G9 G8 G7 refer to system analog LDO performance improve proposal A10 A11 VEMC_3V3_PMU C331 100nF VM VRF18 VIO18 VIO28 VCN18 VCAMD VCAM_IO AVDD22_BUCK AVDD22_BUCK A8 C2 B1 B2 NF BC 1.1 [2] CHD_DM [2] CHD_DP C322 must to be close to PMIC AUXADC_TSX pin C309 C350 4.7uF 4.7uF C303 10uF Based on your system level design , if better EOS performance is needed on your system, please refer to EOS performance enhance proposal C305 0.01uF C339 VR305 MT6323 1K VIBR_PMU 22uF 3 2 VIB-GS-2701 CON301 NP 1 C325 Refer to GPS co-clock layout rule 1uF Vibra R312 VRTC Refer to MT6323 design notice for Buck GND layout rule C311 R305 100K 1K 10uF C301 BAT_ID_ADC [2] VPA for WCDMA NF VCN28 VTCXO C320 AUXADC_REF CLOSE Batconnector 1 R301 VPA_PMU VCAMA VCN33 AVDD33_RTC GND_LDO GND_LDO GND_LDO GND_LDO GND_LDO GND_LDO GND_LDO GND_LDO GND_LDO GND_LDO GND_LDO GND_LDO GND_LDO GND_LDO [3] Refer to MT6323 design notice for Zener selection 47K ALDO OUTPUT VBAT INPUT C322 Between IC and IO port e c i t o n n g i s e d W H 3 2 3 6 T M o t r e f e R R302 TP-1.0MM TP305 if battery NTC is 10kohm, R334=16.9K, R335=27K if battery NTC is 47kohm, R334=61.9K, R335=100K VSYS_SW C358 DVDD18_DIG_PMIC VIO18_PMU VIO18_PMU Based on your system level design , if better ESD performance is needed on your system, please refer to ESD performance enhance proposal H14 VPROC_FB [1,4] GND_VPROC_FB[1] NF VPA_SW C355 VBAT_VPROC VBAT_VPROC VBAT_VPROC VBAT_VPA VF : 4.85V~5.36V VIO18_PMU VSYS C356 C357 DLDO OUTPUT F13 F14 G13 A13 J14 M14 20mil 2 1 Add Zenar Diode500mW Place on the path from VBAT to IC (Battery connector or test point or IO connector) D302 27PF R335 C335 27K VR302 VR301 R334,R335 must to be close to PMIC AUXADC_REF pin VBAT 20mil 1K D12 1.0uF 2 1 R334 1 1 1 1 R317 5 6 BATTCON-R6593004-20005A A14 B14 C332 AUD_MOSI AUD_CLK AUD_MISO VBAT 80mil VPROC_PMU VPROC_PMU[1,3,4] 0.68UH 470nF PMU_TESTMODE E7 E8 B6 [3] VBAT VBAT [3,4,12,21,22,30,31] BAT_ON [3] B12 C12 VPA VPA VPA_FB L301 C353 N2 [2] AUD_DAT_MOSI [2] AUD_CLK [2] AUD_DAT_MISO 40mils 40mils VPROC_FB GND_VPROC_FB VPROC_SW C354 [2] EINT_PMIC [4] EXT_PMIC_EN AUXADC_REF[3] VA_PMU 0 BATSNS[3] 4mil 1% PWRKEY SYSRSTB RESETB FSOURCE INT EXT_PMIC_EN C14 D14 E14 C319 WATCHDOG_B [2] SYSRST_B ISENSE[3] HT304 1 2 3 4 CHRLDO M2 A1 K4 A9 A7 N12 100PF 1.0uF 1.0uF C317 [2] 1K R303 16.9K 1% BATTERY CONNECTOR CON302 N13 VPROC VPROC VPROC 18PF 1 R328 HT303 Differential AUXADC_REF C356，C357，C358，BUCK电路输出端的小电容 请选择耐压值10V以上的 CONTROL SIGNAL R316 [17] PWRKEY Close to PMIC 4mil 0.02 SR0805 [3] CHR_LDO C302 C316 CHR_LDO[3] 40mils TP-1.0MMTP-1.0MM TP312 TP313 [5] [5] LED_RED LED_GREEN LED_BLUE ISINK3 Please use inductor recommand by MTK Refer to MT6323 design notice BUCK OUTPUT CHARGER BATSNS ISENSE BAT_ON VCDT VDRV BAT_ON[3] VCDT[3] VDRV[3] ISENSE_R [4] TP-1.0MM TP-1.0MM TP309 TP310 TP-1.0MM TP311 E9 C9 E10 C10 C324 CHR_LDO[3] 40mils [3] VDRV [5] ACCDET CLK_26M_MT6323 [29] ISENSE/BSTSNS 4mil [6] BATSNS[3] differential to Rsense ISENSE[3] R331 3.3K 40mils AU_HSP[5] AU_HSN[5] AU_HPL AU_HPR 100nF C329 1uF 10 D POWER-NFET+PNP-MI5809 4 8 7 9 C C C D G 5 S B 6 2 3 E U302 C 1 40mils Rsense ISINK0 ISINK1 ISINK2 ISINK3 DRIVER AU_SPKP[5] AU_SPKN[5] VCDT rating: 1.268V R324 39K 40mils H4 J4 100nF VCDT[3] H1 G1 AU_HPL AU_HPR 18PF R329 330K AU_VIN2_P AU_VIN2_N 1.0uF C326 VA_PMU 1. Close to Battery Connector. (Rsense (R328) <10mm) 2. Main path should be 40mil. (VBUS -> U303's E, -> U303's C -> R328 -> VBAT) 3. Star connection from R328 to BAT Connector cap rating depends on Phone OVP spec. AUDIO K1 L1 AU_HSP AU_HSN C333 VBAT Charger SPK_P SPK_N P1 4.7uF VBAT ==> for longer RTC time sustain after battery remove, please refer to RTC design notice <TITLE> TITLE: DOCUMENT NO.: REV: 03_MT6323_PMIC_AUDIO <REV> SIZED: A1 Hardware DEPT. DEPARTMENT: COMPANY: DESIGNER: <DESIGNER> Last Saved Date: 2014-7-30 SHEET: 3 OF 33 当使用Switching charger :Rsense R328 use 56m ohm VBUS VBUS_1 GND VBAT [3,4,12,21,22,30,31] GND I2C Address FAN53555 : 0xC0 NCP6335D: 0x1C VBUS_1 U302 placement, please be close to MT6322 L307 placement, please be close to L301 VBAT [10] ANT_SEL1 40mil GND [2,4,13] SDA1 GND [2,4,13] SCL1 [2] GPIO_CHG_EN ISENSE_R [2] C337 must to be close to U302 [10] ANT_SEL2 40mil OTG-BOOST [4] GPIO93_DRVVBUS VPROC_PMU As short as possible and L307 as close as possible to L301, then connect to VPROC_PMU NC : FN5405/FN54015 10nF : BQ24153 ISENSE_R BATSNS_L 40mil VBAT [3,4] [3,4,12,21,22,30,31] [2,4,13] SDA1 [2,4,13] SCL1 VPROC_FB[1,3] VPROC_FB should be ground shielding. OTG-BOOST [4] GND GND GND FN5405 R410=10K,R412=NF, C402=NF FN5402 R410=NF, R412=10K,C402=NF BQ24158 R410=10K,R412=NF, C402=10nF GND GND If switching charger is used: (1) R1801~R1805, C1801~C1806, L1801, U1801 are needed (2) U303, U304 change to NC (3) R328 change to 56m Ohm External DC-DC for VPROC Switching Charger EXT_PMIC MT6333 switching charger function de-feature (Need to add external SWCHR) Change notice: Page 4 1. Delete R813/C839/U3/R817/R1812/C1815/R335 2. Change C1809 to 1uf 3. Add R341/C1810 for ESD protection 4. Delete ISENSE/BATSNS net 25V rating 5. Change C1806 location (close to MT6333) 6. Add U402 and related circuits MT6333 I2C Address: 0xD6, 0xD7 10V L1801 / L304 / L305 / L306 Please use inductor recommand by MTK Refer to MT6333 design notice 25mil 40mil 40mil 40mil 25mil 40mil VLED 40mil 40mil VBAT 40mil VIO18_PMU 25mil Close to L1801 [2] BUCK1_SW EINT0_MT6333 BUCK1_FB Need pull-up resistor to VIO18 [2,4,13] SCL1 [2,4,13] SDA1 [2,3,21,29] SRCLKENA [3] VM12_SW_PMU BUCK1_FB [1,4] BUCK2_SW VCORE_SW_PMU EXT_PMIC_EN VCORE_SW_FB C338 / C339 are for VMEM_FB / VCORE_FB decoupling proposal. It can be cancel for cost-down proposal VRF_SW_PMU <TITLE> TITLE: DOCUMENT NO.: REV: 04_POWER_SWCHR_EXT_PMIC <REV> SIZED: A1 Hardware DEPT. DEPARTMENT: COMPANY: DESIGNER: <DESIGNER> Last Saved Date: 2014-7-30 SHEET: 4 OF 33 Earphone Audio same power domain close to IC close to connector VIO18_PMU C520 22uF 22uF R507 R508 NF 100 R505 470K R506 47K BEAD501 [5] HP_MIC HP_MIC-1 1800ohm BEAD502 HP_MP3L HP_MP3R AUDIO-EAR-PJES-050-1-G-BLK [5] HP_MP3L-1 1800ohm BEAD505 100 3 1 2 [5] HP_MP3L-1 [5]FM_ANT-1 [5] HP_MIC-1 1800ohm FM_ANT-1 6 5 4 [5]HP_MP3R-1 [5]EAR_DET [5] EAR_DET [5] HP_MP3R-1 [5] [5] VR501 470 470 R530 R531 C505 100PF 2 0 1 C506 CON501 CON503 AUDIO-RECIEVER-1506-S3001/11.5 C522 [3] AU_HSN[3] R521 1800ohm C519 C521 R520 BEAD504 1800ohm 33PF close to connector 33PF close to IC [3] AU_HSP[3] [3] AU_HPR VR502 Receiver BEAD503 33PF [3] AU_HPL NF Based on your system level design , if better desense performance is needed on your system , please refer to desense performance enhance proposal C553 Reserve bead+C footprint for FM performance tuning C552 [2] EINT18_HP R501 1 33PF C504 0 FM_ANT[10] 2.5Kohm VR506 VR505 1 VR504 VR503 Based on your system level design , if better ESD performance is needed on your system, please refer to ESD performance enhance proposal 2 0 L502 R502 2 FM_RX_N_6572[10] 0 1 PAD-2.0X2.0SS XJ503 1 PAD-2.0X2.0 XJ504 1 1 XJ502 XJ501 Single via to GND plane 220ohm AU_SPKP SPK_P BEAD506 C503 100PF [3] 小板喇叭 220ohm [3] AU_SPKN SPK_N VR510 33PF VR511 C501 33PF C502 BEAD507 MICBIAS1 1K Earphone MICPHONE 100nF R511 Close to MIC AU_VIN1_N1 C554 100PF C525 C526 C560 100nF 33PF Handset Microphone 1 [3] ACCDET GND of C(4.7uF) and headset should tie together and single via to GND GND plane Close to EarJack C551 33PF HP_MIC R519 [3] AU_VIN1_P 4.7uF R518 1.5K C550 1K Close to BB [3] AU_VIN1_N [5] together then single via to main GND 1 1 Analog MIC CON502 C511 R522 0 1 R523 0 2 AUDIO-MIC-SMT4013-PRJ7665 VR509 33PF 1.5K 33PF R516 1K if you use digital MIC, please change cap (C511,C512) to 1.0uF R517 100nF C509 4.7uF C512 C508 100PF C513 100nF [3] AU_VIN0_N Analog MIC C510 AU_VIN0_P Close to MIC Close to MIC 1.5K R515 Close to BB [3] TP-1.0MM TP501 TP-1.0MM TP502 VR508 1K R532 MICBIAS0 together then single via to main GND <TITLE> TITLE: REV: 05_AUDIO DOCUMENT NO.: <REV> SIZED: A1 Hardware DEPT. DEPARTMENT: COMPANY: DESIGNER: <DESIGNER> Last Saved Date: 2014-7-30 SHEET: 5 OF 33 eMMC+LPDDR2 162 Ball, 0.5mm pitch 0 R618 DVDD18_EMI VIO18_PMU VDD1=1.8V VDD2=1.20V VDDCA=1.2V VDDQ= 1.20V VDD1 : Core 1 DVDD18_EMI F6 F9 G10 H10 J5 K10 M5 P10 R5 T10 U10 V6 V9 GND VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ T1 M1 H1 VSSCA VSSCA VSSCA B9 E1 F2 F5 G1 L2 M8 U1 V2 V5 C3 VSSM VSSM VSS VSS VSS VSS VSS VSS VSS VSS VSSQM A1 A2 A9 A10 B1 B10 E10 W1 W10 Y1 Y2 Y9 Y10 DNU DNU DNU DNU DNU DNU DNU DNU DNU DNU DNU DNU DNU LP-DDR2 C631 C642 2.2uF J1 L1 T2 VCC VCC VCCQ VDDI A8 B2 B8 A5 CLKM RST CMD B5 C1 C5 EMMC_CLK [2] EMMC_RST [2] EMMC_CMD [2] DAT7 DAT6 DAT5 DAT4 DAT3 DAT2 DAT1 DAT0 B4 A4 A6 B6 A7 B7 B3 A3 EMMC_DAT7 EMMC_DAT6 EMMC_DAT5 EMMC_DAT4 EMMC_DAT3 EMMC_DAT2 EMMC_DAT1 EMMC_DAT0 GND GND GND C601 100nF 100nF C629 GND C630 100nF C628 100nF C627 100nF 2.2uF GND VDDCA VDDCA VDDCA GND 4.7uF GND C640 F7 F10 G5 H9 J10 L6 M6 N6 R10 T9 U5 V7 V10 DVDD12_EMI GND 1. VCC : Core Voltage 2.7v ~ 3.6v 2. VCCQ : IO Voltage 1.7v~1.95v (low voltage range) R612 EMMC_VCC VEMC_3V3_PMU 0 CS0# CS1# P1 P2 CKE0 CKE1 N1 N2 ECKE ECKE ECKE[2,6] ECKE[2,6] EDCLK EDCLK_B EDCLK[2] EDCLK_B[2] [2] [2] [2] [2] [2] [2] [2] [2] ECS0_B[2] ECS1_B[2] CLK CLK# M3 L3 DQS0 DQS0# DQS1 DQS1# DQS2 DQS2# DQS3 DQS3# P6 P5 K6 K5 U8 U9 G8 G9 EDQS0[2] EDQS0_B[2] EDQS1[2] EDQS1_B[2] EDQS2[2] EDQS2_B[2] EDQS3[2] EDQS3_B[2] DM0 DM1 DM2 DM3 N5 L5 T7 H7 EDQM0[2] EDQM1[2] EDQM2[2] EDQM3[2] VREFCA VREFDQ K3 M9 EVREF[2] NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC C2 C4 C6 D1 D2 D3 D4 D5 D6 E2 E3 M2 N3 P3 V3 W2 W3 VIO18_PMU 0 100nF 2.2uF C643 C637 0.22uF C624 4.7uF R613 C636 0 100nF EMMC_VCCQ R614 C634 ZQ0 ZQ1 eMMC VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDD2 : Core 2 C639 G3 F3 2 2 Power E5 G2 K1 M7 U2 W5 1uF DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 C623 T8 R8 R7 R9 R6 P7 P8 P9 K9 K8 K7 J6 J9 J7 J8 H8 W7 U6 W8 T5 U7 W9 V8 T6 H6 F8 E9 G7 H5 E8 G6 E7 E6 F1 V1 W6 GND GND GND GND GND Close to Memory Check MCP part's requirement 100nF ED0 ED1 ED2 ED3 ED4 ED5 ED6 ED7 ED8 ED9 ED10 ED11 ED12 ED13 ED14 ED15 ED16 ED17 ED18 ED19 ED20 ED21 ED22 ED23 ED24 ED25 ED26 ED27 ED28 ED29 ED30 ED31 R609 1 1 240 R610240 VDD1 VDD1 VDD1 VDD1 4.7uF CA0 CA1 CA2 CA3 CA4 CA5 CA6 CA7 CA8 CA9 C641 U3 T3 R3 R2 R1 K2 J2 J3 H3 H2 C638 GND EA0 EA1 EA2 EA3 EA4 EA5 EA6 EA7 EA8 EA9 100nF U601 GND GND Hynix H9TP32A4GDMCPR;Micron MT29PZZZ4D4TKETF-25 BGA162-12X13.5-0.5PB0.27(H9TP32A8JDMCPR) <TITLE> TITLE: DOCUMENT NO.: REV: 06_MEMORY_EMMC_LPDDR2 <REV> SIZED: A1 Hardware DEPT. DEPARTMENT: COMPANY: DESIGNER: <DESIGNER> Last Saved Date: 2014-7-30 SHEET: 6 OF 33 <TITLE> TITLE: DOCUMENT NO.: REV: 07_RF_MT6166_TXVR_2G_B34_B39 <REV> SIZED: A1 Hardware DEPT. DEPARTMENT: COMPANY: DESIGNER: <DESIGNER> Last Saved Date: 2014-7-30 SHEET: 7 OF 33 <TITLE> TITLE: DOCUMENT NO.: REV: 08_RF_MT6166_WCDMA <REV> SIZED: A1 Hardware DEPT. DEPARTMENT: COMPANY: DESIGNER: <DESIGNER> Last Saved Date: 2014-7-30 SHEET: 8 OF 33 <TITLE> TITLE: DOCUMENT NO.: REV: 09_RF_MT6166_B40 <REV> SIZED: A1 Hardware DEPT. DEPARTMENT: COMPANY: DESIGNER: <DESIGNER> Last Saved Date: 2014-7-30 SHEET: 9 OF 33 X1001 XTAL-CRYSTAL-26M-7L26002009 3 OUTPUT VCC GND GND 4 VCN_2V8_PMU U201-F WB_RSTB AVDD18_WBG XIN_WBG AE4 AD6 GPS_RXQN GPS_RXQP GPS_RXIN GPS_RXIP AF5 AG5 AG4 AF4 WB_SCLK WB_SDATA WB_SEN WB_TXQN WB_TXQP WB_TXIN WB_TXIP AF2 AG2 AF1 AE1 WB_TX_QN WB_TX_QP WB_TX_IN WB_TX_IP WB_CRTL0 WB_CRTL1 WB_CRTL2 WB_CRTL3 WB_CRTL4 WB_CRTL5 WB_RXQN WB_RXQP WB_RXIN WB_RXIP AE2 AD2 AC2 AC1 WB_RX_QN WB_RX_QP WB_RX_IN WB_RX_IP ANT_SEL0 ANT_SEL1 ANT_SEL2 AB25 AC26 AC25 WB_RSTB 1.0uF Y10 AA10 F2W_DATA F2W_CLK WB_SCLK WB_SDATA WB_SEN AG7 AF7 AE6 WB_CTRL0 WB_CTRL1 WB_CTRL2 WB_CTRL3 WB_CTRL4 WB_CTRL5 Y6 AA6 AA5 AA4 AB5 AB4 FM_DATA FM_CLK SYSCLK_WCN WIFI/BT/GPS Single ANT Ref. AF6 1 C1022 2 [10] XO_IN 50 Ohm NF L1020 3 NF 2 GND GND GND OUT [10] WB_CTRL0 [10] HT1004 21 WB_TX_IP 18 [10] AVDD18_WB HT1002 [10] AVDD18_GPS HT1003 WB_TX_IN 17 WB_TX_IN [10] WB_TX_QP 16 WB_TX_QP [10] WB_TX_QN 15 WB_TX_QN [10] U1000 50 Ohm MQFN40-5X5-0.4E(MT6627) VCN_2V8_PMU_FM [10] 39 C1008 100PF 钢网做屏蔽处理 GPS_RX_IP 14 GPS_RX_IP GPS_RX_IN 13 GPS_RX_IN [10] GPS_RFIN GPS_RX_QP 12 GPS_RX_QP [10] 40 AVDD18_GPS GPS_RX_QN 11 41 DVSS [10] [10] 600ohm MT6627 SMD QFN40 Close to MT6627 1.0uF C1025 GPS-LNA-RDALN16 0.01uF C1002 XO_IN SEN SDATA SCLK F2W_CLK F2W_DATA FM_DBG CEXT 9 ANT_SEL0 0 8 R1032 4 7 HT1001 2.2uF C1041 0.22uF VCN_3V3_PMU C1040 NF [10] FM_DATA VCN_2V8_PMU XO_IN [10] 4.7uF C1028 C1020 C1012 R1002 0 WB_RSTB [10] C10111.0uF100PF [10]AVDD33_WB 100PF C1003 5 NF C1030 R1010 6 6 VDD 5 EN RFIN NF L1032 RFOUT GND HRST_B GND VCN_2V8_PMU C1004 100PF 3 FB1010 4 2 9.1nH refer to FM desense performance enhance proposal GPS_RX_QN [10] VCN_2V8_PMU_FM 10 L1001 33PF 1 1 C1031 4 0 3 50 Ohm 2 L1012 100NH U1004 GND FM_LANT_P 91NH U1002 GND FM_LANT_N VCN18_PMU Star Conn for WB/GPS/WBG 1V8 FM_LANT_P 91NH AVDD18_GPS [10] 5 37 38 FM_RX_N_6572 L1011 FM_ANT 82nH OUT AVDD28_FM AVDD28_FSOURCE [5] 36 VCN18_PMU WB_TX_IP [10] 1.0uF NC WB_RX_QN [10] C1006 NC 35 WB_RX_QP [10] 19 100nF 34 20 C1007 23 24 22 WB_RX_IN WB_RX_IP WB_CTRL0 25 AVDD33_WBT WB_RX_QP WB_RX_QN 1nF 33 AVDD33_WB [10] GPS_DPX_RFOUT C1005 Based on your system level design , if better WiFi TX performance is needed on your system, please refer to WiFi performance enhance proposal WB_GPS_RF_IN WB_CTRL1 31 WB_CTRL2 RF-SAW-DP1608-V1524CAT 27 WB_RX_IN [10] 26 1 18PF 50 Ohm 32 [5] FM_RX_N_6572 VCN18_PMU [10]AVDD18_WBG 2 C1026 WB_CTRL3 3 28 GPS WB_CTRL4 GND 29 GND 4 WB_RX_IP [10] WB_CTRL5 ANT 2 30 L1015 [10] WB_CTRL1 Close to MT6572 5 4 5 NF L1004 [10] [10] WB_CTRL5 50 Ohm GND T1003 [10] WB_CTRL4 [10] AVDD18_WB R1005 NF C1042 2 1 1 AVDD18_WBT 1 WIFI WB_CTRL3 WB_CTRL2 IN GND 3 T1001 U1003 W_LNA_EXT 2 R1006 NF 1 GND RF-SAW-885033 L1031 0 0 2 [10] ANT_SEL1 ANT_SEL2 1 1 6 IN ANT_SEL0 T1002 ANT_SEL0 ANT1002 U1007 1 C1046 GPS_RX_QN GPS_RX_QP GPS_RX_IN GPS_RX_IP Debug usage MT6592 ANT1001 AVDD18_WBG XO_IN 100nF 0 R1013 [3,10] [10] FM_CLK Based on your system level design , if better GPS performance is needed on your system, please refer to GPS performance enhance proposal [10] WB_SCLK [10]WB_SDATA [10] WB_SEN <TITLE> TITLE: DOCUMENT NO.: REV: 10_WIFI_BT_GPS_FM_MT6627 <REV> SIZED: A1 Hardware DEPT. DEPARTMENT: COMPANY: DESIGNER: <DESIGNER> Last Saved Date: 2014-7-30 SHEET: 10 OF 33 NFC <TITLE> TITLE: REV: 11_NFC DOCUMENT NO.: <REV> SIZED: A1 Hardware DEPT. DEPARTMENT: COMPANY: DESIGNER: <DESIGNER> Last Saved Date: 2014-7-30 SHEET: 11 OF 33 TP-1.0MM TP-1.0MM TP1203 TP1202 TP-1.0MM TP1206 TP-1.0MM TP1201 默认3*3封装 <=8LEDs，可换2520封装 VBAT CTP 1 FB1201 GND [2] EINT14_CTP_RST [2] [3,12] R1218 CTP_EINT_CTP [2] VGP1_PMU 0 R1206 SDA0 [12] 6 GND GND 2 R1202 CTP_SDA_1 [12] SCL0 CTP_SCL_1 [12] 4 2 1nF VR1205 1 C1215 1nF VR1204 2 1 C1207 2 1 0.1uF VR1203 NF VR1202 2 1 C1212 GND NC/OVP/VOUT EN FB 600ohm 1 C1238 5 CTP_SCL_1 CTP_SDA_1 [12]LCD_CABC 4 GND 50V 1uF 3 C1239 47PF GND GND R1208 100K LEDK R1203 3 VGP1_PMU [12] NF 2 CTP_EINT_CTP [12] NF 1 CTP_GPIO_CTP_RSTB [3,12] C1214 NF 2 VR1201 C1213 1 GND GND LED-DRIVER-ET5119A R1212 [12] SW VIN 0 J1201 [12] LEDA [12] U1201 2.2uF [12] [3,12] [2] PWM 0 R1204 [2] FB1202 C1233 CTP_GPIO_CTP_RSTB 1K R1217 EINT2_CTP VGP1_PMU D1201 10uH 30ohm VIO18_PMU 1K C1222 VIO18_PMU L1201 1 1 1 1 10K_NF 1 R1205 C1224 [12] 47PF TP-1.0MM TP-1.0MM TP1205 TP1204 7.5 5 6 GND GND GND ZIF-04-6298-006-000-883+ GND GND GND Backlight LED Driver Main LCM LEDA [12] 47PF C1203 ZIF-FH26-25S-0.3SHW GND 27 26 1K R1207 25 24 100PF [2] LCD_ID_ADC 23 C1209 [12] 22 LEDK 21 [12] 20 LEDA 19 18 R1216 VIO28_PMU R1215 0 17 0 16 VIO18_PMU 15 GND EMI1207 [2] MIPI_TCP [2] MIPI_TCN [2] MIPI_TDP1 [2] MIPI_TDN1 1 4 2 3 EMI1208 [2] MIPI_TDP0 [2] MIPI_TDN0 1 4 2 3 [2] LPTE R1201 33 14 13 C1205 C1206 100nF 100nF LRSTB C1208 100nF [2] 12 [12] LCD_CABC LCD_CABC 11 10 9 8 EMI1209 7 1 4 6 2 3 5 4 3 2 1 J1202 <TITLE> TITLE: DOCUMENT NO.: REV: 12_LCD_CTP_SIDEKEY <REV> SIZED: A1 Hardware DEPT. DEPARTMENT: COMPANY: DESIGNER: <DESIGNER> Last Saved Date: 2014-7-30 SHEET: 12 OF 33 J1301 NF C1319 NF GND [2,4] R1306 1.0uF 28 26 27 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 GND NF NF 100PF C1307 C1342 GND [13] CMDAT1-1 [13] CMDAT3-1 [13] CMDAT4-1 14 12 CMDAT2-1 CMDAT0-1 15 11 CMDAT7-1 [13] NF 0 C1308 R1310 1.0uF R1311 C1310 VCAMD_PMU [13] CMHSYNC-1 C1305 [13] [13] CMDAT5-1 [13] CMDAT6-1 13 VLED [13] CMPCLK-1 CMMCLK_BTB ELCH07-5070J5J7293910-N0 [13] [13] BTBS-BBR43-24KBJ03 [2] EINT9_MAINCAM_RST [2] EINT10_CMPDN [2] [2] 1 5 2 CMVSYNC CMHSYNC 6 3 7 4 8 CMVSYNC-1 [13] EINT10_CMPDN-1 CMHSYNC-1 [13] [13] 10 EMI1301 EINT9_MAINCAM_RST-1 [13] EMI-ICVE10184E070R101FR GND R1302 CMPCLK-1 [13] 0 NF C1302 9 CMPCLK [2] [2] CMDAT7 [2] CMDAT6 [2] CMDAT5 [2] CMDAT4 1 5 2 6 3 7 4 8 [13] [13] CMDAT5-1 [13] CMDAT4-1 [13] 10 EMI1302 CMDAT7-1 CMDAT6-1 EMI-ICVE10184E070R101FR 0 CMMCLK CMMCLK_BTB [13] R1301 9 C1301 [2] OCP8111 R1315=68K R1317=0.22 OCP8110 R1315=82K R1317=0.47 NF [2] CMDAT3 [2] CMDAT2 [2] CMDAT1 [2] 1 5 2 CMDAT0 EMI1303 6 3 7 4 8 CMDAT3-1 [13] CMDAT2-1 [13] CMDAT1-1 [13] CMDAT0-1 [13] FLASH LED 10 VCAMD VCAM_IO VCAMD_IO_PMU GND 0 [13] EINT10_CMPDN-1 NF 0 [13] CMVSYNC-1 100PF VGP3_PMU [13] EINT9_MAINCAM_RST-1 C1309 [3] SCL1 C1306 R1325 [2,4] 1.0uF C1320 0 C1304 1.0uF VCAMA_PMU C1318 VCAMA SDA1 25 9 R1330 VCAM_AF_PMU EMI-ICVE10184E070R101FR MAIN_camera light sensor 0x90 Write(STK3171) light sensor 0x46 Write (LTR-558ALS) Main Camera / Sub Camera share power domain design should double check the voltage level is compatible <TITLE> TITLE: REV: 13_CAMERA DOCUMENT NO.: <REV> SIZED: A1 Hardware DEPT. DEPARTMENT: COMPANY: DESIGNER: <DESIGNER> Last Saved Date: 2014-7-30 SHEET: 13 OF 33 USB HS IF TP-1.0MM TP1401 R1406 TP-1.0MM TP1404 1 1 1 3 1 2 J1401 R1407 R1405 VBUS 0 1 2 NF 3 4 [2] UTXD0 5 D1402 1 VR1401 1 D1401 C1405 2.2uF_NF 2 3 GND USB-UAF95-05254-S135-A-CUS GND 2 0_NF DIODE-ZENER-WZD58L6V2 R1402 2 1K EINT17_IDDIG 1 R1401 [2] ESD-TVS-ESD5342N VR1403 [2] USB_DP TP-1.0MM TP1403 4 VR1402 90 ohm differential 1 1 EMI1401 [2] USB_DM TP-1.0MM TP1402 TP-1.0MM TP1405 NF GND GND 华为项目请预留此二极管，有要求 1. 为方便软件调试打LOG，将UTXD0接至USB接口的Pin 4 ; 2. 如果有OTG功能， R708=0 欧姆 <TITLE> TITLE: REV: 14_USB DOCUMENT NO.: <REV> SIZED: A1 Hardware DEPT. DEPARTMENT: COMPANY: DESIGNER: <DESIGNER> Last Saved Date: 2014-7-30 SHEET: 14 OF 33 0 1 0 J1501 1 NF NF C1503 1 NF C1505 TP-1.0MM TP-1.0MM TP-1.0MM TP-1.0MM TP1501 TP1502 TP1503 TP1504 1 TP-1.0MM TP1515 0 R1501 1 2 2 1 1 R1503 2 1R1511 C1504 [21,22] LTE_USIMLV1_CLK [21,22] LTE_USIMLV1_RST [21,22] LTE_USIMLV1_DATA 25 28 26 27 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 VMCH_PMU 0 R1502 [2] MC1DA2 [2] MC1DA3 [2] MC1CM 0 R1507 0 10 15 R1504 0 R1508 0 11 14 R1505 0 R1509 0 12 13 R1506 0 0 R1512 [21,22] LTE_VSIM1 MC1INSI [2] R1510 SIM1 T卡clk需要保护 MC1CK [2] SD CARD MC1DA0 [2] MC1DA1 [2] TP1508 TP1507 TP1506 TP-1.0MM TP-1.0MM TP-1.0MM TP1505 TP-1.0MM 2.2uF C1502 1 1 1 NF NF C1511 NF C1510 C1509 1 1 1 1 1 NF C1506 NF NF C1507 C1508 1 1uF C1501 2 BTBS-BBR43-24KBJ03 TP1513 TP1512 TP1511 TP1509 TP-1.0MM TP-1.0MM TP-1.0MM TP-1.0MM GND T-card ESD protection is optional depends on T-card's type and position <TITLE> TITLE: REV: 15_DUAL_SIM DOCUMENT NO.: <REV> SIZED: A1 Hardware DEPT. DEPARTMENT: COMPANY: DESIGNER: <DESIGNER> Last Saved Date: 2014-7-30 SHEET: 15 OF 33 <TITLE> TITLE: DOCUMENT NO.: REV: 16_MEMORY_CARD <REV> SIZED: A1 Hardware DEPT. DEPARTMENT: COMPANY: DESIGNER: <DESIGNER> Last Saved Date: 2014-7-30 SHEET: 16 OF 33 KCOL1 R1704 1K R1701 1K R1702 1K KCOL0' [17] KCOL1' [17] KROW0' [17] HOLE-VIA2.4MM HOLE1701 TP-1.0MM TP-1.0MM TP1701 TP1702 1 1 1 1 [3,17] PWRKEY [17] KCOL1' KCOL1' [17] KROW0' KROW0' KCOL0' KCOL0' [17] HOLE-VIA2.4MM HOLE-VIA2.4MM HOLE1706 HOLE1705 HOLE-VIA2.4MM HOLE1703 1 TP-1.0MM TP-1.0MM TP1704 TP1703 1 KCOL0 [2] KROW0 1 [2] 1 [2] HOLE-VIA1.2MM HOLE1713 PWRKEY HOLE1712 1 1 1 C1730 1 PROOF1 ICO-WATERPROOF-D3 1 1 1 FIDUCIAL-MARK-1MM FIDUCIAL-MARK-1MM FIDUCIAL-MARK-1MM FIDUCIAL-MARK-1MM MARK1701MARK1702 MARK1703 MARK1704 GND 1 VR1704 HOLE-1.6MM 1 HOLE-1.6MM 100nF GND VR1706 VR1703 VR1702 1 PROOF1701 ICO-WATERPROOF-D3 HOLE-VIA1.2MM HOLE1714 PROOF1702 1 SN-23X5 HOLE-VIA1.2MM HOLE1716 HOLE1715 1 HOLE-1.2MM 1 1 Volume Up(KCOL1 KROW0) Volume Down(KCOL0 KROW0) HOLE-VIA2.4MM HOLE1702 HOLE1711 J1 [17] KCOL1' [3,17] PWRKEY 1 10 2 9 3 8 4 7 5 KCOL0' KROW0' [17] [17] 6 J1702 BTBS-AXQ1101GX1 1 2 3 4 4PIN-ZHIJIA-S96523A1-SC <TITLE> TITLE: REV: 17_KEY_LEDS DOCUMENT NO.: <REV> SIZED: A1 Hardware DEPT. DEPARTMENT: COMPANY: DESIGNER: <DESIGNER> Last Saved Date: 2014-7-30 SHEET: 17 OF 33 AUX_I2C_SDA [18] AUX_I2C_SCL [18] HALL 优选 VIO18_PMU VDDIO C1801 1uF 9 8 SDX SCK GND CSB PS GND 6 CAP0 C1813 GND SDO VDDD VDDA INT 1 2 12 R1803 0 R1804 0 10 5 EINT_ACC SENSOR-ACCELER-BMA220 GND SDA2 [2,18] SCL2 [2,18] 11 [2,18] GND BMA222E 8bit 优选 VIO18_PMU R1815 VIO18_PMU ALS+PS+IR 47K_NF EINT_ACC [2,18] BMA222E与BMA220的外围器件可以不用修改 M-Sensor Gyroscope *** VIO18_PMU VIO18_PMU GND VIO18_PMU GND GND VIO18_PMU VIO28_PMU EINT20_GY [2] [2,18] SCL2 [2,18] GND SDA2 GND AUX_I2C_SDA [18] GND AUX_I2C_SCL GND [18] GND GND GND VIO28_PMU [2] EINT6_M GND 0xD0 Write MPU6880 SDA2 [2,18] VIO18_PMU 1uF 4 7 0 GND U1801 3 R1801 GND SCL2 [2,18] ECOMPASS_I2C_SCL AD0=0 7b1101000 0x68 AD0=1 7b1101001 0x69 ECOMPASS_I2C_SDA 0x18 Write <TITLE> TITLE: REV: 18_SENSORS DOCUMENT NO.: <REV> A1 SIZED: Hardware DEPT. DEPARTMENT: COMPANY: DESIGNER: <DESIGNER> Last Saved Date: 2014-7-30 SHEET: 18 OF 33 ** * ** <TITLE> TITLE: DOCUMENT NO.: REV: 98_BLOCK_DIAGRAM ** * <REV> A1 SIZED: Hardware DEPT. DEPARTMENT: COMPANY: DESIGNER: <DESIGNER> Last Saved Date: 2014-7-30 SHEET: 19 OF 33 ** ** * Version History Date Version 2013/03/11 V0.1 2013/03/22 V0.11 Page 1. Add R107/R103 2. Delete R605/R107 03 1. Add R326/R328 04 1. Delete U1802 and related circuit 2. Add U401 and related circuit 06 1.Add R418 07 1.Delete R639/R634 10 1. Swap U2 (MT6627) pin 36, 37 and 38 and their circuitry. 2. Remove R1070, R1073 3. F201 change footprint to DIPLEXER/6P/SMD/DP1608 15 1. Change C1218,C1219 to 22pF, Change C1214,C1215 to 1.2pF, Change C1216,C1217 to 68pF , Change c1203 4.7uF 1 1. Remove C138, c153, C145. Change C140, C148 to 1u 3 789 2013/03/22 V0.12 Description Draft release 01 1 3 6 12 1. Add C353, R339, C243 2. Modify Isense trace. 1. Update RF matching (L615, L600, L619, L616, L622, C670, L623, L626, L625, C629, C627, C603, C662, C664, L617, C624, R617, C651, C655, C652, L610, C648, C657, L609, L608, L611, C649, C626, L607, R620, C634, L631, L627, L629, L636) 1. Add R360~R367, R101, R108, R105, R106, R109, R102, R104, R116, R117, R118, R115, R114, R113, R111 R418, R512, R513, R915, R916 for low-power testing 10 1. C222 change to 4.7uF 12 1. Add C914 / R904 <TITLE> TITLE: DOCUMENT NO.: REV: 99_VERSION_HISTORY <REV> A1 SIZED: Hardware DEPT. DEPARTMENT: COMPANY: DESIGNER: <DESIGNER> Last Saved Date: 2014-7-30 SHEET: 20 OF 33 ** BB PART MT6582 [2,21,23] MC2CK MC2DA3 MC2DA3 [2,21,23] [2,21,23] [2,21,23] MC2DA2 MC2DA1 MC2DA2 MC2DA1 [2,21,23] [2,21,23] [2,21,23] MC2DA0 MC2DA0 [2,21,23] AP_PCM_RX [2,21,24] AP_PCM_TX [2,21,24] AP_PCM_RX [2] [2] LTE_PMU_EN_P [2,21,25] LTE_AP_RSTB 0 R8001 UTXD2 URXD2 R8002 0 LTE_PMU_EN_P LTE_AP_RSTB [2,21,24] AP_WAKEMD_INT VBAT VBAT LTE_VSIM1 LTE_VSIM2 LTE_SUART1_RXD LTE_SUART1_TXD [24] [24] LTE_PMU_EN_P LTE_AP_RSTB [2,21,22] [2,21,25] EINT5_RSTB_FROM_LTE EINT7_SDIO_INTB_LTE EINT7_SDIO_INTB_LTE SRCLKENAI [2,21,24] AP_PCM_CK EINT5_RSTB_FROM_LTE [2] [2,21,24] AP_PCM_FSYNC AP_PCM_CK Johnson Yang 130627: LTE_32KIN эパ BPI_BUS14 矗ㄑ [2,21,22] [2,21,23] MC2CM [2,21,24] [2,21,23] [2,21,23] MC2CM [2,21,24] AP_PCM_TX [2,21,24] AP_PCM_FSYNC [2,21,25] MT6290M MC2CK [2,21,23] [2,21,23] [2,21,24] ** * LTE_SRCLKEN_OUT0 0 R8003 R8004 0 [2,21,25] [2,21,23] [22,26,29] LTE_VBAT_MT6339 VBAT LTE_VSIM1 LTE_VSIM2 From MT6339 to SIM2 LTE_USIMLV2_RST [21,22] LTE_USIMLV2_DATA [21,22] LTE_USIMLV2_CLK [21,22] [21,22] LTE_USIMLV2_RST [21,22] LTE_USIMLV2_DATA [21,22] LTE_USIMLV2_CLK From MT6339 to SIM1 [15,21,22] LTE_USIMLV1_CLK [15,21,22] LTE_USIMLV1_DATA LTE_USIMLV1_RST [21,24] LTE_CVJTCK [21,24] LTE_CVJTMS [21,24] [21,24] [15,21,22] LTE_USIMLV1_CLK LTE_USIMLV1_DATA [15,21,22] [15,21,22] [15,21,22] LTE_USIMLV1_RST LTE_CVJTCK LTE_CVJTMS [21,24] [21,24] LTE_MDUART_TXD LTE_MDUART_TXD LTE_MDUART_RXD LTE_MDUART_RXD [21,24] [21,24] AP to MT6169 RF PART VIO18_PMU VTCXO_PMU [2,3,4,21,29] 0 R8005 R8006 0 MT6169_VIO18_PMU MT6169_VTCXO_PMU [2,3,4,21,29] SRCLKENA SRCLKENA MT6165 RF PART [21] [21] [21] [21] [21] LTE_RFIC1_BSI_CK LTE_RFIC1_BSI_CK LTE_RFIC1_BSI_EN LTE_RFIC1_BSI_D2 LTE_RFIC1_BSI_D1 LTE_RFIC1_BSI_EN LTE_RFIC1_BSI_D2 [21] LTE_RFIC1_BSI_D1 [21] [21] LTE_RFIC1_BSI_D0 LTE_RFIC1_BSI_D0 [21] [21] LTE_2G_RX_BBIP LTE_2G_RX_BBIN LTE_2G_RX_BBQP LTE_2G_RX_BBIP [21] [21] [21] LTE_2G_RX_BBQN LTE_2G_RX_BBQN [21] MT6165_CLK1 LTE_VIO18_PMU LTE_VTCXO2 LTE_VRF18_2_PMU [21] [21] [21] LTE_2G_RX_BBIN LTE_2G_RX_BBQP [21] MT6165_CLK1 [21] [21] LTE_VIO18_PMU LTE_VTCXO2 LTE_VRF18_2_PMU <TITLE> TITLE: [21,26] LTE_SRCLKEN_OUT1 LTE_SRCLKEN_OUT1 [21,26] DOCUMENT NO.: REV: 80_AP_MD_I/F_CONNECTION <REV> A1 SIZED: Hardware DEPT. DEPARTMENT: COMPANY: DESIGNER: <DESIGNER> Last Saved Date: 2014-7-30 SHEET: 21 OF 33 ** I2C Address FAN53555 : 0xC0 NCP6335D: 0x1C ** * LTE_VBAT_MT6339 0 R8110 VBAT_BUCK 100K_NF VBAT LTE_SRCLKEN_IN1 B4 AGND AVIN D1 A2 EN A1 VSEL PVIN PVIN PVIN D2 E1 E2 B3 POWER_FAIL B2 INTERRUPT SW SW SW SW D3 D4 E3 E4 PGND PGND PGND PGND C1 C2 C3 C4 FB A4 R8108 0 [24] [24] LTE_I2C_SDA LTE_I2C_SCL B1 A3 SDA SCL NCP6335 / FAN53555 L8107 10uF EXT_VCORE_EN C8124 U8103 R8109 LTE_PMU_EN_P [2,21,22] C337 must to be close to U302 0.47UH LTE_DVCCK As short as possible and L307 as close as possible to L301, then connect to VPROC_PMU C8123 10uF VPROC_FB should be ground shielding. LTE_VBAT_MT6339 Star connection into Power input Pin VBAT_BUCK Star connection into Power input Pin U8101 W:30mil/ (15mil chip ) E2 VBAT_DLDO1 G1 VBAT_DLDO2 K7 VBAT_ALDO A1 DVDD18_VM12 B1 DVDD18_VUSB11 W:30mil/ (15mil chip ) W:20mil/ (15mil chip ) W:30mil/ (15mil chip ) LTE_VIO18_PMU LDO BUCK C8115 C8116 C8117 C8118 C8119 2.2uF 2.2uF 4.7uF 4.7uF 10uF Add 0-ohm for current measurement Input cap should be close to the PMIC GND to redue the loop area W:10mil LTE_VTCXO1 C1 VUSB11 LTE_VTCXO2 LTE_VA18 1.0uF LTE_VM12 E3 H3 D4 E4 F4 G4 E5 F5 C6 E6 F6 G6 B7 C7 D7 E7 F7 G7 H9 J9 GND_LDO1 GND_LDO2 GND_LDO3 GND_LDO4 GND_LDO5 GND_LDO6 GND_LDO7 GND_LDO8 GND_LDO9 GND_LDO10 GND_LDO11 GND_LDO12 GND_LDO13 GND_LDO14 GND_LDO15 GND_LDO16 GND_LDO17 GND_LDO18 GND_LDO19 GND_LDO20 LTE_XRSTB R8105 R8106 0 0 H5 H6 A6 A5 B5 B6 D6 PMU_EN PMU_CHGIN XRSTB SRCLKEN_IN1 SRCLKEN_IN2 PMU_EINT GND_GPIO LTE_USIM1RST LTE_USIM1DATA LTE_USIM1CLK LTE_USIMLV1_RST LTE_USIMLV1_DATA LTE_USIMLV1_CLK B4 J3 B3 J5 K3 J4 USIM1RST USIM1DATA USIM1CLK USIMLV1_RST USIMLV1_DATA USIMLV1_CLK LTE_USIM2RST LTE_USIM2DATA LTE_USIM2CLK LTE_USIMLV2_RST LTE_USIMLV2_DATA LTE_USIMLV2_CLK A3 USIM2RST J2 USIM2DATA C3 USIM2CLK H2 USIMLV2_RST K2 USIMLV2_DATA K1 USIMLV2_CLK LTE_SRCLKEN_IN1 LTE_PMU_EINT [23] LTE_USIM1RST [23] LTE_USIM1DATA [23] LTE_USIM1CLK [15,21] LTE_USIMLV1_RST [15,21] LTE_USIMLV1_DATA [15,21] LTE_USIMLV1_CLK [23] LTE_USIM2RST [23] LTE_USIM2DATA [23] LTE_USIM2CLK [21] LTE_USIMLV2_RST [21] LTE_USIMLV2_DATA [21] LTE_USIMLV2_CLK 2.2UH W:30mil 4.7uF C8113 L8102 W:3mil VIO18_FB B8 W:20mil/ (15mil chip ) L8103 VRF18 F10 2.2UH W:20mil LTE_VRF18_PMU W:3mil VRF18_FB J8 W:20mil/ (15mil chip ) L8104 VRF18_2 E10 2.2UH VRF18_2_FB A8 LTE_VRF18_2_PMU W:30mil/ (15mil chip ) VPA H10 L8105 2.2UH W:30mil W:3mil VPA_FB K9 1.LX should be as short as possible 2.FB should be shielding with GND and don't cross with LX Signals [2,21,22] LTE_PMU_EN_P LTE_VIO18_PMU W:30mil/ (15mil chip ) VIO18 C10 D5 PMU_BSI_CK C4 PMU_BSI_CS C5 PMU_BSI_DATA LTE_PMU_BSI_CK LTE_PMU_BSI_CS0B LTE_PMU_BSI_DO W:3mil VCORE_FB A7 MT6339 A2 VM12 4.7uF W:30mil 10uF C8112 K5 VTCXO1 K6 VTCXO2 K8 VA18 W:10mil W:40mil 4.7uF W:6mil W:6mil 2.2UH C8111 W:10mil LTE_VSIM2 L8101 VCORE A10 G2 VMC F2 VMCH J1 VSIM1 H1 VSIM2 W:8mil C8114 W:40mil/ (15mil chip ) GND1_VCORE GND2_VCORE GND1_VIO18 GND2_VIO18 GND1_VRF18 GND2_VRF18 GND1_VRF18_2 GND2_VRF18_2 GND2_VPA GND1_VPA LTE_VPA_PMU C8110 2.2uF C8 C9 D8 D9 F8 F9 E8 E9 G9 G8 Output cap should be close to the PMIC GND to reduce the loop area USIM VREF AVDD18_DIG C2 PMU_VREF J7 Close to PMIC LTE_PMU_VREF GND_VREF J6 PMU_FSOURCE B2 PMU_TESTMODE H4 100nF W:10mil LTE_VSIM1 LTE_DVCCK D1 VIO28 D3 VIO33 F1 VMIPI F3 VFS W:10mil LTE_VFS [26] LTE_PMU_BSI_CS0B [26] LTE_PMU_BSI_DO W:30mil/ (15mil chip ) W:30mil/ (15mil chip ) 1.0uF W:10mil W:10mil [25] LTE_XRSTB [21,26,29] LTE_SRCLKEN_OUT0 [24] LTE_SRCLKEN_OUT2 [26] LTE_PMU_EINT W:30mil/ (15mil chip ) W:30mil/ (15mil chip ) 1.0uF LTE_VIO33 LTE_DVDD18_MIPI [26] LTE_PMU_BSI_CK W:40mil/ (15mil chip ) A9 B10 J10 K10 G10 D10 1.0uF 1.0uF 4.7uF C8104 VBAT_VCORE VBAT_VIO18 VBAT1_VPA VBAT2_VPA VBAT_VRF18 VBAT_VRF18_2 C8109 C8106 C8105 4.7uF LTE_VA18 C8107 LTE_VSIM1 4.7uF Input cap should be close to the PMIC LTE_VM12 LTE_VSIM2 LTE_VTCXO1 C8101 LTE_VFS LTE_VIO33 Add 0-ohm for current measurement C8103 LTE_VTCXO2 C8102 LTE_DVDD18_MIPI W:10mil/ (10mil chip ) C8108 LTE_VBAT_MT6339 1.GND_VREF couldn't connect to system GND directly. 2.GND_VREF should routing with PMU_VREF together and throuh via connecto GND near the 100nF. <TITLE> TITLE: REV: DOCUMENT NO.: 81_MT6339 DEPARTMENT: Hardware DEPT. <REV> A1 SIZED: COMPANY: DESIGNER: <DESIGNER> Last Saved Date: 2014-7-30 SHEET: 22 OF 33 ** ** * 100nF B19 USB_DL_MODE A1 A2 LTE_SSUSB_VRT A16 B15 MC2CK MC2CM SDIO_CLK SDIO_CMD [22] LTE_USIM1DATA [22] LTE_USIM1RST [22] LTE_USIM2CLK [22] LTE_USIM2DATA [22] LTE_USIM2RST LTE_USIM1CLK LTE_USIM1DATA LTE_USIM1RST LTE_USIM2CLK LTE_USIM2DATA LTE_USIM2RST TP-0.5MM 1 T8205 1 5.1K NF(10K) [22] LTE_USIM1CLK TP-0.5MM R8227 B1 1 USB Trace Routing should be with differential pair XTALI_SSUSB C3 XTALO_SSUSB B2 SSUSB_VRT TP-0.5MM SSUSB_TXP D2 SSUSB_TXN E2 USB_DP USB_DM AVSS_USB AVSS_USB F3 G3 1 SSUSB_RXP SSUSB_RXN T8203 R8226 C8247 AVDD11_SSUSB E3 G5 LTE_VIO18_PMU Close to E1 Pin AVDD33_USB AVDD18_USB AVDD18_SSUSB E1 T8204 AVDD11_SSUSB C2 B3 C1 TP-0.5MM TP-0.5MM LTE_DVCCK C8246 100nF Close to B3/C1 Pin T8201 U8201-A AVDD18_SSUSB 1 AVDD18_USB T8202 Close to C2 Pin 1.0uF AVDD33_USB LTE_VIO18_PMU C8242 LTE_VIO33 M4 M7 M3 L2 M6 L4 USIM1CLK USIM1DATA USIM1RST USIM2CLK USIM2DATA USIM2RST MC2CK MC2CM SDIO_DAT3 B14 MC2DA3 SDIO_DAT2 C14 MC2DA2 SDIO_DAT1 C13 MC2DA1 SDIO_DAT0 E14 MC2DA0 SDIO_HOST_INTB E18 EINT7_SDIO_INTB_LTE MC2DA3 MC2DA2 MC2DA1 MC2DA0 [2,21] [2,21] [2,21] [2,21] [2,21] [2,21] EINT7_SDIO_INTB_LTE 1 T8206 [2,21] TP-0.5MM <TITLE> TITLE: DOCUMENT NO.: REV: 82_MT6290M_USB/SDIO/USIM <REV> A1 SIZED: Hardware DEPT. DEPARTMENT: COMPANY: DESIGNER: <DESIGNER> Last Saved Date: 2014-7-30 SHEET: 23 OF 33 ** ** * TP-0.5MM T8301 U8201-B LTE_VIO18_PMU R8301 MSDC0P_CLK MSDC0P_CMD MSDC0P_INS MSDC0P_WP D7 D5 B6 G6 C7 B4 E6 B5 MSDC0P_DAT7 MSDC0P_DAT6 MSDC0P_DAT5 MSDC0P_DAT4 MSDC0P_DAT3 MSDC0P_DAT2 MSDC0P_DAT1 MSDC0P_DAT0 10K_NF B13 A14 E13 B12 D12 D13 C12 U22 U23 LTE_SPI_CLK [22] LTE_SRCLKEN_OUT2 LTE_SPI_CS0B R8302 10K_NF SPI_CK SPI_CS1B SPI_CS0B SPI_HOLDB SPI_MISO SPI_MOSI SPI_WB SPITOAHB_CK SPITOAHB_DATA NFI_ALE NFI_CLE NFI_WEB NFI_REB NFI_RBY1 NFI_RBY0 NFI_CE1B NFI_CE0B NFI_DAT15 NFI_DAT14 NFI_DAT13 NFI_DAT12 NFI_DAT11 NFI_DAT10 NFI_DAT9 NFI_DAT8 NFI_DAT7 NFI_DAT6 NFI_DAT5 NFI_DAT4 NFI_DAT3 NFI_DAT2 NFI_DAT1 NFI_DAT0 F22 F23 D22 F21 G21 E22 F20 LTE_SRCLKEN_OUT3 E23 B23 LTE_AGPS_OUT A22 C23 A23 D20 AP_PCM_RX C22 AP_PCM_TX E20 AP_PCM_FSYNC D21 AP_PCM_CK 1 A4 F7 A5 E7 R8331 EINT8_AGPS_OUT_LTE [2] LTE_AGPS_OUT [24] LTE_AGPS_OUT [24] 0 [2,21] [2,21] AP_PCM_RX AP_PCM_TX [2,21] AP_PCM_FSYNC [2,21] AP_PCM_CK B22 B20 B21 A20 A19 E19 C21 E21 LTE_VIO18_PMU MT6290_GPIO17: for Conn_LTE co-existence LTE_JTCK R8303 10K LTE_JTDI R8304 10K U8201-C [2] MT6290_GPIO17 [2,21] AP_WAKEMD_INT TP-0.5MM T8306 AP_WAKEMD_INT 1 [24] I2C_EXIST B8 B7 GPIO17 GPIO16 A10 B10 G8 F8 E8 D8 B9 C8 GPIO15 GPIO14 GPIO13 GPIO12 GPIO11 GPIO10 GPIO9 GPIO8 E12 D9 A8 A11 B11 C11 D11 E11 GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 JTCK N19 JTDI P19 JTDO M22 JTMS P20 JTRST_N N22 M19 M20 LTE_CVJTCK LTE_CVJTMS SBJTCK SBJTMS P23 P22 LTE_SBJTCK LTE_SBJTMS SUART0_TXD R22 SUART0_RXD T22 SUART0_RTSB R23 SUART0_CTSB T19 LTE_JTMS LTE_JTRST_N LTE_CVJTCK [21,24] LTE_CVJTMS [21,24] LTE_SUART1_TXD LTE_SUART1_RXD LTE_MDUART_TXD LTE_MDUART_RXD LTE_CVJTMS LTE_SBJTMS LTE_SUART0_TXD LTE_SUART1_TXD [21] [21,24] LTE_MDUART_TXD [21,24] LTE_MDUART_RXD LTE_I2C_SCL LTE_I2C_SDA LTE_SUART0_RTSB LTE_SUART0_CTSB [21,24] [22,24] [22,24] LTE_I2C_SCL [22,24] LTE_I2C_SDA [24] I2C_EXIST R8309 R8310 10K 10K 1 T8303 R8311 1 T8304 R8312 TP-0.5MM 10K TP-0.5MM 10K LTE_SUART1_RXD R8313 10K LTE_MDUART_TXD 1 T8305 R8314 10K LTE_MDUART_RXD [22,24] TP-0.5MM 10K 10K 10K 10K LTE_SBJTCK LTE_SUART1_RXD R8305 R8306 R8307 R8308 LTE_SUART0_RXD MDUART_TXD R20 MDUART_RXD T20 1 T8302 LTE_CVJTCK LTE_SUART0_TXD LTE_SUART0_RXD LTE_SUART0_RTSB LTE_SUART0_CTSB SUART1_TXD P21 SUART1_RXD R21 I2C_SCL V16 I2C_SDA V17 LTE_JTDO LTE_JTCK LTE_JTDI LTE_JTDO LTE_JTMS LTE_JTRST_N CVJTCK CVJTMS TP-0.5MM R8315 1K R8316 1K R8317 10K <TITLE> TITLE: REV: 83_MT6290M_MSDC/SPI/NFI/UART/GP DOCUMENT NO.: <REV> A1 SIZED: Hardware DEPT. DEPARTMENT: COMPANY: DESIGNER: <DESIGNER> Last Saved Date: 2014-7-30 SHEET: 24 OF 33 ** ** * R8401 100K LTE_VA18 LTE_AUX_IN1 100K NTC8402 Close to LTE RF-PA C8407 100nF_NF 100K R8433 LTE_VA18 LTE_VTCXO1 1.0uF AB8 U10 U11 LTE_VA18 LTE_VIO18_PMU AVDD18_MD DVDD18_MD DVDD18_MD 1.0uF 100nF AC13 AC2 V7 Y15 AC1 AVDD18_MEMPLL C8460 C8406 LTE_VIO18_PMU Close to L23 Pin LTE_VA18 AVDD18_AUXADC LTE_XRSTB [22] LTE_XRSTB Close to AA8 Pin C8462 Close to AC10 Pin LTE_VIO18_PMU AVSS_REF AVSS18_L_MEMPLL AVSS18_MEMPLL M17 G2 M18 F2 R_TN_MEMPLL R_TN_MEMPLLC3 R_TP_MEMPLL R_TP_MEMPLLC3 P2 XRSTB Y2 Y3 ET_P ET_N B18 B17 W9 AB11 V9 AA9 AB10 AB9 Close to E16 Pin NTC8401 LTE_AUX_IN1 APC2 APC1 U13 U12 LTE_APC1_6290 AP_RSTB C17 LTE_AP_RSTB C8403 EINT5_RSTB_FROM_LTE A17 LTE_BOPT_RSV VREF_P VREFCA VREFDQ AC7 J1 L22 LTE_VREF_P REXTDN J4 LTE_REXTDN ZQ H2 LTE_ZQ TEST_MODE EFUSE_FSOURCE_P C8459 LTE_0V6_LPDDR2 LTE_0V6_LPDDR2 R8464 LTE_VIO18_PMU 10K C8458 100nF C8461 LTE_0V6_LPDDR2 100nF 100nF NF（ 56ohm） 1% R8465 LTE_32KIN D17 E15 1 EINT5_RSTB_FROM_LTE [2,21] R8463 AC11 AC12 [31] LTE_AP_RSTB [2,21] D18 BOPT_RSV XIN XOUT Close to U1607,rounting with ground guard 100nF_NF LTE_APC1_6290 OUT_RSTB 240 [25] R8422 LTE_VFS RTC32K_BPI_BUS14 [2] LTE_32KIN [25] R_TN_SYSPLLC3 R_TP_SYSPLLC3 0 C8466 1.0uF 100nF C8473 Close to H3 Pin C8472 100nF AVDD18_SYSPLL AVDD18_L_MEMPLL 1.0uF C8469 LTE_VIO18_PMU NF(100nF) 470nF C8468 AVDD18_OSC32K 100nF C8465 LTE_VA18 AVSS_MD AVSS_MD AVSS_MD AVSS_MD AVSS_MD AB7 F1 L21 AUX_IN5 AUX_IN4 AUX_IN3 AUX_IN2 AUX_IN1 AUX_IN0 T8401 TP-0.5MM 100nF C8405 C8456 LTE_VIO18_PMU LTE_VIO18_PMU Close to AA11 Pin AVDD28_DAC AVDD18_MEMPLL AVDD18_OSC32 AVDD18_AUXADC AVDD18_L_MEMPLL AVDD18_SYSPLL 1.0uF LTE_VA18 LTE_VA18 AVDD28_DAC C8470 100K U8201-D AA11 L23 AC10 AA8 H3 E16 LTE_VTCXO1 LTE_VIO18_PMU AVDD18_MD 470nF C8475 100nF C8476 LTE_VA18 LTE_VM12 Close to AB8 Pin 10K 1.0uF 100nF C8402 LTE_0V6_LPDDR2 10K R8473 Close to U10/U11 Pin C8401 1.0uF 100nF C8477 C8478 DVDD18_MD LTE_0V6_LPDDR2 R8471 LTE_VIO18_PMU <TITLE> TITLE: DOCUMENT NO.: REV: 84_MT6290M_MISC <REV> A1 SIZED: Hardware DEPT. DEPARTMENT: COMPANY: DESIGNER: <DESIGNER> Last Saved Date: 2014-7-30 SHEET: 25 OF 33 ** ** * U8201-E [29] LTE_LTEX26M_IN [21] LTE_SRCLKEN_OUT1 [21,22,29] LTE_SRCLKEN_OUT0 [30,31,32] LTE_MIPI0_SCLK [30,31,32] LTE_MIPI0_SDATA LTE_LTEX26M_IN LTE_SRCLKEN_OUT1 LTE_SRCLKEN_OUT0 LTE_MIPI0_SCLK LTE_MIPI0_SDATA U8 LTEX26M_IN Y10 TDX26M_IN RFIC1_BSI_CK AA17 RFIC1_BSI_EN Y17 RFIC1_BSI_D2 AB20 RFIC1_BSI_D1 AC20 RFIC1_BSI_D0 AB19 V3 V2 SRCLKEN_OUT1 SRCLKEN_OUT0 RFIC0_BSI_CK AA16 RFIC0_BSI_EN AB17 RFIC0_BSI_D2 AC19 RFIC0_BSI_D1 AC18 RFIC0_BSI_D0 AB18 AB1 AA1 W2 Y1 W3 MISC_BSI_CK MISC_BSI_CS1B MISC_BSI_CS0B MISC_BSI_DI MISC_BSI_DO PMU_BSI_CK M1 PMU_EINT N2 PMU_BSI_CS1B M5 PMU_BSI_CS0B N3 PMU_BSI_DI M2 PMU_BSI_DO N4 LTE_RFIC0_BSI_CK LTE_RFIC0_BSI_EN LTE_RFIC0_BSI_D2 LTE_RFIC0_BSI_D1 LTE_RFIC0_BSI_D0 LTE_RFIC0_BSI_CK LTE_RFIC0_BSI_EN LTE_RFIC0_BSI_D2 LTE_RFIC0_BSI_D1 LTE_RFIC0_BSI_D0 LTE_PMU_BSI_CK LTE_PMU_EINT LTE_PMU_BSI_CK LTE_PMU_EINT [29] [29] [29] [29] [29] [22] [22] LTE_PMU_BSI_CS0B LTE_PMU_BSI_CS0B LTE_PMU_BSI_DO LTE_PMU_BSI_DO [22] [22] U8201-F [30,31,32,33] [30,31,32,33] [30,31,32,33] LTE_BPI_OUT25 LTE_BPI_OUT24 [30,31,32,33] LTE_BPI_OUT23 LTE_BPI_OUT22 [30,31,32,33] [30,31,32,33] LTE_BPI_OUT18 LTE_BPI_OUT17 [30,31,32,33] LTE_BPI_OUT16 [29] LTE_TXBPI [30] LTE_PAVM1 [30] LTE_PAVM0 LTE_BPI_OUT25 LTE_BPI_OUT24 LTE_BPI_OUT23 LTE_BPI_OUT22 LTE_BPI_OUT18 LTE_BPI_OUT17 LTE_BPI_OUT16 LTE_TXBPI LTE_PAVM1 LTE_PAVM0 T3 U3 R2 R1 T2 P1 T4 U4 P5 R4 BPI_OUT25 BPI_OUT24 BPI_OUT23 BPI_OUT22 BPI_OUT21 BPI_OUT20 BPI_OUT19 BPI_OUT18 BPI_OUT17 BPI_OUT16 N5 AC22 LTE_TXBPI TD_TXBPI U2 U1 PAVM1 PAVM0 BPI_OUT15 BPI_OUT14 BPI_OUT13 BPI_OUT12 BPI_OUT11 BPI_OUT10 BPI_OUT9 BPI_OUT8 BPI_OUT7 BPI_OUT6 BPI_OUT5 BPI_OUT4 BPI_OUT3 BPI_OUT2 BPI_OUT1 BPI_OUT0 P6 AB22 AB23 AA23 AA22 W19 Y20 AA20 AB21 AA21 W21 V21 W20 Y22 W23 W22 LTE_BPI_OUT15 LTE_BPI_OUT14 LTE_BPI_OUT13 LTE_BPI_OUT12 LTE_BPI_OUT11 LTE_BPI_OUT10 LTE_BPI_OUT15 LTE_BPI_OUT14 LTE_BPI_OUT13 LTE_BPI_OUT12 LTE_BPI_OUT11 LTE_BPI_OUT10 [30,31,32,33] [30,31,32,33] [30,31,32,33] [30,31,32,33] [30,31,32,33] [30,31,32,33] LTE_BPI_OUT6[30,31,32,33] LTE_BPI_OUT3 [30,31,32,33] LTE_BPI_OUT2 [30,31,32,33] LTE_BPI_OUT0 [30,31,32,33] U8201-G Y5 AA6 LTE_RX2_BBIP LTE_RX2_BBIN TD_RX_BBIP AB14 TD_RX_BBIN AB13 [29] LTE_RX2_BBQP [29] LTE_RX2_BBQN LTE_RX2_BBQP LTE_RX2_BBQN W7 Y7 LTE_RX2_BBQP LTE_RX2_BBQN TD_RX_BBQP AB15 TD_RX_BBQN AC15 [29] LTE_RX1_BBIP [29] LTE_RX1_BBIN LTE_RX1_BBIP LTE_RX1_BBIN AC5 AB5 LTE_RX1_BBIP LTE_RX1_BBIN [29] LTE_RX1_BBQP [29] LTE_RX1_BBQN LTE_RX1_BBQP LTE_RX1_BBQN AC6 AB6 LTE_RX1_BBQP LTE_RX1_BBQN [29] LTE_TX_BBIP [29] LTE_TX_BBIN LTE_TX_BBIP LTE_TX_BBIN AC3 AB3 LTE_TX_BBIP LTE_TX_BBIN [29] LTE_TX_BBQP [29] LTE_TX_BBQN LTE_TX_BBQP LTE_TX_BBQN AB4 AC4 LTE_TX_BBQP LTE_TX_BBQN [29] LTE_RX2_BBIP [29] LTE_RX2_BBIN LTE_RX2_BBIP LTE_RX2_BBIN TD_TX_BBIP AA12 TD_TX_BBIN Y12 TD_TX_BBQP W14 TD_TX_BBQN Y14 <TITLE> TITLE: DOCUMENT NO.: REV: 85_MT6290M_RF/IQ/BPI <REV> A1 SIZED: Hardware DEPT. DEPARTMENT: COMPANY: DESIGNER: <DESIGNER> Last Saved Date: 2014-7-30 SHEET: 26 OF 33 ** ** * 1.0uF 1.0uF 1.0uF C8608 C8609 1.0uF 1.0uF 100nF C8607 100nF C8604 C8606 100nF C8603 C8605 100nF C8601 C8602 LTE_DVCCK LTE_DVCCK LTE_VIO18_PMU U8201-H DVDD_GPIO A7 G22 DVDD18 DVDD18 DVDD18 DVDD18 DVDD18 F12 F16 M9 R7 U14 100nF DVDD_GPIO DVDD_RFBPI C8615 Close to A7 Pin C8616 100nF DVDD18 Close to F12/F16/M9/R7/U14 Pin C8614 1.0uF C8613 1.0uF C8612 LTE_DVDD18_MIPI LTE_VIO18_PMU H1 L1 DVDD18_DDR0 C8610 LTE_VIO18_PMU DVDD18_MIPI V1 1.0uF LTE_VIO18_PMU LTE_VIO18_PMU DVDD18_JTAG M23 DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS LTE_VIO18_PMU LTE_VIO18_PMU LTE_VIO18_PMU A13 AC23 DVDD18_SDIO B16 DVDD18_DDR1 DVDD18_DDR1 Close to AC23 Pin LTE_VIO18_PMU LTE_VIO18_PMU LTE_DVDD18_MIPI LTE_VIO18_PMU LTE_VIO18_PMU LTE_VIO18_PMU DVDD_SPI Close to A13 Pin 1.0uF 100nF DVDD18_JTAG Close to M23 Pin C8621 Close to C20 Pin C8620 DVDD_NFI C8619 LTE_VM12 100nF H23 J23 K22 C8618 J2 K2 DVDD12_DDR0 DVDD12_DDR0 DVDD12_DDR0 100nF LTE_VM12 DVDD12_DDR1 DVDD12_DDR1 C8617 C16 G20 H22 H4 H5 J22 K10 K11 K12 K13 K14 K20 K21 K4 L10 L11 L12 L13 L14 L20 M10 M11 M12 M13 M14 N10 N11 N12 N13 N14 P10 P11 P12 P13 P14 LTE_VIO18_PMU LTE_VIO18_PMU C4 100nF DVDD_SPI DVDD_RFBPI LTE_VIO18_PMU C20 100nF DVDD_NFI DVDD_MSDC0 C8611 DVCCK DVCCK DVCCK DVCCK DVCCK DVCCK DVCCK DVCCK DVCCK DVCCK DVCCK DVCCK DVCCK DVCCK DVCCK DVCCK 100nF E10 H20 J17 J18 J19 J6 K18 K19 K5 K6 L17 L18 L19 L5 P7 U15 DVDD18_MIPI Close to V1 Pin LTE_VM12 LTE_VIO18_PMU 1.0uF C8623 C8622 100nF LTE_VIO18_PMU DVDD18_SDIO Close to B16 Pin within 150mils LTE_VIO18_PMU 100nF 1.0uF C8635 100nF C8633 C8636 4.7PF(5PF) C8632 1.0uF 1.0uF C8631 C8634 1.0uF C8630 4.7PF(5PF) 100nF C8629 4.7uF C8628 1.0uF C8627 1.0uF C8626 100nF C8624 C8625 LTE_VM12 DVDD12_DDR0 DVDD12_DDR1 DVDD18_DDR1 DVDD18_DDR0 Close to H23/J23/K22 Pin Close to J2/K2 Pin Close to H1/L1 Pin Close to G22 Pin <TITLE> TITLE: DOCUMENT NO.: REV: 86_MT6290M_POWER/GND <REV> A1 SIZED: Hardware DEPT. DEPARTMENT: COMPANY: DESIGNER: <DESIGNER> Last Saved Date: 2014-7-30 SHEET: 27 OF 33 ** <TITLE> TITLE: DOCUMENT NO.: REV: 30_RF_MT6165_2G_TRX ** * <REV> A1 SIZED: Hardware DEPT. DEPARTMENT: COMPANY: DESIGNER: <DESIGNER> Last Saved Date: 2014-7-30 SHEET: 28 OF 33 ** ** * [29,30,31] LTE_TXDET [29,30] LTE_TX_HB2 [29,30] LTE_RFIN1_LB1 [31] [29,32] LTE_RFIN2_MB2 Off-Page Connector To BB IC part [26,29] LTE_RX2_BBIP [26,29] LTE_RX2_BBIN LTE_RX2_BBQP GND GND GND GND GND GND GND GND GND GND F2 F4 F5 F6 F7 F8 F9 F10 F11 F12 LTE_RX2_BBQN [26,29] LTE_RX1_BBIP [26,29] [26,29] [26,29] LTE_RX1_BBIN LTE_RX1_BBQP LTE_RX1_BBQN [26,29] [26,29] LTE_TX_BBIP LTE_TX_BBIN LTE_TX_BBQP LTE_TX_BBQN [26,29] [26,29] [26,29] LTE_RFIC0_BSI_CK [26,29] LTE_RFIC0_BSI_EN [26,29] [26,29] LTE_RFIC0_BSI_D2 LTE_RFIC0_BSI_D1 [26,29] LTE_RFIC0_BSI_D0 [21,22,26,29] LTE_SRCLKEN_OUT0 [26,29] LTE_VIO18_PMU C3105 R3112 2k GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND H11 H10 H9 H8 H7 H6 H5 H4 H3 G12 G11 G10 G9 G8 G7 G6 G5 G4 G3 G2 NF L12 L11 L10 L9 L8 L7 L6 L3 K12 K9 K8 K7 K3 J12 J11 J10 J9 J8 J4 J3 LTE_RFIC0_BSI_CK [26,29] LTE_RFIC0_BSI_EN [26,29] LTE_RFIC0_BSI_D0 [26,29] LTE_RFIC0_BSI_D1 [26,29] LTE_RFIC0_BSI_D2 [26,29] R3104 DET_GND TXO_GND TXO_GND TXO_GND TXO_GND TXO_GND TXO_GND TXO_GND TXO_GND TXO_GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND LTE_TXBPI [26,29] MT6169_VTCXO_PMU [26,29] LTE_RX2_BBIP LTE_RX2_BBIN LTE_RX2_BBQP LTE_RX2_BBQN LTE_RX1_BBIP LTE_RX1_BBIN LTE_RX1_BBQP LTE_RX1_BBQN LTE_TX_BBIP LTE_TX_BBIN LTE_TX_BBQP LTE_TX_BBQN LTE_RFIC0_BSI_CK LTE_RFIC0_BSI_EN LTE_RFIC0_BSI_D2 LTE_RFIC0_BSI_D1 LTE_RFIC0_BSI_D0 LTE_SRCLKEN_OUT0 SRCLKENA SRCLKENA LTE_TXBPI LTE_TXBPI LTE_LTEX26M_IN LTE_LTEX26M_IN [29] MT6169_XO2 MT6169_XO2 [29] MT6169_XO4 MT6169_XO4 MT6169_VIO18_PMU To PMIC MT6323 100nF MT6169_VTCXO_PMU MT6169_VIO18_PMU R3109 LTE_SRCLKEN_OUT0 [21,22,26,29] 0 [26,29] LTE_LTEX26M_IN To PMIC MT6339 R3110 0 SRCLKENA [2,3,4,21,29] 0 LTE_VIO18_PMU NF NC NC 5 2 VCC 6 NF 1 KT2520F26000DCW28QAK U3102 MT6169_VTCXO_PMU 100nF OUT C3110 4 VCONTROL GND 3 LTE_VRF18_PMU C3109 CLK_26M_MT6323 [3] [29] MT6169_XO4 [29] MT6169_XO2 Title 31_RF_MT6169_PIN_OUT Size A2 Date: Mediatek Confidential Tuesday, December 17, 2013 Sheet 31 of 99 C3108 MT6169_XO4 [29] MT6169_XO2 [29] 100nF R3121 0 R3122 R3111 [2] CLK1_BB RES-2K-+-1%-0402 L13 K13 J13 H13 G13 F13 E13 E14 E15 L14 M4 N5 M5 M6 M7 N7 N8 N13 N14 N4 RX2_BBQP RX2_BBQN RX2_BBIN RX2_BBIP RX1_BBQP RX1_BBQN RX1_BBIN RX1_BBIP N15 M15 TX_BBIP TX_BBIN TX_BBQP TX_BBQN F14 F15 H14 G14 H15 J15 J14 K14 D14 C14 C15 M13 TXDET TX_HB2 TX_HB1 TX_MB2 TX_MB1 TX_LB4 TX_LB3 TX_LB2 TX_LB1 RFIP1_LB1 H12 M12 K10 N10 M10 M9 K6 J7 J6 J5 K4 [2,3,4,21,29] C3111 LTE_RFIP2_MB2 2.2uF [29,32] GND GND GND GND GND GND GND GND GND GND GND RFIN2_LB3 E1 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 RFIP2_LB3 B1 C3103 RFIN2_MB1 A1 C3102 A2 100nF RFIP2_MB1 100nF RFIN2_HB2 A3 GND GND GND GND GND GND GND GND GND GND RFIP2_HB2 B3 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 B4 TST4 TST3 TXBPI VRT TST2 TMEAS BSI_CK BSI_EN BSI_D0 BSI_D1 BSI_D2 [26,29] [26,29] GND GND GND GND GND GND GND GND GND RFIN2_LB2 C3 C4 C5 C6 C7 C9 C10 C11 C12 LTE_RFIP2_HB2 LTE_RFIN2_HB2 RFIP2_LB2 B5 C3101 [29,32] [29,32] A5 100nF A6 C3106 RFIN2_HB1 LTE_RFIP2_HB1 LTE_RFIN2_HB1 100nF RFIP2_HB1 [29,32] [29,32] C3107 RFIN2_LB1 100nF B7 B6 VRXHF2 VRXHF1 V28_ESD1 VTXHF VTXLF VRXLF VDCXO_DIG VIO VTCXO RFIP2_LB1 [29,32] LTE_RFIN2_MB2 C8 D13 M11 N11 K11 M8 L4 M3 J1 RFIN1_HB3 B8 C3104 RFIP1_HB3 A8 100nF RFIN1_MB2 A9 LTE_VRF18_PMU B9 LTE_RFIP1_HB3 LTE_RFIN1_HB3 XMODE CLK_SEL EN_26M_BB LTE_RFIN1_MB2 [29,31] [29,31] L2 N1 N2 [29,31] [29,32] LTE_RFIP2_MB2 1K RFIP1_MB2 R3107 LTE_RFIP2_HB2 LTE_RFIN2_HB2 B10 XTAL2 XTAL1 [29,32] [29,32] LTE_RFIP1_MB2 K1 K2 RFIN1_LB3 [29,31] XO3 XO4 XO2 XO1 RFIP1_LB3 B11 G1 H2 H1 M1 RFIN1_HB2 A11 1K RFIP1_HB2 A12 OUT_32K 32K_EN TST1 B12 RFIN1_LB1 B15 LTE_RFIP1_HB2 LTE_RFIN1_HB2 RFIP1_HB1 RFIN1_HB1 [29,31] RFIP2_MB2 B39 DRX RFIN1_LB2 C1 B40 DRX [29,32] LTE_RFIN2_HB1 RFIP1_LB2 A14 F1 J2 F3 LTE_RFIP2_HB1 A15 R3108 LTE_RFIN1_HB3 RFIN1_MB1 [29,31] [29,31] LTE_RFIP1_HB3 [29,31] [29,32] B13 RFIN2_HB3 [29,31] LTE_RFIN1_MB2 B40 PRX RFIP1_MB1 RFIP2_HB3 [29,31] LTE_RFIP1_MB2 B34/B39 PRX B14 RFIN2_MB2 U3101 LTE_RFIP1_MB1 [31] LTE_RFIN1_MB1 [31] E2 LTE_RFIN1_HB2 [29,31] D2 LTE_TX_HB2 [29,30] LTE_RFIP1_HB2 [29,31] B41/B38 PRX B41/B38 DRX LTE_RX1_BBQP [26,29] LTE_RX2_BBIP [26,29] LTE_RX2_BBIN [26,29] LTE_RX2_BBQN [26,29] LTE_RX2_BBQP [26,29] C2 LTE_TX_HB2 B38/B40/B41 LTE_RX1_BBQN [26,29] LTE_RFIN1_HB1 [31] LTE_TX_HB1 [29,30] [26,29] LTE_RX1_BBIN [26,29] LTE_RFIP1_HB1 [31] LTE_TX_HB1 [26,29] LTE_TX_BBQN LTE_RX1_BBIP [26,29] LTE_RFIP1_LB1 [31] LTE_TXDET [29,30,31] B34/B39 [26,29] LTE_TX_BBIN LTE_TX_BBQP [26,29] LTE_TX_LB3 [31] (To RF front-end) LTE_TX_BBIP LTE_TX_HB1 LTE_TX_MB1 [31] Off-Page Connector <TITLE> TITLE: DOCUMENT NO.: REV: 31_RF_MT6169_PIN_OUT <REV> A1 SIZED: Hardware DEPT. DEPARTMENT: COMPANY: DESIGNER: <DESIGNER> Last Saved Date: 2014-7-30 SHEET: 29 OF 33 *** ** * To MT6169 LTE_TX_HB2 [29,30] LTE_TX_HB2 [29,30] LTE_TX_HB1 [29,30] LTE_TX_HB1 [29,30] B38/B40/B41 B34/B39 BPI config. R3212 2 NF 1 [31] BPI0 BPI1 BPI2 BPI3 BPI4 BPI5 BPI6 BPI7 BPI8 BPI9 BPI10 BPI11 BPI12 BPI13 BPI14 BPI15 BPI16 BPI17 BPI18 BPI19 BPI20 BPI21 BPI22 BPI23 BPI24 BPI25 2 4.7nH L3203 2 5.6NH 1 1 1 U3208 R3230 2 NC0 1 1 NF 4 RFIN_B34_39 NC3 21 RFOUT_B34_39 19 1.0nH 2 6 RFIN_B38_40_41RFOUT_B38_41 17 1 2 R1 NF R3231 B34_B39_TX 18PF 0 2 2 C3256 OUT 3 L3202 NF R3213 1 IN 1 33PF 8.2pF 1 LTE_TX_HB2 [29,30] C16 U3207 C3202 2 NF 2 0 L3201 1 L3217 1 C3218 2 GND 18PF 2 LTE_TX_HB1 [29,30] 1 RF3 3 RF2 5 RF1 B41/38_RX [31] U3210 L3211 6.8pF 2 2 B38_TRX [31] B38 TRX NF 1 1 1 2 C3262 C3271 1 IN1 1 C3264 3 GND 5 GND 2 GND 2 NF 3.6nH 2 4 IN2 3.3NH 1 6.8pF C3265 2 U3205 1 1 2 18PF C3283 C3281 18PF 2 1 L3215 2 B40_RX [31] PA VMode to MT6290 (SKY77761) 2 1 4 1.0nH 2 L3220 L3206 B40 TRX LTE_DVDD18_MIPI LTE_MIPI0_SDATA [26,30,31,32] LTE_MIPI0_SCLK [26,30,31,32] 10PF 1 1nF 2 C3267 470nF LTE_MIPI0_SDATA [26,30,31,32] LTE_MIPI0_SCLK [26,30,31,32] LTE_MIPI1_SDATA [30,31,32] LTE_MIPI1_SDATA [30,31,32] C3201 2 C3206 LTE_PAVM1 LTE_PAVM0 MIPI (To MT6290/6339) B40_TRX [31] C3205 3.6nH U3221 OUT 3 NF G IN G 1 2 1.0nH NF 1 1 2 U3206 G L3210 2 [26,30] LTE_PAVM1 [26,30] LTE_PAVM0 5 885049 1 RF3 3 RF2 5 RF1 C3259 GND 2 VC1 C3258 2 18PF C3266 1 C3276 18PF 1 2 VDD 3.6nH 6 1 4 VDD_RFSW [26,30,31,32,33]LTE_BPI_OUT6 VPA_VCC2_HB 1 AT_SEL_DRX AT_SEL_MAIN1 AT_SEL_MAIN2_1 AT_SEL_MAIN2_2 NA NA B34B39_TX_SEL DCS_Notch_SEL NA NA B34B39_PA_EN 2G_TXM_VCTRL_A 2G_TXM_VCTRL_B 2G_TXM_VCTRL_C 2G_TXM_PA_ENABLE ANT_DRX_SP3T_V1 ANT_DRX_SP3T_V2 NA NA ANT_Main1_SP8T_V1 ANT_Main1_SP8T_V2 ANT_Main1_SP8T_V3 3P4T_V1 3P4T_V2 3P4T_V3 3P4T_V4 2 1.0nH NF 1 C3275 1 9 13 14 16 18 20 22 23 25 27 GND VC1 1 GND0 GND1 GND2 GND3 GND4 GND5 GND6 GND7 GND8 GND9 EXPOSED_GND 2 VDD C3263 C3280 2 1 6 NC1 5 1 2 0.01uF C3221 1 1 82PF C3220 2 VBAT_RF 4 VDD_RFSW LTE_BPI_OUT10 [26,30,31,32,33] 1 NF C3279 2 C3260 2 18PF 2 CPL_OUT 24 1.0PF 11 VMODE 3 VCONT0 7 VCONT1 8 VCONT2 26 VBATT 10 VCC 1 C3257 1 18PF C3270 2 18PF C3278 2 18PF C3277 1 [26,30,31,32,33] LTE_BPI_OUT22 [26,30,31,32,33]LTE_BPI_OUT23 [26,30,31,32,33] LTE_BPI_OUT24 [26,30,31,32,33] LTE_BPI_OUT25 12 CPL_IN C3274 51 NF RFOUT_B40 15 2 R3223 LTE_BPI_OUT25 LTE_BPI_OUT24 LTE_BPI_OUT23 LTE_BPI_OUT22 LTE_BPI_OUT21 LTE_BPI_OUT20 LTE_BPI_OUT19 LTE_BPI_OUT18 LTE_BPI_OUT17 LTE_BPI_OUT16 LTE_BPI_OUT15 LTE_BPI_OUT14 LTE_BPI_OUT13 LTE_BPI_OUT12 LTE_BPI_OUT11 LTE_BPI_OUT10 LTE_BPI_OUT9 LTE_BPI_OUT8 LTE_BPI_OUT7 LTE_BPI_OUT6 LTE_BPI_OUT5 LTE_BPI_OUT4 LTE_BPI_OUT3 LTE_BPI_OUT2 LTE_BPI_OUT1 LTE_BPI_OUT0 LTE_BPI_OUT25 [26,30,31,32,33]LTE_BPI_OUT24 [26,30,31,32,33]LTE_BPI_OUT23 [26,30,31,32,33]LTE_BPI_OUT22 [26,30,31,32,33]LTE_BPI_OUT21 [30,31,32,33]LTE_BPI_OUT20 [30,31,32,33]LTE_BPI_OUT19 [30,31,32,33]LTE_BPI_OUT18 [26,30,31,32,33]LTE_BPI_OUT17 [26,30,31,32,33]LTE_BPI_OUT16 [26,30,31,32,33]LTE_BPI_OUT15 [26,30,31,32,33]LTE_BPI_OUT14 [26,30,31,32,33]LTE_BPI_OUT13 [26,30,31,32,33]LTE_BPI_OUT12 [26,30,31,32,33]LTE_BPI_OUT11 [26,30,31,32,33]LTE_BPI_OUT10 [26,30,31,32,33]LTE_BPI_OUT9 [30,31,32,33]LTE_BPI_OUT8 [30,31,32,33]LTE_BPI_OUT7 [30,31,32,33]LTE_BPI_OUT6 [26,30,31,32,33]LTE_BPI_OUT5 [30,31,32,33]LTE_BPI_OUT4 [30,31,32,33]LTE_BPI_OUT3 [26,30,31,32,33]LTE_BPI_OUT2 [26,30,31,32,33]LTE_BPI_OUT1 [30,31,32,33]LTE_BPI_OUT0 [26,30,31,32,33] LTE_MIPI1_SCLK [30,31,32] LTE_MIPI1_SCLK [30,31,32] To LTE_VTCXO1 (0ohm to MT6339) 51(62) 2 R3315 2 VDD_RFSW LTE_TXDET [29,31] R3242 1 LTE_VTCXO1 0 1 1 1 R3316 R3319 100(110) VDD_RFSW only connect to LTE_VTCXO1 by MT6339. (LTE_VTCXO2 off at CSFB) 2 2 100(110) Power Net Connection PA Power 80mil 1 0 2 VBAT R3115 R3116 105欧姆 LTE_VPA_PMU VBAT MTK参考设计R3114 R3115 R3116 0201封装 R3239 1 22uF C3239 2 VBAT_RF 10mil VPA_VCC1 2 LTE_VPA_PMU 2 1 R3237 1uF 1 C3241 VPA_VCC2_HB 0 VPA_VCC2_TDD PA Power Trace Width VPA_VCC1: 10mil VPA_PMU, VPA_VCC2, VPA_VCC2_B7, VPA_VCC2_TDD : 30mil VBAT : 80mil Title 32_RF_MT6169_RF_TX Size MTK Confidential D Date: Tuesday, December 17, 2013 32 <TITLE> TITLE: DOCUMENT NO.: Sheet of 99 REV: 32_RF_MT6169_RF_TX <REV> SIZED: A1 Hardware DEPT. DEPARTMENT: COMPANY: DESIGNER: <DESIGNER> Last Saved Date: 2014-7-30 SHEET: 30 OF 33 ** SKY77593 control logic table Enable VctC VctB VctA LB_GMSK_TX H L L H HB_GMSK_TX H L H H LB_EDGE_TX H H L H HB_EDGE_TX H H H H 2G_LB_Rx L H L L 2G_NDCS_Rx L H H L NA L H L H 2G_HB_Rx L L H L PRX (To MT6169) LTE_RFIP1_HB2 [29,31] C3302 LTE_RFIP1_HB3 [29,31] B34/B39 PRX B40 PRX LTE_RFIN1_HB3 [29,31] LTE_TXDET [29,30,31] CON3304 1 IN OUT 2 C3319 RF-SWITCH-818000291 33PF LTE_TXDET[29,30,31] TRX4 L3347 NF L3307 NF 2G_HB_RX_6169 [31] 23 2G (To MT6165) MAIN2_ANT[33] 2G_LB_RX_6169 [31] 24 NF 1.0nH 25 NF 26 L3318 C3310 27 2G_HB_IN_6165 [31] 2G_HB_IN_6165 [31] 2G_LB_IN_6165 [31] 2G_LB_IN_6165 [31] 2G_HB_DT 2G_LB_DT 2G_NDCS_RX 22 TRX2 TRX3 21 TRX1 GND 16 15 22PF VRAMP VCC 28 L3320 ANT GND [30,31] B40_TRX B38_TRX [30] B41_B38_TRX [31] 2G_HB_RX [31] 2G_LB_RX [31] [31] 2 B34_B39_TRX [31] 22PF C3305 1 LTE_RFIP1_HB3 [29,31] LTE_RFIN1_HB3 [29,31] 1 3 4 5 6 7 8 2 GND TRX5 1K R3305 LTE_BPI_OUT12 [26,30,31,32,33] LTE_RFIP1_MB2 [29,31] LTE_RFIN1_MB2 [29,31] GND GND GND GND TRX6 VBATT 2 C3304 GND BS1 1K 1 GND BS2 TXEN 2 14 R3303 TX_LB_IN MODE 12 20 10 13 LTE_BPI_OUT11 [26,30,32,33] GND TX_HB_IN 9 2 NF 19 1 0 11 R3318 18 1 33PF GND GND 2 R3302 RF-PA-SKY77590 U3301 C3303 LTE_TX_LB3 [29] B41/B38 PRX LTE_RFIN1_HB2 [29,31] LTE_RFIP1_MB2 [29,31] LTE_RFIN1_MB2 [29,31] 2 0 17 1 1 NF R3313 18PF 2G_PAIN_LB ASM_Main2_824~1990MHz R3301 LTE_TX_MB1 [29] LTE_RFIP1_HB2 [29,31] LTE_RFIN1_HB2 [29,31] EDGE TXM 2G_PAIN_HB ** * To MMMB/discrete PA/3P4T B34_TX [31] R3307 VBAT 10K LTE_APC1_6290 [25,31] 2 B39_TX [31] 24K R3308 1 220PF C3315 B41/38_RX [30,31] 2 22uF 1uF C3309 C3308 100nF C3307 33PF C3306 1 B40_RX [30,31] B41_B38_TRX [31] B40_TRX [30,31] B38_TXSAW_OUT [31] LTE_BPI_OUT14 [26,30,31,32,33] 22PF C3316 22PF C3311 LTE_BPI_OUT13 [26,30,31,32,33] LTE_APC1_6290 [25,31] [25,31] LTE_APC1_6290 To LTE_VTCXO1 (0ohm to MT6339) VDD_RFSW MIPI (To MT6290/6339) LTE_DVDD18_MIPI LTE_MIPI0_SDATA [26,30,31,32] LTE_MIPI0_SDATA [26,30,31,32] LTE_MIPI0_SCLK [26,30,31,32] LTE_MIPI0_SCLK [26,30,31,32] LTE_MIPI1_SDATA [30,31,32] LTE_MIPI1_SDATA [30,31,32] LTE_MIPI1_SCLK [30,31,32] 8.2nH 6.8nH L3333 C3340 BAL_PORT1 6 BAL_PORT2 9 2.7PF C3341 2.7PF 3.3NH 4 HCH 3.6nH 1 LCH 18PF L3335 18PF C3339 L3334 L3332 U3307 C3338 3.3PF NF NF NF 2.2NH L3341 L3343 LTE_RFIN1_HB2 [29,31] L3350 L3315 NF 4.7PF(5PF) 3.3PF C3353 GND 7 GND 8 GND 5 L3312 3.9nH NF C3365 DIFF1 3 1.8nH LTE_RFIP1_MB1 [29] RF-SAW-SAWEN1G84CW0F00 U3305 C3360 C3330 2 SE B41/38_RX [30,31] 4.7PF(5PF) 6 1 GND DIFF2 4 C3352 8.2pF(8PF) 7 LTE_RFIP1_HB2 [29,31] U3323 LTE_RFIN1_HB1 [29] 9 8 L3344 BAL1(1842.5) NF NF L3311 BAL2(1842.5) L3314 UBAL(1842.5/1960) 3.9nH GND 3 5 10 4 2 GND GND GND GND 1 2.7nH [26,30,31,32,33] LTE_BPI_OUT25 [26,30,31,32,33] LTE_BPI_OUT24 [26,30,31,32,33] LTE_BPI_OUT23 C3349 C3326 BAL2(1960) BAL1(1960) L3310 2G_HB_RX_6169 [31] BPI config. B34 & B39 PRX B38/41, B40 PRX LTE_RFIP1_HB1 [29] C3329 2 GND 3 GND 10 GND 8.2pF(8PF) LTE_RFIN1_MB2 [29,31] LTE_RFIP1_MB2 [29,31] LTE_RFIN1_MB1 [29] C3367 C3359 LTE_RFIP1_HB3 [29,31] NF L3357 NF 6.8nH 6.8nH B34_B39_TRX [31] 1 2 3 13 12 GND GND 11 RFC 10 GND J1 GND J3 U3312 L3371 V1 4 V2 5 VDD 6 LTE_BPI_OUT17[26,30,31,32,33] LTE_BPI_OUT18[26,30,31,32,33] VDD_RFSW 33PF C3333 33PF 33PF C3332 LTE_RFIP1_LB1 [29] C3370 C3331 C3364 NF NF 2.2PF U3309 [26,30,31,32,33] LTE_BPI_OUT22 [30,31,32,33] LTE_BPI_OUT21 [30,31,32,33] LTE_BPI_OUT20 [30,31,32,33] LTE_BPI_OUT19 [26,30,31,32,33] LTE_BPI_OUT18 [26,30,31,32,33] LTE_BPI_OUT17 [26,30,31,32,33] LTE_BPI_OUT16 [26,30,31,32,33] LTE_BPI_OUT15 [26,30,31,32,33] LTE_BPI_OUT14 [26,30,31,32,33] LTE_BPI_OUT13 [26,30,31,32,33] LTE_BPI_OUT12 [31] 2G_TXM_VCTRL_A [26,30,31,32,33] LTE_BPI_OUT10 [30,31,32,33] LTE_BPI_OUT9 [30,31,32,33] LTE_BPI_OUT8 [30,31,32,33] LTE_BPI_OUT7 [26,30,31,32,33] LTE_BPI_OUT6 [30,31,32,33] LTE_BPI_OUT5 [30,31,32,33] LTE_BPI_OUT4 [26,30,31,32,33] LTE_BPI_OUT3 [26,30,31,32,33] LTE_BPI_OUT2 [30,31,32,33] LTE_BPI_OUT1 [26,30,31,32,33] LTE_BPI_OUT0 BPI0 BPI1 BPI2 BPI3 BPI4 BPI5 BPI6 BPI7 BPI8 BPI9 BPI10 BPI11 BPI12 BPI13 BPI14 BPI15 BPI16 BPI17 BPI18 BPI19 BPI20 BPI21 BPI22 BPI23 BPI24 BPI25 LTE_RFIN1_HB3 [29,31] 6.8pF J2 GND GND 4 22NH 3 6.8pF C3363 9 8 7 OUT2 RF-SAW-SAFEB942MFL0F00 L3309 L3356 2 C3369 OUT1 IN NF 1 56PF L3368 C3361 GND GND 5 LTE_RFIN1_LB1[29] 2G_LB_RX_6169 [31] DIFF1 3 L3355 2 SE 3.3NH L3354 U3344 1 GND DIFF2 4 C3366 B40_RX [30,31] 2.2PF LTE_MIPI1_SCLK [30,31,32] LTE_BPI_OUT25 LTE_BPI_OUT24 LTE_BPI_OUT23 LTE_BPI_OUT22 LTE_BPI_OUT21 LTE_BPI_OUT20 LTE_BPI_OUT19 LTE_BPI_OUT18 LTE_BPI_OUT17 LTE_BPI_OUT16 LTE_BPI_OUT15 LTE_BPI_OUT14 LTE_BPI_OUT13 LTE_BPI_OUT12 2G_TXM_VCTRL_A LTE_BPI_OUT10 LTE_BPI_OUT9 LTE_BPI_OUT8 LTE_BPI_OUT7 LTE_BPI_OUT6 LTE_BPI_OUT5 LTE_BPI_OUT4 LTE_BPI_OUT3 LTE_BPI_OUT2 LTE_BPI_OUT1 LTE_BPI_OUT0 AT_SEL_DRX AT_SEL_MAIN1 AT_SEL_MAIN2_1 AT_SEL_MAIN2_2 NA NA B34B39_TX_SEL DCS_Notch_SEL NA NA B34B39_PA_EN 2G_TXM_VCTRL_A 2G_TXM_VCTRL_B 2G_TXM_VCTRL_C 2G_TXM_PA_ENABLE ANT_DRX_SP3T_V1 ANT_DRX_SP3T_V2 NA NA ANT_Main1_SP8T_V1 ANT_Main1_SP8T_V2 ANT_Main1_SP8T_V3 3P4T_V1 3P4T_V2 3P4T_V3 3P4T_V4 B34_B39_TX [30] <TITLE> TITLE: DOCUMENT NO.: REV: 33_RF_MT6169_RF_PRX <REV> A1 SIZED: Hardware DEPT. DEPARTMENT: COMPANY: DESIGNER: <DESIGNER> Last Saved Date: 2014-7-30 SHEET: 31 OF 33 ** ** * DRX ANT: 1880~2690MHz B40 DRX DRX Car Kit L3408 6.8pF C3405 3.3NH NF DIFF1 3 1.5nH L3403 2 SE L3401 C3404 4 LTE_RFIP2_HB2 [29,32] 1 GND DIFF2 4 3 4.7nH G G DRX (To MT6169) LTE_RFIN2_HB2 [29,32] 6.8pF B41_38_DRX [32] 4 C3411 B40 DRX LTE_RFIN2_HB2 [29,32] LTE_RFIP2_MB2 [29,32] LTE_RFIP2_MB2 [29,32] LTE_RFIN2_MB2 [29,32] LTE_RFIN2_MB2 [29,32] B39 DRX 4.7nH OUT 3 LTE_RFIP2_HB1 [29,32] 6.8pF L3407 1.0nH NF 1 IN VDD_RFSW OUT 4 L3406 U3452 C3433 G 2 VDD C3409 B41_38_DRX [32] 5 G 5 6 NF V2 9 8 7 GND V1 B41/38 DRX LTE_RFIN2_HB1 [29,32] LTE_RFIP2_HB2 [29,32] LTE_RFIN2_HB2 [29,32] L3483 RFC 33PF 11 10 C3408 GND GND LTE_RFIP2_HB1 [29,32] LTE_RFIP2_HB2 [29,32] B41/38 DRX 1 2 3 13 12 J1 GND J3 U3401 LTE_RFIP2_HB1 [29,32] LTE_RFIN2_HB1 [29,32] J2 GND GND RF-SWITCH-818000291 56PF NF C3407 18PF NF C3406 L3428 CON3401 2 OUT IN 1 L3405 LTE_RFIN2_HB1 [29,32] 6.8pF B40_DRX [32] ANT_DRX_SP3T_V1 LTE_BPI_OUT15 [26,30,31,32,33] B39 DRX C3417 22PF 4.7nH OUT 3 22PF NF OUT 4 L3413 1 IN 22PF LTE_RFIP2_MB2 [29,32] U3407 L3412 G 2 C3415 5 G B39_DRX [32] 5.6NH 33PF BPI config. C3413 L3411 33PF LTE_BPI_OUT16 [26,30,31,32,33] C3410 ANT_DRX_SP3T_V2 SKY13373 SP3T_V1 SP3T_V2 V1 V2 J1 (B41_38_DRX) 0 1 J2 (B40_DRX) 1 0 J3 (B39_DRX) 1 1 C3412 ASM_DRX [33] 3.9nH L3402 B39_DRX [32] 885049 U3403 U3404 OUT IN 1.5nH 2 1 B40_DRX [32] G 5 L3421 L3432 SP3T LTE_RFIN2_MB2 [29,32] [26,30,31,32,33] LTE_BPI_OUT25 [26,30,31,32,33] LTE_BPI_OUT24 [26,30,31,32,33] LTE_BPI_OUT23 [26,30,31,32,33] LTE_BPI_OUT22 [30,31,32,33] LTE_BPI_OUT21 [30,31,32,33] LTE_BPI_OUT20 [30,31,32,33] LTE_BPI_OUT19 [26,30,31,32,33] LTE_BPI_OUT18 [26,30,31,32,33] LTE_BPI_OUT17 [26,30,31,32,33] [26,30,31,32,33] [26,30,31,32,33] [26,30,31,32,33] [26,30,31,32,33] [26,30,31,32,33] [26,30,31,32,33] [30,31,32,33] [30,31,32,33] [30,31,32,33] [26,30,31,32,33] [30,31,32,33] [30,31,32,33] [26,30,31,32,33] [26,30,31,32,33] [30,31,32,33] [26,30,31,32,33] LTE_BPI_OUT25 LTE_BPI_OUT24 LTE_BPI_OUT23 LTE_BPI_OUT22 LTE_BPI_OUT21 LTE_BPI_OUT20 LTE_BPI_OUT19 LTE_BPI_OUT18 LTE_BPI_OUT17 LTE_BPI_OUT16 LTE_BPI_OUT15 LTE_BPI_OUT14 LTE_BPI_OUT13 LTE_BPI_OUT12 LTE_BPI_OUT11 LTE_BPI_OUT10 LTE_BPI_OUT9 LTE_BPI_OUT8 LTE_BPI_OUT7 LTE_BPI_OUT6 LTE_BPI_OUT5 LTE_BPI_OUT4 LTE_BPI_OUT3 LTE_BPI_OUT2 LTE_BPI_OUT1 LTE_BPI_OUT0 LTE_BPI_OUT16 LTE_BPI_OUT15 LTE_BPI_OUT14 LTE_BPI_OUT13 LTE_BPI_OUT12 LTE_BPI_OUT11 LTE_BPI_OUT10 LTE_BPI_OUT9 LTE_BPI_OUT8 LTE_BPI_OUT7 LTE_BPI_OUT6 LTE_BPI_OUT5 LTE_BPI_OUT4 LTE_BPI_OUT3 LTE_BPI_OUT2 LTE_BPI_OUT1 LTE_BPI_OUT0 BPI0 BPI1 BPI2 BPI3 BPI4 BPI5 BPI6 BPI7 BPI8 BPI9 BPI10 BPI11 BPI12 BPI13 BPI14 BPI15 BPI16 BPI17 BPI18 BPI19 BPI20 BPI21 BPI22 BPI23 BPI24 BPI25 AT_SEL_DRX AT_SEL_MAIN1 AT_SEL_MAIN2_1 AT_SEL_MAIN2_2 NA NA B34B39_TX_SEL DCS_Notch_SEL NA NA B34B39_PA_EN 2G_TXM_VCTRL_A 2G_TXM_VCTRL_B 2G_TXM_VCTRL_C 2G_TXM_PA_ENABLE ANT_DRX_SP3T_V1 ANT_DRX_SP3T_V2 NA NA ANT_Main1_SP8T_V1 ANT_Main1_SP8T_V2 ANT_Main1_SP8T_V3 3P4T_V1 3P4T_V2 3P4T_V3 3P4T_V4 To LTE_VTCXO1 (0ohm to MT6339) VDD_RFSW MIPI (To MT6290/6339) LTE_DVDD18_MIPI [26,30,31,32] [26,30,31,32] [30,31,32] [30,31,32] LTE_MIPI0_SDATA LTE_MIPI0_SCLK LTE_MIPI1_SDATA LTE_MIPI1_SCLK LTE_MIPI0_SDATA [26,30,31,32] LTE_MIPI0_SCLK [26,30,31,32] LTE_MIPI1_SDATA [30,31,32] LTE_MIPI1_SCLK [30,31,32] <TITLE> TITLE: DOCUMENT NO.: REV: 34_RF_MT6169_RF_DRX <REV> A1 SIZED: Hardware DEPT. DEPARTMENT: COMPANY: DESIGNER: <DESIGNER> Last Saved Date: 2014-7-30 SHEET: 32 OF 33 ** ** * DRX ANT: 704~2700MHz ANT3601 C3606 R3601 1 ANT3602 1 1 ANT3603 ASM_DRX [32] L1 NF 33PF NF L3623 0 AT_SEL_DRX SKY13489 V1 Port 0 RF1 1 RF2 To LTE_VTCXO1 (0ohm to MT6339) VDD_RFSW BPI config. [26,30,31,32,33] LTE_BPI_OUT25 LTE_BPI_OUT25 [26,30,31,32,33] LTE_BPI_OUT24 LTE_BPI_OUT24 [26,30,31,32,33] LTE_BPI_OUT23 [26,30,31,32,33] LTE_BPI_OUT22 [30,31,32,33] LTE_BPI_OUT21 [30,31,32,33] LTE_BPI_OUT20 LTE_BPI_OUT23 BPI0 BPI1 BPI2 BPI3 BPI4 BPI5 BPI6 BPI7 BPI8 BPI9 BPI10 BPI11 BPI12 BPI13 BPI14 BPI15 BPI16 BPI17 BPI18 BPI19 BPI20 BPI21 BPI22 BPI23 BPI24 BPI25 AT_SEL_DRX AT_SEL_MAIN1 AT_SEL_MAIN2_1 AT_SEL_MAIN2_2 NA NA B34B39_TX_SEL DCS_Notch_SEL NA NA B34B39_PA_EN 2G_TXM_VCTRL_A 2G_TXM_VCTRL_B 2G_TXM_VCTRL_C 2G_TXM_PA_ENABLE ANT_DRX_SP3T_V1 ANT_DRX_SP3T_V2 NA NA ANT_Main1_SP8T_V1 ANT_Main1_SP8T_V2 ANT_Main1_SP8T_V3 3P4T_V1 3P4T_V2 3P4T_V3 3P4T_V4 LTE_BPI_OUT19 LTE_BPI_OUT18 LTE_BPI_OUT17 LTE_BPI_OUT16 LTE_BPI_OUT15 LTE_BPI_OUT14 LTE_BPI_OUT13 LTE_BPI_OUT12 ANT3606 ANT3605 ANT3604 LTE_BPI_OUT5 LTE_BPI_OUT4 LTE_BPI_OUT3 LTE_BPI_OUT2 LTE_BPI_OUT1 LTE_BPI_OUT0 1 1 LTE_BPI_OUT10 LTE_BPI_OUT9 LTE_BPI_OUT8 LTE_BPI_OUT7 LTE_BPI_OUT6 1 LTE_BPI_OUT11 C3602 MAIN2_ANT [31] 33PF NF [26,30,31,32,33] LTE_BPI_OUT3 [26,30,31,32,33] LTE_BPI_OUT2 [30,31,32,33] LTE_BPI_OUT1 [26,30,31,32,33] LTE_BPI_OUT0 Main2 ANT: 704~2170MHz AT_SEL_MAIN2_2 LTE_BPI_OUT3 [26,30,31,32,33] LTE_BPI_OUT22 LTE_BPI_OUT21 LTE_BPI_OUT20 L3601 [30,31,32,33] LTE_BPI_OUT19 [26,30,31,32,33] LTE_BPI_OUT18 [26,30,31,32,33] LTE_BPI_OUT17 [26,30,31,32,33] LTE_BPI_OUT16 [26,30,31,32,33] LTE_BPI_OUT15 [26,30,31,32,33] LTE_BPI_OUT14 [26,30,31,32,33] LTE_BPI_OUT13 [26,30,31,32,33] LTE_BPI_OUT12 [26,30,31,32,33] LTE_BPI_OUT11 [26,30,31,32,33] LTE_BPI_OUT10 [30,31,32,33] LTE_BPI_OUT9 [30,31,32,33] LTE_BPI_OUT8 [30,31,32,33] LTE_BPI_OUT7 [26,30,31,32,33] LTE_BPI_OUT6 [30,31,32,33] LTE_BPI_OUT5 [30,31,32,33] LTE_BPI_OUT4 AT_SEL_MAIN2_1 <TITLE> TITLE: REV: 36_RF_AT DOCUMENT NO.: <REV> A1 SIZED: Hardware DEPT. DEPARTMENT: COMPANY: DESIGNER: <DESIGNER> Last Saved Date: 2014-7-30 SHEET: 33 OF 33 </pre><hr>Source Exif Data: <br /><pre>File Type : PDF File Type Extension : pdf MIME Type : application/pdf PDF Version : 1.5 Linearized : Yes Author : huangzhongxi Create Date : 2014:07:30 09:35:10+08:00 Modify Date : 2014:07:30 09:35:10+08:00 XMP Toolkit : Adobe XMP Core 4.2.1-c041 52.342996, 2008/05/07-20:48:00 Format : application/pdf Creator : huangzhongxi Title : 96523_1_13_CSFB_SKY77754_05161406 Creator Tool : PScript5.dll Version 5.2.2 Producer : Acrobat Distiller 9.0.0 (Windows) Document ID : uuid:bbd3c87b-74c2-41a4-8386-e68b0cd79239 Instance ID : uuid:6a9a8ae8-2127-4387-9142-a76c9f37a699 Page Count : 33 </pre> <small>EXIF Metadata provided by <a href="https://exif.tools/">EXIF.tools</a></small> <div id="ezoic-pub-ad-placeholder-110"> <script async src="//pagead2.googlesyndication.com/pagead/js/adsbygoogle.js"></script> <!-- usermanual link ad --> <ins class="adsbygoogle" style="display:block" data-ad-client="ca-pub-0545639743190253" data-ad-slot="6172135303" data-ad-format="link"></ins> <script> (adsbygoogle = window.adsbygoogle || []).push({}); </script> </div> </div> <div id="catlinks" class="catlinks catlinks-allhidden" data-mw="interface"></div> <div class="visualClear"></div> </div> </div> <div id="mw-navigation"> <h2>Navigation menu</h2> <div id="mw-head"> <div id="p-personal" role="navigation" class="" aria-labelledby="p-personal-label"> <!-- <div id="p-search" role="search"> <form action="https://usermanual.wiki/search.php" id="searchform"> <div id="simpleSearch"> <input type="search" name="search" placeholder="Search UserManual.wiki" title="Search UserManual.wiki [ctrl-option-f]" accesskey="f" id="searchInput" tabindex="1" autocomplete="off"><input type="hidden" value="Special:Search" name="title"><input type="submit" name="go" value="Go" title="Find a User Manual" id="searchButton" class="searchButton"> </div> </form> </div>--> <ul> <li id="pt-mycontris"><a href="https://usermanual.wiki/upload" title="Upload User Manual" accesskey="y">Upload a User Manual</a></li> </ul> </div> <div id="left-navigation"> <div id="p-namespaces" role="navigation" class="vectorTabs" aria-labelledby="p-namespaces-label"> <h3 id="p-namespaces-label">Versions of this User Manual:</h3> <ul> <li id="ca-nstab-main"><span><a href="https://usermanual.wiki/Manual/HUAWEIG620Schematic.1670420133" title="User Manual Wiki" accesskey="c">Wiki Guide</a></span></li> <li id="ca-nstab-main"><span><a href="https://usermanual.wiki/Manual/HUAWEIG620Schematic.1670420133/html" title="HTML" accesskey="c">HTML</a></span></li> <li id="ca-nstab-main"><span><a href="https://usermanual.wiki/Manual/HUAWEIG620Schematic.1670420133/amp" title="Mobile AMP" accesskey="c">Mobile</a></span></li> <li id="ca-nstab-main" class="selected" ><span><a href="https://usermanual.wiki/Manual/HUAWEIG620Schematic.1670420133/help" title="Discussion / FAQ / Help" accesskey="c">Download & Help</a></span></li> </ul> </div> </div> <div id="right-navigation"> <div id="p-views" role="navigation" class="vectorTabs" aria-labelledby="p-views-label"> <h3 id="p-views-label">Views</h3> <ul> <li id="ca-view"><span><a href="#">User Manual</a></span></li> <li class="selected" id="ca-edit"><span><a href="https://usermanual.wiki/Manual/HUAWEIG620Schematic.1670420133/help" title="Ask a question" accesskey="e">Discussion / Help</a></span></li> </ul> </div> </div> </div> <div id="mw-panel"> <div id="p-logo" role="banner"><a class="mw-wiki-logo" href="https://usermanual.wiki/Main_Page" title="Visit the main page"></a></div> <div class="portal" role="navigation" id="p-navigation" aria-labelledby="p-navigation-label"> <h3 id="p-navigation-label">Navigation</h3> </div> <div class="portal" role="navigation" id="p-tb" aria-labelledby="p-tb-label"> </div> </div> </div> <div id="footer" role="contentinfo"> <ul id="footer-info"> <li id="footer-info-lastmod">© 2026 UserManual.wiki</li> </ul> <ul id="footer-places"> <li id="footer-places-privacy"><a href="https://usermanual.wiki/ContactUs" title="UserManual.wiki:Contact Us">Contact Us</a></li> <li id="footer-places-about"><a href="https://usermanual.wiki/DMCA" title="UserManual.wiki:DMCA">DMCA</a></li> </ul> <ul id="footer-icons" class="noprint"> <li id="footer-poweredbyico"> </li> </ul> </div> </div></body></html> <script src="/cdn-cgi/scripts/7d0fa10a/cloudflare-static/rocket-loader.min.js" data-cf-settings="01139312680864003f614f51-|49" defer></script>