Panasonic G50 Schematics
User Manual: Manual Panasonic - Schematics & Service Manuals PDF
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VSYN [8] [2] [1] VRF [8] RAMP RF_TXEN CPL VTCXO PCSRX DCSRX [8] [8] GSMRX [8] 33p C1143 C1180 15P 12p L1152 NM C1145 51k R1193 C1141 39p MM8430-2600 J1161 GND 6 GND 5 GND 4 GND 3 9 10 16 P_RX D_RX G_RX U1141 C1181 68p R1190 51.1 L1141 NM C1185 NM modify0512 L1161 15nH 3n9 L1142 0.5p C1144 modify0529 L1162 15nH JP 2 OUT IN 1 AN1161 910 R1191 C1182 150p R1192 51.1 SHS-L090TL 1 2 3 7 6 5 G NC VAPC VCC 5 6 7 8 C1172 10p C1171 33p R1131 51 R1196 JP C1108 10n 33p C1155 3 1 6 E3D C1107 100p C1106 NM 4 5 – 11–1 – JP R1197 12 11 C1105 NM 10 GND C1103 10n 1u/0603 C1174 4 3 2 1 3 1 6 C1102 33p PEMB3 R1198 1k ENA VAPC MAS9122 ENBC OUTC OUTA 4 5 2 8 5 6 7 1k2 R1199 10n/X7R C1177 VREF GND VCC 2 3 4 33p C1116 NM C1115 C1101 - 220uF R1103 1 + E3D 10u/0805 C1178 2 R1102 E3D 220 R1101 C1114 JP R1142 1k C1156 12p CX77314 VAPC Vcmos BS U1101 BEAD B1100 OUTB 4.7K 4.7K C1113 33p U1172 U1173 GND VCC C1110 C1112 NM 10n 1u/0603 C1175 4.7K 4.7K 6.8p E3D 2 L1101 JP C1111 PEMB3 U1171 L1102 4.7nH C1184 33p LDC15D19 U1131 G/I G D/I C1131 NM G/O G D/O U1103 AD8315 FLTR VSET ENBL RFIN 10p C1173 4 14 R1195 JP 4 3 2 1 VC3 VC2 VC1 11 C1157 NM 22p modify0512 E3D C1154 CPL DCS/PCS OUT 13 8 GND GND 14 C1161 2 ANT 13 G_TX 7 D/P_TX GND GND GND GND GND GND GND 1 3 5 6 8 12 15 4 ISO CPL 8 9 GSM OUT GND GND 15 7 16 6 VCC VCC 5 DCS/PCS IN GSM IN 1 4 modify0512 E3B 3 11.1. Circuit Diagram of RF Band-1 3 11. CIRCUIT DIAGRAM 4 1 2 C1176 1u/0603 PA_EN VTX[ Mode G_TX D/P_TX G/D_RX P_RX TRSW_PR TRSW_DT TRSW_GT GSMTX VAPC BS DCSTX VBAT Vc3 0 0 0 1 [1] 8] Vc1 Vc2 1 0 0 1 0 0 0 0 [1] [1] [1] [8] [8] [8] C1252 180R TP9 TP10 C1254 18p C1253 33p 1 2 1 2 DCSRX PCSRX GSMRX VRF RXEN1 RF_TXEN BS VTCXO DCSTX GSMTX 1 VTX 1 VRF B7740 IN G G OUT U1272 B7744 IN G G OUT 4 3 4 3 4 3 10 15p 12p C1267 JPE3C modify 0529 L1261 8n2 L1272 3n9 L1271 3n9 C1271 E3C 0p5 modify 0529 C1272 0p5 C1265 15p C1262 R1295 JP C1250 2p7 C1247 10p L1201 180n/0603 C1204 39p/NPO E3B modify0522 R1203 220/1% C1248 33p C1266 R1206 51 C1205 100p R1207 NM SAFSE942 IN G G OUT U1271 1 2 U1261 510 390 R1205 R1204 C1202 39p/NPO R1202 510/1% C1249 33n R1231 C1203 2.2n/X7R L1241 27n 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 C1245 22p RXENA TXENA PCO VCXO_EN PDETVCC VCC1 TXCPO TXINP LNA900IN GNDLNA900 LNA1800IN PDET LNA1900IN NC NC C1246 100n C1211 22p L1211 82n C1213 NM – 11–2 – C1212 NM C1214 C1215 470p 470p C1216 100n CX74063 VDDBB LE CLK DATA XTALTUNE SXENA VCCFN_CP UHFCPO GNDFN XTAL VCCF VCCD GNDD XTALBUF LPFADJ 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 U1201 R1225 5k6 C1242 10u C1221 22p del C1222 E3B R1221 39k/1% C1229 220p C1241 0.1u C1244 100n 1 1 2 3 1 R1223 10 R1222 10 R1224 10 NM R1296 C1223 C1224 22p 100n 100n R4 E3D C1226 10p C1227 680p 1 R1226 2k C1228 8n2/PC B1241 BEAD C1243 22p TP5 TP6 TP7 B1222 BEAD R1291 NM VTCXO R1292 100nF 1 4 B1221 BEAD C1225 1n GND Vc o/p Vcc U1291 modify0522 E3B 1 TP1 TP2 TP3 TP4 1 11.2. Circuit Diagram of RF Band-2 1 56 55 54 53 52 51 50 49 48 47 46 45 44 TXVCOTUNE TX1800/TX1900 TX900 VCCTXVCO VCC4 RXIP RXIN RXQP RXQN VCC3 VCCUHF UHFTUNE UHFBYP PAVAPC BBVAPC TXIP TXIN TXQP TXQN TXIFP TXIFN VCC2 CAPIP CAPIN CAPQP CAPQN 16 17 18 19 20 21 22 23 24 25 26 27 28 R1297 JP TXQN TXQP TXIN TXIP VRF 13MHz_BB BEAD R1293 NM C1291 VTX 10k SXEN C1230 100n R1232 LE CLK DATA VSYN VRF RXIP RXIN RXQP RXQN TP8 R1294 JP 1 3 2 1 AFC C102 C103 TDO 1 1 1 TDI 1 TP123 TP_GPIO32 TMS 1 TCK R102 10M/0603R 1 1 1 1 TP128 GPCS1 TP102 TP_GPIO14 TP105 TP_GPIO16 TP107 TP_GPIO17 TP108 TCK TP109 TMS TP110 TDI TP111 TDO 1 TP104 TP_GPIO9 TP125 TP_GPIO11 1 1 TP126 TP_GPIO5 X101 MC-146 TBD C113 0.1U /0402C C104 C105 C106 C107 C108 C109 C110 C111 TBD C114 ADD[1..22] LCD_CTL YMU_CS LCD_NRST LCD_ CS BL_KEY BL_LC D YMU_AVCC _ON VIB_ON PJ_FUNC_ SEL GPIO10 PJ_ACC_ IN MIC_ON YMU_IRQ EOC CHG_GAT E_IN LC D_ID CH G_EN CHG_DET NRESET POW ER_ON SYS_ PWR_ON BBCLK CLKON KEYR OW_0 KEYR OW_1 KEYR OW_2 KEYR OW_3 KEYR OW_4 KEYC OL_0 KEYC OL_1 KEYC OL_2 KEYC OL_3 KEYC OL_4 ADD[1..22] ADD1 ADD2 ADD3 ADD4 ADD5 ADD6 ADD7 ADD8 ADD9 AD D10 AD D11 AD D12 AD D13 AD D14 AD D15 AD D16 AD D17 AD D18 AD D19 AD D20 AD D21 AD D22 L14 F12 L13 M12 M5 C5 A7 D11 D10 B12 C11 D9 B11 A11 C10 D8 A10 C9 C7 B9 A9 B8 A8 D6 B7 H14 H13 J12 J11 N14 L12 G14 B3 A3 B2 E14 A6 F4 D4 B5 A5 C4 E4 B4 A4 C3 H4 J3 J2 J4 K3 K2 K4 L4 L1 L3 L5 M1 M2 N1 P1 N2 P2 N3 M3 P4 N4 M4 P5 VCO RE AD6525 GPIO_32(WAIT) SM_SW_SYNC (GPO_10) GPCS1 GPCS0 nDISPLAYCS(LCDCTL) BACKLIGHT1 (GPO_23) BACKLIGHT0 (GPO_22) GPIO_0 GPIO_1 GPIO_2 GPIO_3 GPIO_4 GPIO_5 GPIO_6 GPIO_7 GPIO_8 GPIO_9 GPIO_10 GPIO_11 GPIO_12 GPIO_13 GPIO_14 GPIO_15 GPIO_16 GPIO_17 GPIO_18 GPIO_19 GPIO_20 GPIO_21 RESET CLKIN CLKON OSCOUT OSCIN PWRON GSM_SW_DRV (GPO_11) KEYPADROW0 KEYPADROW1 KEYPADROW2 KEYPADROW3 KEYPADROW4 KEYPADCOL0 KEYPADCOL1 KEYPADCOL2 KEYPADCOL3 KEYPADCOL4 ADD0 ADD1 ADD2 ADD3 ADD4 ADD5 ADD6 ADD7 ADD8 ADD9 ADD10 ADD11 ADD12 ADD13 ADD14 ADD15 ADD16 ADD17 ADD18 ADD19 ADD20 ADD21 ADD22(nDISPLAYCS) U101 0.1U /0402C 0.1U /0402C 0.1U /0402C 0.1U /0402C 0.1U /0402C 0.1U /0402C 0.1U /0402C SIMVCC VMEM H1 P7 K14 C8 VCC1 VCC2 VCC3 VCC4 C101 L9 VSIM 0.1U /0402C 0.1U /0402C 0.1U /0402C L2 N5 N9 N13 VMEM1 VMEM2 VMEM3 VMEM4 VMEM – 11–3 – C112 0.1U /0402C VMEM R101 (GPO_2) (GPO_4) (GPO_7) (GPO_8) (GPO_9) JTAGEN SIMDATAOP SIMCLK SIMRESET (GPIO_23) SIMSUPPLY (GPIO_24) SIMVPROG (GPIO_22) USC0 USC1 USC2 USC3 USC4 USC5 USC6 BSDO BSOFS BSDI BSIFS VSDI VSDO VSFS CLKOUT CLKOUT_GATE (VBCRESET)GPO_24 (ARSM)GPO_5 (ATSM)GPO_6 ASDI ASDO ASFS TX_GSM (GPO_16) ADD23(TX_DCS)GPO_17 (OTH_EN)GPO_18 (OTH_VLO_EN)GPO_19 (OTH_DATA)GPO_20 (OTH_CLK)GPO_21 (RXON)GPO_0 (TXON)GPO_1 GPO_3 TXPA PA_NEGBIAS TXPHASE DCS_SW_SYNC DCS_SW_DRV RD HWR LWR WE ROMCS RAMCS DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 DATA8 DATA9 DATA10 DATA11 DATA12 DATA13 DATA14 DATA15 0R/0402R VRTC E3 VPEG1 VCO RE B14 B10 C6 D5 VEXT1 VEXT2 VEXT3 VEXT4 GND1 GND2 GND3 GND4 GND5 GND6 GND7 GND8 GND9 GND10 GND11 J1 K1 P3 L6 L8 P12 L11 C13 A12 D7 B6 A2 VDDRTC VSSRTC D3 K11 J13 K12 L10 K13 J14 C14 D12 A14 A13 E11 C12 B13 F3 G4 G2 G1 G3 H3 H2 D1 D2 E1 A1 C1 E2 F1 F2 E13 G11 E12 D14 D13 F11 B1 C2 G12 G13 H12 F14 F13 H11 M11 N12 P13 P14 M13 M14 N6 P6 M6 N7 M7 L7 P8 N8 M8 P9 M9 P10 N10 M10 P11 N11 + 1 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D[0..15] SIM_IO SIM_CLK SIM_RESET SIM_ON SIM_PROG US C0 US C1 US C2 US C3 US C4 US C5 US C6 BSDO BSOFS BS DI BSIFS VS DI VSDO VSFS CLK_OUT CLKOUT_GATE VBC_RESET ARSM ATSM AS DI ASDO ASFS RD HWR LW R WE ROMCS RAMCS TP122 TP_JTAGEN BAT101 SEIKO XH414H TBD R107 TBD R103 VMEM RF_TXEN SXEN LE DATA CLK RXEN TXEN PA_EN TRSW_DT TRSW_PR TRSW_GT RXEN1 D[0..15] 2 4 1 3 2 4 1 3 11.3. Circuit Diagram of GSM Processor 1 1 R105 100K/0402R R106 100K/0402R VMEM TP_CLKOUT TP101 RXEN TP124 1 1 TP118 TP_USC6 TP116 TP_USC5 TP114 TP_USC4 1 1 TP112 TP_USC3 US C1 US C2 TP115 TP_USC2 TP113 TP_USC1 1 1 TP106 TP_USC0 TP130 TX 1 1 TP129 RX 1 TP206 BSDO TP208 BSOFS TP207 BSIFS TP205 BS DI 1 1 1 1 VBC_RESET TXEN RXEN CLKOUT_GATE CLK_OUT ATSM ARSM BSIFS BS DI BSOFS BSDO VSFS VS DI VSDO ASDO ASFS AS DI TP_VBCRST 1 TP201 R201 100K/4P2R R207 100K/4P2R B4 A3 B2 B1 C2 C1 K1 K4 J4 K2 J2 K3 J3 E2 F1 F2 G2 D2 D1 E1 H1 H2 J1 IDACOUT IDACREF TDI TDO TMS TCK RESET TXON RXON MCLKEN MCLK ATSM ARSM BSOFS BSDO BSIFS BSDI VSFS VSDO VSDI ASDI ASFS ASDO U201 100K/0402R R213 VCO RE VINAUXP VINAUXN VINNORP VINNORN REFOUT REFCAP AFCDAC RAMPDAC IRXP IRXN QRXP QRXN ITXP ITXN QTXN QTXP B7 B6 A4 B5 A5 A6 J6 K9 K6 – 11–4 – AUXADC6 AUXADC5 AUXADC4 AUXADC3 AUXADC2 AUXADC1 BUZZER VOUTAUXP VOUTAUXN K8 K7 H10 G10 J10 K10 A7 A8 A10 H9 E10 D10 C10 B10 F9 E9 C9 D9 0.1U /0402C C213 C204 0.1U /0402C ADC5 0.1U /0402C C216 VANA 2.2U /0603C R210 100K/0402R /1% Charging T emp VOUTAUXP VOUTAUXN VOUTNORP VOUTNORN VINAUXP VINAUX N C205 BUZZ ER 1 1 C207 C215 TP204 ADC6 TP203 ADC5 PCB_Temp VANA TP_BUZZER TP202 RXIP RXIN RXQP RXQN TXIP TXIN TXQN TXQP 0.1U /0402C 0.1U /0402C 0.1U /0402C C206 VCO RE BATTEMP 0.1U /0402C C218 AFC RAMP VINNORP VINNORN 0.1U /0402C C212 R206 100K/0402R C214 10nF/ 0402C 0.1U /0402C C203 VANA ADC6 C202 0.1U /0402C C201 2.2U /0603C VOUTNORP VOUTNORN VMEM AD6521 G1 DVDD2 2 4 1 3 2 4 1 3 F10 AVDD1 NC(MICCAP) NC(REFCAP2) J8 J9 B9 A9 AVDD2 AGND4 AGND3 AGND2 AGND1 AVDD3 B3 J7 B8 G9 A1 DVDD1 DGND1 DGND3 A2 J5 K5 DVDD3 VANA 1 VMEM 0.1U /0402C C217 NTC 11.4. Circuit Diagram of Voiceband, Baseband and Codec BAT_VOLTAGE VANA R212 100K/N TC/0402R R211 200K/0402R /1% 100K/N TC/0402R R209 R208 200K/0402R /1% NTC P_JACK CON3 02 2 1 BATTEMP 2 1 TP_GND TP302 1 TP_VBAT F302 3 2 1 FULSE/0603 C310 2.2U /25V/0805C C325 39pF T301 2 1 1 1 CRS03 U312 BAT_CON GND BAT_TEMP VBAT 2 2 1 CON3 01 R310 10K U306 BLM55C9V1 4 2 U308 6 EMD2 3 5 CLKON R311 TBD C322 0.1U C309 TBD 1 C301 4.7U /0805C – 11–5 – 1 GND A Y VCC 4 5 1M/0402R R307 U301 GATEDR ISENSE CHRIN GATEIN SIMVSEL CHGEN TCXOEN SIMEN ROWX PWRONKEY PWRONIN VRTCIN BATSNS VBAT2 VBAT 2 R3 TBD C318 68pF VBAT REFOUT RESCAP RESET CHRDET EOC VTCXO VSIM VMEM VCORE VAN VRTC MVBAT 2.2uH /060 3R L301 VTCXO C323 0.1U CRS03 U311 C317 10N/040 2C 1 ADP3522XCP-3.0 9 12 7 10 8 14 28 1 31 30 29 2 4 19 22 C312 10N/040 2C U305 NC7SZU04P5X 3 2 D U309 SI3443DV 1 2 5 6 C321 0.1U 4 R303 0.3/0805R CHG_GAT E_IN SIM_PROG CH G_EN CLKON SIM_ON KEYR OW_4 VBAT C302 0.1U /0402C R301 100K/0402R TP303 POW ERON_ KEY VBAT POWERON_ IN 10N/0402 R314 1 TP305 CHG_GAT E_IN U307 FDC640P 4 1 2 5 6 1 POWER_KEY R302 100K/0402R TP306 CH G_EN 3 DAN2 22 13MHz_BB R309 10K C319 0.01U /040 2C 1 SYS_ PWR_ON 1 2 U302 POW ER_ON 22 K 27 TP301 22 K VBAT 3 AGND 11.5. Circuit Diagram of Power Management System 3 24 32 17 NC NC NC DGND 11 26 15 16 6 13 25 18 20 21 23 3 5 18pF C324 TP304 EOC NRESET C311 0.1U /0402C 0R R313 VTCXO SIMVCC VMEM VCO RE VANA VRTC BAT_VOLTAGE 1 BBCLK CHG_ DET EOC VMEM VRTC CHR_ DET 1 C304 4.7U /0805C C307 2.2U/0805 SIMVCC TP307 C306 4.7U /0805C C303 0.1U /0402C VANA C308 1U/0603C VTCXO C305 4.7U /0805C VCO RE VMEM D[0..15] 8 7 6 5 VMEM GPIO10 NRESET RD HWR LW R WE ROMCS RAMCS 0R/8P4R R401 D[0..15] 0R/0402R TBD R407 R406 WP -ACC CI Os CI Of CE2 s D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 G8 E5 D5 H3 D4 C4 C6 H2 J2 C5 K6 H9 D6 J3 G4 K4 H5 H6 K7 G7 J8 K3 H4 J4 K5 J7 H7 K8 H8 C401 AMD (64+16PS) SA RY/BY RESET OE UB LB WE CEf CE1s WP/ACC CIOs CIOf CE2s DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15/A-1 U401 0.1U /0402C J5 J6 F9 ADD1 ADD2 ADD3 ADD4 ADD5 ADD6 ADD7 ADD8 ADD9 AD D10 AD D11 AD D12 AD D13 AD D14 AD D15 AD D16 AD D17 AD D18 AD D19 AD D20 AD D21 AD D22 – 11–6 – SIM_CLK SIM_RESET ADD[1..22] R404 150R/1%/0402 TP_SIMCLK TP403 C405 22pF TP_SIMRST TP402 TP_SIMVCC 1 TP401 C402 TBD SIMVCC CLK RST VCC J401 C403 0.1U /0402C 1 3 5 R405 100K/0402 2 4 6 SIM SOCKET I/O VPP GND R403 10K/0402 C404 33pF 1 TP_SIMIO NC0 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 G2 F2 E2 D2 F3 E3 D3 C3 C7 E7 F7 C8 D8 E8 F8 D9 G9 F4 E4 D7 E6 E9 ADD[1..22] TP404 VCCf VCCs VSS VSS 1 2 3 4 VMEM 1 11.6. Circuit Diagram of Memory & SIM 1 G3 J9 1 SIM_IO TP405 GND YMU_AVCC _ON 0R/0402 R522 C527 TBD/0402 N O I C G 100K U505 4 5 ADD[1 ..2 2] YMU_CS RD WE YMU_VIB YMU_IRQ NRESET CLK_OUT C513 0.1U /0402C ADD2 C528 0.01U VR EF C519 0.1U C526 4.7U/0805 YMU_AVCC C512 0.1U YMU_AVCC C525 2.2U/0603 ADD[1..22] C530 0.1U /0402C VMEM VOUTAUXN SC1563ISK-3.0 1 2 3 2 19 3 4 1 8 16 32 7 5 6 EXT1 EXT2 /IRQ /RST CLKI VSS SPVSS YMU762(MA3L2) SDOUT(IOVDD) VDD IFSEL(NC) PLLC U506 C529 TBD VOUTNORN VOUTNORP 9 VREF 10 11 18 17 14 13 20K/0402R R508 – 11–7 – HPOUT-L/MONO HPOUT-R SPOUT2 SPOUT1 EQ3 EQ2 10N/040 2C C517 I/O 6 I/O 4 GND2 1 6 4 5 D[0..15] TP503 HPOUT_R HPOUT 200P/0402C C518 0.1U /0402C C521 33P/0402C C532 U507 ESDA I/O 3 GND1 I/O 1 D[0..15] 47K/0402R R509 10K/0402R R514 R510 TBD C520 TBD/0402 C523 33P/0402C 3 2 1 C531 C524 SPK1 33P/0402C 33P/0402C 0R/0402R R504 0R/0402R R503 SDIN(/CS) SCLK(/RD) /WR SYNC(A0) 29 31 28 30 VBAT 15 SPVDD R521 12 EQ1 D0 D1 D2 D3 D4 D5 D6 D7 27 26 25 24 23 22 21 20 D0 D1 D2 D3 D4 D5 D6 D7 33P/0402C C515 BUZZ ER TBD/0402C C522 SPK2 T503 - B (TBD) 1 2 C516 33P/0402C C511 TBD/0402C SPK2 SPK1 TP502 TP_SPK-N 1 T504 - B (TBD) 1 2 T502(TBD) 1 2 11.7. Circuit Diagram of Audio 1 T501(TBD) 1 2 TP501 TP_SPK-P SPEAKER LS501 1 RECEIVE R - B LS502 VINAUXN VINAUXP VOUTAUXP HPOUT 0.1uF C614 MIC_ON 33P/0402C C610 C624 100P/0402 0R R611 N O I C G 4 5 0.1U 33P/0402C C611 R629 TBD/0402R C620 0R R620 R610 1M R609 1M YMU_AVCC LP2985AIMX5-2.5 R615 47K C629 2.2U /0603C 1 2 3 R623 0R C602 10U/0805C TBD/0402C C612 R606 1.2K /1% R630 0R MIC_PWR 10uF/0805 C628 10uF/0805 C616 C630 2.2uF/0603 10N/040 2C C601 2.4K/0402R C622 0.1U /0402C R625 0R C626 10U/080 5C MIC_PWR US C1 C627 0.1U /0402C R643 0R 3 2 1 0 1 S A VCC – 11–8 – EXT_MIC NC7SB3157 B0 GND B1 U603 PJ_FUNC_ SEL 4 5 6 R642 TBd US C6 US C2 PJ_ACC_ IN VINNORN VINNORP 100K R640 C615 33P/0402C VMEM 8.2K R641 0.1U C631 C607 33P/0402C C623 100P/0402 R639 1MR C608 33P/0402C 0.1U C621 T607 - B (TBD) 1 2 MIC_PWR R632 TBD R633 100K/0402R VMEM MIC/ RX 3 2 1 TX I/O 6 I/O 4 GND2 I/O 4 GND2 I/O 6 GND 4 5 6 U605 ESDA I/O 3 GND1 I/O 1 U604 - B ESDA I/O 3 GND1 I/O 1 3 2 1 C603 0.1U /0402C SPK R637 100K/0402R R603 0/0402R C605 TBD/0402C R602 4.7K/0402R MIC_PWR TBD/0402C C606 0R R621 R628 TBD/0402R R624 0R T604 - B (TBD) 1 2 R626 T605 - B (TBD) 1 2 U601 T606 - B 1 2 VBAT T601 - B (TBD) 1 2 T602(TBD) 1 2 11.8. Circuit Diagram of Audio 2 T603(TBD) 1 2 4 5 6 MIC/RX GND TX SPK ACC_ IN 1 2 TP_MIC TP601 1 4 6 5 3 2 PHONEJ ACK-B J601 MICROPH ONE - B MIC601 1 D702 LE D - B D701 LE D - B BL_KEY LE D - B LE D - B R714 200R /8P4R - B D704 D703 V_LED JP702 1 2 3 N/C KEYROW_3 KEYCOL_4 KEYROW_0 KEYCOL_3 KEYROW_1 KEYCOL_2 KEYROW_2 KEYCOL_1 KEYCOL_0 POWER_KEY GND N/C U706 C736 2.2U /0603C 1 2 3 N O I C G U703 4 5 LE D - B LE D - B R702 TBD - B D707 D706 LE D - B D709 10N/040 2C C735 R705 1K/0402R - B 1 1 2 6 E2 B2 C2 FFB2222A - B E1 B1 C1 U702 R713 100R /1%/0402R - B LE D - B D710 M701 TP24 LCD_NRST TP25 WE 3 4 5 + - A D[0..15] 1 1 – 11–9 – 3 TP12 Vibrator SIG 100R /0402R - B R706 1 TP29 VIB_PW R ADD2 DAN222 - B 1 2 U705 TP21 D8 TP20 D9 TP19 D10 TP18 D11 C745 R710 100K R709 100K YMU_VIB VIB_ON R711 TBD R712 TBD 6 5 3 4 EN CX8 VIN CD4 U704 2 9 10 7 1 V_LED 18pF C748 SC600BIMLTR, 5V_ 60M A CF1+ CF1CF2+ CF2- VOUT 18pF C744 C747 C743 C746 C742 1 1 1 1 1 1 1 1 1 1 1 TBD - B 0.1uF - B TBD - B TBD - B TBD - B 18pF C741 D15 D14 D13 D12 D11 D10 D9 D8 TP13 LCD_CTL TP22 LCD_ CS TP23 ADD2 TP17 D12 TP16 D13 TP15 D14 TP14 D15 LCD_CTL LCD_ CS C754 10U/080 5C VBAT WE R708 TBD - B LCD_PWR 1SS355 D713 1 D[0..15] ADD[1..22] BL_LC D 10K - B R707 ADD[1 ..2 2] R704 8.2R/0805R - B VBAT LCD_NRST TP28 LCD_ PWR LG COIN M OTOR C737 10U/0805C LCD_PWR R701 100R /1%/0402 R - B LE D - B D708 LP2985AIMX5-3.0 VBAT KEYPAD_HOT BAR - B 12 1 2 3 4 5 6 7 8 9 10 11 13 VBAT LE D - B D705 1 2 3 KEYR OW_3 KEYC OL_4 KEYR OW_0 KEYC OL_3 KEYR OW_1 KEYC OL_2 KEYR OW_2 KEYC OL_1 KEYC OL_0 POWER_KEY 8 7 6 5 1 2 3 4 VMEM 11.9. Circuit Diagram of User Interface 8 7 6 5 1 2 3 4 2 1 GND 8 33pF C750 C739 1U/0603C C738 1U/0603C 18pF C749 LC D_ID 18pF C753 C755 TBD TP30 V_LED 33pF C752 1 C740 1U/0603C TP27 GND 1 33pF C751 C701 VEE VEE VDD VDD SEL68 VSS RD(E) D7 D6 D5 D4 D3 D2 D1 D0 CS RS RESB WR VSS VSS CA_LED CA_LED AN_LED AN_LED N/C(VOUT) U701 C733 0.1U /040 2 -B C7 33P/0402C R716 TBD R715 0R 1 TP701 LCD_ ID Wintek DX1209K-6C LWa - B 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 2.2U /060 3 -B LCD_PWR 11.10. Circuit Diagram of Keypad SW716 KEY [#] SW711 KEY [0] SW706 KEY [*] SW701 2 2 2 2 1 2 1 1 1 1 2 2 2 2 KEY [SEND] SW717 KEY [9] SW712 KEY [8] SW707 KEY [7] SW702 POWERKEY & END SW718 SOFTKEY_RIGHT 1 1 1 1 1 1 1 KEY [6] SW713 KEY [5] SW708 KEY [4] SW703 2 2 2 1 1 1 2 2 2 – 11–10 – KEY [3] SW714 KEY [2] SW709 KEY [1] SW704 1 1 1 2 2 2 SOFTKEY_LEFT SW715 KEY_[DOWN] SW710 KEY_[UP] SW705 POWER_KEY KEYROW_3 KEYROW_2 KEYROW_1 KEYROW_0 KEYCOL_0 KEYCOL_1 KEYCOL_2 KEYCOL_3 KEYCOL_4 D2 R300 640 0 S3KV 84VD23381FJ-80 AD6525ACA ADP3522 N 43 H L00A – 12–1 – 227 LUNA 600B Z3 Z1 12.1. Main PCB Z3 9122 12. LAYOUT DIAGRAMS 26 800Z 6330 Y762C S3KV Z1 Z1
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File Type : PDF File Type Extension : pdf MIME Type : application/pdf PDF Version : 1.3 Linearized : No Page Count : 11 Producer : Acrobat Distiller 4.0 for Windows Create Date : 2004:01:22 12:43:59 Modify Date : 2005:10:21 00:11:13-03:00EXIF Metadata provided by EXIF.tools