Midland Radio SD125V3 Data Radio User Manual Design Docs

Midland Radio Corporation Data Radio Design Docs

users manual

Topaz3, LLC. 10828 N.W. Airworld Dr. Kansas City, MO 64153 Tel: 816-891-6320 Fax: 816-891-8815August 2002UserGuideSD 125V3 DATA RADIO
SD 125V3Page -1-August 2002THEORY OF OPERATIONTHEORY OF OPERATIONThe SD 125V3 radio is comprised of two PCB's (an RF PCB and a digital PCB).These boards are connected with an 18 pin female and male connector. The digitalboard is interfaced with external data equipment through the 9 pin d-sub male connec-tor, which controls the radio and data receiving and sending. DIGITAL CIRCUITThe digital circuit is charged to be control for all of the signal path and set the frequen-cies to be set and selecting the desired channel.TX-Signal circuit The TX data signal comes from Pin 2 of Con 401, and goes through U404D. The TX-signal is amplified by U406C. The TX-signal is filtered by U405A & B which is a 4'thorder low pass filter, therefore, the filtered signal supply to the RF board for TX modu-lation.RX-Signal Circuit The RX- data signal comes from the RF board, which is connected with pin 10 of Con403. The RX-signal is switched by U404A and adjusted by RV403 and amplified byU407. The amplified signal goes to pin10 of Con 401.RSSI Detector From the RF board, the RSSI (Received Signal Strength Indicator ) signal comes toU403A & B through R461. The pulse is injected from pin 5 of U403B every 1 ms andC451 is discharged. After then, it begins to be charged by R464. Simultaneously,RSSI signal is input to pin 7 of U403A and those signals are compared. The comparedsignal is output from U403A. Pin 1 and the CPU detects the pulse width. The pulsewidth is varied by RSSI DC voltage. Therefore, the CPU determines the carrier detec-tion .EEPROM RX. TX channel and RSSI detection level as well as other data from the programmerare stored in the EEPROM. The data stored is retained without power supplied. Thisis a non-volatile memory . The EEPROM may have information re-programmed orerased. U402 is an EEPROM with 2048 capacity and data is written and read serially. Channel Selector One of 16 channels may be selected using the clip switch named SW401 . SW401encodes the channel number, selected into 4-bit binary code. The binary code plusone equals the channel number. The binary code is decoded by the CPU enabling theappropriate RX or TX frequency and associated data to be selected from theEEPROM. In the binary bit of SW401, the lower 2 bits are connected to Con402. Itcauses the low 4 channels to be selected from the external equipment's.DC to DC Converter The main DC power is injected to the DC to DC converter . The DC to DC converterregulates the various input power supply voltage and outputs a constant voltage of 7.5Volts. It is a source for all of the RF and digital circuits.The DC to DC converter is formed by U801, Q801, Q802, L801 and R804. U801 is aswitch mode DC to DC Converter IC. Input DC various appears as a voltage variousthrough R804. U801 detects the voltage and controls the switching pulse. As theswitching pulses, Q801and Q802 switches the input DC of various supply voltagesand generates the constant DC of supply voltage.
SD 125V3Page -2-August 2002THEORY OF OPERATIONRF CIRCUITSTRANSMITTERThe transmitter is comprised of:1. Buffer2. P.A Module3. Low Pass Filter4. Antenna Switch5. A.P.C CircuitsBuffer VCO output level is -6dBm and amplified to, +6dBm. The buffer consists of Q16 andQ17 for isolation and gain.P. A . M o d u l e The P.A Module contains Q501, Q502, and Q503. Three stage amplifier Q501 ampli-fies the TX signal from +10 dBm to 100 mW. Q502 is amplified to 0.5W. Q503 ampli-fies to 3W and then matched to 50 OHMs using the L.C. network, thereby reducingthe harmonics by -30 dB.Low Pass Filter L7, L8, L11, C72, C73, C74 and C75 are the 7th order Chebyshev low pass filter.Unwanted harmonics are reduced by -70 dBc.Antenna Switch When transmitting, the diodes D5 and D6 are forward biased enabling the RF signalpassage to the antenna. D6 is shorted to ground inhibiting the RF signal to front end.In receive the diodes D5 and D6 are reversed biased passing the signal from theantenna through L13 and C83 to the front end without signal loss.Automatic Current Control (ACC) CircuitsThe ACC circuit consists of R109, variable resistor RV1, IC3(B) and transistors Q21and Q22. The supply current is monitored by the difference voltage on R109 (0.1Ohm). If the current varies by RF power output or other reasons, it produces somebias voltage by IC3A and Q19. The differential signal at the output of IC3 is passed toQ21 and Q22 that produces a constant power output to the antenna. RV1 is used toadjust the RF power level.RF CIRCUITS PLL SYNTHESIZER 12.8 MHz TCXO The TCXO contains the 3-stage thermistor network compensation and crystal oscilla-tor and modulation ports. Compensation is +/-5 PPM or less from -30c to +60c.PLL IC Dual Modules PrescalerInput frequency of 12.8 MHz to IC2 MC14519 pin 20 is divided to 6.25 KHz or 5 KHzby the reference counter, and then supplied to the comparator. RF signal input fromVCO is divided to 1/64 at the prescaler in IC2, divided by A and N counter in IC2 todetermine frequency steps, and then supplied to the comparator. PLL comparisonfrequency is 6.25/5KHz so that minimum programmable frequency step is 5/6.25 KHz.The A and N counter is programmed to obtain the desired frequency by serial data inthe CPU. In the comparator, the phase difference between reference and VCO signalis compared. When the phase of the reference frequency is leading , Fv is the output,but when VCO frequency is leading, Fr is the output. When Fv=Fr, phase detector outis a very small pulse. 64/65 modulus prescaler is comprised in IC2, and has two out-put ports: Port A pin 16: TX enable 2
SD 125V3Page -3-August 2002THEORY OF OPERATION Port B pin 15: prescaler power save control in PLL IC Pin 13 labeled test2 allows thetechnician to see the output of the dual modulus prescaler for trouble shooting pur-poses, no connection should be made to this pin.Level Shifter & Charge PumpThe charge pump is used for changing output signals Fr, Fv at PLL IC from 0-5v to 0-12v necessary for controlling the VCO.Reference Frequency LPFThe Loop Filter contains R12, C21 and C22. LPF settling time is 12mS with 1 KHz fre-quency. This also reduces the residual side-band noise for the best signal-to-noiseratio.DC to DC Converter The DC to DC converter convert the 5v to 14-16v to supply the necessary voltage forwide range frequency in the VCO.VCO The VCO consist of an RX VCO and a TX VCO. It is switched TX/RX by the powersource. It is configured as a colpits oscillator and connected to the buffer as a cascadebias in order to save power. The varicap diode D201/D301 are low-resistance ele-ments and produce a change in frequency with a change in reverse bias voltage (2-11v). L203/L303 are resonant coils, which changes the control voltage by the tuningcore. D202 modulation diode, modulates the audio signal. C204 compensates for thenon-linearity of the VCO due to modulation diode, and maintains a constant modula-tion regardless of frequency .RECEIVERFront End The receive signal is routed backward through the low pass filter, then onward to Pin 1of the Hybrid Receiver Front End Module to a bandpass filter consisting of C622through C608, L607 through L604 is coupled to the base of Q601 which serves as anRF amplifier. Diode D601 serves as protection from static RF overload from nearbytransmitters. The output of Q601 is then coupled to a second bandpass filter consist-ing of C607 through C623 and L604 through L607.The output of Pin 6 is then coupledto the doubly balanced mixer D9. The receiver front end module is factory pre-tunedand requires no adjustment. Repair is effected by replacement of the entire module ofthe proper banded module. The receiver front end module signal pins are as follows:1. RF Input2. Input Ground3. N/A4. Receive +5V5. Ground6. OutputFirst Mixer D9, T2 and T3 are double balanced mixers which provide the 45.1 MHz intermediatefrequency output. The filtered frequency from the front end module is coupled to T2 .The 45.1 MHz IF output is matched to the input of the 2-pole monolithic filter by L14,L31, C69 and C97. The crystal filter provides a bandwidth of +/-7.2 KHz from the oper-ating frequency providing a high degree of spurious and intermodulation protection.Additionally, a 90 MHz trap (XF1) is also placed at the filter output to provide addi-tional attenuation of the second order IMD. The output of the filter is impedancematched by C97 and C69 to the base of the post of filter IF amplifier Q25.Second Oscillator Mixer Limiter And FM DetectorThe output of the post filter amplifier, Q25, is coupled via C98 to the input of IC5 (MC3371). IC5 is a monolithic single conversion FM transceiver, containing a mixer,the second local oscillator, limiter and quadrature detector. Crystal X1 44.645 MHz is
SD 125V3Page -4-August 2002THEORY OF OPERATIONused to provide resultant 455KHz signal from the output of the second mixer. Themixer output is then routed to CF1 ( 455F). These ceramic filters provide the adjacentchannel selectivity of 25 KHz bandwidth .RSSI ( Receiver Sig-nal Strength Indicator )The RSSI signal is output from IC5 on pin 13. As the receiver signals the output, DCvoltage is varied as much as receiver signal strength. Also, the DC signal is tempera-ture compensated with a thermistor (THI ).
SD 125V3Page -5-August 2002WIRING DIAGRAMWIRING DIAGRAMSW401CON1CON4031234117182117182D-SUB 9 CONNECTOR(P/N 950-010-0033)Pin1. ....Audio In (Data RX)Pin2. . . . . Audio Out (Data TX)Pin3.....PTTPin4. . . . . GND (Ground)Pin5. ....B+ (8-18 Volts DC)Pin6. . . . . Carrier Detect (Squelch)Pin7. ....N/C No Connect123456789101112131415617283945115CON401DIGITAL BOARDRF BOARD
Page -6-August 2002BLOCK DIAGRAMBLOCK DIAGRAMANTL.P.FD5ANT SWQ502Q501 Q503P.A. MODULEQ16/Q17TX BUFFERQ202/203TX VCOCONTC21,C22REF L.P.F TX VCO#RLEVEL SHFTERQ6,7,8,11Ref FregIC2PLL CIRCUITPLL ENTCXO1TCXO(12.8MHz)TCXOTCXO MOD+5VL/DQ5RV401BALANCEINVERTER#VDATACPUDC/DC CONVERTERF in16VTX 5VQ12RX BUFEFER L1,L2LOCAL LPFCONT RX VCOQ302/303MODIC3BAUTO POWER CONTROLQ22CONTROLRV1POWER ADJUSTHIFROM CPURV6POWER ADJUSTLOWD6VCCIC3ACURRENT DETECTORCONVERTCURRENT SENSORTX B+FILTERCF12nd IF FILTER25KHzFILTERRX5VFRONT-ENDT2/3/D9MIXERQ601LOW NOISE AMPRX VCOBUFFERU405B2nd LPFU405A2nd LPFRV2MOD LEVELIC405BBUFFERCH SELD/D CONVERTERVin 7.5V-25VVout 7.5VCHANNELL/DIC15V REGULATOR5VVCC 68HC705C8X4013.57TCAPDATA ENU401RX +5V1st IF FILTER45.1MHzQ251st IF AMPXF1MIXERINPUT455KHzT1QUADRATUREX12nd LOCAL44.645MHzCF22nd IF FILTER12.5KHzRSSI OUT DATA OUT3KHz LPFU406B1213U404AU403ALM339U403BLM339RSSI SQUELCH CONTROLPA0U408RESETLK2/LK3LK9/LK10U409COMPARATORIC408EEPROM386 EN123456789DB9DB9 CABLEU405DPREMPHSIS896U404D111012U404BU405C U406C CPU AF MUTER454/C422DEMPHASISRV403AF LEVELU407LM386AUDIO AMP435U404CTX TONE
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