Mitac 8170 Users Manual
8170 to the manual f95a7b09-acb2-4a72-98f2-8a54f26aa8a1
2015-02-09
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SERVICE MANUAL FOR 8170 BY: Jacey Liu TESTING TESTING TECHNOLOGY TECHNOLOGY DEPARTMENT DEPARTMENT // TSSC TSSC Feb . 2002 8170 N/B MAINTENANCE CONTENTS 1. Hardware Engineering Specification-------------------------------------------------------------------------------1.1 1.2 1.3 1.4 1.5 4 Introduction-------------------------------------------------------------------------------------------------------------------------------- 4 System Architecture---------------------------------------------------------------------------------------------------------------------- 5 Electrical Characteristic----------------------------------------------------------------------------------------------------------------- 22 APPENDIX--------------------------------------------------------------------------------------------------------------------------------- 32 BIOS Specification------------------------------------------------------------------------------------------------------------------------ 39 2. System Assembly & Disassembly ------------------------------------------------------------------------------------ 82 2.1 System View-------------------------------------------------------------------------------------------------------------------------------- 82 2.2 System Disassembly---------------------------------------------------------------------------------------------------------------------- 86 3. Definition & Location Connectors / Switches Setting ----------------------------------------------------------- 104 3.1 Main Board--------------------------------------------------------------------------------------------------------------------------------- 104 3.2 D/D Board----------------------------------------------------------------------------------------------------------------------------------- 107 3.3 Touch PAD Board------------------------------------------------------------------------------------------------------------------------- 108 4. Definition & Location Major Components------------------------------------------------------------------------- 109 4.1 Main Board--------------------------------------------------------------------------------------------------------------------------------- 109 4.2 D/D Board---------------------------------------------------------------------------------------------------------------------------------- 111 5. Pin Descriptions of Major Components ---------------------------------------------------------------------------5.1 5.2 5.3 5.4 112 Pentium 4(Willamette/Northwood) Micro-FCPGA 478 pin---------------------------------------------------------------------- 112 Intel 82845(Brookdale Memory Controller HUB)---------------------------------------------------------------------------------- 118 Intel 82801BA(I/O Controller HUB )------------------------------------------------------------------------------------------------- 125 PCI4410(PCMCIA/1394 LINK Controller )---------------------------------------------------------------------------------------- 130 1 8170 N/B MAINTENANCE CONTENTS 6. System Block Diagram ------------------------------------------------------------------------------------------------- 136 7. Maintenance Diagnostic ------------------------------------------------------------------------------------------------ 137 7.1 Introduction-------------------------------------------------------------------------------------------------------------------------------- 137 7.2 Error Codes-------------------------------------------------------------------------------------------------------------------------------- 138 7.3 Debug Card-------------------------------------------------------------------------------------------------------------------------------- 140 8. Trouble Shooting -------------------------------------------------------------------------------------------------------- 142 8.1 No Power------------------------------------------------------------------------------------------------------------------------------------ 143 8.2 Battery Can not Be Charged----------------------------------------------------------------------------------------------------------- 148 8.3 No Display---------------------------------------------------------------------------------------------------------------------------------- 151 8.4 VGA Controller Failure LCD No Display------------------------------------------------------------------------------------------- 153 8.5 VGA Controller Failure External Monitor No Display--------------------------------------------------------------------------- 155 8.6 Memory Test Error----------------------------------------------------------------------------------------------------------------------- 157 8.7 Keyboard(K/B) and Touch Pad(T/B) Test Error----------------------------------------------------------------------------------- 159 8.8 Hard Drive Test Error------------------------------------------------------------------------------------------------------------------- 161 8.9 CD-ROM Drive Test Error------------------------------------------------------------------------------------------------------------- 163 8.10 USB Port Test Error-------------------------------------------------------------------------------------------------------------------- 165 8.11 PIO Port Test Error--------------------------------------------------------------------------------------------------------------------- 167 8.12 PC-Card Failure------------------------------------------------------------------------------------------------------------------------- 169 8.13 IEEE1394 Failure----------------------------------------------------------------------------------------------------------------------- 171 8.14 Audio Failure---------------------------------------------------------------------------------------------------------------------------- 173 8.15 LAN Test Failure------------------------------------------------------------------------------------------------------------------------ 176 9. Spare Parts List ---------------------------------------------------------------------------------------------------------- 178 2 8170 N/B MAINTENANCE CONTENTS 10. System Explode View ------------------------------------------------------------------------------------------------- 189 11. Circuit Diagram -------------------------------------------------------------------------------------------------------- 190 12. Reference ---------------------------------------------------------------------------------------------------------------- 215 3 8170 N/B MAINTENANCE 1.Hardware Engineering Specification 1.1 Introduction 1.1.1 General Description This document describes the system hardware engineering specification for 8170 portable notebook computer system. The 8170 notebook computer is a new mainstream high performance notebook in the MiTAC notebook family. 1.1.2 System Overview CPU Video mPGA 478 -PIN Socket Support Intel Pentium (Willamette)/Northwood in mFC-PGA2 package 1. Dual independent Displays(LCD/CRT, LCD/TV,CRT/TV) 2. Support Motion Compensation and iDCT 3. Support Simultaneous display Momory Two 144Pin SO-DIMM ,withont and on-board Memory PCMCIA 1. Support one slot of TypeII 2. Non Support Zoom video/Audio Function IDE Support 2 IDE channel,Up to Ultra DMA 100 LCD Display Support Dual 85MHz LVDS interface. Support up to QXGA(2048*1536) Resolution Button 5 Easy Start Button(functions defined by user)& 1 Mail Receive Button LAN Support to 10/100 Based T Modem 56Kbps V.90 MDC Modem Pointing Glide PAD with 2 Buttons and 1 scroll button Keyboard Internal Key Matrix Keyboard BIOS 512KB Flash EEPROM (Include System BIOS&VGA BIOS) 4 8170 N/B MAINTENANCE Audio 1. AC'97 Interface Codec. Sound Blaster Pro Compatible. 2. Built-In 21W speaker and 1 Mono-Microphone I/O Port 1. Bi-Direction Parallel Port (EPP/ECP) 2. External VGA Port(D-SUB 15Pins) 3. 2 Standard USB 1.1 Port 4. SPIDF Jack 5. RJ-11 Port for Modem 6. Microphone In Jck 7. RJ-45 Port for LAN 8. VR for Audio Volume Control 9. DC Input Jack 10.Mini IEEE 1394 Port 11. S-Video Output Port(NTSC/PAL) 12. Battery Connector Suspend Mode POS(S1), Suspend to RAM(S3), Suspend to Disk(S4) Indicator HDD,FDD,CD-ROM,Num Lock,Caps Lock, Scroll Lock LEDs 1.2 System Architecture 1.2.1 Block Diagram(without Power System) 5 8170 N/B MAINTENANCE 8170 System Block Diagram 6 8170 N/B MAINTENANCE 1.2.2 Function Description 1.2.2.1 CPU Socket Intel Pentium 4/ Northwood processors with 100MHz FSB.400MHz system bus.Capable of mFC-PGA2 package Available at 1.50, 1.60, 1.70, 1.80, 1.90 and 2 GHz Binary compatible with applications running on previous members of the Intel microprocessor line Intel® NetBurst™ micro-architecture System bus frequency at 400 MHz Rapid Execution Engine: Arithmetic Logic Units (ALUs) run at twice the processor core frequency Hyper Pipelined Technology Advance Dynamic Execution ---Very deep out-of-order execution ---Enhanced branch prediction Level 1 Execution Trace Cache stores 12K micro-ops and removes decoder latency from main execution loops 8 KB Level 1 data cache 256 KB Advanced Transfer Cache (on-die,full speed Level 2 (L2) cache) with 8-way associatively and Error Correcting Code (ECC) 144 new Streaming SIMD Extensions 2 (SSE2) instructions Enhanced floating point and multimedia unit for enhanced video, audio,encryption, and 3D performance Power Management capabilities ---System Management mode ---Multiple low-power states 7 8170 N/B MAINTENANCE Optimized for 32-bit applications running on advanced 32-bit operating systems 8-way cache associatively provides improved cache hit rate on load/store operations. 1.2.2.2 CORE LOGIC Intel Brookdale 82845 Memory Control HUB Intel® Pentium® 4 Processor (478 pin package) Support: ---Enhanced Mode Scaleable Bus Protocol ---2x Address, 4x Data ---System Bus interrupt delivery ---400 MHz system bus ---System Bus Dynamic Bus Inversion (DBI) ---32-bit system bus addressing ---12 deep In-Order Queue ---AGTL+ bus driver technology with integrated AGTL+ termination resistors System Memory Support ---Directly supports one SDR SDRAM channel, 64 bits wide (72 bits with ECC) ---133 MHz SDR SDRAM devices ---64 Mb, 128 Mb, 256 Mb and 512 Mb technologies for x8 and x16 devices ---By using 64 Mb technology, the smallest memory capacity possible is 32 MB ---Configurable optional ECC operation (single bit Error Correction and multiple bit Error Detection) ---Page sizes of 2 KB, 4 KB, 8 KB and 16 KB (individually selected for every row) ---Thermal management ---Maximum of 3 Double-Sided DIMMs (6rows populated) with unbuffered PC133 (with or without ECC) ---3 GB Maximum using 512 Mb technology ---Supports up to 24 simultaneous open pages ---Maximum memory bandwidth of 1.067 GB/s with PC133 8 8170 N/B MAINTENANCE Hub Interface to Intel® 82801BA ICH2 ---266 MB/s point-to-point hub interface to ICH2 ---66 MHz base clock ---MSI interrupt messages, power management state change, SMI, SCI and SERR error indication Accelerated Graphics Port (AGP) Interface --- Supports a single AGP device (either a connector or on the motherboard) ---Supports AGP 2.0 including 1x, 2x, and 4x AGP data transfers and 2x/4x Fast Write protocol ---Supports only 1.5 V AGP electrical characteristics ---32 deep AGP request queue ---Delayed transaction support for AGP-to-System Memory FRAME# semantic reads System Interrupt Support ---System bus interrupt delivery mechanism ---Interrupts signaled as upstream memory writes from AGP/PCI ---Supports peer MSI between hub interface and AGP ---Provides redirection for IPI and upstream interrupts to the system bus Power Management ---SMRAM space remapping to A0000h ---Supports extended SMRAM space above 256 MB, additional TSEG from Top of Memory interface are not supported ---PC ’99 suspend to DRAM support ---ACPI, Revision 1.0b compliant power management ---APM, Revision 1.2 compliant power management ---NT Hardware Design Guide, Version 1.0 compliant Package ---MCH: 593 pin FC-BGA (37.5 x 37.5 mm) 9 8170 N/B MAINTENANCE Intel 82801BA Internal Connect HUB PCI Bus I/F ---Supports PCI at 33 MHz ---Supports PCI Rev 2.2 Specification ---133 MByte/sec maximum throughput ---Supports up to 6 master devices on PCI ---One PCI REQ/GNT pair can be given higher arbitration priority (intended for external 1394 host controller) Integrated LAN Controller ---WfM 2.0 Compliant ---Interface to discrete LAN Connect component ---10/100 Mbit/sec Ethernet support ---1 Mbit/sec HomePNA* support Integrated IDE Controller ---Independent timing of up to 4 drives ---Ultra ATA/100/66/33, BMIDE and PIO modes Read transfers up to 100MB/s, Writes to 89 MB/s ---Separate IDE connections for Primary and Secondary cables ---Implements Write Ping-Pong Buffer for faster write performance USB ---2 UHCI Host Controllers with a total of 4 ports ---USB 1.1 compliant ---Supports wake-up from sleeping states S1–S4 ---Supports legacy Keyboard/Mouse software AC'97 Link for Audio and Telephony CODECs ---AC’97 2.1 compliant 10 8170 N/B MAINTENANCE ---Independent bus master logic for 5 channels (PCM In/Out, Mic Input, Modem In/Out) ---Separate independent PCI functions for Audio and Modem ---Support for up to six channels of PCM audio output (full AC3 decode) ---Supports wake-up events Interrupt Controller ---Support up to 8 PCI interrupt pins ---Supports PCI 2.2 Message-Based Interrupts ---Two cascaded 82C59 ---Integrated I/O APIC capability ---15 interrupts supported in 8259 mode, 24 supported in I/O APIC mode ---Supports Serial Interrupt Protocol ---Supports Front-Side Bus interrupt delivery 1.8 V operation with 3.3 V I/O ---5V tolerant buffers on IDE, PCI, USB Over current and Legacy signals GPIO ---TTL, Open-Drain, Inversion Timers Based on 82C54 ---System timer, Refresh request, Speaker tone output Power Management Logic ---ACPI 1.0 compliant ---ACPI Power Management Timer ---PCI PME# support ---SMI# generation ---All registers readable/restorable for proper resume from 0V suspend states ---Support for APM-based legacy power management for non-ACPI implementations 11 8170 N/B MAINTENANCE External Glue Integration ---Integrated Pull-up, Pull-down and Series Termination resistors on IDE and processor interface Enhanced Hub I/F buffers improve routing flexibility (Not available with all Memory Controller Hubs) Firmware Hub (FWH) I/F supports BIOS memory size up to 8 MBs Low Pin count (LPC) I/F ---Allows connection of legacy ISA and X-Bus devices such as Super I/O ---Supports two Master/DMA devices. Enhanced DMA Controller ---Two cascaded 8237 DMA controllers ---PCI DMA: Supports PC/PCI — Includes two PC/PCI REQ#/GNT# pairs ---Supports LPC DMA ---Supports DMA Collection Buffer to provide Type-F DMA performance for all DMA channels Real-Time Clock ---256-byte battery-backed CMOS RAM ---Hardware implementation to indicate century rollover System TCO Reduction Circuits ---Timers to generate SMI# and Reset upon detection of system hang ---Timers to detect improper processor reset ---Integrated processor frequency strap logic SM Bus ---Host interface allows processor to communicate via SM Bus ---Slave interface allows an external Micro controller to access system resources ---Compatible with most 2-Wire components that are also I2C compatible 12 8170 N/B MAINTENANCE Supports ISA bus via external PCI-ISA Bridge 360-pin EBGA package 1.2.2.3 Memory 64MB PC133 SDRAM SO-DIMM Expandable to 1024MB(2 SODIMM slots). Support 3.3V PC133 SDR SDRAM only. Table 1.1 MEMORY EXPANSION CAPACITY Slot2 0 32MB 64MB 128MB 256MB 512MB 128MB 256MB 512MB 256MB 512MB 512MB Total 64MB 96MB 128MB 192MB 320MB 576MB 256MB 384MB 640MB 512MB 768MB 1024MB 67.6mm ( 2.66”) 54 pin or 50 pin TSOP 54 pin or 50 pin TSOP SPD Slot1 64MB 64MB 64MB 64MB 64MB 64MB 128MB 128MB 128MB 256MB 256MB 512MB 54 pin or 50 pin TSOP 54 pin or 50 pin TSOP 31.75mm (1.25”) 143 1 59 61 Figure 1.1 SO-DIMM MODULE 13 8170 N/B MAINTENANCE 1.2.2.4 I/O Ports • CRT Port @ Standard VGA compatible port @ DDC1 and DDC2B compliant Table 1.2 CRT CONNECTOR PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SIGNAL RED GREEN BLUE Monitor Sense GND GND GND GND VCC GND Monitor Sense CRT DATA HSYNC VSYNC CRT CLK DESCRIPTION Red analog video output Green analog video output Blue analog video output Monitor Sense Ground Ground Ground Ground +5VDC Ground Monitor Sense Data from DDC monitor Horizontal Sync Control Vertical Sync control Clock to DDC monitor 5 4 3 2 1 10 6 15 14 13 12 11 Figure 1.2 CRT CONNECTOR 14 8170 N/B MAINTENANCE • Standard 4 Pins S-VIDEO Port for TV-Out @ Support 1024*768 resolution @ Support 848*480 resolution in 16:9 mode @ Support PAL and NTSC system Table 1.3 S-VIDEO CONNECTOR PIN 1 2 3 4 SIGNAL DESCRIPTION GND GND LUMA O CRMA O Pin 1 Figure1.3 S-VIDEO Port • IEEE1394 Port Table 1.4 IEEE1394 CONNECTOR PIN 1 2 3 4 SIGNAL DESCRIPTION TPBI/O TPB+ I/O TPAI/O TPA+ I/O Figure1.4 IEEE1394 Port • AUDIO Ports @ Built in 1 mono microphone 15 8170 N/B MAINTENANCE @ SPDIF @ Microphone In • RJ11 @ Connection to Modem Daughter Board connector Table 1.5 MODEM CONNECTOR PIN 1 2 3 4 SIGNAL NAME NC LINE+ LINENC DIRECTION I/O I/O - DESCRIPTION No Connect Phone Line Positive Phone Line Negative No Connect Figure 1.5 MODEM Port • RJ45 @ Connection to on-board NIC controller Table 1.6 LAN CONNECTOR PIN 1 2 3 4 5 6 7 8 SIGNAL NAME TX+ TXRX+ TERM 1 TEMR 2 RX TERM 3 TERM 4 DIRECTION Out Out IN IN - DESCRIPTION Transmit Data Ring Transmit Data Tip Receive Data Ring Internal termination resistor Internal termination resistor Receive Data Tip Internal termination resistor Internal termination resistor Figure 1.6 LAN CONNECTOR 16 8170 N/B MAINTENANCE • USB Port @ Two industry standard USB 1.1 ports Table 1.7 USB Port2 PIN 1 2 3 4 SIGNAL NAME VCC DATADATA+ GND DIRECTION I/O I/O - DESCRIPTION USB Device Power (+5VDC) Balanced Data Negaitve Balanced Data Posiitve Ground Figure 1.7 USB Port • Parallel Port @ Configurable as logical ports LPT1,LPT2 or LPT3 @ EPP rev 1.7 & 1.9 compatible @ ECP(IEEE 1284) compatible @ Industry standard 25 Pins connector Figure 1.8 PARALLEL PORT CONNECTOR 17 8170 N/B MAINTENANCE Table 1.8 PARALLEL Port PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Case SIGNAL NAME DIRECTION DESCRIPTION STROBE# O Data Strobe PD0 I/O PP Data bit 0 PD1 I/O PP Data bit 1 PD2 I/O PP Data bit 2 PD3 I/O PP Data bit 3 PD4 I/O PP Data bit 4 PD5 I/O PP Data bit 5 PD6 I/O PP Data bit 6 PD7 I/O PP Data bit 7 -ACK I Printer Acknowledge BUSY I Printer Busy PE I Paper Out SLCT I Print Select Acknowledge -AUTOFDXT O Auto Line Feed -ERROR I Printer Error -INIT O Reset Printer SLCTIN# I Select In GND Ground GND Ground GND Ground GND Ground GND Ground GND Ground GND Ground GND Ground GND Ground 18 8170 N/B MAINTENANCE 1.2.2.5 PC CARD SLOT One Type II/I slot supporting the 1997 PC Card standard, and including full R2(16-bit) and 32-bit Card bus Data transfer TI PCI4410(PCMXCIA Controller)& TI TPS2211(Power Switch) 1.2.2.6 GRAPHICAL SUBBSYSTEM ATI Mobility M6 graphical controller embedded 8M DDR SDRAM 1.2.2.7 DISPLAY Internal LCD Display is 14.1” TFT ISP XGA color External Video refresh rate of up to 100HZ support ---Vertical refresh frequencies to meet VESA requirements ---Simultaneous video in specified video modes-switchable with hot key 1.2.2.8 READ ONLY MEMORY(BIOS FLASH) Fully compatible with industry standard software including windows 2000 & Windows XP Fully support APM V1.2 and latest ACPI specification 4Mb Flash BIOS Inside BIOS core 1.2.2.9 POWER MANAGEMENT FEATURES Local standby mode(individual device such as HDD, graphics controller,LCD etc..) 19 8170 N/B MAINTENANCE CPU Idle mode(including ACPI modes C1 and C2) Suspend mode(including S1 and S3 ACPI modes) Fully APM V1.2 compliant Fully ACPI V1.1 compliant Hibernate for Windows 2000 and windows XP Thermal management Fully US EPA Energy start compliant 1.2.2.10 KEYBOARD CONTROLLER Hitachi H8-3437S 1.2.2.11 SUPER I/O Ns PC87393F LPC interface Ultra I/O 1.2.2.12 LEDS INDICATOR CDROM & HDD & NUM & CAP & SCROLL & EMIAL 1.2.2.13 BUTTONS EMAIL BIN & FIVE PIECE EASY START RTN 20 8170 N/B MAINTENANCE 1.2.2.14 MODEM Table 1.9 MODEM DAUGHTER BOARD CONNECTOR PIN SIGNAL NAME PIN SIGNAL NAME 1 MONO_OUT 2 NC 3 GND 4 MODEM_SPK 5 NC 6 NC 7 NC 8 GND 9 NC 10 +5V 11 NC 12 NC 13 NC 14 NC 15 GND 16 Pull Up to +3V 17 +3V 18 +5V 19 GND 20 GND 21 +3V 22 ACSYNC 23 ACSDOUT 24 MSDIN 25 -ACRST 26 MSDIN 27 GND 28 GND 29 GND 30 ACBITCLK 21 8170 N/B MAINTENANCE 1.3 Electrical Characteristic 1.3.1 Power On Sequence Figure 1.9 Power on Sequence 22 8170 N/B MAINTENANCE 1.3.2 Power On Suspend Sequence Figure 1.10 Power on Suspend Sequence 1.3.3 Resume from Power Suspend Sequence Figure 1.11 Resume from Power Suspend Sequence 23 8170 N/B MAINTENANCE 1.3.4 Suspend to RAM Sequence Figure 1.12 Suspend to RAM sequence 24 8170 N/B MAINTENANCE 1.3.5 Resume from Suspend to RAM Sequence Figure 1.13 Resume from Suspend to RAM Sequence 25 8170 N/B MAINTENANCE 1.3.6 Suspend to Disk Sequence Figure 1.14 Suspend to Disk Sequence 26 8170 N/B MAINTENANCE 1.3.7 Resume from Suspend to Disk Sequence Figure 1.15 Resume from Suspend to Disk Sequence 27 8170 N/B MAINTENANCE 1.3.8 ICH2 GPI/O Pin Define Pin Name Signal Name GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO6 GPIO7 GPIO8 GPIO11 GPIO12 GPIO13 GPIO16 GPIO17 GPIO18 GPIO19 GPIO20 GPIO21 GPIO22 GPIO23 GPIO24 GPIO25 GPIO27 GPIO28 PULL-UP PULL-UP PULL-UP PULL-UP PULL-UP PULL-UP PULL-UP -SCI PULL-UP -EXTSMI PULL-UP TP PULL-UP PULL-UP -ENABKL_MASK -CDROM_PWRON -HDD_PWRON DRAMENA PULL-UP -1394WR -PCIRST_MSK -GATE1394 SPK_OFF Power Type +3.3VS +3.3VS +3.3VS +3.3VS +3.3VS +3.3VS +3.3VS +3.3VA +3.3VA +3.3VA +3.3VA +3.3VS +3.3VS +3.3VS +3.3VS +3.3VS +3.3VS +3.3VS +3.3VS +3.3VA +3.3VA +3.3VA +3.3VA I I X I I I I I I I I O O O O O O O OD O O O O During Immediately After PCIRST# PCIRST# PC/PCI DEVICE PC/PCI DEVICE X X HIGH-Z HIGH-Z HIGH-Z HIGH-Z MAIN I/O S1 S3 S4/S5 Description DRIVEN DRIVEN X HIGH-Z HIGH-Z X X X ACPIMODE-SCI HIGH-Z HIGH-Z DEFINED DEFINED DEFINED DOS MODE -SMI HIGH-Z HIGH-Z HI HI HI HI HIGH-Z LOW HIGH-Z HIGH-Z HIGH-Z HIGH-Z HI HI HI HI HI HIGH-Z LOW HI HI HI HI HI HI DEFINED DEFINED DEFINED DEFINED DEFINED DEFINED DEFINED DEFINED DEFINED DEFINED OFF OFF OFF OFF OFF OFF OFF OFF DEFINED DEFINED DEFINED DEFINED OFF OFF OFF OFF MASK ENABLE OFF Control CDROM Power on OFF Control HDD Power on OFF DRAM Data select OFF DEFINED 1394EEPROM R/W DEFINED MASK PCIRST DEFINED RST CARD BOARD DEFINED OFF SPEAKER 28 8170 N/B MAINTENANCE 1.3.9 Power Consumption Of Suspend Mode Suspend To RAM=0.7Vrms(3.3V audio) <=0.1 20Hz~15Hz 20Hz~15Hz >=70dBFSA <=-55dBFS >=50dB 30 8170 N/B MAINTENANCE Table 1.11 Analog Pass-Through(A-A) for line input to line Output Test Items Frequency Response Dynamic Range(SNR) THD+N Cross-talk Mobile System 20Hz~15kHz >=70dBFSA <=-55dBFS >=50dB Table 1.12 Analog Pass-Through(A-A) for Microphone input to line Output Test Items Frequency Response Dynamic Range(SNR) THD+N Mobile System 100Hz~12kHz >=60dBFSA <=-50dBFS Table 1.13 Digital Recording(A-D-PC) for Microphone input Test Items Full Scale Input Voltage Sample Frequency Accuracy Frequency Response(22.05ks/sec) Dynamic Range(SNR) THD+N Mobile System >=100mVrms <=0.1% 100Hz~8.8kHz >=60dBFSA <=-50dBFS 31 8170 N/B MAINTENANCE 1.4 APPENDIX APPENDIX A WILLAMETTE CPU CORE FEQUENCY SELECTION Bus Ratio 1/8 1/10 1/11 1/12 1/13 1/14 1/15 1/16 1/17 1/18 1/19 1/20 1/21 1/22 1/23 1/24 Core Freq LINT[1]#NMI A20M# 800MHz H H 1.00GHz H H 1.10GHz H H 1.2GHz H L 1.3GHz H L 1.4GHz H L 1.5GHz H L 1.6GHz L H 1.7GHz L H 1.8GHz L H 1.9GHz L H 2.0GHz L L 2.1GHz L L 2.2GHz L L 2.3GHz H H 2.4GHz L L IGNNE# LINT[0]#/INTR H H L H L L H H H L L H L L H H H L L H L L H H H L L H H L L L 32 8170 N/B MAINTENANCE APPENDIX B VOLTAGE INDENTIFICATION DEFFINITION VID4 VID3 VID2 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 0 1 1 0 1 1 0 1 0 1 1 0 1 1 0 1 1 0 1 1 0 0 1 0 0 1 0 0 1 0 0 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 0 0 1 0 0 1 0 0 1 0 0 0 1 0 0 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 VID1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 VID0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Vcc_max VRM output off 1.100 1.125 1.150 1.175 1.200 1.225 1.250 1.275 1.300 1.325 1.350 1.375 1.400 1.425 1.450 1.475 1.500 1.525 1.550 1.575 1.600 1.625 1.650 1.675 1.700 1.725 1.750 1.775 1.800 1.825 1.850 33 8170 N/B MAINTENANCE APPENDIX C FREQUENCY TABLE FOR BCLK[1:0] BSEL1 L L H H BSEL0 L H L H Function 100MHZ RSV RSV RSV LCD CABLE REQUIREMENT Each differential pair need meet maximum in impedance 100Ω DC impedance have to meet maximum impedance 5m Ω in each line Unipac UB 141X01/Hyundai HT14X13/HannStar HSD141PX11 LCD Cable Pin Define Signal name M/B Pin Number LCD module pin number LCDVCC 1 1 LCDVCC 2 2 GND 3 3 GND 4 4 GND 5 7 GND 6 10 TX2CLK+ NC 7 TXCLK+ 8 15 TX2CLKNC 9 TRCLK10 14 GND 11 13 GND 12 16 34 8170 N/B MAINTENANCE TX2OUT0+ TX2OUT1+ TX2OUT0TX2OUT1GND GND TX2OUT2+ TXOUT0+ TX2OUT2TXOUT0GND GND TXOUT2+ TXOUT1+ TXOUT2TXOUT1GND GND LCD_ID0 +3VS LCD_ID1 +3VS LCD_ID2 +3VS NC NC NC NC 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 NC NC NC NC NC NC NC 6 NC 5 19 20 12 9 11 8 NC NC NC NC NC NC NC NC NC NC NC NC 35 8170 N/B MAINTENANCE LCD Panel Type Link Pin Unipac 14.1" TFT:UB 141X01 31&32 tied together Hyundai 14.1" TFT: HT14X13 33&34 tied together HannStar 14.1" TFT: HSD141PX11 31&32,33&34 tied together COM N141P1 LCD Cable Pin Define Signal name M/B pin Number LCDVCC 1 LCDVCC 2 GND 3 GND 4 GND 5 GND 6 TX2CLK+ 7 TXCLK+ 8 TX2CLK9 TXCLK10 GND 11 GND 12 TX2OUT0+ 13 TX2OUT1+ 14 TX2OUT015 TX2OUT116 GND 17 GND 18 TX2OUT2+ 19 LCD module pin number 1 2 3 4 NC NC 20 12 19 11 NC NC 14 16 13 15 NC NC 18 36 8170 N/B MAINTENANCE TXOUT+ TX2OUT2TXOUT0GND GND TXOUT2+ TXOUT1+ TXOUT2TXOUT1GND GND LCD_ID0 +3VS LCD_ID1 +3VS LCD_ID2 +3VS NC NC NC NC 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 6 17 5 NC NC 10 8 9 7 NC NC NC NC NC NC NC NC NC NC NC NC 37 8170 N/B MAINTENANCE DISPLAY Link Pin COM 14.1" SXGA+N141P1 35&36 tied together LCD Panel ID Define Table LCD Panel LCD_ID2 LCD_ID1 LCD_ID0 0 0 1 Uniqac 0 1 0 Hyundai 0 1 1 HannStar 1 0 0 CMO 38 8170 N/B MAINTENANCE 1.5 BIOS Specification 1.5.1 BIOS Feature @ Inside BIOS for Intel 845 + ICH2 chipset @ 256KB flash ROM @ ACPI 1.0b Compliant (S1, S3, S4, S4BIOS) @ Support APM 1.2 (POS, STR, STD) @ SMBIOS 2.3.1 @ Support external 1.44MB USB Floppy @ Support DVD-ROM and CD-ROM @ Support Multi-boot function @ Plug & Play for Devices @ Support FIR @ Silence Boot with Logo customized @ Wake-up from USB @ Fast boot bypass RAM/Floppy/CDROM testing @ BIOS Lock function Add the BIOS lock string at shadow memory address F000:E0C2 39 8170 N/B MAINTENANCE 1.5.2 Component&Drives Please refer to the chapter of Power Management for state definitions. For PCI and PnP terms, please refer to respective specifications 1.5.2.1 CPU @ Intel Pentium 4 Processors Willamette//Northwood, Support upto 1.7GHz, 400 Mhz FSB @ Pentium 4 with 256K L2 Cache @ 64Kbyte on-chip L1 Cache @ CPU’s Power transition (Please refer to the chapter of Power Management for state definitions) When in G0/Full-On, CPU can be in C0/C1/C2. When in G1(STR)/G2(STD)/G3(Mechanical Off) State, CPU power is removed. 1.5.2.2 Memory System @ Two SODIMM for SDRAM extension from 64MB to 512MB Pentium 4 with 256K L2 Cache @ 400MHz Host Bus, 33MHz PCI Bus, 133MHz Memory Clock @ Dynamically row power-down @ Support Auto-refresh and Self-refresh command @ Auto-detect CAS latency Programming @ Memory Auto-sizing @ 1/2/4 Bank SDRAM support, up to 4 page could open at any time 40 8170 N/B MAINTENANCE 1.5.2.3 PCI Devices @ USB ---4 USB port are built in SB chipset (only 2 are supported in this model) ---Wake up from USB device is supported on POS/STR @ VGA ---LCD panel could be turn on/off via function hotkey, or Lid switch if users define “Blank LCD” on cover closed in SCU. ---When in G0/Full-On/Idle, VGA stays in D0 state, Panel stays on. However, if no VGA activities detected for a specific period defined in SCU, VGA will go to D1 state, and Panel will be turned off. ---When in G2/G3/STD/Soft-Off/Mechanical Off State, VGA and Panel are power off. ---When in G1/Standby, VGA stays in D2 state, Panel stays off, Hsync/Vsync is cut. ---When in G1/STR, VGA stays in D3 state, Panel stays off, Hsync/Vsync is cut, especially, Note: VRAM is shared on system DRAM, so no special circuit is provided for VRAM refresh when G1/STR. @ AUDIO ---When in G0/Full-On/Idle, Audio stays in D0 state ---When in G2/G3/STD/Soft-Off/Mechanical Off State, Audio is power off. @ MODEM ---Ring wake-up supported in G1/Standby/Suspend states. ---When in G0/Full-On/Idle, Modem stays in D0 state ---When in G2/G3/STD/Soft-Off/Mechanical Off State, Modem is power off. @ PMCIA(TI4410) ---PME# supported 41 8170 N/B MAINTENANCE ---Ring wake-up supported in G1/Standby/Suspend states. ---When in G0/Full-On/Idle, PCMCIA stays in D0 state if PC card is inserted, and stays in D2 state once PC card is removed. ---When in G2/G3/STD/Soft-Off/Mechanical Off State, PCMCIA is power off. ---When in G1/Standby, PCMCIA stays in D1 state. ---When in G1/Suspend, PCMCIA stays in D3 state. @ IEE1394(TI4410) --- PME# supported @ LAN(RTL8139CL) ---PME# supported ---Ring wake-up supported in G1/Standby/Suspend states. PCI Devices IDSEL PCI Device Intel 845 P2P (NB) P2P (SB) LPC Bridge IDE USB #1 SMB USB #2 AC’97 MC’97 VGA LAN PCMCIA IEEE 1394 IDESL AD14 AD15 AD15 AD15 AD15 AD15 AD15 AD15 AD18 AD19 AD19 Register Setting Bus/ Device/ Function 00 / 00 / 00 00 / 01 / 00 00 / 30 / 00 00 / 31 / 00 00 / 31 / 01 00 / 31 / 02 00 / 31 / 03 00 / 31 / 04 00 / 31 / 05 00 / 31 / 06 01 / 00 / 00 02 / 02 / 00 02/ 03 / 00 02/ 03 / 01 42 8170 N/B MAINTENANCE PCI IRQ Routing CI Device Intel 845 P2P (NB) P2P (SB) LPC Bridge IDE USB #1 SMB USB #2 AC’97 MC’97 VGA LAN PCMCIA IEEE 1394 PIRQ A PIRQ B PIRQ C PIRQ D PIRQ H INT D# INT C# INT B# INT B# INT A# INT A# INT A# INT B# PFA 0x0000 0x0008 0x00F0 0x00F8 0x00F9 0x00FA 0x00FB 0x00FC 0x00FD 0x00FE 0x0100 0x0210 0x0218 0x0219 Bus/ Device/ Function 00 / 00 / 00 00 / 01 / 00 00 / 30 / 00 00 / 31 / 00 00 / 31 / 01 00 / 31 / 02 00 / 31 / 03 00 / 31 / 04 00 / 31 / 05 00 / 31 / 06 01 / 00 / 00 02 / 02 / 00 02/ 03 / 00 02/ 03 / 01 1.5.2.4 PCI Device @ Plug & Play Interface ---Plug and Play BIOS Spec. Rev. 1.0A Compliant ---No ESCD supported @ RTC ---User could setup current date and time in SCU. RTC must be Y2K compliant ---User could also setup a RTC wake-up event at any time of a month. 43 8170 N/B MAINTENANCE @ DMA ---ECP/FIR also use DMA but they are programmable @ PIC ---IRQ0 is used by the system timer ---IRQ1 is used by KBC (Key Board Controller) ---IRQ2 is used by slave PIC ---IRQ3 is used by IR ---IRQ5 is used by Audio ---IRQ7 is used by LPT port ---IRQ8 is used by RTC (Real Time Clock) ---IRQ9 is shared by SCI ---IRQ10 is used by LAN ---IRQ10 is used by PCMCIA ---IRQ10 is used by IEEE 1394 ---IRQ10 is also shared by VGA ---IRQ12 is used by mouse ---IRQ13 is used internally by CPU to recognize FPU interrupts ---IRQ14 is used by IDE channel 1 ---IRQ15 is used by IDE channel 2 ---Preserve two IRQs (4, 6, 11) for other devices to use. 44 8170 N/B MAINTENANCE @ Super I/O ---SIO chip could enter a full power down mode once system enter Suspend states ---Printer Port Print port will enter power down mode when G1/G2/G3/STD/Suspend/Standby state. ---IR Port IR port will enter power down mode and IR module’s power will be cut off when G1/G2/G3/STD/ Suspend/Standby state. @ KBC ---H8 will automatically control its power state. Please refer to KBC’s specification 1.5.2.5 IDE Devices @ Hard Disk ---HD will enter standby mode whenever no access request is made. ---HD will enter standby mode when the system entering Standby state. ---HD will enter sleep mode when the system entering Suspend state. @ CDROM ---CD drive will enter standby mode whenever no access request is made. ---CD drive enter standby mode when the system entering Standby state. ---CD drive enter sleep mode when the system entering Suspend state 45 8170 N/B MAINTENANCE 1.5.2.6 AC’97 Device @ AC’97 Interface @ Audio Codec ---Enter the most power saving state during Suspend. @ Modem Codec ---Enter the most power saving state during Suspend 1.5.2.7 SMB (1) South Bridge SMB BUS @ SMBUS Device SMB Device SDRAM 0 SDRAM 1 CLK_GEN Read Addr 0xA1 0xA1 0xD3 Write Addr 0xA0 0xA0 0xD2 @ SDRAM ---Use SMB link to read configuration data from SDRAM ---Turn off clock if no SO-DIMM insert automatically when POST @ Clock Generator ---Spread spectrum is enabled during POST 46 8170 N/B MAINTENANCE (2) H8 SMB BUS @ Battery Pack ---This is polling by KBC (H8) @ Thermal Sensor ---Sensed by H8 @ Charger ---Directly controlled by H8, please refer to KBC specification 1.5.2.8 Mechanics @ Button ---1 Power Button, 5 Easy Start Buttons, 1 E-Mail Received Button. @ LID Switch ---See 1.6.7 @ LEDs ---All LEDs are controller via H8, Please refer to H8 Specification @ FAN ---Controlled by H8 47 8170 N/B MAINTENANCE 1.5.3 BIOS Setup 1.5.3.1 Introduction SCU allows you to configure the BIOS settings. Those settings are vital for your notebook to identify the types of installed devices as well as to utilize special features. Typical menu items include Date and Time, the types of disk drives, and IDE settings. Special features include Power Saving and Password settings The settings information is stored in the CMOS (Complementary Metal Oxide Semiconductor) RAM, which is powered by a RTC backup battery. You may need to run SCU when * You see an error message on the screen requesting you to run SCU * You want to restore the factory default settings * You want to modify some specific settings 1.5.3.2 Starting SCU SCU is built into the system board. To run SCU, press [F2] during system startup. The main SCU screen appears as shown in Figure 1.15. 48 8170 N/B MAINTENANCE Insyde Software SCU Startup Memory Aug 23, 2001 Disks Components Power pm Exit Devices Primary Master = Primary Slave = Secondary Master= Secondary Slave = Serial Port 2 = Parallel Port = 2:34:12 System 0 MB 0 MB 0 MB 0 MB COM2, 2F8, IRQ3 LPT1, 378, IRQ 7 CPU = Pentium 4 CPU Speed = 0 MHz Memory Base Extended Shadow Reserved Total RAM Cache (Ext) = 640 KB = 64512 KB = 176 KB = 208 KB = 65536 KB = 256 KB Press Key to activate menus, and cursor keys to navigate. Mouse left button, spacebar, and keys accept menu item. Mouse right button and key cancel current action. Figure 1.16 Main SCU Screen The SCU screen can be divided into three areas: @ On the top line of the screen is the menu bar, which lists the titles of the available menus Each menu title contains a pull-down menu, which displays items for settings @ The middle section of the screen displays current settings of the system. If you open a pull-down menu and select an item that provides multiple options, a submenu will pop up and let you make further selections. 49 8170 N/B MAINTENANCE @ The bottom window provides alternative information. Normally it gives the keyboard/mouse instructions for moving around and making selections. When a menu item is highlighted, the window will provide more detailed description of the item. 1.5.3.3 Moving Around and Making Selections You must go through two or three levels to complete the setting for an item. In most cases, there are three levels: menu title, pull-down menu, and submenu. To move around and make selections, you can use both the touch pad/mouse and keyboard @ Using the Touch pad/Mouse You are advised to use the touch pad or mouse. It is more straightforward than using the keyboard. For most items, simply move the pointer with the touch pad/mouse and left-click on the intended item. To cancel your selection, click the right button. For some items, you will need to select with the arrow keys. @ Using the keyboard Keyboard information can be found at the bottom of the screen. You can also use the shortcut key, which is highlighted in a different color on the screen. Described below is the general procedure to complete a setting by use of the keyboard: ® Select a menu title with the left/right arrow key and press [Enter] to pull down the menu. You can directly pull down a menu You can directly pull down a menu by pressing [Alt] and the shortcut key. ® From the pull-down menu, select an item with the up/down arrow key and press [Enter] to access the submenu or change the setting, The submenu displays further options that you can select. 50 8170 N/B MAINTENANCE ® For most menu items, pressing the [Tab] key will jump from one item to another, thus allowing you to go through the items quickly. To confirm the changes you make, press [Enter] or select the OK button. To cancel the changes, press [Esc] or select the Cancel button. 1.5.3.4 Startup Menu The Startup pull-down menu, as shown below, contains some basic configuration and password settings of the system Startup Date and Time Splash Boot Logo √ Fast Boot Boot Device Set Admin password Set User password SCU Color Scheme > > > > > @ Data and time The “Date and Time” item sets the system date and time. When this item is selected, the submenu will display as shown below: Date and Time Day Month Year 23 8 2001 OK OK Hour Minute Second 16 56 53 Cancel Cancel 51 8170 N/B MAINTENANCE @ Splash Boot Logo The “Splach boot Logo” item to enable or disable the big boot logo on screen when system is booting. When this item is selected, no submenu will display. A check mark (√) indicates Enabled; an underline (_) indicates Disabled. The default setting is Disabled @ Fast Boot The “Fast Boot” item, when enabled, speeds up the booting procedure by bypassing the memory test. When this item is selected, no submenu will display. A check mark (√) indicates Enabled; an underline (_) indicates Disabled. The default setting is Enabled. @ Boot Device The “Boot Device” item sets the sequence of booting device. When this item is selected, the submenu will display as shown below. Boot Device 1st Boot Device 2nd Boot Device 3rd Boot Device ( ) Hard Disk C ( ) CD-ROM Drive (.) Diskette A (.) Hard Disk C ( ) CD-ROM Drive ( ) Diskette A ( ) Hard Disk C (.) CD-ROM Drive ( ) Diskette A OK OK Cancel Cancel The default setting is Diskette A, Hard Disk C, then CD-ROM Drive NOTE: If you set all booting options to the same device (say, Hard Disk C),. then the notebook will try to boot from that device only 52 8170 N/B MAINTENANCE @ Set Admin Password This item lets you set up administrator-level password. When this item is selected, the submenu will display as shown below: Set Admin password Enter old ADMIN Password: .......... Enter new ADMIN Password: .......... Verify new ADMIN Password: .......... Verify password when... [X] Boot System [ ] Enter SCU OK OK Cancel Cancel You can directly enter the new password if no password has previously existed. If a password has been previously set up, you have to enter the correct old password before setting up a new one. In either case, you have to enter the new password twice to complete the setting. NOTE: 1. If you want to clear a previous password, you can enter the old password and leave the following fields blank 2. The administrator password is required for booting and entering SCU, so the “Verify password when …” setting can not be changed 53 8170 N/B MAINTENANCE @ Set User Password This item lets you set up user-level password. When this item is selected, the submenu will display as shown below: Set User password Enter old User Password: .......... Enter new User Password: .......... Verify new User Password: .......... Verify password when... [X] Boot System [ ] Enter SCU OK OK Cancel Cancel The procedure to set up the user password is the same as “Set Admin Password”. NOTE: 1. You can not set up the user password unless the administrator password has been set up. 2. If both the administrator and user passwords are set up, only one password is required to boot the system 3. To modify the SCU settings, you have to enter the administrator password. The user password only allows you to browse the settings. 4. If the “Resume System” item is checked, the password is required only when the system is restored from “Suspend-to-disk” status. 54 8170 N/B MAINTENANCE @ SCU Color Scheme The “Splach boot Logo” item select color set for your viewing. When this item is selected, the submenu will display as shown below: SCU Color Scheme Select Color: (.) Color ( ) Alternate Color ( ) Black and White ( ) Reverse Black and OK OK Cancel Cancel The default setting is “Color”. 1.5.3.5 Memory Menu Memory Cache Systems > @ Cache System Cache Systems L1 Cache L2 Cache ( ) Disabled (.) Write Back OK OK ( ) Disabled (.) Write Back Cancel Cancel The default settings of the “L1 Cache” and “L2 Cache” are “Write Back”. 55 8170 N/B MAINTENANCE 1.5.3.6 Disk Menu Disks √ Internal HDC √ IDE Setting Virus Alert > > @ Internal HDC The “Internal HDC” item sets if an internal hard drive is present. When this item is selected, no submenu will display. A check mark (√) indicates Enabled; an underline (_) indicates Disabled The default setting is Enabled @ IDE Setting The “IDE Settings” item sets the type of the hard disk drive in your system. When this item is selected, the submenu will display as show below: IDE Settings HDD Timing ( ) ( ) ( ) ( ) (.) I/O 32 bit transfer Standard Fast PIO Multiword DMA Ultra DMA-33 ATA-66/100 ( ) Disabled (.) Enabled HDD Block transfer ( ) Disabled (.) Enabled OK OK Cancel Cancel 56 8170 N/B MAINTENANCE The “HDD Timing” item sets the data transmit mode of the hard drive. The default setting is Ultra DMA-33 The “I/O 32 bit transfer” item, if enabled, allows you to have better data transfer rate. This effect is more noticeable under DOS system. The default setting is Enabled The “HDD Block transfer” item, if enabled, allows you to use hard disk with large capacity. The default setting is Enabled @ Virus Alert The “Virus Alert” item, when enabled, gives warning messages if the hard disk boot sector (partition table) has been changed When this item is selected, no submenu will display. A check mark (√) indicates Enabled; an underline (_) indicates disabled The default setting is Disabled. 1.5.3.7 Components Components COM Ports > LPT Port √ PS/2 Mouse Port Legacy Usb > √ Keyboard Numlock Keyboard Repeat > @ COM Ports The “COM Ports” item sets the settings of COM Port A and B. When this item is selected, the submenu will display as shown below: 57 8170 N/B MAINTENANCE COM Ports COM B I/O Settings ( ) ( ) (.) ( ) ( ) Disabled COM1, 3F8, COM2, 2F8, COM3, 3E8, COM4, 2E8, IRQ4 IRQ3 IRQ4 IRQ3 Mode Setting For COM B ( ) IrDA (HPSIR) ( ) ASK IR (.) FAST IR DMA Setting For Fast IR (.) DMA 0 ( ) DMA 1 ( ) DMA 3 OK OK Canel Canel COM B is assigned to IR function. You can further select the IR mode in “Mode Setting for COM B” item and DMA channel in“DMA Setting For Fast IR” when you select “Fast IR” in the mode setting. @ LPT Ports The “LPT Port” item sets the settings of LPT port. When this item is selected, the submenu will display as shown below: 58 8170 N/B MAINTENANCE LPT Port Port Address ( ) (.) ( ) ( ) Port Definition None LPT1, 378, IRQ7 LPT2, 278, IRQ5 LPT3, 3BC, IRQ7 ( ) ( ) ( ) (.) Standard AT (Centronics) Bidirectional (PS-2) Enhanced Parallel (EPP) Extended Capabilities (ECP) DMA Setting For ECP Mode (.) DMA 0 ( ) DMA 1 ( ) DMA 3 EPP 1.7 EPP Type : OK OK Cancel Cancel Your system supports EPP (Enhanced Parallel Port) and ECP (Extended Capabilities Port) standards which turn the standard parallel port into a high speed bi-directional peripheral port. If you select ECP item, you can further choose which DMA channel to use. @ PS/2 Ports The “PS/2 Mouse Port” item enables or disables the PS/2 mouse port When this item is selected, no submenu will display. A check mark (√) indicates Enabled; an underline (_) indicates Disabled. The default setting is enabled. 59 8170 N/B MAINTENANCE @ Legacy USB The “Legacy USB” item sets the settings of legacy USB port which enables or disables the USB keyboard, USB mouse, USB floppy and USB CD-ROM in DOS and SCU. When this item is selected, the submenu will display as shown below: Legacy USB [X] Enable USB Port [X] Enable USB FDD [ ] Enable USB CDROM OK OK Cancel Cancel The “Enable USB Port” item enables or disables USB keyboard and USB mouse. The default setting is enabled The “Enable USB FDD” item enables or disables USB FDD. The default setting is enabled. The “Enable USB FDD” item enables or disables boot from USB CDROM. The default setting is disabled @ Keyboard Numlock Keyboard Numlock” item sets if the numeric keypad will function When this item is selected, no submenu will display. A check mark (√) indicates Enabled; an underline (_) indicates Disabled. The default setting is Enabled. 60 8170 N/B MAINTENANCE Note: If you disable this option, you can only activate the numeric keypad by holding down the [Fn] key first, even when the Num Lock indicator is on. However, an externally-connected keyboard is not affected by this feature. @ Keyboard Repeat The “Keyboard Repeat” item sets the repeat rate and delay time of key strokes. When this item is selected, the submenu will display as shown below: Keyboard Repeat Key Repeat Rate ( ) ( ) (.) ( ) ( ) ( ) 2 6 10 15 20 30 cps cps cps cps cps cps OK OK Key Delay ( ) 1/4 sec (.) 1/2 sec ( ) 3/4 sec ( ) 1 sec Cancel Cancel The “Key Repeat Rate” sets the repeat rate when you hold down a key, while the “Key Delay” item sets the delaying time between key repeats 61 8170 N/B MAINTENANCE 1.5.3.8 Power Menu The Power pull-down menu, as shown below, contains the Power Management settings which help save power Power √ Enable Power Saving Low Power Saving Medium Power Saving High Power Saving √ Customize > Suspend Controls > Resume Timer > @ Enable Power Saving The “Enable Power Saving” item is the master control for the Power Management features. If this item is disabled, all Power menu items except “Suspend Controls” will be automatically disabled. When this item is selected, no submenu will display. A check mark (√) indicates Enabled; an underline (_) indicates Disabled. The default setting is enabled @ Low Power Saving / Medium Power Saving / High Power Saving / Customize four items are mutually-exclusive options. You can select one of them. A check mark (√) indicates Enabled; an underline (_) indicates is enabled an underline (_) indicates Disabled 62 8170 N/B MAINTENANCE Descriptions of the four options are: Options Descriptions Max Performance Select this option for the pre-defined settings which allow maximum performance but shortest battery life. Balanced Power Saving Select this option for the pre-defined settings which allow moderate performance and moderate battery life. Max Power Saving Select this option for the pre-defined settings which allow longest battery life but minimum performance. Customize Select this option for setting up your own preferences. When this option is selected, the submenu will display as shown below that allows you to set up Power Saving features. (See the next subsection for information.) Note: Under Windows98/Windows Me/Windows2000, have built-in ACPI configurations which will override these settings When the “Customize” item is selected, the submenu will display as shown below: Customize Video Timeout: Always On Disk Timeout: Always On Global Timeout: Always On Monitor Video Activity: Disabled OK OK Cancel Cancel 63 8170 N/B MAINTENANCE Video Timeout : The “Video Timeout” item sets the time-out period for the monitor to power down if it is not in use during the set period. The monitor will power up again when any key is pressed. The available options are 30 Sec, 2 Min, 5 Min, 10 Min, 15 Min, 30 Min and Always On. Disk Timeout: The “Disk Timeout” item sets the time-out period for the hard disk to power down if it is not in use during the set period. The hard disk will power up again when next accessed. The available options are 30 Sec, 1 Min, 1.5 Min, 2 Min, and Always On. Global Timeout: The “Global Timeout” item sets the time-out period for initiating Standby mode. Whenever the system. begins idling, the Power Saving starts the time-out for the Standby mode. If the system has been idled for the specified time-out period, system will enter Standby mode. If Standby mode is in effect, several system subsystems go into standby or off mode so that system power will be reduced. The system will wake up from Standby mode when system activity is detected. The available options are 1 Min, 2 Min, 4 Min, 6 Min, 8 Min, 12 Min, 16 Min, and Always On. Monitor Video Activity The “Monitor Video Activity” item sets if the video activity will be monitored. If enabled, any activity on the screen (such as showing a movie title) will prevent the monitor from powering down. The available options are Enabled and Disabled. 64 8170 N/B MAINTENANCE @ Suspend Controls The “Suspend Controls” item lets you micromanage several suspend features. When this item is selected, the submenu will display as shown below: Suspend Controls Power Button Function: Lid Switch Function: Suspend type Power On/Off Blank LCD ( ) Suspend To Disk (.) Suspend To Ram Suspend Timeout: Suspend-to-disk: OK OK Never Never Cancel Cancel Power Button Function : This item sets the function of the power button. The available options are Power On/Off and Suspend/ Resume. Note: When this item is set to “Suspend/Resume”, you can turn off the power by pressing the button for 4 seconds. Lid Switch Function : This item sets the sequential event when the top cover is closed while power is on. The available options are Blank LCD, Suspend and CRT/TV Display. 65 8170 N/B MAINTENANCE Suspend Type: This item sets the suspend mode the system will enter. The available options are Suspend To Disk, Suspend To RAM. When Suspend-to-RAM mode is initiated, several subsystems will enter standby or power-off mode to conserve power. The system will wake up from Suspend-to-RAM mode when a key is pressed. “ Resume Timer”, if enabled, can also wake up the system from Suspend-to-RAM mode. When Suspend-to-Disk mode is initiated, the system preserves all the running application programs as a file in a “suspend-to-disk partition” on the hard disk and then turns off automatically. Suspend Timeout : The “Suspend Timeout” item sets the time-out period for initiating suspend mode. This item works in conjunction with previous "Global Timeout" item. When the system enters standby mode, the Power Saving starts the time-out for the Suspend mode. If the system has been in standby mode for the specified time-out period, system will enter Suspend mode. The Suspend mode is determined by the “Suspend Type” item in the “Suspend Controls” submenu. It can be Suspend-to-RAM, Suspend-to-Disk. The available options are 1 Min, 5 Min, 10 Min, 20 Min, 20 Min, 30 Min, and Never. Suspend-to-disk: The “Suspend-to-disk” item sets the time-out period for initiating suspend-to-disk mode. This item works in conjunction with previous "Suspend Timeout" item. When the system enters suspend-to-ram mode, the Power Saving starts the time-out for the Suspend-to-disk mode. If the system has been in suspend-to-ram mode for the specified time-out period, system will enter suspend-to-disk mode. The available options are 1 Min, 5 Min, 10 Min, 20 Min, 30 Min, and Never. 66 8170 N/B MAINTENANCE @ Resume Timer The Resume Timer” item sets the date and time the system will resume from suspend mode. When this item is selected, the submenu will display as shown below : Resume Timer Alarm Resume : Disable Resume Month 8 Resume Day 8 Resume Hour 12 Resume Minute 0 OK OK Cancel Cancel The default setting is Disabled 1.5.3.9 Exit Menu The Exit pull-down menu, as shown below, displays ways of exiting SCU. After finished with your settings, you must save and exit SCU so that the settings can take effect Exit Save and Exit Exit (No Save) Default Settings Restore Settings Version Info > > > > > 67 8170 N/B MAINTENANCE Descriptions of the Exit choices are: Choices Descriptions Save and Reboot Save changes and reboot the system. Exit (No Save) Exit without saving the changes you have made. Default Settings Load factory default values for all the items. Restore Settings Restore previous values for all the items. Version Info Show BIOS version information 1.5.4 Function Hotkeys Fn + F5 Toggle display output. The display switch sequence, please refer to chapter 6 Fn + F6 Brightness Down (16 levels) Fn + F7 Brightness Up (16 levels) Fn + F10 Enable/Disable battery warning beep Fn + F11 Panel on/off Fn + F12 Suspend to RAM or disk 68 8170 N/B MAINTENANCE 1.5.5 Display Out When you boot the system with CRT, display output is LCD&CRT mode. When boot with CRT, the display switch sequence by hotkey FnF5 is as following: LCD&CRT->LCD->CRT When boot with CRT and TV, the display switch sequence by hotkey FnF5 is as following: LCD&CRT->TV&CRT->TV->LCD->CRT 1.5.6 LID @ In Non-ACPI Operating System: LID switch function is dependent on the setting in BIOS setup menu. “Blank LCD” - LCD will be blank when LID is closed. Before LID is closed LID is closed LID is opened LCD is active LCD is blank LCD is active LCD is blank LCD is blank LCD is blank 69 8170 N/B MAINTENANCE “Suspend” -system will enter suspend mode when LID is closed. Before LID is closed LID is closed LID is opened System is On System enters Suspend System still in Suspend System in Suspend System still in Suspend System still in Suspend “CRT/TV Display” -display will be switched to CRT/TV when LID is closed. When the LID is closed, the LCD will be inactive and external display device will be active. When the LID is opened, the display devices status (active/inactive) will be restored to the state before the LID is closed. Some special conditions are list below. Before LID is closed LCD (active) CRT (present, inactive) TV(present, inactive) LCD (inactive) CRT/TV is present LID is closed LCD (inactive) CRT (active) TV(inactive) LCD (inactive) CRT/TV is plugged out LID is opened LCD (active) CRT (inactive) TV(inactive) LCD (active) CRT/TV is not present @ In ACPI Operating System: The LID switch function is dependent on the setting of the Power Management in the operating system. 70 8170 N/B MAINTENANCE 1.5.7 VGA Resolution of Windows 98/Me Driver (Need Modifying via VGA Driver) LCD(LCD&CRT) Resolution Color 640*480 256, 16bit, 32bit 800*600 256, 16bit, 32bit 1024*768 256, 16bit, 32bit CRT(TV) Resolution Color 640*480 256, 16bit, 32bit 800*600 256, 16bit, 32bit 1024*768 256, 16bit, 32bit 1280*1024 256, 16bit 1600*1200 256, 16bit TV(TV+CRT) Resolution Color 640*480 256, 16bit, 32bit 800*600 256, 16bit, 32bit 71 8170 N/B MAINTENANCE 1.5.8 LED Indicators System has nine status LED indicators to display system activity which include below LCD panel unit and above keyboard: 1.5.8.1 Three LED indicators below LCD panel unit: From left to right that indicate AC POWER, BATTERY POWER and BATTERY STATUS ® AC POWER: This LED lights green when the notebook is being powered by AC, and flash (on 1 second, off 1 second ) when Suspend to DRAM is active using AC power. The LED is off when the notebook is off or powered by batteries, or when Suspend to Disk. ® BATTERY POWER:This LED lights green when the notebook is being powered by batteries, and flashes (on 1 second, off 1 second ) when Suspend to DRAM is active using battery power. The LED is off when the notebook is off or powered by AC, or when Suspend to Disk. ® BATTERY STATUS:During normal operation, this LED stays off as long as the battery is charged. When the battery charge drops to 10% of capacity, the LED lights red, flashes per 1 second and beeps per 2 second. When AC is connected, this indicator glows green if the battery pack is fully charged, or orange (amber) if the battery is being charged. 1.5.8.2 Five LED indicators in front of palm rest: From left to right that indicates CD-ROM/MO, HARD DISK DRIVE, , NUM LOCK, CAPS LOCK and SCROLL LOCK. 72 8170 N/B MAINTENANCE 1.5.8.3 Mail/Blue-Tooth LED indicators in front of palm rest: The left side green LED flashing means new mail coming. Otherwise the LED is always OFF. The right side red LED ON means Blue-Tooth module turn ON. 1.5.9 Power Management 1.5.9.1 Features ® APM 1.2/1.1/1.0 compliant ® Battery warning beep ® Battery low suspend to RAM/disk ® Cover switch close to panel off, standby, or suspend ® Hot-key suspend ® Hot-key panel on/off ® Auto clock throttling to prevent overheating ® ACPI 1.0 compliant ® User programmable standby/suspend timers and sustained events when OS doesn’t support APM/ACPI 1.5.9.2 Device power state Note: Each device power states are described in the chapter titled Components & Drives. Please refer to those paragraphs. BIOS will not automatically manage devices’ power states if ACPI engaged or APM engaged but disabled. 73 8170 N/B MAINTENANCE 1.5.9.3 System power state Definitions when ACPI engaged Global States: G0 – Global system is working G1 – Global system is sleeping G3 – Global system is mechanical-off Suspend States: S1 – CPU stop, no system context lost S2 – CPU stop, no system context lost except CPU & cache’s context is lost S3 – CPU stop, the whole system context lost except system memory content is maintained S4 – CPU stop, all system context saved to nonvolatile media before lost. S5 – Soft Off CPU States: C0 – CPU is working C1 – CPU is in Auto Halt Mode C2 – CPU is in Quick Start Mode, the system will maintain the cache coherency C3 – CPU is in Deep Sleep Mode, the system must disable any event which could make the cache lost coherency. This model is not support C3 mode. 74 8170 N/B MAINTENANCE 1.5.9.4 Definitions when APM engaged System States: Full On Idle Standby Suspend Save to Disk -Full running state, the system is in optimized performance -Clock throttling state, CPU is running between C0 & C2 states -Same as S1/S2 above -Same as S3 above (Including save-to-ram and power-on-suspend) -Same as S4 above Note: When Save to Disk partition is not made on disk, BIOS will choose Save to RAM instead of Save to Disk Enter Condition: Idle -Entered when CPU Idle Function is called Standby -Entered when SetPowerState(Standby) Function is called Suspend -Entered when SetPowerState(Suspend) is called, and user select STR in SCU Save to Disk -Entered when SetPowerState(Suspend) is called, and user select STD in SCU Resume Event : Idle -Resume when CPU Busy Function is called Standby -Resume only when keyboard device have activities, when ring come in on internal modem or PCMCIA card. The reason for not selecting track-pad as resume event is that, it’s too sensitive sometimes Suspend -Entered when SetPowerState(Suspend) is called, and user select STR in SCU Save to Disk -Entered when SetPowerState(Suspend) is called, and user select STD in SCU 75 8170 N/B MAINTENANCE Event Notifications: Standby -When all the devices have no system activities for a specific time period, BIOS will inform a standby event once OS calls GetPMEvent Function. Suspend -When all the devices have no system activities for a specific time period, BIOS will inform a suspend event once OS calls GetPMEvent Function. Activities -System activities is defined in SCU one by one. SCU also includes two columns for the time periods for Standby and Suspend. In addition, Keyboard activity is always one of the system activities. Whenever any system activities detected, timers for Standby and Suspend are reloaded into the value specified. By the way, RTC could also programmable to wake up the system from Standby and Suspend states. Exception -Note, when APM is disabled, BIOS should disable all timers and not to automatically power manage devices. Furthermore, the APM BIOS will neither response to CPU Idle Function, nor recognize the time periods set for Standby and Suspend in SCU. 1.5.9.5 Definitions when no APM or ACPI engaged System States: Full On -Full running state, the system is in optimized performance Idle -No Idle mode support in this situation . Standby -Same as S1/S2 above Suspend -Same as S3 above (Including save-to-ram and power-on-suspend) 76 8170 N/B MAINTENANCE Save to Disk -Same as S4 above Note: When Save to Disk partition isn’t made on disk, BIOS will choose Save to RAM instead of Save to Disk Resume Event: Standby -Resume when keyboard/trackpad/PS2 devices have activities, when ring come in on internal modem or PCMCIA card, or when COM has activities if user select to resume from COM port Suspend -Same as resume events for Standby state Save to Disk -Resume when User push power button Enter conditions: -The timers for Standby and Suspend mode when APM engaged are also applied to this situation that no APM or ACPI engaged. Special Events: -Cover switch, or called lid could trigger an event to LCD panel off, Standby(S1/S2), or Suspend(S3/S4). The exact state triggered is selected in SCU -Power button is also a resume event for all power saving mode except the Idle state -When battery capacity is low under 10% while AC is not plug-in, system will begin to alert via PC speaker. User could also press Fn+F10 to disable/enable the warning beep. Once the battery capacity is critically under 3%, system BIOS will try to force the whole system into the STD state. 77 8170 N/B MAINTENANCE 1.5.9.6 Save to disk partition utility 0VMAKFIL.EXE S support partition only Usage: 0VMAKEFILE.EXE -P < Partition size>= total of system RAM size + total of video RAM size 1.5.9.7 ACPI @ Custom Software SMI Command for ACPI(Modifying if Need) (1) 0x81 : Notify BIOS that the system is going to enter S3 (2) 0x82 : Notify BIOS that the system wake up from S3 (3) 0x83 : Get AC Status (4) 0x84 : Get Battery General Status (_STA) (5) 0x85 : Get Battery Information (_BIF) (6) 0x86 : Get Battery Present Status (_BST) (7) 0x87 : Get Battery Trip Point (_BTP) 78 8170 N/B MAINTENANCE @ CMOS mapping for ACPI battery control method to use (Modifying if Need) Index Description 0x40 AC Status 0x41 Battery Info 1 0x42 Battery Info 2 0x43 Battery Info 3 0x44~0x45 Last Full Charge Capacity 0x46~0x47 Remaining Capacity 0x48~0x49 Design Capacity 0x4A~0x4B Design Voltage 0x4C SOC1 0x4D Current Voltage 0x4E Battery Trip Point Comment Bit0: 0 – AC present 1 – AC not present Bit0: Bit1: 0 – NiMH 1 – LiON Bit0: 0 – Battery not present 1 – Battery present Bit1: Bit2: 0 – no force charge 1 – force charge Bit3: Bit0: 0 – no trickle charge 1 – trickle charge 1.5.10 Post Massage Reference to 7.2 79 8170 N/B MAINTENANCE 1.5.11 GPIO settings 1.5.11.1 South Bridge @ GPIO Signal I/O Address GPIO Register I/O Address Map GPIO # 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Multi. Func./Note REQ[A]# REQ[B]#/REQ[5]# Not Implement PIRQ[F]# PIRQ[G]# Not Implement Not Implement Not Implement SMBALERT# Not Implement Not Implement GNT[A]# GNT[B]#/GNT[5]# Type I I N/A I I N/A I I I N/A N/A I I I N/A N/A O O O O O O Signal Name / Description Signal Select Register SCI# EXTSMI# ENABKL_MSK# CDROM_PWRON# HDD_PWRON# 80 8170 N/B MAINTENANCE 22 23 24 25 26 27 28 29 30 31 Not Implement Not Implement Not Implement Not Implement O O I/O I/O N/A I/O I/O N/A N/A N/A DRAMENA 1394WR# PCIRST_MSK# GPIOBASE+04 bit24 = 0 GPIOBASE+04 bit25 = 0 GATE1394# SPK_OFF GPIOBASE+04 bit27 = 0 GPIOBASE+04 bit28 = 0 81 8170 N/B MAINTENANCE 2. System Assembly & Disassembly 2.1 System View 2.1.1 Front View Stereo Speaker Set Device Indicators Mini IEEE1394 Connector Audio Input Connector Line Out Phone Jack Volume Control Top Cover Latch 2.1.2 Left-Side View Kensington Lock Ventilation Openings RJ-45 Connector PC Card Slot Hard Disk Drive 82 8170 N/B MAINTENANCE 2.1.3 Right-Side View Battery Pack CD-ROM/DVD-ROM Drive 2.1.4 Rear View Power Connector S-Video Output Connector USB Ports Parallel Port D/D Fan RJ-11 Connector VGA Port Ventilation Openings 83 8170 N/B MAINTENANCE 2.1.5 Top-Open View LCD Screen Microphone Keyboard Touch pad Power Button Easy Start Buttons Battery Charge Indicator Battery Power Indicator AC Power Indicator 84 8170 N/B MAINTENANCE 2.2 System Disassembly The section discusses at length each major component for disassembly/reassembly and show corresponding illustrations. Use the chart below to determine the disassembly sequence for removing components from the notebook. NOTE: Before you start to install/replace these modules, disconnect all peripheral devices and make sure the notebook is not turned on or connected to AC power. 2.2.1 Battery Pack 2.2.2 Keyboard Modular Components 2.2.3 CPU 2.2.4 HDD Module 2.2.5 CD/DVD-ROM Drive 2.2.6 SO-DIMM NOTEBOOK 2.2.7 LCD Assembly LCD Assembly Components 2.2.8 LCD Panel 2.2.9 Inverter Board 2.2.10 System Board Base Unit Components 2.2.11 Touch pad 2.2.12 Modem Card 85 8170 N/B MAINTENANCE 2.2.1 Battery Pack Disassembly 1. Carefully put the notebook upside down. 2. Slide the release lever to the “unlock” ( ) position (), then slide and hold the release lever outwards and pull the battery pack out of the compartment (). (Figure 2-1) Figure 2-1 Remove the battery pack Reassembly 1. Push the battery pack into the compartment. The battery pack should be correctly connected when you hear a clicking sound. 2. Slide the release lever to the “lock” ( ) position. 86 8170 N/B MAINTENANCE 2.2.2 Keyboard Disassembly 1. Insert a small rod, such as a straightened paper clip, into the eject hole near the power connector of the notebook. (Figure 2-2) Figure 2-2 Insert a rod easy to remove LED Panel Figure 2-3 Remove LED Panel 2. Open the top cover. Push the rod firmly and slide the LED panel to the left (). Then lift the LED panel up from the left side () (Figure 2-3) 87 8170 N/B MAINTENANCE 3. Remove three screws fastening keyboard on the base unit cover. (Figure 2-4) 4. Slightly lift up the keyboard and disconnect the cable from the system board to detach the keyboard. (Figure 2-5) Figure 2-4 Remove three Screws Figure 2-5 Remove keyboard Reassembly 1. Reconnect the keyboard cable and fit the keyboard back into place. 2. Replace the LED panel. 88 8170 N/B MAINTENANCE 2.2.3 CPU Disassembly 1. Remove the LED panel and keyboard to access the CPU compartment. (See section 2.2.2 Disassembly.) 2. Remove five screws locking the heatsink cover. (Figure 2-6) Figure 2-6 Remove the cover Figure 2-7 Remove the heatsink 3. Remove three screws locking the heatsink. (Figure 2-7) 89 8170 N/B MAINTENANCE 4. Disconnect the fan’s power cord from the system board, then lift up the heatsink. (Figure 2-8) 2 1 Figure 2-8 Remove the fan’s power cord Figure 2-9 Remove the CPU 5. push the lever to the right. Then lift up the lever to the vertical position. Finally, remove the existing CPU. Reassembly 1. Carefully, Align the arrowhead corner of the CPU with the beveled corner of the socket, then insert the CPU pins into the holes. Place the lever back to the horizontal position and push the lever to the left . 2. Connect the fan’s power cord to the system board, fit the heatsink onto the top of the CPU and secure with three screws. 3. Replace the keyboard .Then replace LED panel. 90 8170 N/B MAINTENANCE 2.2.4 HDD Module Disassembly 1. Carefully put the notebook upside down. 2. Remove one screw and slide the HDD module out of the compartment. (Figure 2-10) Figure 2-10 Remove HDD Module Figure 2-11 Disassemble the hard disk 3. Remove six screws to separate the hard disk drive from the metal shield. (Figure 2-11) Reassembly 1. To install the hard disk drive, place it in the bracket and secure with six screws. 2. Slide the HDD module into the compartment and secure with one screw. 91 8170 N/B MAINTENANCE 2.2.5 CD/DVD-ROM Drive Disassembly 1. Remove the LED panel and keyboard. (See section 2.2.2 Disassembly.) 2. Remove two screws locking the CD/DVD-ROM drive. (Figure 2-12) Figure 2-12 Push out the CD/DVD -ROM drive 3. Use the screwdriver to push the metal pad to the right and the CD/DVD-ROM drive will pop out. Hold the CD/DVD-ROM drive and slide it outwards carefully. (Figure 2-12) Reassembly 1. Push the CD/DVD-ROM drive into the compartment. 2. Secure the CD/DVD-ROM drive with two screws. 3. Replace the keyboard and LED panel. 92 8170 N/B MAINTENANCE 2.2.6 SO-DIMM Disassembly 1. Carefully put the notebook upside down. 2. Remove four screws to access the SO-DIMM socket. 3. Pull the retaining clips outwards () and remove the SO-DIMM (). (Figure 2-13,14) Figure 2-13 Remove the SO-DIMM Cover Figure 2-14 Remove the SO-DIMM Reassembly 1. To install the SO-DIMM, match the SO-DIMM's notched part with the socket's projected part and firmly insert the SO-DIMM into the socket at 20-degree angle. Then push down until the retaining clips lock the SO-DIMM into position. 2. Replace three screws to lock the SO-DIMM socket cover. 93 8170 N/B MAINTENANCE 2.2.7 LCD Assembly Disassembly 1. Open the top cover. Remove the LED panel, keyboard, and heat sink . (See section 2.2.2 and 2.2.Disassembly.) 2. Pull out the antenna from the CPU compartment. 3. Remove the two hinge covers. (Figure 2-15) Figure 2-15 Remove the LCD hinge covers Figure 2-16 Remove cables and Screws to separate LCD 4. Disconnect the LCD cable from the system board, and remove four screws of the hinges. Now you can separate the LCD assembly from the base unit. (Figure 2-16) 94 8170 N/B MAINTENANCE Reassembly 1. Attach the LCD assembly to the base unit and secure with four screws on the hinges. 2. Reconnect the antenna to the connector on the Mini PCI socket. 3. Reconnect the LCD cable to the system board. 4. Replace the heatsink, keyboard and LED panel.two hinge covers. 5. Replace two hinge covers. 95 8170 N/B MAINTENANCE 2.2.8 LCD Panel Disassembly 1. Remove the LCD assembly. (See section 2.2.7 Disassembly.) 2. Remove the four rubber pads and four screws on the corners of the panel. (Figure 2-17) Figure 2-17 Remove LCD frame Figure 2-18 Remove LCD panel 3. Insert a flat screwdriver to the lower part of the frame and gently pry the frame out. Repeat the process until the frame is completely separated from the housing. 4. Remove the two screws on two sides and two screws on the lower part of of the LCD panel, and disconnect the cable from the inverter board. (Figure 2-18) Reassembly 1. Fit the LCD panel back into place and secure with four screws, and reconnect the cable to the inverter board. 2. Fit the LCD frame back into the housing and replace the four screws and four rubber pads. 3. Replace the LCD assembly. (See section 2.2.7 Reassembly.) 96 8170 N/B MAINTENANCE 2.2.9 Inverter Board Disassembly 1. Remove the LCD assembly. (see section 2.2.7 Disassembly. ). 2. Detach the LCD Panel. (See section 2.2.8 Disassembly. ) 3. To remove the inverter board on the bottom of the LCD assembly, disconnect the cable and remove one screw. (Figure 2-19) Figure 2-19 Remove the Inverter Board Reassembly 1. Fit the inverter board back into place and secure with one screw. 2. Reconnect the cable. 3. Replace the LCD frame. (See section 2.2.8 Reassembly.) 4. Replace the LCD assembly. (See section 2.2.7 Reassembly.) 97 8170 N/B MAINTENANCE 2.2.10 System Board Disassembly 1. Remove the battery pack, keyboard, CPU, HDD module, CD/DVD-ROM drive and LCD assembly. (See sections2.2.1; 2.2.2; 2.2.3; 2.2.4; 2.2.5; 2.2.7 Disassembly.) 2. Remove fourteen screws on the bottom of the notebook. (Figure 2-20) Figure 2-20 Remove the bottom Figure 2-21 Remove the speaker assembly 3. Remove the speaker assembly from the notebook. (Figure 2-21) 98 8170 N/B MAINTENANCE 4. Remove five screws on the rear side of the notebook, and remove three screws locking on the base unit cover. (Figure 2-22) Figure 2-22 Remove the base unit cover Figure 2-23 Lift up the base unit cover 5. Lift up the base unit cover and disconnect the touch pad cord. (Figure 2-23) 99 8170 N/B MAINTENANCE 6. Remove two screws fastening the button board on base unit. and then disconnect two cables from the system board. (Figure 2-23) Figure 2-23 Remove the screws Figure 2-24 Remove the base unit cover 7. Remove five screws from the system board,and lift up the base unit to access the system board. (Figure 2-24) Reassembly 1. Replace five screws fastening the base unit 2. Reconnect two cables to the system board. 3. Replace the button board with two screws. 4. Reconnect the touch pad cable and replace the base unit cover. 5. Replace three screws fastening the base unit cover. 6. Replace five screws on the rear side of the notebook. 100 8170 N/B MAINTENANCE 7. Replace the speaker assembly. 8. Replace fourteen screws on the bottom of the notebook. 9. Replace the battery pack, LED panel, keyboard, CPU, HDD module, CD/DVD-ROM drive and LCD assembly. 101 8170 N/B MAINTENANCE 2.2.11 Touch PAD Disassembly 1. Remove the base unit cover. (See steps 1-6 in section 2.2.11 Disassembly.) 2. Remove the six screws to lift up the touch pad holder and touch pad panel. (Figure 2-25) Figure 2-25 Remove the touch pad Reassembly 1. Replace the touch pad holder and touch pad panel, and secure with six screws. 2. Assemble the notebook. (See section 2.2.11 Reassembly.) 102 8170 N/B MAINTENANCE 2.2.12 Modem Card Disassembly 1. Remove the battery pack, keyboard, CPU, HDD module, CD/DVD-ROM drive, and LCD assembly. (See sections2.2.1; 2.2.2; 2.2.3; 2.2.4; 2.2.5; 2.2.7 Disassembly.) 2. Disassemble the notebook to access the system board. (See section 2.2.10 Disassembly.) 3. Remove the two screws fastening the modem card,and then disconnect the cable from system board. (Figure 2-26) Figure 2-26 Remove the Modem card Reassembly 1. Reconnect the cable to the modem card and secure the modem card with two screws. 2. Assemble the notebook. (See section 2.2.10 Reassembly.) 103 8170 N/B MAINTENANCE 3. Definition & Location Connectors / Switches Setting 3.1 Main Board ( Side A) J1:External VGA Connector J10 J3 J6 J2:LCD Connector J20 J28 J3:D/D Board connector J5 VR1 J11 J4 J15 SW6 J19 J13 U1 J12 J22 J16 J21 J1 J14 J7 J18 J5:Easy Start Button Connector J6:External USB(PIO,IR,TV OUT)Connector J7:CPU FAN Connector J8:Card Bus Socket J8 J9:RJ45 J10:Secondary EIDE Connector J9 J509 J2 J4: Modem Daughter Board to RJ11Connector J11:Modem Daughter Board J12:Internal Keyboard Connector J13:RJ11 104 8170 N/B MAINTENANCE 3. Definition & Location Connectors / Switches Setting 3.1 Main Board ( Side A) J14:Primary EIDE Connector J10 J3 J6 J15:Touch PAD Connector J20 J28 J16:Internal Microphone J5 VR1 J11 J4 J15 SW6 J19 J13 U1 J12 J21 J14 J7 J18 J20:Internal Speaker Connector(R channel) J21:Mini IEEE1394 Connector J22:External Micro Phone Jack J8 J28:Battery Connector VR1:Volume regulator J9 J509 J2 J19:Line Out Phone Jack J22 J16 J1 J18:Internal Speaker Connector(L channel) SW6:Switch Cover 105 8170 N/B MAINTENANCE 3. Definition & Location Connectors / Switches Setting 3.1 Main Board ( Side B ) PU508 U508 J502:D/D FAN connector J503:DIMM1 U509 J503 J505:DIMM2 U516 U505 U504 J505 J502 U507 106 8170 N/B MAINTENANCE 3. Definition & Location Connectors / Switches Setting 3.2 D/D Board J1:Parallel port connector J4 J1 J5 PJ2 J2 J3 J6 IR J2:USB2 connector J3:USB0 connector PJ1 J4:TV Out connector PU1 J5:Power Jack connector J6:Inverter Board connector PJ1:D/D Board connector PJ2: External USB(PIO,IR,TV OUT)Connector USB0 USB0 connector connector Power Power Jack Jack connector connector J5 TV TV Out Out connector connector J4 J3 J2 J1 Parallel Parallel port port connector connector D/D Board Rear Side View 107 8170 N/B MAINTENANCE 3. Definition & Location Connectors / Switches Setting 3.3 Touch PAD Board SW1:SCRL UP U1 SW2:RIGHT J1 SW3:LEFT Connect to MB J15 SW4:SCRL DOWN J501:Touch PAD connector(to MB) J500 SW1 J501 SW3 SW2 SW4 108 8170 N/B MAINTENANCE 4. Definition & Location Major Components 4.1 Main Board ( Side A ) U1:P4(Willamette/Northwood)Micro CPU U3:82845 (Memory controller HUB) U18 U13 U3 U12 U1 U4:RTL8139CL(LANPHY) U7:PCI4410(PCMCIA/1394 controller) U11:74AHC373_V U11 U12:Flash Rom U13:SN74CBTD3384(Level Shift) U17 U17:82801BA(I/O controller) U18: Audio amplifier U4 J509 U7 109 8170 N/B MAINTENANCE 4. Definition & Location Major Components 4.1 Main Board ( Side B ) U504:TPS2211 U507:ICS950805(Clock generator) U508:Micro Controller(H8 F3437) PU508 U509:PC87393(Supper I/O) U508 U516:ATI VGA controller U507 U509 J502 PU508:LTC1709EG-9(CPU_CORE regulator) U504 U516 110 8170 N/B MAINTENANCE 4. Definition & Location Major Components 4.2 D/D Board J4 J1 PJ2 U501:PAC128401Q J5 J2 J3 IR U502:PAC128401Q PU1:MAX1632(3V.5V.12V regulator) PJ1 PU501:AO4400 PU1 PU502:SI4832DY PU503:SI4800DY D/D Board (Side A) PU504:AO4400 PU505:SI4832Dy PU506:SI4800Y U502 U501 PQ502:SI4835DY PQ503:SI4835DY PQ502 PU502 PQ503 PU505 PU506 PU503 PU501 PU504 D/D Board (Side B) 111 8170 N/B MAINTENANCE 5. Pin Descriptions of Major Components 5.1 Pentium 4(Willamette/Northwood) mFC-PGA2 478 pin Name A[35:3]# A20M# Type Input/ Output Input ADS# Input/ Output ADSTB[1:0]# Input/ Output Description A[35:3]# (Address) define a 2 36 -byte physical memory address space. In sub-phase 1 of the address phase, these pins transmit the address of a transaction. In sub-phase 2, these pins transmit transaction type information. These signals must connect the appropriate pins of all agents on the Pentium 4 processor in the 478-pin package system bus. A[35:3]# are protected by parity signals AP[1:0]#. A[35:3]# are source synchronous signals and are latched into the receiving buffers by ADSTB[1:0]#. On the active-to-inactive transition of RESET#, the processor samples a subset of the A[35:3]# pins to determine power-on configuration. If A20M# (Address-20 Mask) is asserted, the processor masks physical address bit 20 (A20#) before looking up a line in any internal cache and before driving a read/write transaction on the bus. Asserting A20M# emulates the 8086 processor's address wrap-around at the 1-Mbyte boundary. Assertion of A20M# is only supported in real mode. A20M# is an asynchronous signal. However, to ensure recognition of this signal following an Input/Output write instruction, it must be valid along with the TRDY# assertion of the corresponding Input/Output Write bus transaction. ADS# (Address Strobe) is asserted to indicate the validity of the transaction address on the A[35:3]# and REQ[4:0]# pins. All bus agents observe the ADS# activation to begin parity checking, protocol checking, address decode, internal snoop, or deferred reply ID match operations associated with the new transaction. Address strobes are used to latch A[35:3]# and REQ[4:0]# on their rising and falling edges. Strobes are associated with signals as shown below. Signals Associated Strobe REQ[4:0]#, A[16:3]# A[35:17]# ADSTB0# ADSTB1# Name AP[1:0]# BCLK[1:0] BINIT# BNR# Type Description Input/ Output AP[1:0]# (Address Parity) are driven by the request initiator along with ADS#,A[35:3]#, and the transaction type on the REQ[4:0]#. A correct parity signal is high if an even number of covered signals are low and low if an odd number of covered signals are low. This allows parity to be high when all the covered signals are high. AP[1:0]# should connect the appropriate pins of all Pentium 4 processor in the 478-pin package system bus agents. The following table defines Request Signals subphase 1 subphase 2 A[35:24]# A[23:3]# REQ[4:0]# AP0# AP1# AP1# AP1# AP0# AP0# Input The differential pair BCLK (Bus Clock) determines the system bus frequency. All processor system bus agents must receive these signals to drive their outputs and latch their inputs. All external timing parameters are specified with respect to the rising edge of BCLK0 crossing V CROSS . Input/ BINIT# (Bus Initialization) may be observed and driven by all Output processor system bus agents and if used, must connect the appropriate pins of all such agents. If the BINIT# driver is enabled during power-on configuration, BINIT# is asserted to signal any bus condition that prevents reliable future operation. If BINIT# observation is enabled during power-on configuration, and BINIT# is sampled asserted, symmetric agents reset their bus LOCK# activity and bus request arbitration state machines. The bus agents do not reset their IOQ and transaction tracking state machines upon observation of BINIT# activation. Once the BINIT# assertion has been observed, the bus agents will re-arbitrate for the system bus and attempt completion of their bus queue and IOQ entries. If BINIT# observation is disabled during power-on configuration, a central agent may handle an assertion of BINIT# as appropriate to the error handling architecture of the system. BNR# (Block Next Request) is used to assert a bus stall by any bus Input/ agent who is unable to accept new bus transactions. During a bus Output stall, the current bus owner cannot issue any new transactions. 112 8170 N/B MAINTENANCE 5.1 Pentium 4(Willamette/Northwood) mFC-PGA2 478 pin Name BPM[5:0]# BPRI# BR0# BSEL[1:0] COMP[1:0] Type Input/ Output Description BPM[5:0]# (Breakpoint Monitor) are breakpoint and performance monitor signals. They are outputs from the processor which indicate the status of breakpoints and programmable counters used for monitoring processor performance. BPM[5:0]# should connect the appropriate pins of all Pentium 4 processor in the 478-pin package system bus agents. BPM4# provides PRDY# (Probe Ready) functionality for the TAP port. PRDY# is a processor output used by debug tools to determine processor debug readiness. BPM5# provides PREQ# (Probe Request) functionality for the TAP port. PREQ# is used by debug tools to request debug operation of the processor. Please refer to the Intel® Pentium® 4 Processor in the 478-pin Package and Intel® 850 Chipset Platform Design Guide for more detailed information. These signals do not have on-die termination. the Intel® Pentium® 4 Processor in the 478-pin Package and Intel® 850 Chipset Platform Design Guide for termination requirements. Input BPRI# (Bus Priority Request) is used to arbitrate for ownership of the processor system bus. It must connect the appropriate pins of all processor system bus agents. Observing BPRI# active (as asserted by the priority agent) causes all other agents to stop issuing new requests, unless such requests are part of an ongoing locked operation. The priority agent keeps BPRI# asserted until all of its requests are completed, then releases the bus by deasserting BPRI#. Input/ BR0# drives the BREQ0# signal in the system and is used by the Output processor to request the bus. During power-on configuration this pin is sampled to determine the agent ID = 0. This signal does not have on-die termination and must be terminated. Output The BCLK[1:0] frequency select signals BSEL[1:0] are used to select the processor input clock frequency. The required frequency is determined by the processor, chipset and clock synthesizer. All agents must operate at the same frequency. The Pentium 4 processor in the 478-pin package operates currently at a 400 MHz system bus frequency (100 MHz BCLK[1:0] frequency). For more information about these pins, including termination recommendations. Analog COMP[1:0] must be terminated on the system board using precision resistors. Refer to the Intel® Pentium® 4 Processor in the 478-pin Package and Intel® 850 Chipset Platform Design Guide for details on implementation. Name D[63:0]# Type Description Input/ Output D[63:0]# (Data) are the data signals. These signals provide a 64-bit data path between the processor system bus agents, and must connect the appropriate pins on all such agents. The data driver asserts DRDY# to indicate a valid data transfer. D[63:0]# are quad-pumped signals and will thus be driven four times in a common clock period. D[63:0]# are latched off the falling edge of both DSTBP[3:0]# and DSTBN[3:0]#. Each group of 16 data signals correspond to a pair of one DSTBP# and one DSTBN#. The following table shows the grouping of data signals to data strobes and DBI#. Quad-Pumped Signal Groups Data Group D[15:0]# D[31:16]# D[47:32]# D[63:48]# DBI[3:0]# DBR# Input/ Output Output DSTBN#/ DSTBP# 0 1 2 3 DBI# 0 1 2 3 Furthermore, the DBI# pins determine the polarity of the data signals. Each group of 16 data signals corresponds to one DBI# signal. When the DBI# signal is active, the corresponding data group is inverted and therefore sampled active high. DBI[3:0]# are source synchronous and indicate the polarity of the D[63:0]# signals. The DBI[3:0]# signals are activated when the data on the data bus is inverted. The bus agent will invert the data bus signals if more than half the bits, within the covered group, would change level in the next cycle. DBI[3:0] Assignment To Data Bus Bus Signal Data Bus Signals DBI3# DBI2# DBI1# DBI0# D[63:48]# D[47:32]# D[31:16]# D[15:0]# DBR# is used only in processor systems where no debug port is implemented on the system board. DBR# is used by a debug port interposer so that an in-target probe can drive system reset. If a debug port is implemented in the system, DBR# is a no connect in the system. DBR# is not a processor signal. 113 8170 N/B MAINTENANCE 5.1 Pentium 4(Willamette/Northwood) mFC-PGA2 478 pin Name Type DBSY# Input/ Output DEFER# Input DP[3:0]# Input/ Output DSTBN[3:0]# Input/ Output Description DBSY# (Data Bus Busy) is asserted by the agent responsible for driving data on the processor system bus to indicate that the data bus is in use. The data bus isreleased after DBSY# is deasserted. This signal must connect the appropriate pins on all processor system bus agents. DEFER# is asserted by an agent to indicate that a transaction cannot be guaranteed in-order completion. Assertion of DEFER# is normally the responsibility of the addressed memory or Input/Output agent. This signal must connect the appropriate pins of all processor system bus agents. DP[3:0]# (Data parity) provide parity protection for the D[63:0]# signals. They are driven by the agent responsible for driving D[63:0]#, and must connect the appropriate pins of all Pentium 4 processor in the 478-pin package system bus gents. Data strobe used to latch in D[63:0]#. Signals D[15:0]#, DBI0# D[31:16]#, DBI1# D[47:32]#, DBI2# D[63:48]#, DBI3# DSTBP[3:0]# Input/ Output GTLREF Output Input IERR# IGNNE# Associated Strobe DSTBN0# DSTBN1# DSTBN2# DSTBN3# Data strobe used to latch in D[63:0]#. Signals D[15:0]#, DBI0# D[31:16]#, DBI1# D[47:32]#, DBI2# D[63:48]#, DBI3# FERR# Name HIT# HITM# Associated Strobe DSTBP0# DSTBP1# DSTBP2# DSTBP3# FERR# (Floating-point Error) is asserted when the processor detects an unmasked floating-point error. FERR# is similar to the ERROR# signal on the Intel 387 coprocessor, and is included for compatibility with systems using MSDOS*-type floating-point error reporting. GTLREF determines the signal reference level for AGTL+ input pins. GTLREF should be set at 2/3 V CC. GTLREF is used by the AGTL+ receivers to determine if a signal is a logical 0 or logical 1. Refer to the Intel® Pentium® 4 Processor in the 478-pin Package and Intel® 850 Chipset Platform Design Guide for more information. INIT# ITPCLKOUT[1:0] ITP_CLK[1:0] Type Description Input/ HIT# (Snoop Hit) and HITM# (Hit Modified) convey Output transaction snoop operation results. Any system bus agent may assert both HIT# and HITM# together to indicate that it requires Input/ a snoop stall, which can be continued by reasserting Output HIT# and HITM# together. Output IERR# (Internal Error) is asserted by a processor as the result of an internal error. Assertion of IERR# is usually accompanied by a SHUTDOWN transaction on the processor system bus. This transaction may optionally be converted to an external error signal (e.g., NMI) by system core logic. The processor will keep IERR# asserted until the assertion of RESET#, BINIT#, or INIT#. This signals does not have on-die termination. Input IGNNE# (Ignore Numeric Error) is asserted to force the processor to ignore a numeric error and continue to execute noncontrol floating-point instructions. If IGNNE# is deasserted, the processor generates an exception on a noncontrol floating-point instruction if a previous floating-point instruction caused an error.IGNNE# has no effect when the NE bit in control register 0 (CR0) is set. IGNNE# is an asynchronous signal. However, to ensure recognition of this signal following an Input/Output write instruction, it must be valid along with the TRDY# assertion of the corresponding Input/Output Write bus transaction. Input INIT# (Initialization), when asserted, resets integer registers inside the processor without affecting its internal caches or floating-point registers. The processor then begins execution at the power-on Reset vector configured during power-on configuration. The processor continues to handle snoop requests during INIT# assertion. INIT# is an asynchronous signal and must connect the appropriate pins of all processor system bus agents. If INIT# is sampled active on the active to inactive transition of RESET#, then the processor executes its Built-in Self-Test (BIST). Output The ITPCLKOUT[1:0] pins do not provide any output for the Pentium® 4 processor in the 478-pin package. Refer to Input ITP_CLK[1:0] are copies of BCLK that are used only in processor systems where no debug port is implemented on the system board. ITP_CLK[1:0] are used as BCLK[1:0] references for a debug port implemented on an interposer. If a debug port is implemented in the system, ITP_CLK[1:0] are no connects in the system. These are not processor signals. 114 8170 N/B MAINTENANCE 5.1 Pentium 4(Willamette/Northwood) mFC-PGA2 478 pin Name LINT[1:0] LOCK# MCERR# PROCHOT# Type Description Input LINT[1:0] (Local APIC Interrupt) must connect the appropriate pins of all APIC Bus agents. When the APIC is disabled, the LINT0 signal becomes INTR, a maskable interrupt request signal, and LINT1 becomes NMI, a nonmaskable interrupt. INTR and NMI are backward compatible with the signals of those names on the Pentium processor. Both signals are asynchronous. Both of these signals must be software configured via BIOS programming of the APIC register space to be used either as NMI/INTR or LINT[1:0]. Because the APIC is enabled by default after Reset, operation of these pins as LINT[1:0] is the default configuration. Input/ LOCK# indicates to the system that a transaction must occur Output atomically. This signal must connect the appropriate pins of all processor system bus agents. For a locked sequence of transactions, LOCK# is asserted from the beginning of the first transaction to the end of the last transaction. When the priority agent asserts BPRI# to arbitrate for ownership of the processor system bus, it will wait until it observes LOCK# deasserted. This enables symmetric agents to retain ownership of the processor system bus throughout the bus locked operation and ensure the atomicity of lock. Input/ MCERR# (Machine Check Error) is asserted to indicate an Output unrecoverable error without a bus protocol violation. It may be driven by all processor system bus agents. MCERR# assertion conditions are configurable at a system level. Assertion options are defined by the following options: Enabled or disabled. Asserted, if configured, for internal errors along with IERR#. Asserted, if configured, by the request initiator of a bus transaction after it observes an error. Asserted by any bus agent when it observes an error in a bus transaction. For more details regarding machine check architecture, please refer to the IA-32 Software Developer’s Manual, Volume 3: System Programming Guide. Output PROCHOT# will go active when the processor temperature monitoring sensor detects that the processor has reached its maximum safe operating temperature. This indicates that the processor Thermal Control Circuit has been activated, if enabled. Name PWRGOOD Type Input RESET# Input RS[2:0]# Input RSP# Input Description PWRGOOD (Power Good) is a processor input. The processor requires this signal to be a clean indication that the clocks and power supplies are stable and within their specifications. ‘Clean’ implies that the signal will remain low (capable of sinking leakage current), without glitches, from the time that the power supplies are turned on until they come within specification. The signal must then transition monotonically to a high illustrates the relationship of PWRGOOD to the RESET# signal. PWRGOOD can be driven inactive at any time, but clocks and power must again be stable before a subsequent rising edge of PWRGOOD. It must also meet the minimum pulse width and be followed by a 1 to 10 ms RESET# pulse. The PWRGOOD signal must be supplied to the processor; it is used to protect internal circuits against voltage sequencing issues. It should be driven high throughout boundary scan operation. Asserting the RESET# signal resets the processor to a known state and invalidates its internal caches without writing back any of their contents. For a power-on Reset, RESET# must stay active for at least one millisecond after VCC and BCLK have reached their proper specifications. On observing active RESET#, all system bus agents will deassert their outputs within two clocks. RESET# must not be kept asserted for more than 10 ms while PWRGOOD is asserted. A number of bus signals are sampled at the active-to-inactive transition of RESET# for power-on configuration. This signal does not have on-die termination and must be terminated on the system board. RS[2:0]# (Response Status) are driven by the response agent (the agent responsible for completion of the current transaction), and must connect the appropriate pins of all processor system bus agents. RSP# (Response Parity) is driven by the response agent (the agent responsible for completion of the current transaction) during assertion of RS[2:0]#, the signals for which RSP# provides parity protection. It must connect to the appropriate pins of all processor system bus agents. A correct parity signal is high if an even number of covered signals are low and low if an odd number of covered signals are low. While RS[2:0]# = 000, RSP# is also high, since this indicates it is not being driven by any agent guaranteeing correct parity. 115 8170 N/B MAINTENANCE 5.1 Pentium 4(Willamette/Northwood) mFC-PGA2 478 pin Name REQ[4:0]# SKTOCC# SLP# SMI# STPCLK# TCK Type Description Input/ REQ[4:0]# (Request Command) must connect the appropriate Output pins of all processor system bus agents. They are asserted by the current bus owner to define the currently active transaction type. These signals are source synchronous to ADSTB0#. Refer to the AP[1:0]# signal description for a details on parity checking of these signals. Output SKTOCC# (Socket Occupied) will be pulled to ground by the processor. System board designers may use this pin to determine if the processor is present. Input SLP# (Sleep), when asserted in Stop-Grant state, causes the processor to enter the Sleep state. During Sleep state, the processor stops providing internal clock signals to all units, leaving only the Phase-Locked Loop (PLL) still operating. Processors in this state will not recognize snoops or interrupts. The processor will recognize only assertion of the RESET# signal, deassertion of SLP#, and removal of the BCLK input while in Sleep state. If SLP# is deasserted, the processor exits Sleep state and returns to Stop-Grant state, restarting its internal clock signals to the bus and processor core units. If the BCLK input is stopped while in the Sleep state the processor will exit the Sleep state and transition to the Deep Sleep state. Input SMI# (System Management Interrupt) is asserted asynchronously by system logic. On accepting a System Management Interrupt, the processor saves the current state and enter System Management Mode (SMM). An SMI Acknowledge transaction is issued, and the processor begins program execution from the SMM handler. If SMI# is asserted during the deassertion of RESET# the processor will tristate its outputs. Input STPCLK# (Stop Clock), when asserted, causes the processor to enter a low power Stop-Grant state. The processor issues a Stop-Grant Acknowledge transaction, and stops providing internal clock signals to all processor core units except the system bus and APIC units. The processor continues to snoop bus transactions and service interrupts while in Stop-Grant state. When STPCLK# is deasserted, the processor restarts its internal clock to all units and resumes execution. The assertion of STPCLK# has no effect on the bus clock; STPCLK# is an asynchronous input. Input TCK (Test Clock) provides the clock input for the processor Test Bus (also knownas the Test Access Port). Name TESTHI[12:8] TESTHI[5:0] Type Description Input TDI (Test Data In) transfers serial test data into the processor. TDI provides the serial input needed for JTAG specification support. Output TDO (Test Data Out) transfers serial test data out of the processor. TDO provides the serial output needed for JTAG specification support. Input TESTHI[12:8] and TESTHI[5:0] must be connected to a VCC power source through a resistor for proper processor operation. THERMDA Other Thermal Diode Anode. THERMDC Other Thermal Diode Cathode. THERMTRIP# Output Assertion of THERMTRIP# (Thermal Trip) indicates the processor junction temperature has reached a level beyond which permanent silicon damage may occur. Measurement of the temperature is accomplished through an internal thermal sensor which is configured to trip at approximately 135°C.Upon assertion of THERMTRIP#, the processor will shut off its internal clocks (thus halting program execution) in an attempt to reduce the processor junction temperature. To protect the processor, its core voltage (VCC) must be removed following the assertion of THERMTRIP#. Once activated, THERMTRIP# remains latched until RESET# is asserted. While the assertion of the RESET# signal will de-assert THERMTRIP# , if the processor’s junction temperature remains at or above the trip level, THERMTRIP# will again be asserted after RESET# is de-asserted. Input TMS (Test Mode Select) is a JTAG specification support signal used by debug tools. Input TRDY# (Target Ready) is asserted by the target to indicate that it is ready to receive a write or implicit writeback data transfer. TRDY# must connect the appropriate pins of all system bus agents. Input TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST# must be driven low during power on Reset. This can be done with a 680 . pull-down resistor. Input VCCA provides isolated power for the internal processor core PLLs. Refer to the Intel® Pentium® 4 Processor in the 478-pin Package and Intel® 850 Chipset Platform Design Guide for complete implementation details. TDI TDO TMS TRDY# TRST# VCCA 116 8170 N/B MAINTENANCE 5.1 Pentium 4(Willamette/Northwood) mFC-PGA2 478 pin Name VCCIOPLL VCCSENSE VCCVID VID[4:0] VSSA VSSSENSE TMS TRDY# TRST# VCCA Type Description Input VCCIOPLL provides isolated power for internal processor system bus PLLs. Follow he guidelines for VCCA, and refer to the Intel® Pentium® 4 Processor in the 478-pin Package and Intel® 850 Chipset Platform Design Guide for complete implementation details. Output VCCSENSE is an isolated low impedance connection to processor core power(VCC). It can be used to sense or measure power near the silicon with little noise. Input There is no imput voltage requirement for VCCVID for designs intended tosupport only the Pentium 4 processor in the 478-pin package. Refer to the Intel® Pentium® 4 Processor in the 478-pin Package and Intel® 850 Chipset Platform Design Guide for more information. Output VID[4:0] (Voltage ID) pins can be used to support automatic selection of power supply voltages (Vcc). These pins are not signals, but are either an open circuit or a short circuit to VSS on the processor. The combination of opens and shorts defines the voltage required by the processor. The VID pins are needed to cleanly support processor voltage specification variations. See 1.4 for definitions of these pins. The power supply must supply the voltage that is requested by these pins, or disable itself. Input VSSA is the isolated ground for internal PLLs. Output VSSSENSE is an isolated low impedance connection to processor core VSS. It can be used to sense or measure ground near the silicon with little noise Input TMS (Test Mode Select) is a JTAG specification support signal used by debug tools. Input TRDY# (Target Ready) is asserted by the target to indicate that it is ready to receive a write or implicit writeback data transfer. TRDY# must connect the appropriate pins of all system bus agents. Input TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST# must be driven low during power on Reset. This can be done with a 680 . pull-down resistor. Input VCCA provides isolated power for the internal processor core PLLs. Refer to the Intel® Pentium® 4 Processor in the 478-pin Package and Intel® 850 Chipset Platform Design Guide for complete implementation details. 117 8170 N/B MAINTENANCE 5.2 Intel 82845(Brookdale Memory Controller HUB) System Bus singnals Name ADS# BNR# Type Description I/O AGTL+ I/O AGTL+ Address Strobe: The system bus owner asserts ADS# to indicate the first of two cycles of a request phase. Block Next Request: BNR# is used to block the current request bus owner from issuing a new request. This signal dynamically controls the system bus pipeline depth. Bus Priority Request: The MCH is the only Priority Agent on the system bus. It asserts this signal to obtain the ownership of the address bus. This signal has priority over symmetric bus requests and will cause the current symmetric owner to stop issuing new transactions unless the HLOCK# signal was asserted. Bus Request 0#: The MCH pulls the processor bus BR0# signal low during CPURST#. The signal is sampled by the processor on the active - to-inactive transition of CPURST#. The minimum setup time for this signal is 4 BCLKs. The minimum hold time is 2 BCLKs and the maximum hold time is 20 BCLKs. BR0# should be three-stated after the hold time requirement has been satisfied. Processor Reset: The CPURST# pin is an output from the MCH. The MCH asserts CPURST# while RSTIN# (PCIRST# from the ICH2) is asserted and for approximately 1 ms after RSTIN# is deasserted. The CPURST# allows the processor to begin execution in a known state. Data Bus Busy: DBSY# is used by the data bus owner to hold the data bus for transfers requiring more than one cycle. Defer Response: This signal, when asserted, indicates that the MCH will terminate the transaction currently being snooped with either a deferred response or with a retry response. Dynamic Bus Inversion: DBI[3:0]# are driven along with the HD[63:0]# signals. DBI[3:0]# Indicate if the associated data signals are inverted. DBI[3:0]# are asserted such that the number of data bits driven electrically low (low voltage) within the corresponding 16-bit group never exceeds 8. DBI[x]# Data Bits DBI3# HD[63:48]# DBI2# HD[47:32]# DBI1# HD[31:16]# DBI0# HD[15:0]# Data Ready. Asserted for each cycle that data is transferred. BPRI# O AGTL+ BR0# I/O AGTL+ CPURST# O AGTL+ DBSY# I/O AGTL+ O AGTL+ DEFER# DBI[3:0]# DRDY# I/O AGTL+ I/O AGTL+ Name HA[31:3]# HADSTB[1:0]# HD[63:0]# HDSTBP[3:0]# HDSTBN[3:0]# HIT# HITM# HLOCK# Type Description I/O Host Address Bus: HA[31:3]# connect to the system address bus. AGTL+ During processor cycles, HA[31:3]# are inputs. The MCH drives HA[31:3]# during snoop cycles on behalf of the hub interface and AGP/Secondary PCI initiators. HA[31:3]# are transferred at 2x rate. Note that the address is inverted on the system bus. I/O Host Address Strobe: The source synchronous strobes used to AGTL+ transfer HA[31:3]# and HREQ[4:0]# at the 2x transfer rate. Strobe Address Bits HADSTB0# HA[16:3]#, HREQ[4:0]# HADSTB1# HA[31:17]# I/O Host Data: These signals are connected to the system data bus. AGTL+ HD[63:0]# are transferred at a 4x rate. Note that the data signals are inverted on the system bus. I/O Differential Host Data Strobes: The differential source synchronous AGTL+ strobes used to transfer HD[63:0]# and DBI[3:0]# at the 4x transfer rate. Strobe Data Bits HDSTBP3#, HDSTBN3# HD[63:48]#, DBI3# HDSTBP2#, HDSTBN2# HD[47:32]#, DBI2# HDSTBP1#, HDSTBN1# HD[31:16]#, DBI1# HDSTBP0#, HDSTBN0# HD[15:0]#, DBI0# I/O Hit: This signal indicates that a caching agent holds an unmodified AGTL+ version of the requested line. HIT# is also driven in conjunction with HITM# by the target to extend the snoop window. I/O Hit Modified: This signal indicates that a caching agent holds a AGTL+ modified version of the requested line and that this agent assumes responsibility for providing the line. HITM# is also driven in conjunction with HIT# to extend the snoop window. I/O Host Lock: All system bus cycles sampled with the assertion of AGTL+ HLOCK# and ADS#, until the negation of HLOCK# must be atomic (i.e., no hub interface or AGP snoopable access to system memory are allowed when HLOCK# is asserted by the processor). 118 8170 N/B MAINTENANCE 5.2 Intel 82845(Brookdale Memory Controller HUB) System Bus singnals Name HREQ[4:0]# HTRDY# RS[2:0]# SCS[11:0]# SMA[12:0] SBS[1:0] SRAS# SCAS# SWE# SDQ[63:0] SCB[7:0] Type Description I/O Host Request Command: These signals define the attributes of the AGTL+ request. In Enhanced Mode HREQ[4:0]# are transferred at 2x rate. HREQ[4:0]# are asserted by the requesting agent during both halves of Request Phase. In the first half the signals define the transaction type to level of detail that is sufficient to begin a snoop request. In the second half the signals carry additional information to define the complete transaction type. The transactions supported by the MCH host bridge are defined in the Section 5.1. I/O Host Target Ready: HTRDY# indicates that the target of the AGTL+ processor transaction is able to enter the data transfer phase. Response Status: RS[2:0]# indicates the type of response according O AGTL+ to the following the table: RS[2:0] Response Type 000 Idle state 001 Retry response 010 Deferred response 011 Reserved (not driven by MCH) 100 Hard Failure (not driven by MCH) 101 No data response 110 Implicit Write back 111 Normal data response O Chip Select: These signals select the particular SDRAM components AGTL+ during the active state. Note: There are two SCS# signals per SDRAM row. These signals can be toggled on every rising system memory clock edge. O Multiplexed Memory Address: These signals are used to provide AGTL+ the multiplexed row and column address to SDRAM. O Memory Bank Select: SBS[1:0] define the banks that are selected AGTL+ within each SDRAM row. The SMA and SBS signals combine to address every possible location in a SDRAM device. O SDRAM Row Address Strobe: SRAS# is Used with SCAS# and AGTL+ SWE# (along with SCS#) to define the DRAM commands. O SDRAM Column Address Strobe: SCAS# is used with SRAS# AGTL+ andSWE# (along with SCS#) to define the SDRAM commands. O Write Enable: SWE# is used with SCAS# and SRAS# (along with AGTL+ SCS#) to define the SDRAM commands. I/O Data Lines: These signals are used to interface to the SDRAM data AGTL+ bus. I/O Check Bit Data Lines: These signals are used to interface to the AGTL+ SDRAM ECC signals. Name SCKE[5:0] RDCLKO SMA[12:0] RDCLKIN Type Description Clock Enable: These pins are used to signal a self-refresh or O AGTL+ Powerdown command to a SDRAM array when entering system suspend. SCKE is also used to dynamically powerdown inactive SDRAM rows. There is one SCKE per SDRAM row. These signals can be toggled on every rising SCLK edge. O Clock Output: RDCLKO is used to emulate source-synch clocking AGTL+ for reads. This signal connects to RDCLKIN. O Multiplexed Memory Address: These signals are used to provide AGTL+ the multiplexed row and column address to SDRAM. I Clock Input: RDCLKIN is used to emulate source-synch clocking AGTL+ for reads. This signal connects to RDCLKO. 119 8170 N/B MAINTENANCE 5.2 Intel 82845(Brookdale Memory Controller HUB) AGP Flow Control Signals Hub Interface Signals Name HI_[10:0] HI_STB HI_STB# Type I/O CMOS I/O CMOS I/O CMOS Type Description RBF# Name I AGP WBF# I AGP Read Buffer Full: RBF# indicates if the master is ready to accept previously requested low priority read data. When RBF# is asserted, the MCH is not allowed to initiate the return low priority read data. That is, the MCH can finish returning the data for the request currently being serviced. RBF# is only sampled at the beginning of a cycle. If the AGP master is always ready to accept return read data, then it is not required to implement this signal. During FRAME# Operation: Not Used. Write-Buffer Full: Indicates if the master is ready to accept fast write data from the MCH. When WBF# is asserted, the MCH is not allowed drive fast write data to the AGP master. WBF# is only sampled at the beginning of a cycle. If the AGP master is always ready to accept fast write data, then it is not required to implement this signal. During FRAME# Operation: Not Used. Description Hub Interface Signals: Signals used for the hub interface. Hub Interface Strobe: One of two differential strobe signals used to transmit or receive packet data over the hub interface. Hub Interface Strobe Compliment: One of two differential strobe signals used to transmit or receive packet data over the hub interface. AGP Addressing Signals Name PIPE# SBA[7:0] Type I AGP I AGP Description Pipelined Read: This signal is asserted by the AGP master to indicate a full-width address is to be enqueued on by the target using the AD bus. One address is placed in the AGP request queue on each rising clock edge while PIPE# is asserted. When PIPE# is deasserted, no new requests are queued across the AD bus. During SBA Operation: Not Used. During FRAME# Operation: Not Used. PIPE# is a sustained three-state signal from masters (graphics controller), and is an MCH input. Note: Initial AGP designs may not use PIPE# (i.e., PCI only 66 MHz). Therefore, an 8 k. pull-up resistor connected to this pin is required on the motherboard. Sideband Address: These signals are used by the AGP master (graphics controller) to place addresses into the AGP request queue. The SBA bus and AD bus operate independently. That is, a transaction can proceed on the SBA bus and the AD bus simultaneously. During PIPE# Operation: Not Used. During FRAME# Operation: Not Used. Note: When sideband addressing is disabled, these signals are isolated (no external/internal pull-up resistors are required). AGP Status Signals Name ST[2:0] Type O AGP Description Status: ST[2:0] provides information from the arbiter to an AGP Master on what it may do. ST[2:0] only have meaning to the master when its G_GNT# is asserted. When G_GNT# is deasserted, these signals have no meaning and must be ignored. Refer to the AGP Interface Specification, Revision 2.0 for further explanation of the ST[2:0] values and their meanings. During FRAME# Operation: These signals are not used during FRAME#-based operation, except that a ¡¥111¡¦ indicates that the master may begin a FRAME# transaction. NOTE: The above table contains two mechanisms to queue requests by the AGP master. Note that the master can only use one mechanism. The master may not switch methods without a full reset of the system. When PIPE# is used to queue addresses the master is not allowed to queue addresses using the SBA bus. For example, during configuration time, if the master indicates that it can use either mechanism, the configuration software will indicate which mechanism the master will use. Once this choice has been made, the master will continue to use the mechanism selected until the master is reset (and reprogrammed) to use the other mode. This change of modes is not a dynamic mechanism but rather a static decision when the device is first being configured after reset. 120 8170 N/B MAINTENANCE 5.2 Intel 82845(Brookdale Memory Controller HUB) AGP Strobes Signals Name AD_STB0 AD_STB0# AD_STB1 AD_STB1# SB_STB SB_STB# Type Description I/O (s/t/s) AGP I/O (s/t/s) AGP I/O (s/t/s) AGP I/O (s/t/s) AGP I AGP Address/Data Bus Strobe-0: This signal provides timing for 2x and 4x data on AD[15:0] and the C/BE[1:0]# signals. The agent that is providing the data drives this signal. Address/Data Bus Strobe-0 Compliment: Differential strobe pair that provides timing information for the AD[15:0] and C/BE[1:0]# signals. The agent that is providing the data drives this signal. Address/Data Bus Strobe-1: This signal provides timing for 2x- and 4x-clocked data on AD[31:16] and C/BE[3:2]# signals. The agent that is providing the data drives this signal. Address/Data Bus Strobe-1 Compliment: The differential compliment to the AD_STB1 signal. It is used to provide timing for 4x-clocked data. Sideband Strobe: This signal provides timing for 2x- and 4xclocked data on the SBA[7:0] bus. It is driven by the AGP master after the system has been configured for 2x- or 4x- clocked sideband address delivery. Sideband Strobe Compliment: SB_STB# is the differential compliment to the SB_STB signal. It is used to provide timing for 4x-clocked data. I AGP Name G_TRDY# G_STOP# G_DEVSEL# G_REQ# G_GNT# G_AD[31:0] AGP/PCISignals G_C/BE[3:0]# For transactions on the AGP interface carried using AGP FRAME# protocol, these signals operate similar to their semantics in the PCI 2.1 specification the exact role of all AGP FRAME# signals are defined below. Name Type Description G_FRAME# I/O FRAME: During FRAME# Operations, G_FRAME# is an output (s/t/s) when the MCH acts as an initiator on the AGP Interface. AGP G_IRDY# I/O Initiator Ready#: This signal indicates the AGP compliant master is (s/t/s) ready to provide all write data for the current transaction. Once AGP G_IRDY# is asserted for a write operation, the master is not allowed to insert wait states. The master is never allowed to insert a wait state during the initial data transfer (32 bytes) of a write transaction. However, it may insert wait states after each 32-byte block is transferred. Type Description I/O Target Ready: This signal indicates the AGP compliant target is (s/t/s) ready to provide read data for the entire transaction (when the transfer AGP size is less than or equal to 32 bytes) or is ready to transfer the initial or subsequent block (32 bytes) of data when the transfer size is greater than 32 bytes. The target is allowed to insert wait states after each block (32 bytes) is transferred on write transactions. I/O STOP: G_STOP Is an input when the MCH acts as a FRAME#-based (s/t/s) AGP initiator and an output when the MCH acts as a FRAME#-based AGP AGP target. G_STOP# is used for disconnect, retry, and abort sequences on the AGP interface. I/O Device Select: This signal indicates that a FRAME#-based AGP (s/t/s) target device has decoded its address as the target of the current AGP access. The MCH asserts G_DEVSEL# based on the DRAM address range being accessed by a PCI initiator. As an input it indicates whether any device on the bus has been selected. I Request: Indicates that a FRAME# or PIPE#-based AGP master is AGP requesting use of the AGP interface. This signal is an input into the MCH. Grant: During SBA, PIPE# and FRAME# operation, G_GNT#, O AGP along with the information on the ST[2:0] signals (status bus), indicates how the AGP interface will be used next. I/O Address/Data Bus: These signals are used to transfer both address AGP and data on the AGP interface. I/O Command/Byte Enable: AGP During FRAME# Operation: During the address phase of a transaction, G_C/BE[3:0]# define the bus command. During the data phase, G_C/BE[3:0]# are used as byte enables. The byte enables determine which byte lanes carry meaningful data. During PIPE# Operation: When an address is enqueued using PIPE#, the G_C/BE# signals carry command information. The command encoding used during PIPE#-based AGP is DIFFERENT than the command encoding used during FRAME#-based AGP cycles (or standard PCI cycles on a PCI bus). 121 8170 N/B MAINTENANCE 5.2 Intel 82845(Brookdale Memory Controller HUB) AGP/PCISignals Name G_PAR Voltage Reference and Power Signals Type Description I/O AGP Parity: During FRAME# Operations: This signal is driven by the MCH when it acts as a FRAME#-based AGP initiator during address and data phases for a write cycle, and during the address phase for a read cycle. PAR is driven by the MCH when it acts as a FRAME#-based AGP target during each data phase of a FRAME#-based AGP memory read cycle. Even parity is generated across AD[31:0] and G_C/BE[3:0]#. During SBA and PIPE# Operation: This signal is not used during SBA and PIPE# operation. Type Description HVREF Name Ref SDREF Ref HI_REF Ref AGPREF Ref Host Reference Voltage: Reference voltage input for the data, address, and common clock signals of the host AGTL+ interface. SDRAM Reference Voltage: Reference voltage input for DQ, DQS, RDCLKIN (SDR). Hub Interface Reference: Reference voltage input for the hub interface. AGP Reference: Reference voltage input for the AGP interface. HLRCOMP GRCOMP HRCOMP[1:0] Clocks, Reset, and Miscellaneous Signals Name BCLK BCLK# 66IN SCK[11:0] RSTIN# TESTIN# Type Description Differential Host Clock In: These pins receive a differential host I CMOS clock from the external clock synthesizer. This clock is used by all of the MCH logic that is in the host clock domain. I 66 MHz Clock In: This pin receives a 66 MHz clock from the clock CMOS synthesizer. This clock is used by AGP/PCI and hub interface clock domains. Note: That this clock input is 3.3 V tolerant. O System Memory Clocks (SDR): These signals deliver a CMOS synchronized clock to the DIMMs. There are two per row. Reset In: When asserted, this signal asynchronously resets the MCH I CMOS logic. RSTIN# is connected to the PCIRST# output of the ICH2. All AGP/PCI output and bi-directional signals will also three-state compliant to PCI Rev 2.0 and 2.1 specifications. Note: This input needs to be 3.3 V tolerant. Test Input: This pin is used for manufacturing and board level test I CMOS purposes. Note: This signal has an internal pull-up resistor. HSWNG[1:0] SMRCOMP VCC1_5 VCC1_8 VCCSM VCCA[1:0] VTT VSS VSSA[1:0] I/O Compensation for Hub Interface: This signal is used to calibrate CMOS the hub interface I/O buffers. It is connected to a 40.2 . pull-up resistor with 1% tolerance and is pulled up to VCC1_8. I/O Compensation for AGP: This signal is used to calibrate buffers. It is CMOS connected to a 40.2 . pull-down resistor with a 1% tolerance. I/O Compensation for Host: These signals are used to calibrate the host CMOS AGTL+ I/O buffers. Each signal is connected to a 24.9 . pull-down resistor with a 1% tolerance. I Host Reference Voltage: Reference voltage input for the CMOS compensation logic. I/O System Memory RCOMP: CMOS 1.5 V Power Input: These pins are connected to a 1.5 V power source. 1.8 V Power Input Pins: These pins are connected to a 1.8 V power source. SDRAM Power Input Pins: These pins are connected to a 3.3 V power source for SDR. PLL Power Input Pins: These pins provide power for the PLL. AGTL+ Bus Termination Voltage Inputs: These pins provide the AGTL+ bus termination. Ground: The VSS pins are the ground pins for the MCH. PLL Ground: The VSSA[1:0] pins are the ground pins for the PLL on the MCH. 122 8170 N/B MAINTENANCE 5.3 Intel 82801BA(I/O Controller HUB ) Firmware Hub Interface Signals Hub Interface Signals Name Type Description HL[11:0] I/O Hub Interface Signals HL_STB I/O HL_STB# I/O HLCOMP I/O Hub Interface Strobe: One of two differential strobe signals used to transmit and receive data through the hub interface. Hub Interface Strobe Complement: Second of the two differential strobe signals. Hub Interface Compensation: Used for hub interface buffer compensation. Name FWH[3:0] / LAD[3:0] FWH[4] / LFRAME# Type Description I/O Firmware Hub Signals: These signals are muxed with LPC address signals. Firmware Hub Signals: This signal is muxed with LPC LFRAME# signal. I/O PCI Interface Signals Type Description AD[31:0] Name I/O C/BE[3:0]# I/O DEVSEL# I/O PCI Address/Data: AD[31:0] is a multiplexed address and data bus. During the first clock of a transaction, AD[31:0] contain a physical address (32 bits). During subsequent clocks, AD[31:0] contain data. The ICH2 drives all 0s on AD[31:0] during the address phase of all PCI Special Cycles. Bus Command and Byte Enables: The command and byte enable signals are multiplexed on the same PCI pins. During the address phase of a transaction,C/BE[3:0]# define the bus command. During the data phase, C/BE[3:0]# define the Byte Enables. C/BE[3:0]# Command Type 0000 Interrupt Acknowledge 0001 Special Cycle 0010 I/O Read 0011 I/O Write 0110 Memory Read 0111 Memory Write 1010 Configuration Read 1011 Configuration Write 1100 Memory Read Multiple 1110 Memory Read Line 1111 Memory Write and Invalidate All command encodings not shown are reserved. The ICH2 does not decode reserved values, and therefore will not respond if a PCI master generates a cycle using one of the reserved values. Device Select: The ICH2 asserts DEVSEL# to claim a PCI transaction. As an output, the ICH2 asserts DEVSEL# when a PCI master peripheral attempts an access to an internal ICH2 address or an address destined for the hub interface (main memory or AGP). As an input, DEVSEL# indicates the response to an ICH2- initiated transaction on the PCI bus. DEVSEL# is tri-stated from the leading edge of PCIRST#. DEVSEL# remains tri-stated by the ICH2 until driven by a target device. LAN Connect Interface Signals Name Type LAN_CLK I LAN_RXD[2:0] I LAN_TXD[2:0] O LAN_RSTSYNC O Description LAN Interface Clock: This signal is driven by the LAN Connect component. The frequency range is 0.8 MHz to 50 MHz. Received Data: The LAN Connect component uses these signals to transfer data and control information to the integrated LAN Controller. These signals have integrated weak pull-up resistors. Transmit Data: The integrated LAN Controller uses these signals to transfer data and control information to the LAN Connect component. LAN Reset/Sync: The LAN Connect component’s Reset and Sync signals are multiplexed onto this pin. EEPROM Interface Signals Type Description EE_SHCLK Name O EE_DIN I EE_DOUT O EE_CS O EEPROM Shift Clock: EE_SHCLK is the serial shift clock output to the EEPROM. EEPROM Data In: EE_DIN transfers data from the EEPROM to the ICH2. This signal has an integrated pull-up resistor. EEPROM Data Out: EE_DOUT transfers data from the ICH2 to the EEPROM. EEPROM Chip Select: EE_CS is a chip-select signal to the EEPROM. 123 8170 N/B MAINTENANCE 5.3 Intel 82801BA(I/O Controller HUB ) PCI Interface Signals Type Description FRAME# Name I/O IRDY# I/O TRDY# I/O Cycle Frame: The current Initiator drives FRAME# to indicate the beginning and duration of a PCI transaction. While the initiator asserts FRAME#, data transfers continue. When the initiator negates FRAME#, the transaction is in the final data phase. FRAME# is an input to the ICH2 when the ICH2 is the target, and FRAME# is an output from the ICH2 when the ICH2 is the Initiator. FRAME# remains tri-stated by the ICH2 until driven by an Initiator. Initiator Ready: IRDY# indicates the ICH2's ability, as an Initiator, to complete the current data phase of the transaction. It is used in conjunction with TRDY#. A data phase is completed on any clock both IRDY# and TRDY# are sampled asserted. During a write, IRDY# indicates the ICH2 has valid data present on AD[31:0]. During a read, it indicates the ICH2 is prepared to latch data. IRDY# is an input to the ICH2 when the ICH2 is the Target and an output from the ICH2 when the ICH2 is an Initiator. IRDY# remains tri-stated by the ICH2 until driven by an Initiator. Target Ready: TRDY# indicates the ICH2's ability as a Target to complete the current data phase of the transaction. TRDY# is used in conjunction with IRDY#. A data phase is completed when both TRDY# and IRDY# are sampled asserted. During a read, TRDY# indicates that the ICH2, as a Target, has placed valid data on AD[31:0]. During a write, TRDY# indicates the ICH2, as a Target is prepared to latch data. TRDY# is an input to the ICH2 when the ICH2 is the Initiator and an output from the ICH2 when the ICH2 is a Target. TRDY# is tri-stated from the leading edge of PCIRST#. TRDY# remains tri-stated by the ICH2 until driven by a target. Stop: STOP# indicates that the ICH2, as a Target, is requesting the Initiator to stop the current transaction. STOP# causes the ICH2, as an Initiatior, to stop the current transaction. STOP# is an output when the ICH2 is a target and an input when the ICH2 is an Initiator. STOP# is tri-stated from the leading edge of PCIRST#. STOP# remains tri-stated until driven by the ICH2. PCI Requests: The ICH2 supports up to 6 masters on the PCI bus. REQ[5]# is muxed with PC/PCI REQ[B]# (must choose one or the other, but not both). If not used for PCI or PC/PCI, REQ[5]#/REQ[B]# can instead be used as GPIO[1]. Note: REQ[0]# is programmable to have improved arbitration latency for supporting PCI-based 1394 controllers. STOP# REQ[0:4]# REQ[5]# / REQ[B]# / GPIO[1] I/O I Name PAR Type I/O PERR# I/O GNT[0:4]# GNT[5]# / GNT[B]# / GPIO[17]# O PCICLK I PCIRST# O SERR# I Description Calculated/Checked Parity: PAR uses "even" parity calculated on 36 bits, AD[31:0] plus C/BE[3:0]#. "Even" parity means that the ICH2 counts the number of 1s within the 36 bits plus PAR and the sum is always even. The ICH2 always calculates PAR on 36 bits, regardless of the valid byte enables. The ICH2 generates PAR for address and data phases and only guarantees PAR to be valid one PCI clock after the corresponding address or data phase. The ICH2 drives and tri-states PAR identically to the AD[31:0] lines except that the ICH2 delays PAR by exactly one PCI clock. PAR is an output during the address phase (delayed one clock) for all ICH2 initiated transactions. PAR is an output during the data phase (delayed one clock) when the ICH2 is the Initiator of a PCI write transaction, and when it is the target of a read transaction. ICH2 checks parity when it is the target of a PCI write transaction. If a parity error is detected, the ICH2 sets the appropriate internal status bits, and has the option to generate an NMI# or SMI#. Parity Error: An external PCI device drives PERR# when it receives data that has a parity error. The ICH2 drives PERR# when it detects a parity error. The ICH can either generate an NMI# or SMI# upon detecting a parity error (either detected internally or reported via the PERR# signal). PCI Grants: The ICH2 supports up to 6 masters on the PCI bus. GNT[5]# is muxed with PC/PCI GNT[B]# (must choose one or the other, but not both). If not needed PCI or PC/PCI, GNT[5]# can instead be used as a GPIO. Pull-up resistors are not required on these signals. If pullups are used, they should be tied to the Vcc3_3 power rail. GNT[B]#/GNT[5]#/GPIO[17] has an internal pullup. PCI Clock: This is a 33 MHz clock. PCICLK provides timing for all transactions on the PCI Bus. . Note:For 82801BAM ICH2-M, this clock does not stop based on the STP_PCI# signal. The PCI Clock only stops based on SLP_S1# or SLP_S3#. PCI Reset: ICH2 asserts PCIRST# to reset devices that reside on the PCI bus. The ICH2 asserts PCIRST# during power-up and when S/W initiates a hard reset sequence through the RC (CF9h) register. The ICH2 drives PCIRST# inactive a minimum of 1 ms after PWROK is driven active. The ICH2 drives PCIRST# active a minimum of 1 ms when initiated through the RC register. System Error: SERR# can be pulsed active by any PCI device that detects a system error condition. Upon sampling SERR# active, the ICH2 has the ability to generate an NMI, SMI#, or interrupt. 124 8170 N/B MAINTENANCE 5.3 Intel 82801BA(I/O Controller HUB ) IDE Interface Signals(continued) PCI Interface Signals Name PME# CLKRUN# (ICH2-M only) REQ[A]# / GPIO[0] REQ[B]# / REQ[5]# / GPIO[1] GNT[A]# / GPIO[16] GNT[B]# / GNT[5]# / GPIO[17] Type Description I PCI Power Management Event: PCI peripherals drive PME# to wake the system from low-power states S1–S5. PME# assertion can also be enabled to generate SCI from the S0 state. In some cases the ICH2 may drive PME# active due to an internal wake event. The ICH2 will not drive PME# high, but it will be pulled up to VccSus3_3 by an internal pull-up resistor. PCI Clock Run: For the ICH2-M, CLKRUN# is used to support PCI Clock Run protocol. This signal connects to PCI devices that need to request clock re-start or prevention of clock stopping. PC/PCI DMA Request [A:B]: This request serializes ISA-like DMA Requests for the purpose of running ISA-compatible DMA cycles over the PCI bus. This is used by devices such as PCI-based Super I/O or audio codecs that need to perform legacy 8237 DMA but have no ISA bus. When not used for PC/PCI requests, these signals can be used as General Purpose Inputs. Instead, REQ[B]# can be used as the 6th PCI bus request. PC/PCI DMA Acknowledges [A:B]: This grant serializes an ISA-like DACK# for the purpose of running DMA/ISA master cycles over the PCI bus. This is used by devices such as PCI-based Super/IO or audio codecs which need to perform legacy 8237 DMA but have no ISA bus. When not used for PC/PCI, these signals can be used as General Purpose Outputs. GNTB# can also be used as the 6th PCI bus master grant output. These signal have internal pull-up resistors. I/O I O IDE Interface Signals Type Description PDCS1#, SDCS1# Name O Primary and Secondary IDE Device Chip Selects for 100 Range: These signals are for the ATA command register block. This output signal is connected to the corresponding signal on the primary or secondary IDE connector. PDCS3#, SDCS3# O Primary and Secondary IDE Device Chip Select for 300 Range: These signals are for the ATA control register block. This output signal is connected to the corresponding signal on the primary or secondary IDE connector. Type Description PDA[2:0], SDA[2:0] Name O PDD[15:0], SDD[15:0] I/O PDDREQ, SDDREQ I PDDACK#, SDDACK# O PDIOR# SDIOR# O Primary and Secondary IDE Device Address: These output signals are connected to the corresponding signals on the primary or secondary IDE connectors. They are used to indicate which byte in either the ATA command block or control block is being addressed. Primary and Secondary IDE Device Data: These signals directly drive the corresponding signals on the primary or secondary IDE connector. There is a weak internal pull-down resistor on PDD[7] and SDD[7]. Primary and Secondary IDE Device DMA Request: These input signals are directly driven from the DRQ signals on the primary or secondary IDE connector. It is asserted by the IDE device to request a data transfer, and used in conjunction with the PCI bus master IDE function. They are not associated with any AT-compatible DMA channel. There is a weak internal pull-down resistor on these signals. Primary and Secondary IDE Device DMA Acknowledge: These signals directly drive the DAK# signals on the primary and secondary IDE connectors. Each signal is asserted by the ICH2 to indicate to the IDE DMA slave devices that a given data transfer cycle (assertion of DIOR# or DIOW#) is a DMA data transfer cycle. This signal is used in conjunction with the PCI bus master IDE function and are not associated with any AT-compatible DMA channel. Primary and Secondary Disk I/O Read (PIO and Non-Ultra DMA): This is the command to the IDE device that it may drive data on the PDD or SDD lines. Data is latched by the ICH2 on the deassertion edge of PDIOR# or SDIOR#. The IDE device is selected either by the ATA register file chip selects (PDCS1# or SDCS1#, PDCS3# or SDCS3#) and the PDA or SDA lines, or the IDE DMA acknowledge (PDDAK# or SDDAK#). Primary and Secondary Disk Write Strobe (Ultra DMA Writes to Disk): This is the data write strobe for writes to disk. When writing to disk, ICH2 drives valid data on rising and falling edges of PDWSTB or SDWSTB. Primary and Secondary Disk DMA Ready (Ultra DMA Reads from Disk): This is the DMA ready for reads from disk. When reading from disk, ICH2 deasserts PRDMARDY# orSRDMARDY# to pause burst data transfers. 125 8170 N/B MAINTENANCE 5.3 Intel 82801BA(I/O Controller HUB ) Interrupt Signals IDE Interface Signals(continued) Name PDIOW# SDIOW# PIORDY SIORDY Type O I Description Primary and Secondary Disk I/O Write (PIO and Non-Ultra DMA): This is the command to the IDE device that it may latch data from the PDD or SDD lines. Data is latched by the IDE device on the deassertion edge of PDIOW# or SDIOW#. The IDE device is selected either by the ATA register file chip selects (PDCS1# or SDCS1#, PDCS3# or SDCS3#) and the PDA or SDA lines, or the IDE DMA acknowledge (PDDAK# or SDDAK#). Primary and Secondary Disk Stop (Ultra DMA): ICH2 asserts this signal to terminate a burst. Primary and Secondary I/O Channel Ready (PIO): This signal keeps the strobe active (PDIOR# or SDIOR# on reads, PDIOW# or SDIOW# on writes) longer than the minimum width. It adds wait states to PIO transfers. Primary and Secondary Disk Read Strobe (Ultra DMA Reads from Disk): When reading from disk, ICH2 latches data on rising and falling edges of this signal from the disk. Primary and Secondary Disk DMA Ready (Ultra DMA Writes to Disk): When writing to disk, this is deasserted by the disk to pause burst data transfers USB Interface Signals Name USBP0P, USBP0N, USBP1P, USBP1N USBP2P, USBP2N, USBP3P, USBP3N OC[3:0]# Type Description I/O Universal Serial Bus Port 1:0 Differential: These differential pairs are used to transmit Data/Address/Command signals for ports 0 and 1 (USB Controller 1). I/O Universal Serial Bus Port 3:2 Differential: These differential pairs are used to transmit Data/Address/Command signals for ports 2 and 3 USB Controller 2). I Overcurrent Indicators: These signals set corresponding bits in the USB controllers to indicate that an overcurrent condition has occurred. Name SERIRQ Type Description I/O Serial Interrupt Request: This pin implements the serial interrupt protocol. PCI Interrupt Requests: In Non-APIC Mode the PIRQx# signals can be routed to interrupts 3:7, 9:12, 14, or 15 as described in the Interrupt Steering section. Each PIRQx# line has a separate Route Control Register. In APIC mode, these signals are connected to the internal I/O APIC in the following fashion: PIRQ[A]# is connected to IRQ16, PIRQ[B]# to IRQ17, PIRQ[C]# to IRQ18, and PIRQ[D]# to IRQ19. This frees the ISA interrupts. PCI Interrupt Requests: In Non-APIC Mode the PIRQx# signals can be routed to interrupts 3:7, 9:12, 14 or 15 as described in the Interrupt Steering section. Each PIRQx# line has a separate Route Control Register. In APIC mode, these signals are connected to the internal I/O APIC in the following fashion: PIRQ[E]# is connected to IRQ20, PIRQ[F]# to IRQ21, PIRQ[G]# to IRQ22, and PIRQ[H]# to IRQ23. This frees the ISA interrupts. If not needed for interrupts, PIRQ[G:F] can be used as GPIO. Interrupt Request 14:15: These interrupt inputs are connected to the IDE drives. IRQ14 is used by the drives connected to the primary controller and IRQ15 is used by the drives connected to the secondary controller. APIC Clock: The APIC clock runs at 33.333 MHz. PIRQ[D:A]# I/OD PIRQ[H]#, PIRQ[G:F]# GPIO[4:3], PIRQ[E]# I/OD IRQ[14:15] I APICCLK APICD[1:0] I I/OD APIC Data: These bi-directional open drain signals are used to send and receive data over the APIC bus. As inputs, the data is valid on the rising edge of APICCLK.As outputs, new data is driven from the rising edge of the APICCLK. LPC Interface Signals Name LAD[3:0] / FWH[3:0] LFRAME# / FWH[4] LDRQ[1:0]# Type Description I/O LPC Multiplexed Command, Address, Data: Internal pull-ups are provided. LPC Frame: LFRAME# indicates the start of an LPC cycle, or an abort. LPC Serial DMA/Master Request Inputs: These signals are used to request DMA or bus master access. Typically, they are connected to external Super I/O device. An internal pull-up resistor is provided on these signals. O O 126 8170 N/B MAINTENANCE 5.3 Intel 82801BA(I/O Controller HUB ) Power Management Interface Signals Type Description THRM# Name I SLP_S1# (ICH2-M only) O Thermal Alarm: THRM# is an active low signal generated by external hardware to start the hardware clock throttling mode. This signal can also generate an SMI# or an SCI. S1 Sleep Control: Clock synthesizer or power plane control. This signal connects to clock synthesizer’s PWRDWN# signal. An optional use is to shut off power to non-critical systems when in the S1 (Powered On Suspend), S3 (Suspend To RAM), S4 (Suspend to Disk), or S5 (Soft Off) states. S3 Sleep Control: Power plane control. This signal is used to shut off power to all non-critical systems when in S3 (Suspend To RAM), S4 (Suspend to Disk) or S5 (Soft Off) states. S5 Sleep Control: Power plane control. This signal is used to shut power off to all non-critical systems when in the S4 (Suspend To Disk) or S5 (Soft Off) states. Power OK: When asserted, PWROK is an indication to the ICH2 that core power and PCICLK have been stable for at least 1 ms. PWROK can be driven asynchronously. When PWROK is negated, the ICH2 asserts PCIRST#. Resume Well Power OK: When asserted, this signal is an indication to the ICH2 that the resume well power (VccSus3_3, VccSus1_8) has been stable for at least10 ms. LAN Power OK: When asserted, this signal is an indication to the ICH2-M that the LAN Controller power (VccLAN3_3, VccLAN1_8) has been stable for at least 10 ms. Power Button: The Power Button will cause SMI# or SCI to indicate a system request to go to a sleep state. If the system is already in a sleep state, this signal will cause a wake event. If PWRBTN# is pressed for more than 4 seconds, this will cause an unconditional transition (power button override) to the S5 state with only the PWRBTN# available as a wake event. Override will occur even if the system is in the S1-S4 states. This signal has an internal pull-up resistor. Ring Indicate: From the modem interface. This signal can be enabled as a wake event; this is preserved across power failures. Resume Well Reset: RSMRST# is used for resetting the resume power plane logic. Suspend Status: This signal is asserted by the ICH2 to indicate that the system will be entering a low power state soon. This can be monitored by devices with memory that need to switch from normal refresh to suspend refresh mode. It can also be used by other peripherals as an indication that they should isolate their outputs that may be going to powered-off planes. This signal is called LPCPD# on the LPC interface. SLP_S3# O SLP_S5# O PWROK I RSM_PWROK (ICH2 0nly) I LAN_PWROK (ICH2-M only) I PWRBTN# I RI# I RSMRST# I SUS_STAT# / LPCPD# O Type Description C3_STAT# / GPIO[21] ICH2-M only) Name O SUSCLK O VRMPWRGD (ICH2) VRMPWRGD/ VGATE (ICH2-M) VGATE / VRMPWRGD (ICH2-M only) I C3_STAT#: This ICH2-M signal is typically configured as C3_STAT#. It is used for indicating to an AGP device that a C3 state transition is beginning or ending. If C3_STAT# functionality is not required, this signal can be used as a GPO. Suspend Clock: This signal is an output of the RTC generator circuit and is used by other chips for the refresh clock. VRM Power Good (ICH2 and ICH2-M): VRMPWRGD should be connected to be the processor’s VRM Power Good. AGPBUSY# (ICH2-M only) I STP_PCI# (ICH2-M only) O STP_CPU# (ICH2-M only) O BATLOW# (ICH2-M only) I CPUPERF# (ICH2-M only) OD SSMUXSEL (ICH2-M only) O I VRM Power Good Gate (ICH2-M): VGATE is used for Intel® SpeedStepTM technology support. It is an output from the processor’s voltage regulator to indicate that the voltage is stable. This signal can go inactive during a Intel® SpeedStepTM transition. In non-Intel® SpeedStepTM technology systems this signal should be connected to the processor VRM Power Good. AGP Bus Busy: This signal supports the C3 state. It provides an indication that the AGP device is busy. When this signal is asserted, the BM_STS bit will be set. If this functionality is not needed, this signal may be configured as a GPI. Stop PCI Clock: This signal is an output to the external clock generator to turn off the PCI clock. It is used to support PCI CLKRUN# protocol. If this functionality is not needed, this signal can be configured as a GPO. Stop CPU Clock: Output to the external clock generator to turn off the processor clock. It is used to support the C3 state. If this functionality is not needed, this signal can be configured as a GPO. Battery Low: Input from battery to indicate that there is insufficient power to boot the system. Assertion prevents wake from S1–S5 state. This signal can also be enabled to cause an SMI# when asserted. In desktop configurations this signal should be pulled high to VccSUS. CPU Performance: This signal is used for Intel® SpeedStepTM technology support. It selects which power state to put the processo in. If this functionality is not needed, this signal can be configured as a GPO. This is an open-drain output signal and requires an external pull-up to the processor I/O voltage. SpeedStep Mux Select: This signal is used for Intel SpeedStepTM technology support. It selects the voltage level for the processor. If this functionality is not needed, this signal can be configured as a GPO. 127 8170 N/B MAINTENANCE 5.3 Intel 82801BA(I/O Controller HUB ) Processor Interface Signals Type Description A20M# Name O CPUSLP# O FERR# I IGNNE# O Mask A20: A20M# goes active based on setting the appropriate bit in the Port 92h register, or based on the A20GATE signal. Speed Strap: During the reset sequence, ICH2 drives A20M# high if the corresponding bit is set in the FREQ_STRP register. Processor Sleep: This signal puts the processor into a state that saves substantial power compared to Stop-Grant state. However, during that time, no snoops occur. The ICH2 can optionally assert the CPUSLP# signal when going to the S1 state. Numeric Coprocessor Error: This signal is tied to the coprocessor error signal on the processor. FERR# is only used if the ICH2 coprocessor error reporting function is enabled in the General Control Register (Device 31:Function 0, Offset D0, bit 13). If FERR# is asserted, the ICH2 generates an internal IRQ13 to its interrupt controller unit. It is also used to gate the IGNNE# signal to ensure that IGNNE# is not asserted to the processor unless FERR# is active. FERR# requires an external weak pull-up to ensure a high level when the coprocessor error function is disabled. Ignore Numeric Error: This signal is connected to the ignore error pin on the processor. IGNNE# is only used if the ICH2 coprocessor error reporting function is enabled in the General Control Register (Device 31:Function 0, Offset D0, bit 13). If FERR# is active, indicating a coprocessor error, a write to the Coprocessor Error Register (F0h) causes the IGNNE# to be asserted. IGNNE# remains asserted until FERR# is negated. If FERR# is not asserted when the Coprocessor Error Register is written, the IGNNE# signal is not asserted. Speed Strap: During the reset sequence, ICH2 drives IGNNE# high if the corresponding bit is set in the FREQ_STRP register. Initialization: INIT# is asserted by the ICH2 for 16 PCI clocks to reset the processor. ICH2 can be configured to support processor BIST. In that case, INIT# will be active when PCIRST# is active. Processor Interrupt: INTR is asserted by the ICH2 to signal the processor that an interrupt request is pending and needs to be serviced. It is an asynchronous output and normally driven low. Speed Strap: During the reset sequence, ICH2 drives INTR high if the corresponding bit is set in the FREQ_STRP register. Non-Maskable Interrupt: NMI is used to force a non-maskable interrupt to the processor. The ICH2 can generate an NMI when either SERR# or IOCHK# is asserted. The processor detects an NMI when it detects a rising edge on NMI. NMI is reset by setting the corresponding NMI source enable/disable bit in the NMI Status and Control Register. Speed Strap: During the reset sequence, ICH2 drives NMI high if the corresponding bit is set in the FREQ_STRP register. INIT# O INTR O NMI O Name Type Description SMI# O STPCLK# O RCIN# I A20GATE I System Management Interrupt: SMI# is an active low output synchronous to PCICLK. It is asserted by the ICH2 in response to one of many enabled hardware or software events. Stop Clock Request: STPCLK# is an active low output synchronous to PCICLK. It is asserted by the ICH2 in response to one of many hardware or software events. When the processor samples STPCLK# asserted, it responds by stopping its internal clock. Keyboard Controller Reset Processor: The keyboard controller can generate INIT# to the processor. This saves the external OR gate with the ICH2’s other sources of INIT#. When the ICH2 detects the assertion of this signal, INIT# isgenerated for 16 PCI clocks.. Note: 82801BA ICH2: The 82801BA ignores RCIN# assertion during transitions to the S3, S4 and S5 states. 82801BAM ICH2-M: The 82801BAM ignores RCIN# assertion during transitions to the S1, S3, S4 and S5 states. A20 Gate: This signal is from the keyboard controller. It acts as an alternative method to force the A20M# signal active. A20GATE saves the external OR gate needed with various other PCIsets. CPU Power Good (82801BAM ICH2-M): This signal should be connected to the processor’s PWRGOOD input. For Intel® SpeedStep™ technology support, this signal is kept high during a Intel® SpeedStep™ technology state transition to prevent loss of processor context. This is an open-drain output signal (external pull-up resistor required) that represents a logical AND of the ICH2-M’s PWROK and VGATE / VRMPWRGD signals. CPUPWRGD OD SM Bus Interface Signals Name Type Description SMBDATA I/OD SMBus Data: External pull-up is required. SMBCLK I/OD SMBus Clock: External pull-up is required. SMBALERT#/ GPIO[11] I SMBus Alert: This signal is used to wake the system or generate an SMI#. If not used for SMBALERT#, it can be used as a GPI. 128 8170 N/B MAINTENANCE 5.3 Intel 82801BA(I/O Controller HUB ) Miscellaneous Signals System Management Interface Signals Name Type Description INTRUDER# I SMLINK[1:0] I/OD Intruder Detect: This signal can be set to disable system if box detected open. This signal’s status is readable, so it can be used like a GPI if the Intruder Detection is not needed. System Management Link: These signals are an SMBus link to an optional external system management ASIC or LAN controller. External pull-ups are required. Note: that SMLINK[0] corresponds to an SMBus Clock signal and SMLINK[1] corresponds to an SMBus Data signal. Real Time Clock Interface Name RTCX1 RTCX2 Type Description Special Crystal Input 1: This signal is connected to the 32.768 KHz crystal. If no external crystal is used, then RTCX1 can be driven with the desired clock rate. Special Crystal Input 2: This signal is connected to the 32.768 KHz crystal. If no external crystal is used, then RTCX2 should be left floating. Type Description SPKR Name O RTCRST# I TP0 (ICH2 0nly) FS0 I Speaker: The SPKR signal is the output of counter 2 and is internally "ANDed" with Port 61h bit 1 to provide Speaker Data Enable. This signal drives an external speaker driver device, which in turn drives the system speaker. Upon PCIRST#, its output state is 1. Note: SPKR is sampled at the rising edge of PWROK as a functional strap. RTC Reset: When asserted, this signal resets register bits in the RTC well and sets the RTC_PWR_STS bit (bit 2 in GEN_PMCON3 register). Note: Clearing CMOS in an ICH2-based platform can be done by using a jumper on RTCRST# or GPI, or using SAFEMODE strap. Implementations should not attempt to clear CMOS by using a jumper to pull VccRTC low. Test Point (82801BA ICH2): This signal must have an external pull-up to VccSus3_3. Functional Strap: This signal is reserved for future use. There is an internal pullup resistor on this signal. I AC’97 Link Signals Name Other Clocks Name CLK14 Type Description I Oscillator Clock: CLK14 is used for 8254 timers and runs at 14.31818 MHz. 82801BA ICH2: This clock is permitted to stop during S3 (or lower) states. 82801BAM ICH2-M: This clock is permitted to stop during S1 (or lower) states. 48 MHz Clock: CLK48 is used to for the USB controller and runs at 48 MHz. 82801BA ICH2: This clock is permitted to stop during S3 (or lower) states. 82801BAM ICH2-M: This clock is permitted to stop during S1 (or lower) states. 66 MHz Clock: CLK66 is used to for the hub interface and runs at 66 MHz. 82801BA ICH2: This clock is permitted to stop during S3 (or lower) states. 82801BAM ICH2-M: This clock is permitted to stop during S1 (or lower) states. CLK48 I CLK66 I Type Description AC_RST# O AC97 Reset: Master H/W reset to external Codec(s) AC_SYNC O AC97 Sync: 48 KHz fixed rate sample sync to the Codec(s) AC_BIT_CLK I AC_SDOUT O AC_SDIN[1:0] I AC97 Bit Clock: 12.288 MHz serial data clock generated by the external Codec(s). See Note. AC97 Serial Data Out: Serial TDM data output to the Codec(s) Note: AC_SDOUT is sampled at the rising edge of PWROK as a functional strap.. AC97 Serial Data In 0: Serial TDM data inputs from the Codecs. See Note. 129 8170 N/B MAINTENANCE 5.4 PCI4410(PCMCIA/1394 LINK Controller ) Power-Supply Terminals Name Type PCI Address and Data Terminals GND Device ground terminals VCC Power-supply terminal for core logic (3.3 V) VCCB Clamp voltage for PC Card interface. Matches card signaling environment, 5 V or 3.3 V. Clamp voltage for miscellaneous I/O signals (MFUNC, GRST#, and SUSPEND#) Clamp voltage for 1394 link function VCCI VCCL Type Description AD[0:31[ Name I/O C/BE[0:3]# I/O PAR I/O PCI address/data bus. These signals make up the multiplexed PCI address and data bus on the primary interface. During the address phase of a primary bus PCI cycle, AD31–AD0 contain a 32-bit address or other destination information. During the data phase, AD31–AD0 contain data. PCI bus commands and byte enables. These signals are multiplexed on the same PCI terminals. During the address phase of a primary bus PCI cycle, C/BE3#–C/BE0# define the bus command. During the data phase, this 4-bit bus is used as byte enables. The byte enables determine which byte paths of the full 32-bit data bus carry meaningful data. C/BE0# applies to byte 0 (AD7–AD0), C/BE1# applies to byte 1 (AD15–AD8), C/BE2# applies to byte 2 (AD23–AD16), and C/BE3# applies to byte 3 (AD31–AD24). PCI bus parity. In all PCI bus read and write cycles, the PCI4410A device calculates even parity across the AD31–AD0 and C/BE3#–C/BE0# buses. As an initiator during PCI cycles, the PCI4410A device outputs this parity indicator with a one-PCLK delay. As a target during PCI cycles, the calculated parity is compared to the initiator’s parity indicator. A compare error results in the assertion of a parity error (PERR#). Description Clamp voltage for PCI interface, ZV interface, SPKROUT, INTA#, INTB# LED_SKT,VCCD0#, VCCD1#, VPPD0, VPPD1 VCCP PC Card Power-Switch Terminals Name VCCD0# VCCD1# VPPD0 VPPD1 Type O O Description Logic controls to the TPS2211 PC Card power-switch interface to control AVCC Logic controls to the TPS2211 PC Card power-switch interface to control AVPP PCI System Terminals Name GRST# Type Description I Global reset. When global reset is asserted, GRST# causes the PCI4410A device to place all output buffers in a high-impedance state and reset all internal registers. When GRST# is asserted, the device is completely in its default state. For systems that require wake-up from D3, GRST# normally is asserted only during initial boot. PRST# should be asserted following initial boot so that PME context is retained when transitioning from D3 to D0. For systems that do not require wake-up from D3, GRST# should be tied to PRST. When the SUSPEND mode is enabled, the device is protected from GRST#, and the internal registers are preserved. All outputs are placed in a high-impedance state, but the contents of the registers are preserved. PCI bus clock. PCLK provides timing for all transactions on the PCI bus. All PCI signals are sampled at the rising edge of PCLK. PCI bus reset. When the PCI bus reset is asserted, PRST# causes the PCI4410A device to place all output buffers in a high-impedance state and reset internal registers. When PRST is asserted, the device is completely nonfunctional. After PRST# is deserted, the PCI4410A device is in a default state. When SUSPEND# and PRST# are asserted, the device is protected from PRST# clearing the internal registers.All outputs are placed in a high-impedance state, but the contents of the registers are preserved. PCLK I PRST# I PCI Interface Control Terminals Type Description DECSEL# Name I/O FRAME# I/O PCI device select. The PCI4410A device asserts DEVSEL# to claim a PCI cycle as the target device. As a PCI initiator on the bus, the PCI4410A device monitors DEVSEL# until a target responds. If no target responds before timeout occurs, the PCI4410A device terminates the cycle with an initiator abort. PCI cycle frame. FRAME# is driven by the initiator of a bus cycle. FRAME# is asserted to indicate that a bus transaction is beginning, and data transfers continue while this signal is asserted. When FRAME# is deasserted, the PCI bus transaction is in the final data phase. PCI bus grant. GNT# is driven by the PCI bus arbiter to grant the PCI4410A device access to the PCI bus after the current data transaction has completed. GNT# may or may not follow a PCI bus request, depending on the PCI bus parking algorithm. Initialization device select. IDSEL# selects the PCI4410A device during configuration space accesses. IDSEL# can be connected to one of the upper 24 PCI address lines on the PCI bus. GNT# I IDSEL# I 130 8170 N/B MAINTENANCE 5.4 PCI4410(PCMCIA/1394 LINK Controller ) PCI Interface Control Terminals Type Description IRDY# Name I/O PERR# I/O REQ# O SERR# O PCI initiator ready. IRDY# indicates the PCI bus initiator’s ability to complete the current data phase of the transaction. A data phase is completed on a rising edge of PCLK, when both IRDY# and TRDY# are asserted. Until IRDY# and TRDY# are both sampled asserted, wait states are inserted. PCI parity error indicator. PERR# is driven by a PCI device to indicate that calculated parity does not match PAR when PERR# is enabled through bit 6 (PERR_EN) of the command register (PCI offset 04h, see Section 4.4). PCI bus request. REQ# is asserted by the PCI4410A device to request access to the PCI bus as an initiator. PCI system error. SERR# is an output that is pulsed from the PCI4410A device when enabled through bit 8 (SERR_EN) of the command register (PCI offset 04h, see Section 4.4) indicating a system error has occurred. The PCI4410A device need not be the target of the PCI cycle to assert this signal. When SERR# is enabled in the command register, this signal also pulses, indicating that an address parity error has occurred on a CardBus interface. PCI cycle stop signal. STOP# is driven by a PCI target to request the initiator to stop the current PCI bus transaction. STOP# is used for target disconnects and is commonly asserted by target devices that do not support burst data transfers. PCI target ready. TRDY# indicates the primary bus target’s ability to complete the current data phase of the transaction. A data phase is completed on a rising edge of PCLK, when both IRDY# and TRDY# are asserted. Until both IRDY# and TRDY# are asserted, wait states are inserted. STOP# I/O TRDY# I/O Type Description MFUNC1 Name I/O MFUNC2 I/O MFUNC3 I/O MFUNC4 I/O MFUNC5 I/O MFUNC6 I/O RI_OUT#/PME# O SPKROUT O SUSPEND# I Multifunction terminal 1. MFUNC1 can be configured as GPI1, GPO1, socket activity LED output, ZV switching outputs, CardBus audio PWM, GPE#, or a parallel IRQ. See Section 4.32, Multifunction Routing Register, for configuration details. Serial data (SDA). When VCCD0# and VCCD1# are high after a PCI reset, the MFUNC1 terminal provides the SDA signaling for the serial bus interface. The two-terminal serial interface loads the subsystem identification and other register defaults from an EEPROM after a PCI reset. See Section 3.6.1, Serial Bus Interface Implementation, for details on other serial bus applications. Multifunction terminal 2. MFUNC2 can be configured as PC/PCI DMA request, GPI2, GPO2, ZV switching outputs, CardBus audio PWM, GPE#, RI_OUT#, or a parallel IRQ. See Section 4.32, Multifunction Routing Register, for configuration details. Multifunction terminal 3. MFUNC3 can be configured as a parallel IRQ or the serialized interrupt signal IRQSER. See Section 4.32, Multifunction Routing Register, for configuration details. Multifunction terminal 4. MFUNC4 can be configured as PCI LOCK#, GPI3, GPO3, socket activity LED output, ZV switching outputs, CardBus audio PWM, GPE#, RI_OUT#, or a parallel IRQ. See Section 4.32, Multifunction Routing Register, for configuration details. Serial clock (SCL). When VCCD0# and VCCD1# are high after a PCI reset, the MFUNC4 terminal provides the SCL signaling for the serial bus interface. The two-terminal serial interface loads the subsystem identification and other register defaults from an EEPROM after a PCI reset. See Section 3.6.1, Serial Bus Interface Implementation, for details on other serial bus applications. Multifunction terminal 5. MFUNC5 can be configured as PC/PCI DMA grant, GPI4, GPO4, socket activity LED output, ZV switching outputs, CardBus audio PWM, GPE#, or a parallel IRQ. See Section 4.32, Multifunction Routing Register, for configuration details. Multifunction terminal 6. MFUNC6 can be configured as a PCI CLKRUN# or a parallel IRQ. See Section 4.32, Multifunction Routing Register, for configuration details. Ring indicate out and power-management event output. Terminal provides an output for ring-indicate or PME# signals. Speaker output. SPKROUT is the output to the host system that can carry SPKR# or CAUDIO through the PCI4410A device from the PC Card interface. SPKROUT is driven as the exclusive-OR combination of card SPKR#//CAUDIO inputs. Suspend. SUSPEND# protects the internal registers from clearing when the GRST or PRST signal is asserted. See Section 3.8.4, Suspend Mode, for details. Multifunction and Miscellaneous Terminals Name Type Description INTA# O Parallel PCI interrupt. INTA# INTB# O Parallel PCI interrupt. INTB# LED_SKT O MFUNC0 I/O PC Card socket activity LED indicator. LED_SKT provides an output indicating PC Card socket activity. Multifunction terminal 0. MFUNC0 can be configured as parallel PCI interrupt INTA#, GPI0, GPO0, socket activity LED output, ZV switching outputs, CardBus audio PWM, GPE#, or a parallel IRQ. See Section 4.32, Multifunction Routing Register, for configuration details. 131 8170 N/B MAINTENANCE 5.4 PCI4410(PCMCIA/1394 LINK Controller ) 16-Bit PC Card Address and Data Terminals Type Description ADDR[0:25] Name O DATA[0:15] I/O PC Card address. 16-bit PC Card address lines. ADDR25 is the most significant bit PC Card data. 16-bit PC Card data lines. DATA15 is the most significant bit. Type Description CE1# CE2# Name O INPACK# I IORD# O IOWR# O OE# O READ IREQ# I Card enable 1 and card enable 2. CE1# and CE2# enable even- and odd-numbered address bytes. CE1#enables even-numbered address bytes, and CE2# enables odd-numbered address bytes. Input acknowledge. INPACK# is asserted by the PC Card when it can respond to an I/O read cycle at the current address.DMA request. INPACK# can be used as the DMA request signal during DMA operations from a 16-bit PC Card that supports DMA. If it is used as a strobe, the PC Card asserts this signal to indicate a request for a DMA operation. I/O read. IORD# is asserted by the PCI4410A device to enable 16-bit I/O PC Card data output during host I/O read cycles. DMA write. IORD# is used as the DMA write strobe during DMA operations from a 16-bit PC Card that supports DMA. The PCI4410A device asserts IORD# during DMA transfers from the PC Card to host memory. I/O write. IOWR# is driven low by the PCI4410A device to strobe write data into 16-bit I/O PC Cards during host I/O write cycles. DMA read. IOWR# is used as the DMA write strobe during DMA operations from a 16-bit PC Card that supports DMA. The PCI4410A device asserts IOWR during transfers from host memory to the PC Card. Output enable. OE# is driven low by the PCI4410A device to enable 16-bit memory PC Card data output during host memory read cycles. DMA terminal count. OE# is used as terminal count (TC) during DMA operations to a 16-bit PC Card that supports DMA. The PCI4410A device asserts OE# to indicate TC for a DMA write operation. Ready. The ready function is provided by READY when the 16-bit PC Card and the host socket are configured for the memory-only interface. READY is driven low by the 16-bit memory PC Cards to indicatethat the memory card circuits are busy processing a previous write command. READY is driven high when the 16-bit memory PC Card is ready to accept a new data-transfer command. Interrupt request. IREQ# is asserted by a 16-bit I/O PC Card to indicate to the host that a device on the 16-bit I /O PC Card requires service by the host software. IREQ# is high (deasserted) when no interrupt is requested. 16-Bit PC Card Interface Control Terminals Name BVD1 (STSCHG#/RI#) BVD2 (SPKR#) CD1# CD2# Type Description I Battery voltage detect 1. BVD1 is generated by 16-bit memory PC Cards that include batteries. BVD1 is used with BVD2 as an indication of the condition of the batteries on a memory PC Card. Both BVD1 and BVD2 are high when the battery is good. When BVD2 is low and BVD1 is high, the battery is weak and should be replaced. When BVD1 is low, the battery is no longer serviceable and the data in the memory PC Card is lost. See Section 5.6, ExCA Card Status-Change-Interrupt Configuration Register, for enable bits. See Section 5.5, ExCA Card Status-Change Register, and Section 5.2,ExCA Interface Status Register, for the status bits for this signal. Status change. STSCHG# is used to alert the system to a change in the READY, write protect, or battery voltage dead condition of a 16-bit I/O PC Card. Ring indicate. R# is used by 16-bit modem cards to indicate a ring detection. I I Battery voltage detect 2. BVD2 is generated by 16-bit memory PC Cards that include batteries. BVD2is used with BVD1 as an indication of the condition of the batteries on a memory PC Card. Both BVD1and BVD2 are high when the battery is good. When BVD2 is low and BVD1 is high, the battery is weak and should be replaced. When BVD1 is low, the battery is no longer serviceable and the data in the memory PC Card is lost. See Section 5.6, ExCA Card Status-Change-Interrupt Configuration Register, for enable bits. See Section 5.5, ExCA Card Status-Change Register, and Section 5.2, ExCA Interface Status Register, for the status bits for this signal. Speaker. SPKR# is an optional binary audio signal available only when the card and socket have been configured for the 16-bit I/O interface. The audio signals from cards A and B are combined by the PCI4410A device and are output on SPKROUT.DMA request. BVD2 can be used as the DMA request signal during DMA operations to a 16-bit PC Card that supports DMA. The PC Card asserts BVD2 to indicate a request for a DMA operation. Card detect 1 and Card detect 2. CD1# and CD2# are connected internally to ground on the PC Card. When a PC Card is inserted into a socket, CD1# and CD2# are pulled low. For signal status, see Section 5.2, ExCA Interface Status Register. 132 8170 N/B MAINTENANCE 5.4 PCI4410(PCMCIA/1394 LINK Controller ) 16-Bit PC Card Interface Control Terminals Name REG# Description O Attribute memory select. REG# remains high for all common memory accesses. When REG# is asserted, access is limited to attribute memory (OE# or WE# active) and to the I/O space (IORD# or IOWR# active). Attribute memory is a separately accessed section of card memory and generally is used to record card capacity and other configuration and attribute information. DMA acknowledge. REG is used as a DMA acknowledge (DACK#) during DMA operations to a 16-bit PC Card that supports DMA. The PCI4410A device asserts REG# to indicate a DMA operation. REG# is used in conjunction with the DMA read (IOWR#) or DMA write (IORD#) strobes to transfer data. PC Card reset. RESET forces a hard reset to a 16-bit PC Card. RESET O WAIT# I WE# O WP IOIS16# VS1# VS2# CardBus PC Card Interface System Terminals Type I I/O Bus cycle wait. WAIT# is driven by a 16-bit PC Card to extend the completion of the memory or I/O cycle in progress. Write enable. WE# is used to strobe memory write data into 16-bit memory PC Cards. WE# also is used for memory PC Cards that employ programmable memory technologies. DMA terminal count. WE# is used as TC during DMA operations to a 16-bit PC Card that supports DMA. The PCI4410A device asserts WE to indicate TC for a DMA read operation. Write protect. WP applies to 16-bit memory PC Cards. WP reflects the status of the write-protect switch on 16-bit memory PC Cards. For 16-bit I/O PC cards, WP is used for the 16-bit port (IOIS16#) function. I/O is 16 bits. IOIS16# applies to 16-bit I/O PC Cards. IOIS16# is asserted by the 16-bit PC Card when the address on the bus corresponds to an address to which the 16-bit PC Card responds, and the I/O port that is addressed is capable of 16-bit accesses. DMA request. WP can be used as the DMA request signal during DMA operations to a 16-bit PC Card that supports DMA. If used, the PC Card asserts WP to indicate a request for a DMA operation. Voltage sense 1 and voltage sense 2. VS1 and VS2, when used in conjunction with each other, determine the operating voltage of the PC Card. Type Description CCLK Name O CCLKRUN# I/O CRST# O CardBus clock. CCLK provides synchronous timing for all transactions on the CardBus interface. All signals except CRST#, CCLKRUN#, CINT#, CSTSCHG, CAUDIO, CCD2#, CCD1#, CVS2, and CVS1 are sampled on the rising edge of CCLK, and all timing parameters are defined with the rising edge of this signal. CCLK operates at the PCI bus clock frequency, but it can be stopped in the low state or slowed down for power savings. CardBus clock run. CCLKRUN# is used by a CardBus PC Card to request an increase in the CCLK frequency, and by the PCI4410A device to indicate that the CCLK frequency is going to be decreased. CardBus reset. CRST# brings CardBus PC Card-specific registers, sequencers, and signals to a known state. When CRST# is asserted, all CardBus PC Card signals are placed in a high-impedance state, and the PCI4410A device drives these signals to a valid logic level. Assertion can be asynchronous to CCLK, but deassertion must be synchronous to CCLK. CardBus PC Card Address and Data Terminals Type Description CAD[0:31] Name I/O CC/BE[0:3]# I/O CPAR I/O CardBus address and data. These signals make up the multiplexed CardBus address and data bus on the CardBus interface. During the address phase of a CardBus cycle, CAD31–CAD0 contain a 32-bit address. During the data phase of a CardBus cycle, CAD31–CAD0 contain data. CAD31 is the most significant bit. CardBus bus commands and byte enables. CC/BE3#–CC/BE0# are multiplexed on the same CardBus terminals. During the address phase of a CardBus cycle, CC/BE3#–CC/BE0# define the bus command. During the data phase, this 4-bit bus is used as byte enables. The byte enables determine which byte paths of the full 32-bit data bus carry meaningful data. CC/BE0# applies to byte 0 (CAD7–CAD0), CC/BE1# applies to byte 1 (CAD15–CAD8), CC/BE2# applies to byte 2 (CAD23–CAD16), and CC/BE3# applies to byte 3 (CAD31–CAD24). CardBus parity. In all CardBus read and write cycles, the PCI4410A device calculates even parity across the CAD and CC/BE buses. As an initiator during CardBus cycles, the PCI4410A device outputs CPAR with a one-CCLK delay. As a target during CardBus cycles, the calculated parity is compared to the initiator’s parity indicator; a compare error results in a parity-error assertion. 133 8170 N/B MAINTENANCE 5.4 PCI4410(PCMCIA/1394 LINK Controller ) CardBus PC Card Interface Control Terminals Name CAUDIO CBLOCK# CCD1# CCD2# CDEVSEL# CFRAME# Type Description I CardBus audio. CAUDIO is a digital input signal from a PC Card to the system speaker. The PCI4410A device supports the binary audio mode and outputs a binary signal from the card to SPKROUT. CardBus lock. CBLOCK# is used to gain exclusive access to a target. CardBus detect 1 and CardBus detect 2. CCD1# and CCD2# are used in conjunction with CVS1 and CVS2 to identify card insertion and interrogate cards to determine the operating voltage and card type. CardBus device select. The PCI4410A device asserts CDEVSEL# to claim a CardBus cycle as the target device. As a CardBus initiator on the bus, the PCI4410A device monitors CDEVSEL# until a target responds. If no target responds before timeout occurs, the PCI4410A device terminates the cycle with an initiator abort. CardBus cycle frame. CFRAME# is driven by the initiator of a CardBus bus cycle. CFRAME# is asserted to indicate that a bus transaction is beginning, and data transfers continue while this signal is asserted. When CFRAME# is deasserted, the CardBus bus transaction is in the final data phase. CardBus bus grant. CGNT# is driven by the PCI4410A device to grant a CardBus PC Card access the CardBus bus after the current data transaction has been completed. CardBus interrupt. CINT# is asserted low by a CardBus PC Card to request interrupt servicing from the host. CardBus initiator ready. CIRDY indicates the CardBus initiator’s ability to complete the current data phase of the transaction. A data phase is completed on a rising edge of CCLK when both CIRDY and CTRDY are asserted. Until both CIRDY and CTRDY are sampled asserted, wait states are inserted. CardBus parity error. CPERR# reports parity errors during CardBus transactions, except during special cycles. It is driven low by a target two clocks following that data when a parity error is detected. CardBus request. CREQ# indicates to the arbiter that the CardBus PC Card desires use of the CardBus bus as an initiator. CardBus system error. CSERR# reports address parity errors and other system errors that could lead to catastrophic results. CSERR# is driven by the card synchronous to CCLK, but deasserted by a weak pull up, and may take several CCLK periods. The PCI4410A device can report CSERR# to the system by assertion of SERR# on the PCI interface. I/O I I/O I/O CGNT# O CINT# I CIRDY# I/O CPERR# I/O CREQ# I CSERR# I Name CSTOP# CSTSCHG# CTRDY# Type Description I/O CardBus stop. CSTOP# is driven by a CardBus target to request the initiator to stop the current CardBus transaction. CSTOP# is used for target disconnects, and is commonly asserted by target devices do not support burst data transfers. CardBus status change. CSTSCHG alerts the system to a change in the card’s status, and is used a wake-up mechanism. CardBus target ready. CTRDY# indicates the CardBus target’s ability to complete the current data phase of the transaction. A data phase is completed on a rising edge of CCLK, when both CIRDY and CTRDY# are asserted; until this time, wait states are inserted. CardBus voltage sense 1 and CardBus voltage sense 2. CVS1 and CVS2 are used in conjunction with CCD1# and CCD2# to identify card insertion and interrogate cards to determine the operating voltage and card type. I I/O CVS1 CVS2 IEEE 1394 PHY/Link Interface Terminals Type Description PHY_CTL1 PHY_CTL0 Name I/O PHY_DATA[0:7] I/O PHY-link interface control. These bidirectional signals control passage of information between the PHY and link. The link can drive these terminals only after the PHY has granted permission, following a link request (LREQ). PHY-link interface data. These bidirectional signals pass data between the PHY and link. These terminals are driven by the link on transmissions and are driven by the PHY on receptions. Only DATA1–DATA0 are valid for 100-Mbit speed. DATA4–DATA0 are valid for 200-Mbit speed and DATA7–DATA0 are valid for 400-Mbit speed. System clock. This input provides a 49.152-MHz clock signal for data synchronization. Link request. This signal is driven by the link to initiate a request for the PHY to perform some service. 1394 link on. This input from the PHY indicates that the link should turn on. Link power status. LPS indicates that link is powered and fully functional. PHY_CLK I PHY_REQ O LINKON I LPS O 134 8170 N/B MAINTENANCE 5.4 PCI4410(PCMCIA/1394 LINK Controller ) Zoomed-Video Interface Terminals Name Type Description ZV_HREF O Horizontal sync to the zoomed-video port ZV_VSYHC O Vertical sync to the zoomed-video port ZV_Y[0:7] O Video data to the zoomed-video port in YUV:4:2:2 format ZV_UV[0:7] O Video data to the zoomed-video port in YUV:4:2:2 format ZV_SCLK O Audio SCLK PCM ZV_MCLK O Audio MCLK PCM ZV_PCLK IO Pixel clock to the zoomed-video port ZV_LRCLK O Audio LRCLK PCM ZV-SDATA O Audio SDATA PCM 135 8170 N/B MAINTENANCE 6. System Block Diagram VID[0:4] U1 Pentium 4 mFC-PGA2 478 Pin J2 LCD Panel 400M J1 Monitor U516 ATI VGA J5 TV OUT HDD J10 IDE2 CD-ROM J2,J3 USB Port D/D Board AGP4X 66M D/D Board J14 IDE1 CPU_CORE U3 82845 MCH 593 PIN mBGA 133M PU508 LTC1709 J503 SO-DIMM1 J505 SO-DIMM2 U14 1394 TSB41AB1 X3 32.768KHZ D/D Board U509 U509 Supper Supper I/O I/O PC87393 PC87393 J1 PIO Port U8 U8 82801BA 82801BA ICH2 ICH2 360 360 PIN PIN mBGA mBGA USB U7 U7 PCI BUS 33M PCI4410 PCI4410 U4 U4 LANPHY LANPHY RTL8139CL RTL8139CL U15 U15 J8 Card BUS Socket AUDIO AUDIO CODEC CODEC LPC BUS ISA BUS U12 U12 Flash FlashROM ROM U508 U508 H8/3437 H8/3437 J15 Touch Pad J21 Mini 1394 J12 Internal Keyboard U18 U18 Amplifier Amplifier J19 Line Out 136 8170 N/B MAINTENANCE 7. Maintenance Diagnostic 7.1 Introduction Every time the computer is turned on ,the system BIOS runs a series of internal checks on the hardware. This power-on self test (post) allows the computer to detect problems as early as the power-on stage. Error messages of post can alert you to the problems of your computer. If an error is detected during these tests, you will see an error message displayed on the screen. If the error occurs before the display, then the screen cannot display the error message. Error codes or system beeps are used to identify a post error that occurs when the screen is not available. The value for the diagnostic post (378H) is written at the beginning of the test. Therefore , if the test fail, the user can determine where the problem occurs by reading the last value written to post 378H by the PIO debug board plug at PIO port. 137 8170 N/B MAINTENANCE 7.2 Error codes : Following is a list of error codes in sequent display on the PIO debug board. Code POST Routine Description Code POST Routine Description 10h Some type of lone reset 20h Test keyboard 11h Turn off FAST A20 for POST 21h Test keyboard controller 12h Signal power on reset 22h Check if CMOS RAM valid 13h Initialize the chipset 23h Test battery fail & CMOS X-SUM 14h Search for ISA Bus VGA adapter 24h Test the DMA controller 15h Reset counter / Timer 1 25h Initialize 8237A controller 16h User register config through CMOS 26h Initialize int vectors 17h Sizememory 27h RAM quick sizing 18h Dispatch to RAM test 28h Protected mode entered safely 19h Check sum the ROM 29h RAM test completed 1Ah Reset PIC’s 2Ah Protected mode exit successful 1Bh Initialize video adapter(s) 2Bh Setup shadow 1Ch Initialize video (6845Regs) 2Ch Going to initialize video 1Dh Initialize color adapter 2Dh Search for monochrome adapter 1Eh Initialize monochrome adapter 2Eh Search for color adapter 1Fh Test 8237A page registers 2Fh Signon messages displayed 138 8170 N/B MAINTENANCE 7.2 Error codes : Following is a list of error codes in sequent display on the PIO debug board. Code POST Routine Description Code POST Routine Description 30h Special init of keyboard ctlr 40h Configure the COMM and LPT ports 31h Test if keyboard Present 41h Initialize the floppies 32h Test keyboard Interrupt 42h Initialize the hard disk 33h Test keyboard command byte 43h Initialize option ROMs 34h Test, blank and count all RAM 44h OEM’s init of power management 35h Protected mode entered safely(2) 45h Update NUMLOCK status 36h RAM test complete 46h Test for coprocessor installed 37h Protected mode exit successful 47h OEM functions before boot 38h Update output port 48h Dispatch to operate system boot 39h Setup cache controller 49h Jump into bootstrap code 3Ah Test if 18.2Hz periodic working 3Bh Test for RTC ticking 3Ch Initialize the hardware vectors 3Dh Search and init the mouse 3Eh Update NUMLOCK status 3Fh Special init of COMM and LPT ports 139 8170 N/B MAINTENANCE 7.3 Debug Card 7.3.1 Diagnostic Tools : The 378 Port Debug Card, a kind of tool, is designed mainly for Notebook . It can be used to test the process of BIOS POST system. It composed of eight . LED and one PIO CONNECTOR as the below figure shows P/N:411904800001 DESCRIPTION :PWA;PWA-378PORT DEBUG BD Note:Order it from MIC/TSSC 140 8170 N/B MAINTENANCE 7.3 Debug Card 7.3.2 CIRCUIT: PIO CONNECTOR 25 13 14 1 LED PIN DEFINITION OF PIO PORT PIN 1 PIN 2-9 PIN10 PIN11 PIN12 PIN13 STB STROBE SIGNAL PIN 14 AFD D0 - D7 PARALLEL PORT DATA BUS D0 TO D7 PIN15 ERR ACK ACKNOWLEDGE HANDSHANK PIN16 INIT BUSY BUSY SIGNAL PIN17 SLIN SIGNAL PE PAPER END PIN18-25 GROUND SLCT PRINTER SELECTED AUTO LINE FEED ERROR AT PRINTER INITIATE OUTPUT PRINTER SELECT 141 8170 N/B MAINTENANCE 8.Trouble Shooting 8.1 No Power 8.9 CD-ROM Drive Test Error 8.2 Battery Can not Be Charged 8.10 USB Port Test Error 8.3 No Display 8.11 PIO Port Test Error 8.4 VGA Controller Failure LCD No Display 8.12 PC-Card Failure 8.5 VGA Controller Failure External Monitor No Display 8.13 IEEE1394 Failure 8.6 Memory Test Error 8.14 Audio Failure 8.7 Keyboard(K/B) and Touch Pad(T/B) Test Error 8.15 LAN Test Error 8.8 Hard Drive Test Error 142 8170 N/B MAINTENANCE 8.1 No Power When the power button is pressed, nothing happens, no fan activity is heard and power indicator is not light up. P2 Power In J5 PQ512 PF501 PL502 PL503 P2 PD2 JS7 PU7 PL8 ALWAYS PD501 P20 +5VAS D509 +5VA VCC_RTC P13 H8_VDD5 P19 L520 PQ502 PQ503 PR513 PR514 PD4-PD6 P20 PL500 PL501PU1, PU2,PU500-PU508 P2 DVMAIN PU12 Q514 L516 P21 CPU_CORE L518 Charge Board PU505 PU506 JL3 JL2 PU1 PL3 ADNP ADNP_1 ADNP_2 P2 P2 L517 P1 PU501 +3V P1 +12V P2 PQ2 +12VS U511 JS502 P17 L20 AVDDAD P2 +3VS L519 JL1 P15 P21 L6,L7 +1.8VS P17 L507 +3VS_SPD P8 L4 +3VCLKPCI P8 +3VCLKANA L514 P11 VDD_DAC1.8 P11 VDD_PLL1.8 P11 VDD_PNLLL1.8 P11 VDD_MEMPLL1.8 P8 +3VCLKCPU P8 +3VCLK66 VCC3_IR 1394AVDD Mother Board P2 PU502 PU503 PU511,PU5 PU6,PL7, PU512,PU9 PD4-PD6 PU10 PU11 P1 PU504 +5V P2 +5VS L12 JS10 U504 PU13 DBATT PU8 P22 VPPA VCCA P15 P15 5V_AMP U505 P16 +3V_LAN P21 +1.5VS P16 L10 R33 AVDD_LAN P10 AGP_VREF P11 VDDR_MEM2.5 L506 P17 L11 +3V_ICH P20 PU514 P11 VDD_DAC2.5 P11 VDD_MCLK2.5 +1.8V_ICH P21 143 8170 N/B MAINTENANCE 8.1 No Power (1) When the power button is pressed, nothing happens, no fan activity is heard and power indicator is not light up. Power on Sequence 144 8170 N/B MAINTENANCE 8.1 No Power (2) When the power button is pressed, nothing happens, no fan activity is heard and power indicator is not light up. PD2 2 3 1 PQ503 SI4835DY PD3 8 7 6 5 3 2 1 2 3 8 ALWAYS J3 P22 PJ1 1 ADINP 10,12 S D G PR4 470K JL2 DVMIAN 1 PL502 120Z/100M PR514 .1 PQ502 PF501 J5 6.5A/32VDC PL503 8 7 6 5 3 2 1 120Z/100M S POWER IN PC505 1U PC510 0.1U PC509 0.1U PD6 D G PD501 PC19 100U RLZ24D PR10 10K PD5 PC17 0.1U PJ2 PR5 470k +5VA PR16 470K PQ1 3 8 IN 2 SENSE 7 FB 3 SHUTDN From H8 PC26 0.1U PL8 6 5VTAP 1 OUT ERR4 GND 1 ADINP_2 2 2 LEARNING 3 3 MB +5V G S PD7 PC24 10U D PQ1 S1231DS Step1 : Connect Adaptor to ( D/D BD ) J5 & O/P “ALWAYS”. Step2 : “ALWAYS” --> PU7 Generate +5VA. Step3 : H8 O/P “LEARNING” for Charger Circuitry. Step4 : For MOSFET “PQ502&PQ503” G=0,D<-->S. Mother Board 1 PR6 100K 2 PU7 PR9 47K G S 1 J6 P22 ADINP_1 D 2N7002 PQ2 SW_+5VA PR513 .1 PD4 P20 ALWAYS JS7 MB JL3 SI4835DY P19 12 LEARNING U508 H8 F3437 19 SW +5VA Step5 : O/P “ADINP”& “DVMAIN”. 145 8170 N/B MAINTENANCE 8.1 No Power (3) When the power button is pressed, nothing happens, no fan activity is heard and power indicator is not light up. PU11 P20 SI4835DY 8 7 6 5 +5VA S D S D PR573 100K G J28 +5VAS 3 2 1 G PQ512 PD503 -ADEN(From H8) PL9 120Z +3V 3 P20 PF2 PL10 120Z PU10 SI4835DY 8 7 6 5 DBATT +5VA---->+5VAS D DVMAIN PR554 1M G PC30 0.1U PC32 0.01U Battery Connector +12VS 8 7 6 5 +3V PR23 4.7K PC43 10P P21 +1.5VS 2 1 D +5VA P19 PR563 100K PQ508 D 2N7002 -ADEN G S S G PC42 470P PQ3 SCK431LCSK-5 PR22 4.7K PR24 4.7K +5VAS DVMAIN PR559 100K PU13 3 AO4400 1 3 2 1 S PF1 PL11 120Z 1,2 1 PQ511 PC44 10U P22 PC45 0.1U 30 PR572 100K PR567 100K 47 U508 3 H8 F3437 2 1 BATT_DEAD Q510 DTC144TKA 1 8 4 PU513A LMV393M PR564 475K 3 + - 2 PQ510 SCK431 PR566 100K 3 ADINP 1 PR561 169K PQ509 DTC144WK 2 Battery OVP +3V---->+1.5VS +5V PR616 0 PC29 4.7U +5V---->+3V_ICH P20 +3V_ICH +3V_ICH 1 VIN GND +1.8V-ICH PU514 VOUT 3 PC27 4.7U D8 RLZ3.6B PC22 0.1U PC559 1U 1 VIN 3 EN 4 2 GND BYP AME8801 PC560 MEEV 0.01U PC558 4.7U P21 +3VS ----> +1.8VS +3VS PU12 AMS1085 3 VIN VOUT 2 OUT 5 PU8 2 P21 +3V_ICH ----> +1.8V_ICH PC37 4.7U GND/ADJ 1 +1.8VS PR19 1.2K PC9 100U PC10 0.1U PR20 560 146 8170 N/B MAINTENANCE 8.1 No Power When the power button is pressed, nothing happens, no fan activity is heard and power indicator is not light up. Battery can not Charge Is the notebook connected to power (AC adaptor)? No Check the following parts for cold solder or one of the following parts on the D/D Board may be defective, use an oscilloscope to check the following signal or replace the parts one at a time and test after each replacement.8 Connect AC adaptor. Yes Parts 1. Make sure that the battery is good. 2. Make sure that the battery is installed properly. 3. Check the D/D board is connected to M/B properly. Power OK? Yes Board-level Troubleshooting J5 PL502 PL503 PD[501:503] PQ1 PR5 PR9 PR514 PR513 JL2 JL3 PD[2:6] PJ1 PJ2 J6 U508 Try another known good D/D Board. Board-level Troubleshooting Check the following parts for cold solder or one of the following parts on the mother-board may be defective, use an oscilloscope to check the following signal or replace the parts one at a time and test after each replacement. Parts No Yes ALWAYS ADINP DVMAIN ADINP_1 ADINP_2 LEARNING Correct it. No Power OK? Signal Replace the faulty D/D Board Replace Motherboard PU7 PQ2 PL8 PQ1 J28 PL[9:11] PF1 PF2 PU10 PU11 PR554 PR559 PQ[508:510] U508 Q510 PU513 PR567 PR572 PR564 PR566 Signal +5VA SW_+5VA DBATT ADINP -ADEN BATT_DEAD DVMAIN 147 8170 N/B MAINTENANCE 8.2 Battery Can not Be Change When the battery is installed but the battery status indicate LED display abnormal. J3 10,12 ADINP +5VAS IN SENSE F/B SHUTDN 5VTAP 6 OUT 1 PC535 4.7U GNT 4 15 VCTL PU510 LP295 PC536 0.1U 13 REFIN J6 2 1 PR548 10 ADINP_2 PR552 10 ADINP_1 PR546 10K E B G S P19 44 40 DCIN 2 5 6 7 3 G 4 24 PU5 S LX 23 22 DL0V PQ506 2N7002 PR539 1K IINP 28 4 PR14 1M 1 2 3 3 2 1 PU512 PR15 1M PR555 12.1K G PU9 PR551 1M PC28 10U D PC538 0.1U G D510 PQ507 2N7002 DBATT PL9 120Z BAT_V PL14 3 2 DBATT D S G S PR536 10K 8 7 6 5 3 2 1 PR556 1M PC539 0.1U +5VA H8 F3437 8 7 6 5 PC23 100U PD6 PU6 G PQ510 100K CSIN 18 BATT 17 PR615 0 U508 PR13 0.035 19 CSIP ICTL 14 PL7 D PGND 20 PR537 47K 1 2 3 5 6 7 DBATT PC18 100U PC20 10U D 21 5 + - 6 8 PR572 100K PR570 12.1K PU513B LMV393M D 1 DL0 PC553 1U PR553 47K 69 25 PC542 0.1U PU511 MAX1772 7 4 S D CHARGING DHI LI_OVP PL6 PD502 27 CSSP 1 PR547 33K BST CSSN PQ505 BT3906 C LI_OVP 26 P22 PL5 PC551 1U 16 2 CELLS LD0 PR569 1M PD4 8 8 2 7 3 PD5 PR557 33 PR541 100K 8 D/D Board connector PR534 100K S PR532 10 PR565 100K PL15 1 39 BAT_VOLT 2 7 38 BAT_TEMP 1 8 99 BAT_CLK 3 6 23 BAT_DATA 4 5 RP518 33*4 BAT_T PR562 301K +5VAS PF2 PL10 120Z PR18 4.99K PF1 PL11 120Z J28 1,2 P20 3 4 BAT_C 5 BAT_D PR17 20K Battery Connector 148 8170 N/B MAINTENANCE 8.2 Battery Can not Be Change When the battery is installed but the battery status indicate LED display abnormal. Battery can not Charge Board-level Troubleshooting Is the notebook connected to power (AC adaptor)? No Connect AC adaptor. Yes Replace Motherboard Check the following parts for cold solder or one of the following parts on the mother-board may be defective, use an oscilloscope to check the following signal or replace the parts one at a time and test after each replacement.2 Parts 1. Make sure that the battery is good. 2. Make sure that the battery is installed properly. Battery charge OK? No Yes Correct it. J3 J6 PR548 PQ505 PR546 PU511 PR534 PD502 PU5 PD[4:6] PL[9:11] PQ507 PR556 PQ510 PR569 PU9 Signal PU510 PR552 PQ506 U508 PR557 PR541 PC542 PU6 PL[5:7] PF[1:2] J28 PU513 PR570 PU512 ADINP ADINP_1 ADINP_2 LI_OVP CHANGING DBTT BAT_T BAT_C BAT_D 149 8170 N/B MAINTENANCE 8.3 No Display System Clock Check R45 1K 0 0 0 1 100MHz 1 1 133MHz H_BSEL R44 1K L517 120Z/100M C626 0.1U +3VS C619 0.1U +3VS C641 0.1U FS1 55 FS2 40 51 R50 1K +3VCLKCPU 46,50 U507 ICS950805 R594 33 -HCLK_CPU R608 33 HCLK_MCH 41 R612 33 -HCLK_MCH 66M_MCH66IN 21 R621 33 21 SMBCLK 21 SMBDATA 39 R624 33 USBCLK_ICH 56 R596 33 14M_ICH 13 R616 33 PCICLK_ICH 22 R620 33 66M_ICH 142 U1 Pentium 4 SMBDATA0 U3 BrookdaleMCH82845 61 SDRAMCLK1 74 SDRAMCLK4 142 SDRAMCLK5 12 +5V R609 33 R595 33 +3VCLKNA 1,26,37 11 10 3 C646 2.2U 19,32 Q7 FDV302 R51 10K SMBCLK P9 G 3 DRAMENA 1 SMBDATA D Q6 DTC144TKA SMBDATA 2 Q8 FDV302 G PCICLK_LPC 8 SIO_14.318MHZ 20 D SMBDATA1 S U509 PC87383 R626 33 R169 100K 66M_AGP R610 33 PCICLK_LAN R607 33 PCICLK_CARD X502 14.318M 3 2 4 2 +3VCLK66 141 R168 100K U17 ICH2 82801BA 141 J505 SDRAMCLK0 +3VCLKPCI 8,14 C649 2.2U L519 120Z/100M 74 HCLK_CPU 45 23 L518 120Z/100M R592 33 54 C622 2.2U C645 0.1U +3VS 52 C625 2.2U L516 120Z/100M 61 P8 FS0 From CPU +3VS J503 FS2 FS1 FS0 CPUCLK DS +3VS C618 5P C617 5P U7 PCI4410 HK U4 RTL8139CL U516 MOBILITY -M6 150 8170 N/B MAINTENANCE 8.3 No Display System Reset Check +5VA P4 H8_VDD5 L520 P7 U1 U3 -CPURST Pentium 4 U10 MAX809 3 VCC P19 RESET# 4 9 59 2 -H8_RESET 36 37 P19 1 21 H8_PWROK 5 U508 D505 BAV99 Micro -POWERBTN -PWRSW P13 P10 U17 18 Q513 DTC144TKA -H8_ICH2BIN 23 -PWRBTN R100 10K H8/F3437 +3V_ICH ICH2 82801BA -PCIRST_MSK +3V -RSMRST C634 .01U Q15 DTC144TKA C181 1U Easy Start Button -BRSTDRV1 2 C630 68P C633 68P NC7S08 U8 3 8170 Power 1 J14 P14 Primary EIDE Connector J10 5 9 -PCIRST P14 Secondary EIDE Connector P18 Y P13 115 -PCIRST_N +3V -BRSTDRV2 14 X503 16MHZ 5 VCC 4 Y A 2 B 3 GNT R55 33 R56 33 U16 1 -CDROM_RST -HDD_RST H8_PWRON U516 VGA M6 R158 4.7K Tr>10ms R617 1K R627 1M -PCIRST -PCIRST +5V Controller P19 5 PWROK +5V 2 J5 4 SN74CBTD3384 +5VA 1 -PCIRST U13 GND 1 3 MCH 82845 H_PWRGD Level Shift +5VA U4 LANPHY A 1 5 VCC NC7S08 4 P15 U509 U7 -CBRST PC87393 PCI14410GHK Module 151 8170 N/B MAINTENANCE 8.3 No Display There is no display on both LCD and VGA monitor after power on although the LCD and monitor is known-good. No Display Monitor or LCD module OK? No Replace monitor or LCD. Board-level Troubleshooting Yes Make sure that CPU module, DIMM memory are installed Properly. Display OK? Yes Correct it. No Yes According error Cord to repair No 1.Try another known good CPU module, DIMM module And BIOS. 2.Remove all of I/O device (FDD, HDD, CD-ROM…….) from motherboard except LCD or monitor. Display OK? Replace Motherboard If 378 Port Have error code Yes Check system clock and reset circuit. 1. Replace faulty part. 2. Connect the I/O device to the M/B one at a time to find out which part is causing the problem. To be continued Clock and reset checking No 152 8170 N/B MAINTENANCE 8.4 VGA Controller Failure LCD No Display There is no display or picture abnormal on LCD or monitor. +3VS 8 7 6 5 D C507 0.1U G +12V F502 L505 SMDC110 120Z/100M J2 NDS9410 LCDVCC C506 0.1U R515 470K C512 10U C503 0.1U R1 P10 Q502 ENPVDD DTC144WK 1 DISPLAY 3 UNIQAC U516 VGA-M6 +3VS LCD_ID0 LCD_ID1 R22 10K LCD_ID2 MOBILITY M6 3 -ENABKL LCD_ID2 U508 Micro Controller H8/F3437 LCD_ID1 0 LCD_ID0 0 HYUNDAI 0 1 0 0 1 1 CMO 1 0 0 P12 33 35 LCD_ID2 RP520 47K*4 LCD 31 LCD_ID0 LCD_ID1 1 HANNSTAR 4 3 2 1 5 6 7 8 +5VAS 2 Q12 DTC144WK 1 J6 7 PJ2 L507 ENPBLT1 7 BKL_VMAIN L510 1 L509 3 4 L508 8 BLADJ 15 15 -AC_POWER 1 8 13 13 -BATT_LED 2 7 5 6 7 8 11 11 -BATT_G 3 6 9 9 9 -BATT_R 4 5 10 8 J6 2 P1 P13 -ENABKL_MSK FA501 45 BLADJ U514 90 LED_DATA 91 LED_CLK 1 -H8_RESET 1 A QE 2 B 8 CLK 9 CLR QF QG QH 11 10 -AC_POWER 11 -BATT_LED Inverter P19 TXOUT [0:2]+ TX2OUT [0:2]+ - 3 2 Q3 DTC144WK 1 U17 ICH2 82801BA C1 1000P Close to LCD Connector 2 1,2 TXCLK+ TX2CLK+ - S TXCLK+, - TXOUT [0:2]+ ,TX2CLK+, - TX2OUT [0:2]+, - Q500 3 2 1 Inverter Board GND1 C513 0.1U 12 -BATT_G C512 0.1U GND2 13 -BATT_R D/D Board 153 8170 N/B MAINTENANCE 8.4 VGA Controller Failure LCD No Display There is no display or picture abnormal on LCD or monitor. VGA Controller Failure Board-level Troubleshooting 1.Confirm monitor is good and check the cable are connected properly. 2. Try another known good LCD Display OK? Yes Replace faulty LCD Replace Motherboard One of the following parts on the mother-board may be defective, use an oscilloscope to check the following signal or replace the parts one at a time and test after each replacement. Parts: No Remove all the I/O device & cable from motherboard except extended LCD. Display OK? Yes Connect the I/O device & cable to the M/B one at a time to find out which part is causing the problem. U516 Q3 R22 Q500 C506 F502 J2 J1 PJ2 L[508:510] U514 L507 C512 U17 Q12 Q502 R515 C507 L505 D500 J6 FA501 C513 Signals: -AC_POWER -BATT_LED -BATT_R -BATT_G -ENABLE_MSK -ENABKL EVPVDD TXCLK[+:-] TX2CLK[+:-] TXOUT[0:2][+:-] TX2OUT[0:2][+:-] LCDVCC BLADJ BKL_VMAIN No 154 8170 N/B MAINTENANCE 8.5 VGA Controller Failure Monitor No Display There is no display or picture abnormal on monitor. F501 R544 4.7K J1 R543 4.7K P12 RED L500 120Z/100M GREEN L501 120Z/100M BLUE L502 120Z/100M G SDA S 1 9 2 10 3 11 4 12 5 13 6 14 7 15 8 FA500 4 5 D Q502 2N7002 HSYNC 3 6 2 7 1 8 VSYNC MONITOR 2 1 3 4 2 1 3 JL1 GND_CRT15 JL2 8 7 6 5 CP500 22P*4 8 8 7 6 5 8 7 4 1 3 CP501 22P*4 RP501 75*4 7 CP3 22P*4 2 4 1 3 2 4 D Q501 2N7002 6 S 16 17 G SCL 5 MOBILITY M6 D500 D1FS4 DDC2B 6 U516 VGA-M6 SMDC110 +5VS 5 P10 +5VS External VGA Connector +3VS 155 8170 N/B MAINTENANCE 8.5 VGA Controller Failure Monitor No Display There is no display or picture abnormal on monitor. VGA Controller Failure 1.Confirm monitor is good and check the cable are connected properly. 2. Try another known good monitor Display OK? Yes Replace faulty monitor. Replace Motherboard One of the following parts on the mother-board may be defective, use an oscilloscope to check the following signal or replace the parts one at a time and test after each replacement. No Remove all the I/O device & cable from motherboard except extended monitor. Display OK? Board-level Troubleshooting Yes Connect the I/O device & cable to the M/B one at a time to find out which part is causing the problem. Parts: Signals: U516 R544 R543 Q501 Q501 CP3 RP501 CP501 FA500 L500 L501 L502 CP500 F501 D500 J1 RED GREEN BLUE SDA HSYNC VSYNC SCL No 156 8170 N/B MAINTENANCE 8.6 Memory Test Error Either one or two extend SO-DIMM RAM Module is failure or system hangs up. J505 SO-DIMM +3V P7 CK[2:3] MA [0:14] P9 CKE[2:3] RP7,RP9 MAA [0:12] SMBDATA1 0*8 MD [0:63] MDD [0:63] +5V SDRAMCLK1 SDRAMCLK1 SDRAMCLK2 SDRAMCLK2 SMBCLK R51 10K -MDQMA [0:7] R1 Q6 DTC144TKA U3 MCH 82845 -CS[0:1] -CS[4:5] -SWEA -SCASA -SRASA -MCS[4:5] -MSWEA -MSCASA -MSRASA RP3 G -MCS[0:1] -MSWEA -MSCASA -MSRASA 0*8 RP14 0*8 -MDQMA [0:7] SDRAMCLK4 SDRAMCLK4 SDRAMCLK5 SDRAMCLK5 MDD [0:63] J503 SO-DIMM S P9 Q7 FDV302P SMBDATA0 D U17 ICH2 82801BA G D P13 DRAMENA S Q8 2N7002 SMBDATA1 R169 100K SMBDATA R168 100K SMBCLK SMBCLK MAA [0:12] CK[0:1] CKE[0:1] +3V 157 8170 N/B MAINTENANCE 8.6 Memory Test Error Either one or two extend SO-DIMM RAM Module is failure or system hangs up. Memory Test Error Board-level Troubleshooting 1.If your system installed with expansion SO-DIMM module then check them for proper installation. 2.Make sure that your SO-DIMM sockets are OK. 3.Then try another known good SO-DIMM modules. Test OK? Yes Replace the faulty SDRAM module. If your system host bus clock running at 100MHZ then make sure that SO-DIMM module meet require of PC 100. Yes Parts: U3 RP9 RP14 J503 Q7 Q15 No Test Ok? Replace Motherboard One of the following components or signals on the motherboard may be defective ,Use an oscilloscope to check the signals or replace the parts one at A time and test after each replacement. Replace the faulty SDRAM module. RP7 RP3 J505 U17 Q8 R51 Signals: MD [0:63] MDD [0:63] MA[0:14] MAA[0:14] -DQMA[0:7] -MDQMA[0:7] -CS[0:3] -MCS[0:3] -SWEA -MSWEA -SCASA -MSCASA -SRASA -MSRASA CK[0:3] CKE[0:3] SDRAMCLK1 SDRAMCLK2 SDRAMCLK4 SDRAMCLK5 SMBCLK SMBDATA SMBDATA0 SMBDATA1 DRAMENA No 158 8170 N/B MAINTENANCE 8.7 Keyboard (K/B) Touch-Pad (T/P) Test Error Error message of keyboard or touch-pad failure is shown or any key does not work. +5VA H8_VDD5 L520 P19 9,59,4 120Z/100M P13 37 IRQ1 53 36 IRQ12 U17 54 -IOR ICH2 82801BA 96 -IOW 97 J12 P19 KO[0:15] U508 XD[0:7] KI[0:7] Micro Controller ICH-A20GATE Internal Keyboard Connector +5V H8/F3437 L13 +5VA 10 72 -ROMCS 8 7 Supper I/O PC87393 73 -MCCS 14 Level Shift P18 U509 R78 10K U13 9 J15 120Z/100M L16 R66 10K -H8_KBCS 6 -H8_A20GATE 15 -H8_MCCS 57 T_CLK 1 120Z/100M 3 120Z/100M 2 L15 T_DATA P19 Touch-pad Oonnctor 4 C149 47P 95 2 C139 47P C135 0.1U 17 R627 98 1M 3 X503 74CBTD3384 16MHz C633 68P C630 68P 159 8170 N/B MAINTENANCE 8.7 Keyboard (K/B) Touch-Pad (T/P) Test Error Error message of keyboard or touch-pad failure is shown or any key does not work. Keyboard or Touch-Pad Test Error Board-level Troubleshooting Is K/B or T/P cable connected to notebook properly? No Correct it. Replace Motherboard Yes Try another known good Keyboard or Touch-pad.(Internal or external) Test Ok? No Yes One of the following parts or signals on the motherboard may be defective, use an oscilloscope to check the signals or replace the parts one at a time and test after each replacement. Signals Parts Replace the faulty Keyboard or Touch-Pad U17 U13 U508 J12 L15 X503 C633 C149 C135 U509 R78 L520 L13 L16 R627 C630 C139 J15 IRQ1 IRQ12 -IOR -IOW XD[0:7] -H8_KBCS -H8_A20GATE -H8_MCCS KO[0:15] KI[0:7] T_CLK T_DATA XTAL EXTAL 160 8170 N/B MAINTENANCE 8.8 Hard Drive Test Error Either an error message is shown, or the driver motor continues spinning, while reading data is from or writing data is to hard drive. +5VS +3VS P13 D S +12VS R137 1M G Q13 DTC144WK C201 0.1U +5VS J21 C182 4.7U R138 10K R156 470 -HDD_PWRON Q14 DTC144WK -HDDACTP P14 39 D12 PG1102W +5VS 41,42 D513 EC10QS04 R84 4.7K R91 10K -HDDRST -HDD_RST -PDACK -PDACK PDA1 PDA1 PDA0 PDA0 ICH2 PIORDY PIORDY PDREQ PDREQ 82801BA -PDIOW -PDIOW -PDIOR IRQ14 -PDIOR INTRQ -PCS1 -PCS1 -PCS3 -PCS3 PDA2 PDA2 U17 1 29 33 35 27 21 23 25 31 37 38 36 DD [0:15] PDD [0:15] R71 5.6K 28 R49 470 Primary EIDE Connector For Hard Disk 161 8170 N/B MAINTENANCE 8.8 Hard Drive Test Error Either an error message is shown, or the driver motor continues spinning, while reading data is from or writing data is to hard drive. Hard Driver Test Error 1. Check if BIOS setup is OK?. 2. Try another working drive and cable. Re-boot OK? Board-level Troubleshooting Yes Replace the faulty parts. Replace Motherboard No Check the system driver for proper installation. Re - Test OK? Yes End One of the following parts or signals on the motherboard may be defective, use an oscilloscope to check the signals or replace the parts one at a time and test after each replacement. PARTS: SIGNALS: U17 Q13 R137 C182 R91 R156 -HDDRST -PDACK PDA1 PDA0 PIORDY PDERQ -PDIOW -PDIOR IRQ14 -PCS1 -PCS3 PDA PDD[0:15] -HDD_PWRON R138 Q14 C201 R84 R71 J21 No 162 8170 N/B MAINTENANCE 8.9 CD-ROM Drive Test Error An error message is shown when reading data from CD-ROM drive. +5VS +3VS P13 D S +12VS R577 1M G Q503 DTC144WK C593 0.1U +5VS C587 4.7U R580 10K J10 R682 470 -CDROM_PWRON Q504 DTC144WK -CDACTP P14 37 D11 PG1102W +5VS 38-42 D508 EC10QS04 R37 4.7K R36 10K -CDROM_RST -CDROM_RST -SDACK -SDACK SDA1 SDA1 SDA0 SDA0 ICH2 SIORDY SIORDY SDREQ SDREQ 82801BA -SDIOW -SDIOW -SDIOR IRQ15 -SDIOR IRQ15 -SCS1 -SCS1 -SCS3 -SCS3 SDA2 SDA2 SDD [0:15] SDD [0:15] U17 5 28 31 33 27 22 25 24 29 35 Secondary EIDE Connector For CD-ROM 36 34 R582 5.6K 163 8170 N/B MAINTENANCE 8.9 CD-ROM Drive Test Error An error message is shown when reading data from CD-ROM drive. CD-ROM Driver Test Error Board-level Troubleshooting 1. Try another known good compact disk. 2. Check install for correctly. One of the following parts or signals on the motherboard may be defective, use an oscilloscope to check the signals or replace the parts one at a time and test after each replacement. Yes Test OK? Replace the faulty parts. No Replace Motherboard Check the CD-ROM driver for proper installation. Yes Re - Test OK? No End PARTS: U17 R577 Q504 C587 R37 R682 J10 R580 Q503 C593 R36 R582 D12 SIGNALS: -CDROM_RST CDROM_PWRON -SDACK SDA1 SDA0 SIORDY SDERQ -SDIOW -SDIOR IRQ15 -SCS1 -SCS3 SDA2 SDD[0:15] 164 8170 N/B MAINTENANCE 8.10 USB Port Test Error An error occurs when a USB I/O device is installed. U2 +5V J6 P13 -USBOC1 46 3 VIN0 4 VIN1 VCCOUT1 2 USB0VCC5 VCCOUT0 1 USB2VCC5 RT9701-CBL PJ2 R4 33k D/D Board L1 46 -USBOC1 C1 1000P 120Z/100M R3 47k C501 0.1U J2 1 USBP2_2- 16 16 USBP2_2- P3 2 4 3 1 2 3 L2 200Z/100M 4 USBP2_2+ 14 14 USBP2_2+ GND U17 R502 15K USB0VCC5 GND_USB ICH2 82801BA R503 15K R5 33K -USBOC0 48 L4 48 -USBOC0 120Z/100M C4 1000P R6 47K J6 C502 0.1U 1 USBP0_0- 30 30 USBP0_0- 2 4 28 3 3 1 USBP0_0+ P3 2 L3 600Z/100M 4 28 USBP0_0+ GND Mother Board R504 15K R505 15K 165 8170 N/B MAINTENANCE 8.10 USB Port Test Error An error occurs when a USB I/O device is installed. USB Test Error Board-level Troubleshooting Check if the USB device is installed properly. (Including charge board.) Test OK? Yes Correct it Replace Motherboard No Check the following parts for cold solder or one of the following parts on the mother-board may be defective, use an oscilloscope to check the following signal or replace the parts one at a time and test after each replacement. Parts: Replace another known good charge board or good USB device. Re-test OK? No Yes Correct it U17 PJ2 R4 C1 R[502:505] L[1:4] R6 J2 Signals: J6 U2 R3 C502 VCC5 USBVCC5 -USBOC1 USBP2_2- R5 C4 J6 USBP2_2+ -USBOC0 USBP0_0USBP0_0+ 166 8170 N/B MAINTENANCE 8.11 PIO Port Test Error When a print command is issued, printer prints nothing or garbage. +5VS U501 P3 PAC128401Q P22 Mother Board J6 PJ2 P2 25 23 43 P18 P_LPD [0:3] RP500 0*4 21 DP_LPD [0:3] 41 P_LPD [4:7] 19 RP502 0*4 DP_LPD [4:7] 39 17 U509 P_SLCT, -P_STB -P_AFD, -P_ERR RP503 0*4 DP_SLCT, -DP_STB 37 PC87393 13 RP1 8 1 -PP_STB 11 14 STB# 1 -P_AFD 7 2 -PP_AFD 10 15 AFD# 14 P_LPD0 6 3 P_LPD0 9 16 LPD0 2 -P_ERR 5 4 -PP_ERR 8 17 ERR# 15 P_LPD1 RP2 8 1 PP_LPD1 7 18 LPD1 3 -P_INIT 7 2 -PP_INIT 6 19 INIT# 16 P_LPD2 6 3 PP_LPD2 5 20 LPD2 4 -P_SLIN 5 4 -PP_SLIN 4 21 SLIN# 17 PP_LPD3 3 22 LPD3 5 2 1 23 24 P_LPD3 R1 0 -DP_AFD, -DP_ERR D/D Board -P_ACK, P_BUSY RP504 0*4 U502 P3 PAC128401Q -DP_INIT, -DP_SLIN -DP_ACK, DP_BUSY RP3 120OHM/100MHZ P_PE R500 0 35 DP_PE 33 31 CP502 100P*4 C504 22P 29 36 34 CP503 CP504 CP505 100P*4 100P*4 100P*4 32 27 J1 -P_STB Supper I/O -P_INIT, -P_SLIN D501 BAS32L 12 P_LPD4 1 8 PP_LPD4 18-27 GND_IO2 12 13 11 14 LPD4 6 7 8 P_LPD5 7 2 PP_LPD5 10 15 LPD5 P_LPD6 6 3 PP_LPD6 9 16 LPD6 P_LPD7 5 4 PP_LPD7 8 17 LPD7 9 -P_ACK 8 1 -PP_ACK 7 18 ACK# 10 P_BUSY 7 2 PP_BUSY 6 19 BUSY 11 P_PE 6 3 PP_PE 5 20 PE 12 P_SLCT 5 4 PP_SLCT 4 21 SLCT 13 3 22 X 23 24 RP4 120OHM/100MHZ X 2 1 GND_IO2 P3 Parallel Port Connector GND_IO2 167 8170 N/B MAINTENANCE 8.11 PIO Port Test Error When a print command is issued, printer prints nothing or garbage. PIO Test Error Board-level Troubleshooting 1. Check if PIO device is installed properly. (J1) 2. Check CMOS LPT port setting properly. Yes Test OK? Correct it No Try another known good PIO device. Yes Replace the faulty parts. No Re - Test OK? Yes End Replace Motherboard One of the following parts or signals on the motherboard may be defective, use an oscilloscope to check the signals or replace the parts one at a time and test after each replacement. PARTS: U509 RP500 R500 C504 J6 PJ2 RP1 RP2 R1 RP3 RP4 U501 U502 J1 RP[502:504] CP[503:505] SIGNALS: P_SLCT, -P_STB -P_AFD, -P_ERR P_LPD [0:7] -P_INIT, -P_SLIN -P_ACK, P_BUSY P_PE AFD# LPD0 ERR# LPD1 INIT# SLIN# LPD3 LPD2 LPD4 LPD5 LPD6 LPD7 ACK# BUSY PE SLCT No 168 8170 N/B MAINTENANCE 8.12 PC-Card Socket Failure An error occurs when a PC card device is installed. +3V VCCA R46 0 U507 P8 ICS950805 P15 R607 33 10 J8 PCICLK_CARD PCI BUS P13 A21 / IDSEL -CBE [0:3] U17 -IRQ0 -CARD_RI CCLK -CRST -CAUDIO -CBLOCK -CCLKRUN -CCD[ 1:2] CCLK -CRST -CAUDIO -CBLOCK -CCLKRUN -CCD[ 1:2] -CIRDY -CPERR -CSERR -CSTOP -CTRDY -CINT -CREQ -CGNT -CDEVSEL -CIRDY -CPERR -CSERR -CSTOP -CTRDY -CINT -CREQ -CGNT -CDEVSEL R2_D2 R2_D14 R2_A16 CPARC VS[1:2] CSTCHG R2_D2 R2_D14 R2_A16 CPARC VS[1:2] CSTCHG PCI4410GHK SERIRQ 82801BA CAD [0:31] -CCBE [0:3] U7 -GNT0 ICH2 CAD [0:31] -CCBE [0:3] -INTA -INTC +12V -PCIRST +3V_ICH R158 4.7K -PCIRST_RST +3V U16 1 A 2 B 3 GNT Q15 9 -VCCEN1 2 -VCCEN0 1 VPPEN0 15 VPPEN1 14 P15 +3V 3.3VA,B VCCD1 VCCD0 VDDP0 U504 5VA,B AVCCC,B,A TPS2211 AVPP 3,4 VPPA C601 0.1u C599 0.1u 10 VDDP1 C609 0.1u +3V 5 VCCA 11-13 -CBRST 5 4 VCC 4 -PCIRST_N 1 Y A Y -GATE1394 2 B 3 GNT +5V 5,6 C612 0.1u C600 0.1u C603 0.1u C594 0.1u Card Bus Socket C82 0.1u U8 NC7S08 169 8170 N/B MAINTENANCE 8.12 PC-Card Socket Failure An error occurs when a PC card device is installed. PC Card and Test Error 1. Check if the PC CARD device is installed properly. 2. Confirm PC card driver is installed ok. Test OK? Yes Board-level Troubleshooting Correct it No Try another known good PC card device. Re-test OK? No Replace Motherboard Check the following parts for cold solder or one of the following parts on the mother-board may be defective, use an oscilloscope to check the following signal or replace the parts one at a time and test after each replacement. Parts: Yes Change the faulty part then end. R607 U17 U7 C82 C594 C600 C603 U507 U8 U9 J8 C599 C602 C609 Signals PCI BUS SIGNAL CCLK -CRST -CAUDIO -CBLOCK -CCLKRUN -CCD[ 1:2] R2_D2 R2_D14 R2_A16 CPARC VS[1:2] CSTCHG -VCCEN1 -VCCEN0 VPPEN0 VPPEN1 170 8170 N/B MAINTENANCE 8.13 IEEE1394 Failure An error occurs when a PC card device or 1394 device is installed. +3V VCCA R46 0 U507 P8 ICS950805 +3V P15 R607 33 10 Q5 DTC144WK PCICLK_CARD +5V R43 47K 8 VCCEN1 P13 Q4 DTC144WK PCI BUS Write Protect when high A21 / IDSEL P13 R53 4.7K R42 47K R52 4.7K 7 WC- 5 6 -IRQ0 U9 NM24C02N -1394WR -CBE [0:3] U17 P15 VCC C99 0.1U VCCEN0 SDA SCLK U7 -GNT0 +3V -CARD_RI 1394AVDD L20 PCI4410GHK SERIRQ -PCLKRUN 30,31,42 -INTA PHY_D [0:7] -INTC PHY_CTL[0:1] P15 PHY_LREQ -PCIRST R158 4.7K Q15 R73 10 PHY_CLK +3V_ICH -PCIRST_MSK 1 +3V 2 PHY_LKON R80 10 19 PHY_LPS 15 U14 TSB41AB1 60 U16 5 4 VCC 4 -PCIRST_N 1 Y A Y B -GATE1394 2 3 GNT B 3 GNT NC7S32 1 2 X504 24.576MHZ -CBRST +3V A U8 NC7S08 1 2 59 5 C134 10P C152 10P 35 TPB- 1 2 34 TPB+ 4 36 TPA- 3 L23 PLP32166 37 54 55 C161 0.1U 1 2 J21 P15 3 4 TPA+ R103 56 TPBIAS 38 FILTER1 82801BA FILTER0 ICH2 R105 56 R124 4.99K R106 56 R115 56 C200 1U 1 2 4 3 L24 PLP32166 GND1 GND2 C199 270P 171 8170 N/B MAINTENANCE 8.13 IEEE1394 Failure An error occurs when a PC card device or 1394 device is installed. IEEE1394 Test Error 1. Check if the 1394 device is installed properly. 2. Confirm 1394 driver is installed ok. Board-level Troubleshooting Replace Motherboard Test OK? Yes Correct it No Parts: Try another known good 1394 device. Re-test OK? No Check the following parts for cold solder or one of the following parts on the mother-board may be defective, use an oscilloscope to check the following signal or replace the parts one at a time and test after each replacement. Yes Change the faulty part then end. U507 U8 C134 Q4 R53 C99 J21 R115 C199 U17 U14 C152 R43 R52 L23 R105 R106 C200 Signals U7 X504 Q5 R42 U9 L24 R103 R124 R607 PCI BUS SIGNAL PCICLK_CARD -CBE[0:3] -IRQ0 -GNT0 -CARD_RI SERIRQ -INTA -INTC CBRST VCCEN0 VCCEN1 PHY_D[0:7] PHY_CTL[0:1] PHY_LREQ PHY_CLK PHY_LKON PHY_LPS TPA+ TPATPB+ TPBPHY_XI PHY_XO 172 8170 N/B MAINTENANCE 8.14 Audio Failure No sound from speaker after audio driver is installed. AVDDAD +3VS +12VS L14 C672 0.1U 120Z/100M AUDIO IN L540 1 O C702 0.1U P13 1 11 -ACRST 9 25 38 U511 7805 C684 10U I 3 GND 2 C674 0.1U L522 P17 AGND 5 ACSDOUT LINE/IN/L R645 ACSDIN U17 8 22 LINE/IN/R C196 2.2U R121 6.8K 24 C183 2.2U R109 6.8K J16 P17 1 10 ACSYNC 2 MIC1 ICH2 23 R648 ACBITCLK 22 21 MIC1 C194 1U AGND AVDDAD R669 47K 6 R670 47K L535 120Z/100M 82801BA SPK_OFF To U18 Next Page 1 U7 62 C669 0.1U 2 3 PCI4410 C667 0.1U U510 NC7S32 A B VCC 5 C670 0.1U Y 4 R646 470K GND R649 47K 48 SPDIFOUT 8 VCC+ 1IN+ 3 7 2OUT 2IN+ 5 6 LINE/OUT/R 12 PC_BEEP X U513 MC33078D ALC201 C675 0.1U -CARDSPK C686 10U/10V U15 +5VS SBSPKR P15 Internal Micro Phone Jack LINE/OUT/L 36 AOUT_R 35 AOUT_L 2IN- 1OUT R148 68K C209 10U/10V To next Page R647 20K MIC_3 MIC_2 C701 0.068U/25V 1 2IN+ 2 4 VCC- R151 100K R671 4.7K L525 120Z/100M CAGND 5 P17 J22 4 3 2 1 External Micro Phone Jack R149 100K J10 2 R88 1M X2 24.576M C148 10P C167 10P 3 XTL/IN XTL/OUT CD/R CD/L CD/GND 20 18 19 C193 1U R134 6.8K CDROM_RIGHT 2 C191 1U R132 6.8K CDROM_LEFT 1 C192 1U R133 0 CDROM_COMM 3 R142 6.8k R140 6.8k R141 0 P14 CD-ROM Audio Jack 173 8170 N/B MAINTENANCE 8.14 Audio Failure No sound from speaker after audio driver is installed. C710 2.2U R678 10K C210 220U R667 15K AUDIO OUT C694 680P 21 P17 RLINE IN 20 R OUT+ RHP IN R666 10K 22 SPKROUT+ 1 J20 15 SPKROUT- 2 R 3 SPKLOUT+ 1 10 SPKLOUT- 2 R OUT- C709 2.2U R677 10K L OUT+ C693 470P Internal Speaker Connector P17 L J18 L OUT- Signal 5 +3V_ICH AOUT_R C717 4.7U 4 SPK_OFF Shut Down VR1 10K 7 Norm al LINE_OUT_5 11 From U17 1 LOW SPK_OFF 6 C718 4.7U HI 3 2 C204 220U Q16 DTC144TKA R166 10K 9 AOUT_L 8 2 +5VS C206 0.1U 18 7 5V_AMP L536 PLP3216S LINE_OUT_2 L523 120Z/100M 3 MUTE OUT SHUTDOWN From U15 front page L47 120Z/100M R548 22 L524 120Z/100M MUTE IN C689 100P R143 1K R122 1K 4 L537 L538 120Z/100M C688 100P L529 120Z/100M U18 1 J19 5 RVDD LVDD -DECT_HP/OPT Amplifier C168 0.1U C166 100U +3VS TPA0202 C708 2.2u R676 10k +3VS_SPD Q514 DTA144WK R665 15k Q515 DTA144TKA 5V_AMP -DEVICE_DECT 5 R664 10K C707 2.2u R675 10k C691 470P LLINE IN HP/LINE# LHP IN Line Out Phone Jack P17 R673 4.7K R659 4.7K R102 47K 4 SE/BTL# 7 8 9 5V_AMP R685 10K C692 680P L531 120Z/100M 4 2 3 1 14 16 SPDIFOUT From U15 front page R113 100K Q10 DTA144TKA 2 1 3 4 L527 L532 120Z/100M PLP3216S 174 8170 N/B MAINTENANCE 8.14 Audio Failure No sound from speaker after audio driver is installed. Audio Drive Failure Board-level Troubleshooting 1. Check if speaker cables are connected properly. 2. Make sure all the drivers are installed properly. Test OK? Yes Correct it. No No 1.If no sound cause of line out, check the following parts & signals: Parts: 1.Try another known good speaker, CD-ROM. 2. Exchange another known good charger board. Re-test OK? Replace Motherboard Check the following parts for cold solder or one of the following parts on the motherboard may be defective,use an oscilloscope to check the following signal or replace parts one at a time and test after each replacement. Yes Correct it. U15 X2 U510 U507 U17 U511 VR1 U18 C[707:710] R[664:667] C[691:694] L47 Q514 Q515 Q10 L[537:539] L523 L524 L528 L531 J[18:20] Signals: AOUT_R AOUT_L SPKROUT+ SPKROUTSPKLOUT+ SPKLOUTLINE_OUT_5 LINE_OUT_2 SPK_OFF SPDIFOUT 2. If no sound cause of MIC, check the following parts & signals: 3. If no sound cause of CD-ROM, check the following parts & signals: Parts: Signals: Parts: Signals: J16 J22 U15 L535 L525 C701 R148 R149 R669 U513 C194 R151 C209 R670 C686 MIC MIC_2 MIC_3 J10 R[132:134] R[140:142] C[191:193] CDROM_RIGHT CDROM_LEFT CDROM_COMM 175 8170 N/B MAINTENANCE 8.15 LAN Test Error An error occurs when a LAN device is installed. +3V L12 120Z/100M +3V_LAN AVDD_LAN L10 L9 L511 77,90,96 +3V_ICH R542 51 92 TXD+ U16 -PCIRST_MSK U17 R541 51 P16 R158 4.7K P13 1 2 Q15 3 VCC A 5 Y 4 B -PCIRST_N R31 0 C567 22P J9 C572 22P L508 PLP3216A 91 TXD- 1 2 4 3 AVDD_LAN TX+ 7 8 115 GNT P17 TD+ TD- TXRX+ 6 R15 0 RX- NC7S32 -PCIRST ICH2 AVDD_LAN C40 0.1U 10 PJTX+ 9 PJTX- 16 PJRX+ 15 PJRX- 8 7 6 3 U2 -CBE[0:3] 82801BA L513 PLP3216A 86 RXIN- AD[0:31],-PCI_REQ1,-PCI_GNT1 -PCI_IRDY,-PCI_TRDY,-FRAME U4 1 87 RXIN+ 4 R549 51 -DEVSEL,-STOP,-PCI_INTD R555 51 U508 H8 F3437 48 3 Q512 DTC144WK RTL8139CL LAN_WAKE 3 11 EECS PCICLK_LAN R32 0 116 MA0 MA1 XTALIN XTALOUT P15 U7 PC14410GHK PJ4 5 4 RD- 3 RDC 14 R17 75 R531 75 PJ7 2 1 C566 1000P RJ45 H0011 XFMR_H0009 3V_LAN MA2 U507 ICS950805 R530 75 C577 0.1U 83 1 R610 33 R12 75 RXC 2 P8 11 RD+ 2 C39 0.1U LANPHY P19 2 1 TXC -PCLKRUN 75 50 1 CS 49 2 SK U5 48 3 DI 93C468 4 47 DO VCC GND 8 5 C69 0.1u L8 PLP3216A 79 X501 25MHZ 78 1 3 L_AGND 2 C585 10P 4 C584 10P 176 8170 N/B MAINTENANCE 8.15 LAN Test Error An error occurs when a LAN device is installed. LAN Test Error 1.Check if the driver is installed properly. 2.Check if the notebook connect with the LAN properly. Test OK? Yes Board-level Troubleshooting Correct it. Replace Motherboard Check the following parts for cold solder or one of the following parts on the mother-board may be defective, use an oscilloscope to check the following signal or replace the parts one at a time and test after each replacement. No Parts: Check if BIOS setup is ok. Re-test OK? No Yes Correct it. U17 R158 R610 U4 R541 L508 C572 U5 C584 R17 J9 U508 U16 R32 L[8:10] R549 L513 C577 C69 C585 R530 Signals U507 Q512 R31 R542 R555 C567 C540 X501 R12 R31 -PCIRST_N -CBE[0:3] LAN_WAKE PCICLK_LAN PCLKRUN XTALIN XTLOUT RXINRXIN+ TXD+ TXDPJTX+ PJTXPJRX+ PJRXPJ4 PJ7 177 8170 N/B MAINTENANCE 9. Spare Parts List -- recommend (1) Category Part Number Description Remark Category Part Number Description CPU 324180786162 BFM-IPC;IC,CPU,WILLA 526267120029(1/15 Delete, PWA;PWA- 411671200004 PWA;PWA-8170,D/D BD,SMT The CPU not use in the part 8170,D/D SDRAM MODULE323767120001 BFM-IPC;DRAM MODULE, COVER ASSY 526267120029 BD,T/U LCD ASSY Remark 346671200011 INSULATOR;CD-ROM,M-B,8170 346671200036 INSULATOR,MDC,8170 413000020305 BFM-IPC;LCD,UB141X01 526267120014,17,29 340671200007 COVER ASSY;KB,8170 413000020281 LCD;14X13-102,TFT,14 526267120037 PCB;PWA-8170 442164900010 TOUCH PAD MODULE;TM41PD-350 TOUCHPAD BD 422665400002 FFC ASSY;TOUCH PAD,CASE KIT,VENU 421671200002 WIRE ASSY;UNIPAC,14. 526267120014,17,29 421671200001 WIRE ASSY;HYUNDAI,14 526267120037 HOUSING KIT 421671200007 WIRE ASSY;INVERTER,8170 340671200007 COVER ASSY; SPEAKER,8170 340671200002 COVER ASSY;8170 340671200006 COVER ASSY;RAM,8170 1/17 ECR:7939102700 delete 340671200025 COVER ASSY;RAM-1,8170 1/17 ECR:7939102700 add 340669900001 TILT UNIT;R,7170 340669900002 TILT UNIT;L,7170 340671200016 HOUSING ASSY;HANNSTER,14.1",LCD, 343671200003 PLATE;KEYBOARD,8170 344669900003 COVER;HINGE,7170 421669900007 WIRE ASSY;TOUCHPAD,7170 346664900010 FILM;LCD PROTEC,.14.2",235*300,5 421671200031 MICROPHONE ASSY;8170 BATT ASSY 526267120037 345671200001 RUBBER;LCD,UP,8170 340671200012 SPEAKER ASSY;R,8170 BD,T/U 340671200015 HOUSING ASSY;HYUNDAI 345669900004 RUBBER;LCD,DOWN,7170 340671200019 SPERKER ASSY;L,8170 8170,MOTHER 526267120014,17,29 341669900004 BRACKET;LCD,14.1",HYUNDAI,L,7170 340671200008 BRACKET ASSY;T-P,8170 PWA;PWA- 340671200017 HOUSING ASSY;UNIPAC, 340671200018 COVER ASSY;LCD,8170 421671200008 WIRE ASSY;MDC,8170 341669900003 BRACKET;LCD,14.1,HYU 340671200020 FAN ASSY;8170 412671200001 PCB ASSY;INVERTER BD,11P,8170,MS 1/22 add option(7939102656) 411671200001 PWA;PWA-8170,MOTHER BD 412671300001 PCB ASSY;D/A BD,SUMIDA,STINGRAY 1/22 add option(7939102656) 412155600047 PCB ASSY;MDM,56K,UNIV,F-PACK,WO/ PWA;PWA- 340671200003 HOUSING ASSY;8170 AC ADPT ASSY 442671200004 AC ADPT ASSY;19V/4.74A,DELTA,817 442671200001 BATT ASSY;11.1V/6AH,LI-,PANASONI 411671200007 PWA;PWA-8170,ESB BD 242670800113 BFM-WORLD MARK;WINXP,7521N 178 8170 N/B MAINTENANCE 9. Spare Parts List -- recommend (2) Category Part Number Description Remark HDD ASSY;30G 344669900010 CASE;HDD,7170 523467120012 BFM-IPC;HDD DRIVE,30 KBD AK;01-EN 526267120029 531066990001 KBD;86,US,K000918E1,7170 531020237308 KBD;87,FR,K000918F1, 526267120014 531020237307 KBD;87,GR,K000918F1, 526267120017,29 332810000033 PWR CORD;125V/7A,2P,BLACK,AMERIC 332810000034 PWR CORD;250V/2.5A,2 526267120017 332810000043 PWR CORD;250V/3A,2P, 526267120037 421015560001 CABLE ASSY;PHONE LINE,6P2C,W/Z C BEZEL ASSY;DVD ROM,QUANTA, 340669900046 BEZEL ASSY;DVD ROM,QUANTA,7170 343669900006 BRACKET;CD-ROM,7170 523430061901 DVD DRIVE;8X,SDR-081,H=12.7,QUAN 179 8170 N/B MAINTENANCE 9. Spare Parts List -- All (1) Part Number Description Location(s) Part Number Description Location(s) 441999900204 AC ADPT ASSY OPTION;8170 272075101701 CAP;100P ,50V ,+ -10%,0603,NPO,S C688,C689,PC528 442671200004 AC ADPT ASSY;19V/4.74A,DELTA,817 272075101701 CAP;100P ,50V ,+ -10%,0603,NPO,S C503,C504,C505,C506 541667120001 AK;01-EN,BOX,8170 272431105901 CAP;100U ,10V ,20%,7343,SMT PC1,PC3,PC8 541667120032 AK;EN,8170,UTILITY ONLY 272431107509 CAP;100U,2V,20%,7343,SDK-CAP C12,C28,PC572,PC573,PC57 441999900056 BATT ASSY OPTION;LI,9-CELL,8170 272075100701 CAP;10P ,50V ,+-10%,0603,NPO,SM C101,C107,C108,C117,C134, 442671200001 BATT ASSY;11.1V/6AH,LI-,PANASONI 272011106701 CAP;10U ,10V,+80-20%,1206,Y5V,S C10,C11,C13,C14,C15,C17,C 298000000002 BATTERY HOLDER;FOR CR2032,BH-800 BT1 272023106701 CAP;10U ,25V ,+80-20%,1210,Y5U, PC20,PC28,PC541,PC544 338530010018 BATTERY; LI,3V/220MAH,CR-2032 BT1 272075120301 CAP;12P ,CR,50V ,5% ,0603,NPO,S C211,C212 340669900046 BEZEL ASSY;DVD ROM,QUANTA,7170 272073180401 CAP;18P ,CR,25V ,10%,0603,NPO,S C556,C559 242670800113 BFM-WORLD MARK;WINXP,7521N 272071105701 CAP;1U ,CR,10V ,80-20%,0603,Y5 C122,C142,C160,C163,C164, 221669940001 BOX;AK,7170 272071105701 CAP;1U ,CR,10V ,80-20%,0603,Y5 PC2 340671200008 BRACKET ASSY;T-P,8170 272003105701 CAP;1U ,CR,25V ,+80%-20%,0805, C171,C522,C545,C681,PC518 343669900006 BRACKET;CD-ROM,7170 272003105701 CAP;1U ,CR,25V ,+80%-20%,0805, PC505 341669900005 BRACKET;LCD,14.1",HANNSTAR,R,717 272002225701 CAP;2.2U ,CR,16V ,+80-20%,0805,Y C183,C196,C622,C625,C646, 341669900004 BRACKET;LCD,14.1",HYUNDAI,L,7170 272012225702 CAP;2.2U ,CR,16V ,+80-20%,1206,Y C638,C65,C81 421015560001 CABLE ASSY;PHONE LINE,6P2C,W/Z C 272075222701 CAP;2200P,50V ,+/-20%,0603,X7R,S C531 421671000001 CABLE ASSY;USB FDD 272075221302 CAP;220P ,50V ,5% ,0603,NPO,SMT C523,C524,C546,C547,C704 272075103702 CAP;.01U ,50V,+80-20%,0603,SMT C562,C576,C60,PC32,PC500, 272075220701 CAP;22P ,50V ,+ -10%,0603,NPO,S C187,C197,C203,C205,C504, 272072473402 CAP;.047U,16V ,10%,0603,X7R,SMT C651 272021226701 CAP;22U ,10V,+80-20%,1210,Y5V,S C16,C49,C514,C552,C59,C61 272075104701 CAP;.1U ,50V,+80-20%,0603,SMT C103,C104,C105,C109,C110, 272043226501 CAP;22U ,25V ,+-20%,1812,Y5U,SMT PC505,PC506,PC507,PC513, 272075104701 CAP;.1U ,50V,+80-20%,0603,SMT C501,C502,C507,C512,C513, 272075271401 CAP;270P ,50V,+-10%,0603,X7R,SMT C199,C46,C93 272003683401 CAP;0.068U,CR,25V,10%,0805,X7R C701 272431337506 CAP;330U,4V,20%,7343,SMT PC7 272075102701 CAP;1000P,50V ,+/-20%,0603,X7R,S C1,C132,C141,C173,C174,C5 272432336506 CAP;33U,16V,+-20%,7343,POSCAP,SM C30,C31 272075102701 CAP;1000P,50V ,+/-20%,0603,X7R,S C1,C4,PC18,PC517,PC518 272421336501 CAP;33U,TT,8V,20%,3528,SMT C570,C571 272030102405 CAP;1000P,CR,3KV,10%,1808,X7R,TU C500,C502,C566 272001475701 CAP;4.7U ,CR,10V ,+80-20%,0805,Y C125,C131,C153,C208,C35,C 180 8170 N/B MAINTENANCE 9. Spare Parts List -- All (2) Part Number Description Location(s) Part Number Description Location(s) 272012475701 CAP;4.7U ,CR,16V ,+80-20%,1206,Y C182,C54,C587 291000142404 CON;FPC/FFC,24P,1MM,H8.2,ST,ACES J12 272012475701 CAP;4.7U ,CR,16V ,+80-20%,1206,Y PC501,PC511,PC514 291000150804 CON;FPC/FFC,8P,1MM,R/A,2CONTAC,E J500 272075471401 CAP;470P ,50V,10%,0603,X7R,SMT C611,C691,C692,C693,C694, 331040020004 CON;HDR,FM,10P*2,2.54MM,R/A,H8,4 J3 272075471401 CAP;470P ,50V,10%,0603,X7R,SMT PC20 331030044013 CON;HDR,FM,22*2,2MM,ST,C16805 272075470701 CAP;47P ,50V ,+ -10%,0603,NPO,S C136,C139,C143,C149,C680, 331040050011 CON;HDR,FM,25P*2,1.27MM,R/A,HSG J6 272075509801 CAP;5P ,CR,50V,+ -.5PF,0603,NP C617,C618 291000011024 CON;HDR,FM,5P*2,1.27MM,ST,H4.5,S J501 272075680302 CAP;68P ,50V ,5% ,0603,NPO,SMT C630,C633 331040020005 CON;HDR,MA,10P*2,2.54MM,R/A,H8.4 PJ1 221668950010 CARD BOARD,BTM,PALLET,M722 291000011209 CON;HDR,MA,12P*1,1.25,ST,SMT J6 221669950008 CARD BOARD;FRAME,PALLET,7170 291000024409 CON;HDR,MA,22P*2,2MM,R/A,SMT,ALL J14 221669950006 CARD BOARD;TOP,PALLET,7170 331040050009 CON;HDR,MA,25P*2,1.27MM,R/A,HSG PJ2 221671220002 CARTON;NON-BRAND,MSL,8170 331040050010 CON;HDR,MA,50P,0.8MM,R/A,H1.1 J10 431671200001 CASE KIT;8170 291000011027 CON;HDR,MA,5P*2,1.27MM,ST,H17.5, J5 344669900010 CASE;HDD,7170 291000020303 CON;HDR,SHROUD,MA,3P,1.25MM,R/A, J502 451669900051 CD ROM ME KIT;24X,7170 291000256823 CON;IC CARD PART;68P,0.635,H5,SM J8 273000500052 CHOKE COIL;0.7UH,1.6mOHM,25%,20A PL1,PL2 331000004018 CON;IEEE1394,MA,4P,.8MM,R/A,LINK J21 273000500053 CHOKE COIL;10UH,21.6mOHM,5.4A PL7 331870004017 CON;MINI DIN,4P,R/A,W/GROND,C108 J4 273000500053 CHOKE COIL;10UH,21.6mOHM,5.4A PL1 331810006044 CON;PHONE JACK,6P2C,H11.5,RJ11,T J13 273000111004 CHOKE COIL;160OHM/100MHZ,25%,321 L23,L24,L508,L513,L532,L53 291000810806 CON;PHONE JACK,8P8C,SMD,RJ45 J9 273000111004 CHOKE COIL;160OHM/100MHZ,25%,321 L2,L3 331840010005 CON;POF MINI JACK,10P,W/SPDIF,2F J19 273000500015 CHOKE COIL;50UH(REF),D.4*2,5.5T, L1 331910003039 CON;POWER JACK,3P,D=2.0,SINGATRO J5 331000007009 CON;BAT,7P,2.5MM,CENLINK J28 331840005013 CON;STEREO JACK,5P,R/A,28MF60-07 J22 331720015006 CON;D,FM,15P,2.29,R/A,3ROW J1 331000004025 CON;USB,MA,R/A,4P*1,2MM,85116-40 J2,J3 331720025005 CON;D,FM,25P,2.775,R/A J1 291000410201 CON;WFR,MA,2P,1.25,ST,SMT/MB J16,J18,J20,J4 291000153006 CON;FPC/FFC,15P*2,.8MM,BD/BD,ST, J11 291000410301 CON;WFR,MA,3P,1.25,ST,SMT/MB J7 291000144004 CON;FPC/FFC,20P*2,1.0MM,H=4.6,ST J2 291000410401 CON;WFR,MA,4P,1.25MM,ST,SMT J501 181 8170 N/B MAINTENANCE 9. Spare Parts List -- All (3) Part Number Description 291000410401 CON;WFR,MA,4P,1.25MM,ST,SMT Location(s) J15 Part Number Description Location(s) 288100112003 DIODE;EC11FS2-TE12L,SCHOTTKY,200 D500 345669600065 CONDUCTIVE TAPE;MB,SDRAM,RACE 288100112003 DIODE;EC11FS2-TE12L,SCHOTTKY,200 PD1 340671200007 COVER ASSY; SPEAKER,8170 288103103001 DIODE;EC31QS03L,30V,3A,SMT PD1,PD2,PD4,PD5,PD6 340671200002 COVER ASSY;8170 288103103001 DIODE;EC31QS03L,30V,3A,SMT PD4,PD5,PD6 340671200001 COVER ASSY;ID1,8170 288104148001 DIODE;RLS4148,200MA,500MW,MELF,S D5,D7 340671200009 COVER ASSY;KB,8170 288100024002 DIODE;RLZ24D,ZENER,23.63V,5%,SMT PD501 340671200018 COVER ASSY;LCD,8170 288100036001 DIODE;RLZ3.6B,ZENER,3.45V,5%,SMT D8 340671200006 COVER ASSY;RAM,8170 288100056005 DIODE;UDZ5.6B,ZENER,5.6V,UMD2,SM PD7 344671000001 COVER;FOR 7170;USB FDD 344670500042 DUMMY CARD;PCMCIA,TETRA 344669900003 COVER;HINGE,7170 523430061901 DVD DRIVE;8X,SDR-081,H=12.7,QUAN 272625220401 CP;22P*4 ,8P,50V ,10%,1206,NPO,S CP500,CP501,CP502,CP503, 523467120011 DVD ROM ASSY;8X,SDR-081,QUANTA,8 291006214438 DIMM SOCKET;144P,.8MM,H4,SX6E,HR J505 272602107501 EC;100U,16V,M,6.3*5.5,-55+85'C,S C166 291006214439 DIMM SOCKET;144P,.8MM,H4,SX6ER,H J503 312271006358 EC;100U,25V,RA,M,D6.3*7,SGX,SANY PC18,PC23,PC46,PC47 288100032013 DIODE;BAS32L,VRRM75V,MELF,SOD-80 PD503 312271006358 EC;100U,25V,RA,M,D6.3*7,SGX,SANY PC11,PC19,PC4,PC5,PC9 288100032013 DIODE;BAS32L,VRRM75V,MELF,SOD-80 D501 272601227501 EC;220U ,10V,M,6.3*7.7,-15+105', C204,C210 288100054001 DIODE;BAT54,30V,200mA,SOT-23 D10,D16 312278206152 EC;820U ,4V,+-20%,10X10.5,FPCAP PC3,PC5,PC6,PC7 288100701002 DIODE;BAV70LT1,70V,225MW,SOT-23 D509,D510 227669900005 END CAP; HEATSINK, AK BOX,7170 288100701002 DIODE;BAV70LT1,70V,225MW,SOT-23 PD2,PD3 227671200001 END CAP;8170 288100099001 DIODE;BAV99,70V,450MA,SOT-23 D1,D3,D4,D6 227669900004 END CAP;BATTERY,7170 288100099001 DIODE;BAV99,70V,450MA,SOT-23 D501,D502,D503,D504,D505 227669900002 END CAP;FDD,FRAME,7170 288100099001 DIODE;BAV99,70V,450MA,SOT-23 D502,D503 227669900003 END CAP;FDD,T/B,7170 288100056003 DIODE;BAW56,70V,215MA,SOT-23 PD500,PD502 481671200002 F/W ASSY;KBD CTRL,8170 U508 288100056003 DIODE;BAW56,70V,215MA,SOT-23 PD502 481671200001 F/W ASSY;SYS/VGA BIOS,8170 U12 288101003001 DIODE;EC10QS03L,30V,1A,SMT D508,D513 340671200020 FAN ASSY;8170 288101003001 DIODE;EC10QS03L,30V,1A,SMT PD503,PD504 523411442052 FD DRIVE;1.44M,3.5",D353FU,MITSU 182 8170 N/B MAINTENANCE 9. Spare Parts List -- All (4) Part Number Description Location(s) Part Number Description Location(s) 523499993004 FDD DRIVER OPTION;EXT. FDD,7170 283466570001 IC;EEPROM,9346,64*16 BITS,SO8,SM U5 523467100002 FDD KIT;D353FUE,FOR 7170,USB,MSL 283400000003 IC;EEPROM,NM24C02N,2K,SO,8P U9 273000610008 FERRITE ARRAY;120OHM/100MHZ,TKIN FA501 283450083002 IC;FLASH,512K*8-70,PLCC32,ST39SF 273000610014 FERRITE ARRAY;60OHM/100MHZ,3216, FA500 284583437003 IC;H8/F3437S,KBD CTRL,TQFP,100P, 273000610014 FERRITE ARRAY;60OHM/100MHZ,3216, RP1,RP2,RP3,RP4 284582801027 IC;ICH2,82801BA,BGA421 U17 273000130019 FERRITE CHIP;120OHM/100MHZ,1608, L500,L501,L502,L520,PL8 284595080001 IC;ICS950805,200MHZ,TSSOP56 U507 273000130019 FERRITE CHIP;120OHM/100MHZ,1608, L508,L510 286100393004 IC;LMV393,DUAL COMPARTOR,SSOP,8P PU513 273000150013 FERRITE CHIP;120OHM/100MHZ,2012, L505,PL10,PL11,PL14,PL15, 286302951015 IC;LP2951ACM,VOLTAGE REGULATOR,S PU7 273000150013 FERRITE CHIP;120OHM/100MHZ,2012, L1,L4,L507,L509,PL2,PL3,PL 286329510001 IC;LP2951CM-3.3,VOLTAGE REGULATO PU510 273000130039 FERRITE CHIP;130OHM/100MHZ,1608, L10,L11,L12,L13,L14,L15,L1 286317099001 IC;LTC1709-9,PWM,QSOP,36P PU508 273000130039 FERRITE CHIP;130OHM/100MHZ,1608, L502,L503,L504,L505 286301632002 IC;MAX1632CAI,PWM CTRL,SSOP,28P PU1 273000130038 FERRITE CHIP;600OHM/100MHZ,1608, L523,L524,L525,L527,L528,L 286301772001 IC;MAX1772,PWM,QSOP,28P PU511 273000150022 FERRITE CHIP;60OHM/100MHZ,2012,S L17,L18,L19 286133078001 IC;MC33078D,LOW NOISE OP AMP.,SO U513 273000150022 FERRITE CHIP;60OHM/100MHZ,2012,S L501 286305248002 IC;MIC 5248-1.2BM5,LV12,LDO REG, U501 422665400002 FFC ASSY;TOUCH PAD,CASE KIT,VENU 284500006003 IC;MOBILTY RADEON M6-D,BGA484 U516 346664900010 FILM;LCD PROTEC,.14.2",235*300,5 281300732001 IC;NC7S32,SINGLE OR GATE,SC70-5 U16,U510 341671200009 FINGER;EMI GROUND SMD FINGER,H=2 E1,E2,E3,E4,E5,E500,E502,E 281307085001 IC;NC7SZ08P5,2-INPUT & GATE,SC70 U8 341671200010 FINGER;EMI GROUND SMD FINGER,H=4 E501,E509,E510,E513 286307805010 IC;NJM78L05UA,VOL REGULATOR,SOT, U511 341671200010 FINGER;EMI GROUND SMD FINGER,H=4 E501 286302040002 IC;P2040B,LCD PANEL EMI,S0,8P U503 342600001203 FINGER;EMI GROUNDING SMD FINGER, E514,E515 284501284001 IC;PAC1284-01Q,TERMIN. NETWK,QSO U501,U502 288003600001 FIR;HSDL3600#007,FRONT VIEW,10P, U1 284587393002 IC;PC87393F,TQFP,100P U509 295000010044 FUSE;1.1A/6V,POLY SWITCH,1210,SM F500,F501,F502 284504410005 IC;PCI4410A,CARDBUS/OHCI,uBGA,20 U7 295000010016 FUSE;NORMAL,6.5A/32VDC,3216,SMT PF1,PF2 286309701001 IC;RT9701,POWER DISTRI SW,SOT23- U2 295000010016 FUSE;NORMAL,6.5A/32VDC,3216,SMT PF501 286300431014 IC;SC431LCSK-.5,.5%,ADJ REG,SOT2 PQ3,PQ510,Q505 286300055001 IC;TC55,3.3V,250mA,REG.,SOT89 PU8 346671200026 GASKET;1394,M/B,8170 183 8170 N/B MAINTENANCE 9. Spare Parts List -- All (5) Part Number Description Location(s) Part Number Description 286100202001 IC;TPA0202,AUDIO AMP,2W,TSSOP,24 U18 242669900005 LABEL;LCD SIDE,7170 286302211001 IC;TPS2211,POWER DISTRI SW,SSOP1 U504 242600000195 LABEL;SOFTWARE,INSYDE BIOS-M 284500411001 IC;TSB41AB1,1394 PHY,PQFP,64P U14 441671200004 LCD ASSY;HANNSTAR,SXGA+,14.1",81 273000114002 INDUCTER;4.7UH,10%,1206,SMT L509,L512 451671200004 LCD ME KIT;HANNSTAR,SXGA+,14.1", 273000990023 INDUCTOR;10UH,CDRH125B,SMT PT1 413000020290 LCD;HSD141PK11-A,TFT,14.1",SXGA+ 273000150106 INDUCTOR;4.7UH,10%,2012,SMT L2,L3 294011200001 LED;GRN,H1.5,0805,PG1102W,SMT Location(s) D11,D12,D13,D14,D15 346671200036 INSULATOR,MDC,8170 344671000003 LENS;HOUSING,USB FDD 346671200011 INSULATOR;CD-ROM,M-B,8170 526267120001 LTXNX;8170/4BCI/30C/1US1/18D3A/X 346668300024 INSULATOR;DIMM P/N MB TOP,HOPE 561567120001 MANUAL KIT;EN,8170,N-B 346669900004 INSULATOR;INVERTER,7170 561567120013 MANUAL;USER'S,EN,8170,N-B 346671200007 INSULATOR;PCMCIA,8170 421671200031 MICROPHONE ASSY;8170 346671200008 INSULATOR;RTC,8170 416267120004 NB PF;HANNSTAR,SXGA+,14.1",8170 531099990101 KBD OPTION;86,US,7170 375102030010 NUT-HEX;M2,2,NIW 531066990001 KBD;86,US,K000918E1,7170 375120262008 NUT-HEX;M2.6,NCG 451671200052 LABEL KIT;N-B,8170 461671200002 PACKING KIT;N-B,8170 242600000145 LABEL;10*10,BLANK,COMMON 227669900006 PAD;LCD/KB,ANIT-STATIC,7170 242600000145 LABEL;10*10,BLANK,COMMON 221669950004 PARTITION;A,PALLET,7170 242662300009 LABEL;25*10MM,3020F 221669950001 PARTITION;AK BOX,7170 242600000378 LABEL;27*7MM,HI-TEMP 260'C 221669950005 PARTITION;B,PALLET,7170 242671200004 LABEL;AGENCY-GLOBAL,MSL,8170 412671200001 PCB ASSY;INVERTER BD,11P,8170,MS 242600000157 LABEL;BAR CODE,125*65,COMMON 412155600047 PCB ASSY;MDM,56K,UNIV,F-PACK,WO/ 242669900012 LABEL;BAR CODE,32x11MM,7170 316671200003 PCB;PWA-8170 TOUCHPAD BD R01 242600000433 LABEL;BLANK,11*5MM,COMMON 316671200002 PCB;PWA-8170/DD BD R01 242669900009 LABEL;BLANK,60*80MM,7170 316671200005 PCB;PWA-8170/ESB BD R01 242664800013 LABEL;CAUTION,INVERT BD,PITCHING 316671200001 PCB;PWA-8170/M BD R01 184 8170 N/B MAINTENANCE 9. Spare Parts List -- All (6) Part Number Description Location(s) Part Number Description 286100202001 IC;TPA0202,AUDIO AMP,2W,TSSOP,24 U18 242669900005 LABEL;LCD SIDE,7170 286302211001 IC;TPS2211,POWER DISTRI SW,SSOP1 U504 242600000195 LABEL;SOFTWARE,INSYDE BIOS-M 284500411001 IC;TSB41AB1,1394 PHY,PQFP,64P U14 441671200004 LCD ASSY;HANNSTAR,SXGA+,14.1",81 273000114002 INDUCTER;4.7UH,10%,1206,SMT L509,L512 451671200004 LCD ME KIT;HANNSTAR,SXGA+,14.1", 273000990023 INDUCTOR;10UH,CDRH125B,SMT PT1 413000020290 LCD;HSD141PK11-A,TFT,14.1",SXGA+ 273000150106 INDUCTOR;4.7UH,10%,2012,SMT L2,L3 294011200001 LED;GRN,H1.5,0805,PG1102W,SMT Location(s) D11,D12,D13,D14,D15 346671200036 INSULATOR,MDC,8170 344671000003 LENS;HOUSING,USB FDD 346671200011 INSULATOR;CD-ROM,M-B,8170 526267120001 LTXNX;8170/4BCI/30C/1US1/18D3A/X 346668300024 INSULATOR;DIMM P/N MB TOP,HOPE 561567120001 MANUAL KIT;EN,8170,N-B 346669900004 INSULATOR;INVERTER,7170 561567120013 MANUAL;USER'S,EN,8170,N-B 346671200007 INSULATOR;PCMCIA,8170 421671200031 MICROPHONE ASSY;8170 346671200008 INSULATOR;RTC,8170 416267120004 NB PF;HANNSTAR,SXGA+,14.1",8170 531099990101 KBD OPTION;86,US,7170 375102030010 NUT-HEX;M2,2,NIW 531066990001 KBD;86,US,K000918E1,7170 375120262008 NUT-HEX;M2.6,NCG 451671200052 LABEL KIT;N-B,8170 461671200002 PACKING KIT;N-B,8170 242600000145 LABEL;10*10,BLANK,COMMON 227669900006 PAD;LCD/KB,ANIT-STATIC,7170 242600000145 LABEL;10*10,BLANK,COMMON 221669950004 PARTITION;A,PALLET,7170 242662300009 LABEL;25*10MM,3020F 221669950001 PARTITION;AK BOX,7170 242600000378 LABEL;27*7MM,HI-TEMP 260'C 221669950005 PARTITION;B,PALLET,7170 242671200004 LABEL;AGENCY-GLOBAL,MSL,8170 412671200001 PCB ASSY;INVERTER BD,11P,8170,MS 242600000157 LABEL;BAR CODE,125*65,COMMON 412155600047 PCB ASSY;MDM,56K,UNIV,F-PACK,WO/ 242669900012 LABEL;BAR CODE,32x11MM,7170 316671200003 PCB;PWA-8170 TOUCHPAD BD R01 242600000433 LABEL;BLANK,11*5MM,COMMON 316671200002 PCB;PWA-8170/DD BD R01 242669900009 LABEL;BLANK,60*80MM,7170 316671200005 PCB;PWA-8170/ESB BD R01 242664800013 LABEL;CAUTION,INVERT BD,PITCHING 316671200001 PCB;PWA-8170/M BD R01 185 8170 N/B MAINTENANCE 9. Spare Parts List -- All (7) Part Number Description Location(s) Part Number Description Location(s) 271071270301 RES;27 ,1/16W,5% ,0603,SMT R502 271071562301 RES;5.6K ,1/16W,5% ,0603,SMT R582,R71 271071301011 RES;301 ,1/16W,1% ,0603,SMT R5,R537 271071511812 RES;51.1,1/16W,1% 0603,SMT R507,R508,R510,R512,R513, 271071301311 RES;301K ,1/16W,1% ,0603,SMT PR562 271071560301 RES;56 ,1/16W,5% ,0603,SMT R103,R105,R106,R115 271071330302 RES;33 ,1/16W,5% ,0603,SMT PR557,R55,R56,R585,R586,R 271071561101 RES;560 ,1/16W,1% ,0603,SMT PR20 271071334301 RES;330K ,1/16W,5% ,0603,SMT R689 271071634111 RES;6.34K,1/16W,1% ,0603,SMT R104 271071333101 RES;33K ,1/16W,1% ,0603,SMT PR547 271071682301 RES;6.8K ,1/16W,5% ,0603,SMT PR519,R151,R24,R27,R550,R 271071333301 RES;33K ,1/16W,5% ,0603,SMT R4,R5 271071620102 RES;62,1/16W,1% 0603,SMT R2,R3,R506,R517 271071374211 RES;37.4K,1/16W,1% ,0603,SMT PR15 271071681101 RES;680 ,1/16W,1% ,0603,SMT R522 271071390302 RES;39 ,1/16W,5% ,0603,SMT R521 271071683301 RES;68K ,1/16W,5% ,0603,SMT R148 271071472101 RES;4.7K ,1/16W,1% ,0603,SMT PR23,PR24,PR572,R158,R19 271071750302 RES;75 ,1/16W,5% ,0603,SMT R12,R17,R514,R530,R531 271071499111 RES;4.99K,1/16W,1% ,0603,SMT PR18,R124,R587 271071822301 RES;8.2K ,1/16W,5% ,0603,SMT R107,R108,R117,R118,R154, 271071402811 RES;40.2 ,1/16W,1% ,0603,SMT R16,R8,R82 271071841101 RES;845 ,1/16W,1% ,0603,SMT R533 271071402311 RES;402K ,1/16W,1% ,0603,SMT PR568 271611000301 RP;0*4 ,8P ,1/16W,5% ,0612,SMT RP521 271071432211 RES;43.2K,1/16W,1% ,0603,SMT PR571 271611103301 RP;10K*4 ,8P ,1/16W,5% ,0612,SMT RP508 271071470301 RES;47 ,1/16W,5% ,0603,SMT R581 271611102301 RP;1K*4 ,8P ,1/16W,5% ,0612,SMT RP510 271071471302 RES;470 ,1/16W,5% ,0603,SMT R156,R157,R682,R683,R684, 271621102302 RP;1K*8 ,10P,1/32W,5% ,1206,SMT RP2,RP505 271071474301 RES;470K ,1/16W,5% ,0603,SMT PR16,R1,R501,R642,R646 271611330301 RP;33*4 ,8P ,1/16W,5% ,0612,SMT RP518 271071474301 RES;470K ,1/16W,5% ,0603,SMT PR4,PR5,PR506 271611472301 RP;4.7K*4,8P ,1/16W,5% ,0612,SMT RP511 271071475011 RES;475 ,1/16W,1% ,0603,SMT R619 271611473301 RP;47K*4 ,8P ,1/16W,5% ,0612,SMT RP520 271071475311 RES;475K ,1/16W,1% ,0603,SMT PR564 271621473301 RP;47K*8 ,10P,1/16W,5% ,1206,SMT RP512,RP515 271071473301 RES;47K ,1/16W,5% ,0603,SMT PR553,R102,R42,R43,R579,R 271611682301 RP;6.8K*4,8P ,1/16W,5% ,0612,SMT RP1,RP506,RP507,RP509 271071473301 RES;47K ,1/16W,5% ,0603,SMT PR9,R3,R6 271611750301 RP;75*4 ,8P ,1/16W,5% ,0612,SMT RP501 271071499811 RES;49.9 ,1/16W,1% ,0603,SMT R520,R527,R528,R529,R535, 271611750301 RP;75*4 ,8P ,1/16W,5% ,0612,SMT RP501 271071499211 RES;49.9K,1/16W,1% ,0603,SMT PR516,PR542 271621822302 RP;8.2K*8,10P,1/32W,5% ,1206,SMT RP15,RP16,RP17,RP18 271071499011 RES;499 ,1/16W,1% ,0603,SMT R14 345671000001 RUBBER FOOT;HOUSING,USB FDD 186 8170 N/B MAINTENANCE 9. Spare Parts List -- All (8) Part Number Description Location(s) Part Number Description Location(s) 345669900004 RUBBER;LCD,DOWN,7170 370103010405 SPC-SCREW;M3L4,NIW,K-HD,T0.3 345671200001 RUBBER;LCD,UP,8170 370103010604 SPC-SCREW;M3L6,NIB,K-HD,t0.8,NYL 565167120001 S/W;CD ROM,SYSTEM,8170 340671200012 SPEAKER ASSY;R,8170 565180626001 S/W;CD*1,DVD,WIN-DVD,INTERVIDEO 340671200019 SPERKER ASSY;L,8170 340671200013 SCREW ASSY;CPU,8170 377244010002 STANDOFF;#4-40DP3.5H5L5.5,NIW 340671200014 SCREW ASSY;IC,82845,8170 341668300008 STANDOFF;MDC MODEM,NLK,HOPE 371102011502 SCREW;M2L15,FLT(+),NIW/NLK 297040105012 SW;PUSH BUTTOM,4P,SP,12V/50MA,H2 SW1,SW2,SW3,SW4,SW5,SW6 323760000002 SDRAM MODULE;256M,8M*16,PC133,SP 297040105010 SW;PUSH BUTTOM,5P,SPST,12V/50MA, SW1,SW2,SW3,SW4 340671200005 SHIELDING ASSY;TOP,8170 297030105003 SW;TOGGLE,SPST,5V/1mA,MPU-101-80 SW6 561860000022 SINGLE PAGE;GN,NOTE FOR BATTERY& 346671200002 THERMAL PAD;HEATSINK,CPU,8170 370102610302 SPC-SCREW;M2.6L3,NIB,K-HD,NYLOK 310111103012 THERMISTOR;10K,1%,RA,0603,1P 370102610405 SPC-SCREW;M2.6L4,NIW,K-HD,t=0.8, 340669900002 TILT UNIT;L,7170 370102610405 SPC-SCREW;M2.6L4,NIW,K-HD,t=0.8, 340669900001 TILT UNIT;R,7170 370102630601 SPC-SCREW;M2.6L6,HDt0.5,NIWNLK 442164900010 TOUCH PAD MODULE;TM41PD-350 370102610805 SPC-SCREW;M2.6L8,K-HD,NIW/NLK 288227002001 TRANS;2N7002LT1,N-CHANNEL FET PQ500,PQ501,PQ506,PQ507 370102010205 SPC-SCREW;M2L2(t0.3),N/W/WLK 288227002001 TRANS;2N7002LT1,N-CHANNEL FET PQ1,PQ3 370102010256 SPC-SCREW;M2L2.5,K-HD(t0.5) NLK, 288203400001 TRANS;AO3400,N-MOSFET,SOT-23 Q13,Q503 370102010256 SPC-SCREW;M2L2.5,K-HD(t0.5) NLK, 288203401001 TRANS;AO3401,P-MOSFET,SOT-23 PQ1,PQ512,Q1,Q509 370102010309 SPC-SCREW;M2L3.0,NIW/NLK,HD07 288204400001 TRANS;AO4400,N-MOSFET,SO-8 PU13,Q500,U505 370102010407 SPC-SCREW;M2L4,K-HD,NIB/NLK 288204400001 TRANS;AO4400,N-MOSFET,SO-8 PU501,PU504 370102010405 SPC-SCREW;M2L4,NIW,K-HD(+),NYLOK 288200144002 TRANS;DTA144WK,PNP,SMT Q514 370102010405 SPC-SCREW;M2L4,NIW,K-HD(+),NYLOK 288200144003 TRANS;DTC144TKA,N-MOSFET,SOT-23 PQ511,Q10,Q15,Q2,Q506,Q5 370102010608 SPC-SCREW;M2L6,KD,HDψ 3 ,NIB/NL 288200144001 TRANS;DTC144WK,NPN,SOT-23,SMT PQ2,PQ509,Q12,Q14,Q3,Q4, 370102010606 SPC-SCREW;M2L6,K-HD(t0.2),NIB/NL 288200302001 TRANS;FDV302P,P-CHANNEL,SOT23 Q7 370102010605 SPC-SCREW;M2L6,NIW,HDT=0.4,779 288203906018 TRANS;MMBT3906L,PNP,Tr35NS,TO236 PQ505 R4 187 8170 N/B MAINTENANCE 9. Spare Parts List -- All (9) Part Number Description Location(s) 288202303001 TRANS;SI2303DS,P-MOSFET,SOT-23 PQ2 288104362001 TRANS;SI4362DY,N-HOSFET,S08 PU1,PU2,PU501,PU502,PU5 288204800001 TRANS;SI4800DY,N-MOS,.0185OHM,SO PU5 288204800001 TRANS;SI4800DY,N-MOS,.0185OHM,SO PU503,PU506 288204832001 TRANS;SI4832DY,N-MOSFET,.028OHM, PU6 288204832001 TRANS;SI4832DY,N-MOSFET,.028OHM, PU502,PU505 288204835001 TRANS;SI4835DY,PMOS,6A/30V,.035, PU10,PU11,PU512,PU9 288204835001 TRANS;SI4835DY,PMOS,6A/30V,.035, PQ502,PQ503 288204892001 TRANS;SI4892DY,N-MOSFET,SO8 PU500,PU503,PU506,PU507 273001050065 TRANSFORMER;10/100 BASE,LF-H72P, U2 373101710301 T-SCREW;I,M1.7,L3,K-HD,D3.0,NIB 373002010002 T-SCREW;S.M2 L4, PAN(+),NIW 373002010003 T-SCREW;S.M2 L5, PAN(+),NIW 270140000003 VARISTOR;280V,5.6X3.8MM,TVB280-0 S500 271911103906 VR;10K,20%,0.05W,RN101GAC10KPGJ- VR1 421671200004 WIRE ASSY;HANNSTAR,14.1",SXGA,LC 421671200007 WIRE ASSY;INVERTER,8170 421671200008 WIRE ASSY;MDC,8170 421669900007 WIRE ASSY;TOUCHPAD,7170 274011431408 XTAL;14.318M,50PPM,32PF,7*5,4P,S X502 274011600408 XTAL;16MHZ,16PF,50PPM,8*4.5,2P X503 274012457406 XTAL;24.576MHZ,16PF,50PPM,8*4.5, X1,X2 274012500401 XTAL;25MHZ,30PPM,18PF,4P,SMT X501 274012700401 XTAL;27MHZ,20PPM,16PF,7*5,4P,SMT X500 274013276114 XTAL;32.768KHZ,10PPM,12.5PF X3 188 A MODEL : 8170 B Revision 02 Contexts Page Title History of Schematics Revision 0A (EVT) Cover Sheet 1 System Block Diagram 2 Power Block Diagram 3 P4-CPU (1/2) 4 P4-CPU (2/2) 5 BROOKDALE-MCH845(1/2) 6 BROOKDALE-MCH845(2/2) 7 Clock Generator,Screw holes 8 Revision 0B (DVT) SO-DIMM Memory X 2 9 1.ADD DIODE FOR S.B +5VS DRAIN. 1.ADD 1UF FOR ADM1021A Temperature Monitor. 2.DEL EMAIL BTN SW5 AND D16 LED INCICATOR. 3.+1.8VA CHANGE (+1.8V_ICH) FOR ICH2. 4.+3VA CHANGE (+3V_ICH) FOR ICH2. 5.-PCIRST CONTROL HDD & CD_ROM RESET,CHANGE VON GPIO PIN EACH RESET FOR S3 WEAKUP. 6.ADD TWO 10K PULL_UP RESISTOR FOR H8 THERMAL SENSE ,TWO FAN FREEBACK SCHEMATIC. 7.ADD U515 & CHANGE J5 FOR 8170 QK/B AND 8175 LED/B COMMON. 8.ADD -LID PIN ON J6 FOR 8175 COVER SWITCH. 9.MODIFY TOUCH_PAD +5VS CHANGE +5VS. 10.MODIFY LANPHY +3VS CHANGE +3V. 11.MODIFY ICH2 +5VA CHANGE +5V. 2 2 12.MODIFY RTC CIRCUITRY +3VA CHANGE +5VA VON 330K & 1M DIVIDER. 2.ADD C717 &C718 (4.7U) for boot time "popo"tone. VGA-M6(1/2) 10 3.ADD R162 modify 2M BIOS pull +5VS. VGA-M6(2/2) 11 5.ADD 1U CAP for inverter RED too light. LCD & CRT Interface 12 7.MDC modify to digital GND. ICH2 13 9.Second fan modify connect Vertical to Horizontally. HDD, CDROM Connector & PULL-UP RESISTER 14 PCMCIA/1394 Controller(PCI4410) & Socket 15 LANPHY,MDC 16 Audio Codec & Amplifier 17 TOUCH PAD,BIOS,SUPER-IO 18 4.Change SDRAM Q8 for IO_DATA ram module. 6.IEEE1394 modify 1394_GND of digital GND for ESD issue. 8.Modify FAN feedback +5V change +5VS and FAN control pin modify +5VS change +5V. Revision 01 (PVT) 1.CHANGE CAP 0.068U OF 0603 TO 0805. 2.LAN OF MA8(PIN61) PULL HI +3V. 3.R163,R164,R696,R697,L535 CHANGE OF DFS FOR COST DOWN. 4.AMP(MUTE IN) ADD PULL HI +5VS. 5.LCD CONNECT PROVISION 5P CAP. POWER STATES Micro Controller(H8) 19 Battery Connector &3V,5V-RESUME POWER 20 -SUSB - HIGH CPU Vcore,1.8V,1.5V 21 -SUSC - HIGH DC-DC CONNECTOR,CHARGER 22 SIGNAL ADP BATTERY DRAW DESIGN CHECK ISSUED FULL ON STD MEC-OFF LOW LOW LOW HIGH LOW LOW STR +19V O O O O +12V O O O O O O O RTC_VCC +3.3V O CPU_CORE +1.75V O X X X +1.8V O X X X +1.8V_ICH +1.8V O O X X VDDR_MEM2.5 +2.5V O X X X O X X X +1.8VS 1 VOTAGE +3VS +3.3V +3V +3.3V BUS MASTER IDSEL STATE O O X X +3V_ICH +3.3V O O X X +5VS +5V O X X X +5V +5V O O X X +5VA +5V O O 0 0 +12VS +12V O X X X +12V +12V O O X X REMARK CHIP IDSEL AD18 AD11 AD18 AD19 REQ/GNT -REQ0/-GNT0 -REQ1/-GNT1 -REQ2/-GNT2 -REQ3/-GNT3 -REQ4/-GNT4 LAN PCMCIA CHIP PCMCIA LAN NU NU PCIINT PCIINT INTA INTC INTH INTD CHIP PCMCIA/ATI VGA PCMCIA/1394 USB2 USB1/LAN 1 COMP 2 GND 3 IN-1 4 GND 5 POWER 6 IN-2 7 GND 8 SOLDER 1 Title Cover Sheet Size C Date: A B Document Number Rev 02 411671200001 Friday, December 28, 2001 Sheet 1 of 22 A B 8170 System Block Diagram Pentium 4 Willamette/Northwood C.P.U. ADM 1021 Micro-FCPGA 478 pin SSOP 16 DDC VSYNC HSYNC R G B CRT PCI 4410 TSB41AB1 PCMCIA/1394 LINK CONTROLLER TI PQFP64 Brookdale AGP BUS 4X C MD[0..63] MCH MA[0..14] BGA 484 BGA 593 DRAM Control LVDS DATA Control AD[0..31] 14.1"/15.1" RTL8139CL LQFP 128 USB0 3 Control HUB[0..11] RJ45 HUB LINK 13 Control Control AD[0..31] PCI BUS AD[0..31] MINI 1394 Controller 0 USB1 3 External Microphone Controller 1 Internal Microphone Intel 82801BA PD[0..15] 16 SD[0..15] Internal Speaker ICH2 Control AC Link BGA 421 5 Realtek ALC201 16 Audio Codec PQFP 48 TPA 0202 Amplifier SPDIF JACK Clock Generator Control 5 LPC Secondary EIDE (CDROM/DVD) Primary EIDE (HDD) 1 ATI M6 VGA Y S Vedio TFT LCD uBGA 209 2 144 Pin SO-DIMM Socket*2 SO-DIMM 1394 PHY Control Power Switch Control A[0..25] D[0..15] 2 -HD[0..63] TPS2211 IC CARD Socket -HA3..31] Thermal Recorder IR Module HP-3600 NS87393 Super I/O PRINTER PORT M.D.C. (30 pin) Control 1 H8-3437 ISA BUS Cover Switch Keyboard Controller 1 Internal Keyboard PQFP 100 TQFP 100PIN ICS950805 RJ-11 JACK External Keyboard Power Button Flash ROM 512KB PLCC 32 Touch PAD FAN1 For CPU 16MHz FAN2 For D/D Title System Block Diagram Size Date: A B Document Number Rev 02 411671200001 Friday, December 28, 2001 Sheet 2 of 22 5 4 3 2 POWER DIAGRAM OF THE 8170 +3V 1 +12VS +1.5VS 1.8VS Shut Down MOSFET SUSB# PWR_ON D Self Dischange (FOR VGA) VDDR_MEM2.5 Shut Down MOSFET DC/DC BOARD ADAPTOR MUST BE MEET ICH2 POWER ON SEQUENCE Shut Down MOSFET Shut Down Protecter Diode 3.3V DC to DC Convertor +3VS * OPTION(NO LINK) +5VS +5V learning 5V DC to DC Convertor C Battery Pack Discharge Shut Down Shut Down P Channel MOSFET SI4835DY D/VMAIN MOSFET +12V Shut Down 12V DC to DC Convertor CPU_CORE_EN D +1.5VS MCH ATI_M6 CPU_CORE CPU(FOR 1.7G) 49.3A +1.8V *ATI_M6 +1.8VS MCH ICH2 ATI_M6 350mA 350mA 1200mA +1.8VA ICH2 5mA VDDR_MEM2.5 ATI_M6 470mA +3V MCH SODIMM M6 ICH2 RTL8139CL IEEE1394 PCI4410 PCMCIA CARD ? 2A 330mA 410mA 330mA 69mA 79mA 500mA +3VS *MCH ICH2 CLOCK M6 SIO LCD ? 410mA 280mA 20mA 50mA 800mA +3VA ICH2 15mA +5V MODEM PCMCIA CARD ? 500mA +5VS IDE CD-ROM ALC200 USBX2 AUDIO AMP 900mA 1500mA 40mA 1000mA 1000mA +5VA H8 40mA +12VS Shut Down MOSFET CPU_CORE Vcc Core DC to DC Convertor LTC1709-9 ? 20mA 1200mA C Diode Charge +5VA Always B High Low Side Regulator LP2951 Choke B +5V Rsense +3V_ICH Regulator TC55RP3302 EMB MUST BE MEET ICH2 POWER ON SEQUENCE +1.8V_ICH Regulator AME8801 CC PWM Charge IC MAX1772 A CHARGE SWITCH SI4925DY CC CV Charge A Title Power Block Diagram Size Date: 5 4 3 2 Document Number Rev 02 411671200001 Friday, December 28, 2001 1 Sheet 3 of 22 5 4 1 -HD[0..63] U1A (6) -H_ADSTB1 (6) -H_ADSTB0 -H_REQ[0..4] U1B BPRI# DBSY# DEFER# DRDY# HIT# HITM# IERR# INIT# LOCK# MCERR# RESET# RS#2 RS#1 RS#0 RSP# TRDY# -H_ADS (6) -H_BNR -H_BNR (6) L25 K26 K25 J26 U6 W4 Y3 H6 TESTHI8 TESTHI9 TESTHI10 -H_BR0 D2 -H_BPRI -H_BR0 (6) W5 -H_INIT G4 -H_LOCK CPU_CORE -H_BPRI (6) -H_DBSY H5 -H_DEFER E2 -H_DRDY H2 -H_HIT F3 -H_HITM E3 R506 62 1% 0603 AC3 1 2 -H_DBSY (6) -H_DEFER (6) -H_DRDY (6) -H_HIT (6) -H_HITM (6) R509 300/NA 0603 1% CPU_CORE R3 62 0603 R2 62 0603 -THRMTRIP -H_PROCHOT -H_INIT -H_INIT (13) -H_LOCK (6) DESIGN GUIDE PAGE 236 DESCRIPTION(NO extra pull-up resistors required) V6 AB25 F4 G5 F1 AB2 J6 1 TESTHI8 TESTHI9 TESTHI10 BR#0 -H_ADS 1 DP#3 DP#2 DP#1 DP#0 G1 AC1 V5 AA3 G2 2 ADS# AP#0 AP#1 BINIT# BNR# 2 A#3 A#4 A#5 A#6 A#7 A#8 A#9 A#10 A#11 A#12 A#13 A#14 A#15 A#16 A#17 A#18 A#19 A#20 A#21 A#22 A#23 A#24 A#25 A#26 A#27 A#28 A#29 A#30 A#31 ADSTB#1 ADSTB#0 REQ#4 REQ#3 REQ#2 REQ#1 REQ#0 A#35 A#34 A#33 A#32 1 K2 K4 L6 K1 L3 M6 L2 M3 M4 N1 M1 N2 N4 N5 T1 R2 P3 P4 R3 T2 U1 P6 U3 T4 V2 R6 W1 T5 U4 R5 L5 H3 J3 J4 K5 J1 AB1 Y1 W2 V3 2 -HA3 -HA4 -HA5 -HA6 -HA7 -HA8 -HA9 -HA10 -HA11 -HA12 -HA13 -HA14 -HA15 -HA16 -HA17 -HA18 -HA19 -HA20 -HA21 -HA22 -HA23 -HA24 -HA25 -HA26 -HA27 -HA28 -HA29 -HA30 -HA31 -H_ADSTB1 -H_ADSTB0 -H_REQ4 -H_REQ3 -H_REQ2 -H_REQ1 -H_REQ0 D (6) -H_REQ[0..4] 2 (6) -HD[0..63] -HA[3..31] (6) -HA[3..31] 3 -CPURST -H_RS2 -H_RS1 -H_RS0 -CPURST (6) H25 K23 J24 L22 M21 H24 G26 L21 D26 F26 E25 F24 F23 G23 E24 H22 D25 J21 D23 C26 H21 G22 B25 C24 C23 B24 D22 C21 A25 A23 B22 B21 -DBI0 -DBI1 -DBI2 -DBI3 E21 G25 P26 V21 D#32 D#33 D#34 D#35 D#36 D#37 D#38 D#39 D#40 D#41 D#42 D#43 D#44 D#45 D#46 D#47 D#48 D#49 D#50 D#51 D#52 D#53 D#54 D#55 D#56 D#57 D#58 D#59 D#60 D#61 D#62 D#63 M23 N22 P21 M24 N23 M26 N26 N25 R21 P24 R25 R24 T26 T25 T22 T23 U26 U24 U23 V25 U21 V22 V24 W26 Y26 W25 Y23 Y24 Y21 AA25 AA22 AA24 -HD32 -HD33 -HD34 -HD35 -HD36 -HD37 -HD38 -HD39 -HD40 -HD41 -HD42 -HD43 -HD44 -HD45 -HD46 -HD47 -HD48 -HD49 -HD50 -HD51 -HD52 -HD53 -HD54 -HD55 -HD56 -HD57 -HD58 -HD59 -HD60 -HD61 -HD62 -HD63 D -DSTBP[0..3] -H_RS[0..2] (6) -H_TRDY (6) -DSTBN0 E22 -DSTBN1 K22 -DSTBN2 R22 -DSTBN3 W22 WMT478/NWD_14 (6) -DSTBN[0..3] D#31 D#30 D#29 D#28 D#27 D#26 D#25 D#24 D#23 D#22 D#21 D#20 D#19 D#18 D#17 D#16 D#15 D#14 D#13 D#12 D#11 D#10 D#9 D#8 D#7 D#6 D#5 D#4 D#3 D#2 D#1 D#0 -DBI[0..3] (6) -DBI[0..3] -H_RS[0..2] -H_TRDY -HD31 -HD30 -HD29 -HD28 -HD27 -HD26 -HD25 -HD24 -HD23 -HD22 -HD21 -HD20 -HD19 -HD18 -HD17 -HD16 -HD15 -HD14 -HD13 -HD12 -HD11 -HD10 -HD9 -HD8 -HD7 -HD6 -HD5 -HD4 -HD3 -HD2 -HD1 -HD0 -DSTBN[0..3] DBI#0 DBI#1 DBI#2 DBI#3 DSTBP#0 DSTBP#1 DSTBP#2 DSTBP#3 -DSTBP[0..3] (6) F21 -DSTBP0 J23 -DSTBP1 P23 -DSTBP2 W23 -DSTBP3 DSTBN#0 DSTBN#1 DSTBN#2 DSTBN#3 WMT478/NWD_14 C C PRECISION FSB COMPENSATION RESISTORS R7 1 2 0603 H_COMP0 1 2 0603 H_COMP1 R515 51 0603 CPU_CORE 10 9 8 7 6 TESTHI8 TESTHI9 TESTHI10 1206 R502 27 0603 B 1K*8 2 1 2 3 4 5 (21) PVID[0..4] C6 B6 B2 H_INTR H_NMI -H_SMI -H_STPCLK D1 E5 B5 Y4 AE1 AE2 AE3 AE4 AE5 PVID[0..4] PLL_VCCA 1 VCCIO_PLL PLL_VSSA 1 AF2 AF3 AF4 AD20 A5 AE23 AD22 A4 CPU_THERMDA CPU_THERMDC -THRMTRIP AE21 A22 A7 B3 C4 A2 CPU_CORE 1 TP1 (5) VCCPVID TP4 TP3 R522 680 0603 AF22 AF23 AC26 AD26 -H_A20M -H_FERR -H_IGNNE PVID4 PVID3 PVID2 PVID1 PVID0 ITP_TCK -ITP_RESET RP505 TESTHI11 TESTHI12 (13) H_INTR (13) H_NMI (13) -H_SMI (13) -H_STPCLK -H_BMP5 -H_BMP4 -H_BMP3 -H_BMP2 -H_BMP1 -H_BMP0 1 TESTHI0 TESTHI1 TESTHI2 TESTHI3 PLACE CLOSE TO CPU SOCKET 2 1K*8 10 9 8 7 6 1 1 2 3 4 5 U1C HCLK_CPU -HCLK_CPU TP6 1 TP8 1 (8) HCLK_CPU (8) -HCLK_CPU (13) -H_A20M (13) -H_FERR (13) -H_IGNNE ITP_TDI ITP_TDO ITP_TMS RP2 TESTHI4 TESTHI5 TESTHI6 TESTHI7 -H_A20M -H_IGNNE H_INTR H_NMI R512 51 0603 2 R519 51 0603 1 1 1 1 1 1 1 R508 51 0603 2 R513 51 0603 2 1 1 R516 51 0603 2 1 R503 150 0603 2 2 REQUEST NEW PART NUMBER FOR 51.1 Ohm, 1% R514 75 0603 2 R521 39 0603 1 1 PLACE THESE INSIDE SOCKET CAVITY 2 R507 TP547 TP40 TP42 TP41 CPU_CORE 1 51.1 1% 2 51.1 1% AD3 AF25 AD2 AF24 1206 BSEL0 BSEL1 TESTHI11 COMP0 COMP1 BCLK0 BCLK1 ITP_CLK0 ITP_CLK1 A20M# FERR# IGNNE# BPM#5 BPM#4 BPM#3 BPM#2 BPM#1 BPM#0 LINT0 LINT1 SMI# STPCLK# TESTHI0 DBR# TESTHI12 VID4 VID3 VID2 VID1 VID0 GTLREF3 GTLREF2 GTLREF1 GTLREF0 VCC RSVD VCCVID VCCA VCCSENSE VCCIOPLL VSSA VSSSENSE TESTHI5 TESTHI4 TESTHI3 TESTHI2 TESTHI7 TESTHI6 SKTOCC# RSVD RSVD RSVD THRMDA THRMDC THRMTRIP# TESTHI1 PWRGOOD PROCHOT# SLP# TCK TDI TDO TMS TRST# RSVD RSVD RSVD RSVD AD6 AD5 1 A6 L24 P1 H_BSEL0 TP2 TESTHI11 H_COMP0 H_COMP1 AB4 AA5 Y6 AC4 AB5 AC6 -H_BMP5 -H_BMP4 -H_BMP3 -H_BMP2 -H_BMP1 -H_BMP0 H_BSEL0 (8) TESTHI0 AD24 TP5 AE25 1 TESTHI12 AD25 H_GTLREF2_3 AA6 F6 AA21 F20 CPU_GTLREF AC23 AC24 AC20 AC21 AB22 AA20 AF26 1 TESTHI5 TESTHI4 TESTHI3 TESTHI2 TESTHI7 TESTHI6 TP7 AA2 AB23 C3 AB26 TESTHI1 H_PWRGD -H_PROCHOT -SLP D4 C1 D5 F7 E6 ITP_TCK ITP_TDI ITP_TDO ITP_TMS -ITP_RESET H_PWRGD (13) -SLP (13) B WMT478/NWD_14 Close to CPU socket +5VS One 220PF for each GTL REF Pin CPU_CORE 4" MAX. CPU_CORE 1 H_GTLREF2_3 1 7343 C31 2 1 20% 16V 33U GND1 GND2 NC1 NC2 NC3 1 2 ADM1021 2 1 VDD ADD0 ADD1 ALERT SDATA SCLK STBY 10 6 R526 10K 0603 11 12 Layout Note: W=12mil H8_THRM_DATA (19) 14 H8_THRM_CLK (19) 15 QSOP16B R523 0_DFS 0603 R524 0_DFS 0603 C715 1U 0603 VCCIO_PLL A 2 C546 220P 0603 5% W/S=12/12 mils (キキキキキキ as short as possible 5 9 13 D+ D- CPU SIGNAL TERMINATION 2 2 1 2 2 1 1 2 GTL Reference CKT C547 220P 0603 5% + C545 1U 0805 5% -CPURST 7 8 TEST TEST1 2 2 2 2 -H_BR0 PLL_VSSA R525 100 0603 1% A CPU_THERMDC H_PWRGD CPU_GTLREF 2 0603 C531 2200P 0603 -H_FERR PLL_VCCA 3 4 1 CPU_THERMDA 62 0603 1% 2 PLACE AT CPU END R527 1 16 R517 C536 0.1U 0603 50V 1 R5 301 0603 1 1 1 R510 51 0603 THERMAL RECORDER 1 CPU_CORE 1 7343 C30 2 1 20% 16V 33U + 0/NA 0603 49.9 1% 1 R6 51 0603 2 2 C524 220P 0603 5% 2 1 2 1 2 1 2 C523 220P 0603 5% 2 R518 C522 1U 0805 5% L3 4.7UH 2012 2 2 R511 100 0603 1% L2 4.7UH 2012 1 U502 1 2 0603 1 PLACE AT CPU END R520 1 49.9 1% 1 CPU_CORE PLL SUPPLY FILTER Title P4-CPU(1/2) Size Document Custom Number Date: 5 4 3 2 Rev 02 411671200001 Friday, December 28, 2001 1 Sheet 4 of 22 5 4 3 2 1 D D CPU_CORE 1 1 C521 10U 1206 10V 2 C12 150U 7343 10V + C28 150U 7343 10V 2 1 C552 + 22U 1210 10V 2 1 C16 22U 1210 10V 2 1 2 1 2 C514 22U 1210 10V CPU_CORE C11 10U 1206 10V 1 C533 0.1U 0603 50V 2 1 C549 0.1U 0603 50V 2 1 C532 0.1U 0603 50V 2 1 C539 0.1U 0603 50V 2 1 2 1 C540 0.1U 0603 50V 2 1 2 1 1 2 C22 0.1U 0603 50V C548 0.1U 0603 50V 1 C538 0.1U 0603 50V C537 10U 1206 10V C513 10U 1206 10V 2 1 C541 10U 1206 10V 2 1 C544 0.1U 0603 50V 2 1 C C534 0.1U 0603 50V 2 2 C543 10U 1206 10V 1 C525 10U 1206 10V 2 2 C526 10U 1206 10V 2 1 C542 10U 1206 10V 1 2 1 C551 10U 1206 10V 1 C530 10U 1206 10V 2 2 C535 10U 1206 10V 2 1 C7 10U 1206 10V 1 2 1 2 2 1 C9 10U 1206 10V C8 22U 1210 10V 1 C19 10U 1206 10V 1 2 1 C23 10U 1206 10V 1 C17 10U 1206 10V 2 2 C25 10U 1206 10V 2 1 C20 10U 1206 10V 1 2 1 C18 10U 1206 10V 1 C27 10U 1206 10V 2 2 C21 10U 1206 10V 2 1 C517 10U 1206 10V 1 2 1 2 2 1 C518 10U 1206 10V 1 CPU_CORE 1 C29 10U 1206 10V 2 C13 10U 1206 10V 2 1 C24 10U 1206 10V 1 C528 10U 1206 10V 2 2 C529 10U 1206 10V 2 1 C14 10U 1206 10V 1 2 1 2 1 C550 10U 1206 10V 2 2 1 2 C26 10U 1206 10V C10 10U 1206 10V B +5VS 1 +5VS 2 R505 10K 0603 2 R504 10 0603 U501 IN EN GND MIC5248 SOT25 PG OUT 4 CPU_CORE_EN 5 VCCPVID CPU_CORE_EN VCCPVID (21) (4) 1 C515 0.1U 0603 16V 10% 1 3 2 C516 1U 0603 2 2 1 WMT478/NWD_14 AE7 AE24 AE22 AE19 AD14 AD12 AD10 AD8 AD4 AD1 AD23 AD21 AE17 AE15 AE13 AE11 AE9 AE26 AB20 AC17 AC15 AC13 AC11 AC9 AC7 AC5 AC2 AC25 AC22 AC19 AD18 AD16 AA4 AA1 AA23 AA19 AB18 AB16 AB14 AB12 AB10 AB8 AB6 AB3 AB24 AB21 V4 V1 V23 W6 W3 W24 W21 Y5 Y2 Y25 Y22 AA17 AA15 AA11 AA9 AA26 AA7 C15 10U 1206 10V 1 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS AF8 VSS AF6 VSS AF1 VSS AF20 VSS A17 VSS A15 VSS A13 VSS A11 VSS A9 VSS A26 VSS AA13 VSS B14 VSS B M25 M22 E11 E9 E26 E7 E4 E1 E23 E19 F18 F16 F14 F12 F10 F8 F5 F2 F25 F22 G6 G3 G24 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS C5 VSS C2 VSS C25 VSS C22 VSS C19 VSS D18 VSS D16 VSS D14 VSS D12 VSS D10 VSS D8 VSS D6 VSS D3 VSS D24 VSS D21 VSS D20 VSS E17 VSS E15 VSS E13 VSS A3 VSS A24 VSS A21 VSS A19 VSS B18 VSS B16 VSS B12 VSS B10 VSS B26 VSS B8 VSS B4 VSS B23 VSS B20 VSS C17 VSS C15 VSS C13 VSS C11 VSS C9 VSS C7 VSS AF18 VSS AF16 VSS AF14 VSS AF12 VSS AF10 VSS C N6 N3 N24 N21 P5 P2 P25 P22 R26 R4 R1 R23 T6 T3 T24 T21 U5 U2 U25 U22 V26 G21 H26 H4 H1 H23 J5 J2 J25 J22 K6 K3 K24 K21 L26 L4 L1 L23 M5 M2 VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC U1D A8 A10 A12 A14 A16 A18 A20 B7 B9 B11 B13 B15 B17 B19 C8 C10 C12 C14 C16 C18 C20 D7 D9 D11 D13 D15 D17 D19 E8 E10 E12 E14 E16 E18 E20 F9 F11 F13 F15 F17 F19 AA8 AA10 AA12 AA14 AA16 AA18 AB7 AB9 AB11 AB13 AB15 AB17 AB19 AC8 AC10 AC12 AC14 AC16 AC18 AD7 AD9 AD11 AD13 AD15 AD17 AD19 AE6 AE8 AE10 AE12 AE14 AE16 AE18 AE20 AF5 AF7 AF9 AF11 AF13 AF15 AF17 AF19 AF21 1 CPU_CORE A A Title P4-CPU(2/2) Size Document Custom Number Date: 5 4 3 2 Rev 02 411671200001 Friday, December 28, 2001 1 Sheet 5 of 22 4 -HA[3..31] 2 -DSTBN0 -DSTBN1 -DSTBN2 -DSTBN3 1 R532 24.9 0603 1% R9 24.9 0603 1% 1 (4) -DSTBN[0..3] -DBI[0..3] (4) -DBI[0..3] -DBI0 -DBI1 -DBI2 -DBI3 (4) (4) (4) (4) (4) (4) (4) (4) (4) (4) (4) BCLK# BCLK HRCOMP1 HSWNG1 HRCOMP0 HSWNG0 -H_ADS -H_TRDY -H_DRDY -H_DEFER -H_HITM -H_HIT -H_LOCK -H_BR0 -H_BNR -H_BPRI -H_DBSY (4) -H_RS[0..2] (4) -CPURST -DSTBP0 -DSTBN0 -DBI0 -DSTBP1 -DSTBN1 -DBI1 -DSTBP2 -DSTBN2 -DBI2 -DSTBP3 -DSTBN3 -DBI3 AD3 AD4 AD5 AE7 AE6 AG4 AD11 AE11 AH9 AC16 AC15 AD15 -H_ADS -H_TRDY -H_DRDY -H_DEFER -H_HITM -H_HIT -H_LOCK -H_BR0 -H_BNR -H_BPRI -H_DBSY -H_RS0 -H_RS1 -H_RS2 -CPURST V3 U7 V4 Y4 Y3 Y5 W5 V7 W3 Y7 V5 W2 W7 W6 AE17 -H_RS[0..2] HDSTBP0# HDSTBN0# DBI0# HDSTBP1# HDSTBN1# DBI1# HDSTBP2# HDSTBN2# DBI2# HDSTBP3# HDSTBN3# DBI3# ADS# HTRDY# DRDY# DEFER# HITM# HIT# HLOCK# BR0# BNR# BPRI# DBSY# RS0# RS1# RS2# CPURST# HVREF_0 HVREF_1 HVREF_2 HVREF_3 HVREF_4 AB17 AB11 Y8 R8 M7 -HD0 -HD1 -HD2 -HD3 -HD4 -HD5 -HD6 -HD7 -HD8 -HD9 -HD10 -HD11 -HD12 -HD13 -HD14 -HD15 -HD16 -HD17 -HD18 -HD19 -HD20 -HD21 -HD22 -HD23 -HD24 -HD25 -HD26 -HD27 -HD28 -HD29 -HD30 -HD31 -HD32 -HD33 -HD34 -HD35 -HD36 -HD37 -HD38 -HD39 -HD40 -HD41 -HD42 -HD43 -HD44 -HD45 -HD46 -HD47 -HD48 -HD49 -HD50 -HD51 -HD52 -HD53 -HD54 -HD55 -HD56 -HD57 -HD58 -HD59 -HD60 -HD61 -HD62 -HD63 -HD[0..63] W8 W26 Y6 Y22 V8 V6 AC26 AC23 AC21 AC20 AC18 AC4 AC1 AB22 AB19 AB16 AB15 AB14 AB13 AG20 AG18 AG1 AF25 AF21 AF19 AF17 AF15 AF13 AF11 AF9 AF7 AF5 AJ27 AJ17 AJ15 AJ13 AJ11 AJ9 AJ7 AJ5 AJ3 AH23 AH21 AH19 AG22 AD6 AD8 AD10 AD12 AD14 AD16 AD19 AD22 AE1 AE4 AE18 AE20 AE29 P14 P16 W1 W4 AA1 AA4 AA8 AA29 AB6 AB9 AB10 AB12 V22 CPU_CORE R535 49.9 0603 1% R536 100 0603 1% C564 0.1U 0603 50V 1 U3D (4) 2 -DSTBP0 -DSTBP1 -DSTBP2 -DSTBP3 -DSTBN[0..3] K8 J8 AC13 AD13 AC2 AA7 2 HXRCOMP HREQ0# HREQ1# HREQ2# HREQ3# HREQ4# HADSTB0# HADSTB1# AA2 AB5 AA5 AB3 AB4 AC5 AA3 AA6 AE3 AB7 AD7 AC7 AC6 AC3 AC8 AE2 AG5 AG2 AE8 AF6 AH2 AF3 AG3 AE5 AH7 AH3 AF4 AG8 AG7 AG6 AF8 AH5 AC11 AC12 AE9 AC9 AE10 AD9 AG9 AC10 AE12 AF10 AG11 AG10 AH11 AG12 AE13 AF12 AG13 AH13 AC14 AF14 AG14 AE14 AG15 AG16 AG17 AH15 AC17 AF16 AE15 AH17 AD17 AE16 1 -HCLK_MCH HCLK_MCH HYRCOMP HYSWING U6 T7 R7 U5 U2 R5 N6 HD0# HD1# HD2# HD3# HD4# HD5# HD6# HD7# HD8# HD9# HD10# HD11# HD12# HD13# HD14# HD15# HD16# HD17# HD18# HD19# HD20# HD21# HD22# HD23# HD24# HD25# HD26# HD27# HD28# HD29# HD30# HD31# HD32# HD33# HD34# HD35# HD36# HD37# HD38# HD39# HD40# HD41# HD42# HD43# HD44# HD45# HD46# HD47# HD48# HD49# HD50# HD51# HD52# HD53# HD54# HD55# HD56# HD57# HD58# HD59# HD60# HD61# HD62# HD63# 2 VSS_0 VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 VSS_13 VSS_14 VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26 VSS_27 VSS_28 VSS_29 VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35 VSS_36 VSS_37 VSS_38 VSS_39 VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47 VSS_48 VSS_49 VSS_50 VSS_51 VSS_52 VSS_53 VSS_54 VSS_55 VSS_56 VSS_57 VSS_58 VSS_59 VSS_60 VSS_61 VSS_62 VSS_63 VSS_64 VSS_65 VSS_66 VSS_67 VSS_68 VSS_69 VSS_70 VSS_71 VSS_72 VSS_73 VSS_74 VSS_75 VSS_76 VSS_77 VSS_78 VSS_79 VSS_80 VSS_81 VSS_82 VSS_83 VSS_84 VSS_85 VSS_86 VSS_87 VSS_88 VSS_89 VSS_90 VSS_91 VSS_92 VSS_93 VSS_94 VSS_95 VSS_96 VSS_97 VSS_98 VSS_99 VSS_100 VSS_101 VSS_102 VSS_103 VSS_104 VSS_105 VSS_106 VSS_107 VSS_108 VSS_109 VSS_110 VSS_111 VSS_112 VSS_113 VSS_114 VSS_115 VSS_116 VSS_117 VSS_118 VSS_119 VSS_120 VSS_121 VSS_122 VSS_123 VSS_124 VSS_125 VSS_126 VSS_127 VSS_128 VSS_129 VSS_130 VSS_131 VSS_132 VSS_133 VSS_134 VSS_135 VSS_136 VSS_137 VSS_138 VSS_139 VSS_140 VSS_141 A15 A11 A7 A3 F24 F20 F16 F12 F8 E29 E26 E4 E1 D21 D17 D13 D9 D5 A27 A23 A19 K27 K7 J29 J26 J22 J6 J4 J1 K5 H21 H19 H17 H15 H13 H11 H9 G26 P8 P6 N29 N22 N17 N15 N13 N8 N4 N1 M23 L26 L24 L22 L8 L6 L4 L1 U29 U15 U4 U1 T22 T16 T14 T8 T6 R26 R17 R15 R13 R4 R1 D C 82845 BGA568_25 2 (4) -H_ADSTB0 (4) -H_ADSTB1 -DSTBP[0..3] HA3# HA4# HA5# HA6# HA7# HA8# HA9# HA10# HA11# HA12# HA13# HA14# HA15# HA16# HA17# HA18# HA19# HA20# HA21# HA22# HA23# HA24# HA25# HA26# HA27# HA28# HA29# HA30# HA31# 1 -H_REQ0 -H_REQ1 -H_REQ2 -H_REQ3 -H_REQ4 -H_ADSTB0 -H_ADSTB1 (8) -HCLK_MCH (8) HCLK_MCH (4) -DSTBP[0..3] T4 T5 T3 U3 R3 P7 R2 P4 R6 P5 P3 N2 N7 N3 K4 M4 M3 L3 L5 K3 J2 M5 J3 L2 H4 N5 G2 M6 L7 -H_REQ[0..4] (4) -H_REQ[0..4] C -HD[0..63] U3C -HA3 -HA4 -HA5 -HA6 -HA7 -HA8 -HA9 -HA10 -HA11 -HA12 -HA13 -HA14 -HA15 -HA16 -HA17 -HA18 -HA19 -HA20 -HA21 -HA22 -HA23 -HA24 -HA25 -HA26 -HA27 -HA28 -HA29 -HA30 -HA31 D 2 (4) -HA[3..31] 3 1 5 82845 BGA568_25 10 mil trace, 7 mil space, Cap place near MCH and between two resistors. B PLACE AT MCH845 B END C562 0.01U 0603 2 R537 301 0603 1 1 CPU_CORE 1 2 HYSWING 2 R540 150 0603 HXSWING, HYSWING 12 mil trace, 10 mil space A A Title Brookdale-MCH845(1/2) Size Document Custom Number Date: 5 4 3 2 Rev 02 411671200001 Friday, December 28, 2001 1 Sheet 6 of 22 3 2 1 +1.5VS 2 1 C157 0.1U 0603 50V 2 1 1 C575 0.1U 0603 50V C45 0.1U 0603 50V 2 2 Layout note: Close to MCH Layout note: Close to ICH2 TP500 TP501 TP517 TP518 TP535 TP31 TP25 TP26 TP32 TP33 TP27 1 1 1 1 1 1 1 1 1 1 1 SRAS# SCAS# SWE# RSVD0 RSVD1 RSVD2 RSVD3 RSVD4 RSVD5 RSVD6 RSVD7 RSVD8 RSVD9 RSVD10 SMRCOMP RDCLKIN RDCLKO SDREF0 SDREF1 2 1 1 C589 0.1U 0603 50V 2 1 C582 0.1U 0603 50V 2 1 C590 0.1U 0603 50V 2 1 2 1 2 C83 10U 1206 10V C588 0.1U 0603 50V OPEN-SMT5 2 C558 0.1U 0603 50V C578 0.1U 0603 50V 2 1 1 C555 0.1U 0603 50V 2 1 C554 0.1U 0603 50V 2 1 1 1 2 C579 0.1U 0603 50V 1 +1.8VS C32 10U 1206 10V C580 4.7U 0805 +80-20% B MEM_BS0 (9) MEM_BS1 (9) 1 1 1 1 1 1 J28 G3 H3 R26 J21 J9 (9) (9) (9) (9) +1.5VS R18 1 20 0603 2 0_DFS 0603 1 C58 10P/NA 0603 2 1% C553 0.1U 0603 50V C34 0.1U 0603 50V C36 0.1U 0603 50V C563 0.1U 0603 50V 1 -CS0 -CS1 TP534 TP533 -CS4 -CS5 TP526 TP536 TP531 TP525 TP22 TP527 1 1 -CS4 -CS5 C565 0.1U 0603 50V C557 0.1U 0603 50V Layout note: Trace length is 1.5" exactly. Place close to MCH +3VS +3V R01 R553 1 R559 49.9 0603 1% C581 0.1U 0603 50V 1 0_DFS 2 1 0/NA 2 R554 0603 2 49.9 0603 1% 0603 R547 2 2 82845 BGA568_25 1 1 2 TP532 TP537 C33 10U 1206 10V 2 -CS0 -CS1 (9) (9) (9) (9) 1 H23 J23 G7 G8 J24 G24 H7 F7 G25 H25 G6 H6 MEM_BS0 MEM_BS1 C55 10U 1206 10V 2 C 1 SCS0# SCS1# SCS2# SCS3# SCS4# SCS5# SCS6# SCS7# SCS8# SCS9# SCS10# SCS11# 1 1 +3V 1 CPU_CORE CKE0 CKE1 CKE2 CKE3 2 SHORT-SMT4 2 G23 J25 G27 AD27 AD26 K25 K23 F26 D12 C26 C23 C8 C5 B19 SCK11 SCK10 SCK9 SCK8 SCK7 SCK6 SCK5 SCK4 SCK3 SCK2 SCK1 SCK0 CKE0 CKE1 CKE2 CKE3 TP540 TP522 TP29 TP30 TP28 TP538 TP541 TP539 +3VS JS2 1 82845 BGA568_25 1 -SRASA -SCASA -SWEA (13) 1 HUB_VREF G5 H5 F15 G16 E3 F3 G14 G15 C2 E2 G13 F13 RSTIN# RSVD TESTIN# G9 F4 G10 F5 G11 E5 F17 G17 + VCCA0 VSSA0 VCCA1 VSSA1 D JO3 2 2 2 1 2 R13 150 0603 C573 10U/NA 1206 10V 1 TP21 1 TP528 1 TP523 1 TP530 1 TP20 1 TP19 R570 22 1 2 0603 R569 1 22 2 0603 1 TP23 1 R575 TP24 1 22 2 0603 R574 22 1 2 0603 (9) -SRASA (9) -SCASA (9) -SWEA HUB_VREF 1 -MCH_TEST SCKE0 SCKE1 SCKE2 SCKE3 SCKE4 SCKE5 SMBA0 SMBA1 1 1 1 1 1 1 1 1 T13 U13 T17 U17 C571 33U 3528 6.3V 2 1 1 SDRAMCLK1 SDRAMCLK0 (9) SDRAMCLK1 (9) SDRAMCLK0 R10 150 0603 C576 0.01U 0603 J27 H27 H26 + C570 33U 3528 6.3V 1 SDRAMCLK5 SDRAMCLK4 (9) SDRAMCLK5 (9) SDRAMCLK4 -PCIRST HI_0 HI_1 HI_2 HI_3 HI_4 HI_5 HI_6 HI_7 HI_8 HI_9 HI_10 HIU_STB HIU_STB# HLRCOMP HI_REF L512 4.7UH-10% 3225 2 +1.8VS P25 P24 N27 P23 M26 M25 L28 L27 M27 N28 M24 N25 N24 P27 P26 L509 4.7UH-10% 3225 1 TP524 HUB_D0 HUB_D1 HUB_D2 HUB_D3 HUB_D4 HUB_D5 HUB_D6 HUB_D7 HUB_D8 HUB_D9 HUB_D10 HUB_STB -HUB_STB HUB_RCOMP HUB_VREF RBF# WBF# PIPE# ST0 ST1 ST2 +1.5VS Power rail for SDR, still exist during STR. G29 C29 L23 D25 A25 H24 D23 K22 H22 F22 A21 H20 D19 H18 F18 A17 H16 D15 H14 F14 A13 H12 D11 H10 F10 A9 H8 D7 F6 A5 G4 G1 C1 J7 J5 K6 K24 K26 VCCSM_0 VCCSM_1 VCCSM_2 VCCSM_3 VCCSM_4 VCCSM_5 VCCSM_6 VCCSM_7 VCCSM_8 VCCSM_9 VCCSM_10 VCCSM_11 VCCSM_12 VCCSM_13 VCCSM_14 VCCSM_15 VCCSM_16 VCCSM_17 VCCSM_18 VCCSM_19 VCCSM_20 VCCSM_21 VCCSM_22 VCCSM_23 VCCSM_24 VCCSM_25 VCCSM_26 VCCSM_27 VCCSM_28 VCCSM_29 VCCSM_30 VCCSM_31 VCCSM_32 VCCSM_33 VCCSM_34 VCCSM_35 VCCSM_36 VCCSM_37 VCC1_8_0 VCC1_8_1 VCC1_8_2 VCC1_8_3 VCC1_8_4 2 (10,13,16,18) -PCIRST B AE22 AE23 AF22 AG25 AF24 AG26 L25 L29 N26 N23 M22 2 (13) HUB_STB (13) -HUB_STB 1 40.2 21% R16 0603 -AGP_RBF -AGP_WBF -AGP_PIPE AGP_ST0 AGP_ST1 AGP_ST2 SBA0 SBA1 SBA2 SBA3 SBA4 SBA5 SBA6 SBA7 SB_STB SB_STB# +1.8VS AJ23 AG23 AJ21 AG21 AF20 AE21 AD20 AB20 AJ19 AG19 AE19 AC19 AF18 AD18 AB18 AA9 AB8 U8 M8 VTT_0 VTT_1 VTT_2 VTT_3 VTT_4 VTT_5 VTT_6 VTT_7 VTT_8 VTT_9 VTT_10 VTT_11 VTT_12 VTT_13 VTT_14 VTT_15 VTT_16 VTT_17 VTT_18 VCC1_5_0 VCC1_5_1 VCC1_5_2 VCC1_5_3 VCC1_5_4 VCC1_5_5 VCC1_5_6 VCC1_5_7 VCC1_5_8 VCC1_5_9 VCC1_5_10 VCC1_5_11 VCC1_5_12 VCC1_5_13 VCC1_5_14 VCC1_5_15 VCC1_5_16 VCC1_5_17 VCC1_5_18 VCC1_5_19 VCC1_5_20 VCC1_5_21 VCC1_5_22 VCC1_5_23 VCC1_5_24 VCC1_5_25 1 +1.8VS AH28 AH27 AG28 AG27 AE28 AE27 AE24 AE25 AF27 AF26 MD[0..63] (9) 2 (10,14) -AGP_RBF (14) -AGP_WBF (14) -AGP_PIPE (10,14) AGP_ST0 (10,14) AGP_ST1 (10,14) AGP_ST2 HUB_D[0..10] HUB_D[0..10] AGP_SBA0 AGP_SBA1 AGP_SBA2 AGP_SBA3 AGP_SBA4 AGP_SBA5 AGP_SBA6 AGP_SBA7 AGP_SBSTB -AGP_SBSTB AD_STB0 AD_STB0# AD_STB1 AD_STB1# MD[0..63] AG29 AC29 W29 R29 AE26 AA26 U26 AJ25 AF23 AD23 AA22 W22 U22 R22 AD21 AB21 P17 U16 R16 N16 T15 P15 U14 R14 N14 P13 2 AGP_SBA[0..7] (10,14) AGP_SBSTB (10,14) -AGP_SBSTB (13) R24 R23 AC27 AC28 MD0 MD1 MD2 MD3 MD4 MD5 MD6 MD7 MD8 MD9 MD10 MD11 MD12 MD13 MD14 MD15 MD16 MD17 MD18 MD19 MD20 MD21 MD22 MD23 MD24 MD25 MD26 MD27 MD28 MD29 MD30 MD31 MD32 MD33 MD34 MD35 MD36 MD37 MD38 MD39 MD40 MD41 MD42 MD43 MD44 MD45 MD46 MD47 MD48 MD49 MD50 MD51 MD52 MD53 MD54 MD55 MD56 MD57 MD58 MD59 MD60 MD61 MD62 MD63 U3B 1 AGP_ADSTB0 -AGP_ADSTB0 AGP_ADSTB1 -AGP_ADSTB1 F27 E27 B28 C27 D26 E25 B25 D24 F23 B23 C22 C21 D20 C19 C18 C17 B13 E13 C12 B11 E11 C10 F9 C9 E8 E7 C7 D6 B5 D4 C3 B2 G28 E28 C28 D27 B27 F25 C25 E24 C24 E23 D22 E22 B21 C20 D18 E18 E14 C13 E12 F11 C11 E10 D10 B9 E9 D8 B7 E6 C6 C4 B3 D3 C16 E16 C15 D14 B17 D16 B15 C14 CPU_CORE MA[0..12] (9) 2 (10) AGP_VREF AGP_ADSTB0 -AGP_ADSTB0 AGP_ADSTB1 -AGP_ADSTB1 AGP_SBA[0..7] 66IN G_FRAME# G_DEVSEL# G_IRDY# G_TRDY# G_STOP# G_PAR G_REQ# G_GNT# GRCOMP AGPREF SDQ0 SDQ1 SDQ2 SDQ3 SDQ4 SDQ5 SDQ6 SDQ7 SDQ8 SDQ9 SDQ10 SDQ11 SDQ12 SDQ13 SDQ14 SDQ15 SDQ16 SDQ17 SDQ18 SDQ19 SDQ20 SDQ21 SDQ22 SDQ23 SDQ24 SDQ25 SDQ26 SDQ27 SDQ28 SDQ29 SDQ30 SDQ31 SDQ32 SDQ33 SDQ34 SDQ35 SDQ36 SDQ37 SDQ38 SDQ39 SDQ40 SDQ41 SDQ42 SDQ43 SDQ44 SDQ45 SDQ46 SDQ47 SDQ48 SDQ49 SDQ50 SDQ51 SDQ52 SDQ53 SDQ54 SDQ55 SDQ56 SDQ57 SDQ58 SDQ59 SDQ60 SDQ61 SDQ62 SDQ63 SCB0 SCB1 SCB2 SCB3 SCB4 SCB5 SCB6 SCB7 1 66M_MCH66IN P22 -AGP_FRAME Y24 -AGP_DEVSEL W28 -AGP_IRDY W27 -AGP_TRDY W24 -AGP_STOP W23 AGP_PAR W25 -AGP_REQ AG24 -AGP_GNT AH25 GRCOMP AD25 AGP_VREF AA21 (8) 66M_MCH66IN (10,14) -AGP_FRAME (10,14) -AGP_DEVSEL (10,14) -AGP_IRDY (10,14) -AGP_TRDY (10,14) -AGP_STOP (10) AGP_PAR (10,14) -AGP_REQ (10,14) -AGP_GNT G_CBE0# G_CBE1# G_CBE2# G_CBE3# SMA0 SMA1 SMA2 SMA3 SMA4 SMA5 SMA6 SMA7 SMA8 SMA9 SMA10 SMA11 SMA12 MA0 MA1 MA2 MA3 MA4 MA5 MA6 MA7 MA8 MA9 MA10 MA11 MA12 2 2 1% 0603 (10,14) (10,14) (10,14) (10,14) (10) V25 V23 Y25 AA23 G_AD0 G_AD1 G_AD2 G_AD3 G_AD4 G_AD5 G_AD6 G_AD7 G_AD8 G_AD9 G_AD10 G_AD11 G_AD12 G_AD13 G_AD14 G_AD15 G_AD16 G_AD17 G_AD18 G_AD19 G_AD20 G_AD21 G_AD22 G_AD23 G_AD24 G_AD25 G_AD26 G_AD27 G_AD28 G_AD29 G_AD30 G_AD31 MA[0..12] G22 E21 F21 G21 E20 G20 E19 F19 G19 G18 E17 E15 G12 1 R8 1 40.2 -AGP_CBE0 -AGP_CBE1 -AGP_CBE2 -AGP_CBE3 -AGP_CBE[0..3] (10) -AGP_CBE[0..3] C R27 R28 T25 R25 T26 T27 U27 U28 V26 V27 T23 U23 T24 U24 U25 V24 Y27 Y26 AA28 AB25 AB27 AA27 AB26 Y23 AB23 AA24 AA25 AB24 AC25 AC24 AC22 AD24 1 D AGP_AD0 AGP_AD1 AGP_AD2 AGP_AD3 AGP_AD4 AGP_AD5 AGP_AD6 AGP_AD7 AGP_AD8 AGP_AD9 AGP_AD10 AGP_AD11 AGP_AD12 AGP_AD13 AGP_AD14 AGP_AD15 AGP_AD16 AGP_AD17 AGP_AD18 AGP_AD19 AGP_AD20 AGP_AD21 AGP_AD22 AGP_AD23 AGP_AD24 AGP_AD25 AGP_AD26 AGP_AD27 AGP_AD28 AGP_AD29 AGP_AD30 AGP_AD31 2 U3A AGP_AD[0..31] (10) AGP_AD[0..31] 1 4 2 5 10 MIL TRACE,150 LATE W/ 7MIL SPACE A A Layout note: Place as close to MCH as possible Title Brookdale-MCH845(2/2) Size Document Custom Number Date: 5 4 3 2 Rev 02 411671200001 Friday, December 28, 2001 1 Sheet 7 of 22 A B CLOCK GENERATOR +3VS +3VCLKCPU L517 FS2 FS1 FS0 CPUCLK 0 0 1 100MHZ 0 1 1 133MHZ X502 1 1 C625 2.2U 0805 +80-20% 3 2 4 14.318MHZ JP_NET20 GNDCPU 2 +3VS 1 C624 0.1U 0603 50V C618 5P 0603 10% C617 5P 0603 10% 2 2 C623 0.1U 0603 50V 1 1 2 JL5 2 1 1 2 C626 0.1U 0603 50V 1 2 120Z/100M 2012 2 1 +3VCLK66 1 C643 0.1U 0603 50V C649 2.2U 0805 +80-20% +3VCLKCPU 46 50 +3VCLKPCI 8 14 4 9 15 20 27 31 36 41 47 1 +3VS 2 C646 2.2U 0805 +80-20% R01 VDDCPU0 VDDCPU1 2 10 11 12 13 16 17 18 2 R594 2 R603 2 R612 1 49.9 1 49.9 1 49.9 1% 1% 1% 0603 0603 0603 1 49.9 1 49.9 1 49.9 1% 1% 1% PCICLK_F0 PCICLK_F1 PCICLK_F2 VDDPCI0 VDDPCI1 GND0 GND1 GND2 GND3 GND4 GND5 GND6 GND7 GND8 66MHZ_OUT0/3V66_2 66MHZ_OUT1/3V66_3 66MHZ_OUT2/3V66_4 3V66_0 66MHZ_IN/3V66_5 IREF 5 6 7 21 22 23 1 1 1 2 R529 2 R602 2 R560 C616 10P/NA 0603 10% C637 10P/NA 0603 10% R528,R529 AS CLOSE AS PISSOBLE TO CPU R563,R560 AS CLOSE AS PISSOBLE TO MCH (NB) R607 R610 R609 R616 2 2 2 2 PCICLK_CARD (15) PCICLK_LAN (16) PCICLK_LPC (18) PCICLK_ICH (13) TP550 TP544 TP543 TP551 TP34 TP552 C627 10P/NA 0603 10% C628 10P/NA 0603 10% C629 10P/NA 0603 10% C671 10P/NA 0603 10% 2 R621 2 R620 2 R626 1 0603 133 0603 133 0603 33 33 24 2 R528 2 R598 2 R563 1 0603 0603 0603 2 2 R592 2 R599 2 R608 1 1 0603 133 0603 133 0603 33 1 0603 133 0603 133 0603 33 1 0603 133 0603 133 0603 133 0603 133 1 1 51 48 44 2 52 49 45 1 1 66M_MCH66IN (7) 66M_ICH (13) 66M_AGP (10) TP553 TP38 42 ICS950805 TSSOP56 GNDCPU R1 2 PCICLK0 PCICLK1 PCICLK2 PCICLK3 PCICLK4 PCICLK5 PCICLK6 VDDREF VDD48 VDDA VDD3V66_0 VDD3V66_1 (18) -HCLK_CPU (4) HCLK_CPU (4) C639 10P/NA 0603 10% C635 10P/NA 0603 10% C640 10P/NA 0603 10% R619 475 0603 1% 3 Q508 1DTC144TKA 2 C647 0.1U 0603 50V 2 -VTT_PWRGD 1 1 C648 0.1U 0603 50V 2 2 C641 0.1U 0603 50V 1 1 R630 10K_DFS 0603 2 120Z/100M 2012 R628 10K 0603 1 +3VCLK66 L519 1 2 +3VS MULTSEL0* VTT_PWRGD# SIO_14.318MHZ 1 1 37 26 19 32 2 0603 2 C644 0.1U 0603 50V 2 1 1 C642 0.1U 0603 50V 2 2 C645 0.1U 0603 50V 2 1 1 120Z/100M 2012 CPU_CORE 2 43 28 CPUCLKC0 CPUCLKC1 CPUCLKC2 33 1 R595 56 1 2 R618 -VTT_PWRGD +3VCLKANA CPUCLKT0 CPUCLKT1 CPUCLKT2 *PD# PCI_STOP# CPU_STOP#* 2 TP37 2 8.2K 1 0603 FS0 FS1 FS2 1 1 +3VS +3VCLKANA 2 REF 35 2 25 34 53 SDATA SCLK 39 38 (13) 14M_ICH (13) 1 0603 R5971K 1 2 3V66_1/VCH_CLK 2 +3VS 2 2 R50 1K 0603 54 55 40 48MHZ_USB 48MHZ_DOT X2 1 FS0 FS1 FS2 X1 2 (9,13) SMBDATA (9,13) SMBCLK L518 1 2 3 1 1 (4) H_BSEL0 R44 1K 0603 +3VS 2 29 30 1 FS0 FS1 FS2 2 0603 -HCLK_MCH (6) HCLK_MCH (6) 2 C622 2.2U 0805 +80-20% 33 0603 1 R624 1 TP36 1 2 Layout note: Place crystal within 500 mils of CLK Gen. 1 1 C621 0.1U 0603 50V 2 2 2 1 1 2 C620 0.1U 0603 50V 2 2 120Z/100M 2012 C619 0.1U 0603 50V U507 R45 1K 0603 2 L516 R40 1K/NA 0603 1 +3VCLKPCI 1 2 33 1 R596 1 1 USBCLK_ICH +3VS GNDCPU FD502 FIDUCIAL-MARK E500 TOUCHPAD_METAL8 E1 TOUCHPAD_METAL8 E2 TOUCHPAD_METAL8 E501 TOUCHPAD_METAL9 E3 TOUCHPAD_METAL8 1 1 1 1 1 E502 TOUCHPAD_METAL8 E504 TOUCHPAD_METAL8 E503 TOUCHPAD_METAL8 E505 TOUCHPAD_METAL8 E506 TOUCHPAD_METAL8 1 FD503 FIDUCIAL-MARK 1 1 1 E6 TOUCHPAD_METAL8 E507 TOUCHPAD_METAL8 E508 TOUCHPAD_METAL8 E509 TOUCHPAD_METAL9 E510 TOUCHPAD_METAL9 E511 TOUCHPAD_METAL8 1 6 1 7 1 4 1 1 2 8 8 1 E5 TOUCHPAD_METAL8 FD500 FIDUCIAL-MARK 8 1 1 1 E7 TOUCHPAD_METAL8 E512 TOUCHPAD_METAL8 E513 TOUCHPAD_METAL9 E514 TOUCHPAD_METAL5 E515 TOUCHPAD_METAL5 1 1 1 12 11 10 1 4 5 6 MTG20 ID5.0/OD7.6 1 7 8 9 5 12 11 10 GND_16 1 4 5 6 MTG22 ID2.8/OD7.6 1 MTG21 ID2.8/OD7.6 1 6 3 2 1 7 3 7 8 9 2 3 2 1 6 4 7 3 5 1 2 4 MTG16 ID2.8/OD6 3 5 7 8 9 4 5 6 7 8 9 MTG18 MTG/ID2.2/OD5.6 MTG19 MTG/ID2.2/OD5.6 12 11 10 FD4 FIDUCIAL-MARK 3 2 1 13 12 11 10 TP_GND 4 5 6 1 MTG15 ID2.8/OD6.0 MTG14 ID2.8/OD7.6 3 2 1 TP_GND FD501 FIDUCIAL-MARK FD3 FIDUCIAL-MARK 1 1 E4 TOUCHPAD_METAL8 FD2 FIDUCIAL-MARK 1 7 8 9 7 8 9 7 8 9 5 4 5 4 AGND 1 FD1 FIDUCIAL-MARK 1 MTG13 ID3.0/OD6.0 1 12 11 10 MTG12 ID3.0/OD6.0 1 4 5 6 MTG11 ID3.0/OD6.0 1 12 11 10 MTG10 ID3.0/OD6.0 1 4 5 6 MTG9 ID3.2/OD6.0 1 12 11 10 MTG8 ID3.2/OD6.0 1 4 5 6 MTG7 ID3.2/OD6.0 1 6 MTG28 ID2.8/OD6.0 1 3 MTG17 ID2.8/OD6.0 1 6 MTG5 ID2.8/OD7.6 1 3 MTG4 ID2.8/OD6.5 1 7 1 2 1 7 3 2 1 3 2 1 2 3 2 1 MTG3 ID2.8/OD7.6 8 1 MTG2 MTG/ID2.2/OD5.6 8 1 MTG1 MTG/ID2.2/OD5.6 TP_GND TP_GND AGND Title Clock Generator,Screw holes Size Document Custom Number R01 FOR EMI ISSUE Date: A B Rev 02 411671200001 Friday, December 28, 2001 Sheet 8 of 22 A B SYSTEM MEMORY SO-DIMM Module +3V R01 +3V MA[0..14] (7) MA[0..14] Close to SO-DIMM Module J503 MDD16 MDD17 MDD18 MDD19 MDD20 MDD21 MDD22 MDD23 RP12 0*8_DFS RPX8 MAA6 MAA8 MAA9 MAA10 RP4 0*8_DFS RPX8 -MDQMA2 -MDQMA3 MDD24 MDD25 MDD26 MDD27 RP8 0*8_DFS RPX8 MDD28 MDD29 MDD30 MDD31 SMBDATA1 RP11 0*8_DFS RPX8 CKE3 (7) SDRAMCLK5 R54 22 0603 MDD48 MDD49 MDD50 MDD51 MDD52 MDD53 MDD54 MDD55 MAA7 MEM_BS0 MEM_BS1 MAA11 -MSRASA -MSWE A -MCS0 -MCS1 SDRAMCLK5 (7) R60 22 0603 C107 10P 0603 C117 10P 0603 Near to SO-DIMM Near to SO-DIMM MEM_BS0 (7) MDD16 MDD17 MDD18 MDD19 MDD20 MDD21 MDD22 MDD23 MAA6 MAA8 MAA9 MAA10 MEM_BS1 (7) -MDQMA2 -MDQMA3 -MDQMA6 -MDQMA7 MDD24 MDD25 MDD26 MDD27 MDD56 MDD57 MDD58 MDD59 MDD28 MDD29 MDD30 MDD31 MDD60 MDD61 MDD62 MDD63 SMBCLK SMBDATA0 SMBCLK (8,13) 2 2 1 2 1 1 2 1 2 C102 10U/NA 1206 16V C111 0.1U 0603 50V 1 C104 0.1U 0603 50V (7) MD[0..63] C114 0.1U 0603 50V 2 1 1 C103 0.1U 0603 50V 2 C110 0.1U 0603 50V 2 1 1 MDD44 MDD45 MDD46 MDD47 2 MDD40 MDD41 MDD42 MDD43 CKE0 (7) -MSCASA CKE1 MAA12 C109 0.1U 0603 50V C116 0.1U 0603 50V 1 1 1 C115 0.1U 0603 50V C113 4.7U_NA 0805 +80-20% 2 CKE0 1 +3V 2 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 +3V 2 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 C112 10U/NA 1206 16V Close to SO-DIMM Module MAA3 MAA4 MAA5 1 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 -MDQMA4 -MDQMA5 C106 10U/NA 1206 16V 2 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 C100 10U/NA 1206 16V 2 SDRAMCLK0 1 -MSCASA CKE3 MAA12 (7) SDRAMCLK0 CKE2 (7) MDD36 MDD37 MDD38 MDD39 2 CKE2 +3V MDD32 MDD33 MDD34 MDD35 C118 4.7U_NA 0805 +80-20% CKE1 (7) SDRAMCLK1 SDRAMCLK1 (7) 1 MDD44 MDD45 MDD46 MDD47 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 MDD48 MDD49 MDD50 MDD51 MDD52 MDD53 MDD54 MDD55 MAA7 MEM_BS0 MEM_BS1 MAA11 R57 22 0603 C108 10P 0603 Near to SO-DIMM +5V 1 C101 10P 0603 MDD12 MDD13 MDD14 MDD15 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 MEM_BS0 (7) R51 10K 0603 MEM_BS1 (7) 2 RP10 0*8_DFS RPX8 -MSRASA -MSWE A -MCS4 -MCS5 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 MDD8 MDD9 MDD10 MDD11 MDD40 MDD41 MDD42 MDD43 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 12 Near to SO-DIMM R59 22 0603 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 MAA3 MAA4 MAA5 2 RP6 0*8_DFS RPX8 SDRAMCLK4 MAA0 MAA1 MAA2 1 (7) SDRAMCLK4 -MDQMA0 -MDQMA1 -MDQMA4 -MDQMA5 2 MDD12 MDD13 MDD14 MDD15 RP5 0*8_DFS RPX8 MDD36 MDD37 MDD38 MDD39 1 MDD8 MDD9 MDD10 MDD11 MDD4 MDD5 MDD6 MDD7 2 -MDQMA6 -MDQMA7 MDD56 MDD57 MDD58 MDD59 3 Q6 DTC144TKA1 R1 2 DRAMENA (13) MDD60 MDD61 MDD62 MDD63 SMBCLK SMBCLK (8,13) DIMM144P/0.8MM/H4 AMP 1123693-1 G DIMM144P/0.8MM G BANK0/1 NO SUPPORT ECC FUNCTION SMBDATA0 NO SUPPORT ECC FUNCTION S D D R168 D S Q8 2N7002 Q7 FDV302P SOT23_FET R169 1 100K 0603 R01 1 100K 0603 SMBDATA1 S 2 BANK2/3 RP13 0*8_DFS RPX8 2 MDD7 MDD39 MDD6 MDD38 MDD5 MDD37 MDD36 MDD4 MDD11 MDD10 MDD42 MDD43 MDD9 MDD41 MDD8 MDD40 MDD52 MDD19 MDD50 MDD18 MDD17 MDD49 MDD16 MDD48 MDD27 MDD60 MDD25 MDD26 MDD58 MDD24 MDD57 MDD22 MDD2 MDD34 MDD3 MDD35 MDD1 MDD33 MDD0 MDD32 MDD15 MDD47 MDD46 MDD14 MDD13 MDD45 MDD12 MDD44 MDD56 MDD23 MDD55 MDD53 MDD54 MDD21 MDD51 MDD20 MDD31 MDD63 MDD30 MDD62 MDD61 MDD29 MDD28 MDD59 MAA0 MAA1 MAA2 MDD32 MDD33 MDD34 MDD35 1 RP3 0*8_DFS RPX8 -MDQMA0 -MDQMA1 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 MDD0 MDD1 MDD2 MDD3 1 1 -MSWEA -MCS5 -MSRASA -MSCASA -MCS4 -MCS0 -MCS1 MDD4 MDD5 MDD6 MDD7 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 D S MD7 MD39 MD6 MD38 MD5 MD37 MD36 MD4 MD11 MD10 MD42 MD43 MD9 MD41 MD8 MD40 MD52 MD19 MD50 MD18 MD17 MD49 MD16 MD48 MD27 MD60 MD25 MD26 MD58 MD24 MD57 MD22 MD2 MD34 MD3 MD35 MD1 MD33 MD0 MD32 MD15 MD47 MD46 MD14 MD13 MD45 MD12 MD44 MD56 MD23 MD55 MD53 MD54 MD21 MD51 MD20 MD31 MD63 MD30 MD62 MD61 MD29 MD28 MD59 RP9 0*8_DFS RPX8 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 2 -SWEA -CS5 -SRASA -SCASA -CS4 -CS0 -CS1 MAA11 MAA12 MAA10 MAA9 MAA8 MAA5 MAA3 1 -SWEA -CS5 -SRASA -SCASA -CS4 -CS0 -CS1 MDD0 MDD1 MDD2 MDD3 RP7 0*8_DFS RPX8 2 (7) (7) (7) (7) (7) (7) (7) MAA6 MAA7 MAA4 MAA1 MAA2 MAA0 1 MA11 MA12 MA10 MA9 MA8 MA5 MA3 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 2 2 9 10 11 12 13 14 15 16 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 9 10 11 12 13 14 15 16 9 10 11 12 13 14 15 16 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 9 10 11 12 13 14 15 16 9 10 11 12 13 14 15 16 2 J505 MA6 MA7 MA4 MA1 MA2 MA0 MD[0..63] R02 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 -MDQMA4 -MDQMA5 -MDQMA2 -MDQMA6 -MDQMA3 -MDQMA7 -MDQMA0 -MDQMA1 R02 SMBDATA (8,13) RP14 0*8_DFS RPX8 Layout Note: Layout Note: SDRAMCLK0,1,4,5 as don't over 2 vias as possible Trace Width 5mils Trace Spacing 12mils Group Spacing (spacing from other signal groups) 12mils Trace Width 5mils Trace Spacing 12mils Group Spacing (spacing from other signal groups) 12mils MCH Data signals 2" Controls Panel Digital Power On/Off BLONb->Control Backlight On/Off C AE19 AF19 AE20 AF20 AE21 AF21 AE18 AF18 +5VS AD20 AC20 DVIDDCCLK & DVIDDCDATA have internal pull-down AF24 AF23 AF22 AE24 AE23 AE22 AD24 AD25 RED (12) GREEN (12) BLUE (12) HSYNC (12) VSYNC (12) R14 1 499 1% +AGP_MEM_REF (13) -ENABKL_MSK 1 2 R539 0_DFS 0603 2 2 DTC144WK Q12 SDA (12) SCL (12) -M6_SUS_STAT R25 1K 0603 1% ENPBLT (22) Internal DAC reference AC26 AC25 AE25 0603 2 VDDR_MEM2.5 R22 10K 0603 AD21 -ENABKL DTC144WK Q3 R20 1K 0603 1% C60 0.01U 0603 -SUS_STAT (13,18) AC221 TP14 Special output pin for Apple monitor R01 2 1 1 C556 18P 25V 0603D 10% 3 2 4 27MHZ 2 C76 0.1U 0603 50V 2 1 C78 0.1U 0603 50V 2 1 2 1K 0603 1% LTGIO0 LTGIO1 LTGIO2 AC8 AD8 AC9 AD9 AE8 AF8 AC10 AD10 AE9 AF9 AD11 AC11 AE11 AF11 AD12 AC12 AD13 AE13 AE12 AF12 ZV_SYNC (15) ZV_HREF (15) CAS# B A9 X500 1 AGP_VREF (7) R35 D SBA0 SBA1 SBA2 SBA3 SBA4 SBA5 SBA6 SBA7 AUXWIN 1M 0603D 1K 0603 1% 2 1 R33 2 STP_AGP# AGP_BUSY# RBF# AD_STB0 AD_STB1 SB_STB 1 2 1 AC6 SERR# TXOUT_L0N TXOUT_L0P TXOUT_L1N TXOUT_L1P TXOUT_L2N TXOUT_L2P TXOUT_L3N TXOUT_L3P TXCLK_LN TXCLK_LP TXOUT_U0N TXOUT_U0P TXOUT_U1N TXOUT_U1P TXOUT_U2N TXOUT_U2P TXOUT_U3N TXOUT_U3P TXCLK_UN TXCLK_UP Y4 AA1 AA2 AA3 ZV_LCDDCNTL [3:0:] have internal pull-down RAS# 1 0603 0603 0603 0603 ZV_LCDCNTL0 ZV_LCDCNTL1 ZV_LCDCNTL2 ZV_LCDCNTL3 ZV_LCDDATA [23:0:] have internal pull-down MEMORY INTERFACE 2 2 2 2 2 2 PCICLK RST# REQ# GNT# PAR STOP# DEVSEL# TRDY# IRDY# FRAME# INTA# TP506 TP507 TP503 TP502 TP508 TP504 TP10 TP13 ZV_SYNC ZV_HREF 1 ZV_PCLK A19 B19 D18 C18 J4 K1 K2 K3 1 0 1 1 0_DFS 1 0_DFS 1 0_DFS 0 1 AA26 AA23 AA25 Y24 J23 J24 J26 K24 K26 K25 AA24 1 1 1 1 1 1 1 1 QS0 QS1 QS2 QS3 QS4 QS5 QS6 QS7 2 R572 R573 R564 R568 R567 66M_AGP -PCIRST -AGP_REQ -AGP_GNT AGP_PAR -M6_STOP -M6_DEVSEL -M6_TRDY -M6_IRDY -M6_FRAME -PCI_INTA C/BE#0 C/BE#1 C/BE#2 C/BE#3 (15) A22 D21 A16 C15 F2 G1 N2 N3 1 -AGP_STOP -AGP_DEVSEL -AGP_TRDY -AGP_IRDY -AGP_FRAME (7,14) -AGP_STOP (7,14) -AGP_DEVSEL (7,14) -AGP_TRDY (7,14) -AGP_IRDY (7,14) -AGP_FRAME F23 J25 L25 N23 ZV_UV[0..7] DQM#0 DQM#1 DQM#2 DQM#3 DQM#4 DQM#5 DQM#6 DQM#7 2 (8) 66M_AGP (7,13,16,18) -PCIRST (7,14) -AGP_REQ (7,14) -AGP_GNT (7) AGP_PAR 0603 ATI Advice. -AGP_CBE0 -AGP_CBE1 -AGP_CBE2 -AGP_CBE3 -AGP_CBE[0..3] (7) -AGP_CBE[0..3] ZV_UV[0..7] (15) B13 A13 C12 B12 A12 D11 C11 B11 A11 C10 B10 A10 D9 C9 3 -M6_SUS_STAT ZV_Y[0..7] MA0 MA1 MA2 MA3 MA4 MA5 MA6 MA7 MA8 MA9 MA10 MA11 MA12 MA13 1 2 0603 ZV_Y[0..7] ZV_Y0 ZV_Y1 ZV_Y2 ZV_Y3 ZV_Y4 ZV_Y5 ZV_Y6 ZV_Y7 ZV_UV0 ZV_UV1 ZV_UV2 ZV_UV3 ZV_UV4 ZV_UV5 ZV_UV6 ZV_UV7 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 1 20K A26 B25 A25 A24 B23 A23 C22 B22 C21 B21 A21 D20 C20 B20 A20 C19 B18 A18 C17 B17 A17 D16 C16 B16 B15 A15 D14 C14 B14 A14 D13 C13 B1 C1 C2 D1 D2 E1 E2 F1 G2 G3 H1 H2 H3 J1 J2 J3 L1 L2 L3 L4 M1 M2 M3 N1 N4 P1 P2 P3 P4 R1 R2 R3 TP515 TP516 TP514 TP520 TP521 TP529 TP519 2 R538 1 AA4 AB1 AB2 AB3 AB4 AC1 AC2 AC3 AD1 AD2 AD3 AE1 AE2 AF1 AF2 AF3 AE3 AF4 AE4 AD4 AF5 AE5 AD5 AC5 1 1 1 1 1 1 1 3 -AGP_BUSY Y2 Y1 W3 W2 W1 V4 V3 V2 V1 U3 U2 U1 T4 T3 1 2 0603 LVDS 20K AGP2X R545 1 GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 GPIO10 GPIO11 GPIO12 GPIO13 ZV_LCDDATA0 ZV_LCDDATA1 ZV_LCDDATA2 ZV_LCDDATA3 ZV_LCDDATA4 ZV_LCDDATA5 ZV_LCDDATA6 ZV_LCDDATA7 ZV_LCDDATA8 ZV_LCDDATA9 ZV_LCDDATA10 ZV_LCDDATA11 ZV_LCDDATA12 ZV_LCDDATA13 ZV_LCDDATA14 ZV_LCDDATA15 ZV_LCDDATA16 ZV_LCDDATA17 ZV_LCDDATA18 ZV_LCDDATA19 ZV_LCDDATA20 ZV_LCDDATA21 ZV_LCDDATA22 ZV_LCDDATA23 TMDS -STP_AGP U516B DAC2 AGP4X 2 0603 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 DAC1 B R546 1 20K D24 C26 D25 D26 E23 E25 E24 E26 F26 G23 G25 G24 G26 H24 H26 H25 L23 L26 L24 M26 M24 N25 M25 N26 P23 P26 P24 R25 R24 R26 T23 T25 CLK SSC +3VS AGP_AD0 AGP_AD1 AGP_AD2 AGP_AD3 AGP_AD4 AGP_AD5 AGP_AD6 AGP_AD7 AGP_AD8 AGP_AD9 AGP_AD10 AGP_AD11 AGP_AD12 AGP_AD13 AGP_AD14 AGP_AD15 AGP_AD16 AGP_AD17 AGP_AD18 AGP_AD19 AGP_AD20 AGP_AD21 AGP_AD22 AGP_AD23 AGP_AD24 AGP_AD25 AGP_AD26 AGP_AD27 AGP_AD28 AGP_AD29 AGP_AD30 AGP_AD31 PCI/AGP ZV PORT/ EXT TMDS/ GPIO/ ROM U516A AGP_AD[0..31] (7) AGP_AD[0..31] M6 MEMORY C559 18P 25V 10% 0603D D Place near AGP Title VGA-M6(1/2) Size Document Custom Number Date: 1 2 3 4 5 6 7 Rev 02 411671200001 Friday, December 28, 2001 Sheet 10 8 of 22 5 4 3 2 1 +1.8VS VDD_MCLK2.5 C5 MPVDD MPVSS 1 1 2 2 1 1 1 2 2 +3VS 0/NA 2 VDDR_MEM2.5 1210 RO1 +1.8VS VDD_PLL1.8 L507 U505 AO4400 SO8 L510 2 1 1 1 2 C604 0.1U 0603 1 +1.8VS R588 4.7K_1% 0603 VDD_PNLPLL1.8 L4 1 2 120Z/100M 1608 2 3 Q505 SCK431LCSK-.5 SOT23N C R01 2 2 2 C611 470P 0603 2 1 1 R591 4.7K 0603 VDD_PLL1.8_GND 1A R587 4.99K 0603 1% C608 10U 1206 2 L5 +3VS 1 C35 4.7U 0805 +80-20% 1 S D C613 10U 1206 PLACE CLOSE TO M6-M 2 4 1 2 C61 22U 1210 10V 1 2 C66 1U 0603 G 1 1 C64 0.1U 0603 50V 2 1 2 1 2 C605 0.1U 0603 50V 2 0_DFS 0603D_DFS VDDR_MEM2.5 C37 0.1U 0603 50V VDD_PNLPLL1.8_GND 1 1 C44 1U 0603 2 C52 0.1U 0603 50V 2 1 2 1 C47 0.1U 0603 50V C38 0.1U 0603 50V 2 0_DFS 0603D_DFS T5 U4 V5 W4 Y5 AA5 AC4 AB5 AB6 AB15 AB16 AB18 AB20 AB21 AB22 AC17 AC23 AC24 2 +3V E6 E7 E9 E11 E13 E14 E16 E18 E20 E21 G5 H4 J5 K4 L5 M4 N5 P5 R4 D7 3 2 1 C568 0.1U 0603 50V 1 8 7 6 5 1 VDDR_MEM2.5 C569 4.7U 0805 +80-20% 2 +12VS 2 120Z/100M 1608 1 1 PLACE CLOSE TO M6-M 2 C73 22U 1210 10V 1 2 C77 1U 0603 2 1210 1 R694 1 1 C70 0.1U 0603 50V 2 C71 0.1U 0603 50V 2 2 B24 F3 D6 C6 D15 D19 D22 G4 1 1 1 D10 C7 C23 D12 D17 E3 F4 0 C49 22U 1210 10V R01 PLACE CLOSE TO M6-M VDD_MEMPLL1.8 L514 2 L515 +1.5VS C610 4.7U 0805 +80-20% 2 C596 0.1U 0603 50V C75 0.1U 0603 50V C606 0.1U 0603 50V C602 0.1U 0603 50V 2 0_DFS 0603D_DFS E22 F22 G22 H23 J22 K23 L22 M23 N22 P22 R23 T22 U23 V22 W23 Y22 AA22 AB23 AB24 D23 C24 1 120Z/100M 1608 1 2 1 1 2 +1.8VS C72 1U 0603 C59 22U 1210 10V B VDD_MEMPLL1.8_GND R01 PLACE CLOSE TO M6-M VDDR_MEM2.5 VDD_DAC2.5 L506 2 120Z/100M 1608 1 1 C561 4.7U 0805 +80-20% 1 C560 0.1U 0603 50V VDD_MCLK2.5 L11 VDDRH MOBILITY-M6 BGA420_64_1MM 2 120Z/100M 1608 2 VDD_MEMPLL1.8_GND 1 2 1 R160 2 AVDD AVSSN AVSSQ 2 1 1 2 1 2 1 2 Select 3.3V or 2.5V to match internal memory core VDD 1 A2 A3 VDD_MEMPLL1.8 A2VDD A2VDDQ A2VSSN_0 A2VSSN_1 A2VSSQ D C43 0.1U 0603 50V C79 4.7U 0805 +80-20% 2 VDD_DAC1.8 AD23 AD22 AC21 TPVDD TPVSS C41 0.1U 0603 50V 1 VDD_PNLPLL1.8_GND AD16 AD15 AC15 AC16 AE15 C42 4.7U 0805 +80-20% 2 VDD_DAC2.5 2 120Z/100M 1608 1 AE17 AF17 VDD_PNLPLL1.8 1 C50 0.1U 0603 50V VDD_PNLIO1.8 (TXVDDR 40MA) (LVDDR 40MA) 1 VDDP_0 VDDP_1 VDDP_2 VDDP_3 VDDP_4 VDDP_5 VDDP_6 VDDP_7 VDDP_8 VDDP_9 VDDP_10 VDDP_11 VDDP_12 VDDP_13 VDDP_14 VDDP_15 VDDP_16 VDDP_17 VDDP_18 VDDP_19 VDDP_20 C51 0.1U 0603 50V L7 PLACE CLOSE TO M6-M LPVDD LPVSS TXVDDR_0 TXVDDR_1 TXVSSR_0 TXVSSR_1 TXVSSR_2 C48 4.7U 0805 +80-20% 1 AC19 AD19 AD18 AD17 AC18 B C67 22U 1210 10V 2 AE10 AF10 LVDDR_0 LVDDR_1 LVSSR_0 LVSSR_1 C68 1U 0603 1 VDD_PLL1.8_GND PVDD PVSS VDDR3_0 VDDR3_1 VDDR3_2 VDDR3_3 VDDR3_4 VDDR3_5 VDDR3_6 VDDR3_7 VDDR3_8 VDDR3_9 VDDR3_10 VDDR3_11 VDDR3_12 VDDR3_13 VDDR3_14 VDDR3_15 VDDR3_16 VDDR3_17 C53 0.1U 0603 50V 2 AC13 AD14 AB13 AC14 CORE & I/O POWER VDDR1_0 VDDR1_1 VDDR1_2 VDDR1_3 VDDR1_4 VDDR1_5 VDDR1_6 VDDR1_7 VDDR1_8 VDDR1_9 VDDR1_10 VDDR1_11 VDDR1_12 VDDR1_13 VDDR1_14 VDDR1_15 VDDR1_16 VDDR1_17 VDDR1_18 VDDR1_19 C63 0.1U 0603 50V 1 VDD_PNLIO1.8 VDDQM_0 VDDQM_1 VDDQM_2 VDDQM_3 VDDQM_4 VDDQM_5 VDDQM_6 VDDQM_7 (AVDD 90MA) 2 120Z/100M 1608 2 AE26 AD26 VDD_PLL1.8 VDDM_0 VDDM_1 VDDM_2 VDDM_3 VDDM_4 VDDM_5 VDDM_6 AB11 H5 K5 M5 R5 U5 W5 AB8 AB14 AB7 AB17 AB19 W22 U22 R22 M22 K22 H22 E19 E17 E15 E12 E10 E8 AB12 2 C VDD_DAC1.8 L6 1 VDDC_0 VDDC_1 VDDC_2 VDDC_3 VDDC_4 VDDC_5 VDDC_6 VDDC_7 VDDC_8 VDDC_9 VDDC_10 VDDC_11 VDDC_12 VDDC_13 VDDC_14 VDDC_15 VDDC_16 VDDC_17 VDDC_18 VDDC_19 VDDC_20 VDDC_21 VDDC_22 VDDC_23 VDDC_24 1 D VSS_0 VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 VSS_13 VSS_14 VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26 VSS_27 VSS_28 VSS_29 VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35 VSS_36 VSS_37 VSS_38 VSS_39 VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47 VSS_48 VSS_49 VSS_50 VSS_51 VSS_52 VSS_53 VSS_54 VSS_55 VSS_56 VSS_57 VSS_58 VSS_59 VSS_60 VSS_61 VSS_62 VSS_63 VSS_64 VSS_65 VSS_66 VSS_67 VSS_68 VSS_69 VSS_70 VSS_71 VSS_72 VSS_73 2 E5 C3 B2 A1 D4 T10 T11 T12 T13 T14 T15 T16 T17 K10 K11 K12 K13 K14 K15 K16 K17 L10 L11 L12 L13 L14 L15 L16 L17 M10 M11 M12 M13 M14 M15 M16 M17 N10 N11 N12 N13 N14 N15 N16 N17 P10 P11 P12 P13 P14 P15 P16 P17 R10 R11 R12 R13 R14 R15 R16 R17 U10 U11 U12 U13 U14 U15 U16 U17 C4 D3 E4 F5 D5 2 +1.8VS U516C C74 0.1U 0603 50V A A Title VGA-M6(2/2) Size Date: 5 4 3 2 Document Number Rev 02 411671200001 Friday, December 28, 2001 1 Sheet 11 of 22 5 LCD & CRT INTERFACE 4 3 2 1 LED INDICATOR D14 SCROLL +5VS 2 1 R683 470 0603 R684 470 0603 D 2 R157 470 0603 (17,19) -SCROLL (17,19) -NUM (17,19) -CAP 2 D 1 1 2 C711 1U/NA 0603 2 C712 1U/NA 0603 2 C713 1U/NA 0603 1 (NA D13,D14,D15,R157 ,R683,R684 For LCD 15") 1 D13 CAP 1 D15 NUM D15 LCD ID SELECT DISPLAY LCD_ID2 LCD_ID1 LCD_ID0 UNIPAC 0 0 1 HYUNDAI 0 1 0 HANNSTAR 0 1 1 Unipac(SXGA) 1 0 0 HannStar(SXGA) 1 0 1 HannStar(XGA)15" 1 1 0 Sumsung(SXGA+)15" 1 1 1 K A PG1102W K A PG1102W K A PG1102W D13 D14 +5VAS (19) -H8_RESET 1 2 LED_CLK 8 -H8_RESET 9 CLK CLR GND -SCROLL -NUM -CAP 3 4 5 6 10 11 12 13 QA QB QC QD QE QF QG QH -AC_POWER -BATT_LED -BATT_R -BATT_G -AC_POWER (22) -BATT_LED (22) -BATT_R (22) -BATT_G (22) 14 VCC 1 7 A B C714 0.1U 0603 50V C719 1U 0603 R01 2 2 74VHC164 TSSOP14 1 (19) LED_CLK LED_DATA 74VHC164 U514 (19) LED_DATA LCD CONNECTOR TXOUT2+ TXOUT2- (10) TXOUT2+ (10) TXOUT2LCD_ID0 LCD_ID1 LCD_ID2 (10) LCD_ID0 (10) LCD_ID1 (10) LCD_ID2 RP1 2 2 1 C506 0.1U 0603 50V CLOSE TO NDS 9410 1 C512 10U 1206 10V +12VS 4 C510 1000P 0603 2 1 1 1 1 2 C503 0.1U 0603 50V 1 2 R501 Q2 R1 3 TXOUT1+ (10) TXOUT1- (10) 8 7 6 5 C 1 mircoSMDC110 8 7 6 5 C507 0.1U 0603 50V 2 3 2 1 TXOUT0+ (10) TXOUT0- (10) TXOUT1+ TXOUT11 2 3 4 C1 1000P 0603 TX2OUT1+ (10) TX2OUT1- (10) TXOUT0+ TXOUT0- C508 10U_NA 1206 10V 470K 0603 2 1 DTC144TKA +3VS ENPVDD ENPVDD (10) 6.8K*4 1206 GND1 GND2 RP520 47K*4 1206 TXCLK+ (10) TXCLK- (10) TX2OUT1+ TX2OUT1- 4 3 2 1 Internal 10K VIL--->2V TXCLK+ TXCLK- SO8 +3VS 1 G TX2OUT2+ TX2OUT2- (10) TX2OUT2+ (10) TX2OUT2- Q500 AO4400 F502 2 Close to LCD Connector D TX2OUT0+ TX2OUT0- 14" 330mA,15"800mA 120Z/100M 2012 L505 1 2 LCDVCC 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 S TX2CLK+ TX2CLK- (10) TX2CLK+ (10) TX2CLK(10) TX2OUT0+ (10) TX2OUT0- J2 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 2 LCDVCC 2 LCD C MA/20PX2/ST ACES 87216-4000 5 6 7 8 R01 Layout Note: +5V S/W/W/S=12/6/6/12 mils as short as possible U500 キキキキキǐキキ B 8 2 7 3 6 4 5 B 1 +5VS 1 F501 +5VS mircoSMDC110 2 +3VS 1 2 L500120Z/100M 1608 GREEN 1 2 L501120Z/100M 1608 (10) BLUE BLUE 1 2 L502120Z/100M 1608 (10) SDA SDA (10) HSYNC HSYNC 4 3 2 1 Q502 D D S S CP501 22P*4 1206 C501 10U_NA 1206 10V JL1 1 2 A SHORT-SMT3 JL500 2 D D S 5 6 7 8 5 6 7 8 J1 VGA SUYIN 7535S-15G2T-05 17 1 CP500 22P*4 1206 5 6 7 8 SCL RP501 75*4 1206 5 6 7 8 (10) SCL 4 3 2 1 4 3 2 1 VSYNC G Q501 A 1 9 2 10 3 11 4 12 5 13 6 14 7 15 8 FA500 120OHM/100MHZ Close to VGA Connector CP506 22P*4 1206 2 2N7002 (10) VSYNC 16 GND_CRT15 5 6 7 8 4 3 2 1 S D2 3 DDC2B (10) GREEN G SSOP8 1 BAV99_NA K 2 Close to VGA Connector 2 EC11FS2 D500 External VGA Connector DDC2B 1Amp (40mil-60mil) 4 3 2 1 W/S=16/12/12/12/16 mils RED 2 (10) RED R543 4.7K 0603 A 1 1 PACDN006/NA R544 4.7K 0603 1 2N7002 SHORT-SMT3 GND_CRT15 GND_CRT15 GND_CRT15 GND_CRT15 GND_CRT15 GND_CRT15 Title LCD & CRT Interface Size Date: 5 4 3 2 Document Number Rev 02 411671200001 Friday, December 28, 2001 1 Sheet 12 of 22 5 4 3 2 1 +3V_ICH +5V MSDIN +1.8V_ICH +3VS W17 Y18 AB19 AA19 W18 Y19 AB20 AA20 -USBOC0 W19 Y20 Y21 W20 10K/NA R74 1 2 1 1 2 2 1 1 1 1 2 2 2 K2 M20 PDCS1# SDCS1# PDCS3# SDCS3# PDA0 PDA1 PDA2 SDA0 SDA1 SDA2 PDDREQ SDDREQ PDDACK# SDDACK# PDIOR# SDIOR# PDIOW# SDIOW# PIORDY SIORDY GPIO6 PIRQH#/GPIO5 INTRUDER# RTCRST# VBIAS RTCX1 RTCX2 PDD0 PDD1 PDD2 PDD3 PDD4 PDD5 PDD6 PDD7 PDD8 PDD9 PDD10 PDD11 PDD12 PDD13 PDD14 PDD15 CLK66 CLK14 CLK48 AC_RST# AC_SYNC AC_BITCLK AC_SDOUT AC_SDIN0 AC_SDIN1 SPKR LAD0/FWH0 LAD1/FWH1 LAD2/FWH2 LAD3/FWH3 LDRQ0# LDRQ1# LFRAME#/FWH4 FS0/FWH5 SDD0 SDD1 SDD2 SDD3 SDD4 SDD5 SDD6 SDD7 SDD8 SDD9 SDD10 SDD11 SDD12 SDD13 SDD14 SDD15 USBP0_P USBP0_N USBP1_P USBP1_N USBP2_P USBP2_N USBP3_P USBP3_N OC0# OC1# OC2# OC3# SMLINK0 SMLINK1 VRMPWRGD BATLOW/TP0 EE_CS EE_DIN EE_DOUT EE_SHCLK VSS_70 VSS_69 VSS_68 E21 C15 E19 D15 -PCS1 -SCS1 -PCS3 -SCS3 F20 F19 E22 A16 D16 B16 PDA0 PDA1 PDA2 SDA0 SDA1 SDA2 G22 B18 F22 B17 G19 D17 G21 C17 G20 A17 PDREQ (14) SDREQ (14) -PDACK (14) -SDACK (14) -PDIOR (14) -SDIOR (14) -PDIOW (14) -SDIOW (14) PIORDY (14) SIORDY (14) PDD[0..15] (14) PDD[0..15] H19 H22 J19 J22 K21 L20 M21 M22 L22 L21 K22 K20 J21 J20 H21 H20 PDD0 PDD1 PDD2 PDD3 PDD4 PDD5 PDD6 PDD7 PDD8 PDD9 PDD10 PDD11 PDD12 PDD13 PDD14 PDD15 D18 B19 D19 A20 C20 C21 D22 E20 D21 C22 D20 B20 C19 A19 C18 A18 SDD0 SDD1 SDD2 SDD3 SDD4 SDD5 SDD6 SDD7 SDD8 SDD9 SDD10 SDD11 SDD12 SDD13 SDD14 SDD15 U19 V20 B15 U20 (14) (14) (14) (14) (14) (14) C SDD[0..15] SDD[0..15] (14) +3V_ICH +3VS R153 1 1 R155 1 R661 (14) (14) (14) (14) 10K 2 0603D 10K 2 0603D R128 10K 0603 0603D 10K 2 VRMPWRGD +3V_ICH P9 P14 P13 VRMPWRGD (21) VSS_0 VSS_1 82801 BGA288_36_36 B 1 1 D -RSMRST R89 10K/NA 0603D 2 2 R75 10K/NA 0603D 2 ACSDOUT 0603 2 USBP0_0- 22 0603 2 USBP0_0+ BAV70LT1 SOT23N R632 1K 0603D 14M_ICH USBP0+ C650 1U 0603 C197 22P 0603 R634 USBCLK_ICH USBP0_0+ (22) C187 22P 0603 R77 15 0603D -RTC_RST 2 R654 15 0603D R662 15 0603D 2 C140 0.1U 0603 50V C211 1 0603 2 USBP2_2- 22 0603 2 USBP2_2+ 2 RTC_X1 1 C205 22P 0603 1 1 X3 32.768KHZ CM200 R145 10M 0603D 2 1 C677 0.1U 0603 50V R127 1 USBP2+ 2 12P 0603 5% W/S=6/12 mils 22 1 2 A USBP2_2- (22) USBP2_2+ (22) C203 22P 0603 4 C147 0.1U 0603 50V 2 1 1 C153 4.7U 0805 +80-20% 2 C683 0.1U 0603 50V 2 1 1 C673 0.1U 0603 50V 2 2 C680 47P 0603 2 1 1 C679 0.1U 0603 50V 2 1 C695 0.1U/NA 0603 50V 2 C143 47P 0603 2 C144 0.1U 0603 50V 1 1 1 C145 0.1U 0603 50V 2 2 C136 47P 0603 2 1 1 C137 0.1U 0603 50V 2 1 C125 4.7U 0805 +80-20% 2 1 2 C208 4.7U 0805 +80-20% 1 R135 1 USBP2R146 10M 0603D C212 +3V_ICH 1 Close to ICH2 RTC_VBIAS 1 BH-800.1K 2 2 C651 0.047U 0603D CLOSE ICH2 C698 10P 0603D 1 -PME +3VS 1 0603D BT1 RTC BATTERY CONN. 2 SMBCLK C678 10P 0603D 2 1K 1 SMBDATA 2 C170 0.1U 0603 50V 2 1 8.2K 2 1 R107 0603 8.2K 2 1 R108 0603 1 10K/NA 2 R605 0603 1 C150 0.1U 0603 50V 2 1 C699 0.1U 0603 50V 2 1 C690 0.1U 0603 50V 2 1 C155 0.1U 0603 50V 2 1 C130 0.1U 0603 50V 2 1 2 1 2 1 2 C126 0.1U 0603 50V ICN2 INTERNAL PULL UP 2 A C131 4.7U 0805 +80-20% C138 10P 0603D 2 R633 1 1 C652 1U 0603 +1.8VS +3V 2 2 0603D 1 8.2K AC_SDOUT PULL HIGH FOR SAFEMODE. 2 2 1 66M_ICH USBP0_0- (22) 1 ICH_A20GATE 22 1 2 R114 1 1 3 R159 1M 0603 1% R123 1 USBP0- W/S=6/12 mils 1 1 1 R125 15K 0603D 2 -WAKE_UP R126 15K 0603D 2 -SMB_ALERT R130 15K 0603D VCC_RTC 1 R131 15K 0603D 2 -1394WR Close to ICH2 (2.0V~3.3V) D509 1 1 RTC CIRCUITRY R689 330K 0603 2 -RCIN -SCI SPK_OFF 1 -THRM C122 1U 0603 Tr>10mS C181 1U 0603D 1 -PCIRST +5VA 2 GPIO6 USBP1+ USBP1USBP3+ USBP3- GPI13 -EXTSMI 1 -HDD_RST K4 K3 J4 J3 C706 0.1U 0603 50V -GATE1394 1 DRAMENA 2 -CDROM_RST 2 0603 10K 2 0603 10K 2 0603 10K 2 0603 10K 2 0603 10K 2 0603 10K 2 0603 8.2K 2 0603 8.2K 2 0603 2 -ENABKL_MSK 0603 2 -PCIRST_MSK 10K 1 1 R99 1 R97 1 R656 1 R93 1 R94 1 R96 1 R144 1 R118 1 R117 2 GPI7 1 USBP0+ USBP0USBP1+ USBP1USBP2+ USBP2USBP3+ USBP3- 1 2 C129 0.1U 0603 50V +3V_ICH 10K 2 1 R87 0603 10K 2 1 R129 0603 10K 2 1 R112 0603 10K 2 1 R111 0603 1 10K/NA 2 R110 0603 10K 2 1 R86 0603 10K 2 1 R101 0603 8.2K 2 1 R90 0603 10K 2 1 R120 0603D 10K 2 1 R119 0603D 1 8.2K/NA 2 R150 0603D Y12 W12 AB13 AB12 Y13 W13 AB11 AA12 A1 A10 R100 10K 0603 1 2 1 2 2 +1.8VS 2 1 1 B C128 0.1U 0603 50V LAD0 LAD1 LAD2 LAD3 -LDRQ 1 -LFRAME +3V_ICH For Vccsus & vccusb pin C127 0.1U 0603 50V V22 22 2 0603 P19 R19 22 2 0603 P21 ACSDIN Y22 MSDIN W22 SBSPKR N22 -USBOC2 (22) -USBOC2 C682 4.7U 0805 +80-20% 3 2 TP548 (18) -LFRAME D4 M19 P20 C703 0.1U 0603 50V 1 2 1 1 1 R147 1 (18) -LDRQ R650 0_DFS 0603 +3V_ICH R674 1 (22) -USBOC0 +3VS +3VS -ACRST ACSYNC ACBITCLK ACSDOUT AC_SDIN0 FOR Audio Codec. AC_SDIN1 FOR MDC. 10K 2 1 R136 0603D 82801 BGA288_36_36 T20 T21 U22 T22 66M_ICH 14M_ICH USBCLK_ICH NO MDC NEED PULL DOWN 10K G3 H2 LAN_CLK LAN_RSTSYNC 2 (14,15) (14,16) (14) (14) (14) (14) +5VS 2 2 G2 G1 H1 F3 F2 F1 LAN_RXD0G2 LAN_RXD0G3 LAN_RXD0G4 LAN_TXD0 LAN_TXD1 LAN_TXD2 -PCI_GNT0 -PCI_GNT1 -PCI_GNT2 -PCI_GNT3 -PCI_GNT4 -PCI_GNT5 Y11 M4 T19 -RTC_RST RTC_VBIAS RTC_X1 RTC_X2 V19 -PCI_GNT0 -PCI_GNT1 -PCI_GNT2 -PCI_GNT3 -PCI_GNT4 -PCI_GNT5 1K 2 0603 1 R69 R01 V5REF1 V5REF2 M2 M1 R4 T2 R1 L4 GPIO6 -PCI_INTH -INTRUDER (8) 66M_ICH (8) 14M_ICH (8) USBCLK_ICH (16,17) -ACRST (16,17) ACSYNC (16,17) ACBITCLK (16,17) ACSDOUT (17) ACSDIN (16) MSDIN (17) SBSPKR (18) LAD[0..3] SERIRQ (14,15,18) (14,15) (14,16) (14) (14) (14) (14) (14) -PCI_INTH C195 0.1U 0603 50V 2 10K 2 10K -PCI_REQ0 -PCI_REQ1 -PCI_REQ2 -PCI_REQ3 -PCI_REQ4 -PCI_REQ5 (7) TP549 V5REF_SUS -PCI_REQ0 -PCI_REQ1 -PCI_REQ2 -PCI_REQ3 -PCI_REQ4 -PCI_REQ5 IRQ14 (14) IRQ15 (14) (10,18) -SUS_STAT (8,9) SMBDATA (8,9) SMBCLK R154 8.2K 0603D GPIO25 GPIO24 THRM# SLP_S3# SLP_S5# PWROK RSM_PWROK PWRBTN# RI# RSMRST# SUSSTAT# SUSCLK# SMBDATA SMBCLK SMBALERT#/GPIO11 D12 D13 R2 R3 T1 AB10 P4 L3 U21 0603 1 R152 0603 1 R651 SERIRQ 40.2 0603 1% HUB_VREF -PCI_INTA (10,14,15) -PCI_INTB (14) -PCI_INTC (14,15) -PCI_INTD (14,16) -1394WR -THRM -SUSB -SUSC PWROK W15 V21 AA13 W16 AB18 R20 Y16 W21 AA17 R21 Y17 AA18 AA16 AB16 AB17 VCCRTC F21 C16 N20 P22 N19 N21 IRQ14 IRQ15 VCC_RTC R82 TP546 -PCIRST_MSK -1394WR -THRM -SUSB -SUSC PWROK -RSMRST -PWRBTN -WAKE_UP -RSMRST -SUS_STAT SUS_CLK32K 1 SMBDATA SMBCLK -SMB_ALERT (19) -PWRBTN (19) -WAKE_UP +1.8VS HUB_STB (7) -HUB_STB (7) C213 0.1U 0603D 50V VCC_CPU1 VCC_CPU2 -PCI_INTA -PCI_INTB -PCI_INTC -PCI_INTD DTC144TKA U17B (15) (19) (15,19,22) (19,22) (19) 1 BAT54 1 P1 P2 P3 N4 D16 3 +5VS_ICHREF Q15 (7) BAT54 VCC_RTC 2 HUB_D0 HUB_D1 HUB_D2 HUB_D3 HUB_D4 HUB_D5 HUB_D6 HUB_D7 HUB_D8 HUB_D9 HUB_D10 1 HUB_STB -HUB_STB -H_A20M (4) -SLP (4) -H_FERR (4) -H_IGNNE (4) -H_INIT (4) H_INTR (4) H_NMI (4) -H_SMI (4) -H_STPCLK (4) -RCIN (19) ICH_A20GATE (19) H_PWRGD (4) HUB_D[0..10] D10 A2 VSS_2 A21 VSS_3 A22 VSS_4 AA1 VSS_5 AA2 VSS_6 AA21 VSS_7 AA22 VSS_8 AB1 VSS_9 AB2 VSS_10 AB21 VSS_11 AB22 VSS_12 B1 VSS_13 B10 VSS_14 B2 VSS_15 B21 VSS_16 B22 VSS_17 B3 VSS_18 B9 VSS_19 C2 VSS_20 C3 VSS_21 C4 VSS_22 C9 VSS_23 D3 VSS_24 D5 VSS_25 D6 VSS_26 D7 VSS_27 D8 VSS_28 D9 VSS_29 E6 VSS_30 E7 VSS_31 E8 VSS_32 E9 VSS_33 J10 VSS_34 J11 VSS_35 J12 VSS_36 J13 VSS_37 J14 VSS_38 J9 VSS_39 K1 VSS_40 K10 VSS_41 K11 VSS_42 K12 VSS_43 K13 VSS_44 K14 VSS_45 K9 VSS_46 L10 VSS_47 L11 VSS_48 L12 VSS_49 L13 VSS_50 L14 VSS_51 L9 VSS_52 M10 VSS_53 M11 VSS_54 M12 VSS_55 M13 VSS_56 M14 VSS_57 M9 VSS_58 N10 VSS_59 N11 VSS_60 N12 VSS_61 N13 VSS_62 N14 VSS_63 N9 VSS_64 P10 VSS_65 P11 VSS_66 P12 VSS_67 A4 B5 A5 B6 B7 A8 B8 A9 C8 C6 C7 C5 A6 A7 A3 B4 C685 0.1U 0603D 50V 1 -H_A20M -SLP -H_FERR -H_IGNNE -H_INIT H_INTR H_NMI -H_SMI -H_STPCLK -RCIN ICH_A20GATE H_PWRGD C681 1U 0805C 16V 2 D11 A12 R22 A11 C12 C11 B11 B12 C10 B13 C13 A13 1 -CDROM_RST -ENABKL_MSK -CDROM_PWRON -HDD_PWRON DRAMENA -HDD_RST -GATE1394 SPK_OFF GPI02/PIRQE# GPI03/PIRQF# GPIO4/PIRQG# GPIO7 GPIO8 GPIO12 GPIO13 GPIO18 GPIO19 GPIO20 GPIO21 GPIO22 GPIO23 GPIO27 GPIO28 R5 T5 U5 V5 V6 V7 V8 (14) (10) (14) (14) (9) (14) (15) (17) GNT0# GNT1# GNT2# GNT3# GNT4# GNTB#/GPIO17/GNT5# H5 VCCSUS1_8_0 J5 VCCSUS1_8_1 V14 VCCSUS1_8_2 V15 VCCSUS1_8_3 V16 VCCSUS1_8_4 (19) -SCI (19) -EXTSMI REQ0# REQ1# REQ2# REQ3# REQ4# REQB#GPIO1/REQ#5 VCCA1_8 VCC1_8_0 VCC1_8_1 VCC1_8_2 VCC1_8_3 VCC1_8_4 VCC1_8_5 -PCI_INTE N3 -PCI_INTF N2 -PCI_INTG N1 GPI7 AA11 -SCI Y14 -EXTSMI W14 GPI13 AB15 -CDROM_RST A15 -ENABKL_MSK D14 -CDROM_PWRON C14 -HDD_PWRON L1 DRAMENA B14 -HDD_RST A14 -GATE1394 AB14 SPK_OFF AA14 (14) -PCI_INTE (14) -PCI_INTF (14) -PCI_INTG IRQ14 IRQ15 APICCLK APICD0 APICD1 SERIRQ DEVSEL# FRAME# IRDY# TRDY# STOP# PAR PCIRST# PLOCK# SERR# PERR# PME# REQA#/GPI0 GNTN#/GPIO16 PCICLK D2 E5 P5 V9 K19 L19 D10 1 TP39 AB7 V3 W8 V4 W1 W2 AA15 AA7 W7 Y7 Y15 M3 L2 W11 VCCPX1 VCCPX2 VCCPS2 VCCPS1 VCCUSB1 VCCUSB2 (8) PCICLK_ICH -DEVSEL -FRAME -IRDY -TRDY -STOP PAR -PCIRST -LOCK -SERR -PERR -PME -PCI_REQA -PCI_GNTA PCICLK_ICH PIRQA# PIRQB# PIRQC# PIRQD# C/BE0# C/BE1# C/BE2# C/BE3# F5 G5 T18 U18 V17 V18 (14,15,16) -DEVSEL (14,15,16) -FRAME (14,15,16) -IRDY (14,15,16) -TRDY (14,15,16) -STOP (15,16) PAR (7,10,16,18) -PCIRST (14) -LOCK (14,15,16) -SERR (14) -PERR (15,16) -PME (14) -PCI_REQA AA3 AB6 Y8 AA9 HL0 HL1 HL2 HL3 HL4 HL5 HL6 HL7 HL8 HL9 HL10 HL11 HL_STB HL_STB# HLCOMP HUBREF VCC3_3_7 VCC3_3_8 VCC3_3_9 VCC3_3_10 VCC3_3_11 VCC3_3_12 VCC3_3_13 VCC3_3_14 VCC3_3_15 VCC3_3_16 VCC3_3_17 C -CBE0 -CBE1 -CBE2 -CBE3 A20M# CPUSLPA# FERR# IGNNE# INIT# INTR NMI SMI# STPCLK# RCIN# A20GATE CPUPWRGD R18 P18 J18 H18 G18 F18 E18 E17 E16 E15 E14 -CBE[0..3] (15,16) -CBE[0..3] AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 VCC3_3_0 VCC3_3_1 VCC3_3_2 VCC3_3_3 VCC3_3_4 VCC3_3_5 VCC3_3_6 AD0 AA4 AD1 AB4 AD2 Y4 AD3 W5 AD4 W4 AD5 Y5 AD6 AB3 AD7 AA5 AD8 AB5 AD9 Y3 AD10 W6 AD11 W3 AD12 Y6 AD13 Y2 AD14 AA6 AD15 Y1 AD16 V2 AD17 AA8 AD18 V1 AD19 AB8 AD20 U4 AD21 W9 AD22 U3 AD23 Y9 AD24 U2 AD25 AB9 AD26 U1 AD27 W10 AD28 T4 AD29 Y10 AD30 T3 AD31 AA10 C176 0.1U 0603D 50V 2 -PCIRST_MSK 1 (15,16) AD[0..31] C178 0.1U 0603D 50V 3 R1 D C177 0.1U 0603D 50V 2V~3.6V 4uA NC7S32 SOT70 U17A C171 1U 0805C 16V 2 A B GND 2 (15,16) -PCIRST_N VCC Y -PCIRST 1 2 3 2 U16 5 4 1 Supply Voltage(Vcc) 2.0V to 6.0V 1 R158 4.7K 0603 2 NC7S32 OR +3V 1 1 CPU_CORE +3VS 2 Title RTC_X2 ICH2 12P 0603 5% R01 Size Date: 5 4 3 2 Document Number Rev 02 411671200001 Friday, December 28, 2001 1 Sheet 13 of 22 A B AGP BUS ENHANCED IDE +3VS +3VS R558 1 6.8K/NA 2 0603 5% R24 (7,10) -AGP_SBSTB -AGP_SBSTB R562 1 6.8K 5% 2 0603 R556 2K/NA 0603 R156 Primary EIDE Connector 2 2 R552 2K/NA 0603 2 470 0603 1 PDA2 -PCS3 -PCS1 -HDD_RST 2 MA/22PX2/ST C16822-X44XX A K FOR 15" CD_ROM CONNECTOR -BRSTDRV1 R156 ,D12 For 15" Platform +5VS CDROM_LEFT CDROM_COMM -BRSTDRV2 SDD7 SDD6 SDD5 SDD4 SDD3 SDD2 SDD1 SDD0 D513 JO29 -HDDACTP (17,19) -HDDACTP 1 2 EC10QS04 A OPEN-SMT4 R01 Q13 S 1 1M 2 (13) -HDD_PWRON 2 Q14 C184 0.1U 0603 50V 1 C198 0.1U 0603 50V 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 -SDIOW SIORDY IRQ15 SDA1 SDA0 -SCS1 -CDACTP CDROMPWR CDROMPWR Close to IDE Connector C201 0.1U 0603 50V C182 4.7U 1206 16V 2 2 3 0603 +3VS 2 1 R137 1 G AO3400 +12VS 1 D S D 2 PCI BUS +3VS DTC144WK R138 -BRSTDRV2 1206 -SDIOW SIORDY IRQ15 SDA1 SDA0 -SCS1 R682 1 2 RP514 SA16 SA17 SA18 SA19 (18,19) IRQ1 (18,19) IRQ12 (18) -MEMR 1 2 3 4 5 SA0 SA1 SA2 SA3 1 2 3 4 5 SA16 SA17 SA18 SA19 IRQ1 IRQ12 -MEMR 10 9 8 7 6 4.7K*8/NA RP516 1 2 3 4 5 1206 1 2 3 4 5 SA4 SA5 SA6 SA7 1 2 3 4 5 SDD[8..15] SDD8 SDD9 SDD10 SDD11 SDD12 SDD13 SDD14 SDD15 SDREQ -SDIOR -SDACK SDA2 (13) SDREQ (13) -SDIOR (13) -SDACK (13) SDA2 (13) CDROMPWR Close to IDE Connector D508 EC10QS04 R582 5.6K 0603 GND1 GND2 GND3 GND4 C591 0.1U 0603 50V C595 0.1U 0603 50V C587 4.7U 1206 16V R01 1 -SCS3 +5VS JO500 1 2 OPEN-SMT4 1206 Q503 SA8 SA9 SA10 SA11 SA8 (18) SA9 (18) SA10 (18) SA11 (18) D MTG23 1 S G AO3400 1206 ID2.8/OD5.5 +12VS 1 R577 0603 1M 2 C593 0.1U 0603 50V Q504 2 (13) -CDROM_PWRON DTC144WK R580 1206 1 2 +3VS 10 9 8 7 6 4.7K*8/NA SDD[8..15] 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 FM/25PX2-R/A C12441-X50XX (18) (18) (18) (18) 10 9 8 7 6 4.7K*8/NA RP517 -CDACTP R682 ,D11 For 15" Platform (13) -SCS3 SA4 SA5 SA6 SA7 10 9 8 7 6 4.7K*8/NA RP513 (18,19) SD0 SD1 SD2 SD3 10 9 8 7 6 4.7K*8/NA RP519 SD[0..7] GND1 GND2 GND3 GND4 R29 470/NA 0603 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 1 SD4 SD5 SD6 SD7 SA12 SA13 SA14 SA15 D11 PG1102W 2 (17,19) -CDACTP (18) (18) (18) (18) CABLE_SEL +3VS SD[0..7] SA12 SA13 SA14 SA15 K 1 470 0603 (18) (18) (18) (18) A +5VS 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 1 SDD7 SDD6 SDD5 SDD4 SDD3 SDD2 SDD1 SDD0 ISA BUS (18) SA0 (18) SA1 (18,19) SA2 (18) SA3 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 SDD[0..7] (13) SDD[0..7] CDROM_COMM (17) CDROM_LEFT (17) CDROM_RIGHT (17) To Audio Codec J10 2 -PCI_INTE (13) -PCI_INTF (13) -PCI_INTG (13) -PCI_INTH (13) R36 10K 0603 1206 +3VS -CDROM_RST (13) W/S=16/12/12/16 mils K -PCI_INTE -PCI_INTF -PCI_INTG -PCI_INTH 2 0603 CDROM_COMM CDROM_LEFT CDROM_RIGHT A R37 4.7K 0603 (13) -SDIOW (13) SIORDY (13) IRQ15 (13) SDA1 (13) SDA0 (13) -SCS1 1 33 1 R55 10 9 8 7 6 GND1 GND2 GND3 GND4 +3VS +3VS -PCI_REQ3 (13) -PCI_REQ4 (13) -PCI_REQ5 (13) SERIRQ (13,15,18) 1206 1 2 3 4 5 8.2K*8 1 -PCI_REQ3 -PCI_REQ4 -PCI_REQ5 SERIRQ SDA2 -SCS3 CDROMPWR CDROMPWR CDROMPWR FM/25PX2-R/A/NA C12441-X50XX 1 -PCI_GNT5 -PCLKRUN (13) -PCI_GNT5 (15,16) -PCLKRUN 8.2K*8 RP18 10 9 8 7 6 (13) (13,15) (13,16) (13) -SDACK 2 -PCI_INTD (13,16) -PCI_INTD 8.2K*8 RP17 -PCI_GNT4 -PCI_REQ0 -PCI_REQ1 -PCI_REQ2 GND1 GND2 GND3 GND4 1206 Secondary EIDE Connector 1 2 3 4 5 -PCI_GNT4 -PCI_REQ0 -PCI_REQ1 -PCI_REQ2 10K 0603 2 -PCI_REQA -PCI_INTA -PCI_INTB -PCI_INTC 10 9 8 7 6 (13,15) (13,16) (13) (13) SDD8 SDD9 SDD10 SDD11 SDD12 SDD13 SDD14 SDD15 SDREQ -SDIOR 3 1 2 3 4 5 -PCI_GNT0 -PCI_GNT1 -PCI_GNT2 -PCI_GNT3 CDROM_RIGHT 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 -MCCS -IOR -IOW -MCCS (18,19) -IOR (18,19) -IOW (18,19) 10K 0603 1 -LOCK -SERR -STOP -TRDY -PCI_GNT0 -PCI_GNT1 -PCI_GNT2 -PCI_GNT3 D S 8.2K*8 RP16 CABLE_SEL 2 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 1 (13) -PCI_REQA (10,13,15) -PCI_INTA (13) -PCI_INTB (13,15) -PCI_INTC 1 +3VS 10 9 8 7 6 2 -LOCK -SERR -STOP -TRDY RP15 1 2 3 4 5 1 (13) (13,15,16) (13,15,16) (13,15,16) -DEVSEL -FRAME -IRDY -PERR -DEVSEL -FRAME -IRDY -PERR 2 (13,15,16) (13,15,16) (13,15,16) (13) 2 J23 D12 PG1102W PLACE CLOSE TO VGA PDA2 (13) -PCS3 (13) -PCS1 (13) -HDD_RST (13) R56 33 0603 470 0603 1 6.8K 5% 2 0603 1 (7,10) -AGP_ADSTB1 R71 5.6K 0603 R79 1 1 R576 1 6.8K 5% 2 0603 -AGP_ADSTB1 2 -AGP_ADSTB0 2 2 R551 2K/NA 0603 (7,10) -AGP_ADSTB0 2 +5VS (13) 2 R561 1 6.8K 5% 2 0603 AGP_ST0 AGP_ST1 AGP_ST2 PDD[8..15] PDD8 PDD9 PDD10 PDD11 PDD12 PDD13 PDD14 PDD15 1 -AGP_SERR (10) -AGP_SERR (7,10) AGP_ST0 (7,10) AGP_ST1 (7,10) AGP_ST2 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 2 (7,10) AGP_SBSTB 2 6.8K 5% 1 0603 0603 5% PDREQ -PDIOW -PDIOR PIORDY -PDACK IRQ14 PDA1 PDA0 (13) PDREQ (13) -PDIOW (13) -PDIOR (13) PIORDY (13) -PDACK (13) IRQ14 (13) PDA1 (13) PDA0 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 K R27 AGP_SBSTB 0603 5% R548 6.8K/NA 1 AGP_ADSTB1 0603 5% R557 6.8K 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 2 R578 2 6.8K 5% 1 0603 R550 6.8K 2 (7,10) AGP_ADSTB1 AGP_ADSTB0 PDD[8..15] J14 +1.5VS 1206 8 7 6 5 1 (7,10) AGP_ADSTB0 6.8K*4 R84 4.7K 0603 PDD7 PDD6 PDD5 PDD4 PDD3 PDD2 PDD1 PDD0 1 RP506 1 2 3 4 -AGP_RBF -AGP_WBF -AGP_REQ -AGP_GNT (7,10) -AGP_RBF (7) -AGP_WBF (7,10) -AGP_REQ (7,10) -AGP_GNT 1206 8 7 6 5 R91 10K 0603 PDD[0..7] (13) PDD[0..7] 2 6.8K*4 2 RP507 1 2 3 4 1 -AGP_STOP -AGP_TRDY DDR SDR 533MHZ 400MHZ 1 -AGP_PIPE (7) -AGP_PIPE (7,10) -AGP_STOP (7,10) -AGP_TRDY 0 1 X X X X 0 1 1206 8 7 6 5 2 (7,10) -AGP_IRDY 6.8K*4 1 -AGP_IRDY RP509 1 2 3 4 1 -AGP_DEVSEL -AGP_FRAME (7,10) -AGP_DEVSEL (7,10) -AGP_FRAME 1 1 AGP_ST1 AGP_ST0 MCH STRAP +1.5VS Title HDD, CDROM Connector & PULL-UP RESISTER Size C 1206 R01 Date: A B Document Number Rev 02 411671200001 Friday, December 28, 2001 Sheet 14 of 22 R47 0/NA 0603 For PCMCIA Controller Decoupling Card Bus Socket 1394AVDD CVS1 CVS2 2 2 2 1 1 1 1 2 2 1 +3V Closed to PHY 2 1 2 1 J8 Close to PCI4410 1 1 VPPA ZV_Y[0..7] (10) 1 ZV_Y[0..7] -CCD1 -CCD2 F11 E13 CVS1 CVS2 (10) GND1 GND2 ZV_PCLK (10) ZV_DATA (17) ZV_LRCLK (17) ZV_MCLK (17) 1 2 3 A B GND 1 ZV_SYNC (10) ZV_HREF (10) 0_DFS 5 4 VCC Y +5V R52 4.7K 0603 PCI4410GHK BGA_GHK_209 U9 1 3 4 A0 SDA A1 SCLK A2 WC- GND VCC 5 SDATA 6 SCLK 1 2 C99 0.1U 0603 50V B -1394WR Write Protect when high. -VCCEN0 -VCCEN1 1 C612 0.1U 0603 50V C609 0.1U 0603 50V 1 1 Close to TPS2211 C603 0.1U 0603 50V C600 0.1U 0603 50V 1 2 3 4 5 6 7 8 VCCD0 VCCD1 3.3VA 3.3VB 5VA 5VB GND OC TPS2211 SHDN VDDP0 VDDP1 AVCCA AVCCB AVCCC AVPP 12V SSOP16 16 15 14 13 12 11 10 9 VPPA +12V Close to TPS2211 2 4 VCCA +3V VPPEN0 VPPEN1 2 1 +5V 2 2 GND1 GND2 1 3 L23 2 4 1 2 3 4 +3V C599 0.1U 0603 50V C598 4.7U_NA 1206 16V C601 0.1U 0603 50V C607 4.7U_NA 1206 16V 3 2 L24 PLP3216S CHOKE_PLP3216S R01 A R124 4.99K 0603 1% C199 270P 0603 10% PHY_XI 1 2 2 2 C152 10P 0603 R81 1M_NA 0603 1 1 PHY_XO 1 C134 2 Title 10P 0603 Size PCMCIA/1394 Controller & Socket 2 PHY_AGND Date: 5 -VCCEN1 1 U504 1 2 3 4 1 2 GND1 GND2 X1 24.576MHZ L19 1 120Z/100M 2012 3 Q5 DTC144WK 47K 0603 8 (NA J21 For LCD 15") 2 1 C200 1U 0603 1 1 R116 1M 0603 1% 2 7 1 CCLK R115 56 0603 Meet 6.3K ohm. PHY_AGND TPBTPB+ TPATPA+ 1 1 R104 6.34K 0603 1% TSB41AB1 PQFP64_0.5MM 2 57 58 17 18 63 64 R95 1K 0603 32 33 39 48 49 50 R92 1K 0603 -1394WR (13) R43 (17) TPB1+ CHOKE_PLP3216S PLP3216S 2 40 41 R98 C156 0.1U 110K_NA 0603 0603 50V R106 56 0603 -1394WR 2 PHY_XO 2 PHY_XI 60 R105 56 0603 R53 4.7K 0603 -VCCEN0 1 1 PLLGND0 PLLGND1 DGND0 DGND1 DGND2 DGND3 59 1 1 1 R85 1K 0603 R0 R1 C161 0.1U 50V 0603 2 2 2 2 1 R72 4.7K 0603 CNA PD SE SM AGND0 AGND1 AGND2 AGND3 AGND4 AGND5 3 14 28 29 R83 10K 0603 XO 1 53 27 2 XI LPS CPS 54 55 3 Q4 DTC144WK 1 RESET TESTM 2 47K 0603 2 FILTER0 FILTER1 C/LKON SYSCLK ISO LREQ Close to PHY R42 1 IEEE1394/4P LINKTEK AVR20-4XXX0X 38 47 1 TPBIAS NC4 2 16 56 NC5 PLLVDD NC2 NC3 PC0 PC1 PC2 +3V (17) TPA1+ R103 56 0603 44 43 1 R593 0603 (17) TPA1- TPB+ TPB- 35 34 4 C ZV_SCLK (17) J21 46 45 C93 270P 0603 10% GND3 GND4 NC7S08/NA SC70 2 R38 1 2 1 25 26 61 62 DVDD0 DVDD1 DVDD2 DVDD3 TPB+ TPB- 1 15 24 NC0 NC1 VPPA -CTRDY -CFRAME CAD17 CAD19 CVS2 -CRST -CSERR -CREQ -CCBE3 CAUDIO CSTSCHG CAD28 CAD30 CAD31 -CCD2 (17) TPB1- Close to PHY 1 PHY_LPS A 19 2 23 1 D0 D1 D2 D3 D4 D5 D6 D7 C46 270P 0603 10% 0.635/H5/68P CL640 HIROSE +5VS TPA+ TPA- 37 36 -CCD1 CAD2 CAD4 CAD6 R2_D14 CAD8 CAD10 CVS1 CAD13 CAD15 CAD16 R2_A18 -CBLOCK -CSTOP -CDEVSEL U506 ZV_ACT NM24C02N SO8 U14 TPA+ TPA- 2 PHY_LREQ CTL0 CTL1 1 2 2 R73 10 0603 2 1 1 +3V 1 20 21 22 2 PHY_LKON PHY_CLK 4 5 6 7 8 9 10 11 12 13 R80 1K 0603 +3V CCLK -CIRDY -CCBE2 CAD18 CAD20 CAD21 CAD22 CAD23 CAD24 CAD25 CAD26 CAD27 CAD29 R2_D2 -CCLKRUN 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 2 ZV_UV[0..7] 2 The length TPA+ and TPA- must be the same.Also,TPB+ and TPBmust be the same.Both pair need to be as close the same length as possible. 2 +3V The singals need to be the same,length must not execeed 4 inches C124 0.1U 0603 50V 2 120Z/100M 1608 PHY_D0 PHY_D1 PHY_D2 PHY_D3 PHY_D4 PHY_D5 PHY_D6 PHY_D7 C154 0.1U 0603 50V 1394AVDD L20 1 PHY_CTL0 PHY_CTL1 2 2 +3V 30 31 42 51 52 PHY_AGND C151 0.1U 0603 50V AVDD0 AVDD1 AVDD2 AVDD3 AVDD4 2 1 1 1 2 C175 0.1U 0603 50V 2 2 ZV_UV[0..7] B C162 0.1U 0603 50V C80 10P/NA 0603 10% R579 47K 0603 -CCBE0 -CCBE1 -CCBE2 -CCBE3 L19 A9 C82 0.1U 0603 50V 2 VCCA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 CAD0 CAD1 CAD3 CAD5 CAD7 -CCBE0 CAD9 CAD11 CAD12 CAD14 -CCBE1 CPAR -CPERR -CGNT -CINT 2 C97 0.1U 0603 50V 2 2 C94 0.1U 0603 50V 1 1 1 2 1 1 2 2 E1 J5 M5 R9 R19 L15 H15 A15 E11 A5 P14 W5 GND0 GND1 GND2 GND3 GND4 GND5 GND6 GND7 GND8 GND9 GND10 GND11 M18 M19 V12 U12 VPPD0 VPPD1 VCCD0 VCCD1 VCCCB0 VCCCB1 H19 A12 E7 R10 VCCI VCCL G1 L2 P3 W7 W13 M14 J18 F17 A13 B9 A7 PHY_D0 PHY_D1 PHY_D2 PHY_D3 PHY_D4 PHY_D5 PHY_D6 PHY_D7 B6 C6 F6 B5 E6 C5 A4 D1 RSVD RSVP C96 0.1U 0603 50V 1 P12 P13 CCD1 CCD2 C90 0.1U 0603 50V 2 IBTA INTB J14 F19 F13 B12 C91 0.1U 0603 50V C594 0.1U 0603 50V 2 V13 U13 CC/BE0 CC/BE1 CC/BE2 CC/BE3 ZV_PCLK ZV_DATA ZV_LRCLK ZV_MCLK ZV_SCLK1 ZV_SYNC ZV_HREF D CB_+3V 2 -PCI_INTA -PCI_INTC (10,13,14) -PCI_INTA (13,14) -PCI_INTC C/BE0 C/BE1 C/BE2 C/BE3 M17 M15 N19 N18 P19 V14 W14 VCCA 1 U7 W4 P1 K6 ZV_UV0 ZV_UV1 ZV_UV2 ZV_UV3 ZV_UV4 ZV_UV5 ZV_UV6 ZV_UV7 C98 10U_NA 1206 10V 2 -CBE0 -CBE1 -CBE2 -CBE3 ZV_PCLK ZV_SDATA ZV_LRCLI ZV_MCLK ZV_SCLK ZV_VSYNC ZV_YHREF R17 N14 P15 P17 R18 N15 P18 N17 C89 0.1U 0603 50V 1 2 ZV_Y0 ZV_Y1 ZV_Y2 ZV_Y3 ZV_Y4 ZV_Y5 ZV_Y6 ZV_Y7 C95 0.1U 0603 50V 2 -FRAME -IRDY -TRDY -DEVSEL -STOP 4.7K 0603 -SERR PAR (13,14,16) -SERR (13,16) PAR -CBE[0..3] (13,16) -CBE[0..3] -PCI_GNT0 -PCI_REQ0 2 R13 U14 W15 V15 R14 U15 W16 T19 C92 0.1U 0603 50V 2 +3VS R39 1 0603 100 -FRAME -IRDY -TRDY -DEVSEL -STOP 1 R41 K14 CRSVD0 F18 CRSVD1 B8 CRSVD2 (13,14,16) (13,14,16) (13,14,16) (13,14,16) (13,14,16) CAD0 CAD1 CAD2 CAD3 CAD4 CAD5 CAD6 CAD7 CAD8 CAD9 CAD10 CAD11 CAD12 CAD13 CAD14 CAD15 CAD16 CAD17 CAD18 CAD19 CAD20 CAD21 CAD22 CAD23 CAD24 CAD25 CAD26 CAD27 CAD28 CAD29 CAD30 CAD31 C615 0.1U 0603 50V R2_D14 R2_A18 R2_D2 (13,14) -PCI_GNT0 (13,14) -PCI_REQ0 AD19 ZV_UV(0) ZV_UV(1) ZV_UV(2) ZV_UV(3) ZV_UV(4) ZV_UV(5) ZV_UV(6) ZV_UV(7) CBLOCK CSERR CPERR CSTOP CINT CGNT CDEVSEL CTRDY CIRDY CRST CFRAME CCLKRUN -CBRST G_RST SPKROUT RI_OUT/PME SUSPEND RST GNT REQ IDSEL FRAME IRDY TRDY DEVSEL STOP PERR SERR PAR E19 B10 F14 E18 A10 F15 E17 A16 C15 F12 E14 F10 (13,16) -PME (13,19,22) -SUSB PCLK V11 U10 P9 W12 M3 H1 H2 L1 P2 N5 R1 P6 R2 P5 R3 T1 -CARDSPK -PME (17) -CARDSPK L18 L14 L17 K18 K19 K15 K17 J19 J17 J15 H18 H17 G19 H14 G17 G18 G14 B15 C14 B14 A14 C13 B13 C12 A11 B11 C11 C9 F9 E9 A8 C8 C614 0.1U 0603 50V 1 M6 -CBRST -CBLOCK -CSERR -CPERR -CSTOP -CINT -CGNT -CDEVSEL -CTRDY -CIRDY -CRST -CFRAME -CCLKRUN PCICLK_CARD (8) PCICLK_CARD LPS CREQ CPAR CCLK CAUDIO CSTSCHG LINKON (14,16) -PCLKRUN C F8 E12 G15 D19 C10 E10 A6 -PCLKRUN CAD0 CDA1 CDA2 CAD3 CAD4 CAD5 CAD6 CAD7 CAD8 CAD9 CAD10 CAD11 CAD12 CAD13 CAD14 CAD15 CAD16 CAD17 CAD18 CAD19 CAD20 CAD21 CAD22 CAD23 CAD24 CAD25 CAD26 CAD27 CAD28 CAD29 CAD30 CAD31 ZV_Y(0) ZV_Y(1) ZV_Y(2) ZV_Y(3) ZV_Y(4) ZV_Y(5) ZV_Y(6) ZV_Y(7) PHY_LPS -CREQ CPAR 22 2 0603 CAUDIO CSTSCHG PHY_LKON SCLK ZV_ACT LEDA_SKT SDATA PHY_CTL(0) PHY_CTL(1) 1 R12 TP35 -CARD_RI SERIRQ (19) -CARD_RI (13,14,18) SERIRQ C7 F7 R606 0603 1 2 10K/NA +3V PHY_CTL0 PHY_CTL1 NC7S08 SC70 PHY_LREQ PHY_CLK -CBRST E8 B7 5 4 PHY_LREQ PHY_CLK VCC Y PHY_RSVD0 PHY_RSVD1 PHY_RSVD2 PHY_RSVD3 PHY_RSVD4 PHY_RSVD5 PHY_RSVD6 PHY_RSVD7 PHY_RSVD8 PHY_RSVD9 PHY_RSVD10 PHY_RSVD11 PHY_RSVD12 A B GND U7 PCI4410 uBGA209 E3 F5 G6 E2 F3 F2 G5 F1 H6 G3 G2 H5 H3 1 2 3 (13,16) -PCIRST_N (13) -GATE1394 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 MFUNC0 MFUNC1 MFUNC2 MFUNC3 MFUNC4 MFUNC5 MFUNC6 VCC0 VCC1 VCC2 VCC3 VCC4 VCC5 VCC6 VCC7 VCC8 VCC9 VCC10 M1 V6 +3V U8 U9 V9 W9 W8 V8 U8 R8 V7 P8 W6 R7 U6 V5 P7 R6 U5 N6 N3 N2 N1 M2 L5 L6 L3 K5 K3 K2 K1 J6 J3 J2 J1 W10 V10 P10 W11 U11 P11 R11 PHY_DATA0 PHY_DATA1 PHY_DATA2 PHY_DATA3 PHY_DATA4 PHY_DATA5 PHY_DATA6 PHY_DATA7 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 VCCP0 VCCP1 AD[0..31] (13,16) AD[0..31] D 1 CB_+3V CB_+3V 1 2 VCCA 1 2 SHORT-SMT3 2 R46 0_DFS 0603 1 1 2 +3V JS8 2 -VCCEN0 -VCCEN1 VPPEN0 VPPEN1 2 +5V 1 PCMCIA CONTROLLER & CARD BUS SCOKET 3 +3V 1 4 1 5 3 2 Document Number Rev 02 411671200001 Friday, December 28, 2001 1 Sheet 15 of 22 5 +3V 4 2 1 +3V_LAN 120Z/100M 1608 2 AD[0..31] (13,15) AD[0..31] JS4 2 SHORT-SMT4 JS6 2 D AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 1 SHORT-SMT4 L_GND 2 R164 GND 9346A 0603 R165 5.6K 1 C +3V 0603 2 L_AGND R02 1 0_DFS XTALIN 0603 CLKRUN# XTALOUT NC2 NC3 NC4 R565 15K 0603 L10 1 -STOP (13,14,15) 0_DFS R32 2 2 1 1 1 C597 0.1U 0603 50V C88 0.1U 0603 50V 2 2 1 1 1 1 2 C592 0.1U 0603 50V AVDD_LAN 120Z/100M 1608 2 L_GND 2 0603 -PCI_GNT1 1 C586 0.1U 0603 50V +3V_LAN 21 116 117 2 1 2 AD18 PAR (13,15) 20 2 1 1 2 1 1 2 108 107 105 104 103 102 101 100 CLK GNT# 1 12 25 35 46 58 59 72 73 77 90 96 106 109 119 R696 2 STOP# PERR# 2 0603 C62 0.1U 0603 50V PCICLK_LAN (8) -PCI_GNT1 (13,14) 79 1 C54 4.7U 1206 16V C56 0.1U 0603 50V 1 1 2 3 4 1 R583 100 23 C84 0.1U 0603 50V 1 CS SK DI DO -FRAME (13,14,15) -DEVSEL (13,14,15) -SERR (13,14,15) +3V_LAN R571 1K 0603 1 VCC EECS MA0 MA1 MA2 MA3 MA4 MA5 MA6 MA7 MA8 MA9 MA10 MA11 MA12 MA13 MA14 MA15 MA16 TP18 C86 0.1U 0603 50V C57 0.1U 0603 50V 2 5 PAR 50 47 48 49 51 52 53 57 60 61 63 64 65 66 67 68 69 70 1 15 19 22 95 3 110 C85 0.1U 0603 50V 2 1 8 C69 0.1U 0603 50V 2 RST# NC0 GND PME# LWAKE 97 R584 4.7K 0603 2 U5 L_AGND 1 0_DFS 115 54 85 76 83 TP17 1 LAN_WAKE 1 C87 0.1U 0603 50V +3V 2 +3V_LAN (13,15) -PME (19) LAN_WAKE FRAME# DEVSEL# SERR# ISOLATE# IDSEL ROMCS# 98 +3VS 2 2 0603 LED2 REQ# TRDY# TP16 C81 2.2U 1206 16V 1 1 0/NA 118 17 1 C65 2.2U 1206 16V (13,15) 2 R30 -PCI_REQ1 (13,14) -PCI_REQ1 (13,14,15) -TRDY 99 -CBE[0..3] C583 0.1U 0603 50V 2 C L_AGND C584 10P 0603 2 2 0603 LED1 INTA# IRDY# -CBE0 -CBE1 -CBE2 -CBE3 75 78 88 89 94 4 R566 1M_NA 0603 X501 25MHZ 1 1 LED0 36 24 14 2 3 2 (7,10,13,18) -PCIRST R31 RXIN+ RXIN- -CBE[0..3] 1 0_DFS (13,15) -PCIRST_N TXD+ TXD- 114 16 (13,14) -PCI_INTD (13,14,15) -IRDY CBE0# CBE1# CBE2# CBE3# GND0 GND1 GND2 GND3 GND4 GND5 GND6 NC1 GND8 GND9 RTSET GND11 GND12 GND13 GND14 GND15 87 86 1 7 18 30 40 56 55 62 71 74 80 84 93 111 112 113 124 92 91 RXIN+ RXIN- RTT2 RTT3 VDD0 VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 NC5 NC6 VDD9 VDD10 VDD11 VDD12 VDD13 VDD14 TXD+ TXD- MD0 MD1 MD2 MD3 MD4 MD5 MD6 MD7 82 81 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 45 44 43 42 41 39 38 37 34 33 32 31 29 28 27 26 13 11 10 9 8 6 5 4 128 127 126 125 123 122 121 120 +3V_LAN U4 2 1 1 1 2 L12 D 3 2 C585 10P 0603 RTL8139CL PQFP128A_0.5MM +3V_LAN L_AGND -PCLKRUN (14,15) 1 0_DFS R697 AVDD_LAN 2 0603 L9 120Z/100M 1608 2 1 L_GND L_AGND R23 1.8K 1 0603 2 1% L_AGND RJ45 R01-->R02 J9 GND1 GND2 GND3 GND4 1 2 4 R15 RD+ RDRDC RX+ RXRXC TDC TD+ TD- TXC TX+ TX- NC0 NC1 NC2 NC3 2 2 11 10 9 PJTX+ PJTX- 3 L508 FM/0.8MM/H2.4 AMP C-179373 1 1 22 22 2 0603 2 0603 R61 1 22 2 0603 ACSYNC MSDIN ACSYNC (13,17) MSDIN (13) ACBITCLK ACBITCLK (13,17) C119 10P/NA 0603 PIN 16 LOW AUDIO CODEC ON MOTHER BD AUDIO CODEC ON DAUGHTER BOARD MDC SCREW HOLE 1 1 MTG24 ID2.8/OD5.0 1 2 1 120Z/100M 2012 2 1 J4 5 1 2 3 C502 1000P 1808 3KV 10% S500 Protector 1 L1 2 50UH GND1 GND2 CHOKE_WLT04020201 L22 F500 2 120Z/100M 2012 1 2 mircoSMDC110 C500 1000P 1808 3KV 10% L25 120Z/100M 2012 R02 4 3 2 A SHORT-SMT3 1 2 GND1 GND2 1.016MM/H8.6 OCTEKCONN PJS-OXSXT Title LANPHY,MDC Size 1 1 MDC_GND2 SHORT-SMT3 JO502 1 2 2 ST/MA-2 HIROSE DF13-2P-1.25V 2 GND_45 1 J13 1 2 1808A 1 GND_45 MDC_GND1 MTG25 ID2.8/OD5.0 RJ11 2 2 1 1 2 2 R530 R531 75 75 0603 0603 C566 1000P 1808 3KV 10% 2 SHORT-SMT4 R12 75 0603 L21 2 1 R17 75 0603 JS500 5 R63 R62 PJ7 120Z/100M 1608 1 C120 0.1U 0603 50V JO501 L_AGND 2 MODEM_SPK (17) MDC HARDWARE STRAP PJ4 H0011 XFMR_H0009 PLP3216S CHOKE_PLP3216S B MODEM_SPK CLOSE TO MDC HIGH 12 13 1 4 4 5 2 C40 0.1U 0603 50V R64 4.7K 1 2 0603 PJRX+ PJRX- 16 15 14 1 2 2 C567 22P 0603 2 2 2 1 R65 0603 0_NA 2 1 1 1 1 1 1 2 2 1 6 7 8 L511 1 C657 0.1U 0603 50V +5V U2 R01 1 1 R541 51 0603 2 AVDD_LAN 0603 2 CLOSE TO MDC 1 1 1 R542 51 0603 C572 22P 0603 0_DFS 1 2 2 3 L513 1 2 3 AVDD_LAN ACSDOUT -ACRST 2 RXIN- TXD+ TXD- (13,17) ACSDOUT (13,17) -ACRST 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 2 L_AGND R555 51 0603 FOR EMI +3V GND_45 2 R549 51 0603 1 1 1 2 1 C39 0.1U 0603 50V GND_16 CHOKE_PLP3216S PLP3216S 2 2 キキキキキǐキキ キ, EX: GND SHIELDING S/W/W/S=12/6/6/12 mils as short as possible RXIN+ 1 1 L_AGND 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 8PX1/1.016MM CONN_PJS-AST_8 JO516 JO31 JO32 JO35 JO30 JO512 C577 0.1U 0603 50V +3V J11 MONO_OUT (17) MONO_OUT Layout Note: A FOR ESD ISSUE GND1 GND2 GND3 GND4 2 B 1 2 3 4 5 6 7 8 1 PJ4 PJRX+ PJTXPJTX+ Modem Dougther Board 1 2 3 4 5 6 7 8 PJ7 PJRX- 2 Date: Document Number Rev 02 411671200001 Friday, December 28, 2001 1 Sheet 16 of 22 5 4 3 2 1 AUDIO CODE & AMPLIFIER +5VS +3VS_SPD +3VS L540 10V 1U 1 2 C164 32 0603 10V 1U 1 2 C160 33 1 2 C158 2 +5VS 34 AGND 1 0.1U_NA 2 2 50V 0603 C165 2 0.1U 50V 0603 A B GND VCC Y 5 4 1 0603 2 1 AFLT1 AFLT2 2 0.1U 0603 50V R647 20K 0603 R02 CHIP ALC201 Cap pin31: 1U Cap pin32: 1U Cap pin33: 1U Cap p33/34 X CS4299 2 2 1 1K 2 0603 19 C192 1 2 1U 10V 0603 R133 1 16 C189 1 2 1U 10V 0603 VIDEO_L 17 C190 1 2 1U 10V 0603 VIDEO_R 14 C186 1 2 1U 10V 0603 15 C202 1 2 1U 10V 0603 13 C185 1 2 1U 10V 0603 37 C142 1 2 1U 10V 0603 39 C141 1 2 1000P 50V 0603 41 C132 1 2 1000P 50V 0603 29 C173 1 2 1000P 50V 0603 30 C174 1 2 1000P 50V 0603 2 0 1 CDROM_RIGHT R01 AGND AGND (14) CDROM_LEFT (14) CDROM_COMM 0603 AVDDAD CDROM_COMM (14) ZV AUDIO U512 R141 0 0603 100K 0603 CDROM_RIGHT CDROM_LEFT 2 R140 100K 0603 7 8 5 6 AGND C697 0.1U/NA 0603 50V MONO_OUT VA+ AOUTL AOUTR AGND ZV_DATA ZV_SCLK ZV_LRCLK ZV_MCLK 1 2 3 4 SDATAI SCLK LRCK MCLK CS4334/NA SO8 C MONO_OUT (16) INTERNAL MICROPHONE J16 1 2 C676 47P_NA 0603 20mil Very Close to Codec ALC201 PQFP48_0.5MM C172 0.1U 0603 50V X C180 0.1U 0603 50V R657 0_DFS 0603 C133 1000P/NA 0603 C179 1U 0603 10V AGND AVDDAD R01 R663 40.2K/NA 0603 1% 2 AGND AGND AGND HIROSE ST/MA-2 DF13-2P-1.25V AGND R653 0_DFS 0603 0.01U X ZV_DATA (15) ZV_SCLK (15) ZV_LRCLK (15) ZV_MCLK (15) AGND 28 VREFOUT 1 R142 AOUT_R 27 REFFLT AGND R01 AOUT_L 2 R649 47K 0603 1 2 ALT_LINE_OUT_L ALT_LINE_OUT_R C670 R646 200K 0603 NC7S32 SC70/SOT70 SPDIFOUT 2 50V R132 1 2 1 1 (15) -CARDSPK 1 2 3 1 0.1U_NA DVSS1 DVSS2 U510 C669 -CARDSPK 0.1U 50V 0603 0603 36 MONO_OUT NC1 NC2 NC3 ID0# ID1# EAPD S/PDIF_OUT 10V 35 PHONE 4 7 0603 1 SBSPKR (13) SBSPKR 50V LINE/OUT/R AVSS1 AVSS2 1 C675 0.1U 1 2 LINE/OUT/L FLTI FLTO 40 43 44 45 46 47 48 C159 C667 FLT3D 26 42 C 0603 50V 1000P_NA 1U MIC 0603 2 0603 2 1 1 2 C167 10P 0603 AUX/R BPCFG 1K C191 1 1 31 R134 1 18 2 2 C163 0603 1 1 0603 10V 2 10V 1U 10V 1U 1 0603 1U 2 2 2 24.576MHZ 1 C148 10P 0603 AUX/L 2 C193 1 2 VIDEO/L PC_BEEP VIDEO/R 1 MODEM_SPK (16) MIC C188 1 20 2 XTL/OUT X2 0603 22 1 CD/GND 12 10V 1 CD/R XTL/IN 3 1M +80-20% 1U 1 2 0603 0805 2 2 MIC2 CD/L 2 1 R88 2 2.2U C194 1 MIC2 MODEM_SPK 2 0603 C687 0.1U_NA 0603 50V 2 25 38 MIC1 CLOSE TO CODEC C183 1 MIC1 R655 1K 0603 1 2 0603 +80-20% 10K 2 (13,16) ACBITCLK 22 1 R648 0805 1 ACBITCLK 2 2.2U 21 24 LINE/IN/R RESET# SDATA/OUT SDATA/IN SYNC BIT/CLK C196 1 2 11 5 8 10 6 23 LINE/IN/L 1 R02 1 2 0603 R652 BEAD 0805C AGND 2 22 1 R645 ACSYNC (13,16) ACSYNC AGND U15 AVDD1 AVDD2 1 9 ACSDIN (13) ACSDIN DVDD1 DVDD2 ACSDOUT (13,16) ACSDOUT AGND AGND 1 -ACRST AGND 2 HDR/MA/1.27MM/NA (13,16) -ACRST C674 0.1U 0603 50V 2 R02 D Close to 78L05 L522 1 R01 3 I GND C684 10U 1206 10V SPKLOUT- S100-0112-321 SPEED O 2 C672 0.1U 0603 50V 1 120Z/100M 2012 1 1 C702 0.1U 0603 50V 2 C668 0.1U 0603 50V 2 C665 0.1U 0603 50V 1 1 1 C146 10U_NA 1206 10V 2 T_CLK (18,19) -SCROLL (12,19) -NUM (12,19) -CDACTP (14,19) 2 Close to Codec R109 6.8K_DFS 5% +12VS U511 L78L05ACU SOT89N 1 Close to Codec C666 10P 0603 1 T_CLK -SCROLL -NUM -CDACTP AVDDAD 2 ACBITCLK TPA1- (15) TPA1+ (15) 1 R121 6.8K_DFS 5% L14 120Z/100M 1608 2 -CAP -HDDACTP SPKLOUT+ (12,19) -CAP (14,19) -HDDACTP SPKROUTVR1_5 AOUT_R LINE_OUT_2 MIC_3 MIC_2 TPA1TPA1+ 2 +5V 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 2 T_DATA SPDIFOUT (18,19) T_DATA 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 1 (15) TPB1(15) TPB1+ 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 2 D 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 SPKROUT+ VR1_2 AOUT_L LINE_OUT_5 -DEVICE_DECT -DECT_HP/OPT TPB1TPB1+ 1 J17 1 (ADD J17 For LCD 15") AGND AGND AGND AGND AGND 2 1000P 1 1 AGND 2 120Z/100M 2012 +5VS 2 VCC+ 1OUT 1IN+ 1IN- 2OUT 2IN+ 2INVCC- 0603 R02 AGND 7 5V_AMP C704 2 5V_AMP R676 2 0603 2 2.2U 10K 0805 +80-20% R665 0603 1 2 15K 1% 1% 8 30 31 32 33 34 C692 1 470P 2 0603 10% VR1_2 AGND AGND C707 1 R675 2 1 2.2U 10K 0805 +80-20% 0603 2 1% 14 16 11 9 SE/BTL# HP/LINE# MUTE IN MUTE OUT NC0 NC1 NC2 10% G6 G7 G8 G9 G10 G1 G2 G3 G4 G5 TPA0202_GND + C168 0.1U 0603 50V AGND 25 26 27 28 29 HI Shut Down LOW AGND AGND 1 1 1 AGND 2 1 2 1 0603 C688 100P 0603 2 1 4.7K 2 -DECT_HP/OPT R673 0603 L528 120Z/100M 1608 1 2 L531 120Z/100M 1608 SPDIFOUT 1 2 1 L539 3 AGND 2 3 1 R685 10K 0603 Q10 R1 2 -DEVICE_DECT 1 2 4 3 1 +3VS_SPD Q514 +3VS DTA144WK 1 R149 100K 0603 AGND 2 120Z/100M 1608 4 R02 AGND C705 220P/NA 0603 10% RA/D3.6/5P HCH IDJ-B27-F6T C696 220P/NA 0603 10% 1608 1 2 L530 120Z/100M AGND CAGND 6 11 Drive IC LED L532 3 4 (NA L523,L524,L536,L532, L527,L528,L531,L537,L538, L539,J19 For LCD 15") A L536 L527 120Z/100M 1608 3 Q515 DTC144TKA 1 R1 2 -DECT_HP/OPT CHOKE_PLP3216S PLP3216S CHOKE_PLP3216S PLP3216S Title DTC144TKA AUDIO CODEC & AMPLIFIER Size Normal -DEVICE_DECT 3 B C701 25V 0805 Date: 5 1 2 L525 120Z/100M 1608 J19 5 4 2 3 1 7 8 9 1 2 0603 2 5 4 3 2 1 2F1138-TJ1 FOXCONN CAGND R113 10U 10V 1206 AGND L537 120Z/100M 1608 1 2 1 2 L538 120Z/100M 1608 120Z/100M 1608 5V_AMP R151 6.8K 0603 5% C209 2 MIC_3 MIC_2 Line Out Phone Jack 5V_AMP 2 1K 0603 1 C689 100P 2 2 2 C166 + 100U 16V EW6.3 TSSOP24_TPA0102 100K 0603 SPK_OFF C206 0.1U 0603 50V R102 47K 0603 1 Signal 0603 + 2 17 23 5 6 4 AGND L529 Very Close to TPA0202 Pin 18/7 SHUTDOWN 0603 1 R664 2 10K 1% C691 1 2 0603 470P 220U 10V EW6.3 1 2 R122 22K 1 AGND 2 MUTE_IN R02 R143 1K C204 L523 120Z/100M 1608 1 2 10% 0603 2 External Micro Phone Jack J22 R02 0.068U 1 AGND 18 7 LINE_OUT_2 2 AGND L 1 12 13 24 0603 2 1 C207 1U 0603 R 1 2 2 C169 1U 0603 2 1 GND0 GND1 GND2 GND3 1 2 SPKLOUT+ SPKLOUT- 1 C708 L BYPASS R BYPASS SPKROUT+ SPKROUT- 3 10 L524 120Z/100M 1608 LINE_OUT_5 1 2 2 6 19 10% JO34 1 RVDD LVDD 2 0603 1 470P AGND JO33 LLINE IN LHP IN 22 15 1 0603 2 1% L OUT+ L OUT- 2 2 1 1 R01 2 1 2.2U 10K 0805 +80-20% C693 R OUT+ R OUT- 1 1 +80-20% R677 RLINE IN RHP IN -DEVICE_DECT J20 HIROSE ST/MA-2 DF13-2P-1.25V J18 HIROSE ST/MA-2 DF13-2P-1.25V 220P 1 R679 R659 10K 0603 Internal Speaker Connector Amplifier 1 1 0805 C709 4 5 2 5 7 6 3 0603 1 R666 2 10K 1% 1 2 2 A 1 C718 4.7U 21 20 VR1 10K EW6.3 2 (NA J20,J18 For LCD 15") U18 10% 2 AOUT_L +80-20% 4 C210 220U 10V 1 2 0603 1 VR1_5 C717 4.7U 0805 AOUT_R 1 2 120Z/100M 2012 C694 470P AOUT_R/L Cap x2 - SIZE0805 R02 R667 0603 1 2 15K 1% 2 (NA VR1,C717,C718 For LCD 15") 0603 2 1% 1 R678 2 1 2.2U 10K 0805 +80-20% 2 C710 1 3 2 MC33078D L26 1 (NA J22,L525, L530 For LCD 15") 1608 AGND R671 4.7K 1 U513 8 1 2 R167 0/NA L535 1 DTC144TKA 0603 2 2 Q16 L18 MUTE_IN 3 R148 68K 0603 120Z/100M_DFS R6800/NA 1 1 (13) SPK_OFF B 1 0603 2 C68610U 10V 1206 1 2 1 SPK_OFF 2 R1 AGND 2 120Z/100M 2012 R670 47K 1 1 R669 47K 0603 1 2 C700 0.1U 0603 50V 2 1000P 0603 2 1 270P R166 10K 0603 1 2 2 1 1 Cap. pin30: 1000P R668 2.7K 1 AVDDAD 2 1000P 12 CS4299 270P 2 ALC2000 1 L17 AD1881 Cap. pin29: 1000P L.CH +5VS R.CH CHIP +3V_ICH 2 Document Number Rev 02 411671200001 Friday, December 28, 2001 1 Sheet 17 of 22 A B (NA L13,L15,L16,C139, C149,C135,J15 For LCD 15") TOUCH_PAD +5V L13 120Z/100M 1608 2 1 T_DATA L15 1 T_CLK L16 1 (17,19) T_DATA (17,19) T_CLK 2 120Z/100M 2 120Z/100M 1 2 3 4 1608 1608 J501 J15 TP_VCC DATA CLK HIROSE ST/MA-4 1 J500 GND2 GND1 2 1 C149 C135 47P 0.1U 0603 0603 50V 2 2 1 DF13-4P-1.25V C139 47P 0603 HIROSE ST/MA-4 DF13-4P-1.25V 1 2 3 4 TP_GND D3 8 7 6 5 4 3 2 1 2 3 SW2 RIGHT LEFT 1 2 5 SCRL_UP SCRL_DOWN 1 3 4 BAV99 RIGHT 12V/50MA STS-042-A D4 2 ACES HDR/MA-8 88206-0800 3 SW3 1 2 5 TP_GND 1 3 4 BAV99 LEFT 2 Flash ROM SD[0..7] (14,19) SD[0..7] SA[0..17] SD0 SD1 SD2 SD3 SD4 SD5 SD6 SD7 1 +5VS 2M ROM------PULL VCC 4M ROM------SA18 R162 0/NA 0603 1 (14) SA18 O0 O1 O2 O3 O4 O5 O6 O7 2 R163 13 14 15 17 18 19 20 21 2 0_DFS 1 0603 VPP +5VS Close to EEPROM 32 2 1 R01-->R02 C123 0.1U 0603 50V 16 Flash ROM U12 VCC A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 CE# OE# WE# VSS 12 11 10 9 8 7 6 5 27 26 23 25 4 28 29 3 2 30 22 24 SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 -ROMCS -MEMR 31 -MEMW 2 12V/50MA STS-042-A SA[0..17] (14,19) D1 2 3 SW1 1 2 5 1 3 4 BAV99 SCRL UP 12V/50MA STS-042-A D6 2 3 SW4 1 2 5 1 3 4 BAV99 SCRL DOWN 12V/50MA STS-042-A TP_GND -ROMCS (19) -MEMR (14) TP_GND 28F020-PLCC STRAP OPTION 1 (14) (14) (14,19) (14) SA0 SA1 SA2 SA3 -XSTB XCNF2 IRQ1 IRQ12 SA0 SA1 SA2 SA3 TP545 1 (14,19) IRQ1 (14,19) IRQ12 -IOR -IOW SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 -IOR -IOW SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 1 1 1 2 2 2 DCD1# DSR1# SIN1 RTS1#/TEST SOUT1/XCNF0 CTS1# DTR1#_BOUT1/BADDR RI1# -COM1DCD -COM1DSR COM1RXD -COM1RTS COM1TXD -COM1CTS -COM1DTR -COM1RI 70 69 68 67 66 IRTX IRRX FIRSEL +3VS R640 10K 0603 P_SLCT (22) P_PE (22) P_BUSY (22) -P_ACK (22) -P_SLIN (22) -P_INIT (22) -P_ERR (22) -P_AFD (22) -P_STB (22) +3VS IRTX IRRX1 IRRX2_IRSL0 IRSL1 IRSL3/PWUREQ# XD0/GPIO00/JOYABTN1 XD1/GPIO01/JOYBBTN1 XD2/GPIO02/JOYAY XD3/GPIO03/JOYBY XD4/GPIO04/JOYBX XD5/GPIO05/JOYAX XD6/GPIO06/JOYBBTN0 XD7/GPIO07/JOYABTN0 XWR#/XCNF1 XRD#/GPIO34/WDO# XIOWR#/XCS1#/MTR1#/DRATE0 XIORD#/GPIO37/IRSL2/DR1# XCS0#/DR1#/XDRY/GPIO25 PC87393 +3VS R644 10K 0603 COM1TXD XCNF0 -MEMW XA0/GPIO20 XA1/GPIO21 XA2/GPIO22 XA3/GPIO23 XA4/GPIO24/XSTB0# XA5/XSTB1#/XCNF2 XA6/GPIO26/PRIQA/XSTB2# XA7/GPIO27/PIRQB XA8/GPIO30/PIRQC XA9/GPIO31/MTR1#/PIRQD XA10/GPIO32/XIORD#/MDRX XA11/GPIO33/XIOWR#/MDTX XA12/GPIO10/JOYABTN1/RI2# XA13/GPIO11/JOYBBTN1/DTR2#_BOUT2 XA14/GPIO12/JOYAY/CTS2# XA15/GPIO13/JOYBY/SOUT2 XA16/GPIO14/JOYBX/RTS2# XA17/GPIO15/JOYAX/SIN2 XA18/GPIO16/JOYBBTN0/DSR2# XA19/DCD2#/JOYABTN0/GPIO17 LATCH MODE ,XA12-19, XRDY ENABLE 1 1 0 LATCH MODE , GPIO 10-17 , XRDY ENABLE 0 1 1 LATCH MODE , XA12-19, XRDY DISABLE 1 1 1 LATCH MODE , GPIO 10-17 ,XRDY DISABLE NORMAL MODE , XRDY DISABLE R303 INDEX REGISTER DATA REGISTER MOUNTED 4EH 4FH OPEN 2EH 2FH +3VS 1 55 56 57 58 59 60 61 62 0 R643 10K/NA 0603 R635 10K 0603 2 DSKCHG# HDSEL# RDATA# WP# TRK0# WGATE# WDATA# SETP# DIR# DR0# MTR0# INDEX# DENSEL DRATE0/IRSL2 35 36 37 40 41 47 49 51 53 54 PIO/-PNF P_SLCT P_PE P_BUSY -P_ACK -P_SLIN -P_INIT -P_ERR -P_AFD -P_STB 1 1 BASE ADDRESS SELECT 1 CLKIN P_LPD0 P_LPD1 P_LPD2 P_LPD3 P_LPD4 P_LPD5 P_LPD6 P_LPD7 2 PNF/XRDY SLCT/WGATE# PE/WDATA# BUSY_WAIT#/MTR1# ACK#/DR1# SLIN#_ASTRB#/STEP# INIT#/DIR# ERR#/HDSEL# AFD#_DSTRB#/DENSEL STB#_WRITE# 52 50 48 46 45 44 43 42 0 (22) 1 PD0/INDEX# PD1/TRK0# PD2/WP# PD3/RDATA# PD4/DSKCHG# PD5/MSEN0 PD6/DRATE0 PD7/MSEN1 P_LPD[0..7] J506 -COM1DCD -COM1DSR COM1RXD -COM1RTS COM1TXD -COM1CTS -COM1DTR -COM1RI 1 2 3 4 5 6 7 8 9 10 11 12 +3VS XCNF1 IRTX (22) IRRX (22) FIRSEL (22) 1 2 3 4 5 6 7 8 9 10 11 12 1 FFC-12P/0.5MM/NA SD0[0..7] 3 2 1 100 99 98 97 96 SD0 SD1 SD2 SD3 SD4 SD5 SD6 SD7 4 5 73 71 72 -MEMW -MEMR -MCCS -ROMCS SD[0..7] (14,19) U11 SD0 SD1 SD2 SD3 SD4 SD5 SD6 SD7 -MEMR (14) -MCCS (14,19) -ROMCS (19) 3 4 7 8 13 14 17 18 1 11 -XSTB D0 D1 D2 D3 D4 D5 D6 D7 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 OC G VCC GND SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 2 5 6 9 12 15 16 19 20 10 SA4 (14) SA5 (14) SA6 (14) SA7 (14) SA8 (14) SA9 (14) SA10 (14) SA11 (14) +3VS C105 0.1U 74AHC373_V R58 10K 0603 VSS0 VSS1 VSS2 VSS3 (14,19) (14,19) (14) (14) (14) (14) (14) (14) (14) (14) 95 94 93 92 91 90 87 86 85 84 83 82 81 80 79 78 77 76 75 74 LCLK LRESET# LFRAME# LDRQ# LPCPD# CLKRUN#/GPIO36 SERIRQ SMI#/GPIO35 P_LPD[0..7] 2 21 22 23 24 25 26 27 28 29 30 31 32 33 34 50V 0603DA NO BIOS X 0 1 20 50V 0603DA TSSOP20 2 (8) SIO_14.318MHZ 50V 0603DA FUNCTIONALITY 0 282574373004 50V 0603DA 2 R01 50V 0603DA 1 (13,14,15) SERIRQ +3VS 8 9 12 11 7 6 10 19 C664 0.1U XCNF0 0 1 1 PCICLK_LPC -PCIRST -LFRAME -LDRQ -LPCPD -CLKRUN SERIRQ 1 10K/NA 2 R641 0603 SIO_14.318MHZ (8) PCICLK_LPC (7,10,13,16) -PCIRST (13) -LFRAME (13) -LDRQ LAD0 LAD1 LAD2 LAD3 C656 0.1U XCNF1 X 2 2 0_DFS 0603 R01 15 16 17 18 C653 0.1U XCNF2 13 38 64 89 1 R639 10K/NA 0603 2 (10,13) -SUS_STAT R637 10K 0603 2 R638 -SUS_STAT +3VS 1 +3VS LAD0 LAD1 LAD2 LAD3 VDD0 VDD1 VDD2 VDD3 U509 LAD[0..3] (13) LAD[0..3] C660 0.1U 14 39 63 88 2 1 +3VS 284587393002 PQFP100_0.5MM MITAC INTERNATIONAL CORP. Title TOUCH PAD,BIOS,SUPER-IO Size Document Number Custom 411671200001 Date: A B Friday, December 28, 2001 Rev 02 Sheet 18 of 22 A 3 1 D501 MODE1 Expended mode with On-Chip ROM disable 1 0 MODE2 Expended mode with On-Chip ROM enable 1 1 MODE3 Single-Chip mode BAV99 +5VA 2 Close to H8-3437F 1 1 JO16 2 1 JO18 2 1 JO20 1 JO17 2 1 JO19 2 1 JO22 2 1 JO21 2 1 JO24 2 1 JO23 2 1 JO26 2 1 JO25 2 1 JO27 SD0 SD1 SD2 SD3 SD4 SD5 SD6 SD7 SD[0..7] (14,18) SD[0..7] FPC/FFC/1MM/24P 85203-24-02 ACES (14,18) IRQ1 (14,18) IRQ12 PWR_ON (22) PWR_ON (22) LEARNING +5VS R1 H8_SCI 2 DTC144TKA D K 2 1 R617 1K 0603 2 CHARGING C720 + 220U/NA 7343 10V FAN Off 2 -ADEN (20) T_CLK (17,18) +5VA Q510 R1 +3V_ICH 2 R02 0603 X503 2 16MHZ C633 TXC8X4.5 68P 0603 5% C630 68P 0603 5% 2 (12) -H8_RESET (14,18) -MCCS (13) -RCIN 1 3 4 7 8 11 -MCCS -RCIN 14 17 18 21 22 K Signal LOW HI R68 FAN0_SPD -DC/DC_FAN FAN Off FAN On (20) -SW_+5VA 1 2 0/NA 0603 R67 0_DFS 0603 2 DF13-3P-1.25H 1 13 1A1 1A2 1A3 1A4 1A5 2A1 2A2 2A3 2A4 2A5 1OE# 2OE# 1B1 1B2 1B3 1B4 1B5 2B1 2B2 2B3 2B4 2B5 VCC GND 2 5 6 9 10 -H8_SMI H8_PWROK H8_A20GATE -H8_KBCS -H8_THRM 15 16 19 20 23 -H8_MCCS -H8_RCIN +5VA RP515 3 1 2 3 4 5 -ADEN H8_MODE0 H8_MODE1 10 9 8 7 6 -RI -BATT_DEAD -POWERBTN Threshold : 4.38V 10 9 8 7 6 KI4 KI5 KI6 KI7 47K*8 1206 RP512 KI0 KI1 KI2 KI3 1 2 3 4 5 47K*8 BAT_CLK R631 1 BAT_DATA R623 1 1206 2 10K 0603 2 10K 0603 1 +5VS +5VA +5V JS9 24 12 1 SN74CBTD3384 QSOP24A R01 2 RP511 SHORT-SMT3 1 FAN 1 2 3 D 1 1 2 3 VCC R66 10K 0603 2 -EXTSMI PWROK ICH_A20GATE -ROMCS -THRM T_CLK T_DATA -LID JO28 1 2 Close to 74CBTD3384DBQ 1 2 3 4 OPEN-SMT3 1 -FAN0 RESET# +5VA R78 10K 0603 2 1 S R1 470K 0603 SOT23N 1 -H8_WAKE_UP Level Shift J502 Q1 AO3401 G 2 1 2 A 1 2 D5 RLS4148 C4 0.1U 0603 50V D S -DC/DC_FAN Control (13) -EXTSMI (13) PWROK (13) ICH_A20GATE (18) -ROMCS (13) -THRM G R688 10K 0603 1 DTC144TKA U13 Close to SI2301DS R01 +5VA +5VA U10 ADM809 2 3 Q9 External Pull Up/Down For H8-3437F Reset 1 -WAKE_UP LAN_WAKE (16) BATT_DEAD (20) C636 0.1U 0603 50V R1 (13) -WAKE_UP +5V (15) 10K 0603 2 +5VA +5VS -CARD_RI Q512 DTC144WK DTC144TKA LOW FAN On 50V 0603 2 2 LAN_WAKE 2 BATT_DEAD 1 2 -FAN 0.1U 1 GND FAN1_SPD -PWRBTN (13) 3 Q513 1DTC144TKA (22) T_DATA (17,18) 1 FAN HIROSE ST/MA-3 DF13-3P-1.25V -PWRBTN R1 -H8_ICH2BTN Q511 2 S 1 ICN2 INTERNAL PULL UP R139 10K/NA 0603 -PWRSW R622 1 HI (NA C638,R629,SW6 For LCD 15") 2 3 -SCI +3V_ICH LED_CLK (12) LED_DATA (12) R627 3 Signal C634 0.1U 50V 0603 SW_+5V A (20) T_CLK -H8_STBY -H8_SUSB -H8_RESET 2 2 RLS4148 1 2 3 1 -ADEN H8_PWROK 1 1 A 2 1 D7 D S CPU_FAN Control (13) -SCI +5V R660 10K 0603 C662 1M R642 470K 0603 Q509 AO3401 G Suspend AGND -LID (22) 1 C659 0.1U 0603 50V -LID 3 4 MPU-101-80 -IOR (14,18) -IOW (14,18) T_DATA -RI -BATT_DEAD PQFP100_0.5MM H8/F3437S G R687 10K 0603 2 +5V Close to SI2301DS R01 J7 -H8_WAKE_UP -H8_SMI H8_SCI IRQ1 IRQ12 -FAN0 -FAN1 H8_PWRON -H8_RCIN LEARNING KI0 KI1 KI2 KI3 KI4 KI5 KI6 KI7 1 2 1 2 2 1K 0603 2 2 C638 2.2U 16V 1206 Normal SW6 1 1 JO15 1 CHG_I (22) BLADJ (22) SA2 (14,18) BLADJ SA2 H8_A20GATE -H8_KBCS -IOR -IOW -H8_MCCS BAT_CLK -H8_SUSC -LID -POWERBTN -H8_THRM SW_+5V A -H8_ICH2BTN H8_A20GATE BAT_DATA H8_MODE0 H8_MODE1 LED_CLK LED_DATA FAN0_SPD FAN1_SPD CHARGING LOW 3 2 1 JO14 Micro Controller HI 1 1 JO13 2 R629 2 1 JO11 2 H8_THRM_DATA (4) Signal Cover Switch 1 1 JO9 2 38 39 40 41 42 43 44 45 93 94 95 96 97 98 99 25 24 23 22 19 18 17 16 6 5 91 90 81 80 69 68 58 57 48 47 31 30 21 20 11 10 8 7 1 2 3 100 P70/AN0 P71/AN1 P72/AN2 P73/AN3 P74/AN4 P75/AN5 P76/AN6/DA0 P77/AN7/DA1 P80/HA0 P81/GA20 P82/CS1 P83/IOR P84/IRQ2/TXD1/I P85/IRQ4/RXD1/C P86/IRQ5/SCK1/S P90/IRQ2/ESC2 P91/IRQ1/EIOW P92/IRQ0 P93/RD P94/WR P95/AS P96/0 P97/WAIT/SDA MD0 MD1 PB0/XDB0 PB1/XDB1 PB2/XDB2 PB3/XDB3 PB4/XDB4 PB5/XDB5 PB6/XDB6 PB7/XDB7 PA0/KEYIN8 PA1/KEYIN9 PA2/KEYIN10 PA3/KEYIN11 PA4/KEYIN12 PA5/KEYIN13 PA6/KEYIN14 PA7/KEYIN15 /STBY/FVPP /NMI /RES XTAL EXTAL /RESO 1 2 2 H8_THRM_CLK (4) 2 1 JO12 P10/A0 P11/A1 P12/A2 P13/A3 P14/A4 P15/A5 P16/A6 P17/A7 P20/A8 P21/A9 P22/A10 P23/A11 P24/A12 P25/A13 P26/A14 P27/A15 P30/HDB0/D0 P31/HDB1/D1 P32/HDB2/D2 P33/HDB3/D3 P34/HDB4/D4 P35/HDB5/D5 P36/HDB6/D6 P37/HDB7/D7 P40/TMCI0 P41/TMO0 P42/TMRI0 P43/TMCI1/HIRQ1 P44/TMO1/HIRQ1 P45/TMRI1/HIRQ1 P46/PW0 P47/PW1 P50/TXD0 P51/RXD0 P52/SCK0 P60/KEYIN0/FTCI P61/KEYIN1/FTOA P62/KEYIN2/FTIA P63/KEYIN3/FTIB P64/KEYIN4/FTIC P65/KEYIN5/FTID P66/KEYIN6/IRQ6 P67/KEYIN7/IRQ7 BAT_T (20) BAT_V (20) BAT_C (20) BAT_D (20) 1 1 JO10 2 79 78 77 76 75 74 73 72 67 66 65 64 63 62 61 60 82 83 84 85 86 87 88 89 49 50 51 52 53 54 55 56 14 13 12 26 27 28 29 32 33 34 35 2 2 1 JO7 2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 C663 0.1U 0603 50V GND_H8 1 VCC1 VCC2 AVCC VCCB U508 C661 0.1U 0603 50V 2 1 JO8 KO0 KO1 KO2 KO3 KO4 KO5 KO6 KO7 KO8 KO9 KO10 KO11 KO12 KO13 KO14 KO15 R4 10K 1% Come From Battery BAT_T BAT_V BAT_C BAT_D 8 7 6 5 2 JP_BEAD_DFS 0603B_DFS 1 RP510 1K*4 1206 2 1 2 3 4 1 1 1 L521 2 2 1 JO5 2 Internal Keyboard Connector 1 JO6 BAT_TEMP BAT_VOLT 5 6 7 8 D506 4 3 2 1 1 GND_H8 2 RP518 33*4 1206 2 GND_H8 2 J12 2 BAV70LT1 R636 10K 0603 3 EASY START BTN/LED INDICATOR 2 +1.8VS BAV99 SPEED S100-0000-101 HDR/SHR/MA/5PX2 1 JO4 D510 C655 0.1U 0603 50V 2 -SCROLL_KI1 -NUM_KI2 -CAP_KI3 -CDACTP_KI4 2 4 6 8 10 +5VS_LEDB KO0 KO1 KO2 KO3 KO4 KO5 KO6 KO7 KO8 KO9 KO10 KO11 KO12 KO13 KO14 KO15 KI0 KI1 KI2 KI3 KI4 KI5 KI6 KI7 C654 0.1U 0603 50V D504 J5 1 3 5 7 9 +5VS D507 120Z/100M 1608 C658 0.1U 0603 50V 1 3 1 C632 0.1U 0603 50V 70 71 92 15 46 36 2 C631 0.1U 0603 50V 1 1 1 2 3 -HDDACTP_KO1 KO0 -PWRSW +5V Close to H8-3437F 2 1 BAV99 3 +5VA +5VS 1 3 D502 12 H8_VDD5 L520 3 1 D505 BAV99 I_LIMIT (22) 2 +5V 24 SN74CBTH3383/NA SSOP24 2 C527 1U_NA 0603 1 1 GND BAV99 2 5 9 15 19 23 Description 0 2 BE MD0 MD1 MODE +5VA VSS1 VSS2 VSS3 VSS4 AVSS AVREF 1 VCC L 9 59 37 4 D503 BAV99 1 100K/NA 2 R692 0603 BX L H 1 R691 0603 1B2 2B2 3B2 4B2 5B2 L 2 13 1A2 2A2 3A2 4A2 5A2 -SCROLL_KI1 -NUM_KI2 -CAP_KI3 -CDACTP_KI4 -HDDACTP_KO1 2 6 10 16 20 1 1 10K/NA 2 1B1 2B1 3B1 4B1 5B1 2 -SCROLL 4 -NUM 8 -CAP 14 -CDACTP 18 -HDDACTP 22 -SCROLL -NUM -CAP -CDACTP -HDDACTP 1A1 2A1 3A1 4A1 5A1 H8 Mode Select Table 1 3 7 11 17 21 3 1 QK-B LED U515 KI1 KI2 KI3 KI4 KO1 BE# 1 BAV99 2 BX 2 +5VA (12,17) (12,17) (12,17) +5VS_LEDB (14,17) (14,17) B NA RP521,R693,R691 FOR 8175 QK-B NA RP521,R693,R692 FOR 8175 LED-B -SCROLL_KI1 -NUM_KI2 -CAP_KI3 -CDACTP_KI4 -HDDACTP_KO1 2 RP521 1206 0*4 1 8 2 7 3 6 4 5 1 2 R693 0 0603 KI1 KI2 KI3 KI4 KO1 C121 0.1U 0603 50V 8 7 6 5 4.7K*4 1206 VDD3 ON then through R/C to generate -RSMRST. -RSMRST(SB I/P) +5VA +5VA Power switch OFF 1 Resume R604 10K 0603 2 Into S4 2 R611 10K 0603 H8(Pin 40) detect powebtn,then delay 100ms to o/p -MVP4BT pulse(1us) to SB.. -H8_ICH2BTN(H8 O/P) ICH2 received -H8_ICH2BTN(H8 O/P), then o/p -SUSB-C. 1 Power switch ON. -POWERBTN(H8 I/P) -H8_SUSB -SUS[B-C](SB O/P) H8's pin14 PWR_ON 3 Q507 DTC144TKA 1 on VCC3/5 then Vcore/Vtt/Vcc25. -H8_SUSC R1 2 -SUSB (13,15,22) 3 Q506 DTC144TKA 1 R1 2 -SUSC (13,22) ALL POWER H8 detect -SUSC,then delay 150ms then o/p PWROK. Title H8 OFF this pin before o/p PWRON low.. Micro Controller PWROK(H8 O/P) Size Document Custom Number Date: A B Rev 02 411671200001 Friday, December 28, 2001 Sheet 19 of 22 A B C D E +5VAS DVMAIN PU10 SI4835DY SO8 8 7 6 5 1 +5VA S D G 3 2 1 1 2 PR559 1M 0603 1 1 (19) -ADEN 1 2 -ADEN D 1 PR563 100K 0603 PC556 0.1U 0603 50V D S G PQ508 2N7002 J33 S 2 2 PR566 100K 0603 1% 4 100K 0603 4 4 LMV393M SSOP8 DVMAIN PR554 4 8 7 6 5 BATT_DEAD (19) PU513A 2 BATT_DEAD 1 D - 3 2 1 PU11 SI4835DY SO8 G + 2 DBATT 2 2 3 4 DBATT PR567 100K 0603 8 PR564 475K 0603 1% S 1 DVMAIN 1 ADINP 1 2 3 4 5 6 7 8 9 PQ509 2 PL9 DTC144WK 169K 0603 1% 1 2 PF2 1 11 1 6.5A/32VDC 1 2 120Z/100M 2012 J28 1 2 3 4 5 6 7 +5VA BAT_V PR18 4.99K 0603 1% LMV393M SSOP8 1 PD507 (19) BAT_D 1 PC32 0.01U 0603 2 PC31 1000P 0603 2 BAV99/NA PC33 0.1U 0603 50V 2 PC34 1000P 0603 3 1 2 2 PR17 20K 0603 1% 1 PC557 0.1U 0603 50V BAT_T 1 (19) BAT_T 1 LI_OVP (22) PU513B 4 1 2 PR571 43.2K 0603 1% LI_OVP 7 2 3 2 - 3 BAV99/NA 2 + 6 BAT_C (19) BAT_C +5VAS 2 3 SCK431LCSK-5 SOT23N 5 1 2 PQ510 1 2 2 PR568 402K 0603 1% 2 8 1 1 PR565 100K 0603 1% PC555 0.1U 0603 50V 1 2 2 PR570 12.1k 0603 1% PR572 4.7K 0603 1% 1 1 1 3 1 2 3 4 5 6 7 7P/2.5MM/H4 CEN SB-07A-4.0-A2 1 (19) BAT_V 11 11P/2.5MM/H3/NA CEN BPH-S-11-G-J1A PC30 0.1U 0603 50V 2 1M 0603 1% 2 +5VAS 2 2012 PL11 1 PR562 301K 0603 1% 2 1 120Z/100M 2 6.5A/32VDC PF1 1 2 1 3 4 5 6 7 8 9 2012 1 120Z/100M PL10 PR569 1 3 PR561 PD508 Don't Stuff DBATT 1 2 PC36 47P_NA 0603 2 PC35 47P_NA 0603 1 DBATT 2 2 +5VA 3 2 1 MTG26 ID2.8/OD7.6 1 4 5 6 12 11 10 1 2 3 4 5 6 7 2 7 8 9 PR16 470K 0603 J29 PQ2 3 -SW_+5VA (19) +5VA R/A-7P/2.5MM/NA SUYIN 250005MR07G100ZU +5VAS DTC144WK PQ512 2 D S S J30 D 1 1 1 -ADEN -ADEN (19) 4 5 6 2 +3V 3 1 PC29 PL8 4.7U 0805 120Z/100M +80-20% 1608 PQ511 R1 11 3 4 5 6 7 8 9 11 11P/2.5MM/H3/NA CEN BPH-S-11-G-J1A 2 1 +5V DTC144TKA 2 2 PC26 0.1U 0603 50V 12 11 10 1 7 8 9 1 PC27 TC55RP3302EMB 4.7U SOT89N 0805 +80-20% 2 1 2 2 K BAS32L RLZ3.6B D8 A 2 1 2 3 4 5 6 7 8 9 MTG27 ID2.8/OD7.6 PD503 +5VA GND VIN 1 VOUT A PC22 0.1U 0603 50V 1 K 3 3 2 1 1 PU8 AO3401 PR573 100K 0603 PR616 0 0805 3V Resume Power +3V_ICH G G +5V 1 1 PU7 S UDZS5.1B SOD323 1 1 PD7 LP2951-02BM SO8 5V Resume Power PQ1 D K 6 1 5 4 PC25 0.1U 0603 50V 2 PC21 0.1U 50V 0603 G 5VTAP OUT ERRGND 2 1 SHORT-SMT4 SW_+5V A 2 (19) SW_+5V A IN SENSE F/B SHUTDN D S 8 2 7 3 PC24 10U 1206 10V AO3401 A 2 G JS7 1 ALWAYS Title BATTERY CONNECTOR & 3V,5V-RESUME POWER Size C Date: A B C D Document Number Rev 02 411671200001 Friday, December 28, 2001 E Sheet 20 of 22 5 4 3 2 1 +5V 1 PC40 0.1U 0603 50V 2 2 PL500 1 1 1 2 PR21 0 0603 PC41 4.7U 0805 +80-20% 2 BEAD 0805C D D PL501 PC508 10U 1812 25V 20% 2 PC510 10U 1812 25V 20% 2 PC507 10U 1812 25V 20% 1 1 1 PC517 10U 1812 25V 20% 2 1 PC514 10U 1812 25V 20% 2 PC506 10U 1812 25V 20% 1 PC513 10U 1812 25V 20% 2 1 PC505 10U 1812 25V 20% 2 1 PC509 10U 1812 25V 20% 2 1 1 PC502 10U 1812 25V 20% 2 PC511 0.1U 0603 50V 2 1 1 PC504 0.1U 0603 50V 2 PC512 0.1U 0603 50V 2 1 1 1 PC503 0.1U 0603 50V 2 2 PC501 0.01U 0603 2 2 PC500 0.01U 0603 2 1 1 PC47 + 100U 25V 20% 1 2 PC46 + 100U 25V 20% 1 2 BEAD 0805C 1 1 2 DVMAIN PR528 1M 0603 VBIAS 18 ATTENIN VID4 VID0 VID3 VID1 VID2 1 2 3 0_NA 0_NA 0_NA 0_NA 0_NA 5 6 7 8 PU507 SI4892DY SO8 D G PC515 25 4 1 1 1 1 1 1 K PR622 1 36 1 0 2 S S PL2 19 PC516 0.1U 0603 50V PU2 D SI4362DY G SO8 4 PU504 D SI4362DY G SO8 4 S S S D G 4 PC6 PC7 820U 820U 4V 4V 2 PR3 1 20 2 2 2 2 CPU_CORE PR4 .003 22 21 2 2 PU506 SI4892DY SO8 D G 4 0.1U 24 2 1 .005 PU505 SI4362DY SO8 0.7UH HK-RM136 30% PD2 PC583 PC574 PC575 100U 100U 100U 6.3V 6.3V 6.3V 7343 7343 7343 PC39 0.1U 50V 0603 2 + EC31QS03L + + + + 2 0 1 PR621 PR514 10 1 2 3 A BAW56 26 1 PR509 PR508 PR510 PR517 PR518 C 5 6 7 8 0603 1 2 3 2 1 ATTENOUT + LTC1709EG-9 SSOP36A 1 17 2 PC17 47P 0603 + 2 16 1000P + 1 NC1 + 1 TG2 SENSE2+ + 2 SENSE2- PD1 2 SW2 S S 1 VOS+ 2 1 BOOST2 1 0.7UH HK-RM136 30% 2 VOS- PC519 10U 1206 10V 3 PD500 28 27 S PU501 SI4362DY SO8 2 BG2 4 PU502 D SI4362DY G SO8 4 EC31QS03L PR502 10 1 PC522 PGND VDIFFOUT 1 1 29 5 6 7 8 15 SGND 30 PU1 D SI4362DY G SO8 4 1 14 INTVCC 31 G 0 2 2 13 ITH PR620 K 12 EXTVCC 2 PC38 0.1U 50V 0603 A PR523 15K 0603 1% BG1 NC0 D 32 1 2 3 SHORT-SMT4 PLLIN 1 PC5 PC582 PC572 PC573 820U 100U 100U 100U 4V 7343 7343 7343 6.3V 6.3V 6.3V 33 5 6 7 8 11 VIN 1 2 3 9 2 BOOST1 PLLFLTR PC3 820U 4V 2 PR1 .005 PL1 1 2 3 1 0.1U 5 6 7 8 100P 2 10 2 PC520 1 2 3 1 8 EAIN 1 34 1 2 PC528 7 JS501 1 S 5 6 7 8 PC529 0.1U 50V Ith S 35 1 2 3 6 1 PC527 470P 6.8K 2 SW1 PR2 .003 23 5 6 7 8 5 2 PR519 1 2 TG1 SENSE1- PU503 SI4892DY SO8 D G 4 1 2 3 4 2 1 SENSE1+ 4 1 EAIN S PR512 1M 0603 PGOOD 2 D 1000P PQ500 2N7002 3 RUNN/SS 2 2 PR516 49.9K 0603 1% 2 G 0 1 2.7K 2 S PR524 1 PC524 1000P PU500 SI4892DY SO8 D PR619 1 2 PQ501 2N7002 D S 1 PR513 10K 1% 1 2 1 2 D 2 RUN/SS 1 C 10 1 5 6 7 8 1 1 PC521 0.1U 1 2 PC523 D S G PR505 2 0805 (13) VRMPWRGD PU508 G (5) CPU_CORE_EN 1U 25V 2 1 5 6 7 8 PC518 PR527 1K 0603 PR521 1M 0603 5 6 7 8 10 2 10 2 1 2 3 2 PR526 1 PR520 1 +5VA PR501 0 0603 PR500 0 0603 2 2 PR515 10 +3VS PR507 10K B PVID[0..4] (4) PVID[0..4] PVID4 PVID3 PVID2 PVID1 PVID0 1 2 3 4 B 8 7 6 5 RP508 10K*4 1206 +1.8V_ICH PU12 VIN 4 1 PC10 0.1U 0603 50V 1 PC560 0.01U 0603 PC558 4.7U 0805 +80-20% 1 1 PC559 1U 0603 10V PC37 4.7U 0805 16V 2 1 5 2 2 PR20 560 0603 1% PC45 0.1U 0603 2 1 BYP PC9 + 100U 7343 6.3V 3 1 PQ3 SCK431LCSK-.5 SOT23N PC44 10U 1206 OUT +1.8VS PR19 1.2K 0603 1% AMS1085 SOT252N 2 1 2 1 1 PC42 470P 0603 2 2 4 PR22 1K 0603 1% 1 G PR23 4.7K 0603 2 2 2 PC43 10U 1206 1 1 VIN GND EN AME8801MEE V SOT25 1 S D +1.5VS 2 1 2 3 3 2 1 2 8 7 6 5 +3V 2 GND/ADJ 1 PU514 2 VOUT 1 PU13 AO4400 SO8 +12VS 1 3 +3VS 2 +3V_ICH 1.8V,1.5V POWER PR24 4.7K_1% 0603 A 2 A Title CPU Vcore/VTT Size Date: 5 4 3 2 Document Number Rev 02 411671200001 Friday, December 28, 2001 1 Sheet 21 of 22 A B C D E ADINP ADINP ADINP_2 ADINP_2 ADINP_1 2 A A PR548 PR555 12.1k 10 0603 1% PD5 10 PD4 K K PC548 1U 25V 0805 PL5 PL6 BEAD 0805C BEAD 0805C 2 1 2 2 2 PL7 PR13 2 1 2 3 2 1 S PR14 1 0603 DBATT PC543 0.1U 0603 50V 1 PC544 10U 1206 25V 1 4 1 1 1 8 7 6 5 PR15 1 0603 PC28 10U 1206 25V PR551 1M 0603 1 2 1 1 2 2 PC539 0.1U 0603 50V PC538 0.1U 0603 50V D 1 2 2 1 1 2 1 2 1 PC540 0.1U 0603 50V PQ507 D 2N7002 S G LI_OVP (20) S 2 2 PR534 100K 0603 1% PR542 49.9K 0603 1% PR535 100K 0603 1% 2 PR536 10K 0603 1% 1 1 1 1 PC535 4.7U 0805 +80-20% 2 2 PC537 0.1U 0603 50V 2 1 LP2951-3.3BM SO8 PC565 0.1U 0603 50V 2 DVCC3 PC536 0.1U 0603 50V (19) CHG_I PR541 100K 0603 1% 2 6 1 5 4 PC564 10U 1206 10V 1 1 1 PR537 1M 0603 1% PU510 5VTAP OUT ERRGND PR556 100K 0603 2 2 0603 IN SENSE F/B SHUTDN 2 2 1 1 2 3 PU6 PC541 10U 1206 25V 2 EC31QS03L SO8 SI4832DY 2 PD6 G 4 2 PC23 + 100U 25V 20% 4 1 G .035 2512 5% 10uH D 3 2 1 S D 1 2 PU5 3 3V Resume Power 1 S PU9 SI4835DY SO8 8 7 6 5 PR549 15K 0603 1% 2 1 PC545 0.1U 0603 50V PR532 10 2 PU512 SI4835DY SO8 SO8 AO4400 PC542 0.1U MAX1772 QSOP28 3 8 2 7 3 D G 4 2 1K 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 1 2 IINP CSSP CSSN BST DHI LX DL0V DL0 PGND CSIP CSIN BATT CELLS VCTL G 1 0.01U DCIN LD0 CLS REF CCS CCI CCV GND0 GND1 ICHG ACIN ACOK REFIN ICTL D 2 PR550 I_CHG 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 S TP542 3 2 PU511 PC549 2 1 PC547 1 0.1U 50V 0603 10V 1 10U 2 2 PC18 + 100U 25V 20% PC20 10U 1206 25V 1 0.01U 1 PC19 0.1U 0603 50V K PC550 PD502 A 1U 1 2 47K 0603 BAW56 1 5 6 7 8 PC553 1 PR558 1K 0603 1% 1 2 3 PR553 (19) CHARGING 1U 2 PC554 1 2 2 S PR557 33 PC551 1 5 6 7 8 PQ506 2N7002 1 D S G 2 (20) LI_OVP 1 D 2 1 PC546 1U 25V 0805 2 0805C 2 1 4 1 BEAD 2 BEAD 0805C 2 PL15 1 2 PR547 33K 0603 PL14 1 1 1 PR560 100K 0603 1% 2 B 4 1 E PQ505 MMBT3906L C EC31QS03L 1 EC31QS03L 1 2 10K 1 PC552 0.1U 0603 50V PR546 2 PR552 1 PC563 10U 1206 10V 2 PR615 0 0603 2 1 1 (19) I_LIMIT 2 ADINP_1 2 1 PR539 1K 0603 1% 2 PR533 15K_NA 0603 1% 2 D 2 (19) PWR_ON D S S 1 G PQ504 2N7002_NA PR543 1M_NA 0603 +5VAS 0_DFS (19) BLADJ BLADJ +12VS (13,15,19) -SUSB R01 ADINP_2 ADINP_2 -LID (19) J3 1 3 5 7 9 11 13 15 17 19 +5V +5VS +3V +3VS +5VS ALWAYS ADINP ADINP C716 0.1U 50V 0603 C5 0.1U 50V 0603 PC2 22U 10V 1210 C6 0.1U 50V 0603 C519 0.1U 0603 50V 1 1 HDR/10PX2/H8.4 PH/PS-D-RA-44-X-X CEN 1 1 DVMAIN C511 0.1U 0603 50V 2 PC1 10U 10V 1206 2 4 6 8 10 12 14 16 18 20 2 C2 0.1U 50V 0603 2 -AC_POWER (12) -BATT_LED (12) -BATT_G (12) -BATT_R (12) ENPBLT (10) PWR_ON (19) LEARNING (19) ADINP_1 1 DVMAIN 1 DP_LPD0 DP_LPD1 DP_LPD2 DP_LPD3 DP_LPD4 DP_LPD5 DP_LPD6 DP_LPD7 DP_SLCT -DP_STB -DP_AFD -DP_ERR -DP_INIT -DP_SLIN -AC_POWER -BATT_LED -BATT_G -BATT_R ENPBLT PWR_ON LEARNING ADINP_1 2 +12V 49 47 45 43 41 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 1 (10) CSYNC (10) TV_CRMA (10) TV_LUMA (10) TV_COMP (13) USBP2_2(13) USBP2_2+ 49 47 45 43 41 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 2 RP504 0*4_DFS 1206 (13) USBP0_0(13) USBP0_0+ 50 48 46 44 42 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 2 RP503 0*4_DFS 1206 FIRSEL -SUSC IRRX IRTX -DP_ACK DP_BUSY DP_PE 2 RP502 0*4_DFS 1206 FIRSEL -SUSC IRRX IRTX 1 RP500 0*4_DFS 1206 1 DP_LPD0 DP_LPD1 DP_LPD2 DP_LPD3 DP_LPD4 DP_LPD5 DP_LPD6 DP_LPD7 DP_SLCT -DP_STB -DP_AFD -DP_ERR -DP_INIT -DP_SLIN -DP_ACK DP_BUSY DP_PE 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 2 2 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 R500 1 2 P_LPD0 P_LPD1 P_LPD2 P_LPD3 P_LPD4 P_LPD5 P_LPD6 P_LPD7 P_SLCT -P_STB -P_AFD -P_ERR -P_INIT -P_SLIN -P_ACK P_BUSY P_PE 0603 1 (18) P_LPD0 (18) P_LPD1 (18) P_LPD2 (18) P_LPD3 (18) P_LPD4 (18) P_LPD5 (18) P_LPD6 (18) P_LPD7 (18) P_SLCT (18) -P_STB (18) -P_AFD (18) -P_ERR (18) -P_INIT (18) -P_SLIN (18) -P_ACK (18) P_BUSY (18) P_PE 50 48 46 44 42 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 2 2 J6 (13) -USBOC0 (13) -USBOC2 (18) (13,19) (18) (18) C509 0.1U 0603 50V C520 0.1U 50V 0603 1 5 6 7 8 5 6 7 8 5 6 7 8 5 6 7 8 2 1 4 3 2 1 4 3 2 1 4 3 2 1 1 4 3 2 1 FM/22PX2/1.27 B06P-0110-441 SPEED CP502 22P*4 1206 CP503 22P*4 1206 CP504 22P*4 1206 CP505 22P*4 1206 C504 22P 0603 5% Title DC-DC CONNECTOR ,CHARGER Size C Date: A B C D Document Number Rev 02 411671200001 Friday, December 28, 2001 E Sheet 22 of 22 5 4 3 2 1 SYSTEM POWER (5V 3V 12V) D D PR509 DVMAIN 1 D2 2 1 2 DVMAIN 0603 2 PC14 0.1U 0603 50V PC16 0.1U 0603 50V 2 2 PC9 + 100U 25V 1 10 1 1 PL2 BEAD 0805C 1 2 PR505 0 0/NA 4 1 6 7 A K PC6 0.1U 0603 50V 1 2 9 2 10 4 0 0603 11 12 1 D SYNC SHDN TIME/ON5 V+ GND VL REF PGND SKIP DL5 RESET BST5 FB5 LX5 CSL5 DH5 CSH5 SEQ MAX1632 2 2 PC15 0.1U 50V 0603 1 25 24 23 PD502 22 1 21 3 2 20 BAW56 19 PC13 0.1U 0603 50V PC511 4.7U 1206 16V 18 17 2 1 PC12 0.1U 50V 0603 16 15 SSOP28A PR503 0 PR501 0_NA B 2 1 2 10UH IND_CDRH125B PC2 1U 0603 1 2 3 PR502 0_NA 2 5 6 7 8 S 3 1 DL3 VDD 26 PU502 SI4832DY SO8 1 PC21 470P_NA 0603 10% 2 PR18 97.6K_NA 0603 1% 1 PR508 0_NA 0603 SI4800DY SO8 LX3 BST3 12OUT 27 2 PC503 0.1U 50V 0603 1 1 PC1 + 100U/H2.8 7343 10V I5 2 0.1U 50V 0603 PC3 + 100U/H2.8 7343 10V 2 PC502 2 BEAD 0805C 2 1 PC501 4.7U 1206 16V 1 1 PD504 EC10QS03L PR1 .015 2512 1% PR17 100K_NA 0603 1% 2 2 K BEAD 0805C PL504 1 2 PU503 4 1 4 G 2 1 1 2 B3 2 D 2 PT1 PL501 2 14 SHORT-SMT3 +5V B A 13 FB3 28 1 JS501 1 2 3 1 1 5 6 7 8 S G BKL_VMAIN (2) BKL_VMAIN PR19 0 1 PR2 2 1 1 PC5 + 100U 25V 2 PC4 + 100U 25V 2 PD1 EC11FS2 DC2010 1 8 DH3 1 5 RUN/ON3 CSL3 2 1 4 PC11 + 100U 25V 2 2 I4 2 PC516 0.1U 50V 0603 2 1 1 1 PL3 BEAD 0805C I3 CSH3 1 3 2 2 1 1 1 2 3 2 A5 PC20 470P 0603 10% 0_NA 0603 PU1 G 5 6 7 8 PR510 1 2 PU505 SI4832DY SO8 +12V PR16 100K 0603 1% 2 1 PR12 1M 0603 2 10UH CDRH127-100MC S 1 PC515 0.1U 0603 50V 1 2 1 1 PC7 + 330U 7343 4V A2 2 PC513 0.1U 0603 50V PC8 + 100U/H2.8 7343 10V 2 1 PC514 4.7U 1206 16V 2 2 A 1 0805C 2 1 K 2 BEAD 2 .015 2512 1% PR15 37.4K 0603 1% PL506 1 PD503 EC10QS03L PL1 1 C 4 PR8 2 0805C D PL507 1 BEAD PR511 1K 0603 1 PC512 470P_NA 0603 10% +3V A4 PR3 1K 0603 2 1 2 3 2 S G C D 5 6 7 8 0603 PC504 0.1U 50V 0603 1 PR504 1 PU506 SI4800DY SO8 2 2 1 1 (2) -SUSC 2 (2) PWR_ON I6 A A Title SYSTEM POWER Size Date: 5 4 3 2 Document Number Rev 0A 411671200004 Monday, October 22, 2001 1 Sheet 1 of 3 5 4 3 2 1 PD2 2 3 1 BAV70LT1 PD3 2 3 ALWAYS 1 BAV70LT1 ADINP JO502 1 D 2 D JL2 OPEN-SMT4 JO503 1 1 ADINP_1 2 SHORT-SMT4 2 OPEN-SMT4 1 2 ADINP_2 PQ503 SI4835DY SO8 PR6 100K 0603 2 A DVMAIN S 2 2 2 EC31QS03L 1 1 K PC17 0.1U 0603 50V PC18 1000P 0603 2 A PD4 K EC31QS03L 8 7 6 5 G 2012 4 PL502 120Z/100M 1 2 PR11 10K 0603 2 PR10 10K 0603 PD5 A D 3 2 1 1 1 1 PC19 + 100U 25V 1 PC10 0.1U 0603 50V PQ502 SI4835DY SO8 PQ1 2N7002 SOT23_FET DVMAIN K EC31QS03L 2 2 470K 0603 2 47K 0603 PD6 1 1 D 1 D S G 2 PR513 .1 S 2 1 LEARNING 1 1 4 PR4 470K 0603 PR5 PR9 LEARNING 8 7 6 5 G 2 S D 3 2 1 L3 SHORT-SMT4 JL3 PR514 .1 1 K 2 L2 120Z/100M PC5082012 0.1U 0603 PC509 50V 0.1U 50V PD501 RLZ24D 2 1 1 1 PC507 0.1U 0603 50V 2 2 PC506 0.1U 0603 50V 2 4 5 6 C PC510 0.1U 0603 50V 2 1 L1 1 PC505 1U 0805 25V C A 6.5A/32VDC 2 JACK-3P 1 PF501 1 1 3 2 PL503 2 J5 2DC-S315-X03 PQ2 SI2301DS PU504 AO4400 SO8 8 7 6 5 +5V 3 2 1 +5VS 8 7 6 5 +3V 3 2 1 +3VS G 4 4 2 G S D PR7 1M 0603 S 1 PU501 AO4400 SO8 G G +12VS D D S D S +12V PR506 D S PQ3 2N7002 1 PC517 0.1U 0603 50V PC518 0.1U 0603 50V 1 S 2 G 470K 0603 2 -SUSB -SUSB 2 1 D 1 2 PR515 1M 0603 B B +12V +5VAS BLADJ -SUSB ADINP_2 +12VS -SUSB ADINP_2 P_LPD0 (3) P_LPD1 (3) P_LPD2 (3) P_LPD3 (3) P_LPD4 (3) P_LPD5 (3) P_LPD6 (3) P_LPD7 (3) P_SLCT (3) -P_STB (3) -P_AFD (3) -P_ERR (3) -P_INIT (3) -P_SLIN (3) -AC_POWER -BATT_LED -BATT_G -BATT_R ENPBLT1 PWR_ON (1) LEARNING +5V +5VS +3V +3VS DVMAIN 1 3 5 7 9 11 13 15 17 19 2 4 6 8 10 12 14 16 18 20 +5VS ALWAYS ADINP C514 0.1U_NA 50V 0603 Note : BKL_VMAIN is Power Trace ALWAYS ENPBLT1 ADINP (1) BKL_VMAIN L510 1 2 BKL_VMAIN L509 1 2 BLADJ L508 1 2 DVMAIN C513 0.1U 0603 50V BEAD 0603B BEAD 0805C BEAD 0603B J6 1 2 3 4 5 6 7 8 9 10 11 12 FA501 -AC_POWER -BATT_LED -BATT_G -BATT_R HDR/10PX2/H8.49 PH-D-RA-44-X-X CEN 1 2 3 4 8 7 6 5 120OHM/100MHZ +5VAS 1 2 L507 BEAD 0805C ADINP_1 GND1 GND2 C512 0.1U 0603 50V 1 2 3 4 5 6 7 8 9 10 11 12 Inverter PJ1 P_LPD0 P_LPD1 P_LPD2 P_LPD3 P_LPD4 P_LPD5 P_LPD6 P_LPD7 P_SLCT -P_STB -P_AFD -P_ERR -P_INIT -P_SLIN -AC_POWER -BATT_LED -BATT_G -BATT_R ENPBLT1 PWR_ON LEARNING ADINP_1 1 49 47 45 43 41 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 2 49 47 45 43 41 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 2 50 48 46 44 42 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 1 USBP2_2USBP2_2+ 50 48 46 44 42 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 2 (3) CSYNC (3) TV_CRMA (3) TV_LUMA (3) TV_COMP (3) USBP2_2(3) USBP2_2+ -USBOC0 -USBOC2 FIRSEL -SUSC IRRX IRTX -P_ACK P_BUSY P_PE USBP0_0USBP0_0+ 1 PJ2 (3) -USBOC0 (3) -USBOC2 (3) FIRSEL (1) -SUSC (3) IRRX (3) IRTX (3) -P_ACK (3) P_BUSY (3) P_PE (3) USBP0_0(3) USBP0_0+ GND1 GND2 MA/12PX1/ST SPEED Y17-101-0001 MA/22PX2/1.27 SPEED G442-8701-441 A A Title DC POWER Size Date: 5 4 3 2 Document Number Rev 0A 411671200004 Monday, October 22, 2001 1 Sheet 2 of 3 5 4 3 2 1 D503 1 2 2 1 +3V D502 Place two fuses on same location, only use one fuse. 3 BAV99 3 BAV99 U2 3 +5V VOUT0 VOUT1 USB2VCC5 1 5 USB0VCC5 RT9701-CBL SOT25 D 1 R4 33K 0603 RP501 75*4 1206 (2) -USBOC2 -USBOC2 2 L1 1 R3 47K 0603 C1 1000P 0603 2 JP_BEAD_DFS 2 GND_TV 2 120Z/100M 2012 C2 10U_NA 1206 10V 2 5 6 7 8 2 1 C504 100P 0603 10% 2 L505 120Z/100M 1608 1 2 C506 100P 0603 10% VIN1 1 1 1 C503 100P 0603 10% TV_LUMA TV_CRMA 2 2 VIN0 2 1 1 CSYNC (2) TV_COMP (2) TV_LUMA (2) TV_CRMA (2) 1 L5 C505 100P 0603 10% 2 2 1 C10801-10405 MINI-DIN/4P 1 2 2 L504 120Z/100M 1608 4 4 3 2 1 1 1 GND1 GND2 GND1 GND2 L502 120Z/100M 1608 1 1 2 3 4 1 2 3 4 D L503 120Z/100M 1608 2 J4 GND TV OUT C501 0.1U 0603 50V GND_TV GND_USB +5VS A (2) USBP2_2- D501 12 13 11 14 10 15 9 16 8 17 7 18 6 19 5 20 4 21 3 2 1 22 23 24 R1 PP_LPD3 2 0 0603 PAC128401Q QSOP24A 1 14 2 15 3 16 4 17 5 18 6 19 7 20 8 21 9 22 10 23 11 24 12 25 13 LPD4 LPD5 LPD6 LPD7 U502 12 0*4 (2) (2) (2) (2) P_LPD4 P_LPD5 P_LPD6 P_LPD7 P_LPD4 P_LPD5 P_LPD6 P_LPD7 ACK# 13 BUSY 11 14 10 15 PE 9 16 SLCT 8 17 7 18 6 19 RP3 8 7 6 5 1 2 3 4 USBP0USBP0+ 26 STB# AFD# LPD0 ERR# LPD1 INIT# LPD2 SLIN# LPD3 PP_LPD4 PP_LPD5 PP_LPD6 PP_LPD7 JO501 10mil 5 20 4 21 3 2 1 22 23 24 GND1 GND2 GND3 GND4 2 SHORT-SMT4 USB0VCC5 GND_USB 5mil USBP+ 5mil -USBOC0 L4 J3 1 (2) -USBOC0 GND_IO2 R6 47K 0603 C4 1000P 0603 GND 2 1 120Z/100M 2012 C3 10U_NA 1206 10V 2 C502 0.1U 0603 50V 1 2 3 4 GND1 GND2 GND3 GND4 1206 GND_USB PAC128401Q QSOP24A 4 VCC3_IR 2010 1 R2 1% C507 0.1U 0603 50V 11 0_DFS 0603 R504 15K 0603 GND1 R505 15K 0603 C510 47P/NA 0603 1 1 (2) USBP0_0+ C511 47P/NA 0603 HSDL-3600 1 2 2 JL501 1 C515 10U_NA 1206 16V IRRX IRTX 2 2 SHORT-SMT4 1 1 IRRX IRTX 2 (2) R501 2.7 (2) 1 2 JL1 VCC AGND FIR_SEL MD0 MD1 NC GND RXD TXD LEDA 2 FIRSEL FIR 1 FIRSEL VCC3_IR 1 2 3 4 5 6 7 8 9 10 2 (2) B 3 L3 2 600Z/100M CORE_ACM2520U 1 U1 +3VS GND1 GND2 GND3 GND4 GND_IO2 FIR Module 1 GND_IO2 1 2 3 4 USB/4PX1 LINKTEK UAR80-4W510 GND_USB (2) USBP0_0- 2 B GND1 GND2 GND3 GND4 R5 33K 0603 10mil 10mil 1 2 3 4 USB/4PX1 LINKTEK UAR80-4W510 5mil USBP- 1 PIO 7536S-25G2T SUYIN GND_IO2 -PP_ACK PP_BUSY PP_PE PP_SLCT 1 10mil 2 1 2 3 4 2 GND 27 RP4 2 J2 1 2 3 4 2 0*4 8 7 6 5 1 GND_USB 1206 -P_ACK P_BUSY P_PE P_SLCT (2) -P_ACK (2) P_BUSY (2) P_PE (2) P_SLCT C 1 PP_LPD1 -PP_INIT PP_LPD2 -PP_SLIN C509 47P/NA 0603 2 1206 1 J1 1 2 3 4 47P/NA 0603 2 P_LPD3 RP2 C508 R503 15K 0603 1 8 7 6 5 Parallel Port Connector (2) P_LPD3 P_LPD1 -P_INIT P_LPD2 -P_SLIN R502 15K 0603 Same legth 2 Layout note: 1 1 (2) USBP2_2+ 1 -PP_STB -PP_AFD PP_LPD0 -PP_ERR 1 1 2 3 4 0*4 (2) P_LPD1 (2) -P_INIT (2) P_LPD2 (2) -P_SLIN L2 2 200Z/100M CORE_ACM2520U RP1 8 7 6 5 1206 C 3 1 2 0*4 -P_STB -P_AFD P_LPD0 -P_ERR (2) -P_STB (2) -P_AFD (2) P_LPD0 (2) -P_ERR 4 K BAS32L U501 2 GND_USB SHORT-SMT4 GND_FIR IR Mode Select IR Mode Select A A HI LOW SIR 1/3 Distance Power LOW LOW HI MIR/FIR Full Distance Power L501 Full Distance Power HI HI MIR/FIR 2/3 Distance Power HI HI HI MIR/FIR 1/3 Distance Power 2 120Z/100M 2012 4 5 6 12 11 10 4 5 6 12 11 10 4 5 6 12 11 10 GND_IO2 FD501 FIDUCIAL-MARK FD503 FIDUCIAL-MARK FD504 FIDUCIAL-MARK FD502 FIDUCIAL-MARK Title DC POWER Size 1 LOW 1 1 HI FD2 FIDUCIAL-MARK 1 2/3 Distance Power FD4 FIDUCIAL-MARK 1 SIR FD3 FIDUCIAL-MARK 1 LOW FD1 FIDUCIAL-MARK 1 LOW HI MTG3 ID2.8/OD7.6 1 LOW LOW MTG2 ID2.8/OD7.6 1 LOW MTG1 ID2.8/OD7.6 3 2 1 Shutdown 7 8 9 TX Function Shutdown 3 2 1 RX Function X 7 8 9 FIRSEL LOW 3 2 1 IRMODE1 HI 7 8 9 IRMODE0 Date: 5 4 3 2 Document Number Rev 0A 411671200004 Monday, October 22, 2001 1 Sheet 3 of 3 Reference Material Intel Pentium 4 Processor mFC-PGA2 478Pin Intel. INC INTEL 82845 Memory Controller Hub Intel. INC INTEL 82801BA I/O Controller Hub Intel. INC PCI4410 Manual-PC Card and OHCI Controller CHRONTEL. INC Frequency Generator ICS950805 ICS. INC Engineer Hardware Specification Technology.Corp/MiTAC Engineer Software Specification Technology.Corp/MiTAC SERVICE SERVICE MANUAL MANUAL FOR FOR 8170 8170 Sponsoring Editor : Jesse Jan Author : Jacey Liu Assistant Editor : Janne Liu Publisher : MiTAC International Corp. Address : 1, R&D Road 2, Hsinchu Science-Based Industrial, Hsinchu, Taiwan, R.O.C. Tel : 886-3-5779250 Fax : 886-3-5781245 First Edition : Feb. 2002 E-mail : Willy.Chen @ mic.com.tw Web : http: //www.mitac.com http: //www.mitacservice.com
Source Exif Data:
File Type : PDF File Type Extension : pdf MIME Type : application/pdf PDF Version : 1.3 Linearized : Yes Encryption : Standard V1.2 (40-bit) User Access : Print, Fill forms, Extract, Assemble, Print high-res Create Date : 2002:01:28 11:51:39 Producer : Acrobat Distiller 4.0 for Windows Modify Date : 2002:02:06 15:45:35+08:00 Page Count : 217EXIF Metadata provided by EXIF.tools