Motorola Mpc8260 Users Manual 8260UM

2015-01-23

• About This Book
  • Before Using this Manual—Important Note
  • Audience
  • Organization
  • Suggested Reading
  • Conventions
  • Acronyms and Abbreviations
  • PowerPC Architecture Terminology Conventions
• PartI Overview
  • Intended Audience
  • Contents
  • Conventions
  • Acronyms and Abbreviations
  • Chapter1 Overview
    • 1.1 Features
    • 1.2 MPC8260’s Architecture Overview
      • 1.2.1 MPC603e Core
      • 1.2.2 System Interface Unit (SIU)
      • 1.2.3 Communications Processor Module (CPM)
    • 1.3 Software Compatibility Issues
      • 1.3.1 Signals
    • 1.4 Differences between MPC860 and MPC8260
    • 1.5 Serial Protocol Table
    • 1.6 MPC8260 Configurations
      • 1.6.1 Pin Configurations
      • 1.6.2 Serial Performance
    • 1.7 MPC8260 Application Examples
      • 1.7.1 Examples of Communication Systems
        • 1.7.1.1 Remote Access Server
        • 1.7.1.2 Regional Office Router
        • 1.7.1.3 LAN-to-WAN Bridge Router
        • 1.7.1.4 Cellular Base Station
        • 1.7.1.5 Telecommunications Switch Controller
        • 1.7.1.6 SONET Transmission Controller
      • 1.7.2 Bus Configurations
        • 1.7.2.1 Basic System
        • 1.7.2.2 High-Performance Communication
        • 1.7.2.3 High-Performance System Microprocessor
  • Chapter2 PowerPC Processor Core
    • 2.1 Overview
    • 2.2 PowerPC Processor Core Features
      • 2.2.1 Instruction Unit
      • 2.2.2 Instruction Queue and Dispatch Unit
      • 2.2.3 Branch Processing Unit (BPU)
      • 2.2.4 Independent Execution Units
        • 2.2.4.1 Integer Unit (IU)
        • 2.2.4.2 Load/Store Unit (LSU)
        • 2.2.4.3 System Register Unit (SRU)
      • 2.2.5 Completion Unit
      • 2.2.6 Memory Subsystem Support
        • 2.2.6.1 Memory Management Units (MMUs)
        • 2.2.6.2 Cache Units
    • 2.3 Programming Model
      • 2.3.1 Register Set
        • 2.3.1.1 PowerPC Register Set
        • 2.3.1.2 MPC8260-Specific Registers
          • 2.3.1.2.1 Hardware Implementation-Dependent Register 0 (HID0)
          • 2.3.1.2.2 Hardware Implementation-Dependent Register 1 (HID1)
          • 2.3.1.2.3 Hardware Implementation-Dependent Register 2 (HID2)
          • 2.3.1.2.4 Processor Version Register (PVR)
      • 2.3.2 PowerPC Instruction Set and Addressing Modes
        • 2.3.2.1 Calculating Effective Addresses
        • 2.3.2.2 PowerPC Instruction Set
        • 2.3.2.3 MPC8260 Implementation-Specific Instruction Set
    • 2.4 Cache Implementation
      • 2.4.1 PowerPC Cache Model
      • 2.4.2 MPC8260 Implementation-Specific Cache Implementation
        • 2.4.2.1 Data Cache
        • 2.4.2.2 Instruction Cache
        • 2.4.2.3 Cache Locking
          • 2.4.2.3.1 Entire Cache Locking
          • 2.4.2.3.2 Way Locking
    • 2.5 Exception Model
      • 2.5.1 PowerPC Exception Model
      • 2.5.2 MPC8260 Implementation-Specific Exception Model
      • 2.5.3 Exception Priorities
    • 2.6 Memory Management
      • 2.6.1 PowerPC MMU Model
      • 2.6.2 MPC8260 Implementation-Specific MMU Features
    • 2.7 Instruction Timing
    • 2.8 Differences between the MPC8260’s Core and the PowerPC 603e Microprocessor
  • Chapter3 Memory Map
• PartII Configuration and Reset
  • Audience
  • Contents
  • Suggested Reading
  • Conventions
  • Acronyms and Abbreviations
  • Chapter4 System Interface Unit (SIU)
    • 4.1 System Configuration and Protection
      • 4.1.1 Bus Monitor
      • 4.1.2 Timers Clock
      • 4.1.3 Time Counter (TMCNT)
      • 4.1.4 Periodic Interrupt Timer (PIT)
      • 4.1.5 Software Watchdog Timer
    • 4.2 Interrupt Controller
      • 4.2.1 Interrupt Configuration
      • 4.2.2 Interrupt Source Priorities
        • 4.2.2.1 SCC, FCC, and MCC Relative Priority
        • 4.2.2.2 PIT, TMCNT, and IRQ Relative Priority
        • 4.2.2.3 Highest Priority Interrupt
      • 4.2.3 Masking Interrupt Sources
      • 4.2.4 Interrupt Vector Generation and Calculation
        • 4.2.4.1 Port C External Interrupts
    • 4.3 Programming Model
      • 4.3.1 Interrupt Controller Registers
        • 4.3.1.1 SIU Interrupt Configuration Register (SICR)
        • 4.3.1.2 SIU Interrupt Priority Register (SIPRR)
        • 4.3.1.3 CPM Interrupt Priority Registers (SCPRR_H and SCPRR_L)
        • 4.3.1.4 SIU Interrupt Pending Registers (SIPNR_H and SIPNR_L)
        • 4.3.1.5 SIU Interrupt Mask Registers (SIMR_H and SIMR_L)
        • 4.3.1.6 SIU Interrupt Vector Register (SIVEC)
        • 4.3.1.7 SIU External Interrupt Control Register (SIEXR)
      • 4.3.2 System Configuration and Protection Registers
        • 4.3.2.1 Bus Configuration Register (BCR)
        • 4.3.2.2 60x Bus Arbiter Configuration Register (PPC_ACR)
        • 4.3.2.3 60x Bus Arbitration-Level Registers (PPC_ALRH/PPC_ALRL)
        • 4.3.2.4 Local Bus Arbiter Configuration Register (LCL_ACR)
        • 4.3.2.5 Local Bus Arbitration Level Registers (LCL_ALRH and LCL_ACRL)
        • 4.3.2.6 SIU Module Configuration Register (SIUMCR)
        • 4.3.2.7 Internal Memory Map Register (IMMR)
        • 4.3.2.8 System Protection Control Register (SYPCR)
        • 4.3.2.9 Software Service Register (SWSR)
        • 4.3.2.10 60x Bus Transfer Error Status and Control Register1 (TESCR1)
        • 4.3.2.11 60x Bus Transfer Error Status and Control Register 2 (TESCR2)
        • 4.3.2.12 Local Bus Transfer Error Status and Control Register1 (L_TESCR1)
        • 4.3.2.13 Local Bus Transfer Error Status and Control Register2 (L_TESCR2)
        • 4.3.2.14 Time Counter Status and Control Register (TMCNTSC)
        • 4.3.2.15 Time Counter Register (TMCNT)
        • 4.3.2.16 Time Counter Alarm Register (TMCNTAL)
      • 4.3.3 Periodic Interrupt Registers
        • 4.3.3.1 Periodic Interrupt Status and Control Register (PISCR)
        • 4.3.3.2 Periodic Interrupt Timer Count Register (PITC)
        • 4.3.3.3 Periodic Interrupt Timer Register (PITR)
    • 4.4 SIU Pin Multiplexing
  • Chapter5 Reset
    • 5.1 Reset Causes
      • 5.1.1 Reset Actions
      • 5.1.2 Power-On Reset Flow
      • 5.1.3 HRESET Flow
      • 5.1.4 SRESET Flow
    • 5.2 Reset Status Register (RSR)
    • 5.3 Reset Mode Register (RMR)
    • 5.4 Reset Configuration
      • 5.4.1 Hard Reset Configuration Word
      • 5.4.2 Hard Reset Configuration Examples
        • 5.4.2.1 Single MPC8260 with Default Configuration
        • 5.4.2.2 Single MPC8260 Configured from Boot EPROM
        • 5.4.2.3 Multiple MPC8260s Configured from Boot EPROM
        • 5.4.2.4 Multiple MPC8260s in a System with No EPROM
• PartIII The Hardware Interface
  • Intended Audience
  • Contents
  • Suggested Reading
  • Conventions
  • Acronyms and Abbreviations
  • Chapter6 External Signals
    • 6.1 Functional Pinout
    • 6.2 Signal Descriptions
  • Chapter7 60x Signals
    • 7.1 Signal Configuration
    • 7.2 Signal Descriptions
      • 7.2.1 Address Bus Arbitration Signals
        • 7.2.1.1 Bus Request (BR)—Output
          • 7.2.1.1.1 Address Bus Request (BR)—Output
          • 7.2.1.1.2 Address Bus Request (BR)—Input
        • 7.2.1.2 Bus Grant (BG)
          • 7.2.1.2.1 Bus Grant (BG)—Input
          • 7.2.1.2.2 Bus Grant (BG)—Output
        • 7.2.1.3 Address Bus Busy (ABB)
          • 7.2.1.3.1 Address Bus Busy (ABB)—Output
          • 7.2.1.3.2 Address Bus Busy (ABB)—Input
      • 7.2.2 Address Transfer Start Signal
        • 7.2.2.1 Transfer Start (TS)
          • 7.2.2.1.1 Transfer Start (TS)—Output
        • 7.2.2.2 Transfer Start (TS)—Input
      • 7.2.3 Address Transfer Signals
        • 7.2.3.1 Address Bus (A[0–31])
          • 7.2.3.1.1 Address Bus (A[0–31])—Output
          • 7.2.3.1.2 Address Bus (A[0–31])—Input
      • 7.2.4 Address Transfer Attribute Signals
        • 7.2.4.1 Transfer Type (TT[0–4])
          • 7.2.4.1.1 Transfer Type (TT[0–4])—Output
          • 7.2.4.1.2 Transfer Type (TT[0–4])—Input
        • 7.2.4.2 Transfer Size (TSIZ[0–3])
        • 7.2.4.3 Transfer Burst (TBST)
        • 7.2.4.4 Global (GBL)
          • 7.2.4.4.1 Global (GBL)—Output
          • 7.2.4.4.2 Global (GBL)—Input
        • 7.2.4.5 Caching-Inhibited (CI)—Output
        • 7.2.4.6 Write-Through (WT)—Output
      • 7.2.5 Address Transfer Termination Signals
        • 7.2.5.1 Address Acknowledge (AACK)
          • 7.2.5.1.1 Address Acknowledge (AACK)—Output
          • 7.2.5.1.2 Address Acknowledge (AACK)—Input
        • 7.2.5.2 Address Retry (ARTRY)
          • 7.2.5.2.1 Address Retry (ARTRY)—Output
          • 7.2.5.2.2 Address Retry (ARTRY)—Input
      • 7.2.6 Data Bus Arbitration Signals
        • 7.2.6.1 Data Bus Grant (DBG)
          • 7.2.6.1.1 Data Bus Grant (DBG)—Input
          • 7.2.6.1.2 Data Bus Grant (DBG)—Output
        • 7.2.6.2 Data Bus Busy (DBB)
          • 7.2.6.2.1 Data Bus Busy (DBB)—Output
          • 7.2.6.2.2 Data Bus Busy (DBB)—Input
      • 7.2.7 Data Transfer Signals
        • 7.2.7.1 Data Bus (D[0–63])
          • 7.2.7.1.1 Data Bus (D[0–63])—Output
          • 7.2.7.1.2 Data Bus (D[0–63])—Input
        • 7.2.7.2 Data Bus Parity (DP[0–7])
          • 7.2.7.2.1 Data Bus Parity (DP[0–7])—Output
          • 7.2.7.2.2 Data Bus Parity (DP[0–7])—Input
      • 7.2.8 Data Transfer Termination Signals
        • 7.2.8.1 Transfer Acknowledge (TA)
          • 7.2.8.1.1 Transfer Acknowledge (TA)—Input
          • 7.2.8.1.2 Transfer Acknowledge (TA)—Output
        • 7.2.8.2 Transfer Error Acknowledge (TEA)
          • 7.2.8.2.1 Transfer Error Acknowledge (TEA)—Input
          • 7.2.8.2.2 Transfer Error Acknowledge (TEA)—Output
        • 7.2.8.3 Partial Data Valid Indication (PSDVAL)
          • 7.2.8.3.1 Partial Data Valid (PSDVAL)—Input
          • 7.2.8.3.2 Partial Data Valid (PSDVAL)—Output
  • Chapter8 The 60x Bus
    • 8.1 Terminology
    • 8.2 Bus Configuration
      • 8.2.1 Single MPC8260 Bus Mode
      • 8.2.2 60x-Compatible Bus Mode
    • 8.3 60x Bus Protocol Overview
      • 8.3.1 Arbitration Phase
      • 8.3.2 Address Pipelining and Split-Bus Transactions
    • 8.4 Address Tenure Operations
      • 8.4.1 Address Arbitration
      • 8.4.2 Address Pipelining
      • 8.4.3 Address Transfer Attribute Signals
        • 8.4.3.1 Transfer Type Signal (TT[0–4]) Encoding
        • 8.4.3.2 Transfer Code Signals TC[0–2]
        • 8.4.3.3 TBST and TSIZ[0–3] Signals and Size of Transfer
        • 8.4.3.4 Burst Ordering During Data Transfers
        • 8.4.3.5 Effect of Alignment on Data Transfers
        • 8.4.3.6 Effect of Port Size on Data Transfers
        • 8.4.3.7 60x-Compatible Bus Mode—Size Calculation
        • 8.4.3.8 Extended Transfer Mode
      • 8.4.4 Address Transfer Termination
        • 8.4.4.1 Address Retried with ARTRY
        • 8.4.4.2 Address Tenure Timing Configuration
      • 8.4.5 Pipeline Control
    • 8.5 Data Tenure Operations
      • 8.5.1 Data Bus Arbitration
      • 8.5.2 Data Streaming Mode
      • 8.5.3 Data Bus Transfers and Normal Termination
      • 8.5.4 Effect of ARTRY Assertion on Data Transfer and Arbitration
      • 8.5.5 Port Size Data Bus Transfers and PSDVAL Termination
      • 8.5.6 Data Bus Termination by Assertion of TEA
    • 8.6 Memory Coherency—MEI Protocol
    • 8.7 Processor State Signals
      • 8.7.1 Support for the lwarx/stwcx. Instruction Pair
      • 8.7.2 TLBISYNC Input
    • 8.8 Little-Endian Mode
  • Chapter9 Clocks and Power Control
    • 9.1 Clock Unit
    • 9.2 Clock Configuration
    • 9.3 External Clock Inputs
    • 9.4 Main PLL
      • 9.4.1 PLL Block Diagram
      • 9.4.2 Skew Elimination
    • 9.5 Clock Dividers
    • 9.6 The MPC8260’s Internal Clock Signals
      • 9.6.1 General System Clocks
    • 9.7 PLL Pins
    • 9.8 System Clock Control Register (SCCR)
    • 9.9 System Clock Mode Register (SCMR)
    • 9.10 Basic Power Structure
  • Chapter10 Memory Controller
    • 10.1 Features
    • 10.2 Basic Architecture
      • 10.2.1 Address and Address Space Checking
      • 10.2.2 Page Hit Checking
      • 10.2.3 Error Checking and Correction (ECC)
      • 10.2.4 Parity Generation and Checking
      • 10.2.5 Transfer Error Acknowledge (TEA) Generation
      • 10.2.6 Machine Check Interrupt (MCP) Generation
      • 10.2.7 Data Buffer Controls (BCTLx)
      • 10.2.8 Atomic Bus Operation
      • 10.2.9 Data Pipelining
      • 10.2.10 External Memory Controller Support
      • 10.2.11 External Address Latch Enable Signal (ALE)
      • 10.2.12 ECC/Parity Byte Select (PBSE)
      • 10.2.13 Partial Data Valid Indication (PSDVAL)
    • 10.3 Register Descriptions
      • 10.3.1 Base Registers (BRx)
      • 10.3.2 Option Registers (ORx)
      • 10.3.3 60x SDRAM Mode Register (PSDMR)
      • 10.3.4 Local Bus SDRAM Mode Register (LSDMR)
      • 10.3.5 Machine A/B/C Mode Registers (MxMR)
      • 10.3.6 Memory Data Register (MDR)
      • 10.3.7 Memory Address Register (MAR)
      • 10.3.8 60x Bus-Assigned UPM Refresh Timer (PURT)
      • 10.3.9 Local Bus-Assigned UPM Refresh Timer (LURT)
      • 10.3.10 60x Bus-Assigned SDRAM Refresh Timer (PSRT)
      • 10.3.11 Local Bus-Assigned SDRAM Refresh Timer (LSRT)
      • 10.3.12 Memory Refresh Timer Prescaler Register (MPTPR)
      • 10.3.13 60x Bus Error Status and Control Registers (TESCRx)
      • 10.3.14 Local Bus Error Status and Control Registers (L_TESCRx)
    • 10.4 SDRAM Machine
      • 10.4.1 Supported SDRAM Configurations
      • 10.4.2 SDRAM Power-On Initialization
      • 10.4.3 JEDEC-Standard SDRAM Interface Commands
      • 10.4.4 Page-Mode Support and Pipeline Accesses
      • 10.4.5 Bank Interleaving
        • 10.4.5.1 SDRAM Address Multiplexing (SDAM and BSMA)
      • 10.4.6 SDRAM Device-Specific Parameters
        • 10.4.6.1 Precharge-to-Activate Interval
        • 10.4.6.2 Activate to Read/Write Interval
        • 10.4.6.3 Column Address to First Data Out—CAS Latency
        • 10.4.6.4 Last Data Out to Precharge
        • 10.4.6.5 Last Data In to Precharge—Write Recovery
        • 10.4.6.6 Refresh Recovery Interval (RFRC)
        • 10.4.6.7 External Address Multiplexing Signal
        • 10.4.6.8 External Address and Command Buffers (BUFCMD)
      • 10.4.7 SDRAM Interface Timing
      • 10.4.8 SDRAM Read/Write Transactions
      • 10.4.9 SDRAM Mode-Set Command Timing
      • 10.4.10 SDRAM Refresh
      • 10.4.11 SDRAM Refresh Timing
      • 10.4.12 SDRAM Configuration Examples
        • 10.4.12.1 SDRAM Configuration Example (Page-Based Interleaving)
      • 10.4.13 SDRAM Configuration Example (Bank-Based Interleaving)
    • 10.5 General-Purpose Chip-Select Machine (GPCM)
      • 10.5.1 Timing Configuration
        • 10.5.1.1 Chip-Select Assertion Timing
        • 10.5.1.2 Chip-Select and Write Enable Deassertion Timing
        • 10.5.1.3 Relaxed Timing
        • 10.5.1.4 Output Enable (OE) Timing
        • 10.5.1.5 Programmable Wait State Configuration
        • 10.5.1.6 Extended Hold Time on Read Accesses
      • 10.5.2 External Access Termination
      • 10.5.3 Boot Chip-Select Operation
      • 10.5.4 Differences between MPC8xx’s GPCM and MPC8260’s GPCM
    • 10.6 User-Programmable Machines (UPMs)
      • 10.6.1 Requests
        • 10.6.1.1 Memory Access Requests
        • 10.6.1.2 UPM Refresh Timer Requests
        • 10.6.1.3 Software Requests—run Command
        • 10.6.1.4 Exception Requests
      • 10.6.2 Programming the UPMs
      • 10.6.3 Clock Timing
      • 10.6.4 The RAM Array
        • 10.6.4.1 RAM Words
          • 10.6.4.1.1 Chip-Select Signals (CxTx)
          • 10.6.4.1.2 Byte-Select Signals (BxTx)
          • 10.6.4.1.3 General-Purpose Signals (GxTx, GOx)
          • 10.6.4.1.4 Loop Control
          • 10.6.4.1.5 Repeat Execution of Current RAM Word (REDO)
        • 10.6.4.2 Address Multiplexing
        • 10.6.4.3 Data Valid and Data Sample Control
        • 10.6.4.4 Signals Negation
        • 10.6.4.5 The Wait Mechanism
        • 10.6.4.6 Extended Hold Time on Read Accesses
      • 10.6.5 UPM DRAM Configuration Example
      • 10.6.6 Differences between MPC8xx UPM and MPC8260 UPM
    • 10.7 Memory System Interface Example Using UPM
      • 10.7.0.1 EDO Interface Example
    • 10.8 Handling Devices with Slow or Variable Access Times
      • 10.8.1 Hierarchical Bus Interface Example
      • 10.8.2 Slow Devices Example
    • 10.9 External Master Support (60x-Compatible Mode)
      • 10.9.1 60x-Compatible External Masters
      • 10.9.2 MPC8260-Type External Masters
      • 10.9.3 Extended Controls in 60x-Compatible Mode
      • 10.9.4 Using BNKSEL SIgnals in Single-MPC8260 Bus Mode
      • 10.9.5 Address Incrementing for External Bursting Masters
      • 10.9.6 External Masters Timing
        • 10.9.6.1 Example of External Master Using the SDRAM Machine
  • Chapter11 Secondary (L2) Cache Support
    • 11.1 L2 Cache Configurations
      • 11.1.1 Copy-Back Mode
      • 11.1.2 Write-Through Mode
      • 11.1.3 ECC/Parity Mode
    • 11.2 L2 Cache Interface Parameters
    • 11.3 System Requirements When Using the L2 Cache Interface
    • 11.4 L2 Cache Operation
    • 11.5 Timing Example
  • Chapter12 IEEE 1149.1 Test Access Port
    • 12.1 Overview
    • 12.2 TAP Controller
    • 12.3 Boundary Scan Register
    • 12.4 Instruction Register
    • 12.5 MPC8260 Restrictions
    • 12.6 Nonscan Chain Operation
• PartIV Communications Processor Module
  • Intended Audience
  • Contents
  • Suggested Reading
  • Conventions
  • Acronyms and Abbreviations
  • Chapter13 Communications Processor Module Overview
    • 13.1 Features
    • 13.2 MPC8260 Serial Configurations
    • 13.3 Communications Processor (CP)
      • 13.3.1 Features
      • 13.3.2 CP Block Diagram
      • 13.3.3 PowerPC Core Interface
      • 13.3.4 Peripheral Interface
      • 13.3.5 Execution from RAM
      • 13.3.6 RISC Controller Configuration Register (RCCR)
      • 13.3.7 RISC Time-Stamp Control Register (RTSCR)
      • 13.3.8 RISC Time-Stamp Register (RTSR)
      • 13.3.9 RISC Microcode Revision Number
    • 13.4 Command Set
      • 13.4.1 CP Command Register (CPCR)
        • 13.4.1.1 CP Commands
      • 13.4.2 Command Register Example
      • 13.4.3 Command Execution Latency
    • 13.5 Dual-Port RAM
      • 13.5.1 Buffer Descriptors (BDs)
      • 13.5.2 Parameter RAM
    • 13.6 RISC Timer Tables
      • 13.6.1 RISC Timer Table Parameter RAM
      • 13.6.2 RISC Timer Command Register (TM_CMD)
      • 13.6.3 RISC Timer Table Entries
      • 13.6.4 RISC Timer Event Register (RTER)/Mask Register (RTMR)
      • 13.6.5 set timer Command
      • 13.6.6 RISC Timer Initialization Sequence
      • 13.6.7 RISC Timer Initialization Example
      • 13.6.8 RISC Timer Interrupt Handling
      • 13.6.9 RISC Timer Table Scan Algorithm
      • 13.6.10 Using the RISC Timers to Track CP Loading
  • Chapter14 Serial Interface with Time-Slot Assigner
    • 14.1 Features
    • 14.2 Overview
    • 14.3 Enabling Connections to TSA
    • 14.4 Serial Interface RAM
      • 14.4.1 One Multiplexed Channel with Static Frames
      • 14.4.2 One Multiplexed Channel with Dynamic Frames
      • 14.4.3 Programming SIx RAM Entries
      • 14.4.4 SIx RAM Programming Example
      • 14.4.5 Static and Dynamic Routing
    • 14.5 Serial Interface Registers
      • 14.5.1 SI Global Mode Registers (SIxGMR)
      • 14.5.2 SI Mode Registers (SIxMR)
      • 14.5.3 SIx RAM Shadow Address Registers (SIxRSR)
      • 14.5.4 SI Command Register (SIxCMDR)
      • 14.5.5 SI Status Registers (SIxSTR)
    • 14.6 Serial Interface IDL Interface Support
      • 14.6.1 IDL Interface Example
      • 14.6.2 IDL Interface Programming
    • 14.7 Serial Interface GCI Support
      • 14.7.1 SI GCI Activation/Deactivation Procedure
      • 14.7.2 Serial Interface GCI Programming
        • 14.7.2.1 Normal Mode GCI Programming
        • 14.7.2.2 SCIT Programming
  • Chapter15 CPM Multiplexing
    • 15.1 Features
    • 15.2 Enabling Connections to TSA or NMSI
    • 15.3 NMSI Configuration
    • 15.4 CMX Registers
      • 15.4.1 CMX UTOPIA Address Register (CMXUAR)
      • 15.4.2 CMX SI1 Clock Route Register (CMXSI1CR)
      • 15.4.3 CMX SI2 Clock Route Register (CMXSI2CR)
      • 15.4.4 CMX FCC Clock Route Register (CMXFCR)
      • 15.4.5 CMX SCC Clock Route Register (CMXSCR)
      • 15.4.6 CMX SMC Clock Route Register (CMXSMR)
  • Chapter16 Baud-Rate Generators (BRGs)
    • 16.1 BRG Configuration Registers 1–8 (BRGCx)
    • 16.2 Autobaud Operation on a UART
    • 16.3 UART Baud Rate Examples
  • Chapter17 Timers
    • 17.1 Features
    • 17.2 General-Purpose Timer Units
      • 17.2.1 Cascaded Mode
      • 17.2.2 Timer Global Configuration Registers (TGCR1 and TGCR2)
      • 17.2.3 Timer Mode Registers (TMR1–TMR4)
      • 17.2.4 Timer Reference Registers (TRR1–TRR4)
      • 17.2.5 Timer Capture Registers (TCR1–TCR4)
      • 17.2.6 Timer Counters (TCN1–TCN4)
      • 17.2.7 Timer Event Registers (TER1–TER4)
  • Chapter18 SDMA Channels and IDMA Emulation
    • 18.1 SDMA Bus Arbitration and Bus Transfers
    • 18.2 SDMA Registers
      • 18.2.1 SDMA Status Register (SDSR)
      • 18.2.2 SDMA Mask Register (SDMR)
      • 18.2.3 SDMA Transfer Error Address Registers (PDTEA and LDTEA)
      • 18.2.4 SDMA Transfer Error MSNUM Registers (PDTEM and LDTEM)
    • 18.3 IDMA Emulation
    • 18.4 IDMA Features
    • 18.5 IDMA Transfers
      • 18.5.1 Memory-to-Memory Transfers
        • 18.5.1.1 External Request Mode
        • 18.5.1.2 Normal Mode
      • 18.5.2 Memory to/from Peripheral Transfers
        • 18.5.2.1 Dual-Address Transfers
          • 18.5.2.1.1 Peripheral to Memory
          • 18.5.2.1.2 Memory to Peripheral
        • 18.5.2.2 Single Address (Fly-By) Transfers
          • 18.5.2.2.1 Peripheral-to-Memory Fly-By Transfers
          • 18.5.2.2.2 Memory-to-Peripheral Fly-By Transfers
      • 18.5.3 Controlling 60x Bus Bandwidth
    • 18.6 IDMA Priorities
    • 18.7 IDMA Interface Signals
      • 18.7.1 DREQx and DACKx
        • 18.7.1.1 Level-Sensitive Mode
        • 18.7.1.2 Edge-Sensitive Mode
      • 18.7.2 DONEx
    • 18.8 IDMA Operation
      • 18.8.1 Auto Buffer and Buffer Chaining
      • 18.8.2 IDMAx Parameter RAM
        • 18.8.2.1 DMA Channel Mode (DCM)
        • 18.8.2.2 Data Transfer Types as Programmed in DCM
        • 18.8.2.3 Programming DTS and STS
      • 18.8.3 IDMA Performance
      • 18.8.4 IDMA Event Register (IDSR) and Mask Register (IDMR)
      • 18.8.5 IDMA BDs
    • 18.9 IDMA Commands
      • 18.9.1 start_idma Command
      • 18.9.2 stop_idma Command
    • 18.10 IDMA Bus Exceptions
      • 18.10.1 Externally Recognizing IDMA Operand Transfers
    • 18.11 Programming the Parallel I/O Registers
    • 18.12 IDMA Programming Examples
      • 18.12.1 Peripheral-to-Memory Mode (60x Bus to Local Bus)—IDMA2
      • 18.12.2 Memory-to-Peripheral Fly-By Mode (Both on 60x Bus)— IDMA3
  • Chapter19 Serial Communications Controllers (SCCs)
    • 19.1 Features
      • 19.1.1 The General SCC Mode Registers (GSMR1–GSMR4)
      • 19.1.2 Protocol-Specific Mode Register (PSMR)
      • 19.1.3 Data Synchronization Register (DSR)
      • 19.1.4 Transmit-on-Demand Register (TODR)
    • 19.2 SCC Buffer Descriptors (BDs)
    • 19.3 SCC Parameter RAM
      • 19.3.1 SCC Base Addresses
      • 19.3.2 Function Code Registers (RFCR and TFCR)
      • 19.3.3 Handling SCC Interrupts
      • 19.3.4 Initializing the SCCs
      • 19.3.5 Controlling SCC Timing with RTS, CTS, and CD
        • 19.3.5.1 Synchronous Protocols
        • 19.3.5.2 Asynchronous Protocols
      • 19.3.6 Digital Phase-Locked Loop (DPLL) Operation
        • 19.3.6.1 Encoding Data with a DPLL
      • 19.3.7 Clock Glitch Detection
      • 19.3.8 Reconfiguring the SCCs
        • 19.3.8.1 General Reconfiguration Sequence for an SCC Transmitter
        • 19.3.8.2 Reset Sequence for an SCC Transmitter
        • 19.3.8.3 General Reconfiguration Sequence for an SCC Receiver
        • 19.3.8.4 Reset Sequence for an SCC Receiver
        • 19.3.8.5 Switching Protocols
      • 19.3.9 Saving Power
  • Chapter20 SCC UART Mode
    • 20.1 Features
    • 20.2 Normal Asynchronous Mode
    • 20.3 Synchronous Mode
    • 20.4 SCC UART Parameter RAM
    • 20.5 Data-Handling Methods: Character- or Message- Based
    • 20.6 Error and Status Reporting
    • 20.7 SCC UART Commands
    • 20.8 Multidrop Systems and Address Recognition
    • 20.9 Receiving Control Characters
    • 20.10 Hunt Mode (Receiver)
    • 20.11 Inserting Control Characters into the Transmit Data Stream
    • 20.12 Sending a Break (Transmitter)
    • 20.13 Sending a Preamble (Transmitter)
    • 20.14 Fractional Stop Bits (Transmitter)
    • 20.15 Handling Errors in the SCC UART Controller
    • 20.16 UART Mode Register (PSMR)
    • 20.17 SCC UART Receive Buffer Descriptor (RxBD)
    • 20.18 SCC UART Transmit Buffer Descriptor (TxBD)
    • 20.19 SCC UART Event Register (SCCE) and Mask Register (SCCM)
    • 20.20 SCC UART Status Register (SCCS)
    • 20.21 SCC UART Programming Example
    • 20.22 S-Records Loader Application
  • Chapter21 SCC HDLC Mode
    • 21.1 SCC HDLC Features
    • 21.2 SCC HDLC Channel Frame Transmission
    • 21.3 SCC HDLC Channel Frame Reception
    • 21.4 SCC HDLC Parameter RAM
    • 21.5 Programming the SCC in HDLC Mode
    • 21.6 SCC HDLC Commands
    • 21.7 Handling Errors in the SCC HDLC Controller
    • 21.8 HDLC Mode Register (PSMR)
    • 21.9 SCC HDLC Receive Buffer Descriptor (RxBD)
    • 21.10 SCC HDLC Transmit Buffer Descriptor (TxBD)
    • 21.11 HDLC Event Register (SCCE)/HDLC Mask Register (SCCM)
    • 21.12 SCC HDLC Status Register (SCCS)
    • 21.13 SCC HDLC Programming Examples
      • 21.13.1 SCC HDLC Programming Example #1
      • 21.13.2 SCC HDLC Programming Example #2
    • 21.14 HDLC Bus Mode with Collision Detection
      • 21.14.1 HDLC Bus Features
      • 21.14.2 Accessing the HDLC Bus
      • 21.14.3 Increasing Performance
      • 21.14.4 Delayed RTS Mode
      • 21.14.5 Using the Time-Slot Assigner (TSA)
      • 21.14.6 HDLC Bus Protocol Programming
        • 21.14.6.1 Programming GSMR and PSMR for the HDLC Bus Protocol
        • 21.14.6.2 HDLC Bus Controller Programming Example
  • Chapter22 SCC BISYNC Mode
    • 22.1 Features
    • 22.2 SCC BISYNC Channel Frame Transmission
    • 22.3 SCC BISYNC Channel Frame Reception
    • 22.4 SCC BISYNC Parameter RAM
    • 22.5 SCC BISYNC Commands
    • 22.6 SCC BISYNC Control Character Recognition
    • 22.7 BISYNC SYNC Register (BSYNC)
    • 22.8 SCC BISYNC DLE Register (BDLE)
    • 22.9 Sending and Receiving the Synchronization Sequence
    • 22.10 Handling Errors in the SCC BISYNC
    • 22.11 BISYNC Mode Register (PSMR)
    • 22.12 SCC BISYNC Receive BD (RxBD)
    • 22.13 SCC BISYNC Transmit BD (TxBD)
    • 22.14 BISYNC Event Register (SCCE)/BISYNC Mask Register (SCCM)
    • 22.15 SCC Status Registers (SCCS)
    • 22.16 Programming the SCC BISYNC Controller
    • 22.17 SCC BISYNC Programming Example
  • Chapter23 SCC Transparent Mode
    • 23.1 Features
    • 23.2 SCC Transparent Channel Frame Transmission Process
    • 23.3 SCC Transparent Channel Frame Reception Process
    • 23.4 Achieving Synchronization in Transparent Mode
      • 23.4.1 Synchronization in NMSI Mode
        • 23.4.1.1 In-Line Synchronization Pattern
        • 23.4.1.2 External Synchronization Signals
          • 23.4.1.2.1 External Synchronization Example
        • 23.4.1.3 Transparent Mode without Explicit Synchronization
      • 23.4.2 Synchronization and the TSA
        • 23.4.2.1 Inline Synchronization Pattern
        • 23.4.2.2 Inherent Synchronization
      • 23.4.3 End of Frame Detection
    • 23.5 CRC Calculation in Transparent Mode
    • 23.6 SCC Transparent Parameter RAM
    • 23.7 SCC Transparent Commands
    • 23.8 Handling Errors in the Transparent Controller
    • 23.9 Transparent Mode and the PSMR
    • 23.10 SCC Transparent Receive Buffer Descriptor (RxBD)
    • 23.11 SCC Transparent Transmit Buffer Descriptor (TxBD)
    • 23.12 SCC Transparent Event Register (SCCE)/Mask Register (SCCM)
    • 23.13 SCC Status Register in Transparent Mode (SCCS)
    • 23.14 SCC2 Transparent Programming Example
  • Chapter24 SCC Ethernet Mode
    • 24.1 Ethernet on the MPC8260
    • 24.2 Features
    • 24.3 Connecting the MPC8260 to Ethernet
    • 24.4 SCC Ethernet Channel Frame Transmission
    • 24.5 SCC Ethernet Channel Frame Reception
    • 24.6 The Content-Addressable Memory (CAM) Interface
    • 24.7 SCC Ethernet Parameter RAM
    • 24.8 Programming the Ethernet Controller
    • 24.9 SCC Ethernet Commands
    • 24.10 SCC Ethernet Address Recognition
    • 24.11 Hash Table Algorithm
    • 24.12 Interpacket Gap Time
    • 24.13 Handling Collisions
    • 24.14 Internal and External Loopback
    • 24.15 Full-Duplex Ethernet Support
    • 24.16 Handling Errors in the Ethernet Controller
    • 24.17 Ethernet Mode Register (PSMR)
    • 24.18 SCC Ethernet Receive BD
    • 24.19 SCC Ethernet Transmit Buffer Descriptor
    • 24.20 SCC Ethernet Event Register (SCCE)/Mask Register (SCCM)
    • 24.21 SCC Ethernet Programming Example
  • Chapter25 SCC AppleTalk Mode
    • 25.1 Operating the LocalTalk Bus
    • 25.2 Features
    • 25.3 Connecting to AppleTalk
    • 25.4 Programming the SCC in AppleTalk Mode
      • 25.4.1 Programming the GSMR
      • 25.4.2 Programming the PSMR
      • 25.4.3 Programming the TODR
      • 25.4.4 SCC AppleTalk Programming Example
  • Chapter26 Serial Management Controllers (SMCs)
    • 26.1 Features
    • 26.2 Common SMC Settings and Configurations
      • 26.2.1 SMC Mode Registers (SMCMR1/SMCMR2)
      • 26.2.2 SMC Buffer Descriptor Operation
      • 26.2.3 SMC Parameter RAM
        • 26.2.3.1 SMC Function Code Registers (RFCR/TFCR)
      • 26.2.4 Disabling SMCs On-the-Fly
        • 26.2.4.1 SMC Transmitter Full Sequence
        • 26.2.4.2 SMC Transmitter Shortcut Sequence
        • 26.2.4.3 SMC Receiver Full Sequence
        • 26.2.4.4 SMC Receiver Shortcut Sequence
        • 26.2.4.5 Switching Protocols
      • 26.2.5 Saving Power
      • 26.2.6 Handling Interrupts in the SMC
    • 26.3 SMC in UART Mode
      • 26.3.1 Features
      • 26.3.2 SMC UART Channel Transmission Process
      • 26.3.3 SMC UART Channel Reception Process
      • 26.3.4 Programming the SMC UART Controller
      • 26.3.5 SMC UART Transmit and Receive Commands
      • 26.3.6 Sending a Break
      • 26.3.7 Sending a Preamble
      • 26.3.8 Handling Errors in the SMC UART Controller
      • 26.3.9 SMC UART RxBD
      • 26.3.10 SMC UART TxBD
      • 26.3.11 SMC UART Event Register (SMCE)/Mask Register (SMCM)
      • 26.3.12 SMC UART Controller Programming Example
    • 26.4 SMC in Transparent Mode
      • 26.4.1 Features
      • 26.4.2 SMC Transparent Channel Transmission Process
      • 26.4.3 SMC Transparent Channel Reception Process
      • 26.4.4 Using SMSYN for Synchronization
      • 26.4.5 Using the Time-Slot Assigner (TSA) for Synchronization
      • 26.4.6 SMC Transparent Commands
      • 26.4.7 Handling Errors in the SMC Transparent Controller
      • 26.4.8 SMC Transparent RxBD
      • 26.4.9 SMC Transparent TxBD
      • 26.4.10 SMC Transparent Event Register (SMCE)/Mask Register (SMCM)
      • 26.4.11 SMC Transparent NMSI Programming Example
    • 26.5 The SMC in GCI Mode
      • 26.5.1 SMC GCI Parameter RAM
      • 26.5.2 Handling the GCI Monitor Channel
        • 26.5.2.1 SMC GCI Monitor Channel Transmission Process
        • 26.5.2.2 SMC GCI Monitor Channel Reception Process
      • 26.5.3 Handling the GCI C/I Channel
        • 26.5.3.1 SMC GCI C/I Channel Transmission Process
        • 26.5.3.2 SMC GCI C/I Channel Reception Process
      • 26.5.4 SMC GCI Commands
      • 26.5.5 SMC GCI Monitor Channel RxBD
      • 26.5.6 SMC GCI Monitor Channel TxBD
      • 26.5.7 SMC GCI C/I Channel RxBD
      • 26.5.8 SMC GCI C/I Channel TxBD
      • 26.5.9 SMC GCI Event Register (SMCE)/Mask Register (SMCM)
  • Chapter27 Multi-Channel Controllers (MCCs)
    • 27.1 Features
    • 27.2 MCC Data Structure Organization
    • 27.3 Global MCC Parameters
    • 27.4 Channel Extra Parameters
    • 27.5 Super-Channel Table
    • 27.6 Channel-Specific HDLC Parameters
      • 27.6.1 Internal Transmitter State (TSTATE)
      • 27.6.2 Interrupt Mask (INTMSK)
      • 27.6.3 Channel Mode Register (CHAMR)
      • 27.6.4 Internal Receiver State (RSTATE)
    • 27.7 Channel-Specific Transparent Parameters
      • 27.7.1 Channel Mode Register (CHAMR)—Transparent Mode
    • 27.8 MCC Configuration Registers (MCCFx)
    • 27.9 MCC Commands
    • 27.10 MCC Exceptions
      • 27.10.1 MCC Event Register (MCCE)/Mask Register (MCCM)
        • 27.10.1.1 Interrupt Table Entry
    • 27.11 MCC Buffer Descriptors
      • 27.11.1 Receive Buffer Descriptor (RxBD)
      • 27.11.2 Transmit Buffer Descriptor (TxBD)
    • 27.12 MCC Initialization and Start/Stop Sequence
      • 27.12.1 Single-Channel Initialization
      • 27.12.2 Super Channel Initialization
    • 27.13 MCC Latency and Performance
  • Chapter28 Fast Communications Controllers (FCCs)
    • 28.1 Overview
    • 28.2 General FCC Mode Registers (GFMRx)
    • 28.3 FCC Protocol-Specific Mode Registers (FPSMRx)
    • 28.4 FCC Data Synchronization Registers (FDSRx)
    • 28.5 FCC Transmit-on-Demand Registers (FTODRx)
    • 28.6 FCC Buffer Descriptors
    • 28.7 FCC Parameter RAM
      • 28.7.1 FCC Function Code Registers (FCRx)
    • 28.8 Interrupts from the FCCs
      • 28.8.1 FCC Event Registers (FCCEx)
      • 28.8.2 FCC Mask Registers (FCCMx)
      • 28.8.3 FCC Status Registers (FCCSx)
    • 28.9 FCC Initialization
    • 28.10 FCC Interrupt Handling
    • 28.11 FCC Timing Control
    • 28.12 Disabling the FCCs On-the-Fly
      • 28.12.1 FCC Transmitter Full Sequence
      • 28.12.2 FCC Transmitter Shortcut Sequence
      • 28.12.3 FCC Receiver Full Sequence
      • 28.12.4 FCC Receiver Shortcut Sequence
      • 28.12.5 Switching Protocols
    • 28.13 Saving Power
  • Chapter29 ATM Controller
    • 29.1 Features
    • 29.2 ATM Controller Overview
      • 29.2.1 Transmitter Overview
        • 29.2.1.1 AAL5 Transmitter Overview
        • 29.2.1.2 AAL1 Transmitter Overview
        • 29.2.1.3 AAL0 Transmitter Overview
        • 29.2.1.4 Transmit External Rate and Internal Rate Modes
      • 29.2.2 Receiver Overview
        • 29.2.2.1 AAL5 Receiver Overview
        • 29.2.2.2 AAL1 Receiver Overview
        • 29.2.2.3 AAL0 Receiver Overview
      • 29.2.3 Performance Monitoring
      • 29.2.4 ABR Flow Control
    • 29.3 ATM Pace Control (APC) Unit
      • 29.3.1 APC Modes and ATM Service Types
      • 29.3.2 APC Unit Scheduling Mechanism
      • 29.3.3 Determining the Scheduling Table Size
        • 29.3.3.1 Determining the Cells Per Slot (CPS) in a Scheduling Table
        • 29.3.3.2 Determining the Number of Slots in a Scheduling Table
      • 29.3.4 Determining the Time-Slot Scheduling Rate of a Channel
      • 29.3.5 ATM Traffic Type
        • 29.3.5.1 Peak Cell Rate Traffic Type
        • 29.3.5.2 Determining the PCR Traffic Type Parameters
        • 29.3.5.3 Peak and Sustain Traffic Type (VBR)
          • 29.3.5.3.1 Example for Using VBR Traffic Parameters
          • 29.3.5.3.2 Handling the Cell Loss Priority (CLP)—VBR Type 1 and 2
        • 29.3.5.4 Peak and Minimum Cell Rate Traffic Type (UBR+)
      • 29.3.6 Determining the Priority of an ATM Channel
    • 29.4 VCI/VPI Address Lookup Mechanism
      • 29.4.1 External CAM Lookup
      • 29.4.2 Address Compression
        • 29.4.2.1 VP-Level Address Compression Table (VPLT)
        • 29.4.2.2 VC-Level Address Compression Tables (VCLTs)
      • 29.4.3 Misinserted Cells
      • 29.4.4 Receive Raw Cell Queue
    • 29.5 Available Bit Rate (ABR) Flow Control
      • 29.5.1 The ABR Model
        • 29.5.1.1 ABR Flow Control Source End-System Behavior
        • 29.5.1.2 ABR Flow Control Destination End-System Behavior
        • 29.5.1.3 ABR Flowcharts
      • 29.5.2 RM Cell Structure
        • 29.5.2.1 RM Cell Rate Representation
      • 29.5.3 ABR Flow Control Setup
    • 29.6 OAM Support
      • 29.6.1 ATM-Layer OAM Definitions
      • 29.6.2 Virtual Path (F4) Flow Mechanism
      • 29.6.3 Virtual Channel (F5) Flow Mechanism
      • 29.6.4 Receiving OAM F4 or F5 Cells
      • 29.6.5 Transmitting OAM F4 or F5 Cells
      • 29.6.6 Performance Monitoring
        • 29.6.6.1 Running a Performance Block Test
        • 29.6.6.2 PM Block Monitoring
        • 29.6.6.3 PM Block Generation
        • 29.6.6.4 BRC Performance Calculations
    • 29.7 User-Defined Cells (UDC)
      • 29.7.1 UDC Extended Address Mode (UEAD)
    • 29.8 ATM Layer Statistics
    • 29.9 ATM-to-TDM Interworking
      • 29.9.1 Automatic Data Forwarding
      • 29.9.2 Using Interrupts in Automatic Data Forwarding
      • 29.9.3 Timing Issues
      • 29.9.4 Clock Synchronization (SRTS and Adaptive FIFOs)
      • 29.9.5 Mapping TDM Time Slots to VCs
      • 29.9.6 CAS Support
      • 29.9.7 Trunk Condition
      • 29.9.8 ATM-to-ATM Data Forwarding
    • 29.10 ATM Memory Structure
      • 29.10.1 Parameter RAM
        • 29.10.1.1 Determining UEAD_OFFSET (UEAD Mode Only)
        • 29.10.1.2 VCI Filtering (VCIF)
        • 29.10.1.3 Global Mode Entry (GMODE)
      • 29.10.2 Connection Tables (RCT, TCT, and TCTE)
        • 29.10.2.1 ATM Channel Code
        • 29.10.2.2 Receive Connection Table (RCT)
          • 29.10.2.2.1 AAL5 Protocol-Specific RCT
          • 29.10.2.2.2 AAL5-ABR Protocol-Specific RCT
          • 29.10.2.2.3 AAL1 Protocol-Specific RCT
          • 29.10.2.2.4 AAL0 Protocol-Specific RCT
        • 29.10.2.3 Transmit Connection Table (TCT)
          • 29.10.2.3.1 AAL5 Protocol-Specific TCT
          • 29.10.2.3.2 AAL1 Protocol-Specific TCT
          • 29.10.2.3.3 AAL0 Protocol-Specific TCT
          • 29.10.2.3.4 VBR Protocol-Specific TCTE
          • 29.10.2.3.5 UBR+ Protocol-Specific TCTE
          • 29.10.2.3.6 ABR Protocol-Specific TCTE
      • 29.10.3 OAM Performance Monitoring Tables
      • 29.10.4 APC Data Structure
        • 29.10.4.1 APC Parameter Tables
        • 29.10.4.2 APC Priority Table
        • 29.10.4.3 APC Scheduling Tables
      • 29.10.5 ATM Controller Buffer Descriptors (BDs)
        • 29.10.5.1 Transmit Buffer Operations
        • 29.10.5.2 Receive Buffers Operation
          • 29.10.5.2.1 Static Buffer Allocation
          • 29.10.5.2.2 Global Buffer Allocation
          • 29.10.5.2.3 Free Buffer Pools
          • 29.10.5.2.4 Free Buffer Pool Parameter Tables
        • 29.10.5.3 ATM Controller Buffers
        • 29.10.5.4 AAL5 RxBD
        • 29.10.5.5 AAL1 RxBD
        • 29.10.5.6 AAL0 RxBD
        • 29.10.5.7 AAL5, AAL1 User-Defined Cell—RxBD Extension
        • 29.10.5.8 AAL5 TxBDs
        • 29.10.5.9 AAL1 TxBDs
        • 29.10.5.10 AAL0 TxBDs
        • 29.10.5.11 AAL5, AAL1 User-Defined Cell—TxBD Extension
      • 29.10.6 AAL1 Sequence Number (SN) Protection Table (AAL1 Only)
      • 29.10.7 UNI Statistics Table
    • 29.11 ATM Exceptions
      • 29.11.1 Interrupt Queues
      • 29.11.2 Interrupt Queue Entry
      • 29.11.3 Interrupt Queue Parameter Tables
    • 29.12 The UTOPIA Interface
      • 29.12.1 UTOPIA Interface Master Mode
        • 29.12.1.1 UTOPIA Master Multiple PHY Operation
      • 29.12.2 UTOPIA Interface Slave Mode
        • 29.12.2.1 UTOPIA Slave Multiple PHY Operation
        • 29.12.2.2 UTOPIA Clocking Modes
        • 29.12.2.3 UTOPIA Loop-Back Modes
    • 29.13 ATM Registers
      • 29.13.1 General FCC Mode Register (GFMR)
      • 29.13.2 FCC Protocol-Specific Mode Register (FPSMR)
      • 29.13.3 ATM Event Register (FCCE)/Mask Register (FCCM)
      • 29.13.4 FCC Transmit Internal Rate Registers (FTIRRx)
    • 29.14 ATM Transmit Command
    • 29.15 SRTS Generation and Clock Recovery Using External Logic
    • 29.16 Configuring the ATM Controller for Maximum CPM Performance
      • 29.16.1 Using Transmit Internal Rate Mode
      • 29.16.2 APC Configuration
      • 29.16.3 Buffer Configuration
  • Chapter30 Fast Ethernet Controller
    • 30.1 Fast Ethernet on the MPC8260
    • 30.2 Features
    • 30.3 Connecting the MPC8260 to Fast Ethernet
    • 30.4 Ethernet Channel Frame Transmission
    • 30.5 Ethernet Channel Frame Reception
    • 30.6 Flow Control
    • 30.7 CAM Interface
    • 30.8 Ethernet Parameter RAM
    • 30.9 Programming Model
    • 30.10 Ethernet Command Set
    • 30.11 RMON Support
    • 30.12 Ethernet Address Recognition
    • 30.13 Hash Table Algorithm
    • 30.14 Interpacket Gap Time
    • 30.15 Handling Collisions
    • 30.16 Internal and External Loopback
    • 30.17 Ethernet Error-Handling Procedure
    • 30.18 Fast Ethernet Registers
      • 30.18.1 FCC Ethernet Mode Register (FPSMR)
      • 30.18.2 Ethernet Event Register (FCCE)/Mask Register (FCCM)
    • 30.19 Ethernet RxBDs
    • 30.20 Ethernet TxBDs
  • Chapter31 FCC HDLC Controller
    • 31.1 Key Features
    • 31.2 HDLC Channel Frame Transmission Processing
    • 31.3 HDLC Channel Frame Reception Processing
    • 31.4 HDLC Parameter RAM
    • 31.5 Programming Model
      • 31.5.1 HDLC Command Set
      • 31.5.2 HDLC Error Handling
    • 31.6 HDLC Mode Register (FPSMR)
    • 31.7 HDLC Receive Buffer Descriptor (RxBD)
    • 31.8 HDLC Transmit Buffer Descriptor (TxBD)
    • 31.9 HDLC Event Register (FCCE)/Mask Register (FCCM)
    • 31.10 FCC Status Register (FCCS)
  • Chapter32 FCC Transparent Controller
    • 32.1 Features
    • 32.2 Transparent Channel Operation
    • 32.3 Achieving Synchronization in Transparent Mode
      • 32.3.1 In-Line Synchronization Pattern
      • 32.3.2 External Synchronization Signals
      • 32.3.3 Transparent Synchronization Example
  • Chapter33 Serial Peripheral Interface (SPI)
    • 33.1 Features
    • 33.2 SPI Clocking and Signal Functions
    • 33.3 Configuring the SPI Controller
      • 33.3.1 The SPI as a Master Device
      • 33.3.2 The SPI as a Slave Device
      • 33.3.3 The SPI in Multimaster Operation
    • 33.4 Programming the SPI Registers
      • 33.4.1 SPI Mode Register (SPMODE)
        • 33.4.1.1 SPI Examples with Different SPMODE[LEN] Values
      • 33.4.2 SPI Event/Mask Registers (SPIE/SPIM)
      • 33.4.3 SPI Command Register (SPCOM)
    • 33.5 SPI Parameter RAM
      • 33.5.1 Receive/Transmit Function Code Registers (RFCR/TFCR)
    • 33.6 SPI Commands
    • 33.7 The SPI Buffer Descriptor (BD) Table
      • 33.7.1 SPI Buffer Descriptors (BDs)
        • 33.7.1.1 SPI Receive BD (RxBD)
        • 33.7.1.2 SPI Transmit BD (TxBD)
    • 33.8 SPI Master Programming Example
    • 33.9 SPI Slave Programming Example
    • 33.10 Handling Interrupts in the SPI
  • Chapter34 I2C Controller
    • 34.1 Features
    • 34.2 I2C Controller Clocking and Signal Functions
    • 34.3 I2C Controller Transfers
      • 34.3.1 I2C Master Write (Slave Read)
      • 34.3.2 I2C Loopback Testing
      • 34.3.3 I2C Master Read (Slave Write)
      • 34.3.4 I2C Multi-Master Considerations
    • 34.4 I2C Registers
      • 34.4.1 I2C Mode Register (I2MOD)
      • 34.4.2 I2C Address Register (I2ADD)
      • 34.4.3 I2C Baud Rate Generator Register (I2BRG)
      • 34.4.4 I2C Event/Mask Registers (I2CER/I2CMR)
      • 34.4.5 I2C Command Register (I2COM)
    • 34.5 I2C Parameter RAM
    • 34.6 I2C Commands
    • 34.7 The I2C Buffer Descriptor (BD) Table
      • 34.7.1 I2C Buffer Descriptors (BDs)
        • 34.7.1.1 I2C Receive Buffer Descriptor (RxBD)
        • 34.7.1.2 I2C Transmit Buffer Descriptor (TxBD)
  • Chapter35 Parallel I/O Ports
    • 35.1 Features
    • 35.2 Port Registers
      • 35.2.1 Port Open-Drain Registers (PODRA–PODRD)
      • 35.2.2 Port Data Registers (PDATA–PDATD)
      • 35.2.3 Port Data Direction Registers (PDIRA–PDIRD)
      • 35.2.4 Port Pin Assignment Register (PPAR)
      • 35.2.5 Port Special Options Registers A–D (PSORA–PSORD)
    • 35.3 Port Block Diagram
    • 35.4 Port Pins Functions
      • 35.4.1 General Purpose I/O Pins
      • 35.4.2 Dedicated Pins
    • 35.5 Ports Tables
    • 35.6 Interrupts from Port C
    • A.1 PowerPC Registers—User Registers
    • A.2 PowerPC Registers—Supervisor Registers
    • A.3 MPC8260-Specific SPRs