National Instruments Pxi Ni 5401 Users Manual User
NI 5401 to the manual 039b4da2-64a8-4ea3-af6b-28cdc43061e1
2015-02-05
: National-Instruments National-Instruments-Pxi-Ni-5401-Users-Manual-493601 national-instruments-pxi-ni-5401-users-manual-493601 national-instruments pdf
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Page Count: 60
- NI 5401 User Manual
- Support
- Important Information
- Conventions
- Contents
- Chapter 1 Generating Functions with the NI 5401
- Chapter 2 Function Generator Operation
- Appendix A Specifications
- Appendix B Optional Accessories
- Appendix C Frequency Resolution and Lookup Memory
- Appendix D Technical Support Resources
- Glossary
- Index
- Figures
- Figure 1-1. NI 5401 I/O Connectors
- Figure 1-2. Output Levels and Load Termination Using a 50 W Output Impedance
- Figure 1-3. SYNC Output and Duty Cycle
- Figure 1-4. NI 5401 50-Pin Digital Connector Pin Assignments
- Figure 1-5. SHC50-68 68-Pin Connector Pin Assignments
- Figure 1-6. VirtualBench-FG Soft Front Panel for Function Generation
- Figure 1-7. VirtualBench-FG General Settings Dialog Box for the NI 5401
- Figure 1-8. VirtualBench-FG Signals Settings Dialog Box for the NI 5401
- Figure 1-9. VirtualBench-FG Load Waveform Dialog Box
- Figure 1-10. VirtualBench-FG Frequency List Editor Dialog Box
- Figure 1-11. Waveform Editor Soft Front Panel
- Figure 2-1. NI 5401 Block Diagram
- Figure 2-2. Waveform Data Path Block Diagram
- Figure 2-3. DDS Building Blocks
- Figure 2-4. Waveform Generation Trigger Sources
- Figure 2-5. Single Trigger Mode
- Figure 2-6. Continuous Trigger Mode
- Figure 2-7. Stepped Trigger Mode
- Figure 2-8. Analog Output and SYNC Out Block Diagram
- Figure 2-9. Waveform and Trigger Timings
- Figure 2-10. Output Attenuation Chain
- Figure 2-11. PLL Architecture for the NI 5401 for PCI
- Figure 2-12. PLL Architecture for the NI 5401 for PXI
- Figure 2-13. Analog Filter Correction
- Figure 2-14. RTSI Trigger Lines and Routing for the NI 5401 for PCI
- Figure 2-15. PXI Trigger Lines, 10 MHz Backplane Oscillator, and Routing for the NI 5401 for PXI
- Table