Nec 78K 0 Series Users Manual 78K0 Instructions UM

2015-01-24

• COVER
• Major Revisions in This Edition
• INTRODUCTION
• CHAPTER 1 MEMORY SPACE
  • 1.1 Memory Spaces
  • 1.2 Internal Program Memory (Internal ROM) Space
  • 1.3 Vector Table Area
  • 1.4 CALLT Instruction Table Area
  • 1.5 CALLF Instruction Entry Area
  • 1.6 Internal Data Memory (Internal RAM) Space
  • 1.7 Special Function Register (SFR) Area
  • 1.8 External Memory Space
  • 1.9 IEBus Register Area
• CHAPTER 2 REGISTERS
  • 2.1 Control Registers
    • 2.1.1 Program counter (PC)
    • 2.1.2 Program status word (PSW)
    • 2.1.3 Stack pointer (SP)
  • 2.2 General-Purpose Registers
  • 2.3 Special Function Registers (SFRs)
• CHAPTER 3 ADDRESSING
  • 3.1 Instruction Address Addressing
    • 3.1.1 Relative addressing
    • 3.1.2 Immediate addressing
    • 3.1.3 Table indirect addressing
    • 3.1.4 Register addressing
  • 3.2 Operand Address Addressing
    • 3.2.1 Implied addressing
    • 3.2.2 Register addressing
    • 3.2.3 Direct addressing
    • 3.2.4 Short direct addressing
    • 3.2.5 Special-function register (SFR) addressing
    • 3.2.6 Register indirect addressing
    • 3.2.7 Based addressing
    • 3.2.8 Based indexed addressing
    • 3.2.9 Stack addressing
• CHAPTER 4 INSTRUCTION SET
  • 4.1 Operation
    • 4.1.1 Operand identifiers and description methods
    • 4.1.2 Description of “operation” column
    • 4.1.3 Description of “flag operation” column
    • 4.1.4 Description of number of clocks
    • 4.1.5 Instructions listed by addressing type
  • 4.2 Instruction Codes
    • 4.2.1 Description of instruction code table
    • 4.2.2 Instruction code list
• CHAPTER 5 EXPLANATION OF INSTRUCTIONS
  • 5.1 8-Bit Data Transfer Instructions
  • 5.2 16-Bit Data Transfer Instructions
  • 5.3 8-Bit Operation Instructions
  • 5.4 16-Bit Operation Instructions
  • 5.5 Multiply/Divide Instructions
  • 5.6 Increment/Decrement Instructions
  • 5.7 Rotate Instructions
  • 5.8 BCD Adjust Instructions
  • 5.9 Bit Manipulation Instructions
  • 5.10 Call Return Instructions
  • 5.11 Stack Manipulation Instructions
  • 5.12 Unconditional Branch Instruction
  • 5.13 Conditional Branch Instructions
  • 5.14 CPU Control Instructions
• APPENDIX A REVISION HISTORY
• APPENDIX B INSTRUCTION INDEX (MNEMONIC: BY FUNCTION)
• APPENDIX C INSTRUCTION INDEX (MNEMONIC: IN ALPHABETICAL ORDER)