Nexus 21 1066Mt S Interposer Users Manual NEX NEXVuDDR800M X
1066MTs Interposer to the manual 0f8e1930-12e6-4c16-8b9b-dc677d1a1114
2015-02-05
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NEX-DDR3INTR-THIN DDR3 800/1066MT/s Interposer For use with the TLA7BB4 Logic Analyzer Modules Including these Software Support packages: B_DDR3D_2D (Single/Dual/Quad Rank, single slot with Selective Clocking) *B_DDR3D_2G (2 or 3 DIMM slots, two Rank @ 800MT/s) *B_DDR3D_3A (2 DIMM slots, two Rank @ 1066MT/s) * Optional Software Copyright © 2007 Nexus Technology, Inc. All rights reserved. Contents of this publication may not be reproduced in any form without the written permission of Nexus Technology, Inc. Brand and product names used throughout this manual are the trademarks of their respective holders. DDR3THIN-MN-XXX 1 Doc. Rev. 1.11 Product Warranty Due to wide variety of possible customer target implementations, this product has a 30 day acceptance period by the customer from the date of receipt. If the customer does not contact Nexus Technology within 30 days of the receipt of the product, it will be said that the customer has accepted the product. If the customer is not satisfied with this product, they may return it within 30 days for a refund. This Nexus Technology product has a warranty against defects in material and workmanship for a period of 1 year from the date of shipment. During the warranty period, Nexus Technology will, at its option, either replace or repair products proven to be defective. For warranty service or repair, this product must be returned to the factory. For products returned to Nexus Technology for warranty service, the Buyer shall prepay shipping charges to Nexus Technology and Nexus Technology shall pay shipping charges to return the product to the Buyer. However, the Buyer shall pay all shipping charges, duties, and taxes for products returned to Nexus Technology from another country. Nexus Technology warrants that its software and hardware designated by Nexus Technology for use with an instrument will execute its programming instructions when properly installed on that instrument. Nexus Technology does not warrant that the operation of the hardware or software will be uninterrupted or error-free. Limitation of Warranty The foregoing warranty shall not apply to defects resulting from improper or inadequate maintenance by the Buyer, Buyer-supplied software or interfacing, unauthorized modification or misuse, operation outside of the environmental specifications for the product, or improper site preparation or maintenance. NO OTHER WARRANTY IS EXPRESSED OR IMPLIED. NEXUS TECHNOLOGY SPECIFICALLY DISCLAIMS THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Exclusive Remedies THE REMEDIES PROVIDED HERIN ARE BUYER’S SOLE AND EXCLUSIVE REMEDIES. NEXUS TECHNOLOGY SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES, WHETHER BASED ON CONTRACT, TORT OR ANY OTHER LEGAL THEORY. Software License Agreement IMPORTANT – Please read this license agreement carefully before opening the CD case. Rights in the software are offered only on the condition that the customer agrees to all terms and conditions of the license agreement. Opening the CD case indicates your acceptance of these terms and conditions. If you do not agree to the licensing agreement, you may return the unopened package for a full refund. DDR3THIN-MN-XXX 2 Doc. Rev. 1.11 License Agreement In return for payment for this product, Nexus Technology grants the Customer a SINGLE user LICENSE in the software subject to the following: Use of the Software: - Customer may use the software on only one Tektronix mainframe logic analysis system at any given time - Customer may make copies or adaptations of the software (see Copies and Adaptations below for more information) - Customer may NOT reverse assemble or decompile the software Copies and Adaptations: - Are allowed for archival purpose only - When copying for adaptation is an essential step in the use of the software with the logic analyzer and/or logic analysis mainframe so long as the copies and adaptations are used in no other manner. Customer has no right to copy software unless it acquires an appropriate license to reproduce from Nexus Technology. - Customer agrees that it does not have any title or ownership of the software, other than the physical media. Ownership: - Customer acknowledges and agrees that the software is copyrighted and protected under the copyright laws. - Transfer of the right of ownership shall only be done with the consent of Nexus Technology. Sublicensing and Distribution: - Customer may not sublicense the software or distribute copies of the software to the public in physical media or by electronic means or any other means without the prior written consent of Nexus Technology. Compliance with WEEE and RoHS Directives This product is subject to European Union regulations on Waste Electrical and Electronics Equipment. Return to Nexus Technology for recycle at end of life. Costs associated with the return to Nexus Technology are the responsibility of the sender. DDR3THIN-MN-XXX 3 Doc. Rev. 1.11 TABLE OF CONTENTS 1.0 OVERVIEW ........................................................................................................................... 9 1.1 General Information ............................................................................................................ 9 1.2 Software Package description.............................................................................................. 9 1.3 Eye size required ............................................................................................................... 11 2.0 SOFTWARE INSTALLATION ........................................................................................... 11 3.0 CONNECTING to the NEX-DDR3INTR-THIN INTERPOSER ........................................ 12 3.1 General .............................................................................................................................. 12 3.2 B_DDR3D_2D Support..................................................................................................... 12 3.3 B_DDR3D_2G Support..................................................................................................... 12 3.4 B_DDR3D_3A Support..................................................................................................... 13 3.5 Short “LEASH” probes ..................................................................................................... 15 3.5.1 Samtec connector on the LEASH probe pins ............................................................ 16 3.5.2 LEASH probe to NEX-PRB1X/2X connection......................................................... 17 3.5.3 Alternate use of NEX-PRB1X or NEX-PRB2X probes ............................................ 17 3.6 Slot Numbering............................................................................................................. 18 3.7 Display Groups not in Tables 1,2 or 3............................................................................... 39 4.0 CLOCK SELECTION .......................................................................................................... 40 4.1 B_DDR3D_2D Clocking Selections ................................................................................. 40 4.2 B_DDR3D_2G Clocking Selections ................................................................................. 41 4.3 B_DDR3D_3A Clocking Selections ................................................................................. 43 5.0 CONFIGURING FOR READ / WRITE DATA ACQUISITION........................................ 44 5.1 A Note About the Different Data Groups.......................................................................... 44 5.2 MagniVu Signals ............................................................................................................... 44 5.3 Adjusting Input Thresholds for Proper Data Acquisition.................................................. 53 5.4 DDR3 and DDR3SPA ....................................................................................................... 53 5.5 Selecting B_DDR3E_XX Read Data Sample Points ........................................................ 53 5.6 Selecting B_DDR3D_XX Write Data Sample Points....................................................... 54 5.7 B_DDR3D_XX Support Setup.......................................................................................... 55 5.8 Setting B_DDR3D_3A Read Data Sample Points ............................................................ 62 6.0 VIEWING DATA ................................................................................................................. 63 6.1 Viewing B_DDR3D_XX Data .......................................................................................... 63 6.2 Viewing Raw DDR3 Data using B_DDR3D_XX Supports......................................... 66 6.3 B_DDR3D_2A / 3A Mnemonics Description................................................................... 66 6.4 B_DDR3D_2G Mnemonics Description........................................................................... 66 6.5 Viewing Timing Data on the TLA .................................................................................... 67 7.0 HINTS & TIPS ..................................................................................................................... 69 7.1 Symbolic Triggering on a Command using B_DDR3D_XX Supports............................. 69 7.3 Capturing MRS (Mode Register Set) Cycles .................................................................... 70 7.4 Clock Capture quality........................................................................................................ 71 7.5 Thresholds ......................................................................................................................... 72 APPENDIX A – How DDR Data is Clocked ............................................................................... 73 A.1 Background....................................................................................................................... 73 A.2 DDR Acquisition - General .............................................................................................. 73 A.3 B_DDR3D_2D / 2G / 3A Data Acquisition ..................................................................... 74 APPENDIX B - Considerations.................................................................................................... 75 B.1 NEX-DDR3INTR-THIN Bus Loading............................................................................. 75 B.2 DIMM connector location for best quality signal capture................................................ 75 DDR3THIN-MN-XXX 4 Doc. Rev. 1.11 B.3 TLA7BB4 Module to module skew.................................................................................. 75 APPENDIX C – 240-pin DDR3 DIMM Pinout ........................................................................... 76 APPENDIX D –Data Flow Through the Probes (coax cable to channel) .................................... 78 APPENDIX E – B_DDR3D_2D Support Pinout, DIMM Slot 0.................................................. 80 APPENDIX F – B_DDR3_2G Support Pinout, DIMM Slot 0 Auxiliary Signals ....................... 82 APPENDIX G – B_DDR3D_3A Support Pinout, DIMM Slot 1 ................................................. 84 APPENDIX H – Data Group / Data Byte / Strobe Cross-Reference............................................ 86 APPENDIX I – NEX-DDR3INTR-THIN Silkscreen................................................................... 87 APPENDIX J – Keep out area ...................................................................................................... 88 APPENDIX K – Simulation Model.............................................................................................. 89 APPENDIX L - References .......................................................................................................... 90 APPENDIX M - Support .............................................................................................................. 91 DDR3THIN-MN-XXX 5 Doc. Rev. 1.11 TABLE OF FIGURES Figure 1 – Drawing of Interposer with probes attached ............................................................... 15 Figure 2 – Samtec connector on the LEASH probe...................................................................... 16 Figure 3 – LEASH probe to NEX-PRB1X/2X connection .......................................................... 17 Figure 4 - Read Data Latency = CAS Latency + CAS Additive Latency + RDIMM (5+0+1) = 6 cycles) ........................................................................................................................................... 54 Figure 5 - Write Data Latency = CAS Write Latency + RDIMM (5+1) = 6 cycles..................... 54 Figure 6 - Locating Minimum Valid B_DDR3D_XX Read Data Window ................................. 55 Figure 7 - Measuring B_DDR3D_XX RdA_DatHi / Lo Read Data Setup & Hold ..................... 56 Figure 8 - Measuring B_DDR3D_XX RdB_DatHi / Lo Read Data Setup & Hold ..................... 57 Figure 9 - Setting B_DDR3D_XX RdA_DatHi / Lo and RdB_DatHi / Lo Sample Points ......... 57 Figure 10 - Locating Minimum Valid B_DDR3D_XX Write Data Window .............................. 58 Figure 11 - Measuring B_DDR3D_XX WrA_DatHi / Lo Write Data Setup & Hold.................. 59 Figure 12 - Measuring B_DDR3D_XX WrB_DatHi / Lo Write Data Setup & Hold.................. 59 Figure 13 - Setting B_DDR3D_XX WrA_DatHi / Lo and WrB_DatHi / Lo Sample Points ...... 60 Figure 14 - Viewing Individual 8-bit Read Data Groups ............................................................. 61 Figure 15 - Setting Individual Setup & Hold Values for the 8-bit Read Data Groups................. 61 Figure 16 - B_DDR3D_XX Listing Display ................................................................................ 63 Figure 17 - Disassembly Properties .............................................................................................. 64 Figure 18 - B_DDR3D_XX Listing Display - Control Flow ....................................................... 65 Figure 19 - B_DDR3D_XX MagniVu Display on TLA .............................................................. 68 Figure 20 - B_DDR3D_2D MRS Trigger .................................................................................... 71 Figure 21 - MRS Cycle Acquisition Disassembly........................................................................ 71 DDR3THIN-MN-XXX 6 Doc. Rev. 1.11 TABLE OF TABLES Table 1 - B_DDR3D_2D (<=1066MT/s Read and Write) TLA Channel Grouping.................... 19 Table 2 - B_DDR3D_2G (<=1066MT/s Read and Write) TLA Channel Grouping.................... 25 Table 3 - B_DDR3D_3A (<=1066MT/s Read and Write) TLA Channel Grouping.................... 31 Table 4 - B_DDR3D_2D/_2G TLA MagniVu Channel Grouping .............................................. 45 Table 5 - B_DDR3D_3A TLA MagniVu Channel Grouping ...................................................... 48 Table 6 - B_DDR3D_2A / 3A Mnemonics Definition................................................................. 66 Table 7 - B_DDR3D_2G Mnemonics Definition......................................................................... 67 Table 8 - B_DDR3D_2D / 3A Control Symbol Table ................................................................ 69 Table 9 - B_DDR3D_2G Control Symbol Table ........................................................................ 70 DDR3THIN-MN-XXX 7 Doc. Rev. 1.11 DDR3THIN-MN-XXX 8 Doc. Rev. 1.11 1.0 OVERVIEW 1.1 General Information The DDR3 Interposer Products are designed for ease of use. Interposers extra signal trace length, also an extra connector that might affect the quality of the system operation in some systems. • This Product is designed for capture of 1066MT/s or slower, and may only be used with the Tektronix TLA7BB4 acquisition modules. This product requires the use of the new NEX-PRB1X-T / PRB2X-T Low Profile Distributed probes available from Nexus. Tektronix P68xx or P69xx probes can not be used. This Interposer has been designed to provide a quick and easy connection to interface to a Tektronix TLA7BB4 Logic Analyzer acquisition cards to a 240-pin DDR3 (Double Data Rate 3) bus. Contact NEXUS Technology for other available DDR3 Products. The Nexus Technology web site (www.NexusTechnology.com) contains information on the latest software release. 1.2 Software Package description The NEX-DDR3INTR-THIN support includes the following software packages: B_DDR3D_2D allows the user to acquire Read AND Write data from a single, dual or quad rank DDR3 DIMM running 1066MT/s or less. This support requires 1ea. NEXPRB1X-T and 3ea. NEX-PRB2X-T Low Profile Distributed probes, and two merged Tektronix TLA7BB4 acquisition cards. This support can use selective clocking to reduce the number of Idle states acquired by the logic analyzer. Optional software available for the NEX-DDR3INTR-THIN support includes the following software packages: B_DDR3D_2G allows the user to acquire Read AND Write data from a memory channel made up of two or three DIMM slots with one or two rank DDR3 DIMMs running 800MT/s or less. This is total disassembly for the 3 DIMM memory channel. This support requires 2ea. NEX-PRB1X-T and 3ea. NEX-PRB2X-T Low Profile Distributed probes, and two merged Tektronix TLA7BB4 acquisition cards. This support also requires the NEX-PRBCOAX product. This support can be used with Single Rank and Dual Rank DIMMs (will also support a single quad rank DIMM). Reads for the three DIMMs must have a common data eye (over lap) of 330ps. No selective clocking B_DDR3D_3A allows the user to acquire Read AND Write data from a memory channel made up of two DIMM slots with single or dual rank DDR3 DIMMs running 1066MT/s or less. This is total disassembly for the 2 DIMM memory channel. This support requires 5ea. NEX-PRB1X-T and 3ea. NEX-PRB2X-T Low Profile Distributed probes, and three merged Tektronix TLA7BB4 acquisition cards. This support also requires two DDR3THIN-MN-XXX 9 Doc. Rev. 1.11 NEX-DDR3INTR-THIN Interposer products. This support can be used with Single Rank and Dual Rank DIMMs. Note that this manual uses some terms generically. For instance, references to the TLA700/7000 apply to all suitable TLA700/7000 Logic Analyzers, or PCs being used to control the TLA. NEX-DDR3INTR-THIN refers to the B_DDR3D_2D/2G/3A software support packages. Appendix G has a silk-screened print of the NEX-DDR3INTR-THIN Logic Analyzer Interposer board. Referring to this drawing while reading the manual is suggested. This manual assumes that the user is familiar with the DDR3 SDRAM Specification and the Tektronix TLA Logic Analyzers. It is also expected that the user is familiar with the Windows environment used with the TLA. DDR3THIN-MN-XXX 10 Doc. Rev. 1.11 1.3 Eye size required The Eye size (stable data) required at the input resistor to the Nexus passive probes (NEXPRB1X(-T) & NEX-PRB2X(-T)) is 330ps, and 0.2V. Capture accuracy may be affected if a stable eye can not meet this requirement. . The eye is a perfectly shaped diamond with each side equal distant from the center. 2.0 SOFTWARE INSTALLATION To Install the NEX-DDR3INTR-THIN software support place the B_DDR3D_XX Install CD in the CD drive of the TLA or the PC being used to control the TLA. Using Windows Explorer select the CD, navigate to the support_software folder, select the folder of the support to be installed (B_DDR3D_2D, B_DDR3D_2G or B_DDR3D_3A) and then run the .MSI file within the folder. The selected software will be installed on the TLA’s hard disk. To load the support into the TLA, first select the desired Logic Analyzer module (different supports require different module counts) in the Setup window, select Load Support Package from the File pull-down, then choose the software package name you are want to load and click on Okay. Note that this support requires two or more merged modules and that the TLA acquisition cards must be configured properly for the software to load. DDR3THIN-MN-XXX 11 Doc. Rev. 1.11 3.0 CONNECTING to the NEX-DDR3INTR-THIN INTERPOSER 3.1 General Care should be taken to support the weight of the acquisition probes so that the Logic Analyzer Interposer board and/or target socket are not damaged. 3.2 B_DDR3D_2D Support To acquire DDR3 Read and Write data at speeds up to 1066MT/s requires two merged TLA7BB4 136-channel, with 1.4G state option, acquisition cards and the use of the B_DDR3D_2D support software. The Master card will be in the lower numbered of the two cards. Slave card #1 is in the adjacent high-numbered slots. The logic analyzer modules should be connected to the DDR3 DIMM Interposer as follows using (1) NEX-PPRB1X-T probes and three (3) NEX-PRB2X-T probes: TLA Master Connect the NEX-PRB1X-T “C” probe head to DDR3 Interposer’s LEASH (soldered-on coax cable) that is attached to “M_C” position on the Interposer. Connect the NEX-PRB2X-T A3/2 & A1/0 probe head to DDR3 Interposer’s LEASH that is attached to “M_ A3/2 A1/0” position on the Interposer. Match the label on the end of the NEX-PRB1X-T/2X-T probes with the labels on the front of the Tektronix Logic Analyzer Master module and connect. TLA Slave Connect the NEX-PRB2X-T A3/2 & A1/0 probe head to DDR3 Interposer’s LEASH that is attached to “S_ A3/2 A1/0” position on the Interposer. Connect the NEX-PRB2X-T “C3/2” & “E3/2” probe head to DDR3 Interposer’s LEASH that is attached to “S_C3/2 E3/2” position on the Interposer. See Figure 1 for connections. Table 1 shows the Channel Grouping / Wiring for use with the B_DDR3D_2D support. 3.3 B_DDR3D_2G Support To acquire DDR3 Read and Write data from two or three DIMM slots, for total memory channel disassembly, at speeds up to 800MT/s requires two merged TLA7BB4 136-channel, with 1.4G state option, acquisition cards and the use of the B_DDR3D_2G optional support software. The Master card will be in the lower numbered, of the two cards. Slave card #1 will be in the adjacent high-numbered slots. This support requires an additional NEX-PRB1X-T (for a total of 2), and the NEX-PRBCOAX product. The logic analyzer modules should be connected to the DDR3 DIMM Interposer as follows using (1) NEX-PPRB1X-T probes and three (3) NEXPRB2X-T probes, with the additional NEX-PRB1X-T connected to the NEX-PRBCOAX: DDR3THIN-MN-XXX 12 Doc. Rev. 1.11 TLA Master Connect the NEX-PRB1X-T “C” probe head to DDR3 Interposer’s LEASH (soldered-on coax cable) that is attached to “M_C” position on the Interposer. Connect the NEX-PRB2X-T A3/2 & A1/0 probe head to DDR3 Interposer’s LEASH that is attached to “M_ A3/2 A1/0” position on the Interposer. Connect the NEX-PRB1X-T “E” probe head to the NEX-PRBCOAX. Note the leads 9- 12 of the NEX-PRBCOAX must be connected to the second slots Chip Select lines (CS) near the second and third DIMM socket, usually on the back of the mother board. Match the label on the end of the NEX-PRB1X-T/2X-T probes with the labels on the front of the Tektronix Logic Analyzer Master module and connect. TLA Slave Connect the NEX-PRB2X-T A3/2 & A1/0 probe head to DDR3 Interposer’s LEASH that is attached to “S_ A3/2 A1/0” position on the Interposer. Connect the NEX-PRB2X-T “C3/2” & “E3/2” probe head to DDR3 Interposer’s LEASH that is attached to “S_C3/2 E3/2” position on the Interposer. See Figure 1 for connections. Table 2 shows the Channel Grouping / Wiring for use with the B_DDR3D_2G support. 3.4 B_DDR3D_3A Support To acquire DDR3 Read and Write data from a two DIMM slots, for total memory channel disassembly, at speeds up to 1066MT/s requires three merged TLA7BB4 136-channel, with 1.4G state option, acquisition cards and the use of the B_DDR3D_3A optional support software. The Master card will be in the lower numbered, of the three cards. Slave card #1 will be in the adjacent high-numbered slots. Slave card #2 will be in the adjacent low-numbered slots. This support also requires two NEX-DDR3INTR-THIN Interposer products. The logic analyzer modules should be connected to the DDR3 DIMM Interposer as follows using (5) NEXPPRB1X-T probes and three (3) NEX-PRB2X-T probes: TLA Master Connect the NEX-PRB1X-T “C” probe head to DDR3 Interposer’s LEASH (soldered-on coax cable) that is attached to “M_C” position on the Interposer. Connect the NEX-PRB2X-T A3/2 & A1/0 probe head to DDR3 Interposer’s LEASH that is attached to “M_ A3/2 A1/0” position on the Interposer. Match the label on the end of the NEX-PRB1X-T/2X-T probes with the labels on the front of the Tektronix Logic Analyzer Master module and connect. DDR3THIN-MN-XXX 13 Doc. Rev. 1.11 TLA Slave1 Connect the NEX-PRB2X-T A3/2 & A1/0 probe head to DDR3 Interposer’s LEASH that is attached to “S_ A3/2 A1/0” position on the Interposer. Connect the NEX-PRB2X-T “C3/2” & “E3/2” probe head to DDR3 Interposer’s LEASH that is attached to “S_C3/2 E3/2” position on the Interposer. TLA Slave2 Connect the NEX-PRB1X-T A3/2 D3/2 probe head to DDR3 Interposer’s LEASH that is attached to “M_A3/2 A1/0” position on the second Interposer. Connect the NEX-PRB1X-T A1/0 D1/0 probe head to DDR3 Interposer’s LEASH that is attached to “S_A3/2 A1/0” position on the second Interposer. Connect the NEX-PRB1X-T “C” probe head to DDR3 Interposer’s LEASH that is attached to “M_C3/2 C1/0” position on the second Interposer. Connect the NEX-PRB1X-T “E” probe head to DDR3 Interposer’s LEASH that is attached to “S_C3/2 E3/2” position on the second Interposer. See Figure 1 for connections. Table 3 shows the Channel Grouping / Wiring for use with the B_DDR3D_3A support. DDR3THIN-MN-XXX 14 Doc. Rev. 1.11 3.5 Short “LEASH” probes The standard product includes 4 “LEASH” probes connected to this Interposer product. These short probes are soldered directly onto the interposer and interface the Interposer to the Passive probes that connect to the logic analyzer. These “LEASH” probes are to allow the user to easily install and remove the Interposer product in their system with out the added weight of the passive probe attached. There may be other probing options in the future. Contact Nexus for any updates. Figure 1 below shows the location on the Interposer of the LEASH probe connections. Location of HCD connectors, right under metal compression plate, and probe tip board: S_C3/2 PRB2 M_A3/2 A1/0 PRB2 M_ PRB1 S_A3/2 A1/0 PRB2 Figure 1 – Drawing of Interposer with probes attached The four (4) each, 1 foot long, “LEASH” probes that are soldered onto the Interposer are in turn connected to either a NEX-PRB1X-T or NEX-PRB2X-T probe. The NEX-PRB1X-T or NEXPRB2X-T probe in turn connects to the input of the logic analyzer modules. The connection between the LEASH Probes and the logic Analyzer is a Samtec connector with a pin out as shown below on the LEASH probe. Refer to 3.2 to determine if a NEX-PRB1X-T or NEXPRB2X-T connects to each LEASH probe. DDR3THIN-MN-XXX 15 Doc. Rev. 1.11 The strain relief on the LEASH to NEXPRB1X/2X interface, while designed for bench handling, can be damaged by twisting the coax cables. Bends of over 45 degrees in this area should be avoided. The coax connection points, under any circumstances, are not to be bent. 3.5.1 Samtec connector on the LEASH probe pins Figure 2 – Samtec connector on the LEASH probe The LEASH probe connects to the NEX-PRB1X-T or NEX-PRB2X-T probe using two plastic nuts and screws, with a plastic spacer between the two boards. These parts are supplied. DDR3THIN-MN-XXX 16 Doc. Rev. 1.11 3.5.2 LEASH probe to NEX-PRB1X/2X connection Probe tip on the NEX-PRB1X-T or NEX-PRB2X-T Interposer here Two each plastic Spacers Screws & Nuts Hold each probe together Transition board on the “LEASH” Cable end Figure 3 – LEASH probe to NEX-PRB1X/2X connection 3.5.3 Alternate use of NEX-PRB1X or NEX-PRB2X probes The NEX-PRB1X or NEX-PRB2X can be used in place of the “-T” probes but will have to be secured for long term connection by tie-wraps. DDR3THIN-MN-XXX 17 Doc. Rev. 1.11 3.6 Slot Numbering The Interposer must be installed in the furthest slot from the memory controller. For 1066MT/s support only the two furthest slots may be used. Slots are named as shown below: Slot naming for a three slot system Memory controller Slot C Slot B cS0-1# cCLKE0-1 (from NEXPRBCOAX) Slot A bS0-1# S0-3# bCLKE0-1 CLKE0(from NEXPRBCOAX) If only one slot is used it must be the furthest slot from the memory controller. If two slots are used they must be the furthest slots from the memory controller. Quad rank is only supported in the single slot configuration Interposer in any two or three slot configuration must be in the furthest slot. 1066MT/s full channel support (B_DDR3D_3A) requires two interposers in the two furthest slots from the memory controller. DDR3THIN-MN-XXX 18 Doc. Rev. 1.11 Group Name RdA_DatHi (Hex) Signal Name RD_A_DQ63 RD_A_DQ62 RD_A_DQ61 RD_A_DQ60 RD_A_DQ59 RD_A_DQ58 RD_A_DQ57 RD_A_DQ56 RD_A_DQ55 RD_A_DQ54 RD_A_DQ53 RD_A_DQ52 RD_A_DQ51 RD_A_DQ50 RD_A_DQ49 RD_A_DQ48 RD_A_DQ47 RD_A_DQ46 RD_A_DQ45 RD_A_DQ44 RD_A_DQ43 RD_A_DQ42 RD_A_DQ41 RD_A_DQ40 RD_A_DQ39 RD_A_DQ38 RD_A_DQ37 RD_A_DQ36 RD_A_DQ35 RD_A_DQ34 RD_A_DQ33 RD_A_DQ32 DDR3 Pin # 234 233 228 227 115 114 109 108 225 224 219 218 106 105 100 99 216 215 210 209 97 96 91 90 207 206 201 200 88 87 83 81 TLA Input S_A2:0 S_A2:1 S_A2:5 S_CK0 S_A2:2 S_A2:3 S_A2:7 S_A3:0 S_A3:2 S_A3:3 S_A3:7 S_A1:5 S_A3:1 S_A3:4 S_A1:7 S_A1:6 S_A1:4 S_A1:1 S_A0:7 S_A0:6 S_A1:3 S_A1:2 S_A0:5 S_A0:4 S_A0:3 S_A0:2 M_C2:1 M_C2:4 S_A0:1 S_A0:0 M_C2:6 M_C2:7 Group Name RdA_DatLo (Hex) Signal Name RD_A_DQ31 RD_A_DQ30 RD_A_DQ29 RD_A_DQ28 RD_A_DQ27 RD_A_DQ26 RD_A_DQ25 RD_A_DQ24 RD_A_DQ23 RD_A_DQ22 RD_A_DQ21 RD_A_DQ20 RD_A_DQ19 RD_A_DQ18 RD_A_DQ17 RD_A_DQ16 RD_A_DQ15 RD_A_DQ14 RD_A_DQ13 RD_A_DQ12 RD_A_DQ11 RD_A_DQ10 RD_A_DQ9 RD_A_DQ8 RD_A_DQ7 RD_A_DQ6 RD_A_DQ5 RD_A_DQ4 RD_A_DQ3 RD_A_DQ2 RD_A_DQ1 RD_A_DQ0 DDR3 Pin # 156 155 150 149 37 36 31 30 147 146 141 140 28 27 22 21 138 137 132 131 19 18 13 12 129 128 123 122 10 9 4 3 TLA Input M_A0:6 M_A0:3 S_C2:0 S_C2:1 M_A0:4 M_A0:1 S_C2:2 S_C2:3 S_C2:4 S_C2:5 S_C3:2 S_C3:3 S_C2:6 S_C2:7 S_C3:1 S_C3:4 S_C3:6 S_C3:7 S_E3:4 S_E3:1 S_C3:5 S_E3:7 S_E3:3 S_E3:2 S_E3:0 S_E2:7 S_E2:3 S_E2:2 S_Q3 S_E2:5 S_E2:1 S_E2:0 Table 1 - B_DDR3D_2D (<=1066MT/s Read and Write) TLA Channel Grouping Notes: 1. All signals on this page are required for accurate post-processing of acquired data 2. The ‘S’ in front of a TLA channel denotes the Slave card of the merged pair DDR3THIN-MN-XXX 19 Doc. Rev. 1.11 Group Name RdB_DatHi (Hex) Signal Name DDR3 Pin# TLA Input RD_B_DQ63 RD_B_DQ62 RD_B_DQ61 RD_B_DQ60 RD_B_DQ59 RD_B_DQ58 RD_B_DQ57 RD_B_DQ56 RD_B_DQ55 RD_B_DQ54 RD_B_DQ53 RD_B_DQ52 RD_B_DQ51 RD_B_DQ50 RD_B_DQ49 RD_B_DQ48 RD_B_DQ47 RD_B_DQ46 RD_B_DQ45 RD_B_DQ44 RD_B_DQ43 RD_B_DQ42 RD_B_DQ41 RD_B_DQ40 RD_B_DQ39 RD_B_DQ38 RD_B_DQ37 RD_B_DQ36 RD_B_DQ35 RD_B_DQ34 RD_B_DQ33 RD_B_DQ32 234 233 228 227 115 114 109 108 225 224 219 218 106 105 100 99 216 215 210 209 97 96 91 90 207 206 201 200 88 87 83 81 S_A2:0^1 S_A2:1^1 S_A2:5^1 S_CK0^1 S_A2:2^1 S_A2:3^1 S_A2:7^1 S_A3:0^1 S_A3:2^1 S_A3:3^1 S_A3:7^1 S_A1:5^1 S_A3:1^1 S_A3:4^1 S_A1:7^1 S_A1:6^1 S_A1:4^1 S_A1:1^1 S_A0:7^1 S_A0:6^1 S_A1:3^1 S_A1:2^1 S_A0:5^1 S_A0:4^1 S_A0:3^1 S_A0:2^1 M_C2:1^1 M_C2:4^1 S_A0:1^1 S_A0:0^1 M_C2:6^1 M_C2:7^1 Group Name RdB_DatLo (Hex) Signal Name DDR3 Pin# TLA Input RD_B_DQ31 RD_B_DQ30 RD_B_DQ29 RD_B_DQ28 RD_B_DQ27 RD_B_DQ26 RD_B_DQ25 RD_B_DQ24 RD_B_DQ23 RD_B_DQ22 RD_B_DQ21 RD_B_DQ20 RD_B_DQ19 RD_B_DQ18 RD_B_DQ17 RD_B_DQ16 RD_B_DQ15 RD_B_DQ14 RD_B_DQ13 RD_B_DQ12 RD_B_DQ11 RD_B_DQ10 RD_B_DQ9 RD_B_DQ8 RD_B_DQ7 RD_B_DQ6 RD_B_DQ5 RD_B_DQ4 RD_B_DQ3 RD_B_DQ2 RD_B_DQ1 RD_B_DQ0 156 155 150 149 37 36 31 30 147 146 141 140 28 27 22 21 138 137 132 131 19 18 13 12 129 128 123 122 10 9 4 3 M_A0:6^1 M_A0:3^1 S_C2:0^1 S_C2:1^1 M_A0:4^1 M_A0:1^1 S_C2:2^1 S_C2:3^1 S_C2:4^1 S_C2:5^1 S_C3:2^1 S_C3:3^1 S_C2:6^1 S_C2:7^1 S_C3:1^1 S_C3:4^1 S_C3:6^1 S_C3:7^1 S_E3:4^1 S_E3:1^1 S_C3:5^1 S_E3:7^1 S_E3:3^1 S_E3:2^1 S_E3:0^1 S_E2:7^1 S_E2:3^1 S_E2:2^1 S_Q3^1 S_E2:5^1 S_E2:1^1 S_E2:0^1 Table 1 – B_DDR3D_2D (<=1066MT/s Read and Write) TLA Channel Grouping (cont’d.) Notes: 1. All signals on this page are required for accurate post-processing of acquired data 2. The ‘S’ in front of a TLA channel denotes the Slave card of the merged pair 3. All signals on this page are stored in the TLA7BB4’s Prime memory and will not have a MagniVu display value DDR3THIN-MN-XXX 20 Doc. Rev. 1.11 Group Name WrA_DatHi (Hex) Signal Name WR_A_DQ63 WR_A_DQ62 WR_A_DQ61 WR_A_DQ60 WR_A_DQ59 WR_A_DQ58 WR_A_DQ57 WR_A_DQ56 WR_A_DQ55 WR_A_DQ54 WR_A_DQ53 WR_A_DQ52 WR_A_DQ51 WR_A_DQ50 WR_A_DQ49 WR_A_DQ48 WR_A_DQ47 WR_A_DQ46 WR_A_DQ45 WR_A_DQ44 WR_A_DQ43 WR_A_DQ42 WR_A_DQ41 WR_A_DQ40 WR_A_DQ39 WR_A_DQ38 WR_A_DQ37 WR_A_DQ36 WR_A_DQ35 WR_A_DQ34 WR_A_DQ33 WR_A_DQ32 DDR3 Pin # 234 233 228 227 115 114 109 108 225 224 219 218 106 105 100 99 216 215 210 209 97 96 91 90 207 206 201 200 88 87 83 81 TLA Input S_D2:0 S_D2:1 S_D2:5 S_Q1 S_D2:2 S_D2:3 S_D2:7 S_D3:0 S_D3:2 S_D3:3 S_D3:7 S_D1:5 S_D3:1 S_D3:4 S_D1:7 S_D1:6 S_D1:4 S_D1:1 S_D0:7 S_D0:6 S_D1:3 S_D1:2 S_D0:5 S_D0:4 S_D0:3 S_D0:2 M_C0:1 M_C0:4 S_D0:1 S_D0:0 M_C0:6 M_C0:7 Group Name WrA_DatLo (Hex) Signal Name WR_A_DQ31 WR_A_DQ30 WR_A_DQ29 WR_A_DQ28 WR_A_DQ27 WR_A_DQ26 WR_A_DQ25 WR_A_DQ24 WR_A_DQ23 WR_A_DQ22 WR_A_DQ21 WR_A_DQ20 WR_A_DQ19 WR_A_DQ18 WR_A_DQ17 WR_A_DQ16 WR_A_DQ15 WR_A_DQ14 WR_A_DQ13 WR_A_DQ12 WR_A_DQ11 WR_A_DQ10 WR_A_DQ9 WR_A_DQ8 WR_A_DQ7 WR_A_DQ6 WR_A_DQ5 WR_A_DQ4 WR_A_DQ3 WR_A_DQ2 WR_A_DQ1 WR_A_DQ0 DDR3 Pin # 156 155 150 149 37 36 31 30 147 146 141 140 28 27 22 21 138 137 132 131 19 18 13 12 129 128 123 122 10 9 4 3 TLA Input M_D0:6 M_D0:3 S_C0:0 S_C0:1 M_D0:4 M_D0:1 S_C0:2 S_C0:3 S_C0:4 S_C0:5 S_C1:2 S_C1:3 S_C0:6 S_C0:7 S_C1:1 S_C1:4 S_C1:6 S_C1:7 S_E1:4 S_E1:1 S_C1:5 S_E1:7 S_E1:3 S_E1:2 S_E1:0 S_E0:7 S_E0:3 S_E0:2 S_CK2 S_E0:5 S_E0:1 S_E0:0 Table 1 – B_DDR3D_2D (<=1066MT/s Read and Write) TLA Channel Grouping (cont’d.) Notes: 1. All signals on this page are required for accurate post-processing of acquired data 2. The ‘S’ in front of a TLA channel denotes the Slave card of the merged pair DDR3THIN-MN-XXX 21 Doc. Rev. 1.11 Group Name WrB_DatHi (Hex) Signal Name WR_B_DQ63 WR_B_DQ62 WR_B_DQ61 WR_B_DQ60 WR_B_DQ59 WR_B_DQ58 WR_B_DQ57 WR_B_DQ56 WR_B_DQ55 WR_B_DQ54 WR_B_DQ53 WR_B_DQ52 WR_B_DQ51 WR_B_DQ50 WR_B_DQ49 WR_B_DQ48 WR_B_DQ47 WR_B_DQ46 WR_B_DQ45 WR_B_DQ44 WR_B_DQ43 WR_B_DQ42 WR_B_DQ41 WR_B_DQ40 WR_B_DQ39 WR_B_DQ38 WR_B_DQ37 WR_B_DQ36 WR_B_DQ35 WR_B_DQ34 WR_B_DQ32 WR_B_DQ33 DDR3 Pin # 234 233 228 227 115 114 109 108 225 224 219 218 106 105 100 99 216 215 210 209 97 96 91 90 207 206 201 200 88 87 83 81 TLA Input S_D2:0^1 S_D2:1^1 S_D2:5^1 S_Q1^1 S_D2:2^1 S_D2:3^1 S_D2:7^1 S_D3:0^1 S_D3:2^1 S_D3:3^1 S_D3:7^1 S_D1:5^1 S_D3:1^1 S_D3:4^1 S_D1:7^1 S_D1:6^1 S_D1:4^1 S_D1:1^1 S_D0:7^1 S_D0:6^1 S_D1:3^1 S_D1:2^1 S_D0:5^1 S_D0:4^1 S_D0:3^1 S_D0:2^1 M_C0:1^1 M_C0:4^1 S_D0:1^1 S_D0:0^1 M_C0:6^1 M_C0:7^1 Group Name WrB_DatLo (Hex) Signal Name WR_B_DQ31 WR_B_DQ30 WR_B_DQ29 WR_B_DQ28 WR_B_DQ27 WR_B_DQ26 WR_B_DQ25 WR_B_DQ24 WR_B_DQ23 WR_B_DQ22 WR_B_DQ21 WR_B_DQ20 WR_B_DQ19 WR_B_DQ18 WR_B_DQ17 WR_B_DQ16 WR_B_DQ15 WR_B_DQ14 WR_B_DQ13 WR_B_DQ12 WR_B_DQ11 WR_B_DQ10 WR_B_DQ9 WR_B_DQ8 WR_B_DQ7 WR_B_DQ6 WR_B_DQ5 WR_B_DQ4 WR_B_DQ3 WR_B_DQ2 WR_B_DQ1 WR_B_DQ0 DDR3 Pin # 156 155 150 149 37 36 31 30 147 146 141 140 28 27 22 21 138 137 132 131 19 18 13 12 129 128 123 122 10 9 4 3 TLA Input M_D0:6^1 M_D0:3^1 S_C0:0^1 S_C0:1^1 M_D0:4^1 M_D0:1^1 S_C0:2^1 S_C0:3^1 S_C0:4^1 S_C0:5^1 S_C1:2^1 S_C1:3^1 S_C0:6^1 S_C0:7^1 S_C1:1^1 S_C1:4^1 S_C1:6^1 S_C1:7^1 S_E1:4^1 S_E1:1^1 S_C1:5^1 S_E1:7^1 S_E1:3^1 S_E1:2^1 S_E1:0^1 S_E0:7^1 S_E0:3^1 S_E0:2^1 S_CK2^1 S_E0:5^1 S_E0:1^1 S_E0:0^1 Table 1 – B_DDR3D_2D (<=1066MT/s Read and Write) TLA Channel Grouping (cont’d.) Notes: 1. All signals on this page are required for accurate post-processing of acquired data 2. The ‘S’ in front of a TLA channel denotes the Slave card of the merged pair 3. All signals on this page are stored in the TLA7BB4’s Prime memory and will not have a MagniVu display value DDR3THIN-MN-XXX 22 Doc. Rev. 1.11 Group Name RdAChkBits (OFF) RdBChkBits 4 (OFF) ADatMsks (BIN) Signal Name RD_A_CB7 RD_A_CB6 RD_A_CB5 RD_A_CB4 RD_A_CB3 RD_A_CB2 RD_A_CB1 RD_A_CB0 RD_B_CB7 RD_B_CB6 RD_B_CB5 RD_B_CB4 RD_B_CB3 RD_B_CB2 RD_B_CB1 RD_B_CB0 A_DM7/DQS16 A_DM6/DQS15 A_DM5/DQS14 A_DM4/DQS13 A_DM3/DQS12 A_DM2/DQS11 A_DM1/DQS10 A_DM0/DQS9 DDR3 Pin # 165 164 159 158 46 45 40 39 165 164 159 158 46 45 40 39 230 221 212 203 152 143 134 125 TLA Input M_A1:5 M_A1:4 M_A1:0 M_A0:7 M_A1:6 M_A1:3 M_CK1 M_A0:5 M_A1:5^1 M_A1:4^1 M_A1:0^1 M_A0:7^1 M_A1:6^1 M_A1:3^1 M_CK1^1 M_A0:5^1 S_A2:4 S_A3:6 S_A1:0 M_C2:0 M_A0:2 S_CK3 S_E3:5 S_E2:6 Group Name WrAChkBits 4 (OFF) WrBChkBits 4 (OFF) BDatMsks 4 (BIN) Signal Name WR_A_CB7 WR_A_CB6 WR_A_CB5 WR_A_CB4 WR_A_CB3 WR_A_CB2 WR_A_CB1 WR_A_CB0 WR_B_CB7 WR_B_CB6 WR_B_CB5 WR_B_CB4 WR_B_CB3 WR_B_CB2 WR_B_CB1 WR_B_CB0 B_DM7/DQS16 B_DM6/DQS15 B_DM5/DQS14 B_DM4/DQS13 B_DM3/DQS12 B_DM2/DQS11 B_DM1/DQS10 B_DM0/DQS9 DDR3 Pin # 165 164 159 158 46 45 40 39 165 164 159 158 46 45 40 39 230 221 212 203 152 143 134 125 TLA Input M_D1:5 M_D1:4 M_D1:0 M_D0:7 M_D1:6 M_D1:3 M_Q0 M_D0:5 M_D1:5^1 M_D1:4^1 M_D1:0^1 M_D0:7^1 M_D1:6^1 M_D1:3^1 M_Q0^1 M_D0:5^1 S_A2:4^1 S_A3:6^1 S_A1:0^1 M_C2:0^1 M_A0:2^1 S_CK3^1 S_E3:5^1 S_E2:6^1 Table 1 – B_DDR3D_2D (<=1066MT/s Read and Write) TLA Channel Grouping (cont’d.) Notes: 1. ‘ # ‘ denotes a low-true signal 2. The ‘S’ in front of a TLA channel denotes the Slave card of the merged set 3. The ‘M’ in front of a TLA channel denotes the Master card of the merged pair 4. Signals in these groups are acquired using the TLA’s demux capability and will not have a MagniVu display value DDR3THIN-MN-XXX 23 Doc. Rev. 1.11 Group Name Control 2 (SYM) Strobes (HEX) Unprobed Signal Name CKE1 CKE0 S3# S2# S1# S0# BA2 BA1 BA0 A15 A14 A13 A12/BC# A10/AP RAS# CAS# WE# DQS7 DQS6 DQS5 DQS4 DQS3 DQS2 DQS1 DQS0 All DQSx# DDRCK1+/SA1 SDA SA0 SCL DDR3 Pin # 169 50 49 48 76 193 52 190 71 171 172 196 174 70 192 74 73 111 103 94 85 34 25 16 7 TLA Input M_A3:2 M_A3:1 M_C2:5 M_C3:0 M_C3:4 M_C3:3 M_A3:0 M_C3:7 M_C1:6 M_CK0 M_A2:5 M_CK3 M_A2:4 M_C1:3 M_C3:6 M_C3:5 M_C1:7 S_A2:6 S_A3:5 S_CK1 M_C2:3 M_A0:1 S_C3:0 S_E3:6 S_E2:4 Group Name Address 2 (Hex) Misc 2 (OFF) Ungrouped 63/64 237 238 117 118 Signal Name BA2 BA1 BA0 A15 A14 A13 A12/BC# A11 A10/AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 MISC1 MISC0 DDRCK0+/DQS8 DM8 ERR_OUT#³ RESET# TEST ODT0 ODT1 PAR_IN DDR3 Pin # 52 190 71 171 172 196 174 55 70 175 177 56 178 58 59 180 61 181 188 TLA Input M_A3:0 M_C3:7 M_C1:6 M_CK0 M_A2:5 M_CK3 M_A2:4 M_A2:6 M_C1:3 M_A2:1 M_A2:0 M_A2:3 M_C0:3 M_A2:2 M_C0:5 M_C1:0 M_Q1 M_C1:1 M_C1:5 Placeholder Placeholder 184/185 43 161 53 168 167 195 77 68 M_C1:4 M_A1:2 M_A1:1 M_A2:7 M_A3:6 M_A3:7 M_C2:0 M_C2:1 M_C1:2 Table 1 – B_DDR3D_2D TLA Channel Grouping (cont’d.) Notes: 1. ‘ # ‘ denotes a low-true signal 2. These signals are required for accurate acquisition and post-processing of acquired data 3. The ‘S’ in front of a TLA channel denotes the Slave card of the merged pair 4. The ‘M’ in front of a TLA channel denotes the Master card of the merged pair 5. Signals in these groups are acquired using the TLA’s demux capability and will not have a MagniVu display value DDR3THIN-MN-XXX 24 Doc. Rev. 1.11 Group Name RdA_DatHi (Hex) Signal Name RD_A_DQ63 RD_A_DQ62 RD_A_DQ61 RD_A_DQ60 RD_A_DQ59 RD_A_DQ58 RD_A_DQ57 RD_A_DQ56 RD_A_DQ55 RD_A_DQ54 RD_A_DQ53 RD_A_DQ52 RD_A_DQ51 RD_A_DQ50 RD_A_DQ49 RD_A_DQ48 RD_A_DQ47 RD_A_DQ46 RD_A_DQ45 RD_A_DQ44 RD_A_DQ43 RD_A_DQ42 RD_A_DQ41 RD_A_DQ40 RD_A_DQ39 RD_A_DQ38 RD_A_DQ37 RD_A_DQ36 RD_A_DQ35 RD_A_DQ34 RD_A_DQ33 RD_A_DQ32 DDR3 Pin # 234 233 228 227 115 114 109 108 225 224 219 218 106 105 100 99 216 215 210 209 97 96 91 90 207 206 201 200 88 87 83 81 TLA Input S_A2:0 S_A2:1 S_A2:5 S_CK0 S_A2:2 S_A2:3 S_A2:7 S_A3:0 S_A3:2 S_A3:3 S_A3:7 S_A1:5 S_A3:1 S_A3:4 S_A1:7 S_A1:6 S_A1:4 S_A1:1 S_A0:7 S_A0:6 S_A1:3 S_A1:2 S_A0:5 S_A0:4 S_A0:3 S_A0:2 M_C2:1 M_C2:4 S_A0:1 S_A0:0 M_C2:6 M_C2:7 Group Name RdA_DatLo (Hex) Signal Name RD_A_DQ31 RD_A_DQ30 RD_A_DQ29 RD_A_DQ28 RD_A_DQ27 RD_A_DQ26 RD_A_DQ25 RD_A_DQ24 RD_A_DQ23 RD_A_DQ22 RD_A_DQ21 RD_A_DQ20 RD_A_DQ19 RD_A_DQ18 RD_A_DQ17 RD_A_DQ16 RD_A_DQ15 RD_A_DQ14 RD_A_DQ13 RD_A_DQ12 RD_A_DQ11 RD_A_DQ10 RD_A_DQ9 RD_A_DQ8 RD_A_DQ7 RD_A_DQ6 RD_A_DQ5 RD_A_DQ4 RD_A_DQ3 RD_A_DQ2 RD_A_DQ1 RD_A_DQ0 DDR3 Pin # 156 155 150 149 37 36 31 30 147 146 141 140 28 27 22 21 138 137 132 131 19 18 13 12 129 128 123 122 10 9 4 3 TLA Input M_A0:6 M_A0:3 S_C2:0 S_C2:1 M_A0:4 M_A0:1 S_C2:2 S_C2:3 S_C2:4 S_C2:5 S_C3:2 S_C3:3 S_C2:6 S_C2:7 S_C3:1 S_C3:4 S_C3:6 S_C3:7 S_E3:4 S_E3:1 S_C3:5 S_E3:7 S_E3:3 S_E3:2 S_E3:0 S_E2:7 S_E2:3 S_E2:2 S_Q3 S_E2:5 S_E2:1 S_E2:0 Table 2 - B_DDR3D_2G (<=1066MT/s Read and Write) TLA Channel Grouping Notes: 1. All signals on this page are required for accurate post-processing of acquired data 2. The ‘S’ in front of a TLA channel denotes the Slave card of the merged set DDR3THIN-MN-XXX 25 Doc. Rev. 1.11 Group Name RdB_DatHi (Hex) Signal Name DDR3 Pin# TLA Input RD_B_DQ63 RD_B_DQ62 RD_B_DQ61 RD_B_DQ60 RD_B_DQ59 RD_B_DQ58 RD_B_DQ57 RD_B_DQ56 RD_B_DQ55 RD_B_DQ54 RD_B_DQ53 RD_B_DQ52 RD_B_DQ51 RD_B_DQ50 RD_B_DQ49 RD_B_DQ48 RD_B_DQ47 RD_B_DQ46 RD_B_DQ45 RD_B_DQ44 RD_B_DQ43 RD_B_DQ42 RD_B_DQ41 RD_B_DQ40 RD_B_DQ39 RD_B_DQ38 RD_B_DQ37 RD_B_DQ36 RD_B_DQ35 RD_B_DQ34 RD_B_DQ33 RD_B_DQ32 234 233 228 227 115 114 109 108 225 224 219 218 106 105 100 99 216 215 210 209 97 96 91 90 207 206 201 200 88 87 83 81 S_A2:0^1 S_A2:1^1 S_A2:5^1 S_CK0^1 S_A2:2^1 S_A2:3^1 S_A2:7^1 S_A3:0^1 S_A3:2^1 S_A3:3^1 S_A3:7^1 S_A1:5^1 S_A3:1^1 S_A3:4^1 S_A1:7^1 S_A1:6^1 S_A1:4^1 S_A1:1^1 S_A0:7^1 S_A0:6^1 S_A1:3^1 S_A1:2^1 S_A0:5^1 S_A0:4^1 S_A0:3^1 S_A0:2^1 M_C2:1^1 M_C2:4^1 S_A0:1^1 S_A0:0^1 M_C2:6^1 M_C2:7^1 Group Name RdB_DatLo (Hex) Signal Name DDR3 Pin# TLA Input RD_B_DQ31 RD_B_DQ30 RD_B_DQ29 RD_B_DQ28 RD_B_DQ27 RD_B_DQ26 RD_B_DQ25 RD_B_DQ24 RD_B_DQ23 RD_B_DQ22 RD_B_DQ21 RD_B_DQ20 RD_B_DQ19 RD_B_DQ18 RD_B_DQ17 RD_B_DQ16 RD_B_DQ15 RD_B_DQ14 RD_B_DQ13 RD_B_DQ12 RD_B_DQ11 RD_B_DQ10 RD_B_DQ9 RD_B_DQ8 RD_B_DQ7 RD_B_DQ6 RD_B_DQ5 RD_B_DQ4 RD_B_DQ3 RD_B_DQ2 RD_B_DQ1 RD_B_DQ0 156 155 150 149 37 36 31 30 147 146 141 140 28 27 22 21 138 137 132 131 19 18 13 12 129 128 123 122 10 9 4 3 M_A0:6^1 M_A0:3^1 S_C2:0^1 S_C2:1^1 M_A0:4^1 M_A0:1^1 S_C2:2^1 S_C2:3^1 S_C2:4^1 S_C2:5^1 S_C3:2^1 S_C3:3^1 S_C2:6^1 S_C2:7^1 S_C3:1^1 S_C3:4^1 S_C3:6^1 S_C3:7^1 S_E3:4^1 S_E3:1^1 S_C3:5^1 S_E3:7v S_E3:3^1 S_E3:2^1 S_E3:0^1 S_E2:7^1 S_E2:3^1 S_E2:2^1 S_Q3^1 S_E2:5^1 S_E2:1^1 S_E2:0^1 Table 2 – B_DDR3D_2G (<=1066MT/s Read and Write) TLA Channel Grouping (cont’d.) Notes: 1. All signals on this page are required for accurate post-processing of acquired data 2. The ‘S’ in front of a TLA channel denotes the Slave card of the merged set 3. All signals on this page are acquired using the TLA’s demux capability and will not have a MagniVu display value DDR3THIN-MN-XXX 26 Doc. Rev. 1.11 Group Name WrA_DatHi (Hex) Signal Name WR_A_DQ63 WR_A_DQ62 WR_A_DQ61 WR_A_DQ60 WR_A_DQ59 WR_A_DQ58 WR_A_DQ57 WR_A_DQ56 WR_A_DQ55 WR_A_DQ54 WR_A_DQ53 WR_A_DQ52 WR_A_DQ51 WR_A_DQ50 WR_A_DQ49 WR_A_DQ48 WR_A_DQ47 WR_A_DQ46 WR_A_DQ45 WR_A_DQ44 WR_A_DQ43 WR_A_DQ42 WR_A_DQ41 WR_A_DQ40 WR_A_DQ39 WR_A_DQ38 WR_A_DQ37 WR_A_DQ36 WR_A_DQ35 WR_A_DQ34 WR_A_DQ33 WR_A_DQ32 DDR3 Pin # 234 233 228 227 115 114 109 108 225 224 219 218 106 105 100 99 216 215 210 209 97 96 91 90 207 206 201 200 88 87 83 81 TLA Input S_D2:0 S_D2:1 S_D2:5 S_Q1 S_D2:2 S_D2:3 S_D2:7 S_D3:0 S_D3:2 S_D3:3 S_D3:7 S_D1:5 S_D3:1 S_D3:4 S_D1:7 S_D1:6 S_D1:4 S_D1:1 S_D0:7 S_D0:6 S_D1:3 S_D1:2 S_D0:5 S_D0:4 S_D0:3 S_D0:2 M_C0:1 M_C0:4 S_D0:1 S_D0:0 M_C0:6 M_C0:7 Group Name WrA_DatLo (Hex) Signal Name WR_A_DQ31 WR_A_DQ30 WR_A_DQ29 WR_A_DQ28 WR_A_DQ27 WR_A_DQ26 WR_A_DQ25 WR_A_DQ24 WR_A_DQ23 WR_A_DQ22 WR_A_DQ21 WR_A_DQ20 WR_A_DQ19 WR_A_DQ18 WR_A_DQ17 WR_A_DQ16 WR_A_DQ15 WR_A_DQ14 WR_A_DQ13 WR_A_DQ12 WR_A_DQ11 WR_A_DQ10 WR_A_DQ9 WR_A_DQ8 WR_A_DQ7 WR_A_DQ6 WR_A_DQ5 WR_A_DQ4 WR_A_DQ3 WR_A_DQ2 WR_A_DQ1 WR_A_DQ0 DDR3 Pin # 156 155 150 149 37 36 31 30 147 146 141 140 28 27 22 21 138 137 132 131 19 18 13 12 129 128 123 122 10 9 4 3 TLA Input M_D0:6 M_D0:3 S_C0:0 S_C0:1 M_D0:4 M_D0:1 S_C0:2 S_C0:3 S_C0:4 S_C0:5 S_C1:2 S_C1:3 S_C0:6 S_C0:7 S_C1:1 S_C1:4 S_C1:6 S_C1:7 S_E1:4 S_E1:1 S_C1:5 S_E1:7 S_E1:3 S_E1:2 S_E1:0 S_E0:7 S_E0:3 S_E0:2 S_CK2 S_E0:5 S_E0:1 S_E0:0 Table 2 – B_DDR3D_2G (<=1066MT/s Read and Write) TLA Channel Grouping (cont’d.) Notes: 1. All signals on this page are required for accurate post-processing of acquired data 2. The ‘S’ in front of a TLA channel denotes the Slave card of the merged set DDR3THIN-MN-XXX 27 Doc. Rev. 1.11 Group Name WrB_DatHi (Hex) Signal Name WR_B_DQ63 WR_B_DQ62 WR_B_DQ61 WR_B_DQ60 WR_B_DQ59 WR_B_DQ58 WR_B_DQ57 WR_B_DQ56 WR_B_DQ55 WR_B_DQ54 WR_B_DQ53 WR_B_DQ52 WR_B_DQ51 WR_B_DQ50 WR_B_DQ49 WR_B_DQ48 WR_B_DQ47 WR_B_DQ46 WR_B_DQ45 WR_B_DQ44 WR_B_DQ43 WR_B_DQ42 WR_B_DQ41 WR_B_DQ40 WR_B_DQ39 WR_B_DQ38 WR_B_DQ37 WR_B_DQ36 WR_B_DQ35 WR_B_DQ34 WR_B_DQ32 WR_B_DQ33 DDR3 Pin # 234 233 228 227 115 114 109 108 225 224 219 218 106 105 100 99 216 215 210 209 97 96 91 90 207 206 201 200 88 87 83 81 TLA Input S_D2:0^1 S_D2:1^1 S_D2:5^1 S_Q1^1 S_D2:2^1 S_D2:3^1 S_D2:7^1 S_D3:0^1 S_D3:2^1 S_D3:3^1 S_D3:7^1 S_D1:5^1 S_D3:1^1 S_D3:4^1 S_D1:7^1 S_D1:6^1 S_D1:4^1 S_D1:1^1 S_D0:7^1 S_D0:6^1 S_D1:3^1 S_D1:2^1 S_D0:5^1 S_D0:4^1 S_D0:3^1 S_D0:2v M_C0:1^1 M_C0:4^1 S_D0:1v S_D0:0^1 M_C0:6^1 M_C0:7^1 Group Name WrB_DatLo (Hex) Signal Name WR_B_DQ31 WR_B_DQ30 WR_B_DQ29 WR_B_DQ28 WR_B_DQ27 WR_B_DQ26 WR_B_DQ25 WR_B_DQ24 WR_B_DQ23 WR_B_DQ22 WR_B_DQ21 WR_B_DQ20 WR_B_DQ19 WR_B_DQ18 WR_B_DQ17 WR_B_DQ16 WR_B_DQ15 WR_B_DQ14 WR_B_DQ13 WR_B_DQ12 WR_B_DQ11 WR_B_DQ10 WR_B_DQ9 WR_B_DQ8 WR_B_DQ7 WR_B_DQ6 WR_B_DQ5 WR_B_DQ4 WR_B_DQ3 WR_B_DQ2 WR_B_DQ1 WR_B_DQ0 DDR3 Pin # 156 155 150 149 37 36 31 30 147 146 141 140 28 27 22 21 138 137 132 131 19 18 13 12 129 128 123 122 10 9 4 3 TLA Input M_D0:6^1 M_D0:3^1 S_C0:0^1 S_C0:1^1 M_D0:4^1 M_D0:1^1 S_C0:2^1 S_C0:3^1 S_C0:4^1 S_C0:5^1 S_C1:2^1 S_C1:3^1 S_C0:6^1 S_C0:7^1 S_C1:1^1 S_C1:4^1 S_C1:6^1 S_C1:7^1 S_E1:4^1 S_E1:1^1 S_C1:5^1 S_E1:7^1 S_E1:3^1 S_E1:2^1 S_E1:0^1 S_E0:7^1 S_E0:3^1 S_E0:2^1 S_CK2^1 S_E0:5^1 S_E0:1^1 S_E0:0^1 Table 2 – B_DDR3D_2G (<=1066MT/s Read and Write) TLA Channel Grouping (cont’d.) Notes: 1. All signals on this page are required for accurate post-processing of acquired data 2. The ‘S’ in front of a TLA channel denotes the Slave card of the merged set 3. All signals on this page are stored in the TLA7BB4’s Prime memory and will not have a MagniVu display value DDR3THIN-MN-XXX 28 Doc. Rev. 1.11 Group Name RdAChkBits (OFF) RdBChkBits 4 (OFF) ADatMsks (BIN) Signal Name RD_A_CB7 RD_A_CB6 RD_A_CB5 RD_A_CB4 RD_A_CB3 RD_A_CB2 RD_A_CB1 RD_A_CB0 RD_B_CB7 RD_B_CB6 RD_B_CB5 RD_B_CB4 RD_B_CB3 RD_B_CB2 RD_B_CB1 RD_B_CB0 A_DM7/DQS16 A_DM6/DQS15 A_DM5/DQS14 A_DM4/DQS13 A_DM3/DQS12 A_DM2/DQS11 A_DM1/DQS10 A_DM0/DQS9 DDR3 Pin # 165 164 159 158 46 45 40 39 165 164 159 158 46 45 40 39 230 221 212 203 152 143 134 125 TLA Input M_A1:5 M_A1:4 M_A1:0 M_A0:7 M_A1:6 M_A1:3 M_CK1 M_A0:5 M_A1:5^1 M_A1:4^1 M_A1:0^1 M_A0:7^1 M_A1:6^1 M_A1:3^1 M_CK1^1 M_A0:5^1 S_A2:4 S_A3:6 S_A1:0 M_C2:0 M_A0:2 S_CK3 S_E3:5 S_E2:6 Group Name WrAChkBits 4 (OFF) WrBChkBits 4 (OFF) BDatMsks 4 (BIN) Signal Name WR_A_CB7 WR_A_CB6 WR_A_CB5 WR_A_CB4 WR_A_CB3 WR_A_CB2 WR_A_CB1 WR_A_CB0 WR_B_CB7 WR_B_CB6 WR_B_CB5 WR_B_CB4 WR_B_CB3 WR_B_CB2 WR_B_CB1 WR_B_CB0 B_DM7/DQS16 B_DM6/DQS15 B_DM5/DQS14 B_DM4/DQS13 B_DM3/DQS12 B_DM2/DQS11 B_DM1/DQS10 B_DM0/DQS9 DDR3 Pin # 165 164 159 158 46 45 40 39 165 164 159 158 46 45 40 39 230 221 212 203 152 143 134 125 TLA Input M_D1:5 M_D1:4 M_D1:0 M_D0:7 M_D1:6 M_D1:3 M_Q0 M_D0:5 M_D1:5^1 M_D1:4^1 M_D1:0^1 M_D0:7^1 M_D1:6^1 M_D1:3^1 M_Q0^1 M_D0:5^1 S_A2:4^1 S_A3:6^1 S_A1:0^1 M_C2:0^1 M_A0:2^1 S_CK3^1 S_E3:5^1 S_E2:6^1 Table 2 – B_DDR3D_2G (<=1066MT/s Read and Write) TLA Channel Grouping (cont’d.) Notes: 1. 2. 3. 4. ‘ # ‘ denotes a low-true signal The ‘S’ in front of a TLA channel denotes the Slave card of the merged set The ‘M’ in front of a TLA channel denotes the Master card of the merged set All signals on this page are stored in the TLA7BB4’s Prime memory and will not have a MagniVu display value DDR3THIN-MN-XXX 29 Doc. Rev. 1.11 Group Name Control 2 (SYM) Misc 2 (OFF) Unprobed Signal Name cCKE1 cCKE0 bCLK1 bCLK0 CKE1 CKE0 cS1# cS0# bS1# bS0# S3# S2# S1# S0# BA2 BA1 BA0 A15 A14 A13 A12/BC# A10/AP RAS# CAS# WE# MISC1 MISC0 DDRCK0+/All DQSx# DDRCK1+/SA1 SDA SA0 SCL DDR3 Pin # From Slot C From Slot C From Slot B From Slot B 169 50 From Slot C From Slot C From Slot B From Slot B 49 48 76 193 52 190 71 171 172 196 174 70 192 74 73 Placeholder Placeholder 184/185 TLA Input M_E3:5 M_E3:4 M_Q2 M_E1:7 M_A3:2 M_A3:1 M_E2:6 M_E2:2 M_E0:4 M_E0:0 M_C2:5 M_C3:0 M_C3:4 M_C3:3 M_A3:0 M_C3:7 M_C1:6 M_CK0 M_A2:5 M_CK3 M_A2:4 M_C1:3 M_C3:6 M_C3:5 M_C1:7 M_A3:5 M_A3:4 M_C1:4 Group Name Address 2 (Hex) Strobes (HEX) Ungrouped 63/64 237 238 117 118 Signal Name BA2 BA1 BA0 A15 A14 A13 A12/BC# A11 A10/AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 DQS7 DQS6 DQS5 DQS4 DQS3 DQS2 DQS1 DQS0 DQS8 1_DQS8 DM8 ERR_OUT#³ RESET# TEST ODT0 ODT1 PAR_IN DDR3 Pin # 52 190 71 171 172 196 174 55 70 175 177 56 178 58 59 180 61 181 188 111 103 94 85 34 25 16 7 43 43 161 53 168 167 195 77 68 TLA Input M_A3:0 M_C3:7 M_C1:6 M_CK0 M_A2:5 M_CK3 M_A2:4 M_A2:6 M_C1:3 M_A2:1 M_A2:0 M_A2:3 M_C0:3 M_A2:2 M_C0:5 M_C1:0 M_Q1 M_C1:1 M_C1:5 S_A2:6 S_A3:5 S_CK1 M_C2:3 M_A0:1 S_C3:0 S_E3:6 S_E2:4 M_A1:2 S2_D3:2 M_A1:1 M_A2:7 M_A3:6 M_A3:7 M_C2:0 M_C2:1 M_C1:2 Table 2 – B_DDR3D_2G (<=1066MT/s Read and Write) TLA Channel Grouping (cont’d.) Notes: 1. ‘ # ‘ denotes a low-true signal 2. These signals are required for accurate acquisition and post-processing of acquired data 3. The ‘S’ in front of a TLA channel denotes the Slave card of the merged set 4. The ‘M’ in front of a TLA channel denotes the Master card of the merged set DDR3THIN-MN-XXX 30 Doc. Rev. 1.11 Group Name RdA_DatHi (Hex) Signal Name RD_A_DQ63 RD_A_DQ62 RD_A_DQ61 RD_A_DQ60 RD_A_DQ59 RD_A_DQ58 RD_A_DQ57 RD_A_DQ56 RD_A_DQ55 RD_A_DQ54 RD_A_DQ53 RD_A_DQ52 RD_A_DQ51 RD_A_DQ50 RD_A_DQ49 RD_A_DQ48 RD_A_DQ47 RD_A_DQ46 RD_A_DQ45 RD_A_DQ44 RD_A_DQ43 RD_A_DQ42 RD_A_DQ41 RD_A_DQ40 RD_A_DQ39 RD_A_DQ38 RD_A_DQ37 RD_A_DQ36 RD_A_DQ35 RD_A_DQ34 RD_A_DQ33 RD_A_DQ32 DDR3 Pin # 234 233 228 227 115 114 109 108 225 224 219 218 106 105 100 99 216 215 210 209 97 96 91 90 207 206 201 200 88 87 83 81 TLA Input S_A2:0 S_A2:1 S_A2:5 S_CK0 S_A2:2 S_A2:3 S_A2:7 S_A3:0 S_A3:2 S_A3:3 S_A3:7 S_A1:5 S_A3:1 S_A3:4 S_A1:7 S_A1:6 S_A1:4 S_A1:1 S_A0:7 S_A0:6 S_A1:3 S_A1:2 S_A0:5 S_A0:4 S_A0:3 S_A0:2 M_C2:1 M_C2:4 S_A0:1 S_A0:0 M_C2:6 M_C2:7 Group Name RdA_DatLo (Hex) Signal Name RD_A_DQ31 RD_A_DQ30 RD_A_DQ29 RD_A_DQ28 RD_A_DQ27 RD_A_DQ26 RD_A_DQ25 RD_A_DQ24 RD_A_DQ23 RD_A_DQ22 RD_A_DQ21 RD_A_DQ20 RD_A_DQ19 RD_A_DQ18 RD_A_DQ17 RD_A_DQ16 RD_A_DQ15 RD_A_DQ14 RD_A_DQ13 RD_A_DQ12 RD_A_DQ11 RD_A_DQ10 RD_A_DQ9 RD_A_DQ8 RD_A_DQ7 RD_A_DQ6 RD_A_DQ5 RD_A_DQ4 RD_A_DQ3 RD_A_DQ2 RD_A_DQ1 RD_A_DQ0 DDR3 Pin # 156 155 150 149 37 36 31 30 147 146 141 140 28 27 22 21 138 137 132 131 19 18 13 12 129 128 123 122 10 9 4 3 TLA Input M_A0:6 M_A0:3 S_C2:0 S_C2:1 M_A0:4 M_A0:1 S_C2:2 S_C2:3 S_C2:4 S_C2:5 S_C3:2 S_C3:3 S_C2:6 S_C2:7 S_C3:1 S_C3:4 S_C3:6 S_C3:7 S_E3:4 S_E3:1 S_C3:5 S_E3:7 S_E3:3 S_E3:2 S_E3:0 S_E2:7 S_E2:3 S_E2:2 S_Q3 S_E2:5 S_E2:1 S_E2:0 Table 3 - B_DDR3D_3A (<=1066MT/s Read and Write) TLA Channel Grouping Notes: 1. All signals on this page are required for accurate post-processing of acquired data 2. The ‘M’ in front of a TLA channel denotes the Master card of the merged set 3. The ‘S’ in front of a TLA channel denotes Slave card #1 of the merged set DDR3THIN-MN-XXX 31 Doc. Rev. 1.11 Group Name RdB_DatHi (Hex) Signal Name DDR3 Pin# TLA Input RD_B_DQ63 RD_B_DQ62 RD_B_DQ61 RD_B_DQ60 RD_B_DQ59 RD_B_DQ58 RD_B_DQ57 RD_B_DQ56 RD_B_DQ55 RD_B_DQ54 RD_B_DQ53 RD_B_DQ52 RD_B_DQ51 RD_B_DQ50 RD_B_DQ49 RD_B_DQ48 RD_B_DQ47 RD_B_DQ46 RD_B_DQ45 RD_B_DQ44 RD_B_DQ43 RD_B_DQ42 RD_B_DQ41 RD_B_DQ40 RD_B_DQ39 RD_B_DQ38 RD_B_DQ37 RD_B_DQ36 RD_B_DQ35 RD_B_DQ34 RD_B_DQ33 RD_B_DQ32 234 233 228 227 115 114 109 108 225 224 219 218 106 105 100 99 216 215 210 209 97 96 91 90 207 206 201 200 88 87 83 81 S_A2:0^1 S_A2:1^1 S_A2:5^1 S_CK0^1 S_A2:2^1 S_A2:3^1 S_A2:7^1 S_A3:0^1 S_A3:2^1 S_A3:3^1 S_A3:7^1 S_A1:5^1 S_A3:1^1 S_A3:4^1 S_A1:7^1 S_A1:6^1 S_A1:4^1 S_A1:1^1 S_A0:7^1 S_A0:6^1 S_A1:3^1 S_A1:2^1 S_A0:5^1 S_A0:4^1 S_A0:3^1 S_A0:2^1 M_C2:1^1 M_C2:4^1 S_A0:1^1 S_A0:0^1 M_C2:6^1 M_C2:7^1 Group Name RdB_DatLo (Hex) Signal Name DDR3 Pin# TLA Input RD_B_DQ31 RD_B_DQ30 RD_B_DQ29 RD_B_DQ28 RD_B_DQ27 RD_B_DQ26 RD_B_DQ25 RD_B_DQ24 RD_B_DQ23 RD_B_DQ22 RD_B_DQ21 RD_B_DQ20 RD_B_DQ19 RD_B_DQ18 RD_B_DQ17 RD_B_DQ16 RD_B_DQ15 RD_B_DQ14 RD_B_DQ13 RD_B_DQ12 RD_B_DQ11 RD_B_DQ10 RD_B_DQ9 RD_B_DQ8 RD_B_DQ7 RD_B_DQ6 RD_B_DQ5 RD_B_DQ4 RD_B_DQ3 RD_B_DQ2 RD_B_DQ1 RD_B_DQ0 156 155 150 149 37 36 31 30 147 146 141 140 28 27 22 21 138 137 132 131 19 18 13 12 129 128 123 122 10 9 4 3 M_A0:6^1 M_A0:3^1 S_C2:0^1 S_C2:1^1 M_A0:4^1 M_A0:1^1 S_C2:2^1 S_C2:3^1 S_C2:4^1 S_C2:5^1 S_C3:2^1 S_C3:3^1 S_C2:6^1 S_C2:7^1 S_C3:1^1 S_C3:4^1 S_C3:6^1 S_C3:7^1 S_E3:4^1 S_E3:1^1 S_C3:5^1 S_E3:7^1 S_E3:3^1 S_E3:2^1 S_E3:0^1 S_E2:7^1 S_E2:3^1 S_E2:2^1 S_Q3^1 S_E2:5^1 S_E2:1^1 S_E2:0^1 Table 3 – B_DDR3D_3A (<=1066MT/s Read and Write) TLA Channel Grouping (cont’d.) Notes: 1. All signals on this page are required for accurate post-processing of acquired data 2. The ‘M’ in front of a TLA channel denotes the Master card of the merged set 3. The ‘S’ in front of a TLA channel denotes Slave card #1 of the merged set 4. All signals on this page are stored in the TLA7BB4’s Prime memory and will not have a MagniVu display value DDR3THIN-MN-XXX 32 Doc. Rev. 1.11 Group Name 1_RdA_DatHi (Hex) Signal Name 1_RD_A_DQ63 1_RD_A_DQ62 1_RD_A_DQ61 1_RD_A_DQ60 1_RD_A_DQ59 1_RD_A_DQ58 1_RD_A_DQ57 1_RD_A_DQ56 1_RD_A_DQ55 1_RD_A_DQ54 1_RD_A_DQ53 1_RD_A_DQ52 1_RD_A_DQ51 1_RD_A_DQ50 1_RD_A_DQ49 1_RD_A_DQ48 1_RD_A_DQ47 1_RD_A_DQ46 1_RD_A_DQ45 1_RD_A_DQ44 1_RD_A_DQ43 1_RD_A_DQ42 1_RD_A_DQ41 1_RD_A_DQ40 1_RD_A_DQ39 1_RD_A_DQ38 1_RD_A_DQ37 1_RD_A_DQ36 1_RD_A_DQ35 1_RD_A_DQ34 1_RD_A_DQ33 1_RD_A_DQ32 DDR3 Pin # 234 233 228 227 115 114 109 108 225 224 219 218 106 105 100 99 216 215 210 209 97 96 91 90 207 206 201 200 88 87 83 81 TLA Input S2_A0:0 S2_A0:1 S2_A0:5 S2_CK1 S2_A0:2 S2_A0:3 S2_A0:7 S2_A1:0 S2_A1:2 S2_A1:3 S2_A1:7 S2_D1:5 S2_A1:1 S2_A1:4 S2_D1:7 S2_D1:6 S2_D1:4 S2_D1:1 S2_D0:7 S2_D0:6 S2_D1:3 S2_D1:2 S2_D0:5 S2_D0:4 S2_D0:3 S2_D0:2 S2_C2:1 S2_C2:4 S2_D0:1 S2_D0:0 S2_C2:6 S2_C2:7 Group Name 1_RdA_DatLo (Hex) Signal Name 1_RD_A_DQ31 1_RD_A_DQ30 1_RD_A_DQ29 1_RD_A_DQ28 1_RD_A_DQ27 1_RD_A_DQ26 1_RD_A_DQ25 1_RD_A_DQ24 1_RD_A_DQ23 1_RD_A_DQ22 1_RD_A_DQ21 1_RD_A_DQ20 1_RD_A_DQ19 1_RD_A_DQ18 1_RD_A_DQ17 1_RD_A_DQ16 1_RD_A_DQ15 1_RD_A_DQ14 1_RD_A_DQ13 1_RD_A_DQ12 1_RD_A_DQ11 1_RD_A_DQ10 1_RD_A_DQ9 1_RD_A_DQ8 1_RD_A_DQ7 1_RD_A_DQ6 1_RD_A_DQ5 1_RD_A_DQ4 1_RD_A_DQ3 1_RD_A_DQ2 1_RD_A_DQ1 1_RD_A_DQ0 DDR3 Pin # 156 155 150 149 37 36 31 30 147 146 141 140 28 27 22 21 138 137 132 131 19 18 13 12 129 128 123 122 10 9 4 3 TLA Input S2_D2:6 S2_D2:3 S2_E2:0 S2_E2:1 S2_D2:4 S2_D2:1 S2_E2:2 S2_E2:3 S2_E2:4 S2_E2:5 S2_E3:2 S2_E3:3 S2_E2:6 S2_E2:7 S2_E3:1 S2_E3:4 S2_E3:6 S2_E3:7 S2_E1:4 S2_E1:1 S2_E3:5 S2_E1:7 S2_E1:3 S2_E1:2 S2_E1:0 S2_E0:7 S2_E0:3 S2_E0:2 S2_Q2 S2_E0:5 S2_E0:1 S2_E0:0 Table 3 – B_DDR3D_3A (<=1066MT/s Read and Write) TLA Channel Grouping (cont’d.) Notes: 1. These signals are acquired from the second DIMM slot 2. All signals on this page are required for accurate post-processing of acquired data 3. The ‘S2’ in front of a TLA channel denotes Slave card #2 of the merged set DDR3THIN-MN-XXX 33 Doc. Rev. 1.11 Group Name 1_RdB_DatHi (Hex) Signal Name DDR3 Pin# TLA Input Group Name Signal Name DDR3 Pin# TLA Input 1_RD_B_DQ63 1_RD_B_DQ62 1_RD_B_DQ61 1_RD_B_DQ60 1_RD_B_DQ59 1_RD_B_DQ58 1_RD_B_DQ57 1_RD_B_DQ56 1_RD_B_DQ55 1_RD_B_DQ54 1_RD_B_DQ53 1_RD_B_DQ52 1_RD_B_DQ51 1_RD_B_DQ50 1_RD_B_DQ49 1_RD_B_DQ48 1_RD_B_DQ47 1_RD_B_DQ46 1_RD_B_DQ45 1_RD_B_DQ44 1_RD_B_DQ43 1_RD_B_DQ42 1_RD_B_DQ41 1_RD_B_DQ40 1_RD_B_DQ39 1_RD_B_DQ38 1_RD_B_DQ37 1_RD_B_DQ36 1_RD_B_DQ35 1_RD_B_DQ34 1_RD_B_DQ33 1_RD_B_DQ32 234 233 228 227 115 114 109 108 225 224 219 218 106 105 100 99 216 215 210 209 97 96 91 90 207 206 201 200 88 87 83 81 S2_A0:0^1 S2_A0:1^1 S2_A0:5^1 S2_CK1^1 S2_A0:2^1 S2_A0:3^1 S2_A0:7^1 S2_A1:0^1 S2_A1:2^1 S2_A1:3^1 S2_A1:7^1 S2_D1:5^1 S2_A1:1^1 S2_A1:4^1 S2_D1:7^1 S2_D1:6^1 S2_D1:4^1 S2_D1:1^1 S2_D0:7^1 S2_D0:6^1 S2_D1:3^1 S2_D1:2^1 S2_D0:5^1 S2_D0:4^1 S2_D0:3^1 S2_D0:2^1 S2_C2:1^1 S2_C2:4^1 S2_D0:1^1 S2_D0:0^1 S2_C2:6^1 S2_C2:7^1 1_RdB_DatLo (Hex) 1_RD_B_DQ31 1_RD_B_DQ30 1_RD_B_DQ29 1_RD_B_DQ28 1_RD_B_DQ27 1_RD_B_DQ26 1_RD_B_DQ25 1_RD_B_DQ24 1_RD_B_DQ23 1_RD_B_DQ22 1_RD_B_DQ21 1_RD_B_DQ20 1_RD_B_DQ19 1_RD_B_DQ18 1_RD_B_DQ17 1_RD_B_DQ16 1_RD_B_DQ15 1_RD_B_DQ14 1_RD_B_DQ13 1_RD_B_DQ12 1_RD_B_DQ11 1_RD_B_DQ10 1_RD_B_DQ9 1_RD_B_DQ8 1_RD_B_DQ7 1_RD_B_DQ6 1_RD_B_DQ5 1_RD_B_DQ4 1_RD_B_DQ3 1_RD_B_DQ2 1_RD_B_DQ1 1_RD_B_DQ0 156 155 150 149 37 36 31 30 147 146 141 140 28 27 22 21 138 137 132 131 19 18 13 12 129 128 123 122 10 9 4 3 S2_D2:6^1 S2_D2:3^1 S2_E2:0^1 S2_E2:1^1 S2_D2:4^1 S2_D2:1^1 S2_E2:2^1 S2_E2:3^1 S2_E2:4^1 S2_E2:5^1 S2_E3:2^1 S2_E3:3^1 S2_E2:6^1 S2_E2:7^1 S2_E3:1^1 S2_E3:4^1 S2_E3:6^1 S2_E3:7^1 S2_E1:4^1 S2_E1:1^1 S2_E3:5^1 S2_E1:7^1 S2_E1:3^1 S2_E1:2^1 S2_E1:0^1 S2_E0:7^1 S2_E0:3^1 S2_E0:2^1 S2_Q2^1 S2_E0:5^1 S2_E0:1^1 S2_E0:0^1 Table 3 – B_DDR3D_3A (<=1066MT/s Read and Write) TLA Channel Grouping (cont’d.) Notes: 1. 2. 3. 4. These signals are acquired from the second DIMM slot All signals on this page are required for accurate post-processing of acquired data The ‘S2’ in front of a TLA channel denotes Slave card #2 of the merged set All signals on this page are stored in the TLA7BB4’s Prime memory and will not have a MagniVu display value DDR3THIN-MN-XXX 34 Doc. Rev. 1.11 Group Name WrA_DatHi (Hex) Signal Name WR_A_DQ63 WR_A_DQ62 WR_A_DQ61 WR_A_DQ60 WR_A_DQ59 WR_A_DQ58 WR_A_DQ57 WR_A_DQ56 WR_A_DQ55 WR_A_DQ54 WR_A_DQ53 WR_A_DQ52 WR_A_DQ51 WR_A_DQ50 WR_A_DQ49 WR_A_DQ48 WR_A_DQ47 WR_A_DQ46 WR_A_DQ45 WR_A_DQ44 WR_A_DQ43 WR_A_DQ42 WR_A_DQ41 WR_A_DQ40 WR_A_DQ39 WR_A_DQ38 WR_A_DQ37 WR_A_DQ36 WR_A_DQ35 WR_A_DQ34 WR_A_DQ33 WR_A_DQ32 DDR3 Pin # 234 233 228 227 115 114 109 108 225 224 219 218 106 105 100 99 216 215 210 209 97 96 91 90 207 206 201 200 88 87 83 81 TLA Input S_D2:0 S_D2:1 S_D2:5 S_Q1 S_D2:2 S_D2:3 S_D2:7 S_D3:0 S_D3:2 S_D3:3 S_D3:7 S_D1:5 S_D3:1 S_D3:4 S_D1:7 S_D1:6 S_D1:4 S_D1:1 S_D0:7 S_D0:6 S_D1:3 S_D1:2 S_D0:5 S_D0:4 S_D0:3 S_D0:2 M_C0:1 M_C0:4 S_D0:1 S_D0:0 M_C0:6 M_C0:7 Group Name WrA_DatLo (Hex) Signal Name WR_A_DQ31 WR_A_DQ30 WR_A_DQ29 WR_A_DQ28 WR_A_DQ27 WR_A_DQ26 WR_A_DQ25 WR_A_DQ24 WR_A_DQ23 WR_A_DQ22 WR_A_DQ21 WR_A_DQ20 WR_A_DQ19 WR_A_DQ18 WR_A_DQ17 WR_A_DQ16 WR_A_DQ15 WR_A_DQ14 WR_A_DQ13 WR_A_DQ12 WR_A_DQ11 WR_A_DQ10 WR_A_DQ9 WR_A_DQ8 WR_A_DQ7 WR_A_DQ6 WR_A_DQ5 WR_A_DQ4 WR_A_DQ3 WR_A_DQ2 WR_A_DQ1 WR_A_DQ0 DDR3 Pin # 156 155 150 149 37 36 31 30 147 146 141 140 28 27 22 21 138 137 132 131 19 18 13 12 129 128 123 122 10 9 4 3 TLA Input M_D0:6 M_D0:3 S_C0:0 S_C0:1 M_D0:4 M_D0:1 S_C0:2 S_C0:3 S_C0:4 S_C0:5 S_C1:2 S_C1:3 S_C0:6 S_C0:7 S_C1:1 S_C1:4 S_C1:6 S_C1:7 S_E1:4 S_E1:1 S_C1:5 S_E1:7 S_E1:3 S_E1:2 S_E1:0 S_E0:7 S_E0:3 S_E0:2 S_CK2 S_E0:5 S_E0:1 S_E0:0 Table 3 – B_DDR3D_3A (<=1066MT/s Read and Write) TLA Channel Grouping (cont’d.) Notes: 1. All signals on this page are required for accurate post-processing of acquired data 2. The ‘M’ in front of a TLA channel denotes the Master card of the merged set 3. The ‘S’ in front of a TLA channel denotes Slave card #1 of the merged set DDR3THIN-MN-XXX 35 Doc. Rev. 1.11 Group Name WrB_DatHi (Hex) Signal Name WR_B_DQ63 WR_B_DQ62 WR_B_DQ61 WR_B_DQ60 WR_B_DQ59 WR_B_DQ58 WR_B_DQ57 WR_B_DQ56 WR_B_DQ55 WR_B_DQ54 WR_B_DQ53 WR_B_DQ52 WR_B_DQ51 WR_B_DQ50 WR_B_DQ49 WR_B_DQ48 WR_B_DQ47 WR_B_DQ46 WR_B_DQ45 WR_B_DQ44 WR_B_DQ43 WR_B_DQ42 WR_B_DQ41 WR_B_DQ40 WR_B_DQ39 WR_B_DQ38 WR_B_DQ37 WR_B_DQ36 WR_B_DQ35 WR_B_DQ34 WR_B_DQ32 WR_B_DQ33 DDR3 Pin # 234 233 228 227 115 114 109 108 225 224 219 218 106 105 100 99 216 215 210 209 97 96 91 90 207 206 201 200 88 87 83 81 TLA Input S_D2:0^1 S_D2:1^1 S_D2:5^1 S_Q1^1 S_D2:2^1 S_D2:3^1 S_D2:7^1 S_D3:0^1 S_D3:2^1 S_D3:3^1 S_D3:7^1 S_D1:5^1 S_D3:1^1 S_D3:4^1 S_D1:7^1 S_D1:6^1 S_D1:4^1 S_D1:1^1 S_D0:7^1 S_D0:6^1 S_D1:3^1 S_D1:2^1 S_D0:5^1 S_D0:4^1 S_D0:3^1 S_D0:2^1 M_C0:1^1 M_C0:4^1 S_D0:1^1 S_D0:0^1 M_C0:6^1 M_C0:7^1 Group Name WrB_DatLo (Hex) Signal Name WR_B_DQ31 WR_B_DQ30 WR_B_DQ29 WR_B_DQ28 WR_B_DQ27 WR_B_DQ26 WR_B_DQ25 WR_B_DQ24 WR_B_DQ23 WR_B_DQ22 WR_B_DQ21 WR_B_DQ20 WR_B_DQ19 WR_B_DQ18 WR_B_DQ17 WR_B_DQ16 WR_B_DQ15 WR_B_DQ14 WR_B_DQ13 WR_B_DQ12 WR_B_DQ11 WR_B_DQ10 WR_B_DQ9 WR_B_DQ8 WR_B_DQ7 WR_B_DQ6 WR_B_DQ5 WR_B_DQ4 WR_B_DQ3 WR_B_DQ2 WR_B_DQ1 WR_B_DQ0 DDR3 Pin # 156 155 150 149 37 36 31 30 147 146 141 140 28 27 22 21 138 137 132 131 19 18 13 12 129 128 123 122 10 9 4 3 TLA Input M_D0:6^1 M_D0:3^1 S_C0:0^1 S_C0:1^1 M_D0:4^1 M_D0:1^1 S_C0:2^1 S_C0:3^1 S_C0:4^1 S_C0:5^1 S_C1:2^1 S_C1:3^1 S_C0:6^1 S_C0:7^1 S_C1:1v S_C1:4^1 S_C1:6^1 S_C1:7^1 S_E1:4^1 S_E1:1v S_C1:5^1 S_E1:7^1 S_E1:3^1 S_E1:2^1 S_E1:0^1 S_E0:7^1 S_E0:3^1 S_E0:2^1 S_CK2^1 S_E0:5^1 S_E0:1^1 S_E0:0^1 Table 3 – B_DDR3D_3A (<=1066MT/s Read and Write) TLA Channel Grouping (cont’d.) Notes: 1. All signals on this page are required for accurate post-processing of acquired data 2. The ‘M’ in front of a TLA channel denotes the Master card of the merged set 3. The ‘S’ in front of a TLA channel denotes Slave card #1 of the merged set 4. All signals on this page are stored in the TLA7BB4’s Prime memory and will not have a MagniVu display value DDR3THIN-MN-XXX 36 Doc. Rev. 1.11 Group Name RdAChkBits (OFF) RdBChkBits 4 (OFF) 1_RdAChkBits (OFF) ADatMsks (BIN) Signal Name RD_A_CB7 RD_A_CB6 RD_A_CB5 RD_A_CB4 RD_A_CB3 RD_A_CB2 RD_A_CB1 RD_A_CB0 RD_B_CB7 RD_B_CB6 RD_B_CB5 RD_B_CB4 RD_B_CB3 RD_B_CB2 RD_B_CB1 RD_B_CB0 1_RD_A_CB7 1_RD_A_CB6 1_RD_A_CB5 1_RD_A_CB4 1_RD_A_CB3 1_RD_A_CB2 1_RD_A_CB1 1_RD_A_CB0 A_DM7/DQS16 A_DM6/DQS15 A_DM5/DQS14 A_DM4/DQS13 A_DM3/DQS12 A_DM2/DQS11 A_DM1/DQS10 A_DM0/DQS9 DDR3 Pin # 165 164 159 158 46 45 40 39 165 164 159 158 46 45 40 39 165 164 159 158 46 45 40 39 230 221 212 203 152 143 134 125 TLA Input M_A1:5 M_A1:4 M_A1:0 M_A0:7 M_A1:6 M_A1:3 M_CK1 M_A0:5 M_A1:5^1 M_A1:4^1 M_A1:0^1 M_A0:7^1 M_A1:6^1 M_A1:3^1 M_CK1^1 M_A0:5^1 S2_D3:5 S2_D3:4 S2_D3:0 S2_D2:7 S2_D3:6 S2_D3:3 S2_Q0 S2_D2:5 S_A2:4 S_A3:6 S_A1:0 M_C2:0 M_A0:2 S_CK3 S_E3:5 S_E2:6 Group Name WrAChkBits 4 (OFF) WrBChkBits 4 (OFF) 1_RdBChkBits 4 (OFF) BDatMsks 4 (BIN) Signal Name WR_A_CB7 WR_A_CB6 WR_A_CB5 WR_A_CB4 WR_A_CB3 WR_A_CB2 WR_A_CB1 WR_A_CB0 WR_B_CB7 WR_B_CB6 WR_B_CB5 WR_B_CB4 WR_B_CB3 WR_B_CB2 WR_B_CB1 WR_B_CB0 1_RD_B_CB7 1_RD_B_CB6 1_RD_B_CB5 1_RD_B_CB4 1_RD_B_CB3 1_RD_B_CB2 1_RD_B_CB1 1_RD_B_CB0 B_DM7/DQS16 B_DM6/DQS15 B_DM5/DQS14 B_DM4/DQS13 B_DM3/DQS12 B_DM2/DQS11 B_DM1/DQS10 B_DM0/DQS9 DDR3 Pin # 165 164 159 158 46 45 40 39 165 164 159 158 46 45 40 39 165 164 159 158 46 45 40 39 230 221 212 203 152 143 134 125 TLA Input M_D1:5 M_D1:4 M_D1:0 M_D0:7 M_D1:6 M_D1:3 M_Q0 M_D0:5 M_D1:5^1 M_D1:4^1 M_D1:0^1 M_D0:7^1 M_D1:6^1 M_D1:3^1 M_Q0^1 M_D0:5^1 S2_D3:5^1 S2_D3:4^1 S2_D3:0^1 S2_D2:7^1 S2_D3:6^1 S2_D3:3^1 S2_Q0^1 S2_D2:5^1 S_A2:4^1 S_A3:6^1 S_A1:0^1 M_C2:0^1 M_A0:2^1 S_CK3^1 S_E3:5^1 S_E2:6^1 Table 3 – B_DDR3D_3A (<=1066MT/s Read and Write) TLA Channel Grouping (cont’d.) Notes: 1. ‘ # ‘ denotes a low-true signal 2. The ‘M’ in front of a TLA channel denotes the Master card of the merged set 3. The ‘S’ in front of a TLA channel denotes Slave card #1 of the merged set 4. The ‘S2’ in front of a TLA channel denotes Slave card #2 of the merged set 5. Signals in these groups are acquired using the TLA’s demux capability and will not have a MagniVu display value DDR3THIN-MN-XXX 37 Doc. Rev. 1.11 Group Name Control 2 (SYM) Strobes (HEX) Unprobed Signal Name CKE1 CKE0 S3# S2# S1# S0# BA2 BA1 BA0 A15 A14 A13 A12/BC# A10/AP RAS# CAS# WE# DQS7 DQS6 DQS5 DQS4 DQS3 DQS2 DQS1 DQS0 All DQSx# DDRCK1+/SA1 SDA SA0 SCL DDR3 Pin # 169 50 49 48 76 193 52 190 71 171 172 196 174 70 192 74 73 111 103 94 85 34 25 16 7 TLA Input M_A3:2 M_A3:1 S2_C2:5 S2_C3:0 M_C3:4 M_C3:3 M_A3:0 M_C3:7 M_C1:6 M_CK0 M_A2:5 M_CK3 M_A2:4 M_C1:3 M_C3:6 M_C3:5 M_C1:7 S_A2:6 S_A3:5 S_CK1 M_C2:3 M_A0:1 S_C3:0 S_E3:6 S_E2:4 Group Name Address 2 (Hex) Misc 2 (OFF) Ungrouped 63/64 237 238 117 118 Signal Name BA2 BA1 BA0 A15 A14 A13 A12/BC# A11 A10/AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 MISC1 MISC0 DDRCK0+/DQS8 DM8 ERR_OUT#³ RESET# TEST ODT0 ODT1 PAR_IN DDR3 Pin # 52 190 71 171 172 196 174 55 70 175 177 56 178 58 59 180 61 181 188 Placeholder Placeholder 184/185 43 161 53 168 167 195 77 68 TLA Input M_A3:0 M_C3:7 M_C1:6 M_CK0 M_A2:5 M_CK3 M_A2:4 M_A2:6 M_C1:3 M_A2:1 M_A2:0 M_A2:3 M_C0:3 M_A2:2 M_C0:5 M_C1:0 M_Q1 M_C1:1 M_C1:5 M_A3:5 M_A3:4 M_C1:4 M_A1:2 M_A1:1 M_A2:7 M_A3:6 M_A3:7 M_C2:0 M_C2:1 M_C1:2 Table 3 – B_DDR3D_3A TLA Channel Grouping (cont’d.) Notes: 1. ‘ # ‘ denotes a low-true signal 2. These signals are required for accurate acquisition and post-processing of acquired data 3. The ‘M’ in front of a TLA channel denotes the Master card of the merged set 4. The ‘S’ in front of a TLA channel denotes Slave card #1 of the merged set 5. The ‘S2’ in front of a TLA channel denotes Slave card #2 of the merged set 6. Signals in these groups are acquired using the TLA’s demux capability and will not have a MagniVu display value DDR3THIN-MN-XXX 38 Doc. Rev. 1.11 3.7 Display Groups not in Tables 1,2 or 3 There are several groups in the List window that are not documented in the tables as these groups are used only by the post-processing display software. To ensure correct data display these groups must not be modified. These groups are: • • • • • • DataHi DataLo ChekBits Command DataMasks MRSAddr DDR3THIN-MN-XXX 39 Doc. Rev. 1.11 4.0 CLOCK SELECTION 4.1 B_DDR3D_2D Clocking Selections There are two clocking option fields available when using the B_DDR3D_2D support package. These select fields permit the user to setup the TLA acquisition as follows: SDRAM Clocking: – Permits selecting the Clocking Mode to be used to acquire DDR3 data. It is important to note that the selection chosen will force unused Chip Selects and CKE1 into inactive states. The field choices are: S0#; Every Rising Edge (default) – Clocks data using every rising edge of DDR Clock 0. Forces CKE1 low and S1-3# high. No Idle Cycle filtering is done. S0# & S1#; Every Rising Edge – Clocks data using every rising edge of DDR Clock 0. Forces S2-3# high. No Idle Cycle filtering is done. S0-3#; Every Rising Edge – Clocks data using every rising edge of DDR Clock 0. No Idle Cycle filtering is done. S0#; Total L <=5 – utilizes Selective Clocking to reduce acquisition of Idle bus states. Forces CKE1 low and S1-3# high. S0# & S1#; Total L <=5 - utilizes Selective Clocking to reduce acquisition of Idle bus states. Forces S2-3# high. S0-3#; Total L <=5 - utilizes Selective Clocking to reduce acquisition of Idle bus states. S0#; Total L <=6 S0# & S1#; Total L <=6 S0-3#; Total L <=6 . . . S0#; Total L <=25 S0# & S1#; Total L <=25 S0-3#; Total L <=25 The above selections reduce the number of Idle cycles stored by the acquisition card to provide optimum use of the acquisition memory. Data is stored whenever RAS# or CAS# is asserted low along with a valid Chip Select. After every assertion of CAS# (paired with a valid Chip Select) samples are taken during the next X DDR Clock cycles to ensure that all valid memory cycles have been acquired. The acquisition then pauses and waits for the next Command. If CAS# and a Chip Select are asserted during these X clock cycles the count is reset. The X-clock cycle value is determined by adding the maximum Burst Length of 8 clock cycles to the selected maximum Read Latency. So for a selected Total DDR3THIN-MN-XXX 40 Doc. Rev. 1.11 Latency of <= 5 cycles the support software will store a total of 13 clock cycles worth of data after the Read or Write Command appears on the bus. Refresh Cycles: – Permits choosing whether Refresh Cycles will be stored or not. The field choices are: Acquire (default) – Refresh Cycles will be stored. Do Not Acquire – This mode will reduce the number of Refresh cycles stored by the acquisition card to provide optimum use of the acquisition memory. NOTE: This mode is disabled when the SDRAM Clocking choice is set to a Every Rising Edge selection. 4.2 B_DDR3D_2G Clocking Selections There is one clocking option field available when using the B_DDR3D_2G support package. These select fields permit the user to setup the TLA acquisition as follows: Active Chip Selects: – Permits selecting which of 8 possible Chip Selects are active on the target. The rising edge of the DDR Clock is always used to acquire data. How the display software interprets which Chip Selects are active will be based on this field setting. With 8 possible Chip Selects and 6 Clock Enable signals it is possible to support data acquisition from a 3 slot channel at 800. See section 3.6 for channel configuration. This support only allows one quad rank support in slot A (the interposer slot), or most combinations of single and dual rank DIMMs in the three slots. The “B” slot is the DIMM slot between the Interposer and the memory controller. The “C” slot is the slot nearest the memory controller in a three slot system. The field choices shown correspond to the Chip Select number defined in the channel map, and are as follows: Chip Select(s) Equivalent Memory DIMM configuration C:____B:____A:___0 0r0r1r (default) – Only S0# in the Interposer slot is active; all other Chip Selects will be forced inactive (high) by the support package. Equivalent to one Single Rank DIMM. C:____B:____A:__10 0r0r2r – S0# and S1# in the Interposer slot are active, equivalent to a Dual Rank DIMM. C:____B:____A:3210 0r0r4r – S0#, S1#, S2# and S3# in the Interposer slot are active, equivalent to a Quad Rank DIMM. DDR3THIN-MN-XXX 41 Doc. Rev. 1.11 C:____B:_0__A:___0 0r1r1r – bS0# in the slot between the Interposer and the memory controller and S0# in the Interposer slot are active, equivalent to two Single Rank DIMMs. C:____B:_0__A:__10 0r1r2r – bS0#, S0# and S1# are active, equivalent to one Single Rank DIMM and one Dual Rank DIMM. C:____B:10__A:___0 0r2r1r – bS1#, bS0# and S0# are active, equivalent to a Dual Rank DIMM and a Single Rank DIMM. C:____B:10__A:__10 0r2r2r – bS1#, bS0#, S1# and S0# are active, equivalent to two Dual Rank DIMMs. C:_0__B:_0__A:___0 1r1r1r – cS0# is the slot nearest the memory control if three slot channel, bS0# is the slot in the middle of a three slot channel and S0# in the Interposer slot are active, equivalent to three Single Rank DIMMs. C:_0__B:_0__A:__10 1r1r2r – cS0#, bS0#, S0# and S1# are active, equivalent to two Single Rank DIMMs and one Dual Rank DIMM. C:_0__B:10__A:___0 1r2r1r – cS0#, bS1#, bS0# and S0# are active, equivalent to a Dual Rank DIMM and two Single Rank DIMMs. C:_0__B:10__A:__10 1r2r2r – cS0#, bS1#, bS0#, S1# and S0# are active, equivalent to a Single Rank DIMM, and two Dual Rank DIMMs. C:10__B:_0__A:___0 2r1r1r – cS1#, cS0#, bS0# and S0# are active, equivalent to two Single Rank DIMMs, and a dual rank DIMM. C:10__B:_0__A:__10 2r1r2r – cS1#, cS0#, bS0#, S0# and S1# are active, equivalent to one Single Rank DIMM and two Dual Rank DIMMs. C:10__B:10__A:___0 2r2r1r – cS1#, cS0#, bS1#, bS0# and S0# are active, equivalent to two Dual Rank DIMM and a Single Rank DIMM. C:10__B:10__A:__10 2r2r2r – cS1#, cS0#, bS1#, bS0#, S1# and S0# are active, equivalent to three Dual Rank DIMMs. DDR3THIN-MN-XXX 42 Doc. Rev. 1.11 4.3 B_DDR3D_3A Clocking Selections There is one clocking option field available when using the B_DDR3D_3A support package. This select field sets up the TLA acquisition as follows: SDRAM DDR CLK0 Clocking: – Permits selecting the Clocking Mode to be used to acquire DDR3 data. Only one choice is available: Every Rising Edge – As the name implies this will cause the acquisition card to acquire data on every Rising edge of the DDR Clock 0. DDR3THIN-MN-XXX 43 Doc. Rev. 1.11 5.0 CONFIGURING FOR READ / WRITE DATA ACQUISITION Prior to configuring your NEX-DDR3INTR-THIN support package it is strongly recommended that Appendix A (“How DDR Data is Clocked”), section 5.4 (“Selecting DDR Read Sample Points”) and section 5.5. (“Selecting DDR Write Sample Points”) be read. This background information is very helpful and facilitates proper support configuration. 5.1 A Note About the Different Data Groups The NEX-DDR3INTR-THIN support software have three different areas where signal groups are defined to provide specific functionality. There are the MagniVu data groups (see Table 4) are the groups that contain raw MagniVu data. Storage data groups (see Tables 1, 2 and 3) can be seen in the acquisition card Setup window and contain the data stored in Main Memory which is used for the Listing display. Capture data groups (not defined in this manual) are the groups seen in the TLA’s Setup & Hold dialog box and are the groups used to capture data during each DDR clock cycle. The MagniVu and Capture data groups will be referred to in the following explanation on determining and setting the correct sample points to acquire Read and Write data. Please contact your local Tektronix representative for a detailed explanation of the different data group areas and what they mean. 5.2 MagniVu Signals Because of the design of the Tektronix TLA7BB4 acquisition cards different data groups need to be defined for use within MagniVu. Table 4 shows the MagniVu group definitions present in the B_DDR3D_2D/_2G supports. Table 5 shows the MagniVu group definitions present in the B_DDR3D_3A support. DDR3THIN-MN-XXX 44 Doc. Rev. 1.11 Group Name Data_H i Signal Name DQ63 TLA Input S_A2:0 DQ62 DQ61 DQ60 DQ59 DQ58 DQ57 DQ56 DQ55 DQ54 DQ53 DQ52 DQ51 DQ50 DQ49 DQ48 DQ47 DQ46 DQ45 DQ44 DQ43 DQ42 DQ41 DQ40 DQ39 DQ38 DQ37 DQ36 DQ35 DQ34 DQ33 DQ32 S_A2:1 S_A2:5 S_CK0 S_A2:2 S_A2:3 S_A2:7 S_A3:0 S_A3:2 S_A3:3 S_A3:7 S_A1:5 S_A3:1 S_A3:4 S_A1:7 S_A1:6 S_A1:4 S_A1:1 S_A0:7 S_A0:6 S_A1:3 S_A1:2 S_A0:5 S_A0:4 S_A0:3 S_A0:2 M_C2:1 M_C2:4 S_A0:1 S_A0:0 M_C2:6 M_C2:7 Group Name Data_L o Signal Name DQ31 TLA Input M_A0:6 DQ30 DQ29 DQ28 DQ27 DQ26 DQ25 DQ24 DQ23 DQ22 DQ21 DQ20 DQ19 DQ18 DQ17 DQ16 DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 M_A0:3 S_C2:0 S_C2:1 M_A0:4 M_A0:1 S_C2:2 S_C2:3 S_C2:4 S_C2:5 S_C3:2 S_C3:3 S_C2:6 S_C2:7 S_C3:1 S_C3:4 S_C3:6 S_C3:7 S_E3:4 S_E3:1 S_C3:5 S_E3:7 S_E3:3 S_E3:2 S_E3:0 S_E2:7 S_E2:3 S_E2:2 S_Q3 S_E2:5 S_E2:1 S_E2:0 Table 4 - B_DDR3D_2D/_2G TLA MagniVu Channel Grouping Notes: 1. The ‘S’ in front of a TLA channel denotes the Slave card of the merged pair 2. The ‘M’ in front of a TLA channel denotes the Master card of the merged pair DDR3THIN-MN-XXX 45 Doc. Rev. 1.11 Group Name DataByte 7 DataByte 6 DataByte 5 DataByte 4 Signal Name DQ63 TLA Input S_A2:0 DQ62 DQ61 DQ60 DQ59 DQ58 DQ57 DQ56 DQ55 S_A2:1 S_A2:5 S_CK0 S_A2:2 S_A2:3 S_A2:7 S_A3:0 S_A3:2 DQ54 DQ53 DQ52 DQ51 DQ50 DQ49 DQ48 DQ47 S_A3:3 S_A3:7 S_A1:5 S_A3:1 S_A3:4 S_A1:7 S_A1:6 S_A1:4 DQ46 DQ45 DQ44 DQ43 DQ42 DQ41 DQ40 DQ39 S_A1:1 S_A0:7 S_A0:6 S_A1:3 S_A1:2 S_A0:5 S_A0:4 S_A0:3 DQ38 DQ37 DQ36 DQ35 DQ34 DQ33 DQ32 S_A0:2 M_C2:1 M_C2:4 S_A0:1 S_A0:0 M_C2:6 M_C2:7 Group Name DataByte 3 DataByte 2 DataByte 1 DataByte 0 Signal Name DQ31 TLA Input M_A0:6 DQ30 DQ29 DQ28 DQ27 DQ26 DQ25 DQ24 DQ23 M_A0:3 S_C2:0 S_C2:1 M_A0:4 M_A0:1 S_C2:2 S_C2:3 S_C2:4 DQ22 DQ21 DQ20 DQ19 DQ18 DQ17 DQ16 DQ15 S_C2:5 S_C3:2 S_C3:3 S_C2:6 S_C2:7 S_C3:1 S_C3:4 S_C3:6 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 S_C3:7 S_E3:4 S_E3:1 S_C3:5 S_E3:7 S_E3:3 S_E3:2 S_E3:0 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 S_E2:7 S_E2:3 S_E2:2 S_Q3 S_E2:5 S_E2:1 S_E2:0 Table 4 – B_DDR3D_2D/_2G TLA MagniVu Channel Grouping (cont’d.) Notes: 1. The ‘S’ in front of a TLA channel denotes the Slave card of the merged pair 2. The ‘M’ in front of a TLA channel denotes the Master card of the merged pair DDR3THIN-MN-XXX 46 Doc. Rev. 1.11 Group Name CheckBit s Strobes 2 Control 2 Signal Name CB7 TLA Input M_A1:5 CB6 CB5 CB4 CB3 CB2 CB1 CB0 DQS8 DQS7 DQS6 DQS5 DQS4 DQS3 DQS2 DQS1 DQS0 CKE1 CKE0 S3# S2# S1# S0# BA2 BA1 BA0 A15 A14 A13 A12/BC# A10/AP RAS# CAS# WE# M_A1:4 M_A1:0 M_A0:7 M_A1:6 M_A1:3 M_CK1 M_A0:5 M_A1:2 S_A2:6 S_A3:5 S_CK1 M_C2:3 M_A0:0 S_C3:0 S_E3:6 S_E2:4 M_A3:2 M_A3:1 M_C2:5 M_C3:0 M_C3:4 M_C3:3 M_A3:0 M_C3:7 M_C1:6 M_CK0 M_A2:5 M_CK3 M_A2:4 M_C1:3 M_C3:6 M_C3:5 M_C1:7 Group Name DataMasks Address 2 Orphans Misc 2,5 Signal Name DM7 TLA Input S_A2:4 DM6 DM5 DM4 DM3 DM2 DM1 DM0 BA2 BA1 BA0 A15 A14 A13 A12/BC# A11 A10/AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 PAR_IN ERR_OUT# TEST RESET# ODT1 ODT0 MISC1 MISC0 DDRCK0 S_A3:6 S_A1:0 M_C2:0 M_A0:2 S_CK3 S_E3:5 S_E2:6 M_A3:0 M_C3:7 M_C1:6 M_CK0 M_A2:5 M_CK3 M_A2:4 M_A2:6 M_C1:3 M_A2:1 M_A2:0 M_A2:3 M_C0:2 M_A2:2 M_C0:5 M_C1:0 M_Q1 M_C1:1 M_C1:5 M_C1:2 M_A2:7 M_A3:7 M_A3:6 M_C3:1 M_C3:2 M_A3:5 M_A3:4 M_C1:4 Table 4 – B_DDR3D_2D/_2G (<=1333MT/s Read and Write) TLA Channel Grouping (cont’d.) Notes: 1. ‘ # ‘ denotes a low-true signal 2. These signals are required for accurate acquisition and post-processing of acquired data 3. The ‘S’ in front of a TLA channel denotes the Slave card of the merged pair 4. The ‘M’ in front of a TLA channel denotes the Master card of the merged pair 5. MISC1 and MISC0 are placeholders only and will not have interesting data on them DDR3THIN-MN-XXX 47 Doc. Rev. 1.11 Group Name Data_H i Signal Name DQ63 TLA Input S_A2:0 DQ62 DQ61 DQ60 DQ59 DQ58 DQ57 DQ56 DQ55 DQ54 DQ53 DQ52 DQ51 DQ50 DQ49 DQ48 DQ47 DQ46 DQ45 DQ44 DQ43 DQ42 DQ41 DQ40 DQ39 DQ38 DQ37 DQ36 DQ35 DQ34 DQ33 DQ32 S_A2:1 S_A2:5 S_CK0 S_A2:2 S_A2:3 S_A2:7 S_A3:0 S_A3:2 S_A3:3 S_A3:7 S_A1:5 S_A3:1 S_A3:4 S_A1:7 S_A1:6 S_A1:4 S_A1:1 S_A0:7 S_A0:6 S_A1:3 S_A1:2 S_A0:5 S_A0:4 S_A0:3 S_A0:2 M_C2:1 M_C2:4 S_A0:1 S_A0:0 M_C2:6 M_C2:7 Group Name Data_L o Signal Name DQ31 TLA Input M_A0:6 DQ30 DQ29 DQ28 DQ27 DQ26 DQ25 DQ24 DQ23 DQ22 DQ21 DQ20 DQ19 DQ18 DQ17 DQ16 DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 M_A0:3 S_C2:0 S_C2:1 M_A0:4 M_A0:1 S_C2:2 S_C2:3 S_C2:4 S_C2:5 S_C3:2 S_C3:3 S_C2:6 S_C2:7 S_C3:1 S_C3:4 S_C3:6 S_C3:7 S_E3:4 S_E3:1 S_C3:5 S_E3:7 S_E3:3 S_E3:2 S_E3:0 S_E2:7 S_E2:3 S_E2:2 S_Q3 S_E2:5 S_E2:1 S_E2:0 Table 5 - B_DDR3D_3A TLA MagniVu Channel Grouping Notes: 1. The ‘S’ in front of a TLA channel denotes the Slave card of the merged pair 2. The ‘M’ in front of a TLA channel denotes the Master card of the merged pair DDR3THIN-MN-XXX 48 Doc. Rev. 1.11 Group Name DataByte 7 DataByte 6 DataByte 5 DataByte 4 Signal Name DQ63 TLA Input S_A2:0 DQ62 DQ61 DQ60 DQ59 DQ58 DQ57 DQ56 DQ55 S_A2:1 S_A2:5 S_CK0 S_A2:2 S_A2:3 S_A2:7 S_A3:0 S_A3:2 DQ54 DQ53 DQ52 DQ51 DQ50 DQ49 DQ48 DQ47 S_A3:3 S_A3:7 S_A1:5 S_A3:1 S_A3:4 S_A1:7 S_A1:6 S_A1:4 DQ46 DQ45 DQ44 DQ43 DQ42 DQ41 DQ40 DQ39 S_A1:1 S_A0:7 S_A0:6 S_A1:3 S_A1:2 S_A0:5 S_A0:4 S_A0:3 DQ38 DQ37 DQ36 DQ35 DQ34 DQ33 DQ32 S_A0:2 M_C2:1 M_C2:4 S_A0:1 S_A0:0 M_C2:6 M_C2:7 Group Name DataByte 3 DataByte 2 DataByte 1 DataByte 0 Signal Name DQ31 TLA Input M_A0:6 DQ30 DQ29 DQ28 DQ27 DQ26 DQ25 DQ24 DQ23 M_A0:3 S_C2:0 S_C2:1 M_A0:4 M_A0:1 S_C2:2 S_C2:3 S_C2:4 DQ22 DQ21 DQ20 DQ19 DQ18 DQ17 DQ16 DQ15 S_C2:5 S_C3:2 S_C3:3 S_C2:6 S_C2:7 S_C3:1 S_C3:4 S_C3:6 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 S_C3:7 S_E3:4 S_E3:1 S_C3:5 S_E3:7 S_E3:3 S_E3:2 S_E3:0 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 S_E2:7 S_E2:3 S_E2:2 S_Q3 S_E2:5 S_E2:1 S_E2:0 Table 5 – B_DDR3D_3A TLA MagniVu Channel Grouping (cont’d.) Notes: 1. The ‘S’ in front of a TLA channel denotes the Slave card of the merged pair 2. The ‘M’ in front of a TLA channel denotes the Master card of the merged pair DDR3THIN-MN-XXX 49 Doc. Rev. 1.11 Group Name Data_Hi_1 Signal Name 1_DQ63 TLA Input S2_A0:0 1_DQ62 1_DQ61 1_DQ60 1_DQ59 1_DQ58 1_DQ57 1_DQ56 1_DQ55 1_DQ54 1_DQ53 1_DQ52 1_DQ51 1_DQ50 1_DQ49 1_DQ48 1_DQ47 1_DQ46 1_DQ45 1_DQ44 1_DQ43 1_DQ42 1_DQ41 1_DQ40 1_DQ39 1_DQ38 1_DQ37 1_DQ36 1_DQ35 1_DQ34 1_DQ33 1_DQ32 S2_A0:1 S2_A0:5 S2_CK1 S2_A0:2 S2_A0:3 S2_A0:7 S2_A1:0 S2_A1:2 S2_A1:3 S2_A1:7 S2_D1:5 S2_A1:1 S2_A1:4 S2_D1:7 S2_D1:6 S2_D1:4 S2_D1:1 S2_D0:7 S2_D0:6 S2_D1:3 S2_D1:2 S2_D0:5 S2_D0:4 S2_D0:3 S2_D0:2 S2_C2:1 S2_C2:4 S2_D0:1 S2_D0:0 S2_C2:6 S2_C2:7 Group Name Data_Lo_ 1 Signal Name 1_DQ31 TLA Input S2_D2:6 1_DQ30 1_DQ29 1_DQ28 1_DQ27 1_DQ26 1_DQ25 1_DQ24 1_DQ23 1_DQ22 1_DQ21 1_DQ20 1_DQ19 1_DQ18 1_DQ17 1_DQ16 1_DQ15 1_DQ14 1_DQ13 1_DQ12 1_DQ11 1_DQ10 1_DQ9 1_DQ8 1_DQ7 1_DQ6 1_DQ5 1_DQ4 1_DQ3 1_DQ2 1_DQ1 1_DQ0 S2_D2:3 S2_E2:0 S2_E2:1 S2_D2:4 S2_D2:1 S2_E2:2 S2_E2:3 S2_E2:4 S2_E2:5 S2_E3:2 S2_E3:3 S2_E2:6 S2_E2:7 S2_E3:1 S2_E3:4 S2_E3:6 S2_E3:7 S2_E1:4 S2_E1:1 S2_E3:5 S2_E1:7 S2_E1:3 S2_E1:2 S2_E1:0 S2_E0:7 S2_E0:3 S2_E0:2 S2_Q2 S2_E0:5 S2_E0:1 S2_E0:0 Table 5 - B_DDR3D_3A TLA MagniVu Channel Grouping Notes: 1. The ‘S’ in front of a TLA channel denotes the Slave card of the merged pair 2. The ‘M’ in front of a TLA channel denotes the Master card of the merged pair DDR3THIN-MN-XXX 50 Doc. Rev. 1.11 Group Name DataByte7_ 1 DataByte6_ 1 DataByte5_ 1 DataByte4_ 1 Signal Name 1_DQ63 TLA Input S2_A0:0 1_DQ62 1_DQ61 1_DQ60 1_DQ59 1_DQ58 1_DQ57 1_DQ56 1_DQ55 S2_A0:1 S2_A0:5 S2_CK1 S2_A0:2 S2_A0:3 S2_A0:7 S2_A1:0 S2_A1:2 1_DQ54 1_DQ53 1_DQ52 1_DQ51 1_DQ50 1_DQ49 1_DQ48 1_DQ47 S2_A1:3 S2_A1:7 S2_D1:5 S2_A1:1 S2_A1:4 S2_D1:7 S2_D1:6 S2_D1:4 1_DQ46 1_DQ45 1_DQ44 1_DQ43 1_DQ42 1_DQ41 1_DQ40 1_DQ39 S2_D1:1 S2_D0:7 S2_D0:6 S2_D1:3 S2_D1:2 S2_D0:5 S2_D0:4 S2_D0:3 1_DQ38 1_DQ37 1_DQ36 1_DQ35 1_DQ34 1_DQ33 1_DQ32 S2_D0:2 S2_C2:1 S2_C2:4 S2_D0:1 S2_D0:0 S2_C2:6 S2_C2:7 Group Name DataByte3_ 1 DataByte2_ 1 DataByte1_ 1 DataByte0_ 1 Signal Name 1_DQ31 TLA Input S2_D2:6 1_DQ30 1_DQ29 1_DQ28 1_DQ27 1_DQ26 1_DQ25 1_DQ24 1_DQ23 S2_D2:3 S2_E2:0 S2_E2:1 S2_D2:4 S2_D2:1 S2_E2:2 S2_E2:3 S2_E2:4 1_DQ22 1_DQ21 1_DQ20 1_DQ19 1_DQ18 1_DQ17 1_DQ16 1_DQ15 S2_E2:5 S2_E3:2 S2_E3:3 S2_E2:6 S2_E2:7 S2_E3:1 S2_E3:4 S2_E3:6 1_DQ14 1_DQ13 1_DQ12 1_DQ11 1_DQ10 1_DQ9 1_DQ8 1_DQ7 S2_E3:7 S2_E1:4 S2_E1:1 S2_E3:5 S2_E1:7 S2_E1:3 S2_E1:2 S2_E1:0 1_DQ6 1_DQ5 1_DQ4 1_DQ3 1_DQ2 1_DQ1 1_DQ0 S2_E0:7 S2_E0:3 S2_E0:2 S2_Q2 S2_E0:5 S2_E0:1 S2_E0:0 Table 5 – B_DDR3D_3A TLA MagniVu Channel Grouping (cont’d.) Notes: 1. The ‘S’ in front of a TLA channel denotes the Slave card of the merged pair 2. The ‘M’ in front of a TLA channel denotes the Master card of the merged pair DDR3THIN-MN-XXX 51 Doc. Rev. 1.11 Group Name ChkBits Strobes 2 DataMasks Control 2 Misc 2,5 Signal Name CB7 CB6 CB5 CB4 CB3 CB2 CB1 CB0 DQS8 DQS7 DQS6 DQS5 DQS4 DQS3 DQS2 DQS1 DQS0 DM7 DM6 DM5 DM4 DM3 DM2 DM1 DM0 CKE1 CKE0 S3# S2# S1# S0# BA2 BA1 BA0 A15 A14 A13 A12/BC# A10/AP RAS# CAS# WE# MISC1 MISC0 DDRCK0 TLA Input M_A1:5 M_A1:4 M_A1:0 M_A0:7 M_A1:6 M_A1:3 M_CK1 M_A0:5 M_A1:2 S_A2:6 S_A3:5 S_CK1 M_C2:3 M_A0:0 S_C3:0 S_E3:6 S_E2:4 S_A2:4 S_A3:6 S_A1:0 M_C2:0 M_A0:2 S_CK3 S_E3:5 S_E2:6 M_A3:2 M_A3:1 S2_C2:5 S2_C3:0 M_C3:4 M_C3:3 M_A3:0 M_C3:7 M_C1:6 M_CK0 M_A2:5 M_CK3 M_A2:4 M_C1:3 M_C3:6 M_C3:5 M_C1:7 M_A3:5 M_A3:4 M_C1:4 Group Name ChkBits_1 Strobes_1 2 Address 2 Orphans Signal Name 1_CB7 1_CB6 1_CB5 1_CB4 1_CB3 1_CB2 1_CB1 1_CB0 1_DQS8 1_DQS7 1_DQS6 1_DQS5 1_DQS4 1_DQS3 1_DQS2 1_DQS1 1_DQS0 BA2 BA1 BA0 A15 A14 A13 A12/BC# A11 A10/AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 PAR_IN ERR_OUT# TEST RESET# ODT1 ODT0 TLA Input S2_D3:5 S2_D3:4 S2_D3:0 S2_D2:7 S2_D3:6 S2_D3:3 S2_Q0 S2_D2:5 S2_D3:2 S2_A0:6 S2_A1:5 S2_CK2 S2_C2:3 S2_D2:0 S2_E3:0 S2_E1:6 S2:E0:4 M_A3:0 M_C3:7 M_C1:6 M_CK0 M_A2:5 M_CK3 M_A2:4 M_A2:6 M_C1:3 M_A2:1 M_A2:0 M_A2:3 M_C0:2 M_A2:2 M_C0:5 M_C1:0 M_Q1 M_C1:1 M_C1:5 M_C1:2 M_A2:7 M_A3:7 M_A3:6 M_C3:1 M_C3:2 Table 5 – B_DDR3D_3A (<=1333MT/s Read and Write) TLA Channel Grouping (cont’d.) Notes: 1. ‘ # ‘ denotes a low-true signal 2. These signals are required for accurate acquisition and post-processing of acquired data 3. The ‘S’ in front of a TLA channel denotes the Slave card of the merged pair 4. The ‘M’ in front of a TLA channel denotes the Master card of the merged pair 5. MISC1 and MISC0 are placeholders only and will not have interesting data on them DDR3THIN-MN-XXX 52 Doc. Rev. 1.11 5.3 Adjusting Input Thresholds for Proper Data Acquisition The Interposer DDR3 support was designed to work with the new Nexus Low Profile Distributed probes. To maximize the electrical characteristics of the acquired waveforms the probe input resistors values were placed at 510 ohms. This value results in a divide by ten of the signals to the logic analyzer when using the NEX-PRB1X-T and NEX-PRB2X-T probes. The logic analyzer expects a divide by 20. Since the divide value is different than the standard Tektronix probe the voltage swing and offset will be higher than expected, and the thresholds will be different. Instead of the expected 0.75 threshold of approximately 1.9V threshold will be required. Use of the logic analyzer output to a scope will be required to determine the exact threshold for the system under test. 5.4 DDR3 and DDR3SPA It is strongly recommended that Nexus’ DDR3SPA (DDR3 Sample Point Analyzer) be used to determine the proper sample point setting necessary for accurate Read and Write data acquisition. Given the correct DDR bus parameters (Latency, Burst Length, etc.) SPA will analyze any Read and/or Write bus transactions in MagniVu memory and return suggested sample points. Refer to the DDR SPA documentation for more specific information on using this software. If for whatever reason DDR3SPA doesn’t appear to provide good sample point setting information the following sections describe how to evaluate acquired DDR3 data to determine the proper sample points manually. 5.5 Selecting B_DDR3E_XX Read Data Sample Points For the DDR3 Read data to be properly acquired it is necessary to choose the proper sample points to ensure that data is acquired at the proper point in the transaction. Since valid DDR3 Read data is straddled by the Strobes (see Figure 4) the Setup & Hold sample point must be set for the valid data that occurs closest to the clock edge. The appropriate clock edge for Reads is determined by adding the Additive Latency value to the CAS Latency value and adding one if Registered memory (RDIMMs) are being used, resulting in the total number of clock cycles from the Read Command to the first valid Read Data. (If these values are not known the technique described in Section 7.3 can be used to determine the necessary values with the exception of whether or not the memory is RDIMM or UDIMM.) In Figure 4 the total Read latency is 6 cycles. The B_DDR3D_XX supports acquire two samples of valid Read data on each rising edge of the DDR3 clock. So to acquire both pieces of data the RdA_DatHi/Lo data groups must have their sample point set to that shown by Sample Pt. #1 in the Figure, and the RdB_DatHi/Lo data groups must have their sample point set to that shown by Sample Pt. #2. DDR3THIN-MN-XXX 53 Doc. Rev. 1.11 Sample Pt. #2 Sample Pt. #1 Figure 4 - Read Data Latency = CAS Latency + CAS Additive Latency + RDIMM (5+0+1) = 6 cycles) 5.6 Selecting B_DDR3D_XX Write Data Sample Points Unlike valid DDR Read data, valid Write data is bisected by the Strobes. Since valid DDR3 Write data is bisected by the Strobes (see Figure 5) the Setup & Hold sample point must be set for the valid data that occurs closest to the clock edge. The appropriate clock edge for Writes is determined by counting the number of clock cycles specified by the Write Latency MRS value from the Write Command to the first valid Write Data. (If these values are not known the technique described in Section 7.3 can be used to determine them.) In Figure 5 the total Write latency is 6 cycles (Write Latency plus the additional one cycle delay for RDIMM memory). Sample Pt. #1 Sample Pt. #2 Write Data Preamble Figure 5 - Write Data Latency = CAS Write Latency + RDIMM (5+1) = 6 cycles DDR3THIN-MN-XXX 54 Doc. Rev. 1.11 The B_DDR3D_XX supports acquire two samples of valid Write data on each rising edge of the DDR3 clock. So to acquire both pieces of data the WrA_DatHi/Lo data groups must have their sample point set to that shown by Sample Pt. #1 in the Figure, and the WrB_DatHi/Lo data groups must have their sample point set to that shown by Sample Pt. #2. NOTE - It is important to note that because of the design of the TLA acquisition card inputs and the Strobe activity prior to Write data being placed on the data bus it will appear as if the Strobes indicate valid Write data earlier than the data is actually there (see the circle indicated as Write Data Preamble in Figure 5). These Write Preamble Strobe edges should NOT be used to determine where valid Write data is on the data bus. 5.7 B_DDR3D_XX Support Setup Using the B_DDR3D_XX supports it is possible to acquire both Read and Write data by setting the sample point of the data groups appropriately. To adjust the Read Data group sample points first make an appropriate acquisition of Read data by triggering on a Read command. Then create a timing window display of MagniVu data and display the Data_Hi and Data_Lo 32-bit data groups, the individual Command group signals and the DDR3 clock that was used for the data acquisition (DDRCK0). A sample waveform display of MagniVu Read data is shown in Figure 6. To determine the sample point, locate the smallest window of valid Read data during the acquired burst (see Figure 6). Note that in this instance the first piece of valid data happens significantly after the rising edge it is associated with. In fact the initial valid data appears at the DDR Clock falling edge. This delay must be taken into account or data will not be aligned properly in the Listing display window. Note that A and B data (corresponding to ADataHi/Lo and BDataHi/Lo data groups) have been indicated. Latency expires Read Command Valid Read Data Begins A B A Minimum S&H B Figure 6 - Locating Minimum Valid B_DDR3D_XX Read Data Window DDR3THIN-MN-XXX 55 Doc. Rev. 1.11 A B Figure 7 - Measuring B_DDR3D_XX RdA_DatHi / Lo Read Data Setup & Hold Zoom in further to determine the Setup and Hold sample point necessary to acquire valid data at that point (Figure 7) and use the cursors to measure the time from the clock edge to the start of valid Read data. In this example the delay from edge to data is approximately -1.05ns after the clock edge, meaning that a suitable Setup & Hold value for the RdA_DatHi capture group would be -1.055ns/1.289ns. Note that the Data_Lo group is valid somewhat later than the Data_Hi group with its valid time starting at approximately 1.23ns after the clock edge, so the Setup & Hold sample point for the RdA_DatLo capture group would be set to -1.23ns/1.465ns. Now the sample point for the RdB_DatHi and RdB_DatLo groups must be determined (see Figure 8). The next valid Read data (after the cycle measured above) occurs approximately 2.37ns after the rising edge of DDRCK0, so a suitable Setup & Hold value for the RdB_DatHi capture group would be –2.383ns/2.617ns. As with the A data the Data_Lo group is somewhat later than the Data_Hi group. The Data_Lo valid time starts at approximately -2.52ns so a suitable Setup & Hold value for the RdB_DatLo capture group would be -2.52ns/2.754ns. DDR3THIN-MN-XXX 56 Doc. Rev. 1.11 A B Figure 8 - Measuring B_DDR3D_XX RdB_DatHi / Lo Read Data Setup & Hold Now the sample point positions must be set for the RdA_DatHi, RdA_DatLo, RdB_DatHi and RdB_DatLo capture groups in the Setup window (see Figure 9). This window is found by going to the LA Card’s Setup window, then clicking on the More button to the right of the clock select field. The TLA acquisition cards require a valid data window of approximately 300ps, and this window can be placed to begin from 15.098ns prior to the clock edge to 7.383ns after the edge in roughly 20ps increments. Each 32-bit data group (RdA_DatHi, RdA_DatLo, RdB_DatHi, RdB_DatLo) will require its own value programmed from the measurements noted in the MagniVu window. Figure 9 - Setting B_DDR3D_XX RdA_DatHi / Lo and RdB_DatHi / Lo Sample Points DDR3THIN-MN-XXX 57 Doc. Rev. 1.11 Setting the Setup & Hold values for acquiring Write data is a similar process. To determine the Write Data group sample points first make an appropriate acquisition of Write data by triggering on a Write Command. Then, as above, create a timing window display of MagniVu data and display the Data_Hi and Data_Lo 32-bit data groups, the individual Command group signals and the DDR3 clock that was used for the data acquisition (DDRCK0). A sample waveform display of MagniVu Write data is shown in Figure 10. To determine the sample point, locate the smallest window of valid Write data during the acquired burst (see Figure 10). Note that in this instance the first piece of valid data happens before the rising edge it is associated with. This shift must be taken into account or data will not be aligned properly in the Listing display window. Note that A and B data (corresponding to ADataHi/Lo and BDataHi/Lo data groups) have been indicated. Refer to section 5.6 for important information on properly determining the Write data sample points. Latency expires Write Command A B A B Minimum S&H Write Data Preamble Figure 10 - Locating Minimum Valid B_DDR3D_XX Write Data Window Zoom in further to determine the Setup and Hold sample point necessary to acquire valid data at that point (Figure 11) and use the cursors to measure the time from the clock edge to the start of valid Write data. In this example the data leads the clock edge by approximately 740ps, meaning that a suitable Setup & Hold value for the WrA_DatHi capture group would be 742ps/-508ps. Note that the Data_Lo group is valid somewhat later than the Data_Hi group with its valid time starting at approximately 430ps prior to the clock edge, so the Setup & Hold sample point for the WrA_DatLo capture group would be set to 430ps/-195ps. DDR3THIN-MN-XXX 58 Doc. Rev. 1.11 A B Figure 11 - Measuring B_DDR3D_XX WrA_DatHi / Lo Write Data Setup & Hold Now the sample point for the WrB_DatHi and WrB_DatLo groups must be determined (see Figure 12). The next valid Write data (after the cycle measured above) occurs approximately 500ps after the rising edge of DDRCK0, so a suitable Setup & Hold value for the WrB_DatHi capture group would be -508ps/742ps. As with the A data the Data_Lo group is somewhat later than the Data_Hi group. The Data_Lo valid time starts at approximately -800ps so a suitable Setup & Hold value for the WrB_DatLo capture group would be -801ps/1.035ns. Figure 12 - Measuring B_DDR3D_XX WrB_DatHi / Lo Write Data Setup & Hold The sample point positions must now be set for the WrA_DatHi, WrA_DatLo, WrB_DatHi, WrB_DatLo groups in the Setup window (Figure 13). Note that if the Upper Strobes are being DDR3THIN-MN-XXX 59 Doc. Rev. 1.11 used as Data Masks then the WrtMasks group should have a Setup & Hold value that matches that of the Write Data groups. Figure 13 - Setting B_DDR3D_XX WrA_DatHi / Lo and WrB_DatHi / Lo Sample Points Because of the speeds of DDR3 data it may be necessary to program Setup & Hold values for each of the 8-bit groups that are associated with a given Strobe. This could be required if there is significant skew between the DDR Strobes. Figure 14 shows some of these additional data groups (DataByte7-0) added to the same Waveform display shown in Figure 12. Note that it is now possible to determine the skew between data groups and place these values into the Setup & Hold Window settings in the TLA Setup window (see Figure 15). Refer to Appendix F Data Group / Byte / Strobe Cross-Reference for details on which 8-bit groups make up a 32-bit group. When setting the individual Setup & Hold values it is suggested that the settings for the associated 32-bit group (RdA_DatHi, RdA_DatLo, RdB_DatHi, RdB_DatLo, WrA_DatHi, WrA_DatLo, WrB_DatHi, WrB_DatLo) be reset to “Support Package Default”. This will prevent the TLA from displaying warnings that conflicting values have been set for the data bits. The Support Package Default Setup & Hold values are the same as the TLA default values – 117ps/117ps. It will also be necessary to program the Setup & Hold values for all of the 8-bit groups in the affected 32-bit group. If conflicting Setup & Hold points are programmed then the values will have exclamation marks beside them to denote the conflict. DDR3THIN-MN-XXX 60 Doc. Rev. 1.11 Figure 14 - Viewing Individual 8-bit Read Data Groups Figure 15 - Setting Individual Setup & Hold Values for the 8-bit Read Data Groups Note: Values shown are for illustration purposes only DDR3THIN-MN-XXX 61 Doc. Rev. 1.11 5.8 Setting B_DDR3D_3A Read Data Sample Points The same procedure outlined above for setting Read Data sample points should be used to determine the sample points for Read Data from teh second DIMM slot. Set the sample points for the groups named RdA_DatHi_1, RdA_DatLo_1, RdB_DatHi_1 and RdB_DatLo_1. DDR3THIN-MN-XXX 62 Doc. Rev. 1.11 6.0 VIEWING DATA 6.1 Viewing B_DDR3D_XX Data When using the NEX-DDR3INTR-THIN support packages the raw Address and Data groups are suppressed and are replaced with post-processed data in new groups. This data is displayed in new groups that have the support package name preceding it (i.e., B_DDR3D_XX Address, B_DDR3D_XX DataHi, etc.). The raw data groups are suppressed so that the display of data can be done in a more user-friendly fashion. The Command group is suppressed because its function is replaced with a column labeled “B_DDR3D_XX Mnemonics”. The Interposer support software includes post-processing code that permits masking out all invalid Read / Write and non-Command data, providing the user a much better overview of bus activity. Figure 16 shows the default B_DDR3D_XX display where all DDR3 data is displayed. Figure 16 - B_DDR3D_XX Listing Display DDR3THIN-MN-XXX 63 Doc. Rev. 1.11 To change the display it is necessary to bring up the window’s Properties window (perform a right mouse-click in the State display window) and select the Disassembly tab. This will bring up the configuration window shown in Figure 17. Figure 17 - Disassembly Properties There are several select fields available in this window, some of which must be set correctly for the post-processing software to work properly. These fields and their selections are: Burst Length - permits setting the burst length for Read and Write data. Valid choices are 4 (the default) 8, and 4/8 On-the-Fly. This value must be set properly for all valid Read and Write data to be displayed. CAS Latency (CL) - sets the delay, in clock cycles, from the Read command until the first piece of valid Read data is available. This value must be set properly for all valid Read Data to be displayed. Valid choices are 5 (default), 6, 7, 8, 9 or 10 cycles. CAS Additive Latency - additional latency for data cycles. This value must also be set properly for valid Read Data to be displayed. Valid choices are 0 (default), CL-1, or CL2 cycles. CAS Write Latency – number of clock cycles from Write command to the first Write Data. This value must be set properly for all valid Write Data to be displayed. Valid choices are 5 (default), 6, 7, or 8 cycles. Registered? – must be set to reflect whether or not Registered DDR memory is used. Default is No. When set to Yes an additional clock cycle delay is added to CAS Latency and to valid Read and Write Data tagging. DDR3THIN-MN-XXX 64 Doc. Rev. 1.11 DM Signal Use - permits setting Data Mask functionality to Write Masks (default) or Strobes. When set to Write Mask the DM signals will be used to mask Write Data to show which data bytes were valid in the cycle. In addition to these Disassembly Properties selections, changing the settings in the Show field results in display changes as well: Hardware - (default) displays all acquired cycles Software - suppresses all idle or wait cycles Control Flow - shows Address Command and valid Read / Write data cycles Subroutine - shows valid Read / Write data cycles only Figure 18 - B_DDR3D_XX Listing Display - Control Flow Changing the Show field setting in the display of Figure 16 from Hardware to Control Flow results in the display of Figure 18 where only Row and Column Address commands and valid DDR3THIN-MN-XXX 65 Doc. Rev. 1.11 data are displayed. Note that the timestamp is updated to reflect the time between displayed cycles. 6.2 Viewing Raw DDR3 Data using B_DDR3D_XX Supports In order to make the display of DDR3 data more user-friendly the raw data from the Address, all Data and other groups is suppressed in the B_DDR3D_2D Listing display. Instead the postprocessing display software formats and reorders the data to tag and display valid DDR3 Address, Commands and Data. In the case of the B_DDR3D_2D supports, which stores two Read and two Write data cycles in each TLA Sample location, the data is reordered chronologically in the display with the oldest data being shown on the line above the newer data. To see the raw data using the Interposer support package perform a right mouse click in the Listing window, select Add Column… then click on the group to be added. Refer to the TLA User’s Manual or online help for further information on added or deleting data groups. 6.3 B_DDR3D_2A / 3A Mnemonics Description Table 6 gives a brief description of each of the text lines displayed in the B_DDR3D_2A / _3A post-processing software display. Mnemonic Description ACT – BANK ACTIVATE (Sx#) Bank: DESL - IGNORE COMMAND (E)MRS – (EXTENDED) MODE REGISTER SET x (Sx#) NOP - NO OPERATION (Sx#) PRE – SINGLE BANK PRECHARGE (Sx#) Bank: PREA – PRECHARGE ALL BANK (Sx#) RDA – READ W/AUTO PRECHARGE (Sx#) Bank: RD - READ (Sx#) Bank: READ DATA REF - REFRESH (Sx#) WRA – WRITE W/AUTO PRECHARGE (Sx#) Bank: WR - WRITE (Sx~) Bank: WRITE DATA ZQCL – ZQ CALIBRATION LONG (Sx#) ZQCS – ZQ CALIBRATION SHORT (Sx#) Active command – activate a row in a bank for subsequent access (Chip Select 0-3; Bank x) Deselect function – no new command Mode Register Set command, registers 0-3; (Chip Select 0-3) No Operation command (Chip Select 0-3) Precharge command (Chip Select 0-3; Bank x) Precharge All command (Chip Select 0-3) Read command with auto precharge (Chip Select 0-3; Bank x) Read command – initiates a burst read access to active row (Chip Select 0-3; Bank x) Valid Read data on the bus Self Refresh command (Chip Select 0-3) Write command with auto precharge (Chip Select 0-3; Bank x) Write command – initiates a burst write access to active row (Chip Select 0-3; Bank x) Valid Write data on the bus ZQ Calibration Long (Chip Select 0-3) ZQ Calibration Short (Chip Select 0-3) Table 6 - B_DDR3D_2A / 3A Mnemonics Definition 6.4 B_DDR3D_2G Mnemonics Description DDR3THIN-MN-XXX 66 Doc. Rev. 1.11 Table 7 gives a brief description of each of the text lines displayed in the B_DDR3D_2G postprocessing software display. Mnemonic Description ACT – BANK ACTIVATE (Sx# / bS# / cS#) Bank: DESL - IGNORE COMMAND (E)MRS – (EXTENDED) MODE REGISTER SET x (Sx# / bS# / cS#) NOP - NO OPERATION (Sx# / bS# / cS#) PRE – SINGLE BANK PRECHARGE (Sx# / bS# / cS#) Bank: PREA – PRECHARGE ALL BANK (Sx# / bS# / cS#) RDA – READ W/AUTO PRECHARGE (Sx# / bS# / cS#) Bank: RD - READ (Sx# / bS# / cS#) Bank: READ DATA REF - REFRESH (Sx# / bS# / cS#) WRA – WRITE W/AUTO PRECHARGE (Sx# / bS# / cS#) Bank: WR - WRITE (Sx# / bS# / cS#) Bank: WRITE DATA ZQCL – ZQ CALIBRATION LONG (Sx# / bS# / cS#) ZQCS – ZQ CALIBRATION SHORT (Sx# / bS# / cS#) Active command – activate a row in a bank for subsequent access (Slot A, B or C; Chip Select 0-3; Bank x) Deselect function – no new command Mode Register Set command, registers 0-3; (Slot A, B or C; Chip Select 0-3) No Operation command (Slot A, B or C; Chip Select 0-3) Precharge command (Slot A, B or C; Chip Select 0-3; Bank x) Precharge All command (Slot A, B or C; Chip Select 0-3) Read command with auto precharge (Slot A, B or C; Chip Select 0-3; Bank x) Read command – initiates a burst read access to active row (Slot A, B or C; Chip Select 0-3; Bank x) Valid Read data on the bus Self Refresh command (Slot A, B or C; Chip Select 0-3) Write command with auto precharge (Slot A, B or C; Chip Select 0-3; Bank x) Write command – initiates a burst write access to active row (Slot A, B or C; Chip Select 0-3; Bank x) Valid Write data on the bus ZQ Calibration Long (Slot A, B or C; Chip Select 0-3) ZQ Calibration Short (Slot A, B or C; Chip Select 0-3) Table 7 - B_DDR3D_2G Mnemonics Definition 6.5 Viewing Timing Data on the TLA By default, the TLA will display an acquisition in the Listing (State) mode. However, the same data can be displayed in Timing form by adding a Waveform Display window. This is done by clicking on the Window pull-down, selecting New Data Window, clicking on Waveform Window Type, then choosing the Data Source. Two valid choices are presented: B_DDR3D_XX and B_DDR3D_XX: MagniVu. The first will show the exact same data (same acquisition mode) as that shown in the Listing window, except in Waveform format. The second selection will show all of the channels in 8GHz MagniVu mode, so that edge relationships can be examined around the MagniVu trigger point. MagniVu is very useful and in some cases necessary to see/resolve DDR3 data. With either selection, all channels can be viewed by scrolling down the window. Refer to the TLA System User’s Manual for additional information on formatting the Waveform display. DDR3THIN-MN-XXX 67 Doc. Rev. 1.11 Figure 19 - B_DDR3D_XX MagniVu Display on TLA DDR3THIN-MN-XXX 68 Doc. Rev. 1.11 7.0 HINTS & TIPS 7.1 Symbolic Triggering on a Command using B_DDR3D_XX Supports A Symbol Table has been included for the Control data groups defined in each of the support packages. The Symbol Table for the B_DDR3D_2D / 3A supports is shown in Table 8; the Symbol Table for the B_DDR3D_2G support is shown in Table 9. The use of Symbol Tables when triggering makes it easier for the user to define a given cycle to be triggered on. Rather than trying to remember what signals make up the Control group, the Symbol Table has the appropriate bits already set for the given cycle. It is important to note that changing the channel definition of the Control group can result in incorrect symbol information being displayed. Symbol Definition cc ssss = x1 1110 for S0# cc ssss = 1x 1101 for S1# cc ssss = x1 1011 for S2# cc ssss = 1x 0111 for S3# x in Definition = Don’t Care MRS – Sx# MODE REGISTER SET cc ssss xxx xxx xx000 REF – Sx# REFRESH cc ssss xxx xxx xx001 PRE – Sx# SINGLE BANK PRECHARGE cc ssss xxx xxx x0010 PREA – Sx# PRECHARGE ALL BANKS cc ssss xxx xxx x1010 ACT – Sx# ACTIVATE BANK cc ssss xxx xxx xx011 WR – Sx# WRITE cc ssss xxx xxx x0100 WRA – Sx# WRITE WITH AUTO cc ssss xxx xxx x1100 PRECHARGE RD – Sx# READ cc ssss xxx xxx x0101 RDA – Sx# READ WITH AUTO cc ssss xxx xxx x1101 PRECHARGE NOP –Sx# NO OPERATION cc ssss xxx xxx xx111 DES - DEVICE DESELECT cc ssss xxx xxx xxxxx ZQCL – Sx# ZQ CALIBRATION LONG cc ssss xxx xxx x1110 ZQCS – Sx# ZQ CALIBRATION SHORT cc ssss xxx xxx x0110 Table 8 - B_DDR3D_2D / 3A Control Symbol Table Signals, left-to-right: CKE1, CKE0, S3#, S2#, S1#, S0#, BA2, BA1, BA0, A15, A14, A13, A12/BC#, A10/AP, RAS#, CAS#, WE# DDR3THIN-MN-XXX 69 Doc. Rev. 1.11 Symbol Definition cccc ssssssss = xxxxx1 1110 for S0# cccc ssssssss = xxxx1x 1101 for S1# cccc ssssssss = xxxxx1 1011 for S2# cccc ssssssss = xxxx1x 0111 for S3# cccc ssssssss = xxxxx1 1110 for bS0# cccc ssssssss = xxxx1x 1101 for bS1# cccc ssssssss = xxxxx1 1011 for cS0# cccc ssssssss = xxxx1x 0111 for cS1# x in Definition = Don’t Care MRS – Sx# MODE REGISTER SET cccc ssssssss xxx xxx xx000 MRS – bSx# MODE REGISTER SET cccc ssssssss xxx xxx xx000 MRS – cSx# MODE REGISTER SET cccc ssssssss xxx xxx xx000 REF – Sx# REFRESH cccc ssssssss xxx xxx xx001 PRE – Sx# SINGLE BANK PRECHARGE cccc ssssssss xxx xxx x0010 PREA – Sx# PRECHARGE ALL BANKS cccc ssssssss xxx xxx x1010 ACT – Sx# ACTIVATE BANK cccc ssssssss xxx xxx xx011 WR – Sx# WRITE cccc ssssssss xxx xxx x0100 WRA – Sx# WRITE WITH AUTO cccc ssssssss xxx xxx x1100 PRECHARGE RD – Sx# READ cccc ssssssss xxx xxx x0101 RDA – Sx# READ WITH AUTO cccc ssssssss xxx xxx x1101 PRECHARGE NOP –Sx# NO OPERATION cccc ssssssss xxx xxx xx111 DES - DEVICE DESELECT cccc ssssssss xxx xxx xxxxx ZQCL – Sx# ZQ CALIBRATION LONG cccc ssssssss xxx xxx x1110 ZQCS – Sx# ZQ CALIBRATION SHORT cccc ssssssss xxx xxx x0110 Table 9 - B_DDR3D_2G Control Symbol Table Signals, left-to-right: cCKE1, cCKE0, bCKE1, bCKE0, CKE1, CKE0, cS1#, cS0#, bS1#, bS0#, S3#, S2#, S1#, S0#, BA2, BA1, BA0, A15, A14, A13, A12/BC#, A10/AP, RAS#, CAS#, WE# 7.3 Capturing MRS (Mode Register Set) Cycles If the characteristics of the DDR target (latency, burst length) are not known it is possible to acquire this information using the TLA so that the post-processing Control settings can be properly set. This information is programmed into the DDR memory upon system boot by use of the MRS (Mode Register Set) command, and is required when using the NEX-DDR3INTRTHIN supports for the post-processing software to properly decode the acquisitions. The TLA trigger shown in Figure 19 can be used to acquire the MRS cycles when using either of these supports. Note that because there is no Trigger event defined in this example that it will be necessary to Stop the TLA acquisition manually to display the MRS data. A trigger could certainly be added in either (or both) of the Trigger events, but the method shown ensures that the last valid MRS cycles will be acquired regardless of the memory depth setting of the acquisition card. DDR3THIN-MN-XXX 70 Doc. Rev. 1.11 Figure 20 - B_DDR3D_2D MRS Trigger In the trigger example a Storage condition has been created so that only MRS cycles will be stored. In testing, multiple MRS cycles were seen during the boot process, and the example triggers shown will ensure that all of the MRS cycles will be acquired, an example of which is shown in Figure 20. The last acquired MRS cycle will reflect the settings used in the DDR target – in this case, a CAS latency of 2 cycles with a Burst length of 8. Figure 21 - MRS Cycle Acquisition Disassembly 7.4 Clock Capture quality The clock captured by the logic analyzer may exhibit ringing. If this ringing is such that a clock reference voltage can not be determined it is suggested that the capacitor on the DIMM across DDR3THIN-MN-XXX 71 Doc. Rev. 1.11 the differential pair by removed. The added capacitance of the logic analyzer compensates for this missing capacitor. 7.5 Thresholds Analog waveforms and their associated thresholds viewed using the Tektronix Analog Mux will display amplitudes and thresholds that are not an exact representation of the actual analog waveform. The Nexus passive probes used on DDR3 NEXVu and Interposer products are designed to supply maximum voltage swing to the Logic analyzer to insure correct digital signal swing capture at the high DDR3 rates. While the Tektronix active P69xx and P68xx series of probe, being general purpose probes, divide the input voltage swing by 20 the passive probes from Nexus divide the signals by approximately 7.5. Since the divide value is different than the standard Tektronix probe the voltage swing and offset will be higher than expected, and the thresholds will be different. Instead of the expected 0.75 threshold of approximately 1.9V threshold will be required. This was designed specifically for DDR3 signals to allow the best possible capture of the digital representation of these signals. Viewing the output of the Logic Analyzer analog mux should be used as a tool to provide fine adjustment of the logic analyzer signal Vref. The threshold value determined in this manner should be used as the threshold setting for the Nexus DDR3 product. Please note: Only the vertical resolution is affected by the Nexus passive probes. DDR3THIN-MN-XXX 72 Doc. Rev. 1.11 APPENDIX A – How DDR Data is Clocked A.1 Background Demultiplexing means that the TLA’s Logic Analyzer card can have one data probe connected to the target yet store incoming data in two or four separate data sections of the card. For instance, the A3 data section (8-bits) can be connected to the target and data can be stored in the A3 section and the D3 section. Using the equivalent of 4X demux (by utilizing both the cross-point switch and prime memory capabilities of the acquisition card), connections made to the A3 channels permit data to be stored in the A3, A3B (prime channels), D3 and D3B sections. A very useful side benefit of using demux is that, since only one set of TLA data channels has to be connected, only one probe load is added to the target, even though data is stored in two or four different locations of the acquisition card. A.2 DDR Acquisition - General All of the above is background necessary to understand how the TLA is able to acquire data at rates that initially look too fast. The speeds of DDR3 (1066 MT/s) require different setups to enable proper data acquisition. In addition, instead of trying to use the 8 Data Strobes to acquire data our solution uses CLK0 of the DDR SDRAM Clocks and all data acquisition is adjusted in relation to the clock edges. The 8 Data Strobes cannot be easily used to acquire data as some TLA configurations only support 4 Clock Inputs. Also, the Strobes cannot be used to acquire Address and Command information. DDR3THIN-MN-XXX 73 Doc. Rev. 1.11 A.3 B_DDR3D_2D / 2G / 3A Data Acquisition These supports requires two (2) merged 136-channel with 1.4G state option TLA7BB4 acquisition cards used in a TLA7XX logic analyzer. Data is acquired using the rising edge of the DDR clock. A_Data information is earlier (older) data than the information stored in B_Data. Different Sample Points must be set for each of the four 32-bit Data groups, and, if necessary, sample points can be set for any of the 8-bit data groups or for individual data bits. Clock Read Rb Ra Rd Rc Re RdA-S&H RdB-S&H Write Wa Wb Wc Wd We WrA-S&H WrB-S&H DDR3THIN-MN-XXX 74 Doc. Rev. 1.11 APPENDIX B - Considerations B.1 NEX-DDR3INTR-THIN Bus Loading It must be noted that the NEX-DDR3INTR-THIN Interposer is designed to minimal effect on the user’s circuit. The acquired signals are sampled at top edge connector, and then passed through isolation resistors to the probe. There will be an effective 600 ohm load on all probed signals. The B_DDR3D_3A support will use two Interposers and will double probe all signal. Thus the DC load will be near 300 ohms. The DDR3 Interposer has been tested via detailed simulations, and by actual in circuit testing. B.2 DIMM connector location for best quality signal capture An interposer is subject to reflected noise and the quality of the acquisitions should improve if the Interposer is in the furthest slot away from the memory controller. If the memory channel contains two DIMM slots and only one will be used, the slot used must be the furthest away from the memory controller. B.3 TLA7BB4 Module to module skew At print time Tektronix had not yet specified the module to module skew that will be displayed in MagniVu, and timing modes. This skew is around 300ps. It is expected that in future releases Tektronix will remove this skew. Contact Tektronix for updates. DDR3THIN-MN-XXX 75 Doc. Rev. 1.11 APPENDIX C – 240-pin DDR3 DIMM Pinout Pin # 1 2 3 4 Front Side (left 1-60) X64 X72 NonECC Parity VREF VREF VSS VSS DQ0 DQ0 DQ1 DQ1 Back Side (right 121-180 Pin # X64 Non-Parity X72 ECC 121 122 123 124 VSS DQ4 DQ5 VSS DM0 DQS9 NC DQS9# VSS VSS DQ4 DQ5 VSS DM0 DQS9 NC DQS9# VSS 5 VSS VSS 125 6 DQS0# DQS0# 126 7 DQS0 DQS0 127 Front Side (left 61-120) X64 X72 Pin # NonECC Parity 61 A2 A2 62 VDD VDD 63 CK1 CK1 64 CK1# CK1# 65 VDD Back Side (right 181-240) X64 X72 Pin # NonECC Parity 181 A1 A1 182 VDD VDD 183 VDD VDD 184 CK0 CK0 VDD 185 CK0# CK0# 66 VDD VDD 186 VDD VDD 67 VREF NC Par_In VDD A10/AP BA0 VDD WE# 187 TEST/NC TEST/NC 188 A0 A0 189 190 191 192 193 VDD BA1 VDD RAS# S0# VDD BA1 VDD RAS# S0# 8 VSS VSS 128 DQ6 DQ6 68 9 10 11 12 13 DQ2 DQ3 VSS DQ8 DQ9 DQ2 DQ3 VSS DQ8 DQ9 129 130 131 132 133 VSS VSS 134 74 CAS# CAS# 194 VDD VDD 15 DQS1# DQS1# 135 75 VDD VDD 195 ODT0 ODT0 16 DQS1 DQS1 136 DQ7 VSS DQ12 DQ13 VSS DM1 DQS10 NC DQS10# VSS 69 70 71 72 73 14 DQ7 VSS DQ12 DQ13 VSS DM1 DQS10 NC DQS10# VSS VREF NC Par_In VDD A10/AP BA0 VDD WE# 76 17 VSS VSS 137 DQ14 DQ14 77 18 DQ10 DQ10 138 DQ15 DQ15 78 19 DQ11 DQ11 139 VSS VSS 79 20 21 22 VSS DQ16 DQ17 VSS DQ16 DQ17 140 141 142 80 81 82 VSS VSS 143 83 VSS VSS 203 24 25 26 27 28 29 30 31 DQS2# DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 DQS2# DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 144 145 146 147 148 149 150 151 84 85 86 87 88 89 90 91 DQS4# DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 DQS4# DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 204 205 206 207 208 209 210 211 32 VSS VSS 152 92 VSS VSS 212 33 34 35 36 37 38 39 40 DQS3# DQS3 VSS DQ26 DQ27 VSS NC NC DQS3# DQS3 VSS DQ26 DQ27 VSS CB0 CB1 153 154 155 156 157 158 159 160 DQ20 DQ21 VSS DML2 DQS11 DQS11# VSS DQ22 DQ23 VSS DQ28 DQ29 VSS DM3 DQS12 DQS12# VSS DQ30 DQ31 VSS CB4 CB5 VSS S1# RSVD ODT1 VDD RSVD Spd3 VSS DQ32 DQ33 23 DQ20 DQ21 VSS DML2, DQS11 DQS11# VSS DQ22 DQ23 VSS DQ28 DQ29 VSS DM3 DQS12 DQS12# VSS DQ30 DQ31 VSS NC NC VSS S1# RSVD ODT1 VDD RSVD SPD# VSS DQ32 DQ33 93 94 95 96 97 98 99 100 DQS5# DQS5 VSS DQ42 DQ43 VSS DQ48 DQ49 DQS5# DQS5 VSS DQ42 DQ43 VSS DQ48 DQ49 213 214 215 216 217 218 219 220 DDR3THIN-MN-XXX 76 196 A13 A13 197 VDD VDD 198 Free Free 199 VSS VSS 200 201 202 DQ36 DQ37 VSS DM4 DQS13 DQS13# VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DM5 DQS14 DQS14# VSS DQ46 DQ47 VSS DQ52 DQ53 VSS DQ36 DQ37 VSS DM4 DQS13 DQS13# VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DM5 DQS14 DQS14# VSS DQ46 DQ47 VSS DQ52 DQ53 VSS Doc. Rev. 1.11 APPENDIX C - 240-pin DDR3 DIMM Pinout (cont’d.) Front Side (left 1-60) X64 Pin X72 Non# ECC Parity 42 43 44 45 46 47 48 DQS8# DQS8 VSS NC NC VSS Free KEY DQS8# DQS8 VSS CB2 CB3 VSS Free 162 163 164 165 166 167 168 49 RESET# RESET# 169 CKE1 CKE1 110 VSS VSS 50 51 52 CKE0 VDD BA2 NC CKE0 VDD BA2 NC 170 171 172 VDD A15 A14 VDD A15 A14 111 112 113 DQS7# DQS7 VSS DQS7# DQS7 VSS Back Side (right 181-240) X64 Pin X72 Non# ECC Parity DM6 DM6 221 DQS15 DQS15 222 DQS15# DQS15# 223 VSS VSS 224 DQ54 DQ54 225 DQ55 DQ55 226 VSS VSS 227 DQ60 DQ60 228 DQ61 DQ61 229 VSS VSS DM7 DM7 230 DQS16 DQS16 231 DQS16# DQS16# 232 VSS VSS 233 DQ62 DQ62 ERR-OUT# ERR-OUT# 173 VDD VDD 114 DQ58 DQ58 234 DQ63 DQ63 VDD A11 A7 VDD A5 A4 VDD VDD A11 A7 VDD A5 A4 VDD 174 175 176 177 178 179 180 A12 A9 VDD A8 A6 VDD A3 A12 A9 VDD A8 A6 VDD A3 115 116 117 118 119 120 DQ59 VSS SA0 SLC SA2 VTT DQ59 VSS SA0 SLC SA2 VTT 235 236 237 238 239 240 VSS VDDSPD SA1 SDA VSS VTT VSS VDDSPD SA1 SDA VSS VTT 41 53 54 55 56 57 58 59 60 VSS Back Side (right 121-180 Pin # VSS 161 DDR3THIN-MN-XXX X64 Non-Parity DM8 DQS17 DQS17# VSS NC NC VSS Test Free KEY Front Side (left 61-120) X64 Pin X72 Non# ECC Parity X72 ECC DM8 DQS17 DQS17# VSS CB6 CB7 VSS Test Free 77 101 VSS VSS 102 103 104 105 106 107 108 109 DQS6# DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 DQS6# DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 Doc. Rev. 1.11 APPENDIX D –Data Flow Through the Probes (coax cable to channel) Data flow Slave1 C3/2/1/0 Master A3/2 D3/2 Master C3/2/1/0 Slave1 A3/2 D3/2 Slave1 E3/2/1/0 Master A1/0 D1/0 Slave1 A1/0 D1/0 Plastic Housing that plugs into TLA 7BB4 Samtec Connectors plug together at this point J15-x Coax on top J16-x Coax on J16-1 edge J15-1 edge Master A3/2 & Slave1 C3/2 & E3/2 DDR3THIN-MN-XXX Interposer Slave1 A3/2 & A1/0 Master 78 Doc. Rev. 1.11 APPENDIX D - Data Flow Through the Probes (cont’d.) Coax wire PIN J16-2 J16-5 J16-8 J16-11 J16-14 J16-17 J16-4 J16-7 J16-10 J16-13 J16-16 J16-3 J16-6 J16-9 J16-12 J16-15 J16-18 J15-18 J15-15 J15-12 J15-9 J15-6 J15-3 J15-16 J15-13 J15-10 J15-7 J15-4 J15-17 J15-14 J15-11 J15-8 J15-5 J15-2 DDR3THIN-MN-XXX M_C Channel C2:0 C2:5 C3:3 C1:5 C1:0 C0:3 C2:4 C3:2 C3:7 C1:1 C0:6 C2:1 CLK3 C3:6 C1:4 C0:7 C0:2 C2:2 C2:7 C3:4 C1:6 Q1 C0:1 C2:6 C3:1 C1:7 C1:2 C0:4 C2:3 C3:0 C3:5 C1:3 C0:5 C0:0 M_A3/2 A1/0 Channel A0:0 A0:5 A1:3 A3:5 A3:0 A2:3 A0:4 A1:2 A1:7 A3:1 A2:6 A0:1 CLK1 A1:6 A3:4 A2:7 A2:2 A0:2 A0:7 A1:4 A3:6 CLK0 A2:1 A0:6 A1:1 A3:7 A3:2 A2:4 A0:3 A1:0 A1:5 A3:3 A2:5 A2:0 79 S_A3/2 A1/0 Channel A0:0 A0:5 A1:3 A3:5 A3:0 A2:3 A0:4 A1:2 A1:7 A3:1 A2:6 A0:1 CLK1 A1:6 A3:4 A2:7 A2:2 A0:2 A0:7 A1:4 A3:6 CLK0 A2:1 A0:6 A1:1 A3:7 A3:2 A2:4 A0:3 A1:0 A1:5 A3:3 A2:5 A2:0 S_C3/2 E3/2 Channel E2:0 E2:5 E3:3 C3:5 C3:0 C2:3 E2:4 E3:2 E3:7 C3:1 C2:6 E2:1 Q3 E3:6 C3:4 C2:7 C2:2 E2:2 E2:7 E3:4 C3:6 CLK3 C2:1 E2:6 E3:1 C3:7 C3:2 C2:4 E2:3 E3:0 E3:5 C3:3 C2:5 C2:0 Doc. Rev. 1.11 APPENDIX E – B_DDR3D_2D Support Pinout, DIMM Slot 0 Samtec Pin Coax Pin 15 29 25 28 24 21 19 20 16 12 10 11 9 6 4 5 3 46 32 36 33 37 40 J15-6 J15-10 J15-9 J16-11 J16-12 J15-8 J15-7 J16-13 J16-14 J16-15 J16-16 J15-5 J15-4 J16-17 J16-18 J15-3 J15-2 J16-6 J16-10 J16-9 J15-11 J15-12 J16-8 TLA Channe l CK1 A1:7 A1:6 A1:5 A1:4 A1:3 A1:2 A1:1 A1:0 A0:7 A0:6 A0:5 A0:4 A0:3 A0:2 A0:1 A0:0 CK0 A3:7 A3:6 A3:5 A3:4 A3:3 42 41 45 J16-7 J15-13 J15-14 A3:2 A3:1 A3:0 49 51 50 52 55 57 56 58 DDR3 Signal CB1 NC CB3 CB7 CB6 CB2 DQS8 DM8 CB5 CB4 DQ31 CB0 DQ27 DQ30 DM3 DQ26 DQS3 A15 TEST RESET# NC NC NC CKE1 CKE0 BA2 ERR_OUT J15-15 A2:7 # J15-16 A2:6 A11 J16-5 A2:5 A14 J16-4 A2:4 A12 J15-17 A2:3 A7 J15-18 A2:2 A5 J16-3 A2:1 A9 J16-2 A2:0 A8 2X Probe Connection used with B_DDR3D_2D software M_A3/2 A1/0 DDR3THIN-MN-XXX 80 Samte c Pin 46 32 36 33 37 40 42 41 45 49 51 50 52 55 57 56 58 15 29 25 28 24 21 Coax Pin J16-6 J16-10 J16-9 J15-11 J15-12 J16-8 J16-7 J15-13 J15-14 J15-15 J15-16 J16-5 J16-4 J15-17 J15-18 J16-3 J16-2 J15-6 J15-10 J15-9 J16-11 J16-12 J15-8 TLA Channe l CK3+ C3:7 C3:6 C3:5 C3:4 C3:3 C3:2 C3:1 C3:0 C2:7 C2:6 C2:5 C2:4 C2:3 C2:2 C2:1 C2:0 Q1+ C1:7 C1:6 C1:5 C1:4 C1:3 19 20 16 J15-7 J16-13 J16-14 C1:2 C1:1 C1:0 12 J16-15 C0:7 10 J16-16 C0:6 11 J15-5 C0:5 9 J15-4 C0:4 6 J16-17 C0:3 4 J16-18 C0:2 5 J15-3 C0:1 3 J15-2 C0:0 1X Probe Connection used with B_DDR3D_2D software M_C3/2 C1/0 DDR3 Signal A13 BA1 RAS# CAS# S1# S0# ODT0 ODT1 S2# DQ32 DQ33 S3# DQ36 DQS4 NC DQ37 DM4 A2 WE# BA0 A0 CK0 A10 PAR_I N A1 A3 NC NC A4 NC A6 NC NC NC Doc. Rev. 1.11 APPENDIX E – B_DDR3D_2D Support Pinout, DIMM Slot 0 (Cont’d.) Coax TLA DDR3 Samtec Pin Channel Signal Pin 15 J15-6 CK1 DQS5 29 J15-10 A1:7 DQ49 25 J15-9 A1:6 DQ48 28 J16-11 A1:5 DQ52 24 J16-12 A1:4 DQ47 21 J15-8 A1:3 DQ43 19 J15-7 A1:2 DQ42 20 J16-13 A1:1 DQ46 16 J16-14 A1:0 DM5 12 J16-15 A0:7 DQ45 10 J16-16 A0:6 DQ44 11 J15-5 A0:5 DQ41 9 J15-4 A0:4 DQ40 6 J16-17 A0:3 DQ39 4 J16-18 A0:2 DQ38 5 J15-3 A0:1 DQ35 3 J15-2 A0:0 DQ34 46 J16-6 CK0 DQ60 32 J16-10 A3:7 DQ53 36 J16-9 A3:6 DM6 33 J15-11 A3:5 DQS6 37 J15-12 A3:4 DQ50 40 J16-8 A3:3 DQ54 42 J16-7 A3:2 DQ55 41 J15-13 A3:1 DQ51 45 J15-14 A3:0 DQ56 49 J15-15 A2:7 DQ57 51 J15-16 A2:6 DQS7 50 J16-5 A2:5 DQ61 52 J16-4 A2:4 DM7 55 J15-17 A2:3 DQ58 57 J15-18 A2:2 DQ59 56 J16-3 A2:1 DQ62 58 J16-2 A2:0 DQ63 2X Probe Connection used with B_DDR3D_2D software S_A3/2 A1/0 DDR3THIN-MN-XXX 81 Coax TLA DDR3 Samtec Pin Channel Signal Pin 46 J15-6 Q3 DQ3 32 J15-10 E3:7 DQ10 36 J15-9 E3:6 DQS1 33 J16-11 E3:5 DM1 37 J16-12 E3:4 DQ13 40 J15-8 E3:3 DQ9 42 J15-7 E3:2 DQ8 41 J16-13 E3:1 DQ12 45 J16-14 E3:0 DQ7 49 J16-15 E2:7 DQ6 51 J16-16 E2:6 DM0 50 J15-5 E2:5 DQ2 52 J15-4 E2:4 DQS0 55 J16-17 E2:3 DQ5 57 J16-18 E2:2 DQ4 56 J15-3 E2:1 DQ1 58 J15-2 E2:0 DQ0 15 J16-6 CK3 DM2 29 J16-10 C3:7 DQ14 25 J16-9 C3:6 DQ15 28 J15-11 C3:5 DQ11 24 J15-12 C3:4 DQ16 21 J16-8 C3:3 DQ20 19 J16-7 C3:2 DQ21 20 J15-13 C3:1 DQ17 16 J15-14 C3:0 DQS2 12 J15-15 C2:7 DQ18 10 J15-16 C2:6 DQ19 11 J16-5 C2:5 DQ22 9 J16-4 C2:4 DQ23 6 J15-17 C2:3 DQ24 4 J15-18 C2:2 DQ25 5 J16-3 C2:1 DQ28 3 J16-2 C2:0 DQ29 2X Probe Connection used with B_DDR3D_2D software S_C3/2 E3/2 Doc. Rev. 1.11 APPENDIX F – B_DDR3_2G Support Pinout, DIMM Slot 0 Auxiliary Signals Samte c Pin Coax Pin TLA Channe l 46 32 36 J16-6 J16-10 J16-9 E3:7 E3:6 33 J15-11 E3:5 37 40 42 41 45 49 J15-12 J16-8 J16-7 J15-13 J15-14 J15-15 E3:4 E3:3 E3:2 E3:1 E3:0 E2:7 51 50 52 55 J15-16 J16-5 J16-4 J15-17 E2:6 E2:5 E2:4 E2:3 57 56 58 J15-18 J16-3 J16-2 E2:2 E2:1 E2:0 15 J15-6 Q2 29 25 28 24 21 19 20 16 12 10 11 J15-10 J15-9 J16-11 J16-12 J15-8 J15-7 J16-13 J16-14 J16-15 J16-16 J15-5 E1:7 E1:6 E1:5 E1:4 E1:3 E1:2 E1:1 E1:0 E0:7 E0:6 E0:5 9 6 4 5 J15-4 J16-17 J16-18 J15-3 E0:4 E0:3 E0:2 E0:1 3 J15-2 E0:0 DDR3 Signal NC NC NC cCLKE1 LEAD-6 cCLKE0 LEAD-5 NC NC LEAD-4 LEAD-3 NC cS1# LEAD-2 NC NC NC cS0# LEAD-1 NC NC bCLKE1 LEAD10 bCLKE0 LEAD-7 LEAD-8 NC NC NC LEAD-9 NC NC NC NC NC bS1# LEAD11 NC NC NC bS0# LEAD12 Optional Flying Lead Probe Connection used with B_DDR3D_2G software M_E3/2 E1/0 DDR3THIN-MN-XXX 82 Doc. Rev. 1.11 DDR3THIN-MN-XXX 83 Doc. Rev. 1.11 APPENDIX G – B_DDR3D_3A Support Pinout, DIMM Slot 1 Samte c Pin Coax Pin 15 29 25 28 24 21 19 20 16 12 10 11 9 6 4 5 3 46 32 36 33 37 40 42 41 45 J15-6 J15-10 J15-9 J16-11 J16-12 J15-8 J15-7 J16-13 J16-14 J16-15 J16-16 J15-5 J15-4 J16-17 J16-18 J15-3 J15-2 J16-6 J16-10 J16-9 J15-11 J15-12 J16-8 J16-7 J15-13 J15-14 TLA Channe l Q0+ D3:7 D3:6 D3:5 D3:4 D3:3 D3:2 D3:1 D3:0 D2:7 D2:6 D2:5 D2:4 D2:3 D2:2 D2:1 D2:0 CK0+ A3:7 A3:6 A3:5 A3:4 A3:3 A3:2 A3:1 A3:0 DDR3 Signal CB1 NC CB3 CB7 CB6 CB2 DQS8 DM8 CB5 CB4 DQ31 CB0 DQ27 DQ30 DM3 DQ26 DQS3 A15 TEST RESET# NC NC NC CKE1 CKE0 BA2 ERR_OUT 49 J15-15 A2:7 # 51 J15-16 A2:6 A11 50 J16-5 A2:5 A14 52 J16-4 A2:4 A12 55 J15-17 A2:3 A7 57 J15-18 A2:2 A5 56 J16-3 A2:1 A9 58 J16-2 A2:0 A8 2X Probe Connection used with B_DDR3D_2D software M_A3/2 A1/0 (S2_A3/2 D3/2 Logic Analyzer Probe) DDR3THIN-MN-XXX 84 Samte c Pin 46 32 36 33 37 40 42 41 45 49 51 50 52 55 57 56 58 15 29 25 28 24 21 19 20 16 Coax Pin J16-6 J16-10 J16-9 J15-11 J15-12 J16-8 J16-7 J15-13 J15-14 J15-15 J15-16 J16-5 J16-4 J15-17 J15-18 J16-3 J16-2 J15-6 J15-10 J15-9 J16-11 J16-12 J15-8 J15-7 J16-13 J16-14 TLA Channe l CK3+ C3:7 C3:6 C3:5 C3:4 C3:3 C3:2 C3:1 C3:0 C2:7 C2:6 C2:5 C2:4 C2:3 C2:2 C2:1 C2:0 Q1+ C1:7 C1:6 C1:5 C1:4 C1:3 C1:2 C1:1 C1:0 DDR3 Signal A13 BA1 RAS# CAS# S1# S0# ODT0 ODT1 S2# DQ32 DQ33 S3# DQ36 DQS4 NC DQ37 DM4 A2 WE# BA0 A0 CK0 A10 PAR_IN A1 A3 12 J16-15 C0:7 NC 10 J16-16 C0:6 NC 11 J15-5 C0:5 A4 9 J15-4 C0:4 NC 6 J16-17 C0:3 A6 4 J16-18 C0:2 NC 5 J15-3 C0:1 NC 3 J15-2 C0:0 NC 1X Probe Connection used with B_DDR3D_2D software M_C3/2 C1/0 (S2_C3/2/1/0 Logic Analyzer Probe) Doc. Rev. 1.11 APPENDIX G – B_DDR3D_3A Support Pinout, DIMM Slot 1 (cont’d.) Samtec Pin DDR 3 Signa l 15 J15-6 CK2+ DQS5 29 J15-10 D1:7 DQ49 25 J15-9 D1:6 DQ48 28 J16-11 D1:5 DQ52 24 J16-12 D1:4 DQ47 21 J15-8 D1:3 DQ43 19 J15-7 D1:2 DQ42 20 J16-13 D1:1 DQ46 16 J16-14 D1:0 DM5 12 J16-15 D0:7 DQ45 10 J16-16 D0:6 DQ44 11 J15-5 D0:5 DQ41 9 J15-4 D0:4 DQ40 6 J16-17 D0:3 DQ39 4 J16-18 D0:2 DQ38 5 J15-3 D0:1 DQ35 3 J15-2 D0:0 DQ34 46 J16-6 CK1+ DQ60 32 J16-10 A1:7 DQ53 36 J16-9 A1:6 DM6 33 J15-11 A1:5 DQS6 37 J15-12 A1:4 DQ50 40 J16-8 A1:3 DQ54 42 J16-7 A1:2 DQ55 41 J15-13 A1:1 DQ51 45 J15-14 A1:0 DQ56 49 J15-15 A0:7 DQ57 51 J15-16 A0:6 DQS7 50 J16-5 A0:5 DQ61 52 J16-4 A0:4 DM7 55 J15-17 A0:3 DQ58 57 J15-18 A0:2 DQ59 56 J16-3 A0:1 DQ62 58 J16-2 A0:0 DQ63 2X Probe Connection used with B_DDR3D_2D software S_A3/2 A1/0 (S2_A1/0 D1/0 Logic Analyzer Probe) DDR3THIN-MN-XXX Coax Pin TLA Channe l 85 Samte c Pin Coax Pin TLA Channe l DDR 3 Signa l 15 J15-6 Q2+ DQ3 29 J15-10 E1:7 DQ10 25 J15-9 E1:6 DQS1 28 J16-11 E1:5 DM1 24 J16-12 E1:4 DQ13 21 J15-8 E1:3 DQ9 19 J15-7 E1:2 DQ8 20 J16-13 E1:1 DQ12 16 J16-14 E1:0 DQ7 12 J16-15 E0:7 DQ6 10 J16-16 E0:6 DM0 11 J15-5 E0:5 DQ2 9 J15-4 E0:4 DQS0 6 J16-17 E0:3 DQ5 4 J16-18 E0:2 DQ4 5 J15-3 E0:1 DQ1 3 J15-2 E0:0 DQ0 46 J16-6 Q3+ DM2 32 J16-10 E3:7 DQ14 36 J16-9 E3:6 DQ15 33 J15-11 E3:5 DQ11 37 J15-12 E3:4 DQ16 40 J16-8 E3:3 DQ20 42 J16-7 E3:2 DQ21 41 J15-13 E3:1 DQ17 45 J15-14 E3:0 DQS2 49 J15-15 E2:7 DQ18 51 J15-16 E2:6 DQ19 50 J16-5 E2:5 DQ22 52 J16-4 E2:4 DQ23 55 J15-17 E2:3 DQ24 57 J15-18 E2:2 DQ25 56 J16-3 E2:1 DQ28 58 J16-2 E2:0 DQ29 2X Probe Connection used with B_DDR3D_2D software S_C3/2 E3/2 (S2_E3/2/1/0 Logic Analyzer Probe) Doc. Rev. 1.11 APPENDIX H – Data Group / Data Byte / Strobe Cross-Reference 32-bit Data Group RdADatHi RdADatLo WrADatHi WrADatLo RdBDatHi RdBDatLo WrBDatHi WrBDatLo 8-bit Data Group RdADatB7 RdADatB6 RdADatB5 RdADatB4 RdADatB3 RdADatB2 RdADatB1 RdADatB0 WrADatB7 WrADatB6 WrADatB5 WrADatB4 WrADatB3 WrADatB2 WrADatB1 WrADatB0 RdBDatB7 RdBDatB6 RdBDatB5 RdBDatB4 RdBDatB3 RdBDatB2 RdBDatB1 RdBDatB0 WrBDatB7 WrBDatB6 WrBDatB5 WrBDatB4 WrBDatB3 WrBDatB2 WrBDatB1 WrBDatB0 Strobe DQS7 DQS6 DQS5 DQS4 DQS3 DQS2 DQS1 DQS0 DQS7 DQS6 DQS5 DQS4 DQS3 DQS2 DQS1 DQS0 DQS7 DQS6 DQS5 DQS4 DQS3 DQS2 DQS1 DQS0 DQS7 DQS6 DQS5 DQS4 DQS3 DQS2 DQS1 DQS0 Data Bits 63,62,61,60,59,58,57,56 55,54,53,52,51,50,49,48 47,46,45,44,43,42,41,40 39,38,37,36,35,34,33,32 31,30,29,28,27,26,25,24 23,22,21,20,19,18,17,16 15,14,13,12,11,10,9,8 7,6,5,4,3,2,1,0 63,62,61,60,59,58,57,56 55,54,53,52,51,50,49,48 47,46,45,44,43,42,41,40 39,38,37,36,35,34,33,32 31,30,29,28,27,26,25,24 23,22,21,20,19,18,17,16 15,14,13,12,11,10,9,8 7,6,5,4,3,2,1,0 63,62,61,60,59,58,57,56 55,54,53,52,51,50,49,48 47,46,45,44,43,42,41,40 39,38,37,36,35,34,33,32 31,30,29,28,27,26,25,24 23,22,21,20,19,18,17,16 15,14,13,12,11,10,9,8 7,6,5,4,3,2,1,0 63,62,61,60,59,58,57,56 55,54,53,52,51,50,49,48 47,46,45,44,43,42,41,40 39,38,37,36,35,34,33,32 31,30,29,28,27,26,25,24 23,22,21,20,19,18,17,16 15,14,13,12,11,10,9,8 7,6,5,4,3,2,1,0 B_DDR3D_XX Groups/Bytes/Strobes Cross Reference DDR3THIN-MN-XXX 86 Doc. Rev. 1.11 APPENDIX I – NEX-DDR3INTR-THIN Silkscreen Front Silk-screen DDR3THIN-MN-XXX 87 Doc. Rev. 1.11 APPENDIX J – Keep out area DDR3THIN-MN-XXX 88 Doc. Rev. 1.11 APPENDIX K – Simulation Model Double this if you are using two Interposers on the same memory channel DDR3THIN-MN-XXX 89 Doc. Rev. 1.11 APPENDIX L - References JEDEC PC3-6400/PC3-8500-10660 DDR3 SDRAM Unbuffered DIMM Design Specification Revision 0.1 March 20, 2006. Tektronix TLA7000 Series Installation Manual Tek part number 071-1747-03 Tektronix TLA7000 Series Technical Reference Manual Tektronix part number 071-1764-00 Nexus Low Profile Distributed Probe Manual— Part number LowProfileProbes-MN-XXX JEDEC DDR3 SDRAM Standard JESD79-3 June 2007 DDR3THIN-MN-XXX 90 Doc. Rev. 1.11 APPENDIX M - Support About Nexus Technology, Inc. Established in 1991, Nexus Technology, Inc. is dedicated to developing, marketing, and supporting Bus Analysis applications for Tektronix Logic Analyzers. We can be reached at: Nexus Technology, Inc. P.O. Box 6575 Nashua, NH 03063 TEL: 877-595-8116 FAX: 877-595-8118 Web site: http://www.nexustechnology.com Support Contact Information Technical Support General Information Quote Requests techsupport@nexustechnology.com support@nexustechnology.com quotes@nexustechnology.com We will try to respond within one business day. If Problems Are Found Document the problem and e-mail the information to us. If at all possible please forward a Saved System Setup (with acquired data) that shows the problem. Please do not send a text listing alone as that does not contain enough data for analysis. To prevent corruption during the mailing process it is strongly suggested that the Setup be zipped before transmission. DDR3THIN-MN-XXX 91 Doc. Rev. 1.11
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