Intel(R) 64 And IA 32 Architectures Software Developer's Manual, Volume 2B 253667 Intel64 Archtectures Developers Manual Insruction Set Reference, N Z
253667-Intel64%20and%20IA-32%20Archtectures%20Software%20Developers%20Manual-Volume%202B-Insruction%20Set%20Reference%2C%20N-Z
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- Chapter 4 Instruction Set Reference, N-Z
- 4.1 Imm8 Control Byte Operation for PCMPESTRI / PCMPESTRM / PCMPISTRI / PCMPISTRM
- 4.2 Instructions (N-Z)
- NEG-Two's Complement Negation
- NOP-No Operation
- NOT-One's Complement Negation
- OR-Logical Inclusive OR
- ORPD-Bitwise Logical OR of Double-Precision Floating-Point Values
- ORPS-Bitwise Logical OR of Single-Precision Floating-Point Values
- OUT-Output to Port
- OUTS/OUTSB/OUTSW/OUTSD-Output String to Port
- PABSB/PABSW/PABSD - Packed Absolute Value
- PACKSSWB/PACKSSDW-Pack with Signed Saturation
- PACKUSDW - Pack with Unsigned Saturation
- PACKUSWB-Pack with Unsigned Saturation
- PADDB/PADDW/PADDD-Add Packed Integers
- PADDQ-Add Packed Quadword Integers
- PADDSB/PADDSW-Add Packed Signed Integers with Signed Saturation
- PADDUSB/PADDUSW-Add Packed Unsigned Integers with Unsigned Saturation
- PALIGNR - Packed Align Right
- PAND-Logical AND
- PANDN-Logical AND NOT
- PAUSE-Spin Loop Hint
- PAVGB/PAVGW-Average Packed Integers
- PBLENDVB - Variable Blend Packed Bytes
- PBLENDW - Blend Packed Words
- PCLMULQDQ - Carry-Less Multiplication Quadword
- PCMPEQB/PCMPEQW/PCMPEQD- Compare Packed Data for Equal
- PCMPEQQ - Compare Packed Qword Data for Equal
- PCMPESTRI - Packed Compare Explicit Length Strings, Return Index
- PCMPESTRM - Packed Compare Explicit Length Strings, Return Mask
- PCMPGTB/PCMPGTW/PCMPGTD-Compare Packed Signed Integers for Greater Than
- PCMPGTQ - Compare Packed Data for Greater Than
- PCMPISTRI - Packed Compare Implicit Length Strings, Return Index
- PCMPISTRM - Packed Compare Implicit Length Strings, Return Mask
- VPERMILPD - Permute Double-Precision Floating-Point Values
- VPERMILPS - Permute Single-Precision Floating-Point Values
- VPERM2F128 - Permute Floating-Point Values
- PEXTRB/PEXTRD/PEXTRQ - Extract Byte/Dword/Qword
- PEXTRW-Extract Word
- PHADDW/PHADDD - Packed Horizontal Add
- PHADDSW - Packed Horizontal Add and Saturate
- PHMINPOSUW - Packed Horizontal Word Minimum
- PHSUBW/PHSUBD - Packed Horizontal Subtract
- PHSUBSW - Packed Horizontal Subtract and Saturate
- PINSRB/PINSRD/PINSRQ - Insert Byte/Dword/Qword
- PINSRW-Insert Word
- PMADDUBSW - Multiply and Add Packed Signed and Unsigned Bytes
- PMADDWD-Multiply and Add Packed Integers
- PMAXSB - Maximum of Packed Signed Byte Integers
- PMAXSD - Maximum of Packed Signed Dword Integers
- PMAXSW-Maximum of Packed Signed Word Integers
- PMAXUB-Maximum of Packed Unsigned Byte Integers
- PMAXUD - Maximum of Packed Unsigned Dword Integers
- PMAXUW - Maximum of Packed Word Integers
- PMINSB - Minimum of Packed Signed Byte Integers
- PMINSD - Minimum of Packed Dword Integers
- PMINSW-Minimum of Packed Signed Word Integers
- PMINUB-Minimum of Packed Unsigned Byte Integers
- PMINUD - Minimum of Packed Dword Integers
- PMINUW - Minimum of Packed Word Integers
- PMOVMSKB-Move Byte Mask
- PMOVSX - Packed Move with Sign Extend
- PMOVZX - Packed Move with Zero Extend
- PMULDQ - Multiply Packed Signed Dword Integers
- PMULHRSW - Packed Multiply High with Round and Scale
- PMULHUW-Multiply Packed Unsigned Integers and Store High Result
- PMULHW-Multiply Packed Signed Integers and Store High Result
- PMULLD - Multiply Packed Signed Dword Integers and Store Low Result
- PMULLW-Multiply Packed Signed Integers and Store Low Result
- PMULUDQ-Multiply Packed Unsigned Doubleword Integers
- POP-Pop a Value from the Stack
- POPA/POPAD-Pop All General-Purpose Registers
- POPCNT - Return the Count of Number of Bits Set to 1
- POPF/POPFD/POPFQ-Pop Stack into EFLAGS Register
- POR-Bitwise Logical OR
- PREFETCHh-Prefetch Data Into Caches
- PSADBW-Compute Sum of Absolute Differences
- PSHUFB - Packed Shuffle Bytes
- PSHUFD-Shuffle Packed Doublewords
- PSHUFHW-Shuffle Packed High Words
- PSHUFLW-Shuffle Packed Low Words
- PSHUFW-Shuffle Packed Words
- PSIGNB/PSIGNW/PSIGND - Packed SIGN
- PSLLDQ-Shift Double Quadword Left Logical
- PSLLW/PSLLD/PSLLQ-Shift Packed Data Left Logical
- PSRAW/PSRAD-Shift Packed Data Right Arithmetic
- PSRLDQ-Shift Double Quadword Right Logical
- PSRLW/PSRLD/PSRLQ-Shift Packed Data Right Logical
- PSUBB/PSUBW/PSUBD-Subtract Packed Integers
- PSUBQ-Subtract Packed Quadword Integers
- PSUBSB/PSUBSW-Subtract Packed Signed Integers with Signed Saturation
- PSUBUSB/PSUBUSW-Subtract Packed Unsigned Integers with Unsigned Saturation
- PTEST- Logical Compare
- PUNPCKHBW/PUNPCKHWD/PUNPCKHDQ/PUNPCKHQDQ- Unpack High Data
- PUNPCKLBW/PUNPCKLWD/PUNPCKLDQ/PUNPCKLQDQ- Unpack Low Data
- PUSH-Push Word, Doubleword or Quadword Onto the Stack
- PUSHA/PUSHAD-Push All General-Purpose Registers
- PUSHF/PUSHFD-Push EFLAGS Register onto the Stack
- PXOR-Logical Exclusive OR
- RCL/RCR/ROL/ROR--Rotate
- RCPPS-Compute Reciprocals of Packed Single-Precision Floating- Point Values
- RCPSS-Compute Reciprocal of Scalar Single-Precision Floating-Point Values
- RDMSR-Read from Model Specific Register
- RDPMC-Read Performance-Monitoring Counters
- RDTSC-Read Time-Stamp Counter
- RDTSCP-Read Time-Stamp Counter and Processor ID
- REP/REPE/REPZ/REPNE/REPNZ-Repeat String Operation Prefix
- RET-Return from Procedure
- ROUNDPD - Round Packed Double Precision Floating-Point Values
- ROUNDPS - Round Packed Single Precision Floating-Point Values
- ROUNDSD - Round Scalar Double Precision Floating-Point Values
- ROUNDSS - Round Scalar Single Precision Floating-Point Values
- RSM-Resume from System Management Mode
- RSQRTPS-Compute Reciprocals of Square Roots of Packed Single- Precision Floating-Point Values
- RSQRTSS-Compute Reciprocal of Square Root of Scalar Single- Precision Floating-Point Value
- SAHF-Store AH into Flags
- SAL/SAR/SHL/SHR-Shift
- SBB-Integer Subtraction with Borrow
- SCAS/SCASB/SCASW/SCASD-Scan String
- SETcc-Set Byte on Condition
- SFENCE-Store Fence
- SGDT-Store Global Descriptor Table Register
- SHLD-Double Precision Shift Left
- SHRD-Double Precision Shift Right
- SHUFPD-Shuffle Packed Double-Precision Floating-Point Values
- SHUFPS-Shuffle Packed Single-Precision Floating-Point Values
- SIDT-Store Interrupt Descriptor Table Register
- SLDT-Store Local Descriptor Table Register
- SMSW-Store Machine Status Word
- SQRTPD-Compute Square Roots of Packed Double-Precision Floating- Point Values
- SQRTPS-Compute Square Roots of Packed Single-Precision Floating- Point Values
- SQRTSD-Compute Square Root of Scalar Double-Precision Floating- Point Value
- SQRTSS-Compute Square Root of Scalar Single-Precision Floating- Point Value
- VSTMXCSR-Store MXCSR Register State
- STC-Set Carry Flag
- STD-Set Direction Flag
- STI-Set Interrupt Flag
- STMXCSR-Store MXCSR Register State
- STOS/STOSB/STOSW/STOSD/STOSQ-Store String
- STR-Store Task Register
- SUB-Subtract
- SUBPD-Subtract Packed Double-Precision Floating-Point Values
- SUBPS-Subtract Packed Single-Precision Floating-Point Values
- SUBSD-Subtract Scalar Double-Precision Floating-Point Values
- SUBSS-Subtract Scalar Single-Precision Floating-Point Values
- SWAPGS-Swap GS Base Register
- SYSCALL-Fast System Call
- SYSENTER-Fast System Call
- SYSEXIT-Fast Return from Fast System Call
- SYSRET-Return From Fast System Call
- TEST-Logical Compare
- VTESTPD/VTESTPS-Packed Bit Test
- UCOMISD-Unordered Compare Scalar Double-Precision Floating-Point Values and Set EFLAGS
- UCOMISS-Unordered Compare Scalar Single-Precision Floating-Point Values and Set EFLAGS
- UD2-Undefined Instruction
- UNPCKHPD-Unpack and Interleave High Packed Double-Precision Floating-Point Values
- UNPCKHPS-Unpack and Interleave High Packed Single-Precision Floating-Point Values
- UNPCKLPD-Unpack and Interleave Low Packed Double-Precision Floating-Point Values
- UNPCKLPS-Unpack and Interleave Low Packed Single-Precision Floating-Point Values
- VERR/VERW-Verify a Segment for Reading or Writing
- WAIT/FWAIT-Wait
- WBINVD-Write Back and Invalidate Cache
- WRMSR-Write to Model Specific Register
- XADD-Exchange and Add
- XCHG-Exchange Register/Memory with Register
- XGETBV-Get Value of Extended Control Register
- XLAT/XLATB-Table Look-up Translation
- XOR-Logical Exclusive OR
- XORPD-Bitwise Logical XOR for Double-Precision Floating-Point Values
- XORPS-Bitwise Logical XOR for Single-Precision Floating-Point Values
- XRSTOR-Restore Processor Extended States
- XSAVE-Save Processor Extended States
- XSAVEOPT-Save Processor Extended States Optimized
- XSETBV-Set Extended Control Register
- VZEROALL-Zero All YMM Registers
- VZEROUPPER-Zero Upper Bits of YMM Registers
- Chapter 5 VMX Instruction Reference
- 5.1 Overview
- 5.2 Conventions
- 5.3 VMX Instructions
- INVEPT- Invalidate Translations Derived from EPT
- INVVPID- Invalidate Translations Based on VPID
- VMCALL-Call to VM Monitor
- VMCLEAR-Clear Virtual-Machine Control Structure
- VMLAUNCH/VMRESUME-Launch/Resume Virtual Machine
- VMPTRLD-Load Pointer to Virtual-Machine Control Structure
- VMPTRST-Store Pointer to Virtual-Machine Control Structure
- VMREAD-Read Field from Virtual-Machine Control Structure
- VMRESUME-Resume Virtual Machine
- VMWRITE-Write Field to Virtual-Machine Control Structure
- VMXOFF-Leave VMX Operation
- VMXON-Enter VMX Operation
- 5.4 VM Instruction Error Numbers
- Chapter 6 Safer Mode Extensions Reference
- 6.1 Overview
- 6.2 SMX Functionality
- 6.3 GETSEC Leaf Functions
- GETSEC[CAPABILITIES] - Report the SMX Capabilities
- GETSEC[ENTERACCS] - Execute Authenticated Chipset Code
- GETSEC[EXITAC]-Exit Authenticated Code Execution Mode
- GETSEC[SENTER]-Enter a Measured Environment
- GETSEC[SEXIT]-Exit Measured Environment
- GETSEC[PARAMETERS]-Report the SMX Parameters
- GETSEC[SMCTRL]-SMX Mode Control
- GETSEC[WAKEUP]-Wake up sleeping processors in measured environment
- Appendix A Opcode Map
- A.1 Using Opcode Tables
- A.2 Key to Abbreviations
- A.3 One, Two, and THREE-Byte Opcode Maps
- A.4 Opcode Extensions For One-Byte And Two- byte Opcodes
- A.5 Escape Opcode Instructions
- A.5.1 Opcode Look-up Examples for Escape Instruction Opcodes
- A.5.2 Escape Opcode Instruction Tables
- A.5.2.1 Escape Opcodes with D8 as First Byte
- A.5.2.2 Escape Opcodes with D9 as First Byte
- A.5.2.3 Escape Opcodes with DA as First Byte
- A.5.2.4 Escape Opcodes with DB as First Byte
- A.5.2.5 Escape Opcodes with DC as First Byte
- A.5.2.6 Escape Opcodes with DD as First Byte
- A.5.2.7 Escape Opcodes with DE as First Byte
- A.5.2.8 Escape Opcodes with DF As First Byte
- Appendix B Instruction Formats and Encodings
- B.1 Machine Instruction Format
- B.2 General-Purpose Instruction Formats and Encodings for Non-64-Bit Modes
- B.3 Pentium® Processor Family Instruction Formats and Encodings
- B.4 64-bit Mode Instruction Encodings for SIMD Instruction Extensions
- B.5 MMX Instruction Formats and Encodings
- B.6 Processor ExtendeD State INstruction Formats and EncodIngs
- B.7 P6 Family INstruction Formats and Encodings
- B.8 SSE Instruction Formats and Encodings
- B.9 SSE2 Instruction Formats and Encodings
- B.10 SSE3 Formats and Encodings Table
- B.11 SSsE3 Formats and Encoding Table
- B.12 AESNI and PCLMULQDQ INstruction Formats and Encodings
- B.13 Special Encodings for 64-Bit Mode
- B.14 SSE4.1 Formats and Encoding Table
- B.15 SSE4.2 Formats and Encoding Table
- B.16 Floating-Point Instruction Formats and Encodings
- B.17 VMX Instructions
- B.18 SMX Instructions
- Appendix C Intel® C/C++ Compiler Intrinsics and Functional Equivalents