FPGA Surevyor III XC3S200 Board_Manual 3HA05 2.FPGA XC3S200F F4 Board Manual
FPGA_Surevyor-III_XC3S200F_F4_Board_Manual
3HA05-2.FPGA_Surevyor-III_XC3S200F_F4_Board_Manual
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FPGA Surveyor-III XC3S200 Board Manual (Rev2.07/03/07) FPGA Surveyor-III XC3S200F FPGA Surveyor-III XC3S200F4 BoardManual APEX INSTRUMENT CO., LTD. 77/9 !"#$%&'()%*1 ,--$%&'()%* ./*01"2'$ 3/4145167( 7(5038'29%-:( 10900 ;8(.:0-2939-2084 .?7!@ : 0-2939-2084 77/9 SOI LADPRAO 1 , LADPRAO ROAD , JOMPOL , JATUJAK DISTRICT , BANGKOK THAILAND 10900 TEL. 0-2939-2084 FAX.0-2939-2084 1 FPGA Surveyor-III XC3S200 Board Manual (Rev2.07/03/07) FPGA Surveyor-III XC3S200 FPGA Surveyor-III XC3S200F FPGA Surveyor-III XC3S200F4 FPGA Logic Trainer 1 FPGA !""#$% 200,000 400,000 #&&' () Platform Flash PROM '*#+," -%$ #" Platform Flash PROM . " * JTAG & $ #-'$% 20,000 ! #! #/' "!""# "#/0 &&&!! 1(*. # # "00&& &", 1 2 $%, ' # ", (*3"&" 1 FPGA Surveyor-III XC3S200 !/&0", #! FPGA Surveyor-III XC3S200 #" • FPGA Spatan-3 XC3S200-4TQ144C (XC3S400-4TQ144C '* " F4) • Platform Flash PROM XCF01SVO20C (XCF02VO20C '* " F4) • 7 Segment 4 *# • DIP Switch 8 " • LED 3 $ 8 " 2 FPGA Surveyor-III XC3S200 Board Manual (Rev2.07/03/07) • LED 2 $ 8 " • Logic Switch ( Slide Switch ) 8 &" • Switch One-Shot 2 &" • Switch Bounce 2 &" • Switch Bounceless 2 &" • 6 Expansion ports ( 48 Bits I/O ) • Relay 220 V/3A 2 &" • Clock generator :1[100Hz 10[1KHz • Buzzer 1 &" • 25 MHz Oscillator ! FPGA & Spartan-3 XC3S200 )0 FPGA &# Spatan-3 !" !1 * "!"' RAM " 216Kbits &"!/ J " 12 ) " DCM # 4 ) '(*## "00&!! NO&""' )"(*# # "'"# 0P0Q# #/Q( )0!/&0 • !"" 200,000 #& • 18Kb block RAMs ' " 12 ) " 216K bits(' " 18 ) '* " F4) • 18x18 hardware multiplier ' " 12 )(' " 18 ) '* " F4) • Digital Clock Manager (DCM) ' " 4 ) • Digitally Controlled Impedance (DCI) 1.) 3 45 18Kb block RAM 18Kb block RAM * "!"'!"+"/ 200 Mhz ' " 12 ) Block RAM &)$' RAM *1 ROM * &"( 2 &( 3 2 , RAM Single Port 3 RAM Single Port , &g # Block RAM &) 3 FPGA Surveyor-III XC3S200 Board Manual (Rev2.07/03/07) 2.) 18x18 Hardware multiplier 18x18 hardware multiplier 3^_-`%(@&.*(@*01(:abcd%3(e1(a^/-%& 18x18 fg4 2hc6i$67jb@.c&0&60(a^8hk 4 2h1d%-*- 12 l5& (a^8hk 4 18x18 hardware multiplier 3.) Digital Clock Manager Digital Clock Manager (DCM) "!"'!3#)"##"#33/ h0# -%( )0' " 4 ) $1" DCM )"'(*## ",% # 1#$!"$&g ## -0&#Q #)" %!"' &*33/ h0##Q #*g *#& 33/h0##"-0!! -#33/ h0##-0&0#" $ '() &"#' 0 33/ h0#!"$&g&() Variable Clock #Q # &( DCM 3#j/ 5 5 3#j/," DCM • • • • • • DCM ' ( * & *!"$ ( Clock Divider ) "-%(*!"$&&#!"$0 &*"&", & !1 1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5, 5.5, 6, 6.5, 7, 7.5, 8, 9, 10, 11,12, 13, 14, 15, *1 16 &' !"$ (Clock Doubler ) "-%(*!"$&& 2 ,!"$0 & Digital Frequency Synthesizer ( DFS ) "-%$#'* (*!"$&&#.!/,!"$0 &" , M/D M = 2 $% 32 D = 1 $% 32 &" Fin = 25 MHz $&# Fout= 200 MHz ' 1# M=8 , D=1 " DFS '() ) " ##, , # -% &33/ h##",0 ) 10 [ 11 & *1 1 g &()"s!" --0 P0-- Delay-Locked Loop (DLL) "() #O3*#1 s( "(*#&&s&# Quadrant Phase Shift "1 s 90 , 180 270 w &' Fine Phase Shift "()( #1 s !" 1/ 256 ,!!"$ 4 FPGA Surveyor-III XC3S200 Board Manual (Rev2.07/03/07) 4.) Digitally Controlled Impedance (DCI) Digitally Controlled Impedance (DCI) ()x# 33/ ( PCB #!"!&&0 - * 3& FPGA Survayer-III XC3S200 6 6 f"(@&(5n- FPGA Survayer-III XC3S200 1. 5& 5K 1.1) 7-Segment (DIGIT 1 1 DIGIT4) 46*.c&0o$3!3*-3!732-4@ (7-Segment ) 86p0 4 9$67 :q" DIGIT1 [ DIGIT4 1rsl)38:-g:7%(c.7- (Scan)s-7%(.c&0 46*3$/f-46*.c&0o$86p0 4 9$67'()"2t 76-3'qk"^(r9#6&c%#c6ib%b O/P 1%7 FPGA ;hk 8 3c)-sl)cd%9(6fcn0 Data 3'qk".c&0o$ .$r"h7 4 3c)-sl)cd%9(6f.:;,&(n*2 (Common Cathode) /"0.4n$r9$67&60(%#$r3"h#&s-4%(%08hk 1 ; $677%(8d%0%-1r3^_&60-h:p q"1r8d%7%(cn046*3$/u^8hk9$67.(7.$)*8d%7%(3$q"7s9)9$67.(7.c&0o$ 1%7-6p-1v03^$hk#-u^cn046*3$//"09$678hkc"0.$)* 3$q"79$678hkc"0s9).c&0o$ .$r8d%9$67,6&u^1-:(f86p0 4 9$67 .$)*1v0*-7$6f2%3(gk28h9k $67.(7s92n.$r*-u^3(qk"#t 1r8d%s9) 5 FPGA Surveyor-III XC3S200 Board Manual (Rev2.07/03/07) oa)sl)2"039e-46*3$/4g&'()"276-;h/)".2)*n%7%(c6f3^$hk#-9$67s-7%(.c&0o$4)"08d%s9)3(e*7*n%8hk4%:-3(%1r2"0u&)86- !vk0; 86k*u^4%:-3(%1r2"0.#7u&)8hk^(r2%b 25 [ 30 :(6p04n"*g-%8h &60-6p-"#n%0-)"#:*(4)"0c.7-;sl):*%23(e*u2n-)"#7*n% 120 :(6p0 4n"*g-%8h ( 30 :(6p0 X 4 9$67 = 120 :(6p04n"*g-%8h ) 1v01r2"0u2n39e-7%(7(r'(gf/"046*.c&0o$ s-7%(.c&0o$-6p-9%74)"07%(s9)3!732-4@s&/"046*.c&0o$4g&u&)-6p-4)"0cn0c6ii%b$"1g7 w1x ;h&k )%-.";-&857 /%1r2h46*4)%-8%- R1-R8/-%& 100 ;"9@24n""-57(276f I/O /"0 FPGA 3'qk"1d%76&7(r.c.4n$r3!732-4@ s-cn*-8h/k %.:;,&(n*2 s-.4n$r9$67-6p-,)%4)"07%(s9)9$67s&4g&7e4)"0s9)/%:%;,&(n*2/"09$67-6-p 3^_-$"1g7 w0x .$r/"s9)c60374*n%46*.c&0o$3!3*3!732-4@ DIGIT2 .$r DIGIT1 9(q"c"046*c5&8)%#8%0/*%2q",a7""7.ff2%s9)2h7%(7$6f46*.c&0o$;%(925- 180 "0y% 3'qk"s9)15& (.) /"0 DIGIT2 .$r DIGIT1 /vp-u^"#an&)%-f-3'qk"^(r;#l-@s-7%(.c&03:(qk"092%# w : x (Colon) s-7%(8d%-%zg7% 9(q"7%(.c&03^_-"0y%s-0%-8hk37hk#*76f"5b9{a2g ) 11:39 *1 20o C .4n7%(.c&046*3$/4n%0t #60:0sl)c%#c6ii%b3&h#*76f c"046*.(7 #&,#/,#,, FPGA &1 " 7 & 1 #&,#/,#,, FPGA 7-Segment FPGA Pin a p4 b p2 c p1 d p141 e p140 f p137 g p135 dp () p132 DIGIT1 (Common1) p5 DIGIT2 (Common2) p6 DIGIT3 (Common3) p131 DIGIT4 (Common4) p130 7 " ." 7-Segment 6 FPGA Surveyor-III XC3S200 Board Manual (Rev2.07/03/07) 1.2 LED L M& 1.) LED monitor ZLED0-LED7) f"(@&8&$"0-hp2h LED 8 &*0 :q" LED1 [ LED8 ;n"/%:%;,& (Cathode) $07(%*-&@ .$r4n"/%.";-&3/)%76f/% "g-'543"%4@'54 (I/O) /"0 FPGA ;h46*4)%-8%-.ff3-43*g(@: ({%#s-^(r7"f&)*# R=470 ;"9@2 4 46*.#7"gc(r ) :q" RNET3 .$r RNET4 4n""-57(2"#an3'qk"1d%76&7(r.c ( ,/,33/( &0 High w1x LED ( ,/ &0 Low w0x LED *#33/, - LED &!"",% #! Duty Cycle , 33/, LED &#/%"g-'543"%4@'54 (I/O) /"0lg' FPGA &g & 2 " 8 & 2 ,33/, LED & #/%"g-'543"%4@'54 (I/O) /"0lg' FPGA LED FPGA Pin LED0 P35 LED1 P33 LED2 P32 LED3 P31 LED4 P30 LED5 P28 LED6 P27 LED7 P26 (a^8hk 8 *01(.c&0o$&)*# LED monitor 2.) Logic monitor ( MN0 1 MN7 ) LED $&"33/$ !1 High w1x, Low w0x High impedance wZx &", LED !"!(),33/, ) MN0 MN0 Pin 1 MN0 Pin 2 $ MN0 Pin 1 0# w1x MN0 Pin 2 0# w0x '(* MN0 " ( ## ," *1*#0#"# " () 33/1'(* $'* Logic Monitor ) ( ,/,33/( &0 High w1x ( ,/,33/( &0 Low w0x ," ( ,/ 33/ High impedance wZx *#33/, 33/- 7 FPGA Surveyor-III XC3S200 Board Manual (Rev2.07/03/07) ,"# '(**+ ,33/, &# FPGA ,&g & 4 ", Logic monitor 9 & 3 LED $ &g Logic Color High w1x Red Low w0x Green High impedance wZx Off Pulse Orange & 4 ,33/, LED & #/%"g-'543"%4@'54 (I/O) /"0lg' FPGA Bi-color LED FPGA pin MN0 MN1 MN2 MN3 MN4 MN5 MN6 MN7 P51 P50 P47 P46 P44 P41 P40 P36 9", Logic monitor 8 FPGA Surveyor-III XC3S200 Board Manual (Rev2.07/03/07) 1.4 K1- K6 &&33/"Q #&! !& K1-K6 1)1&33/#/Q #*1 33/,& 1 ! !& K1- K6 $## 33/ #"/ !%1 #O3*##" ,)'33/ ( Cross talk ) 1& *10 ,#! !& "'(*33/ #"( #j/"# # '(*##" ,)33/#0# 1 I/O * 3.3 "& ( ,/ I/O '* &+$,0 &0#()# 3.3 5 "&& &1 I/O 0 &()y 3.3 "& *#&#)1&#&&# Q # 5 "&' &- 3.3 "& # ) *1'* ss ) -&# 74HCxx *1 74ACxx -%*! .1 ""-* ()s& & 2 { 6 "& ) 74HC125 & ( #/ ss#0 s 3.3 "& 0 &,ss&#&& 5 "&%' &&"& / 220 *& #0 &1'## *,0 &(*#0 #" 10 mA 1x# (*0 &* &$ && 5 "�#&# TTL !!"& # *1/ 100 * 1#0# } 1 } (* &&&'#"&# CMOS #()!!"& '(*"' !"$#" &" #)1&&&#-&# TTL *1 CMOS #0 &, FPGA 10 ( #/ Input 5 "& g () CPLD &# XC9500XL ) XC9572XL ss I/O , CPLD 3.3 "& &$ 3/&& 5 "&,&&&&"& & ##, I/O &( 10 &"#)1&&&#-&# TTL *1 CMOS #0 &, FPGA #&&"& (Pulled up) Q( )0# #&"'#& Jumper J5 &"" &$ &##+(*$ J5 # #&33/ I/O ##! !& K1 { K6 $&#() !"$g *1&#x# ##" ,) x# (*#0!1 ,33/ Q( , PCB #+!" () (Flat Cable) '* '(*() , 40 !""33/!"#0 10 { 15 - &0& ( 1#*-1& !0"&" #"() )1&33/*"J0 # ,!0"&) & #(* I/O , FPGA Slow Slew Rate 133/#" ,) # ,33/( #/()( #0/".# 1#!/&0*1., 9 FPGA Surveyor-III XC3S200 Board Manual (Rev2.07/03/07) Transmission Line effect #0,% ( PCB "$%33/ ( ) " !1 !"", , PCB "#33//!"#0 (2/nS) x )"",% (Rise time) -%( #/ O/P , FPGA Fast slew rate )"",% / #" 1 nS " ( #/ Slow slew rate )"",% / 3 nS (2/nS) x 3 nS = 6 = 15 - &0& ( #/ "#" .# 1##0# ,33/ '(*"' .0 # #,1# Terminate ""0P* '*)0&# Spartan-3 Digitally Controlled Impedance (DCI) ( #)" #,O3*# ( #&33/#Q # $ Vcc ""#&&"#+, 0.1 uF 10nF &0*1&"#+ )0 (Chip capacitor) (#g ," Vcc #"#g #& &' (-%&" ") 1 Q #"1(* Vcc !/&0ssx AC 1 " #" #&,,! !& K1- K6 #,, FPGA & 5 4%(%08hk 5(%#$r3"h#&7%(4n"/%/"0:"-3-:34"(@ K1- K6 76f/%/"0 FPGA 10 FPGA Surveyor-III XC3S200 Board Manual (Rev2.07/03/07) 4%(%08hk 5(%#$r3"h#&7%(4n"/%/"0:"-3-:34"(@ K1- K6 76f/%/"0 FPGA (&) 4%(%08hk 5 (%#$r3"h#&7%(4n"/%/"0:"-3-:34"(@ K1- K6 76f/%/"0 FPGA (&) 11 FPGA Surveyor-III XC3S200 Board Manual (Rev2.07/03/07) 2. 56789:;<7==>6?;@?ABC 2.1 P 2h&g'c*g4l@ ( Dip Switch ) "h7 8 c*g4l@ ;^74g9%73$qk"-c*g8!@$0u^8hk OFF 1r8d%s9)u&)$"1g7 w1x (Active Low) .$r 9%73$qk"-c*g4!@/-vp u^8hk ON 1r8d%s9)u&)$"1g7 w0x 4%(%08hk 6 (%#$r3"h#&7%(4n"/%/"0 &g'c*g4l@ 76f/%/"0 FPGA (4n") DIP SWITCH FPGA Pin DIP1 P68 DIP 2 P63 DIP 3 P60 DIP 4 P59 DIP 5 P56 DIP 6 P55 DIP 7 P53 DIP 8 P52 2.2 Q &4 5L& Variable clock generator 8%0&)%-"g-'54f"(@&8"&$"0-hp2hc*g8!@7&4g&^$n"#&6f ( Push botton Switch ) "#an 6 46*:q" PB1 [ PB6 .$r Variable clock generator (VRCLK) ;sl)u"!h PIC16F676 3'h#046*3&h#* (%#$r3"h#&*01(.c&0&60(a^8hk 11 ;hk PB1 .$r PB2 1r3^_One-shot push button switch *1 "0-#&0(*33/&& 33/- 1 # !!"#", -)" High w1x !"#"0- *#+& " -#$#01"0- ##! PB3 .$r PB4 1r3^_- Bounce-less push button switch *1 "0-#&0(*&& 33/- 1 #!!"#",-)" High w1x #"!#"0&- # Low w0x 1"0&- -%33/- 33/* ( Square Wave ) 033/"- ( Bounce-less ) PB5.$rPB6 3^_- Bounce push button switch *1c*g8!@7&4g&^$n"#&6f((2&% ;hk PB1-PB6 1r4n""#an76f/%/"0 FPGA ;^74g9%7u2n2h7%(7&1r3^_-$"1g7 w1x .$r9%77&1r3^_-$"1g7 w0x 3-qk"01%72h46*4)%-8%- RNET1 4n"'a$"6'"#an Range selector of on board variable clock generator (J1) ()& )"!"$,33/ h0#lock ( )1 1 2 ) Low Frequency generator $ 2 )"!1 High Frequency ( )1 2 3 ) " #!"$ POT1 4%(%08hk 7 (%#$r3"h#&7%(4n"/%3/)%76f/%/"0 FPGA Pushutton CLK FPGA Pin PB1 OUT P8 PB2 OUT P10 PB3 OUT P11 PB4 OUT P12 PB5 P13 PB6 P14 VRCLK P7 12 FPGA Surveyor-III XC3S200 Board Manual (Rev2.07/03/07) (a^8hk 12 (%#$r3"h#&*01(c()%0'6$!@.$rClock 2.3 Q&& f"(@&8&$"0-hp#602h!":37e4cd%9(6f4g&46p0""c!g$3$34"(@ (Oscillator socket) s9)"h7 1 46* !vk0^74g1rsl)u"!h 3f"(@ 74AC04 !0& 25 Mhz &"& 330 * 1 #* &"#+ 15 pF ' " 2 &" -0& x ,, GCLK6 *1 p127 , FPGA $&# -0& #+(*$- 74AC04 &"" #+$(-0& 3.3 "&&# & &!"$ 1 Mhz $% 50 MHz &&1"( FPGA &# Spartan-3 Digital Clock Manager (DCM) " !"'!3#) "##"#33/ h0#( )0' " 4 ) ( *#/#+$() DCM )"!"$&# !"' &()-0&#Q #0&0 &( 2.4 Relay connector ( NO1, NO2 ) ,"&* ! +!, 1 2 (RLY1, RLY2), 3A 250V ' " 2 ) &' ! +!( #&0 (NO) "),, 1 2 &#, P125 P124 , FPGA &' -%() I/O "#, 1 3 , K1 ( Jumper &' * S) ( #/&#() 1 2 (*$ Jumper &' * O 2.5 JTAG connector *"&()&#" * JTAG Cable)() #,&" FPGA Flash PROM 2.6 Slide switch ( SW0 1 SW7 ) "0-1 ()x ,, CPLD $1 w1x $1 ,% w0x )1&# ,, FPGA ' Active Low ) # 1# R &#,, Slide switch ,# Vcc 13 FPGA Surveyor-III XC3S200 Board Manual (Rev2.07/03/07) 4%(%08hk 8 (%#$r3"h#&7%(4n"/% Slide switch 3/)%76f/%/"0 FPGA Slide switch FPGA Pin SW7 P15 SW6 P17 SW5 P18 SW4 P20 SW3 P21 SW2 P23 SW1 P24 SW0 P25 3 RS-232C & RS-232C ()- ICL3232 *1 MAX3232 13 #&,, p128 p129 14 13 & RS-232C 14 #&& RS-232C # FPGA 14 FPGA Surveyor-III XC3S200 Board Manual (Rev2.07/03/07) 4. Misc 4.1 DC Adaptor input jack *"&s1x (* #( #' &# & s# 7V [ 9V ," ( "# }+ # }- 4.2 Power switch "0-()s(*# 4.3 Power LED "( ,/ g s*1 4.4 JUMPER J2 Jumper &#PB5 PB6 ,# FPGA (1&' * S) "'* #,0 & " -%(*0# ) "#- CMOS" -%*1 # TTL , 0# w1x &*1" ,0 & " (" R=4.7-10k) 1!(* 0# w0x *1w1x #" #/#'* ,1() %,-% &#- CMOS &&,0 &,# Vcc *1 Ground *1&*1" 4.5 46*"#n%07%(;^(.7(23"%4@'54/"0 FPGA u?3$hp#0 Vcco /"0f"(@&-hp3^_- 3.3V &60-6p- I/O 86p092&1r3^_-(rff 3.3V38n%-6p- !vk0c%2%(,3$q"7 I/Ou&)3'h#0 2 l-g& :q" LVCMOS33 9(q" LVTTL &604%(%08hk 2 46*"#n%07%(;^(.7(23"%4@'54/"0 FPGA 3^_-.ff LVTTL (IOSTANDARD = LVTTL) .$r3^_-.ff Slow slew Rate (SLEW = SLOW) s- Edit Constraints(Text).c&0&60(a^8h1k 5 9(q"s-9-)%4n%0 PACE .c&0(a^8hk 16 (a^8h1k 5 7%(;^(.7(23"%4@'54/"0 FPGA 3^_-.ff LVCMOS .$r3^_-.ff Slow slew Rate s- Edit Constraints(Text) 15 FPGA Surveyor-III XC3S200 Board Manual (Rev2.07/03/07) (a^8h1k 6 7%(;^(.7(23"%4@'54/"0 FPGA 3^_-.ff LVCMOS .$r3^_-.ff Slow slew Rate s-9-)%4n%0 PACE 4.6 M;?:?M:C;5N JTAG O89PQR:S;5N J1 :"-3-:34"(@ JTAG sl)cd%9(6f4n"c%#&%*-@;9$& (JTAG Cable) 3/)%76f'"(@4/-%-(Printer Port)/"0:"2'g*34"(@ 3'qk" ;^(.7(2/)"2a$*01( (Configuration data) $0 FPGA f"(@&8&$"0-hp,a7""7.ffs9);^(.7(2 Serial Flash PROM .$r FPGA s- JTAG Mode (Boundary Scan Mode)u&);(0;sl)c%#&%*-@;9$& .$rsl) Master Serial Mode 3'qk"s9) Serial Flash PROM c%2%(,;^(.7(2 FPGA "#n%0"64;-264g857:(6p08hk1n%#u?3$hp#0 s- Master Serial Mode -6p-4)"03!4 Jumper J1 s9) M0, M1, M2 = 000 4%28hkc(5^u*)s-4%(%08hk 3 c%#&%*-@;9$&c%2%(,sl)u&)86p0/"0 Xilinx 9(q"/"0f(gj683"3'73"07eu&) (s9)2% '()"276ff"(@&8&$"0"#an.$)*) .$ru2n*n%1r46p0:n% M0, M1 .$r M2 "#ans-;92&"qk-s&7e#60c%2%(,;^(.7(2;sl)c%# JTAGu&) 16 FPGA Surveyor-III XC3S200 Board Manual (Rev2.07/03/07) 4%(%08hk 3 (%#7%(3!4;92&s-7%(;^(.7(2 FPGA 7%(;^(.7(2 FPGA ;(0on%-8%0c%# JTAG -6p-oa)sl)1r4)"0$f/)"2a$s- Flash PROM 8gp07n"-3c2" 46*"#n%0.c&0 &60(a^8hk 17 7%(u2n$f/)"2a$*01(""71%7 Flash PROM 7n"-"%18d%s9)/)"2a$8hk;^(.7(2$0 FPGA u2nc2fa(b@ (;u2n2h7%( 34q"-*n%37g&/)"og&'$%&) 3'(%r FPGA 1r,a73!4"#ans- Master Serial Mode 1v0,a7;^(.7(21%7 Flash PROM "#n%0"64;-264g 3(h#f()"#.$)*86-8h8hk3(gk24)-1n%#u?3$hp#0 7%(;^(.7(2*01($0 FPGA -6p-3(%1r4)"0c()%0u?$@'()"28h1k r;^(.7(2$0 Platform Flash PROM .$r FPGA 7n"1%7-6p-.$)*8d%7%(4n"c%# JTAG .$r4n"u?3$hp#03/)%f"(@&.$)*8d%7%(&%*-@;9$&*01(8hk4)"07%($0can Flash PROM .$rlg' FPGA 4%2$d%&6f !vk0/6p-4"-&%*-@;9$&-6p-8hk1":"2'g*34"(@1r^(%7lg'86p0 2 46*'()"276-&60(a^8hk 18 3'(%r2h7%(""7.ffs9)s-;92& JTAG 4n",v076-*-.ff$a7;!n3'qk"cr&*732qk";^(.7(2 3(%1v0c%2%(,3$q"78hk1r&%*-@;9$&/)"2a$$0lg'86p0c"046*9(q"46*s&46* 9-vk07eu&) .$r3-qk"01%7 Platform Flash PROM .$r FPGA 4n"76-s-;92& Master serial (M0 , M1 , M2 = 0) "h7&)*# &60-6p-857 :(6p08hk3(gk21n%#u?s9)f"(@&8&$"0 FPGA 1r&%*-@;9$&/)"2a$1%7 Platform Flash PROM 2%8hk FPGA "#n%0"64;-264g (a^8hk 17 .c&07%($f/)"2a$s- Flash PROM 8gp07n"-7%(;^(.7(2 FPGA ;(0on%-8%0c%# JTAG 17 FPGA Surveyor-III XC3S200 Board Manual (Rev2.07/03/07) (a^8hk 18 /6p-4"-&%*-@;9$&8hk1":"2'g*34"(@1r^(%7lg' Flash PROM .$r FPGA '()"276- 18
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