60333100A_3436_3437_Drum_Storage_Ctlr_Oct70 60333100A 3436 3437 Drum Storage Ctlr Oct70

User Manual: Pdf 60333100A_3436_3437_Drum_Storage_Ctlr_Oct70

Open the PDF directly: View PDF .
Page Count: 53

Download
Open PDF In Browser	View PDF

CONTROL DATA
CORPORATION

CONTROL DATA ®
3436-A, 3637 -AlBIC
DRUM STORAGE CONTROLLERS

REFERENCE MANUAL

REVISION RECORD
REVISION
A
(10-1-70)

DESCRIPTION
Manual released; this publication obsoletes the 3436/3637 Drum Storage Controllers section of the
3000 SERIES PERIPHERAL EQUIPMENT Reference Manual, Pub. No. 60108800.

Information

contained herein is the same as that found in Rev. U of the obsolete manual.

Publication No.
60333100

Address comments concerning this
manual to:

Printed in the United States of America

Control Data Corporation
Technical Publications Department
4201 North Lexington Avenue
Arden Hills, Minnesota 55112
or use Comment Sheet in the back of
this manual.

PREFACE
This publication contains reference information for Control Data® 3436-A, 3637-A/B/C
Drum Storage Controllers which may be used in conjunction with standard Control Data
3000 series data channels.

The reader should be familiar with characteristics of the

3000 series data channels.

60333100 A

iii

CONTENTS
Functional Description

Buffer Timing

27
28

Addressing
863 Format

Drum Controllers

865 Format

Storage

Data Format

Program Compatability

Address Characteristics

865 I/O Operations

Data Transfer

Simultaneous Selection

Performance Timing

Buffer Restrictions
Master Clear, Release and
Disconnect

33
33

Not Ready

Interrupts

Write Timing

Subsystem Configuration

Drum Units

Codes
Connect Code

Function Codes

15
21

Subsystem Errors and
Performance

Programming Considerations

Status Codes

:30

Lost Data Error

24
24

Parity Errors

Not Ready Causes

Manual Operations

Sample Program Routine
Program Sequence

40
40
41

Program

FIGURES
8

Typical Drum Subsystem

Holding Register During
Read/Write Operation

Theoretical Byte Recording Format

863 Drum Address Format

Connect Code Format

10 865 Drum Address Format

Function Code Format

Write Timing

11 Drum Unit Switches and
Indicators

Holding Registers During
Write Operations

12 Controller Interior Switches
and Indicators

Read/Write Check Timing

TABLES
1
2

Drum Capacity and Transfer
Specifications

Interlace Specifications

60333100 A

Connect, Function, and
Status Codes

Switches and Indicators

'""

DRUM STORAGE CONTROLLER

DRUM STORAGE UNIT

3436-A,3637-A/B/C DRUM

STORAGE

CONTROLLERS

This manual describes a drum storage subsystem consisting of the CONTROL DATA ®
3436/3637 Drum Storage Controllers" CONTROL DATA~' 3000 Series Data Channels"
and the following peripheral storage devices: CONTROL DATA® 861/863 and 865 Drum
Storage Units.

It includes relevant system specifications" programming procedures"

codes" manual operating information and sample program routines.

It is assumed the

reader is familiar with 3000 Series logic" instructions" and procedures.
The following terms are used throughout this section and are defined here for clarification:
•

Drum: The physical drum assembly" consisting of the drum drive motor"
recording surface" drum case and logic mounted thereon. It does not include the cabinet which houses the drum assembly.

•

Drum Unit: The drum and cabinet in which it is housed along with the associated
drum unit logic and electronics.

•

Drum Controller: The logic interface between the drum unite s) and the data
channel(s) and the cabinet in which the logic is housed.

FUNCTIONAL DESCRIPTION

The controllers" in conjunction with the drum units operate as a drum storage subsystem having medium access time" nonvolatile" mass-memory facilities.

The

subsystem provides large-volume data storage with high-speed transfer capabilities.

The subsystem incorporates features which permit:
1)

Byte addressable data access in the 863 Drum Units.

Sector addressable data access in the 865 Drum Units.

Continuous addressing throughout each drum unit.

Data checking on completion of a Write operation (Write Check).

The ability to determine the approximate drum angular position for maximum
programming efficiency.

60333100 A

SUBSYSTEM CONFIGURATION
Two major elements constitute the drum storage subsystem: The drum controllers and
the drum units.

Up to eight drum units may be connected to each controller, and each

drum unit may be connected to two controllers.

Thus, the controller/drum unit con-

figuration allows two or more computing systems to be integrated via the drum units
and permits multiple operations to take place within a system.
typical drum subsystem.

Figure 1 shows a

Solid lines encompass the equipments necessary for a mini-

mum subsystem; dashed lines indicate subsystem expansion capabilities.

---r--

3000 SERIES
DATA CHANNEL

-----L:j-

DRUM
CONTROLLER

II1_

liT

UNIT

-+--~

r-=~
I 3000 SERIES , l DATA CHANNEL I

If'" "

DRUM

-L
-I - .I T
3000 SERIE~

I
!
,-l.- _ 1:"""_1-_
_
I ~_.....,
-i=DATA CHANNEL

---1

DRUM

I CONTROLLER
3000 SERIES ,
.......I....-...&....-L\_ _ _\ II I
I
I DATA CHANNE'::.J
I
UP TO 8 DRUM UNITS
~~- -t- --1- ---I

\
n

'v-I~-::l----

,.-- -__

I ~(-~lJI I
I I
l I
I J
--~
(-'-_/

Figure 1.

Typical Drum Subsystem

The subsystem incorporates features that allow the controller to operate with two 3000
Series Data Channels on a time-shared basis.
between the computers and the controllers.

The data channels provide an interface

The subsystem also allows time -shared

drum operations between controllers in the system.

In this case, the drum unit acts as

a common storage medium between the two controllers.

60333100 A

A description of equipment which may be incorporated into the drum storage
and its

capabi1ities~

subsystem~

is shown below.

3436 -A Drum Storage Controller - Provides a single data channel interface to
any of the 861/863 Drum Units.
3637 -A Drum Storage Controller - Provides a dual data channel interface to any
of the 861/863 Drum Units.
3637 -B Drum Storage Controller - Provides dual data channel interface to any of
the 861/863/865 Drum Units.
861-B Drum Unit - Provides byte addressable data storage

(2~ 097~

152 data bytes)

with variable transfer rate capabilities.
863-B/C Drum Unit - Provides byte addressable data storage

(2~ 097~

152 data

bytes) with variable transfer rate capabilities.
865-A/B Drum Unit - Provides sector addressable data storage (128 data bytes/
sector;

4~ 194~

304 bytes total capacity) at a fixed transfer rate.

Most of the information in this section is common to all of the equipment.
that is unique to a particular controller or drum unit is so stated.
863 -B Drum Units are similar.
this section;

however~

For

simplicity~

Information

The 861-Band

only the 863 is referenced throughout

all references and information applicable to the 863 also apply

to the 861.

DRUM UNITS
The basic purpose of the drum unit (which houses the drum and associated electronics)
is to provide recording surfaces for storage of data.

The

drum~

a vertical axis, is plated with a metallic recording medium.

which is mounted on

Each 863 drum contains

832 recording tracks; each 865 drum contains 768 recording tracks.
are used to make up three sets of control timing tracks.

Six other tracks

One track of each set provides

timing (Clock pulses); the other track of each set provides reference (indexing) information.
One of the three sets of control tracks is designated as a master set; the other two sets
are designated as working sets.

Provision is made within each drum unit for rewriting

the working tracks from the master set while the master set may be written or rewritten
via an external oscillator (one megacycle for the 863 Drum Unit; two megacycles for
the 865 Drum Unit).

60333100 A

The drum unit also contains the drum drive motor
drum electronics.

the R/W heads

and the associated

Provision is made within the 861/863 drum units for manual selec-

tion of the interface transfer rates and drum size.

All drum units provide for setting

of the unit designation (unit number) 1 and various maintenance switch functions.
The exchange of the following signals between the controller and drum units is necessary to control drum operation: (C - D) indicates the signal originates in the controller
and is sent to the drum; (D -

C) indicates the signal originates in the drum and is sent

to the controller.
Select (C -

This signal is sent to a1l drum units attached to the controller.

The signal indicates

that the unit code is on the line and causes the drum unit to examine the code.
Select Reply (D -

This signal is sent in response to the Select signal and indicates that the designated drum
unit has been selected.

Absence of the signal indicates that the desired drum was un-

available (either no such drum exists or the drum is reserved by another controller).
Head Group Address (C -

These signals carry the 8 -bit head group code (and Head Subgroup in the 865) from the
controller Address register.

The signals are decoded by the drum unit to select the

appropriate head group (and head subgroup in the 865).
Angular Address (C - D)
These signals carry the 15 -bit (14 -bit in the 865) angular address to the drum unit from
the controller Address register.

For the 863 1 the signals are decoded according to the

interlace to determine the angular position of the data to be read or written.

For the

865 1 the signals are decoded to determine the starting sector address of the data to be

read or written.
Read Angular Count (D - C)
These 12 signals carry: 1) from the 863

the upper 12 bits of the 15 -bit Angular Count.

This indicates within 8 byte locations the present position of the drum; 2) from the 865
(in the lower order positions) the 7 -bit sector address portion of the Angular Count.
This indicates the sector presently being referenced by the drum.
4

60333100 A

Write (C - D)
This signal indicates the data is on the lines and directs the drum unit to record the data
at the addressed location or sector.
Read (C - D)
This signal directs the drum unit to read data from the addressed byte or sector.
Data Ready (D - C)
This signal (sent in response to the Read signal) indicates that the requested byte (in
the case of the 863) is on the lines to the controller.
that a data byte (from the
Compare (D -

requested

For the 865, the signal indicates

sector) is on the lines to the controller.

This signal indicates that the drum unit is presently accessing the byte (for the 863) or
the sector (for the 865) location indicated by the controller Address register.

In the

case of the 863" the signal initiates the Read operation within the controller if in the Read
mode.

In the case of the 865" this signal comes up only at the beginning of the ad-

dressed sector.

For both the 863 and 865" the signal activates the Address Compare

interrupt if selected.
Write Reply (D - C)
This signal is sent in response to a Write signal.

It indicates that the Write operation

has been accepted by the drum unit and will commence upon determination of a successful Write Compare.
Write Compare (D - C)
This signal is sent in response to a Write signal.

It indicates that the angular address

sent by the controller and the angular position of the drum compare and that the previously selected Write operation is being initiated at that location.
Index (D - C)
This is the Stop Index signal from the index control track.

The signal indicates the end

of the clock and the beginning of the dead zone and head switching time for each revolution of the drum.
60333100 A

Drum Ready (D -- C)
This signal indicates that the unit code and the designation switch setting agree, the
drum is up to speed, and no timing errors exist.
Clock (D -- C)
Two clock signals (Clock 1 and Clock 2) are sent by the selected drum unit.

The signals

come from the control timing tracks and provide the two phases of the 1-MHz clock.
(The 865 drum 2 -MHz clock is broken down to 1 MHz for controller use. )
Release (C -- D)
This signal removes all operating modes and reserves in the drum units; however, it
does not affect any drum unit reserved by another controller.
MC (C -- D)
This signal clears most logic conditions, selections, and reserves within the drum
units; however, it does not affect any drum unit reserved by another controller.
Manually initiated Master Clear removes all error conditions and the Drum Ready
condition, causing the drum to recheck all timing and synchronization before becoming
Ready again.

(This requires approximately 70 ms. )

Drum Type (D -- C)
When a logical

1 , this signal indicates that the selected drum unit contains an 863

Drum with 32K byte storage per head group; when a logical

0 , this signal indicates

that the selected drum unit contains an 865 Drum with 65K byte storage per head group.
Data Error (D -- C)*
The presence of this signal indicates that either a Transmission Parity Error has been
detected during a Write operation, or that a Checkword Error has been detected during
a Read operation.

*These signals are only applicable to and returned only by the 865 Drum Units.
6

60333100 A

Busy (D- C)*
The presence of this signal indicates that the drum unit is busy with a data handling
operation.

Note that even if a Write or Read operation terminates prior to the end of

the sector, the drum unit remains busy until the checkword is read or written at the
end of that sector.
Lost Data (D -- C)*
The presence of this signal indicates that

1) the data channel has failed to maintain

the proper transfer rate while writing, (the controller checks for Lost Data during
Read operations), or 2) the byte address portion does not contain all zeros when a new
110 initiation is attempted.

sector.

(All 110 operations must commence at the beginning of a

At that point the byte address portion equals all zeros).

In addition to the signals, 13 bidirectional lines carry the data and parity information
and Connect codes between the controller Transfer register and the drum unit.
DRUM CONTROLLERS
The standard 3000 Series signals are exchanged between the controller and the data
channel.

The controller provides an interface between the drum units and the com-

puter via the data channels.

The controller translates the Connect and function codes

issued by the computer to control drum operation.

The controller synchronizes and

transfers data between the druIps and the computers in a parallel 13 -bit byte format.
The computers control the drum (and controller) operations through the use of 12 -bit
function codes and a 21-or 22-bit address word** (dependent upon the type of drum unit
in use).

Issuing of a function code specifying a mode of operation prepares the con-

troller and drum unit for an 110 operation. The drum seeks the specified head group
and the sector or angular address position specified by the contents of the Address
register in the controller.

The specific operation commences upon initiation of an

110 at the location specified by the address.

*These signals are applicable to the 865 Drum Units.
**For specific format and address word information, refer to ADDRESSING.

60333100 A

Subsequent to the initiation of an I/O to/from the drum, the computer may issue a Load
Address code followed by 2 bytes which form the address word.

If an address word is

issued, it is loaded into the controller Address register, and the next operation commences at this new address location.

If no new address is received by the controller

prior to the initiation of an I/O, operation commences at the address presently held in
the Address register*.
STORAGE
The types of drum units are similar in that they are all mounted in identical cabinets,
they all utilize a metallic magnetic recording medium, and all have the same number
of data recording tracks per unit.

The drums differ in their physical appearance, bit

and track arrangement, and logically in their recording and addressing techniques and
total storage capacities.
863 Drum Units
These drums have 768 data tracks and 64 parity tracks.

The tracks are divided into

64 groups of 13 tracks each (12 data and one parity track per group).

The groups are

organized vertically on the drum and are referred to as head groups.

Each bit of a

byte is written on a separate track of the group (see Figure 2).

Each track provides

32,768 bits of storage with a total capacity of 25,165,824 data bits (4,194" 304 6-bit
characters) per drum unit.
865 Drum Units
These drums have 768 data tracks divided into 64 head groups of 12 tracks each.
head group is further sub -divided into four subgroups of 3 tracks each.

Four bits of

each byte are written serially on each of the three tracks of the subgroup.
are written serially and in parallel as three groups of 4 bits each.

Each

The bytes

(See Figure 2. )

DATA FORMAT
Each 12 -bit byte plus an associated parity hit is transferred in parallel between the data
channels and the controller, and between the controller and selected drum units.

*With the 865 Drum, the byte portion of the address must equal zero or a Lost Data
Error will occur upon initiation of the operation.

60333100 A

863 Drum Units
In the 863 Drum Units the bytes are recorded in parallel on the 13 tracks of a head
group.

Data is written on the drum in a byte format within a head group: bytes are

recorded by laying down 1 bit in each of the 13 tracks of the head group.

Any byte may

be read or written without interference or reference to adjacent bytes (bits).

13-BIT$ (\3 TRACKS)
I OF 64 HEAD GROUPS

863 DRUM

.:::----mif-=~~~I!S:~~~~~::S}
:::::::::::===nn
_
~:::==fllll
. __________ _

I OF 64 HEAD GROUPS
(4 HEAD SUBGROUPS)

:~Il

865 DRUM

Figure 2.

Theoretical Byte Recording Format

865 Drum Units
In the 865 Drum Units each byte is recorded in 3 sets (tracks) of 4 bits each.
sets are recorded in parallel with the 4 bits within each set recorded serially.

The 3
A total

of 128 bytes are recorded in each sector of the drum.

60333100 A

ADDRESS CHARACTERISTICS
Data is referenced by means of a 21-or 22 -bit address. * The address is assembled in
the controller from two 12 -bit bytes sent via the data channel to the controller.

In the

863 a 21-bit address designates the specific head group and angular position of the byte
on the drum; in the 865, a 22 -bit address specifies the head group, the head subgroup
and the starting sector address.
Addresses are continuous throughout the drum.

For multiple-byte (or sector) transfers

the address is automatically augmented to select the next sequential byte (or sector)
without the necessity of readdressing from the computer.
Address sequencing is continuous from the starting address to the end of the drum;
however, operation is not end-:around within a drum unit.
863 Drum Units
The data is byte addressable.

Each 21-bit address references the head group and

angular position of one of the 32, 768 bytes within that head group.
865 Drum Unit
Data is sector addressable.

The sectors are referenced by means of a 22 -bit address.

Each address references a head group, a head subg!'oup, and a sector within the head
group.

DATA TRANSFER
The minimum data transfer is 1 bytet ; the maximum data transfer is an entire drum.
Table 1 lists the drum unit capacities and transfer information.
In the 865 Drum Unit data is transferred at a set rate of 1 byte every 2 microseconds.
In the 863 Drum Unit data is transferred at a maximum rate of 1 byte per microsecond.

*Dependent upon the type of drum used in the subsystem.
address word information, refer to Addressing.

For specific format and

t Although as little as 1 byte may be read or written in the 865, the smallest addressable quantity is a sector (128 bytes)

60333100 A

The transfer rate is variable in the 863 Drum Unit, and can be reduced in binary increments by a logic interlace built into the drum unit.

Table 2 indicates the interlaces

available along with the various byte transfer timing.
uallyat each drum unit.

The interlace is selected man-

Therefore, various 863 Drum Units in a subsystem may have

independent data transfer rates.

TABLE 1.. DRUM CAPACITY AND TRANSFER SPECIFICATIONS
865 Drum

863 Drum
C~pacity

Data Bits
6 -bit Characters

25,165,824

50,331,648

4,194,304

8, 388, 604

768

32,768

65,536

Tracks (data)
Bits/Track
Transfer
Minimum Quantity

1 byte

1 byte*

Maximum Quantity

2,097, 152 bytes

4, 194, 304 bytes

Maximum Rate

2,000,000 Characters/
second
(IXl interlace)

1,000,000 Characters/
second

TABLE 2.

INTERLACE SPEC-IFICATIONS
Transfer Rate

Ratio

f.J,sec/ Byte, Minimum

Byte/Sec~

(Maximum)

1: 1

1,000,000

2: 1

500,000

4:1

250,000

8:1
16:1

125,000

62,500

32:1

31,250

Registers within the controller and drum unit are used for synchronization and buffering.
Buffering limitations are explained under Buffer Timing.

* Although as little as

1 byte may be read or written in the 865, the smallest addressable quantity is a sector (128 bytes).

60333100 A

In the 865 Drum Unit the data channel must maintain the specified transfer rate or a
Lost Data condition will occur.

In the

863~

data is never missed due to the failure of

the data channel to maintain the selected interlace rate.

If a byte is missed (either

not received by the controller in time to be written on the drum or the last byte is not
accepted from the controller when the next byte is ready to be read). the controller
automatically enters a Readdress state during which the drum readdresses the location
of the missed byte (the Address register is decremented and the address relocated).
Accordingly~

position.

the drum must make one full revolution in order to relocate the desired

(The 863 Drum Unit requires 34 ms per revolution.)

PERFORMANCE TIMING
The access and total operating time involved in a data transfer is equal to the sum of
the times involved in addressing the

drum~

locating the address byte or sector (865),

and performing the transfer.
Head Switching
Head switching time is defined as the interval necessary to electronically switch from
one head group to another (or to the specified head group on an initial address operation).
This is a

constant~

and is equal to 100 usec.

Latency Time
Latency time is defined as the interval between the end of head switching time and the
point at which the addressed byte or sector (865) arrives under the R/W heads.

This

is a maximum of one revolution of the drum (33.4 ms); the average time is one-half
revolution.
Access Time
Access time is defined as the time necessary to electronically switch to the desired
head group plus the latency time necessary to locate the specified sector (865) or
angular address (863); bring the desired data under the selected head group.
During multiple byte transfers which encompass more than one head
switching takes place during the drum index time.

Thus~

group~

the head

additional access time is not

required to reference the next sequential head group; however, the transfer time is
increased by the 100 usec index time (see Programming Considerations; Write Timing).

60333100 A

CODES
Table 2 lists all codes applicable to the drum storage subsystem.
explanation of each code follows the table.
TABLE 2..

A complete

CONNECT 1 FUNCTION 1 AND STATUS CODES
Connect .
NOOU':C

Connect Controller and Drum
Function
Release and Disconnect

0000

Select Interrupt on Ready and Not Busy

0020

Release Interrupt on Ready and Not Busy

0021

Select Interrupt on End of Operation
Release Interrupt on End of Operation
Select Interrupt on Abnormal End of Operation
Release Interrupt on Abnormal End of Operation
Select Interrupt on Opposite Channel Release**
Release Interrupt on Opposite Channel Release**

0022
0023
0024
0025
0026
0027

Select Interrupt on Address Compare
Release Interrupt on Address Compare
Load Address

0030
0031
0040

Read
Write
Write Check

0041
0042
0043
0044

Read Angular Count

Status

XXXI
XXX 2
XXX 4

Ready
Busy
Drum Reject/ Lost Datat
W rite Check Error
End of Drum
Release Interrupt**
Address Compare Interrupt
Interrupt on Ready and Not Busy
Interrupt on End of Operation
Interrupt on Abnormal End of Operation
Read Parity Error
Reserved**
*N

= equipment

number of the controller.

XXIX
XX2X
XX4X
XIXX
X2XX
X4XX
1XXX
2XXX
4XXX
U

= drum

storage unit number.

**Not applicable to the 3436 Drum Storage Controller
t When operating with 3436/3637 -A Controllers this bit indicates a Drum
Reject; with 3637 -B Controllers l this bit indicates Lost Data.
l

60333100 A

CONNECT CODE

Connect Controller and Drum (NOOU)
The 12-bit Connect code (Figure 3) designates the equipment (controller) and the unit
(drum) with which the computer desires to communicate.
Once the data channel is connected to a controller and drum unit, the controller and
drum unit are reserved until specifically released by that channel.

The channels may

reserve additional drum units andlor controllers by issuing additional Connect instructions.

Each Connect must receive a Reply for a successful connect and reservation to

be made.

If a Connect is rejected, the controller and/or drum is unavailable (non-

existent or reserved by another channel).
NOTE
A Connect is never rejected because the
subsystem is Not Ready.
When more than one connect is made (to reserve more than one drum unit)

initiation

of an IIO takes place at the controller and drum selected by the last successful Connect
operation.
Equip No. (Controller)
3 bits
11

Unit No. (Drum)
3 bits

9, 8

Figure 3.

3, 2

Connect Code Format

Bits 0 -2
These 3 bits designate the unit (drum) with which the program desires to communicate.
The number designating the unit is variable from 0 -7 by means of a rotary designation
switch located in the drum unit.
Bits 3-8
Unused.

60333100 A

Bits 9-11
These 3 bits designate the equipment with which the program desires to communicate ..
The number designating the drum controller is variable by means of a rotary designation switch located in the controller cabinet.
Upon receipt of the Connect code by the controller ~ a Reply or Rej ect is returned to the
available~

data channel.

If the desired controller and drum are

immediately..

If the controller is unable to accept the code and perform the

Reject is returned.

Upon receipt of a

Reject~

a Reply is returned
connect~

the computer must request a status

response and interrogate the status bits in order to determine whether the Rej ect was
a result of the controller being reserved or the drum unit being unavailable.

(Refer to

explanation of status response bits Drum Reject (XXX4) and Reserved (4XXX). )
FUNCTION CODES
The four-digit octal function codes (Figure 4) are divided into two major categories.
The upper two digits of the code must be zeros; the categories are:
1)

The mode codes (000 - and 004 - ) which affect operating modes and,

The interrupt codes (002 - and 003 - ) which set and remove interrupt selections.

3 bits

9, 8

;Figure 4.

6, 5

3 bits

- 3, 2

Function Code Format

A Rej ect is issued upon receipt of a mode or release function code whenever the controller is busy (I/O in process).
Unassigned function codes are replied but ignored by the controller.
Mode Codes
The first code in this group (the Release and Disconnect (0000)

code)~

while not actually

a mode code, provides the computer with the means of releasing the drum subsystem
and deselecting the data channel (without using a Master Clear), removing all reserves,
mode selections and Interrupt signals.

The remaining five codes in the group provide

the computer with a means of selecting one of five operational modes.

In the latter five

cases, actual operation commences after the mode selection has been made and an I/O
is initiated.
60333100 A

Transmission of a new select code prior to initiation of an I/O removes the present
selection and replaces it with a new selection. In all cases# the select code is cleared
upon completion of the mode of operation (end of I/O).

Therefore# each individual

buffer must be preceded by an operating mode code.
Release and Disconnect (0000)

This code releases the subsystem from the data channel.

It causes all reserves to be

removed# clears all Interrupt signals# removes all mode selections# clears the Read
Parity and Write Check Error conditions, and drops the status response lines.

(See

Programming Consideration; Master Clear# Release and Disconnect.)
Load Address (0040)

This mode, in conjunction with an output buffer, causes the controller to load the next
output buffer into the controller Address register.
Read (0041)

This mode, in conjunction with an input buffer, causes the controller to initiate a Read
operation from the drum at the address specified by the content of the Address register.
The operation will continue until halted by one of the conditions listed under Interrupt
on End of Operation.
Write (0042)

This mode, in conjunction with an output buffer, causes the controller to initiate a
Write operation to the drum at the address specified by the content of the controller
Address register.

The operation continues until halted by one of the conditions listed

under the Interrupt on End of Operation.
Write Check (0043)

This mode# in conjunction with an output buffer, causes the controller to initiate a Read
froln the drum at the address specified by the content of the controller Address register.
The output buffer transmits data to the controller which is compared on a bit -by-bit
basis with the data read from the drum.

60333100 A

Upon occurrence of a miscompare (compare error), the Write Check Error status bit
is set. The occurrence of a write check error causes the Abnormal End of Operation
interrupt to be set (if selected).
NOTE
The operation ends before the byte in error
is replied; thus, in this case, the Address
register contains the address of the byte in
error.
Read Angular Count (0044)

This mode, in conjunction with an input buffer, causes the controller to return to the
data channel a portion of the drum angular count.

The count held in the Angular

Counter is advanced by the drum unit Clock pulses and is synchronized with the rotation of the drum.

Thus, the count (at any particular instant) represents the angular

position of the drum in relation to the various address locations.
NOTE
The count returned is from the drum unit
Angular Counter and is NOT the contents
of the Address register.
The count returned to the data channel by the controller is dependent upon the type of
drum unit selected.
•

865 Drum Unit:

The controller returns the- 7 -bit sector address portion of

the count presently associated with the data block being referenced.
The Angular Count is not timed with the beginning of the sector, and therefore
the programmer cannot expect to operate on the next sector of the drum consistently.

The programs next operation should be initiated on the returned

address + 2.
•

(See Address Compare Interrupt .. )

861/863 Drum Unit:
angular count.

The controller returns the upper 12 bits of the 15-bit

These 12 bits are sufficient to indicate within eight address

positions (approximately 8 f.,lsec) the present position of the drum.

If the

input buffer is more than 1 byte in length, the count presently held in the
continuously incrementing Angular Counter is returned on each byte transmitted.
The lower 15 bits of the 21-bit address indicate the angular address of a particular byte.
60333100 A

The actual angular position of the byte on the drum depends upon
17

the interlace selected.

To determine the physical location (angular position)

of a particular byte address, the angular address portion of the byte address
is left shifted, end -around, by the number of bits equal to the log2 of the
interlace. An example follows:
Drum Interlace = 8-1

Log 2

Byte Address ~~8

Angular Address 31465

Head Address j
Angular Address

8=3

8
Angular Address = 011 001 100 110 101 2
Physical Location = 001 100 110 101 011

Interrupt Codes
These codes establish and remove the interrupt selections which determine what conditions send an interrupt to the data channel.

The codes are never rejected by the control-

ler.
A manual Master Clear or channel Master Clear removes all interrupt selections.
Interrupt indications (interrupt active) are removed whenever a manual Master Clear,
channel Master Clear, release, or any interrupt function (select or release) is performed.

The indication (but not the selection) is also removed whenever a new mode

of operation is selected.

Select Interrupt on Ready and Not Busy (0020)

Selection of this code causes the interrupt line to be activated and the associated status
bit set the next time the subsystem becomes Ready and Not Busy (at the end of the next
operation).

(For an explanation of Ready and Not Busy conditions, refer to the asso-

ciated status response bit description. )
Release Interrupt on Ready and Not Busy (0021)

This code removes the associated interrupt selection set up by the 0020 code.

interrupt notification of Ready and Not Busy will be sent until the condition is reselected.
Select Interrupt on End of Operation (0022)

This code causes the interrupt line to be activated and the associated status bit to be
sent upon completion of the next operation whether the end of operation is normal or
abnormal.
18

60333100 A

Normally, operation ends upon completion of a buffer; however, during Write operation,
the End of Operation signal is delayed until completion of writing of the last byte on the
drum.

Although this is a fixed delay for the operation, the length of the delay is inher-

ently dependent on the interlace being used, on the last address of the drum, and on
whether a single byte is being written.

(For specific times, refer to Program Consider-

ations; Write Timing.)
Release Interrupt on End oj Operation (0023)

This code removes the associated interrupt selections set up by the 0022 code.

interrupt indication of end of operation will be sent until the condition is res elected.
Select Interrupt on Abnormal End oj Operation (0024)

This code causes the interrupt line to be activated and the associated status bit set upon
the stopping of an operation due to any abnormal condition within the controller or drum
unit.
The following conditions are considered abnormal:
1)

The drum unit becomes Not Ready.

Any 110 attempt to reference an address exceeding the last address of the drum.

Occurrence of a read parity error (parity error in the data read from the drum).

Occurrence of a write check error (lack of a comparison during a Write Check
operation) •

Conditions 1 and 2 cause operations to cease immediately whether the interrupt is selected or not.

If the interrupt is not selected, operation ends in a normal manner even

though conditions 3 or 4 or both have occurred.
Release Interrupt on Abnormal End oj Operation (0025)

This code removes the associated interrupt selection set up by the 0024 code.

interrupt indication of abnormal end of operation will be sent until the condition is reselected.
Select Interrupt on Opposite Channel Release (0026)

This code causes an Interrupt signal to be sent and the associated status bit set whenever the opposite data channel (the channel presently maintaining a Reserve state of
the controller) releases its reservation of the controller and drum units.
60333100 A

NOTE
If only one data channel is connected to the

controller (as in the 3436) this code is not
applicable and should not be used.
NOTE
The interrupt is conditioned upon the dropping of the reserve. Therefore, a Master
Clear causes the interrupt only if the data
channel executing the Master Clear has the
drum sUb-system reserved.
Release Interrupt on Opposite Channel Release (0027)*

This code removes the associated interrupt selection set by the 0026 code.

No interrupt

indication of a release by the other channel will be set until the condition is reselected.
Select Interrupt on Address Compare (0030)

This code causes the interrupt line to be activated and the associated status bit set upon
occurrence (locating) of an address comparison between contents of the drum Angular
Counter and the contents of the controller Address register.
When operating with an 863 Drum Unit, this interrupt operates in either of the following
modes:
1)

Upon detection of a specified address: if none of the 0041 through 0044 codes
have been selected prior to location of the address, the interrupt occurs
immediately.

Upon location of the specified address: if a mode is selected prior to location
of the address, the interrupt is sent upon initiation of data transfer (I/O) at
that address.

When operating with an 865 Drum Unit, this interrupt is conditioned only on the sector
portion of the address.

The interrupt occurs when the beginning of the specified sector

is detected, and accordingly does not permit enough time for an operation to be initiated to that sector.
Release Interrupt on Address Compare (0031)

This code removes the associated interrupt selection set up by the 0030 code.

No in-

terrupt indication of an address comparison will be sent until the condition is reselected.

60333100 A

STATUS CODES
In order for the computer to determine the state of the controller and
status response is available to the data channel.

drums~

a 12 -bit

The computer initiates a Copy Status

instruction and samples the status response on the lines from the controller.
puter may sample a status response anytime it is

connected~

The com-

or after a connect attempt

is rej ected~ even if the controller andlor drum unit are under control or reservation by
a different data channel.
The Copy Status response bits (Table 3) indicate the state of the controller and! or
drums to which the data channel is connected or last attempted to connect.

A "1" in

the bit position indicates the condition is present (or has occurred); a "0" indicates the
condition is not present (or has not occurred).

It should be noted that the interrupts

must have been selected or the associated interrupt status bit will be a "0" even
though a condition that would normally set the interrupt has occurred (e. g., a copy
status will not indicate that an abnormal end of operation has occurred unless the
Abnormal End of Operation interrupt is selected).
interrupt is

selected~

the operation

ends~

If the Abnormal End of Operation

the Interrupt and Error status bits are set,

and the interrupt is sent to the data channel immediately upon occurrence of the error
condition.

However, if the Abnormal End of Operation interrupt is not selected, the

Error status bits are set immediately upon occurrence of the error condition even
though the operation may not end until the buffer is completed (end of 1/0).
Ready (XXXl)-Bit

The presence of this bit indicates that the drum unit that last connected is in an operable condition and ready for use.

The drum is considered Ready when it is up to oper-

ating speed, all voltages are at proper operating levels, and no timing fault conditions
exist.

The bit will remain a "I" until the unit becomes inoperable or certain fault

conditions occur (see Not Ready Causes).
Busy (XXX2)-Bit 1

The presence of this bit indicates that the drum unit specified by the Connect code is
currently performing an operation (data transfer) and is unable to initiate any new
action at this time.

The bit will become a "0" at the end of operation.

The Busy status normally follows the Channel Busy signal; however, in a Write mode,
the Busy status remains until the last byte has been written on the drum, or in the case
of the 865, until a checkword has been written or read. Any abnormal condition which
causes an end of operation to occur causes the Busy status to drop.
60333100 A

The Busy status does not respond to buffers attempted on a unit which is Not Ready or
to buffers which are inconsistent with the selected mode of operation or for which no
mode of operation has been selected (e. g.

attempting to initiate an output buffer when

a Read mode is selected).
Drum Reject/Lost Data (XXX4)-Bit 2

Dependent upon the controller model used in the subsystem" this bit indicates:
•

3436/3637 -A Controllers - Drum Reject
The presence of this bit indicates that the instruction has been rejected
because the specified drum unit was unavailable.

This bit will be a "1"

whether another controller is actually using the unit or simply has it
reserved.

The bit will also become a "1" if the unit specified by the code

does not exist (no drum unit has that unit designation switch setting).
•

3637 -B Controller - Lost Data
The presence of this bit indicates that data has been lost due to the data
channel's failure to maintain the specified transfer rate to the 865 Drum
Unit" or that the starting byte address was unequal to zero upon initiation
of an I/O operation. (this bit is not used when 861/863 Drum Units are
attached to this controller).

Write Check Error (XXIXJ-Bit 3

The presence of this bit indicates that a miscompare has occurred during a Write
Check operation.

The bit is a "0" from initiation of the operation until the completion

of the operation" providing the record compares for the entire buffer.

If a miscompare

is detected" the bit becomes a "1" immediately" and operation ceases if the Abnormal
End of Operation interrupt is selected.
End of Drum (XX2X)-Bit 4

The presence of this bit indicates that: 1) with 3436/3637 -A Controllers" the drum unit
has addressed and used the final address on the drum. The bit remains a "1" until the
subsystem is readdressed or master cleared (a Me clears the Address register to
00000) or~ 2) with 3637 -B Controllers" that the operation being initiated on the drum is
attempting to go end-around on the drum. (Refer to section on Addressing).
Release Interrupt (XX4X)-Bit 5

The presence of this bit indicates that the interrupt was caused by the other data
channel releasing its reserve of the controller and/ or drum u:r{its.
22

60333100 A

Address Compare Interrupt (XIXX)-Bit 6

The presence of this bit indicates that the interrupt was caused by an existing comparison between the content of the controller Address register and the drum angular
position (see 0030 Interrupt on Address Compare).
Interrupt on Ready and Not Busy (X2XX)-Bit 7

The presence of this bit indicates that the interrupt was caused by the specified condition" i. e." the drum unit is in the Ready state and is not currently Busy.
Interrupt on End of Operation (X4XX)-Bit 8*

The presence of this bit indicates that the interrupt was caused by an End of Operation.
Interrupt on Abnormal End oj Operation (lXXX)-Bit 9 *

The presence of this bit indicates that the interrupt was caused by an Abnormal End of
Operation.
Read Parity Error (2XXX)-Bit 10

The presence of this bit indicates that either a parity or checkword error has been
detected in the data read from the drum during a Read or Write Check operation.

When

an 865 Drum is selected, the occurrence of a transmission parity error between the
controller and drum unit also causes this bit to set.
Reserved (4XXX)- Bit 11

Dependent upon the controller model used in the subsystem" this bit indicates:
•

For 3436/3637 -A Controller: The presence of this bit indicates that the instruction has been rej ected because of the Reserved condition.

If the status

occurs without the Drum Reject status bit set, it indicates that the controller
is reserved by the other data channel.

If the status occurs with the Drum

Reject bit set" it indicates that the controller is not reserved by the other
channel but that the desired drum unit was reserved or unavailable.

*For an explanation of an End of Operation and an Abnormal End of Operation, see
interrupt function codes 0022 and 0024.
60333100 A

•

For 3637 -B Controllers: The presence of this bit indicates that the instruction
has been rejected because the controller is reserved by the other data channel.
If the bit is a zero after a connect is rejected, it indicates that the controller

is not reserved by the other channel but that the desired drum unit was reserved or unavailable.

SUBSYSTEM ERRORS AND PERFORMANCE
The controller is designed to recognize lost data, parity, and write check errors.
Other internal drum errors cause the subsystem to go to the Not Ready state.

The

write check, lost data, and read parity errors may be detected through the use of
interrupts and the Copy Status instruction.

LOST DATA ERROR
This error and associated status bit is applicable only when operating with an 865 Drum
Unit.

The error occurs (and the associated status bit sets) whenever:

•

A data transfer is initiated anywhere other than at the start of a sector.

•

The data channel fails to maintain the required transfer rate between the
channel and controller I drum unit.

Upon occurrence of a Lost Data error condition, all further data transfer (within the
operation) ceases and an Abnormal End of Operation occurs.

If selected, the Abnormal

End of Operation Interrupt sets.

PARITY ERRORS
The controller is designed to recognize two distinct types of parity errors:
1)

A parity error associated with the byte received from the data channel, called
a Transmission Parity Error.

A parity error associated with the data read from the drum, called a Read
Parity Error.

The Read Parity Error and Transmission Parity Error circuits are independent of one
another. The data transfer circuits within the controller are designed so that the

60333100 A

occurrence of one type of error does not cause the occurrence of the other

0. e. ,

occurrence of either type of error causes the controller to correct (toggle) the parity
bit prior to transferring the byte).
Read Parity Error
During Read or Write Check (special type of Read) operation, a check is made on the
data read from the drum.

If an error is detected ll the Read Parity Error FF sets

causing the associated parity error indicator to light and status bit to set.

If selected,

the Abnormal End of Operation Interrupt occurs and that status bit is set.

In the case

of the 861/863 drums it indicates that a parity error was deleted in the data byte read
from the drum.

In the case of the 865 it indicates that either a checkword error was

detected in association with the sector read from the drum or a parity error was detected in the data transferred between the drum and the controller.
NOTE
The Read Parity Error FF and status bit
remain set until a new operation is initiated.
Transmission Parity Error
The Transmission (XMSN) Parity circuits examine each byte transmitted tol from the
controller ll generate a new parity bit for that byte ll and compare the parity bit generated
with the parity bit accompanying the byte.
Parity Error indicator lights up.

If the bits do not agree, the Transmission

Transmission of the error indication to the data

channel is dependent upon the code or data causing the error as follows:

XMSN Parity Error on Connect: If the error is detected in conjunction with a Connect
code the connect and status droPIl no action is taken by the controller upon the code in
error ll the TRANSMISSION PIE indicator. (XMSN) lights up; however, no Reply, Rejectll
II

or Transmission Parity Error signals are sent to the data channe1.
XMSN Parity Error on Function: If a Transmission Parity Error occurs in conjunction
with a function code, the XMSN Parity Error signal is enabled to the data channel and
the error indicator lights up; however, the function code is ignored by the controller.
(No Reply or Reject is sent).

60333100 A

XMSN Parity Error on Data Transfer: If a Transmission Parity Error is detected on a
data byte received from or transmitted to the data channel, the XMSN Parity Error
signal is enabled and the error indicator lights up.

Transfer of the byte in error con-

tinues in the normal manner.
The 865 Drum Unit also checks and generates parity for each byte transmitted to or
received from the controller.

(Parity bits are not written on or read from the 865

drum; only the checkword is used for data error detection. )
In the 863, if a Transmission Parity Error occurs during a Write operation, the parity
bit of the byte in error is toggled and the byte in error along with the toggled parity bit
is transferred to and written on the drum. If a Read Parity Error occurs during a Read
operation, the parity bit in error is toggled and the byte in error, along with the corrected parity bit is transferred to the data channel.

(Toggling of the parity bit has the

effect of correcting the parity error, not the byte, so that the byte in error does not
cause a parity error to be detected in the opposite parity circuit as the byte in error is
transferred. )
NOTE
Once the parity bit is toggled and the byte
transferred, all indication of the byte in error
is removed (except as noted under Read Parity
Error). Thus it becomes the responsibility
of the programmer to maintain the knowledge
and indication of the byte in error and its
location on the drum (in the case of a Write)
or in the computer (in the case of a Read) in
order to avoid inadvertent use of the data in
error.
Only a master clear clears a Transmission Parity Error in the 3436/3637-A Controllers; any MC or new Connect operation clears the Transmission Parity Error in the
3637-B Controller.

NOT READY CAUSES
The drum subsystem becomes Not Ready only when the associated drum unit is Not
Ready.

•
•
•
26

The drum is Not Ready when any of the following conditions exist:
The drum is not up to operating speed.
Any abnormal voltage levels exist in the dc circuits.
A timing error exists or has been detected.

60333100 A

If the system becomes Not Ready during a data transfer" an abnormal end of operation

is generated (the End of Operation and/ or the Abnormal End of Operation interrupts are
set if selected).

The Not Ready status is removed by a manual master clear only.

BUFFER TIMING*
The following indicates the buffer timing** available to the data channel when operating
with 863 Drum Units.

If the channel fails to operate within these times the controller

automatically enters a Readdress state during which the drum readdresses the location
of the missed byte (the Address register is decremented and the address relocated).
Accordingly" the drum must make one full revolution in order to relocate the desired
position. (The 861/863 Drum Unit requires 34 ms per revolution.)
Timing of transfers within the drum subsystem is determined by the drum unit timing.
The timing is referenced at the start of a Write cycle (for Write operations) or the
start of a Read cycle (for Read and Write Check operations).
1)

Minimum data signal to Reply time is 0.1 microseconds for Read and Write
operations and O. 16 microseconds for Write Check operations.

The time from the dropping of the data signal to the dropping of the Reply is
constant at 0.04 microseconds.

Byte timing is dependent on the interlace selected.

The time between bytes is

equal to the interlace rate in microseconds ..
Write Timing
1)

The data signal must occur no later than O. 08 microseconds before the start
of the associated Write cycle.

The earliest a Reply can occur for the data signal of a given byte is 1.1 microseconds following the start of the Write cycle of the preceeding byte plus one

H. e ... the earliest a Reply can occur for Byte C is 1. 1 microseconds after the
start of the Write cycle for Byte A).
3)

Refer to Figure 5.

Figure.6 shows holding registers during Write operations.

*Not applicable to 865 Drum Units.
**All times are taken from the controller cable interface.
60333100 A

r--BYTE

TIMING

(~~~~~ ~~~~;_Y_CL_E__________~~~________________~p;q~________________~fCl~______
NS~

r-680

.------

r----

LATEST DATA SIGNAL I
A
B
I
C
(BYTE A)
____~L~~__~~~.•.__
.~.~
.•· ______~____________________
~'~_______________

I'E~----"OO NS-----~~I

Figure 5 ,;

BYTE
C

r---!
C

.------

EARLIEST REPLY SIGNAL
(BYTE C)

Write Timing

DATA( BUFFER} REG.

-7} ~I I

CONTROLLER

TE
eYe

DATA CHANNEL

Figure 6.

DATA

REG.

BYTE
A

WR ITE
DRIVER

DRUM UNIT

Holding Registers During Write Operations

Read and Write Check Timing
1)

The Data Signal for a byte must drop (indicating data channel acceptance of the
byte) at least 0.05 microseconds before the start of the Read Reply sequence
for the following byte.

The earliest a Reply can occur is O. 34 microseconds for a Read operation and
0.4 microseconds for a Write Check following the start of the Read Reply
sequence for that byte (refer to Figure 7). :.

Figure 8 shows the holding register during Read/Write Check operation.

ADDRESSING
After transmitting the Connect code, the computer may transmit an operating mode
code or a Load Address mode code.

If the operation is to start or continue at the ad-

dress location presently held in the controller register, an operating mode select code
is sent immediately upon completion of the connect.

The address currently held in the

60333100 A

START READ

(~~~~~:,~~C)

BYTE TIMING

----::J
'1

__~~~\A~)~1__________________~~~?B~j~~__________________~f§J_

Source Exif Data:

File Type                       : PDF
File Type Extension             : pdf
MIME Type                       : application/pdf
PDF Version                     : 1.3
Linearized                      : No
XMP Toolkit                     : Adobe XMP Core 4.2.1-c041 52.342996, 2008/05/07-21:37:19
Producer                        : Adobe Acrobat 9.0 Paper Capture Plug-in
Modify Date                     : 2018:05:08 19:13:02-07:00
Create Date                     : 2018:05:08 19:13:02-07:00
Metadata Date                   : 2018:05:08 19:13:02-07:00
Format                          : application/pdf
Document ID                     : uuid:2d2a1daa-d169-b941-b593-de0f422d915c
Instance ID                     : uuid:5bd078b0-cdfd-174f-adb6-60ad00952de3
Page Layout                     : SinglePage
Page Mode                       : UseOutlines
Page Count                      : 53

EXIF Metadata provided by EXIF.tools

60333100A_3436_3437_Drum_Storage_Ctlr_Oct70 60333100A 3436 3437 Drum Storage Ctlr Oct70

Navigation menu

Versions of this User Manual:

Views

Navigation