Configuration Guide For Display Drivers (ACPI And XML) 80 NB116 2 ACPI ON WINDOWS

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Qualcomm Technologies, Inc.

Configuration Guide for Display Drivers
(ACPI and XML)
80-NB116-2 G
March 27, 2017

Confidential and Proprietary – Qualcomm Technologies, Inc.
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Restricted Distribution: Not to be distributed to anyone who is not an employee of either Qualcomm Technologies, Inc. or its
affiliated companies without the express approval of Qualcomm Configuration Management.
Not to be used, copied, reproduced, or modified in whole or in part, nor its contents revealed in any manner to others without the
express written permission of Qualcomm Technologies, Inc.
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This technical data may be subject to U.S. and international export, re-export, or transfer (“export”) laws. Diversion contrary to U.S.
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© 2013-2017 Qualcomm Technologies, Inc. All rights reserved.

Revision history
Revision

Date

June 2013

Initial release

April 2014

Updated Section 3.3 and Tables 4-1, 5-2, 5-4, 5-5, 6-1, 8-4, 8-6, 8-7, 8-8,
9-2, and 11-1; added Sections 5.2.3, 8.2, 9.3, Table 10-2, and Chapters
13 and 14

February 2015

Updated Section 2.1 and Tables 4-1, 8-1, 8-6, and 9-2; added
Chapter 17

March 2015

Updated Tables 4-1, 7-1, 8-6, and 8-7; added Section 8.1.11

February 2016

August 2016

Updated Sections 2.1, 3.3 and Tables 4-1, 7-1, and 8-1; added Table 8-2
and Section 12.1.1

March 2017

Updated Table 4-1, 6-1, 7-1, 8-1, 8-2, and 9-4
Updated Sections 15.4.1, 15.4.2, 15.4.3, and 15.4.6
Added Sections 15.4.8, 15.4.9, and 15.4.10

80-NB116-2 G

Description

Updated Tables 4-1, 7-1, 8-1, 8-9, and 17-1

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Contents

1 Introduction...................................................................................................... 8
1.1 Purpose.......................................................................................................................... 8
1.2 Conventions .................................................................................................................. 8
1.3 Technical assistance ...................................................................................................... 8

2 ACPI configuration for display drivers .......................................................... 9
2.1 Panel configuration in the boot sequence ..................................................................... 9

3 Panel configuration format ........................................................................... 10
3.1 Tag syntax ................................................................................................................... 10
3.2 Special keyword tags .................................................................................................. 10
3.3 Supported data types ................................................................................................... 11
3.4 Limitations .................................................................................................................. 12

4 Supported tag list .......................................................................................... 13
5 Panel configuration tag descriptions .......................................................... 24
5.1 Informational fields..................................................................................................... 24
5.2 EDID fields ................................................................................................................. 24
5.2.1 Static EDID fields ............................................................................................ 24
5.2.2 Detailed timing fields ...................................................................................... 25
5.2.3 EDID information ............................................................................................ 26
5.2.4 Dynamic EDID fields ...................................................................................... 26
5.3 Panel timings configuration ........................................................................................ 28

6 Display hardware tag descriptions .............................................................. 30
6.1 Common hardware configuration parameters ............................................................. 30

7 Display features ............................................................................................. 33
7.1 Display feature flags ................................................................................................... 33

8 Display interface-specific configurations.................................................... 35
8.1 DSI interface configurations ....................................................................................... 35
8.1.1 Common DSI configurations ........................................................................... 35
8.1.2 Display stream compression (DSC)................................................................. 42
8.1.3 Init sequence timing ......................................................................................... 43
8.1.4 DSI DCS command configurations ................................................................. 44
8.1.5 Supported DCS commands .............................................................................. 45
8.1.6 Special DCS commands .................................................................................. 45

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Configuration Guide for Display Drivers (ACPI and XML)

Contents

8.1.7 DSI interface timing overrides......................................................................... 46
8.1.8 DSI Video mode configuration ........................................................................ 47
8.1.9 DSI Command mode configuration ................................................................. 52
8.1.10 DSI Command mode TE synchronization ..................................................... 54
8.1.11 Tear check threshold parameters ................................................................... 55
8.1.12 Dual DSI configuration.................................................................................. 55
8.2 DSI Command mode configuration ............................................................................ 56
8.3 eDP configuration ....................................................................................................... 58
8.4 HDMI configuration ................................................................................................... 60

9 Backlight configuration................................................................................. 62
9.1 Common backlight configuration parameters ............................................................. 63
9.2 PWM (PMIC)-based backlight control ....................................................................... 64
9.3 Sample backlight configurations................................................................................. 65
9.3.1 WLED configuration (1 WLED string) ........................................................... 65
9.3.2 LPG configuration ........................................................................................... 66
9.4 I2C-based backlight control ........................................................................................ 66
9.5 DSI DCS-based backlight control ............................................................................... 66
9.6 ACPI-based backlight control ..................................................................................... 67
9.7 CABL configuration ................................................................................................... 67
9.8 Advanced backlight configuration .............................................................................. 68

10 ESD detection and recovery configuration ............................................... 69
11 AD core configuration (preliminary) .......................................................... 70
12 Platform-specific GPIO configuration ........................................................ 71
12.1 GPIO configuration................................................................................................... 74

13 Power-saving configuration ....................................................................... 75
14 Sharpening configuration ........................................................................... 78
15 Display-specific ACPI methods .................................................................. 79
15.1 _ROM method .......................................................................................................... 80
15.2 ROM multipanel support .......................................................................................... 80
15.3 BLCP method ........................................................................................................... 82
15.3.1 BLCP format for DSI DCS commands.......................................................... 83
15.3.2 BLCP format for I2C commands ................................................................... 83
15.4 Panel calibration commands (PIGC, PPCC, PPGC, PGRT, PBRT, HSIC, PGMT) 84
15.4.1 Panel Inverse Gamma Correction (PIGC) ..................................................... 85
15.4.2 Panel Color Correction (PPCC) ..................................................................... 86
15.4.3 Panel Gamma Correction (PGCT) ................................................................. 87
15.4.4 Panel Gamma Response Table (PGRT)......................................................... 88
15.4.5 HSIC panel HSIC configuration table ........................................................... 90
15.4.6 Panel Gamut Mapping Table (PGMT) .......................................................... 90
15.4.7 Panel Backlight Response Table (PBRT) ...................................................... 92
15.4.8 Panel Linear Gamma Correction (PLGC) ..................................................... 94

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Configuration Guide for Display Drivers (ACPI and XML)

Contents

15.4.9 Panel Gamut Mapping Table (PWGM) ......................................................... 94
15.4.10 Panel Dithering Table (DITH) ..................................................................... 96

16 Registry key entries .................................................................................... 98
16.1 CABL ........................................................................................................................ 98
16.2 SBC ........................................................................................................................... 98
16.3 AVI Info Frame Packet ............................................................................................. 98
16.4 HDCP ........................................................................................................................ 99

17 OLED power ............................................................................................... 100
A Specifying the I2C connection in graphics.asl ......................................... 102
B Sample ACPI configuration for DCS-based backlight control ................ 103
C References................................................................................................... 109
C.1 Related documents ................................................................................................... 109
C.2 Acronyms and terms ................................................................................................ 109

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Configuration Guide for Display Drivers (ACPI and XML)

Contents

Figures
Figure 2-1 Panel configuration role in the boot sequence............................................................................ 9
Figure 5-1 Example phone dimensions and EDID population .................................................................. 26
Figure 5-2 Panel timings configuration ..................................................................................................... 28
Figure 8-1 Init sequence timing ................................................................................................................. 43
Figure 8-2 DSI DCS command configurations .......................................................................................... 44
Figure 8-3 DSI Command mode TE synchronization................................................................................ 54
Figure 8-4 DSI data transmission with respect to panel scanline .............................................................. 55
Figure 9-1 Backlight control under WDDM model ................................................................................... 62
Figure 12-1 Panel power-on reset .............................................................................................................. 71
Figure 17-1 PMIC IBB and LAB modules .............................................................................................. 100

Tables
Table 4-1 Supported tag list ....................................................................................................................... 13
Table 5-1 Informational fields ................................................................................................................... 24
Table 5-2 Static EDID fields...................................................................................................................... 24
Table 5-3 Detailed timing fields ................................................................................................................ 25
Table 5-4 Dynamic EDID fields ................................................................................................................ 26
Table 5-5 Panel timing fields ..................................................................................................................... 28
Table 6-1 Common hardware configuration parameters ........................................................................... 30
Table 7-1 Feature flags that can be enabled or disabled ............................................................................ 33
Table 8-1 Common DSI configurations ..................................................................................................... 35
Table 8-2 Parameters to configure the DSC module for DSI .................................................................... 42
Table 8-3 DSI DCS command configuration tags ..................................................................................... 44
Table 8-4 Supported DCS commands ........................................................................................................ 45
Table 8-5 Special DCS commands ............................................................................................................ 45
Table 8-6 DSI interface timing overrides .................................................................................................. 46
Table 8-7 DSI Video mode configuration.................................................................................................. 47
Table 8-8 DSI Command mode configuration ........................................................................................... 52
Table 8-9 eDP configuration ...................................................................................................................... 58
Table 8-10 HDMI configuration ................................................................................................................ 60
Table 9-1 Common backlight configuration parameters ........................................................................... 63
Table 9-2 PWM (PMIC)-based backlight control...................................................................................... 64
Table 9-3 CABL configuration .................................................................................................................. 67
Table 9-4 Backlight configuration ............................................................................................................. 68
Table 10-1 ESD Detection and Recovery tags........................................................................................... 69
Table 10-2 Display recovery threshold ...................................................................................................... 69
Table 11-1 AD core tags ............................................................................................................................ 70
Table 12-1 Panel resources ........................................................................................................................ 72

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Configuration Guide for Display Drivers (ACPI and XML)

Contents

Table 12-2 GPIO configuration tags .......................................................................................................... 74
Table 13-1 Power saving configuration ..................................................................................................... 76
Table 13-2 Power saving levels supported by the driver ........................................................................... 77
Table 14-1 Sharpening parameters ............................................................................................................ 78
Table 17-1 IBB/LAB management configuration.................................................................................... 101
Table A-1 XML tags and descriptions ..................................................................................................... 102

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1 Introduction

1.1 Purpose
This document is intended for display developers who are looking to customize the displayspecific Advanced Configuration and Power Interface (ACPI) entries for a particular display
device. Knowledge of display interfaces, Windows display driver model (WDDM) architecture,
and ACPI programming are prerequisites for this document. The XML syntax is common
between UEFI and ACPI, therefore this document applies to both configuration methods.
This document supports the MSM8974, MSM8x26, MSM8x62, MSM8084, MSM8x94,
MSM8996, and MSM8998 chipsets. Configurations mentioned in this document are specific to
these chipset families.

1.2 Conventions
Function declarations, function names, type declarations, and code samples appear in a different
font, e.g., #include.
Code variables appear in angle brackets, e.g., .
Commands to be entered appear in a different font, e.g., copy a:*.* b:.
Button and key names appear in bold font, e.g., click Save or press Enter.
Shading indicates content that has been added or changed in this revision of the document.

1.3 Technical assistance
For assistance or clarification on information in this document, submit a case to Qualcomm
Technologies, Inc. (QTI) at https://createpoint.qti.qualcomm.com/.
If you do not have access to the CDMATech Support Service website, register for access or send
email to support.cdmatech@qti.qualcomm.com.

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2 ACPI configuration for display drivers

2.1 Panel configuration in the boot sequence
The role of the panel configuration in the boot sequence is shown in Figure 2-1.

Firmware (UEFI)
(xml binary configuration)

HLOS Loader

Kernel Mode Driver

Figure 2-1 Panel configuration role in the boot sequence
The following two-stage sequence is specific to HLOSes that use UEFI and ACPI:


Firmware (UEFI) boot – During UEFI boot, the panel configuration is loaded directly from a
panel configuration in the UEFI binary. This configuration is parsed and applied to the
display controller.



OS boot (graphics miniport) – During OS boot, the KMD parses the display configuration
from the ACPI (_ROM) method.

Both boot stages use similar XML configurations. However, the data is physically located in two
locations even though the data has many configurations that are identical. The reason for this is
that the UEFI does not directly process data from the ACPI tables, and therefore the data cannot
be shared between both boot sequences. The Figure 2-1 shows the role of panel configuration in
the boot sequence.

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3 Panel configuration format

The panel configuration format is XML-like, only certain data fields are parsed and only certain
tags are recognized.

3.1 Tag syntax
The tag syntax is similar to XML using braces for various tags.

Tag Data

Tag Data
More Data



All tags must be unique except for certain keyword tags that are ignored



All tags must end with a



Tags are case-insensitive



Tags cannot be made from spaces or special characters

3.2 Special keyword tags


The tag is ignored.



Tags that use the keyword Group are ignored. However, tags within the context of a group
branch are parsed, for example, Group xyz is ignored, but MyTagA is parsed.

data



Comments are added as . However, comments should be avoided because
they add extra parsing time and size to the configuration.



Data appears after the tag name is ignored, but can be used for comments or informational
purposes.

tag data

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Configuration Guide for Display Drivers (ACPI and XML)

Panel configuration format

3.3 Supported data types
Parsing of data supports several data types.




Integer – Integer data can be in the form of decimal digits or hex digits. Depending on the
integer size, the range can vary; e.g., if the size is 1 byte, the range is 0x00-0xFF (0 to 255
decimal). Hex digits must be prefixed with “0x”, e.g., these are all valid integer values:


123456



0xFFEE23

Integer list – Integer lists are an ordered list of integers separated by spaces. Each entry is
interpreted as hex values regardless if it is prepended with 0x.




String – String data can be any alphanumeric sequence including spaces, e.g.:




NOTE:

Same String Data 1234

Boolean – Boolean data consists of either the true or false keyword tag. The case does not
matter.


True



false

GUID – The GUID tag accepts a standard Windows GUID, e.g.:




0x1234 0x456 0xAA 0xBB

{0xf9938f2d, 0x3756, 0x4760, 0xa0, 0x44, 0xcb, 0x29, 0xaf, 0xba,
0x5a, 0x69}

Binary – The binary field is a special field that is used to describe raw information, i.e.,
packet data. Each hex pair byte is separated by spaces and the “0x” prefix is not allowed.
Multiple packets can be formed by adding a new byte sequence on each line.

This is an important differentiator. Multiple bytes in the same line represent a single sequence,
while multiple bytes on multiple lines represent multiple packet sequences.

23 b0 04 29 b3 00 87 29 b6 30 83

23 b0 04 29 b3 00
87 29 b6 30 83

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Configuration Guide for Display Drivers (ACPI and XML)

Panel configuration format

3.4 Limitations


ASCII only – Only ASCII characters must be used. Unicode and double byte characters are
not supported.



Limited XML support – The format of the panel configuration is XML-like, and not all XML
tags are supported. Avoid using syntax that is not described in this document.



Configuration size – The panel configuration size is bounded by the amount of memory
allocated to store the configuration. Size limitations include all characters, including white
spaces, tags, and control characters (line feeds and carriage returns).


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4 Supported tag list

Table 4-1 provides a list of all of the currently supported panel configuration tags. This list is
subject to change.
Table 4-1 Supported tag list
NOTE:

The following table has been updated.

Panel name

Type
(size in bytes)

Purpose

Firmware
(UEFI)
supported

Graphics
KMD
supported

PanelName

String(13)

EDID reporting

Yes

PanelDescription

String (128)

EDID reporting

Yes

ManufactureID

Integer(2)

EDID reporting

Yes

ProductCode

Integer(2)

EDID reporting

Yes

SerialNumber

Integer(4)

EDID reporting

Yes

WeekofManufacture

Integer(1)

EDID reporting

Yes

YearofManufacture

Integer(1)

EDID reporting

Yes

EDIDVersion

Integer(1)

EDID reporting

Yes

EDIDRevision

Integer(1)

EDID reporting

Yes

VideoInputDefinition

Integer(1)

EDID reporting

Yes

HorizontalScreenSize

Integer(1)

EDID reporting

Yes

VerticalScreenSize

Integer(1)

EDID reporting

Yes

DisplayTransferCharacteristics

Integer(1)

EDID reporting

Yes

FeatureSupport

Integer(1)

EDID reporting

Yes

Red.GreenBits

Integer(1)

EDID reporting

Yes

Blue.WhiteBits

Integer(1)

EDID reporting

Yes

RedX

Integer(1)

EDID reporting

Yes

RedY

Integer(1)

EDID reporting

Yes

GreenX

Integer(1)

EDID reporting

Yes

GreenY

Integer(1)

EDID reporting

Yes

BlueX

Integer(1)

EDID reporting

Yes

BlueY

Integer(1)

EDID reporting

Yes

WhiteX

Integer(1)

EDID reporting

Yes

WhiteY

Integer(1)

EDID reporting

Yes

EstablishedTimingsI

Integer(1)

EDID reporting

Yes

EstablishedTimingsII

Integer(1)

EDID reporting

Yes

ManufacturesTiming

Integer(1)

EDID reporting

Yes

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Panel name

Type
(size in bytes)

Supported tag list

Purpose

Firmware
(UEFI)
supported

Graphics
KMD
supported

StandardTimings1

Integer(2)

EDID reporting

Yes

StandardTimings2

Integer(2)

EDID reporting

Yes

StandardTimings3

Integer(2)

EDID reporting

Yes

StandardTimings4

Integer(2)

EDID reporting

Yes

StandardTimings5

Integer(2)

EDID reporting

Yes

StandardTimings6

Integer(2)

EDID reporting

Yes

StandardTimings7

Integer(2)

EDID reporting

Yes

StandardTimings8

Integer(2)

EDID reporting

Yes

SignalTimingInterface

Integer(1)

EDID reporting

Yes

HorizontalScreenSizeMM

Integer(1)

EDID reporting

Yes

VerticalScreenSizeMM

Integer(1)

EDID reporting

Yes

HorizontalVerticalScreenSizeMM

Integer(1)

EDID reporting

Yes

InterfaceType

Integer(4)

Display hardware
configuration

Yes

PanelOrientation

Integer(4)

Display hardware
configuration

InterfaceColorFormat

Integer(4)

Display hardware
configuration

Yes

ComponentOrdering

Integer(4)

Display hardware
configuration

Yes

PixelPacking

Integer(4)

Display hardware

Yes

PixelAlignment

Integer(4)

Configuration

Yes

Display Hardware Configuration

HorizontalActive

Integer(4)

Configuration

Yes

HorizontalFrontPorch

Integer(4)

Display hardware

Yes

HorizontalBackPorch

Integer(4)

Configuration

Yes

HorizontalSyncPulse

Integer(4)

Display hardware

Yes

HorizontalSyncSkew

Integer(4)

Configuration

Yes

HorizontalLeftBorder

Integer(4)

Display hardware

Yes

HorizontalRightBorder

Integer(4)

Configuration

Yes

VerticalActive

Integer(4)

Display hardware

Yes

VerticalFrontPorch

Integer(4)

Configuration

Yes

VerticalBackPorch

Integer(4)

Display hardware

Yes

VerticalSyncPulse

Integer(4)

Configuration

Yes

VerticalTopBorder

Integer(4)

Display hardware

Yes

VerticalBottomBorder

Integer(4)

Configuration

Yes

InvertDataPolarity

Boolean

Display hardware

Yes

InvertVsyncPolairty

Boolean

Configuration

Yes

InvertHsyncPolarity

Boolean

Display hardware

Yes

BorderColor

Integer(4)

Configuration

Yes

UnderflowColor

Integer(4)

Configuration

Yes

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Panel name

Type
(size in bytes)

Supported tag list

Purpose

Firmware
(UEFI)
supported

Graphics
KMD
supported

DisplayPrimaryFlags

Integer(4)

Display
configuration

Yes

DisplayExternalFlags

Integer(4)

Display
configuration

Yes

ESDDetectionTime

Integer(4)

ESD detection
and recovery

Yes

ESDDetectionFailureRetry

Integer(4)

ESD detection
and recovery

Yes

DisplayRecoveryThreshold

Integer(4)

ESD detection
and recovery

Yes

DSIRefreshRate

Integer(4)

DSI hardware
configuration

Yes

DSIDynamicRefreshRates

Integer list(16)

DSI hardware
configuration

Yes

DSIBitClockFrequency

Integer(4)

DSI hardware
configuration

Yes

DSIDynamicBlankingRefreshRateList

Integer list(16)

DSI hardware
configuration

Yes

DSIDynamicVFrontPorchList

Integer list(16)

DSI hardware
configuration

Yes

DSIDynamicVBackPorchList

Integer list(16)

DSI hardware
configuration

Yes

DSIDynamicVSyncPulseList

Integer list(16)

DSI hardware
configuration

Yes

DSIDynamicHFrontPorchList

Integer list(16)

DSI hardware
configuration

Yes

DSIDynamicHBackPorchList

Integer list(16)

DSI hardware
configuration

Yes

DSIDynamicHSyncPulseList

Integer list(16)

DSI hardware
configuration

Yes

DSILanes

Integer(4)

DSI hardware
configuration

Yes

DSIChannelId

Integer(4)

DSI hardware
configuration

Yes

DSIVirtualId

Integer(4)

DSI hardware
configuration

Yes

DSIColorFormat

Integer(4)

DSI hardware
configuration

Yes

DSIPacketTransferHS

Boolean

DSI hardware
configuration

Yes

DSIClockHSForceRequest

Integer(4)

DSI hardware
configuration

Yes

DSIPixelXferTiming

Integer(4)

DSI hardware
configuration

Yes

DSIHostLaneMapping

Integer(4)

DSI hardware
configuration

Yes

DSI Hardware Configuration

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Configuration Guide for Display Drivers (ACPI and XML)

Panel name

Type
(size in bytes)

Supported tag list

Purpose

Firmware
(UEFI)
supported

Graphics
KMD
supported

DSILP11AtInit

Integer(4)

DSI hardware
configuration

Yes

DSIPhyDCDCMode

Boolean

DSI hardware
configuration

Yes

DSIEnterULPSPowerDown

Boolean

DSI hardware
configuration

Yes

DSIBitClkScalePercent

Integer(4)

DSI hardware
configuration

Yes

DSIBitClkScalePercent

Integer(4)

DSI hardware
configuration

Yes

DSIEscapeClockDivisor

Integer(4)

DSI hardware
configuration

Yes

DSIEscapeClockFrequency

Integer(4)

DSI hardware
configuration

Yes

DSITimingHSZeroOverride

Boolean

DSI hardware
configuration

Yes

DSITimingHSZeroValue

Integer(4)

DSI hardware
configuration

Yes

DSITimingHSExitOverride

Boolean

DSI hardware
configuration

Yes

DSITimingHSExitValue

Integer(4)

DSI hardware
configuration

Yes

DSITimingHSPrepareOverride

Boolean

DSI hardware
configuration

Yes

DSITimingHSPrepareValue

Integer(4)

DSI hardware
configuration

Yes

DSITimingHSTrailOverride

Boolean

DSI hardware
configuration

Yes

DSITimingHSTrailValue

Integer(4)

DSI hardware
configuration

Yes

DSITimingHSRequestOverride

Boolean

DSI hardware
configuration

Yes

DSITimingHSRequestValue

Integer(4)

DSI hardware
configuration

Yes

DSITimingCLKZeroOverride

Boolean

DSI hardware
configuration

Yes

DSITimingCLKZeroValue

Integer(4)

DSI hardware
configuration

Yes

DSITimingCLKTrailOverride

Boolean

DSI hardware
configuration

Yes

DSITimingCLKTrailValue

Integer(4)

DSI hardware
configuration

Yes

DSITimingCLKPrepareOverride

Boolean

DSI hardware
configuration

Yes

DSITimingCLKPrepareValue

Integer(4)

DSI hardware
configuration

Yes

DSITimingCLKPreOverride

Boolean

DSI hardware
configuration

Yes

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Configuration Guide for Display Drivers (ACPI and XML)

Panel name

Type
(size in bytes)

Supported tag list

Purpose

Firmware
(UEFI)
supported

Graphics
KMD
supported

DSITimingCLKPreValue

Integer(4)

DSI hardware
configuration

Yes

DSITimingCLKPostOverride

Boolean

DSI hardware
configuration

Yes

DSITimingCLKPostValue

Integer(4)

DSI hardware
configuration

Yes

DSITimingTASureOverride

Boolean

DSI hardware
configuration

Yes

DSITimingTASureValue

Integer(4)

DSI hardware
configuration

Yes

DSITimingTAGoOverride

Boolean

DSI hardware
configuration

Yes

DSITimingTAGoValue

Integer(4)

DSI hardware
configuration

Yes

DSITimingTAGetOverride

Boolean

DSI hardware
configuration

Yes

DSITimingTAGetValue

Integer(4)

DSI hardware
configuration

Yes

DSITrafficMode

Integer(4)

DSI hardware
configuration

Yes

DSIHsaHseAfterVsVe

Boolean

DSI hardware
configuration

Yes

DSILowPowerModeInHFP

Boolean

DSI hardware
configuration

Yes

DSILowPowerModeInHBP

Boolean

DSI hardware
configuration

Yes

DSILowPowerModeInHSA

Boolean

DSI hardware
configuration

Yes

DSILowPowerModeInBLLPEOF

Boolean

DSI hardware
configuration

Yes

DSIForceCmdInVideoHS

Boolean

DSI hardware
configuration

Yes

DSILowPowerModeInBLLP

Boolean

DSI hardware
configuration

Yes

DSICMDSwapInterface

Boolean

DSI hardware
configuration

Yes

DSICMDUsingTrigger

Boolean

DSI hardware
configuration

Yes

DSITECheckEnable

Boolean

DSI hardware
configuration

Yes

DSITEUsingDedicatedTEPin

Boolean

DSI hardware
configuration

Yes

DSITEvSyncStartPos

Integer(4)

DSI hardware
configuration

Yes

DSITEvSyncContinueLines

Integer(4)

DSI hardware
configuration

Yes

DSITEvSyncStartLineDivisor

Integer(4)

DSI hardware
configuration

Yes

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Configuration Guide for Display Drivers (ACPI and XML)

Panel name

Type
(size in bytes)

Supported tag list

Purpose

Firmware
(UEFI)
supported

Graphics
KMD
supported

DSITEvSyncPosSafetyMargin

Integer(4)

DSI hardware
configuration

Yes

DSITEvSyncBelowSafetyMargin

Integer(4)

DSI hardware
configuration

Yes

DSITEPercentVariance

Integer(4)

DSI hardware
configuration

Yes

DSITEvSyncRdPtrIrqLine

Integer(4)

DSI hardware
configuration

Yes

DSIDataStrengthLP

Integer(4)

DSI hardware
configuration

Yes

DSIDataStrengthHS

Integer(4)

DSI hardware
configuration

Yes

DSIClockStrengthHS

Integer(4)

DSI hardware
configuration

Yes

DSIEnableAutoRefresh

Boolean

DSI hardware
configuration

Yes

DSIAutoRefreshFrameNumDiv

Integer(4)

DSI hardware
configuration

Yes

DSIPhyDCDCMode

Boolean

DSI hardware
configuration

Yes

DSIInitSequence

Binary

DSI panel
configuration

Yes

DSITermSequence

Binary

DSI panel
configuration

Yes

DSIStatusSequence

Binary

DSI panel status
check

Yes

DSIDisableEoTAfterHSXfer

Boolean

DSI hardware
configuration

Yes

DSIInitMasterTime

Integer(4)

DSI hardware
configuration

Yes

DSIDmaDelayAfterVsync

Integer(4)

DSI DMA
scheduling

Yes

DSITEvSyncSelect

Integer(4)

DSI hardware
configuration

Yes

DSICmdModeIdleTime

Integer(4)

DSI hardware
configuration

Yes

DSIFBCEnable

Boolean

Display/DSI
hardware
configuration

Yes

DSIFBCProfileID

Integer(4)

Display/DSI
hardware
configuration

Yes

DSIControllerMapping

Integer List(16)

DSI hardware
configuration

Yes

DSISlaveControllerSkewLines

Integer(4)

DSI hardware
configuration

Yes

DSITransferRetryCntr

Integer(4)

DSI hardware
configuration

Yes

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Configuration Guide for Display Drivers (ACPI and XML)

Panel name

Type
(size in bytes)

Supported tag list

Purpose

Firmware
(UEFI)
supported

Graphics
KMD
supported

DSINullpacketInsertionBytes

Integer(4)

DSI hardware
configuration

Yes

DSIFlags

Integer(4)

DSI hardware
configuration

Yes

DSIDSCEnable

Boolean

DSI hardware
configuration

Yes

DSIDSCProfileId

Integer(4)

DSI hardware
configuration

Yes

DSIDSCSliceHeight

Integer(4)

DSI hardware
configuration

Yes

DSIDSCSliceWidth

Integer(4)

DSI hardware
configuration

Yes

DSIDSCMajorVersion

Integer(4)

DSI hardware
configuration

Yes

DSIDSCMinorVersion

Integer(4)

DSI hardware
configuration

Yes

DSIDSCScrVersion

Integer(4)

DSI hardware
configuration

Yes

EDPRefreshRate

Integer(4)

eDP hardware
configuration

Yes

EDPTraining

Integer(4)

eDP hardware
configuration

Yes

EDPPixelClockFrequency

Integer(4)

eDP hardware
configuration

Yes

EDPDPCDRead

Boolean

eDP hardware
configuration

Yes

EDPEDIDRead

Boolean

eDP hardware
configuration

Yes

EDPNumberOfLanes

Integer(4)

eDP hardware
configuration

Yes

EDPLinkRate

Integer(4)

eDP hardware
configuration

Yes

EDPASSREnable

Boolean

eDP hardware
configuration

Yes

EDPEnhancedFrameEnable

Boolean

eDP hardware
configuration

Yes

EDPMaxLinkRate

Integer(4)

eDP hardware
configuration

Yes

EDPRGBMap

Integer(4)

eDP hardware
configuration

Yes

EDPLaneMap

Integer(4)

eDP hardware
configuration

Yes

EDPHPDActiveLow

Boolean

eDP hardware
configuration

Yes

EDPDynamicRefreshRates

Integer List

eDP hardware
configuration

Yes

eDP Configuration

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Configuration Guide for Display Drivers (ACPI and XML)

Panel name

Type
(size in bytes)

Supported tag list

Purpose

Firmware
(UEFI)
supported

Graphics
KMD
supported

EDPStatusSequence

Binary

eDP panel status
check

Yes

EDPPowerUpWaitInMs

Integer(4)

eDP hardware
configuration

Yes

EDPMaxAuxRetry

Integer(4)

eDP hardware
configuration

Yes

HDMIAviInfoFramePacketsDisable

Boolean

HDMI hardware
configuration

Yes

HDMIOutVoltageSwingCtrlEnable

Boolean

HDMI hardware
configuration

Yes

HDMIOutVoltageSwingCtrl

Integer(4)

HDMI hardware
configuration

Yes

HDMIMaxNumReAuthentication

Integer(4)

HDMI hardware
configuration

Yes

HDMIMaxModeWidth

Integer(4)

HDMI hardware
configuration

Yes

HDMIMaxModeHeight

Integer(4)

HDMI hardware
configuration

Yes

HDMIMaxModeRefreshRate

Integer(4)

HDMI hardware
configuration

Yes

HDMIMinModeWidth

Integer(4)

HDMI hardware
configuration

Yes

HDMIMinModeHeight

Integer(4)

HDMI hardware
configuration

Yes

HDMIMinModeRefreshRate

Integer(4)

HDMI hardware
configuration

Yes

HDMIInjectedModeList

Integer List

HDMI hardware
configuration

Yes

HDMIDDCTimeoutInMs

Integer(4)

HDMI hardware
configuration

Yes

BacklightType

Integer(4)

Backlight
configuration

Yes

BacklightPmicModel

Integer(4)

Backlight
configuration

Yes

BacklightPMICNum

Integer(4)

Backlight
configuration

Yes

BacklightPmicControlType

Integer(4)

Backlight
configuration

Yes

BacklightPMICBankSelect

Integer(4)

Backlight
configuration

Yes

BacklightPMICPWMFrequency

Integer(4)

Backlight
configuration

Yes

BacklightSteps

Integer(4)

Backlight
configuration

Yes

HDMI Configuration

Backlight Configuration

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Configuration Guide for Display Drivers (ACPI and XML)

Panel name

Type
(size in bytes)

Supported tag list

Purpose

Firmware
(UEFI)
supported

Graphics
KMD
supported

BacklightDefault

Integer(4)

Backlight
configuration

Yes

BacklightLowPower

Integer(4)

Backlight
configuration

Yes

BacklightPmicAdvancedConfig

Boolean

Advance WLED
backlight
configuration

Yes

BacklightPmicWledInternalModResol
ution

Integer(4)

Advance WLED
backlight
configuration

Yes

BacklightPmicWledModulationClkSel

Integer(4)

Advance WLED
backlight
configuration

Yes

BacklightPmicWledDimmingMethod

Integer(4)

Advance WLED
backlight
configuration

Yes

BacklightPmicWledOvp

Integer(4)

Advance WLED
backlight
configuration

Yes

BacklightPmicWledIlim

Integer(4)

Advance WLED
backlight
configuration

Yes

BacklightPmicWledFeedbackCtrl

Integer(4)

Advance WLED
backlight
configuration

Yes

BacklightPmicWlepLoopCompRes

Integer(4)

Advance WLED
backlight
configuration

Yes

BacklightPmicWledVrefControl

Integer(4)

Advance WLED
backlight
configuration

Yes

BacklightPmicWledFullScaleCurrent

Integer(4)

Advance WLED
backlight
configuration

Yes

BacklightPmicWledModulatorSrcSel

Integer(4)

Advance WLED
backlight
configuration

Yes

CABLMinUserLevel

Integer(4)

CABL
configuration

Yes

CABLMinBacklightLevel

Integer(4)

CABL
configuration

Yes

CABLFilterThreshold

Integer(4)

CABL
configuration

Yes

Display1Reset1Info

String(64)

Platform GPIO
configuration

Yes

Display1Power1Info

String(64)

Platform GPIO
configuration

Yes

CABL Configuration

Platform Hardware Configuration

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Configuration Guide for Display Drivers (ACPI and XML)

Panel name

Type
(size in bytes)

Supported tag list

Purpose

Firmware
(UEFI)
supported

Graphics
KMD
supported

Display1Power2Info

String(64)

Platform GPIO
configuration

Yes

Display1Power3Info

String(64)

Platform GPIO
configuration

Yes

Display1I2C1Info

String(64)

Platform I2C
configuration

Yes

Display1I2C2Info

String(64)

Platform I2C
configuration

Yes

Display1Special1Info

String(64)

Platform GPIO
configuration

Yes

Display4Reset1Info

String(64)

Platform GPIO
configuration

Yes

Display4Power1Info

String(64)

Platform GPIO
configuration

Yes

Display4Power2Info

String(64)

Platform GPIO
configuration

Yes

Display4Power3Info

String(64)

Platform GPIO
configuration

Yes

Display4Special1Info

String(64)

Platform GPIO
configuration

Yes

PMIPowerPmicModel

Integer(4)

PMIC Power
configuration

Yes

PMIPowerPmicNum

Integer(4)

PMIC Power
configuration

Yes

PMIPowerConfig

Integer(4)

PMIC Power
configuration

Yes

DynamicEDIDEnabled

Boolean

Dynamic EDID
configuration

Yes

DynamicEDIDI2CSlaveAddress

Integer(4)

Dynamic EDID
configuration

Yes

DynamicEDIDI2CFrequency

Integer(4)

Dynamic EDID
configuration

Yes

DynamicEDIDI2CGSBIPort

Integer(4)

Dynamic EDID
configuration

Yes

DynamicEDIDPTM

Integer(4)

Dynamic EDID
configuration

Yes

DynamicEDIDStartAddress

Integer(4)

Dynamic EDID
configuration

Yes

AdaptiveBrightnessFeature

Integer(4)

Adaptive
brightness
configuration

Yes

CABLEnable

Boolean

Adaptive
brightness
configuration

Yes

Dynamic EDID Configuration

Adaptive Brightness

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Configuration Guide for Display Drivers (ACPI and XML)

Panel name
SVIEnable

Type
(size in bytes)

Supported tag list

Purpose

Firmware
(UEFI)
supported

Graphics
KMD
supported

Boolean

Adaptive
brightness
configuration

Yes

ADEnable

Boolean

AD configuration

Yes

ADMaxIterations

Integer(4)

AD configuration

Yes

Assertive Display (AD)

ADStrengthLimit

Integer(4)

AD configuration

Yes

ADBacklightMin

Integer(4)

AD configuration

Yes

ADBacklightMax

Integer(4)

AD configuration

Yes

ADAmbientLightMin

Integer(4)

AD configuration

Yes

ADCalibrationA

Integer(4)

AD configuration

Yes

ADCalibrationB

Integer(4)

AD configuration

Yes

ADCalibrationC

Integer(4)

AD configuration

Yes

ADCalibrationD

Integer(4)

AD configuration

Yes

ADFilterA

Integer(4)

AD configuration

Yes

ADFilterB

Integer(4)

AD configuration

Yes

ADTFilterControl

Integer(4)

AD configuration

Yes

ADAssymetry

Binary

AD configuration

Yes

ADColorCorrection

Binary

AD configuration

Yes

ADSensorLinearization

Binary

AD configuration

Yes

ADPrivateData

Binary

AD configuration

Yes

Integer(4)

Power saving

Yes

SharpeningEdgeThreshold

Integer(4)

Sharpening

Yes

SharpeningSmoothThreshold

Integer(4)

Sharpening

Yes

SharpeningNoiseThreshold

Integer(4)

Sharpening

Yes

TLMMGPIODefaultLow

Integer list(8)

GPIO
configuration

Yes

TLMMGPIODefaultHigh

Integer list(8)

GPIO
configuration

Yes

Power saving configuration
DisplayPowerSavingOverride
Sharpening Configuration

GPIO Configuration

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5 Panel configuration tag descriptions

5.1 Informational fields
The fields listed in Table 5-1 are used for informational purposes only. They are optional fields
that may or may not be parsed or used.
Table 5-1 Informational fields
Tag
PanelDescription

Description
Used for debugging purposes

5.2 EDID fields
The graphics KMD needs to report accurate EDID information about all monitors, internal and
external. For details, see VESA Enhanced Extended Display Identification Data – Implementation
Guide (Version 1.0 (June 2001)).
Only the first 128-byte block of the EDID is reported to the operating system. No extension
blocks are supported.

5.2.1 Static EDID fields
The following fields are statically defined in the panel configuration and reported as is to the
operating system as shown in Table 5-2. The OEM is responsible for populating these fields to
meet the panel definition.
Table 5-2 Static EDID fields
Tag

EDID field
offset

EDID field description

PanelName

58h

Detailed timing #3 or display descriptor

ProductCode

0Ah

ID product code

SerialNumber

0Ch

ID serial number

WeekofManufacture

10h

Week of manufacture

YearofManufacture

11h

Year of manufacture

EDIDVersion

12h

Version number

EDIDRevision

13h

Revision number

VideoInputDefinition

14h

Video input definition

HorizontalScreenSize

15h

Horizontal screen size in cm of aspect ratio

VerticalScreenSize

16h

Vertical screen size in cm of aspect ratio

DisplayTransferCharacteristics

17h

Display transfer characteristics (gamma)

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Configuration Guide for Display Drivers (ACPI and XML)

Tag

EDID field
offset

FeatureSupport

18h

Panel configuration tag descriptions

EDID field description
Feature support

Red.GreenBits

19h

Red/green low order bits

Blue.WhiteBits

1Ah

Blue/white low order bits

RedX

1Bh

Red-x high order bits

RedY

1Ch

Red-y high order bits

GreenX

1Dh

Green-x high order bits

GreenY

1Eh

Green-y high order bits

BlueX

1Fh

Blue-x high order bits

BlueY

20h

Blue-y high order bits

WhiteX

21h

White-x high order bits

WhiteY

22h

White-y high order bits

EstablishedTimingsI

23h

Established timings I

EstablishedTimingsII

24h

Established timings I

ManufacturesTiming

25h

Established timings I

StandardTimings1

26h

Standard timing 1

StandardTimings2

28h

Standard timing 2

StandardTimings3

2Ah

Standard timing 3

StandardTimings4

2Ch

Standard timing 4

StandardTimings5

2Eh

Standard timing 5

StandardTimings6

30h

Standard timing 6

StandardTimings7

32h

Standard timing 7

StandardTimings8

34h

Standard timing 8

5.2.2 Detailed timing fields
A single mode is populated in the detailed timing fields based on the EDID configuration given in
Table 5-3, which describes how fields can be overwritten from the detailed timing descriptors.
Table 5-3 Detailed timing fields
Tag

Detailed timing
offset

Detailed timing description

HorizontalScreenSizeMM

0Ch

Horizontal addressable video image size in mm
(lower 8 bits)

VerticalScreenSizeMM

0Dh

Vertical addressable video image size in mm
(lower 8 bits)

HorizontalVerticalScreenSizeMM

0Eh

Vertical and horizontal upper 4 bits

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Configuration Guide for Display Drivers (ACPI and XML)

Panel configuration tag descriptions

5.2.3 EDID information
Correct EDID information is important to the overall user experience. Inaccurate or invalid EDID
information could result in an overall unpleasant user experience. Specifically, screen dimensions
are important to the overall look and feel of the user interface.
The screen size in both cm and mm must be reported, e.g., if the phone dimensions are 5.8 cm
and 10.3 cm, as shown in Figure 5-1, the EDID would be populated as shown below.

5.8cm

10.3cm

5
10

58
103
2

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Configuration Guide for Display Drivers (ACPI and XML)

Display interface-specific configurations

Tag

Description

DSIEscapeClockFrequ
ency

When DSIEscapeClockDivisor is used this fileld must be populated with the
expected escape clock frequency.
This expected clock frequency is used to adjust all of the other DSI D Phy
timings. As there is no feedback mechanism for the driver to know the exact
escape clock frequency if it is not derived from CXO (19.2 MHz), the user must
pass in the exact value in hertz.
Incorrectly enabling the escape clock divisor or not properly setting this
frequency will result in DSI timings that are out of specification.
For a 17 MHz escape clock:
< DSIEscapeClockFrequency>17000000

DSITransferRetryCntr

When sending and receving DCS commands (BTA), the driver will attempt to
retry upon failure of the original command.
This field allows the OEM to adjust the number of attempts for any read or write
command before it gives up and returns an error.
The default value is 2 (meaning 2 total attempts), but this can be disabled or
increased based on the requirements.

DSINullpacketInsertion
Bytes

During pixel data transmission, the controller idles the data lanes (LP00)
between pixel tranmissions. Enabling this configuration forces the controller to
insert NULL packets to keep the data lanes in HS.
The value represents the size of the NULL packets; a value of 0 means
disabled.

DSIFlags

This field is an integer that represents a bitwise mask of DSI configuration
options.
The following table lists valid values.
Value
(decimal)

80-NB116-2 G

Definition

0x0001

QDI_PANEL_DSI_FLAG_DSI_DCS_FIFO_ONLY
This flag forces the driver to use a FIFO to send DCS
packets instead of a DMA buffer. This option reduces
the latency for start of packet transmission but limits the
maximum packet size that can be sent to 64 bytes total
including headers.

0x0002

QDI_PANEL_DSI_FLAG_DSI_DISABLE_BURST_MOD
E
This flag disables Burst mode which allows DMA
packets to interleave between pixel data transfers. By
default the hardware is configured to burst all pixel data
together without interruption.
The default configuration is the most optimal and this
flag should typically not be needed.

0x0004

QDI_PANEL_DSI_FLAG_DISABLE_PPS_CMD
This flag disables sending of the PPS packets when
MIPI DSC is enabled. When disabled the driver will not
automatically send the PPS packets during panel
initialization. Some panels do not support PPS packets
and this flag should be set for those panels.

All other values

Reserved

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Configuration Guide for Display Drivers (ACPI and XML)

Display interface-specific configurations

8.1.2 Display stream compression (DSC)
Table 8-2 shows the parameters used to configure the DSC module for DSI.
Table 8-2 Parameters to configure the DSC module for DSI
NOTE:

The following table has been updated.
Tag

Description

DSIDSCEnable

This Boolean flag determines whether to enable the DSC feature in MDSS. This
requires a DSI panel supporting DSC.

DSIDSCProfileID

This integer specifies the index in the profile table that describes the DSC
configuration.

LM split

Block
prediction

Compression
ratio

Yes

Encoder

0
1

Table definitions:
 Encoder – Number of DSC instances (one per 4-lane controller).
 LM split – MDSS layer mixer split configuration used
 Block prediction – Enable block prediction
 Compression ratio – DSC compression ratio
 Slice height – DSC slice height
 Slice width – DSC slice width
DSIDSCSliceHeight

This integer specifies the DSC slice height in pixels.

DSIDSCSliceWidth

This integer specificies the DSC slice width in pixels.

DSIDSCMajorVersion

The DSC version specification supported by the panel. Must be 1 for v1.x

DSIDSCMinorVersion

The DSC version specification supported by the panet. 0 (v1.0) and 1 (v1.1) are
supported.

DSIDSCScrVersion

The rate control parameters configuration, default is 0, or 1 for rate control set 1.

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Configuration Guide for Display Drivers (ACPI and XML)

Display interface-specific configurations

8.1.3 Init sequence timing
To meet the requirements of varying panel hardware, the initialization sequence can be tuned
based on particular DSI parameters, shown in Figure 8-1.

Panel Power Rails

Panel Reset Pin
B

Data Lanes

LP Data

LP11

HS Data
C

Clock Lane

HS Clock

Figure 8-1 Init sequence timing
Init sequence timing depends on the following parameters:
a. DSILP11AtInit – MIPI Alliance Specification for Display Serial Interface (Version
1.03.00 (August 2011)) requires the data and clock lanes to be in the LP11 state after the
reset pin has been deasserted. In previous revisions of the specification, the lanes were
required to be in LP11 before the reset had been asserted. The DSILP11AtInit
configuration allows licensees to force the lanes to LP11 before the reset is asserted; the
default behavior is to assert LP11 after reset.
b. DSIInitMasterTime – After asserting LP11, the panel IC may require additional delay
times to complete initialization before the first DCS command can be recognized. By
default the minimum delay is 2 ms, however, the licensee can overwrite this to any value.
c. DSIClockHSForceRequest – Some panel ICs may require the host to drive the clock
lanes to HS. Typically this is done if the panel IC requires an external oscillator. This
configuration allows for three options:

80-NB116-2 G

–

Clock lane is only transitioned into HS during a HS data transmission (default).

–

Clock lane is always in HS.

–

Clock lane is in HS after the init sequence is complete.

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Configuration Guide for Display Drivers (ACPI and XML)

Display interface-specific configurations

8.1.4 DSI DCS command configurations
During panel initialization and shutdown, the licensee can send custom panel sequences to
initialize and shut down the panel. Figure 8-2 shows when these commands are sent.

Panel Power on Reset

DSI Init Sequence

DSI Active

DSI Term
Sequence

Panel Power Rails

Panel Reset Pin

Data Lanes

LP11

LP11
LP Data

Clock Lane

HS Data

LP Data

HS Clock

Figure 8-2 DSI DCS command configurations
Table 8-5 shows the DSI DCS command configuration tags.
Table 8-3 DSI DCS command configuration tags
Tag

Description

DSIInitSequence

This is a binary data value that is used to send DCS commands to the panel during
panel initialization (display on). One or multiple packets can be sent using this
sequence; see the binary data type description of how to build a packet.
This data is always sent to the panel in LP mode, e.g.:
05 11 00

DSITermSequence

80-NB116-2 G

; DCS command 5h, followed by two payload
; bytes 11h and 00h

This is a binary data value that is used to send DCS commands to the panel during
panel termination (display off). One or multiple packets can be sent using this
sequence; see the binary data type description of how to build a packet.
This data is always sent to the panel in LP mode.

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Display interface-specific configurations

8.1.5 Supported DCS commands
Any valid DCS command and payload can be sent. Table 8-4 provides examples of the valid DCS
commands supported. For more details, see MIPI Alliance Specification for D-PHY (Version
1.00.00 (May 2009)).
Table 8-4 Supported DCS commands
Command
(hex)

Payload size
(bytes)

Generic short write, no parameters

Generic short write, 1 parameter

Generic short write, 2 parameters

DCS short write, no parameters

DCS short write, 1 parameter

Generic long write

Definition

Other commands may not be supported or may be reserved.

8.1.6 Special DCS commands
There are certain reserved commands that can be used and are interpreted by the driver as having
a special meaning. These commands are not valid DCS commands but are intercepted by the
driver to have a special function as shown in Table 8-5.
Table 8-5 Special DCS commands
Command
(hex)

Payload size
(bytes)

Stall between commands; payload is used to indicate the number of
milliseconds to stall between commands; valid range is 1 to 255; example:
 05 11 00 – DCS command 5 h, with 11 h as payload
 FF 5C – Wait for 92 ms
 05 15 00 – DCS command 5 h, with 15 h as payload

Configure MDP to output constant color to clear the display frame buffer
for smart panel. The payload is used to indicate the desired constant color
in RGB format. Valid range for each color component is 0 to 255. The
default color is black if no payload is specified, e.g.:
 FE FF FF 00 – Configure MDP to output yellow constant color
If this command is used during panel initialization, then constant color will
be sent to the panel to clear the random garbage data in the display
module buffer.
If this command is used during display reset while MDP has already been
configured, the last frame in MDP is sent to the panel.

Broadcast mask used to mask which controller(s) the command is sent to;
this is only valid for dual-DSI applications.

Definition

Mask (hex)

80-NB116-2 G

Definition

0x1

Command is sent to controller 0; default

0x2

Command is sent to controller 1

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Configuration Guide for Display Drivers (ACPI and XML)

Display interface-specific configurations

8.1.7 DSI interface timing overrides
The DSI timings are automatically calculated based on the required refresh rate/bit clock
frequency. If the panel has specific timing requirements, the adjustment for each timing can be
overridden. Table 8-6 lists of DSI interface timing overrides.
Table 8-6 DSI interface timing overrides
Tag

Units

DSITimingHSZeroOverride

Boolean

DSITimingHSZeroValue

Integer

DSITimingHSExitOverride

Boolean

DSITimingHSExitValue

Integer

DSITimingHSPrepareOverride

Boolean

DSITimingHSPrepareValue

Integer

DSITimingHSTrailOverride

Boolean

DSITimingHSTrailValue

Integer

DSITimingHSRequestOverride

Boolean

DSITimingHSRequestValue

Integer

DSITimingCLKZeroOverride

Boolean

DSITimingCLKZeroValue

Integer

DSITimingCLKTrailOverride

Boolean

DSITimingCLKTrailValue

Integer

DSITimingCLKPrepareOverride

Boolean

DSITimingCLKPrepareValue

Integer

DSITimingCLKPreOverride

Boolean

DSITimingCLKPreValue

Integer

DSITimingCLKPostOverride

Boolean

DSITimingCLKPostValue

Integer

DSITimingTASureOverride

Boolean

DSITimingTASureValue

Integer

DSITimingTAGoOverride

Boolean

DSITimingTAGoValue

Integer

DSITimingTAGetOverride

Boolean

DSITimingTAGetValue

Integer

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Notes
See MIPI Alliance Specification for D-PHY
(Version 1.00.00 (May 2009)) for details on each
timing parameter.

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Display interface-specific configurations

8.1.8 DSI Video mode configuration
Table 8-7 lists configurations specific to DSI Video mode.
Table 8-7 DSI Video mode configuration
Tag
DSITrafficMode

Description
Integer defining the DSI Traffic mode for operation; this value is based
on the QDI_DSITrafficModeType enumeration.
Value
(decimal)

Definition

QDI_DSIVideoTrafficMode_NonBurst_VSPulse

QDI_DSIVideoTrafficMode_NonBurst_VSEvent

QDI_DSIVideoTrafficMode_Burst

All other values are invalid or not supported.
DSIHsaHseAfterVsVe

This Boolean determines whether the hardware should send horizontal
sync pulses during the vertical blanking period.
Value
(Boolean)

DSILowPowerModeInHFP

FALSE

Do not send a horizontal start/end packet after
the vertical sync/end

TRUE

Send a horizontal start/end packet after the
vertical sync/end

This Boolean determines the DSI lane state during a Horizontal Front
Porch (HFP) blanking period.
Note: It is recommended that this value be set to TRUE for LP mode if
the panel supports this feature. Forcing the lanes to HS during this
period will consume additional power and prevent DCS commands
from being sent during this period.
Value
(Boolean)

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Definition

FALSE

The DSI clock and lanes should stay in HS
mode during the HFP blanking period. The
hardware will send blanking packets during this
period.

TRUE

The DSI clock and lanes should enter LP mode
during the HFP blanking period.

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Tag
DSILowPowerModeInHBP

Description
This Boolean determines the DSI lane state during the Horizontal
Blanking Period (HBP).
Note: It is recommended that this value be set to TRUE for LP mode if
the panel supports this feature. Forcing the lanes to HS during this
period will consume additional power and prevent DCS commands
from being sent during this period.
Value (Boolean)

DSILowPowerModeInHSA

DSILowPowerModeInBLLPEOF

FALSE

The DSI clock and lanes should stay in HS
mode during the HBP. The hardware sends
blanking packets during this period.

TRUE

The DSI clock and lanes should enter LP mode
during the HBP.

This Boolean determines the DSI lane state during Horizontal Sync
Active (HSA).
Note: It is recommended that this value be set to TRUE for LP mode if
the panel supports this feature. Forcing the lanes to HS during this
period will consume additional power and prevent DCS commands
from being sent during this period.
Value (Boolean)

Definition

FALSE

The DSI clock and lanes should stay in HS
mode during the Horizontal Sync Period (HSP).
The hardware will send blanking packets during
this period.

TRUE

The DSI clock and lanes should enter LP mode
during the HSP.

This Boolean determines the DSI lane state during the last line of the
Blanking Low Power Period (BLLP).
Note: It is recommended that this value be set to TRUE for LP mode if
the panel supports this feature. Forcing the lanes to HS during this
period will consume additional power and prevent DCS commands
from being sent during this period.
Value (Boolean)

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Definition

FALSE

The DSI clock and lanes should stay in HS
mode during the last line of the BLLP. The
hardware will send blanking packets during this
period.

TRUE

The DSI clock and lanes should enter LP mode
during the last line of the BLLP.

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Tag
DSILowPowerModeInBLLP

Description
This Boolean determines the DSI lane state during BLLP.
Note: It is recommended that this value be set to TRUE for LP mode if
the panel supports this feature. Forcing the lanes to HS during this
period will consume additional power and prevent DCS commands
from being sent during this period.
Value (Boolean)

Definition

FALSE

The DSI clock and lanes should stay in HS
mode during the BLLP. The hardware will send
blanking packets during this period.

TRUE

The DSI clock and lanes should enter LP mode
during the BLLP.

DSIDmaDelayAfterVsync

This integer is used in the DSI DMA read/write scheduling in Video
mode. The software schedules the DSI DMA operations when the DSI
controller is busy transferring pixel data, and the DMA packets are sent
to the panel when pixel transfer is done by the hardware. This integer
decides the number of milliseconds after vsync that the software can
trigger the DMA packets transfer.

DSIPixelXferTiming (replacement for
DSIForceCmdInVideoHS)

Integer defining the scenarios to enable/disable the video HS pixel data
transfer for initialization and termination sequence. This value is based
on the DSIPixelXferTiming enumeration.
Any combination of enumerations can be combined to meet the init and
termination sequence requirements. Disabling and enabling bits cannot
be combined together.
Value
(decimal)

DSIForceCmdInVideoHS (to be
deprecated)

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Definition

QDI_DSI_PIXEL_TX_DISABLED_DURING_INIT_TERM
High-speed video data is disabled during the init
sequence.

QDI_DSI_PIXEL_TX_ENABLED_DURING_INIT
High-speed video data is enabled during the init
sequence.

QDI_DSI_PIXEL_TX_ENABLED_DURING_TERM
High-speed video data is disabled during the termination
sequence.

QDI_DSI_PIXEL_TX_ENABLED_DURING_INIT_TERM
High-speed video data is enabled during the termination
sequence.

Video HS pixel data will be started before the initialization sequence
from the OEM/ACPI has been sent to the panel. Video HS pixel data
transfer will be active even during the termination sequence from the
OEM/ACPI.

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Tag
DSIDynamicRefreshRates

Display interface-specific configurations

Description
The refresh rates supported by the panel other than the default refresh
rate; this is a list of refresh rates in Q16.16 format, e.g.:
0x3C0000
0x320000
Adds 48 Hz and 50 Hz respectively to the list of supported refresh
rates.
The driver may prune refresh rates from this list based on the
capabilities of the display hardware. Not all interfaces and panel
configurations support dynamic refresh changes.
Note: The list of frequencies can be in any order, but the default
refresh rate must appear first.

DSIDynamicBlankingRefreshRateList

Refresh rates supported by the panel by adjusting the panel blanking; it
is the licensee’s responsibility to calibrate and configure the blanking
configuration. This is a list of refresh rates in Q16.16 format, e.g.:

0x3C0000
0x300000
0x320000

Adds 48 Hz and 50 Hz respectively to the list of supported refresh rates
that can be achieved by adjusting the panel blanking.
Note: The list of frequencies can be in any order, but the default
refresh rate must appear first.

DSIDynamicVFrontPorchList

Vertical front porch adjustment is part of the dynamic blanking
configuration required to achieve a particular refresh rate, e.g.:

0x07
0x09
0x05

These vertical front porch values correspond one to one with the
refresh rates in DSIDynamicBlankingRefreshRateList and must be in
the same order.

DSIDynamicVBackPorchList

Vertical back porch adjustment is part of the dynamic blanking
configuration required to achieve a particular refresh rate, e.g.:

0x06
0x07
0x05

These vertical back porch values correspond one to one with the
refresh rates in DSIDynamicBlankingRefreshRateList and must be in
the same order.

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Tag
DSIDynamicVSyncPulseList

Display interface-specific configurations

Description
Vsync pulse adjustment is part of the dynamic blanking configuration
required to achieve a particular refresh rate, e.g.:

0x03
0x04
0x02

These vsync pulse values correspond one to one with the refresh rates
in DSIDynamicBlankingRefreshRateList and must be in the same
order.

DSIDynamicHFrontPorchList

Horizontal front porch adjustment is part of the dynamic blanking
configuration required to achieve a particular refresh rate, e.g.:

0x03
0x04
0x03

These horizontal front porch values correspond one to one with the
refresh rates in DSIDynamicBlankingRefreshRateList and must be in
the same order.

DSIDynamicHBackPorchList

Horizontal back porch adjustment is part of the dynamic blanking
configuration required to achieve a particular refresh rate, e.g.:

0x03
0x03
0x02

These horizontal back porch values correspond one to one with the
refresh rates in DSIDynamicBlankingRefreshRateList and must be in
the same order.

DSIDynamicHSyncPulseList

Hsync pulse adjustment is part of the dynamic blanking configuration
required to achieve a particular refresh rate, e.g.:

0x03
0x03
0x01

These hsync pulse values correspond one to one with the refresh rates
in DSIDynamicBlankingRefreshRateList and must be in the same
order.

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8.1.9 DSI Command mode configuration
Table 8-8 lists configurations specific to DSI Command mode.
Table 8-8 DSI Command mode configuration
Tag

Description

DSICMDSwapInterface

Reserved Boolean, must be FALSE or leave as undefined

DSICMDUsingTrigger

Reserved Boolean, must be FALSE or leave as undefined

DSITECheckEnable

This Boolean enables the TE check hardware block within MDP.
Value (Boolean)

DSITEUsingDedicatedTEPin

Definition

FALSE

Tear check hardware block is disabled

TRUE

Tear check hardware block is enabled

This Boolean enables the TE via an external GPIO or via an
embedded-TE signal.
Value (Boolean)

Definition

FALSE

TE uses an internal TE signal, embedded TE

TRUE

TE uses a dedicated GPIO, external TE signal

DSITEvSyncStartPos

Line number from which the TE kickoff condition is evaluated for vertical
synchronization

DSITEvSyncRdPtrIrqLine

This integer configures the scanline number that the DSI pixel transfer
will start on. This should be retained at the default value of 0. Adjusting
this number to a higher value results in delaying the start of the pixel
transfer.

DSITEvSyncContinueLines

This integer represents the difference in the number of lines between the
estimated read and write pointers to allow updating of all the lines except
the first line of the frame. This threshold is maintained only when Tear
Check block is enabled.

DSITEvSyncStartLineDivisor

This integer represents the fraction of the total height from the top, within
which the read pointer should fall, so as to allow the first line update of
the frame. This threshold is maintained only when Tear Check block is
enabled.
For example, if this value is set to 4 and height is 100 lines, then only
when the internal read pointer falls between 0 to 25 (=100/4) lines is the
first line of the frame updated.
Valid range is from 2 to height, default value is 4 (25%)
See Section 8.1.10 for more details and examples.

DSITEPercentVariance

This integer is the percent value by which the refresh rate would be
reduced so that the internal estimation of time taken by the panel to read
a line is increased. Fine-tuning of this value ensures that external TE
comes before the internal timer expires.
Valid range is 0 to 100, representing 0% to 100%, default value is 0 (0%)
See Section 8.1.10 for more details and examples.

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Tag
DSIEnableAutoRefresh

Display interface-specific configurations

Description
This Boolean enables the auto-refresh hardware (if available). The
auto-refresh hardware is used to self-trigger the DSI Command mode
engine without software interaction.
Value (Boolean)

Definition

FALSE

Auto-refresh hardware is disabled

TRUE

Auto-refresh hardware is enabled; hardware will
automatically trigger periodic updates based on an
internal counter

DSIAutoRefreshFrameNumDiv

This integer defines the interval at which the auto-refresh hardware is
triggered. Values range from 1 to 4095.
The rate at which the hardware internal counter triggers the DSI
command mode update is based on the formula:
Auto-Refresh Rate = DSIRefreshRate/DSIAutoRefreshFrameNumDiv

DSITEvSyncSelect

This integer defines the external vsync source. Default value is 0, which
indicates it is from the dedicated GPIO pin.
Value (Boolean)

DSICmdModeIdleTime

Definition

HAL_MDP_PINGPONG_VSYNC_SELECT_TYPE_
VSYNC_0_GPIO

HAL_MDP_PINGPONG_VSYNC_SELECT_TYPE_
VSYNC_1_GPIO

HAL_MDP_PINGPONG_VSYNC_SELECT_TYPE_
VSYNC_2_GPIO

HAL_MDP_PINGPONG_VSYNC_SELECT_TYPE_
TE_INTF_0

HAL_MDP_PINGPONG_VSYNC_SELECT_TYPE_
TE_INTF_1

HAL_MDP_PINGPONG_VSYNC_SELECT_TYPE_
TE_INTF_2

HAL_MDP_PINGPONG_VSYNC_SELECT_TYPE_
TE_INTF_3

This integer defines the number of idle cycles to insert in between pixel
data packets. If this configuration is used to enforce a stop state in
between pixel data packets in command demo, the delay must take into
consideration the time to enter and exit the stop state, which includes the
following timings:
t_clk_prepare + t_clk_zero + t_clk_pre + Tlpx +
t_hs_prepare + t_hs_zero + t_hs_sync +t_hs_exit +
t_hs_trail + t_clk_post + t_clk_trail
Valid range is 0 to 0x1FF clock cycles and the default value is 0

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Tag

Description

DSIDisableEoTAfterHSXfer

This Boolean disables the EoT packet after a HS data burst. The default
value is FALSE.
Value (Boolean)

DSIBitClkScalePercent

Definition

FALSE

EoT packet is appended after a HS burst

TRUE

EoT packet is not sent

In command mode operation, the data transfer rate is typically tuned to
meet the requested refresh rate (DSIRefreshRate). In most cases, this is
16.6 ms (60 fps).
Some margin must be added to this transfer rate to account for system
variances and leave room to transfer DCS commands. The
DSIBitClkScalePercent increases the bitrate by a specific percentage. By
default the variance is 5% but can be decreased or increased to the
required amount. The valid rate is from 1% to 100%. However, there may
be clock limitations that prevent a dramatic increase.

8.1.10 DSI Command mode TE synchronization
Figure 8-3 shows the DSI Command mode TE synchronization.

Panel
Module
DSI Lanes

8x74
SOC

Video
RAM

Scan-out

Figure 8-3 DSI Command mode TE synchronization
MIPI DSI Command mode data transfer synchronization requires the TE signal from the panel
module. The TE signal is used to synchronize the internal data transfer to ensure a safe region
where an update can occur without causing tearing on the display.

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Figure 8-4 shows the DSI data transmission with respect to the panel scanline.

Panel Scanline

DSI Data transmission (Using Tear Check)

DSI Data transmission (No Tear Check)

Video Ram
Pixel n

Pixel 0

Direction of scan-out

Figure 8-4 DSI data transmission with respect to panel scanline
Two basic methods handle this synchronization:


Data transfer behind the scanline (not recommended) – This method requires the DSI link
rate (bitclock) to be configured to the panels refresh rate or faster. The tear check block must
be enabled in order to throttle the data transfer to ensure the write never crosses the current
scanline. The data transfer ahead of the scanline is recommended because it provides a much
simpler solution and increased efficiency on the bus.



Data transfer ahead of the scanline – This method requires the DSI link rate (bitclock) to be
configured equal to the panel’s refresh rate or faster. The teach check block must be disabled
in this configuration. The increased link rate will guarantee that the scanline never catches up
to the data transfer.

8.1.11 Tear check threshold parameters
DSITEPercentVariance
The DSITEPercentVariance represents the percent value by which refresh rate is to be reduced
for the internal timer to ensure that the external TE comes before the internal timer expires. This
can be used for fine-tuning the TE under the conditions when the frequency of the external TE
varies.

8.1.12 Dual DSI configuration
DSIControllerMapping
The DSIControllerMapping field configures the mapping from the logical DSI port to the
physical DSI port. In a single DSI 4-lane configuration, this allows for mapping of the primary
DSI to the secondary DSI port. For example:
0x1

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Without this configuration, the default configuration maps the primary display to the primary DSI
port.
For dual DSI configurations, the mapping informs the driver that two DSI ports are needed and
how those ports should be mapped. The ID order applied in the mapping tag indicates what DSI
port should assigned to the primary and slave DSI ports.
For example, a typical 8-lane dual DSI solution should map the master to DSI port 0 and the slave
to DSI port 1.
0x0 0x1

DSISlaveControllerSkewLines
In dual DSI configurations, the master and slave ports will send their pixel stream at the same
time. For a specific configuration, a skew may be needed. This configuration allows the
controllers to skew the transfers.
The field represents how many lines the slave should be skewed from the master.
To skew (delay) the slave tramission by 2 lines, the following configuration may be used:
2

To skew (delay) the master tramission by 2 lines, a negative value may be used:
-2

8.2 DSI Command mode configuration
8.2.1 Scenario A – Free run transfer (no tear check block)
Panel transfer should start at the start of the TE. It is desired to run the data transfer faster than the
TE, within 14 ms, to guarantee that the update is completed ahead of the TE. No tear check block
is required in such a configuration. Tearing was visible if the transfer was started at line 1, so the
transfer was adjusted to start on line 760.
Configuration

Value

Mode

Command code

Lanes

Resolution

768x1280

Bit depth

24 bpp

Refresh rate

60 Hz

Bitclock rate

 354 MHz – For 16.6 ms transfer
 419 MHz – For 14 ms transfer

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ACPI configuration
0x3C0000
419991600
False
True
760

8.2.2 Scenario B – Using tear check block (transfer throttling)
Panel transfer uses the tear check block to throttle the transfer. The bitclock is calculated by the
driver and is designed to complete the transfer in 16.6 ms (60 Hz).
The internal counter runs 10% slower (percent variance) than 60 Hz. The transfer must fall within
the first quarter of the panel height (start line divisor) and the transfer can be started after the TE
has reached line 2. The transfer should be 3 lines behind the TE (sync continue lines).
Configuration

Value

Mode

Command mode

Lanes

Resolution

768x1280

Bit depth

24 bpp

Refresh rate

60 Hz

ACPI configuration
True
2
3
4
0xa0000

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8.3 eDP configuration
The only required tag for eDP is to select interface 14 (DP) in the InterfaceType tag. Table 8-9
lists optional overrides that could serve to speed up boot time or to work around panel issues.
Table 8-9 eDP configuration
Tag

Description

EDPRefreshRate

This integer is used to specify the refresh rate of the panel in Q16.16
format. This tag allows the OEM to configure the exact refresh rate of the
panel. The driver configures the correct internal clocks to achieve the
requested refresh rate.
Example:
60 Hz = 0x003C0000
58 Hz = 0x003A0000

EDPTraining

This integer can be used to specify the link training type through the AUX
channel.
Value (decimal)

Definition

No link training

Full link training

Fast link training

By default, link training is disabled.
EDPPixelClockFrequency

This allows the licensee to configure an exact pixel clock frequency. The
drive will then calculate the refresh rate based on the requested pixel
clock frequency and will override the value given through
EDPRefreshRate.

EDPDPCDRead

This Boolean value can be used to enable (TRUE) or disable (FALSE)
reading DPCD during initialization of the panel.
If this tag is FALSE, link training is implicitly disabled and the following
tags must be provided:
 EDPNumberOfLanes
 EDPLinkRate
 EDPASSREnable
 EDPEnhancedFrameEnable
By default, DPCD reading is enabled.

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Tag

Display interface-specific configurations

Description

EDPEDIDRead

This Boolean value can be used to enable (TRUE) or disable (FALSE)
reading EDID through the AUX channel.
If this tag is FALSE, the following tags must be provided:
 EDPRefreshRate
 HorizontalActive
 HorizontalFrontPorch
 HorizontalBackPorch
 HorizontalSyncPulse
 HorizontalSyncSkew
 VerticalActive
 VerticalFrontPorch
 VerticalBackPorch
 VerticalSyncPulse
 InvertDataPolarity
 InvertVsyncPolairty
 InvertHsyncPolarity
By default, EDID reading is enabled.

EDPNumberOfLanes

Number to specify number of lanes to use; valid values are 1, 2, and 4. If
this tag is provided, the EDPLinkRate must also be provided.
By default, the number of lanes is calculated programmatically.

EDPLinkRate

Number to specify the link rate of each lane; valid values are 270000 and
162000.
If this tag is provided, the EDPNumberOfLanes must also be provided.
By default, the link rate is calculated programmatically.

EDPASSREnable

This Boolean value can be used to enable (TRUE) or disable (FALSE)
Alternate Scrambler Seed Reset.
By default, this is enabled if both source and sink devices support eDP 1.2
or greater.

EDPEnhancedFrameEnable

This Boolean value can be used to enable (TRUE) or disable (FALSE)
enhanced framing.
By default, this is enabled if both source and sink devices support eDP 1.2
or greater.

EDPHPDActiveLow

This Boolean value can be used to specify if the HPD signal is active low
(TRUE) or active high (FALSE).
By default, HPD is active low.

EDPDynamicRefreshRates

The refresh rates supported by the panel other than the default refresh
rate; this is a list of refresh rates in Q16.16 format.
The driver might prune refresh rates from this list based on the capabilities
of the display hardware.

EDPStatusSequence

This is a binary data value that is used to send AUX read commands to
the panel to decide panel status. Syntax of each command is:

AUX Type: 1->AUX/DPCD, 2->I2C/EDID
Example:

01 05 02 01

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Tag

Display interface-specific configurations

Description

EDPPowerUpWaitInMs

Number to specify the time in milliseconds to wait after panel power up
and before next AUX read/write.
By default the number is 0, meaning no wait.

EDPMaxAuxRetry

Number to specify the trial time after panel power up and before a
successful AUX read/write
The following logic shows the use of EDPPowerUpWaitInMs and
EDPMaxAuxRetry; it will be executed only once after panel power up.
While(loop++2000
This value configures either the WLED or PWM frequency depending
on the BacklightPmicControlType.

BacklightPmicAdvancedConfig

This configuration enables all advanced configuration parameters.
Depending on the PMIC there are several advanced settings; for more
information, see the Advanced WLED configuration and/or PMIC
documentation.

9.3 Sample backlight configurations
9.3.1 WLED configuration (1 WLED string)
1
5
1
0
1
800000
100
80
40
True

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0
3
0
0
5
0
3
2
25
0
False

9.3.2 LPG configuration
1
3
1
0
7
800000
100
80
40

9.4 I2C-based backlight control
If the platform uses I2C to control the backlight level, the BLCP ACPI method is used for
controlling the commands sent to the backlight. See Section 15.2 for more details.

9.5 DSI DCS-based backlight control
If the platform uses a DSI DCS command to control the backlight level, the BLCP ACPI method
is used for controlling the commands sent to the backlight. See Section 15.2 for more details.

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Backlight configuration

9.6 ACPI-based backlight control
If the licensee wishes to control backlight directly from ACPI, this method should be selected.
The BLCP ACPI method is used directly to control the backlight on the platform. The licensee
would be responsible for handling the incoming request within the ACPI BLCP method. An
example configuration is using the ACPI method to directly modify registers to adjust the
backlight.

9.7 CABL configuration
This section of configuration determines how the CABL algorithm behaves. CABL helps reduce
backlight level. However, it retains the apparent brightness of the screen by manipulating the
pixel values. This saves power.
The CABL algorithm is only used for the primary display.
Supplying these tags requires deep understanding on CABL. Documentation on CABL is outside
the scope of this document. All of the following tags are optional, and acceptable default values
are used when not supplied.
Table 9-3 CABL configuration
Tag

Description

CABLMinUserLevel

This defines the lowest level that can be configured as original backlight
level (before CABL algorithm processing) and still keep CABL active; any
level lower than this will deactivate CABL.
The range is 1 to 255, where 255 is 100% backlight level.
This item is important so that CABL can be configured when to deactivate
itself (basically turns off) to save processing power when CABL savings
are not significant.
The default value is 0, meaning algorithm default 75 (30%).

CABLMinBacklightLevel

This defines the lowest backlight level CABL algorithm that will output
even when other calculations give a lower level.
The range is 1 to 255, where 255 is 100% backlight level.
This item limits CABL so that it does not go too low, which can cause
quality degradation. This number should be lower than
CABLMinUserLevel.
The default value is 0, meaning algorithm default of 30 (12%).

CABLFilterThreshold

This configures the maximum backlight change that can happen on each
CABL iteration during regular CABL operation. This prevents huge
backlight changes that might be noticeable to the user.
The range is 1 to 255.
The default value is 0, meaning algorithm default 10 (4%).

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Backlight configuration

9.8 Advanced backlight configuration
Table 9-4 defines the PMIC WLED parameters.
Table 9-4 Backlight configuration
NOTE:

The following table has been updated.
Tag

Description

BacklightPmicAdvancedConfig

Set advance PMIC configuration for backlight control

BacklightPmicWledInternalModResolution

Internal digital modulator configured

BacklightPmicWledModulationClkSel

Digital modulator input clock frequency control

BacklightPmicWledDimmingMethod

Modulator dimming mode control

BacklightPmicWledOvp

Control for the over-voltage protection threshold

BacklightPmicWledIlim

Current limit after soft start is complete

BacklightPmicWledFeedbackCtrl

Forces selection of LED output as feedback node for the
boost

BacklightPmicWlepLoopCompRes

Control to select the compensation resistor

BacklightPmicWledVrefControl

Reference voltage for boost feedback

BacklightPmicWledFullScaleCurrent

Select current sink for the LED

BacklightPmicWledModulatorSrcSel

 1 – External PWM
 0 – Internal digital modulator

BacklightPmicWledCabcEnable

Enable content adaptive backlight control for current sinks

BacklightPmicOLEDWledAvddVoltage

Configures the AVDD voltage for the WLED module in
AMOLED mode.

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10 ESD detection and recovery
configuration

ESD Detection and Recovery is configured using the tags given in Table 10-1 and Table 10-2.
Table 10-1 ESD Detection and Recovery tags
Tag

Description

ESDDetectionTime

This integer (in milliseconds) is used to schedule how fast the ESD detection
and recovery will be running. The default value in ACPI is 0, which means the
ESD Detection and Recovery feature is disabled.

ESDDetectionFailureRetry

This integer is used as a retry count if ESD detection returns failure before
recovery is called. The default value is 5 if this parameter is omitted.

DSIStatusSequence

This is a binary data value that is used to send DCS read commands to the
panel to decide panel status. Syntax of each command is:

Currently, only short DCS command with no parameter is supported, e.g.:
06 0a 1c
; Short DCS command to get panel power mode
; and expected panel response is 0x1C

Table 10-2 Display recovery threshold
Tag
DisplayRecoveryThreshold

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Description
This configuration will set up the threshold for recovery configuration.
The value set in the field will determine the threshold beyond which
display recovery action will be triggered.
If the value is set to 0, the recovery feature is disabled.
Unit is in number of vsyncs. It is recommended that this should be less
than 120 (2 sec) to avoid a TDR from resetting the display before it can
self-recover.

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11 AD core configuration (preliminary)

The AD Core is configured using the tags given in Table 11-1.
Table 11-1 AD core tags
Tag

Description

ADEnable

This Boolean can be used as a master enable for the AD core.
Setting this tag as TRUE does not necessarily enable the core. Other
programmatic decisions might prevent the core from being enabled.

ADMaxIterations

Number of iterations needed by the AD core to converge

ADStrengthLimit

Number to program the strength limit obtained during calibration

ADBacklightMin

Number to program the minimum backlight obtained during calibration

ADBacklightMax

Number to program the maximum backlight obtained during calibration

ADAmbientLightMin

Number to program the minimum ambient light level obtained during calibration

ADCalibrationA

Number to program the CalibrationA value obtained during calibration

ADCalibrationB

Number to program the CalibrationB value obtained during calibration

ADCalibrationC

Number to program the CalibrationC value obtained during calibration

ADCalibrationD

Number to program the CalibrationD value obtained during calibration

ADFilterA

Number to program the ambient light filter; this value is obtained during calibration

ADFilterB

Number to program the ambient light filter; this value is obtained during calibration

ADTFilterControl

Number to program the ambient light filter; this value is obtained during calibration

ADAssymetry

These binary tags are used to program tables obtained during calibration.
Each table consists of 33 entries. Each entry is 2 bytes long. Entries are in
hexadecimal notation, e.g.:

00 00
01 01
02 02
…
31 31
32 32

ADPrivateData

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Private data that must be filled with specific values
aPrivateData[11] – This field configures the BacklightScale. This can be set
depending on the number of bits that want to be used to represent the backlight
level, e.g., if backlight level will be 16 bits, then BacklightScale should be 0xFFFF,
if it is an 8-bit range, then BacklightScale should be set to 0x00FF; the maximum
value permitted is the default 0xFFFF. If this value is modified from the default,
the BacklightLevel input needs to be adjusted.

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12 Platform-specific GPIO configuration

A majority of the power rails and GPIOs (both TLMM (MSM) and PMIC) are configured by the
PEP component of Windows. However, panels often require specific timing and control of GPIOs
during boot. Table 12-1 gives details on additional configuration operations available.
Figure 12-1 shows panel power-on reset.
Panel Power on Reset

Power Rails
Reset Pin

Figure 12-1 Panel power-on reset
During the panel power-on reset sequence, additional GPIOs can be configured. All of these
configurations are optional. If PEP is sufficient to control these resources, these configurations
must be disabled.

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Platform-specific GPIO configuration

Table 12-1 Panel resources
NOTE:

The following table has been updated.
Tag
Display1Reset1Info

Description
This string is used to configure the reset pin of all internal panel
(QDI_DISPLAY_PRIMARY, QDI_DISPLAY_SECONDARY, so on). The
following information is parsed in a comma-delimited format:
“ResourceName, Assert State, Pulse Width, Assert on Power Down”
 Resource name – This is a string matching the resource (GPIO) name
assigned to the graphics KMD in graphics.asl.
 Assert state – This is the state of the GPIO pin when being asserted.
This can be either of the following values:
 0 – Active low; the GPIO is pulled low during assertion of the reset
 1 – Active high; the GPIO is pulled high during the assertion of the
reset
 Pulse width – This determines the pulse width of the reset in
microseconds (µs) when the reset is asserted. If the pulse width is 0, no
pulse is created and the line is directly deasserted when active.
 Active-on power down – This Boolean allows for the reset to be asserted
during power-down. Depending on the panel configuration, this may be
required. Examples are DISPLAY_RESET_PIN, 0, 500, 0.
 Primary panel configuration is specified by DSI_PANEL_RESET and
other internal configuration specified by DSI_PANELX_RESET, where X
= 2, 3, .., N. For example N = 2 for secondary, 3 for Third, and so on.
 Reset pin configuration examples for primary panels are

 DSI_PANEL_RESET, 0, 500, 0
Power Off

Power Rails

Power On

Power Off

500ms

Reset Line

 DSI_PANEL_RESET, 0, 0, 1
Power Off

Power On

Power Off

Power Rails
Reset Line

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Tag

Platform-specific GPIO configuration

Description

Display1Power1Info
Display1Power2Info
Display1Power3Info
Display4Power1Info
Display4Power2Info
Display4Power3Info

This string is used to configure the state of GPIOs during power-on/off of
the internal panels (Display1Power1Info is used for
QDI_DISPLAY_PRIMARY, QDI_DISPLAY_SECONDARY etc). Other
resources can be associated with external displays by using other tags;
Dislpay4Power1Info is for (QDI_DISPLAY_EXTERNAL,
QDI_DISPLAY_EXTERNAL2, and so on).
The following information is parsed in a comma-delimited format:
“ResourceName, AssertState, RefCount, ActiveDelay, InactiveDelay”
Up to three resources can be controlled, Power1, Power2, and Power3.
These are all optional and the licensee should remove these settings if they
are not used.
 Resource name – This is a string matching the resource (GPIO) name
assigned to the graphics KMD in graphics.asl.
 Assert state – This is the state of the GPIO pin when being asserted; this
can be one of the following values:
 0 – Active low, the GPIO is pulled low during power-on
 1 – Active high, the GPIO is pulled high during power-on
 RefCount – If a resource is shared between one or multiple displays, the
resource is automatically ref counted by the driver. If the licensee wants
to specify a default refcount during boot, this field is used to set the
default refcount. A default refcount > 0 set during boot means the
resource will never be deasserted during power-off.
 Active delay – This integer allows the driver to delay for a specific
number of microseconds after asserting this resource during power-on.
 Inactive delay – This integer allows the driver to delay for a specific
number of microseconds after deasserting this resource during poweroff.

Display1Special1Info
Display4Special1Info

This string is used to configure special states of GPIOs during power-on of
the internal panels (Display1Special1Info=QDI_DISPLAY_PRIMARY,
QDI_DISPLAY_SECONDARY etc). Other resources can be associated with
external displays by using other tags; Display4Special1Info is for
(QDI_DISPLAY_EXTERNAL, QDI_DISPLAY_EXTERNAL2, so on).
The following information is parsed in a comma-delimited format:
“ResourceName, ChipId, OutBufferCfg, Voltage Source, Source,
BufferStrength”
 Resource name – This is a PMIC GPIO number that needs the special
configuration.
 ChipId – This value is specific to the PMIC.
 Out Buffer Cfg – This value is specific to the PMIC.
 Voltage source – This value is specific to the PMIC.
 Source – This value is specific to the PMIC.
 Buffer strength – This value is specific to the PMIC.

Display1I2C1Info
Display1I2C2Info

This parameter defines I2C connections used. There can be maximum of
two I2C connections. The following information is parsed in a commadelimited format:
“ResourceName, I2CSlaveType”
 1 – I2C slave is for the backlight driver
 2 – I2C slave is for the panel EDID EEPROM

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12.1 GPIO configuration
Table 12-2 show the tags that allow for a default GPIO configuration to be applied prior to
initializing the display.
NOTE:

This configuration is available only in boot loaders (UEFI).
Table 12-2 GPIO configuration tags
Tag

Description

TLMMGPIODefaultLow

This integer list provides the list of MSM GPIO numbers that should be
defaulted to high. Only confirgure GPIOs related to the display itself.
Note: This list is in hex, for example, GIO#91 should be written as 5B.

TLMMGPIODefaultHigh

This integer list provides the list of MSM GPIO numbers that should be
defaulted to high. Only configure GPIOs related to the display itself.
Note: This list is in hex, for example, GIO#91 should be written as 5B.

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13 Power-saving configuration

The optional configuration shown in Table 13-1 is used for display power saving when a device
enters idle/static screen (vsync interrupt is masked off). There are various scenarios when a
device can enter idle screen, e.g., when a user reads webpage content.
There are different modes in which the power-saving feature operates. One of the modes is to
allow command data transfer between the panel and the MSM even though the device has entered
the power-saving configuration. The other mode is to block the command data transfer between
the MSM and the panel when the device enters the power-saving configuration.
If an OEM wants to configure the hardware or transmit commands to the panel using the OEM
panel driver, it is highly advisable to not configure the power-saving configuration to block data.
In addition to these modes, there are different power-saving levels that can be configured as well.
A higher power-saving level means greater savings can be attained.
Currently, the power-saving feature supports three power-saving levels. At power saving level 0,
there are no power savings and the device would be functioning normally with the power saving
configuration disabled. When the device transitions to level 2, maximum power savings can be
attained. By default, the device is allowed to transfer data when the device enters the powersaving configuration with the power-saving level configured for maximum power savings.

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Power-saving configuration

Table 13-1 lists the power saving configuration parameters.
Table 13-1 Power saving configuration
Tag
DisplayPowerSavingOverride

Description
The following optional ACPI configuration field is used to override the
default power saving mode and levels; flags can be combined where it
makes sense.
Value (in hex)

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Definition

0x1

This allows data transfer while power saving is
enabled. If both allow data and block data bits
are set, then allow data transfer takes
precedence over block data transfer; by default,
data transfer is allowed while power saving is
enabled.

0x2

Power-saving level is configured to level 0. No
other power-saving level transitions are allowed
when configured at level 0. This is equivalent to
power saving being disabled.

0x4

Power-saving level is configured to level 1. This
allows transitions between level 0 and level 1
power-saving levels. This power-saving level
provides conservative power saving with lower
latency. If both level 0 and level 1 power-saving
levels are configured, then level 1 power saving
takes precedence.

0x8

Power-saving level is configured to level 2. This
allows transitions between all the power-saving
levels. This power-saving level provides
aggressive power saving with higher latency. If
all three power-saving levels are configured, then
level 2 power-saving level takes precedence.
This is the default power-saving level.

0x10

This is block data transfer during power saving.

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Power-saving configuration

Table 13-2 Power saving levels supported by the driver
Level

Description

Level 0 (no power
savings)

In level 0, the driver is expected to perform normal operation. By default,
when the display is turned on it transitions to level 0. Display power saving
can take effect any time by transitioning to either level 1 or level 2. Vsyncs
can be turned on/off.

Level 1 (conservative
power savings)

In level 1, there is no actual data transfer happening between the MSM and
the panel. Vsyncs are turned off, but it is still necessary to maintain phase.
Latency to enter and exit from this mode is kept to a minimum. Expected
latency for transitioning to level 1 should be less than 2 ms. However,
transitioning from level 1 to other levels should be less than 5 ms. Due to
this restriction, there is a limit on what can be turned off. Entering this state
will lower clocks and possibly gate off, reducing bandwidth votes.

Level 2 (aggressive power
savings)

In level 2, maximum display power saving can be achieved. Vsyncs are
turned off, and there is no need to maintain phase. Much higher latency is
allowed compared to level 1. Expected latency for transitioning to level 2
should be less than 2 ms. However, transitioning from level 2 to other levels
should be less than 16 ms. This limit gives flexibility to save more power by
turning off additional hardware components.
Entering this state includes all power savings from level 1, plus turning off
PLLs and enabling Deep Sleep states for peripherals, e.g., ULPS, where
applicable.

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14 Sharpening configuration

Table 14-1 lists the sharpening threshold configuration parameters.
Table 14-1 Sharpening parameters
Tag

Description

SharpeningEdgeThreshold

Sharpening edge threshold value; range is 1 to 1024

SharpeningSmoothThreshold

Sharpening smoothness threshold value; range is 1 to 1024

SharpeningNoiseThreshold

Sharpening noise threshold value; range is 1 to 256

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15 Display-specific ACPI methods

NOTE:

Numerous changes were made in this chapter.
Display configuration data for all panels (internal and external) are stored in the ACPI as per the
following file structure.
graphics.asl
- Primary panel GPIO resources
- Secondary panel GPIO resources
- Internal panel N GPIO resources

1...N External displays

1...N Internal displays
display.asl
_ROM
PIGC
PPCC
PGCT
PGRT
PBRT
HSIC
PGMT
PBRT
PLGC
PWGM
DITH

display2.asl
ROM2
IGC2
PCC2
GCT2
GRT2
BRT2
HSI2
GMT2
BRT2
LGC2
WGM2
DIT2

panelcfg.asl
PCFG
PCF1
PCF2

panelcfg2.asl
PCFG
PCF1
PCF2

backlightcfg.asl
BLCP

backlightcfg2.asl
BLCP

Primary Display

Secondary Display

displayN.asl
ROMN
IGCN
PCCN
GCTN
GRTN
BRTN
HSIN
GMTN
BRTN
LGCN
WGMN
DITN

panelcfgN.asl
PCFG
PCF1
PCF2

displayext.asl

ROE1

panelcfgext.asl
PCFG

displayext2.asl

displayextN.asl

ROE2

ROEN

panelcfgext2.asl

panelcfgextN.asl

PCFG

backlightcfgN.asl
BLCP

Internal N Display

External Display

External2 Display

External N Display

The power component configuration for all the panels are stored in graphics_resources.asl as
described in the diagram below. It is recommended that OEM should only update the F-State
component with power Grids, WLEDs, GPIOs, and so on and should not modify the P-State
component.

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graphics_resource.asl
Display, graphics, video resources

1...N Internal display power component
Power Component
F states
P states

Power Component
F states
P states

Primary Display

Secondary Display

1...N external display power component
Power Component

Power Component

F states
P states

Internal N Display

External Display

External2 Display

Power Component
F states
P states

External N Display

Note: F States for internal displays require platform specific customizations for the power grid.

The following sections describe each method with respect to primary panel. The configuration for
other panels should be followed in same way.

15.1 _ROM method
The _ROM method is a standard ACPI method to retrieve proprietary information. This method
is used by the graphics KMD to retrieve the panel configuration XML data from ACPI.

_ROM(offset, buffersize)
Parameters:
[in] offset :
file.

the offset in bytes to read from the panel configuration

[in] buffersize : the size in bytes of the response buffer.
bytes can be read at a time.
Return:

Up to 4096

Buffer : A response buffer containing the requested panel configuration
data. If a buffer of 1 byte is returned with a null byte the input offset
is out of range.

The _ROM method is found in display.asl and includes configuration data from panelcfg.asl.

15.2 ROM multipanel support
The _ROM method with three parameters is also supported by the driver. This extension will
allow multiple panel configurations to be stored in ACPI. The additional parameter is a unique
panel ID that is passed from the firmware (UEFI).
_ROM(offset, buffersize, panelid)
Parameters:
[in] offset :
file.

the offset in bytes to read from the panel configuration

[in] buffersize : the size in bytes of the response buffer.
bytes can be read at a time.

Up to 4096

[in] panelID : Unique panel ID passed from the firmware (DisplayDxe).
Return:

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Buffer : A response buffer containing the requested panel configuration
data. If a buffer of 1 byte is returned with a null byte the input offset
is out of range.

Example of a three parameter ROM
///
// _ROM Method - Used to retrieve proprietary ROM data
//
Method (_ROM, 3, NotSerialized) {
Switch (Arg2)
{
// Panel with ID 0xC130B0
Case (0xC130B0) {
Store (PCF1, Local2);
}
// All others
Default {
Store (PCFG, Local2);
}
}
// Ensure offset does not exceed the buffer size
// otherwise return a Null terminated buffer
If (LGreaterEqual(Arg0, Sizeof(Local2)))
{
Return( Buffer(){0x0} )
}
Else
{
// Make a local copy of the offset
Store(Arg0, Local0)
}
// Ensure the size requested is less than 4k
If (LGreater(Arg1, 0x1000))
{
Store(0x1000, Local1)
}
else
{
Store(Arg1, Local1)
}

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// Finaly ensure the total size does not exceed the size of the buffer
if (LGreater(Add(Local0, Local1), Sizeof(Local2)))
{
// Calculate the maximum size we can return
Subtract(Sizeof(Local2), Local0, Local1);
}
// Multiply offset and size by 8 to convert to bytes and create the RBuf
CreateField(Local2, Multiply(0x8, Local0), Multiply(0x8, Local1), RBUF)
Return(RBUF)
}

For more details on passing this ID from the firmware, refer to the MDPFirmwareEnvType
structure in the UEFI.

15.3 BLCP method
The BLCP method is a proprietary method used to return control packet information based on
changes on backlight. Licensees may customize this method to send control packet information to
the Graphics KMD.
BLCP(backlightLevel)
Parameters:
[in] backlight level :

the current backlight level, valid range is 0-100

Return:
Buffer : A response buffer containing the requested panel configuration
data. The format of the buffer is specific to the backlight hardware
control method.

Buffer format
4 bytes

Variable length

Packet Header

Packet Payload

The format of the BLCP buffer consists of a 4-byte packet header followed by a variable-sized
payload. The packet header consists of a DWORD value with the length (in bytes) of the variable
packet payload.
Multiple packets can be combined by appending a packet header and payload together. No
padding is allowed between packet headers and payload. A final packet header contains the value
0x00000000 indicating the end of the packet sequence.

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The contents of the payload packet depend on the control method for the backlight. The formats
for various packets are described in Section 15.3.1 and Section 15.3.2.

15.3.1 BLCP format for DSI DCS commands
The DCS command consists of one of the valid DCS commands. See Section 8.1 for details on
the supported DCS commands and special DCS commands. The payload size is variable. The
packet header must include both the size of the DCS command and the payload.

1 byte

Variable length

DCS Command

DCS Payload

Example
Send two DCS (+ payload) commands with a 10-ms delay between the two commands:
1. 11h + 01h 02h 03h 04h
2. FFh + 0Ah
3. 12h + 05h 06h
Packet #1
05

11h

Packet #2
01 02 03 04

FFh

Packet #3
0A

12h

05 06

15.3.2 BLCP format for I2C commands
The I2C packet consists of a 2-byte address followed by a variable-sized payload.

2 byte

Variable length

I2C Address

I2C Payload

Example
Send two I2C commands to address 1020h:
1. Command 01h 02h 03h 04 to address 1020h
2. Command 05h 06h to address 1020h

Packet #1
06

1020h

Packet #2
01 02 03 04

1020h

05 06

The BPCP method is found in backlight.asl.

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15.4 Panel calibration commands (PIGC, PPCC, PPGC,
PGRT, PBRT, HSIC, PGMT)
The panel calibration data is stored in the ACPI table, and the data is read out during panel
initialization and then programmed into hardware blocks, which includes:


Panel inverse gamma correction



Panel color correction



Panel gamma correction



Panel gamma response table



Panel backlight response table



Panel HSIC table



Panel 3D gamut mapping table

These ACPI methods defined for the driver to retrieve the corresponding data are:


PIGC – Method to retrieve panel inverse gamma correction data



PPCC – Method to retrieve panel color correction data



PGCT – Method to retrieve segment panel gamma correction data



PGRT – Method to retrieve panel gamma response table



PBRT – Method to retrieve panel backlight response table



HSIC – Method to retrieve HSIC configuration data



PGMT – Method to retrieve panel gamut mapping data



PBRT – Method to retrieve panel backlight response data



PLGC – Method to retrieve panel linear gamma correction data



PWGM – Method to retrieve panel wide gamut mapping data



DITH – Method to reteive panel dithering data

The actual data should be represented by fix-point data with corresponding resolution that
matches the hardware. If the data is obtained from a QTI calibration tool, it is already in the
correct format. Otherwise, the data must be adjusted before it is stored in the buffer.

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15.4.1 Panel Inverse Gamma Correction (PIGC)
The data for PIGC should be stored in the buffer inside the PIGC method. This buffer contains
data for three color components (Red, Green, and Blue), and each with 256 entries of 16-bit
integer in U12 format.
PIGC()

Parameters
None

Return
This returns Buffer, a response buffer containing the inverse gamma correction data.
NOTE:

The following graphic has been updated.
16 bits

16 bits

Red[0]

Red[1]

Red[2]

...

Red[255]

Green[0]

Green[1]

Green[2]

...

Green[255]

Blue[0]

Blue[1]

Blue[2]

...

Blue[255]

The buffer size should be 256*3*2 = 1536 bytes.

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15.4.2 Panel Color Correction (PPCC)
The data for PCC should be stored in the buffer inside the PPCC method, and it is a 3x11 matrix
with each coefficient represented by a 64-bit integer (long long).
PPCC()

Parameters
None

Return
This returns Buffer, a response buffer containing the panel color correction data.
NOTE:

The following graphic has been updated.
64 bits

64 bits

Red[0]

Red[1]

Red[2]

...

Red[10]

Green[0]

Green[1]

Green[2]

...

Green[10]

Blue[0]

Blue[1]

Blue[2]

...

Blue[10]

The buffer size should be 3*11*8 = 264 bytes.
Data representations for each coefficient are:
Coefficient index

Representation

S13.3

S2.15

S1.27

S1.39

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15.4.3 Panel Gamma Correction (PGCT)
The data for PGCT should be stored in the buffer inside the PGCT method. It contains data for
the three color components with 16 segments for each. The segment is described by four integer
parameters, including enable flag, start, gain, and offset.
PGCT()

Parameters
None

Return
This returns Buffer, a A response buffer containing the panel gamma correction data.
Below is the data format of one segment:
NOTE:

The following graphic has been updated.
32 bits

32 bits

Enable

Start

Gain

Offset

Data representation for each parameter is:
Enable

U1.0

Start

U12

Gain

U13.2

Offset

U8.7

The complete data buffer for PGCT is:
128 bits

128 bits

Red_Seg[0]

Red_Seg[1]

Red_Seg[2]

...

Red_Seg[15]

Green_Seg[0]

Green_Seg[1]

Green_Seg[2]

...

Green_Seg[15]

Blue_Seg[0]

Blue_Seg[1]

Blue_Seg[2]

...

Blue_Seg[15]

The buffer size is 3*16*4*4 = 768 bytes.

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15.4.4 Panel Gamma Response Table (PGRT)
This method returns the gamma response table for a panel. The table is given in a 256-entry array,
where the first entry value represents the luminance (Y) achieved when displaying black on the
screen (shade value is 0 for all R, G, and B) and the last entry represents the luminance (Y)
achieved when displaying white on the screen (shade value is 255 for all R, G, and B).
The array must be 256 entries.
The range of each entry must be from 0 to 0xffff.
Values are least significant byte first, e.g., {0x01, 0x00} represents 0x1 and {0x02, 0x01}
represents 0x0102.
A linear mapping example (mainly for formatting sample) is:
Method (PGRT, 2, NotSerialized) {
Name (BUF1, Buffer() {
0x00, 0x00, 0x01, 0x01, 0x02, 0x02, 0x03, 0x03,
0x04, 0x04, 0x05, 0x05, 0x06, 0x06, 0x07, 0x07,
0x08, 0x08, 0x09, 0x09, 0x0a, 0x0a, 0x0b, 0x0b,
0x0c, 0x0c, 0x0d, 0x0d, 0x0e, 0x0e, 0x0f, 0x0f,
0x10, 0x10, 0x11, 0x11, 0x12, 0x12, 0x13, 0x13,
0x14, 0x14, 0x15, 0x15, 0x16, 0x16, 0x17, 0x17,
0x18, 0x18, 0x19, 0x19, 0x1a, 0x1a, 0x1b, 0x1b,
0x1c, 0x1c, 0x1d, 0x1d, 0x1e, 0x1e, 0x1f, 0x1f,
0x20, 0x20, 0x21, 0x21, 0x22, 0x22, 0x23, 0x23,
0x24, 0x24, 0x25, 0x25, 0x26, 0x26, 0x27, 0x27,
0x28, 0x28, 0x29, 0x29, 0x2a, 0x2a, 0x2b, 0x2b,
0x2c, 0x2c, 0x2d, 0x2d, 0x2e, 0x2e, 0x2f, 0x2f,
0x30, 0x30, 0x31, 0x31, 0x32, 0x32, 0x33, 0x33,
0x34, 0x34, 0x35, 0x35, 0x36, 0x36, 0x37, 0x37,
0x38, 0x38, 0x39, 0x39, 0x3a, 0x3a, 0x3b, 0x3b,
0x3c, 0x3c, 0x3d, 0x3d, 0x3e, 0x3e, 0x3f, 0x3f,
0x40, 0x40, 0x41, 0x41, 0x42, 0x42, 0x43, 0x43,
0x44, 0x44, 0x45, 0x45, 0x46, 0x46, 0x47, 0x47,
0x48, 0x48, 0x49, 0x49, 0x4a, 0x4a, 0x4b, 0x4b,
0x4c, 0x4c, 0x4d, 0x4d, 0x4e, 0x4e, 0x4f, 0x4f,
0x50, 0x50, 0x51, 0x51, 0x52, 0x52, 0x53, 0x53,
0x54, 0x54, 0x55, 0x55, 0x56, 0x56, 0x57, 0x57,
0x58, 0x58, 0x59, 0x59, 0x5a, 0x5a, 0x5b, 0x5b,
0x5c, 0x5c, 0x5d, 0x5d, 0x5e, 0x5e, 0x5f, 0x5f,
0x60, 0x60, 0x61, 0x61, 0x62, 0x62, 0x63, 0x63,
0x64, 0x64, 0x65, 0x65, 0x66, 0x66, 0x67, 0x67,
0x68, 0x68, 0x69, 0x69, 0x6a, 0x6a, 0x6b, 0x6b,
0x6c, 0x6c, 0x6d, 0x6d, 0x6e, 0x6e, 0x6f, 0x6f,
0x70, 0x70, 0x71, 0x71, 0x72, 0x72, 0x73, 0x73,
0x74, 0x74, 0x75, 0x75, 0x76, 0x76, 0x77, 0x77,

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0x78, 0x78, 0x79, 0x79, 0x7a, 0x7a, 0x7b, 0x7b,
0x7c, 0x7c, 0x7d, 0x7d, 0x7e, 0x7e, 0x7f, 0x7f,
0x80, 0x80, 0x81, 0x81, 0x82, 0x82, 0x83, 0x83,
0x84, 0x84, 0x85, 0x85, 0x86, 0x86, 0x87, 0x87,
0x88, 0x88, 0x89, 0x89, 0x8a, 0x8a, 0x8b, 0x8b,
0x8c, 0x8c, 0x8d, 0x8d, 0x8e, 0x8e, 0x8f, 0x8f,
0x90, 0x90, 0x91, 0x91, 0x92, 0x92, 0x93, 0x93,
0x94, 0x94, 0x95, 0x95, 0x96, 0x96, 0x97, 0x97,
0x98, 0x98, 0x99, 0x99, 0x9a, 0x9a, 0x9b, 0x9b,
0x9c, 0x9c, 0x9d, 0x9d, 0x9e, 0x9e, 0x9f, 0x9f,
0xa0, 0xa0, 0xa1, 0xa1, 0xa2, 0xa2, 0xa3, 0xa3,
0xa4, 0xa4, 0xa5, 0xa5, 0xa6, 0xa6, 0xa7, 0xa7,
0xa8, 0xa8, 0xa9, 0xa9, 0xaa, 0xaa, 0xab, 0xab,
0xac, 0xac, 0xad, 0xad, 0xae, 0xae, 0xaf, 0xaf,
0xb0, 0xb0, 0xb1, 0xb1, 0xb2, 0xb2, 0xb3, 0xb3,
0xb4, 0xb4, 0xb5, 0xb5, 0xb6, 0xb6, 0xb7, 0xb7,
0xb8, 0xb8, 0xb9, 0xb9, 0xba, 0xba, 0xbb, 0xbb,
0xbc, 0xbc, 0xbd, 0xbd, 0xbe, 0xbe, 0xbf, 0xbf,
0xc0, 0xc0, 0xc1, 0xc1, 0xc2, 0xc2, 0xc3, 0xc3,
0xc4, 0xc4, 0xc5, 0xc5, 0xc6, 0xc6, 0xc7, 0xc7,
0xc8, 0xc8, 0xc9, 0xc9, 0xca, 0xca, 0xcb, 0xcb,
0xcc, 0xcc, 0xcd, 0xcd, 0xce, 0xce, 0xcf, 0xcf,
0xd0, 0xd0, 0xd1, 0xd1, 0xd2, 0xd2, 0xd3, 0xd3,
0xd4, 0xd4, 0xd5, 0xd5, 0xd6, 0xd6, 0xd7, 0xd7,
0xd8, 0xd8, 0xd9, 0xd9, 0xda, 0xda, 0xdb, 0xdb,
0xdc, 0xdc, 0xdd, 0xdd, 0xde, 0xde, 0xdf, 0xdf,
0xe0, 0xe0, 0xe1, 0xe1, 0xe2, 0xe2, 0xe3, 0xe3,
0xe4, 0xe4, 0xe5, 0xe5, 0xe6, 0xe6, 0xe7, 0xe7,
0xe8, 0xe8, 0xe9, 0xe9, 0xea, 0xea, 0xeb, 0xeb,
0xec, 0xec, 0xed, 0xed, 0xee, 0xee, 0xef, 0xef,
0xf0, 0xf0, 0xf1, 0xf1, 0xf2, 0xf2, 0xf3, 0xf3,
0xf4, 0xf4, 0xf5, 0xf5, 0xf6, 0xf6, 0xf7, 0xf7,
0xf8, 0xf8, 0xf9, 0xf9, 0xfa, 0xfa, 0xfb, 0xfb,
0xfc, 0xfc, 0xfd, 0xfd, 0xfe, 0xfe, 0xff, 0xff})
// Return the packet data
Return(BUF1)
}

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15.4.5 HSIC panel HSIC configuration table
This method returns hue, saturation, intensity, and contrast table values to be applied to the panel.
The method must return five 32-bit values representing this table. HSIC values are 32-bit integer
values. Ranges from -100 to +100 are allowed.
Method (HSIC, 2, NotSerialized) {
Name (BUF1, Buffer() {
0x00, 0x00, 0x00, 0x01,

// Enable HSIC table

0x00, 0x00, 0x00, 0x0A,

// +10 Hue adjustment

0xFF, 0xFF, 0xFF, 0x01,

// -15 Saturation adjustment

0x00, 0x00, 0x00, 0x00,

// 0 Intensity adjustment

0x00, 0x00, 0x00, 0x02,

// 2 Contrast adjustment

// Return the packet data
Return(BUF1)
}

15.4.6 Panel Gamut Mapping Table (PGMT)
This method returns a table that corresponds to the 3D gamut lookup table. The data is organized
into seven tables of varying lengths, each entry is 16-bits.
T VESA
Enhanced
Extended
Display
Identification
Data table

Number of entries

125

100

The component layout and ordering are shown here.

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The following graphic has been updated.
16 bits

16 bits

Red_comp[0][0]

Red_comp[0][1]

Red_comp[0][2]

...

Red_comp[7][79]

Green_comp[0][0]

Green_comp[0][1]

Green_comp[0][2]

...

Green_comp[7][79]

Blue_comp[0][0]

Blue_comp[0][1]

Blue_comp[0][2]

...

Blue_comp[7][79]

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15.4.7 Panel Backlight Response Table (PBRT)
This method returns the backlight response table for a panel. The table is given in a 256-entry
array, where the first entry value represents the backlight level to achieve 0 luminance, and the
last entry represents the highest backlight level to achieve the maximum desired luminance. In
other words, this array serves as a map from luminance to backlight levels, where the index is the
desired luminance level and the value (or output) is the backlight level to be sent to the hardware
(backlight controller).
The array must be 256 entries.
The range of each entry must be from 0 to 0xffff.
Values are least significant byte first, e.g., {0x01, 0x00} represents 0x1 and {0x02, 0x01}
represents 0x0102.
A linear mapping example (mainly for formatting sample) is:
Method (PBRT, 2, NotSerialized) {
Name (BUF1, Buffer() {
0x00, 0x00, 0x01, 0x01, 0x02, 0x02, 0x03, 0x03,
0x04, 0x04, 0x05, 0x05, 0x06, 0x06, 0x07, 0x07,
0x08, 0x08, 0x09, 0x09, 0x0a, 0x0a, 0x0b, 0x0b,
0x0c, 0x0c, 0x0d, 0x0d, 0x0e, 0x0e, 0x0f, 0x0f,
0x10, 0x10, 0x11, 0x11, 0x12, 0x12, 0x13, 0x13,
0x14, 0x14, 0x15, 0x15, 0x16, 0x16, 0x17, 0x17,
0x18, 0x18, 0x19, 0x19, 0x1a, 0x1a, 0x1b, 0x1b,
0x1c, 0x1c, 0x1d, 0x1d, 0x1e, 0x1e, 0x1f, 0x1f,
0x20, 0x20, 0x21, 0x21, 0x22, 0x22, 0x23, 0x23,
0x24, 0x24, 0x25, 0x25, 0x26, 0x26, 0x27, 0x27,
0x28, 0x28, 0x29, 0x29, 0x2a, 0x2a, 0x2b, 0x2b,
0x2c, 0x2c, 0x2d, 0x2d, 0x2e, 0x2e, 0x2f, 0x2f,
0x30, 0x30, 0x31, 0x31, 0x32, 0x32, 0x33, 0x33,
0x34, 0x34, 0x35, 0x35, 0x36, 0x36, 0x37, 0x37,
0x38, 0x38, 0x39, 0x39, 0x3a, 0x3a, 0x3b, 0x3b,
0x3c, 0x3c, 0x3d, 0x3d, 0x3e, 0x3e, 0x3f, 0x3f,
0x40, 0x40, 0x41, 0x41, 0x42, 0x42, 0x43, 0x43,
0x44, 0x44, 0x45, 0x45, 0x46, 0x46, 0x47, 0x47,
0x48, 0x48, 0x49, 0x49, 0x4a, 0x4a, 0x4b, 0x4b,
0x4c, 0x4c, 0x4d, 0x4d, 0x4e, 0x4e, 0x4f, 0x4f,
0x50, 0x50, 0x51, 0x51, 0x52, 0x52, 0x53, 0x53,
0x54, 0x54, 0x55, 0x55, 0x56, 0x56, 0x57, 0x57,
0x58, 0x58, 0x59, 0x59, 0x5a, 0x5a, 0x5b, 0x5b,
0x5c, 0x5c, 0x5d, 0x5d, 0x5e, 0x5e, 0x5f, 0x5f,
0x60, 0x60, 0x61, 0x61, 0x62, 0x62, 0x63, 0x63,
0x64, 0x64, 0x65, 0x65, 0x66, 0x66, 0x67, 0x67,
0x68, 0x68, 0x69, 0x69, 0x6a, 0x6a, 0x6b, 0x6b,
0x6c, 0x6c, 0x6d, 0x6d, 0x6e, 0x6e, 0x6f, 0x6f,

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0x70, 0x70, 0x71, 0x71, 0x72, 0x72, 0x73, 0x73,
0x74, 0x74, 0x75, 0x75, 0x76, 0x76, 0x77, 0x77,
0x78, 0x78, 0x79, 0x79, 0x7a, 0x7a, 0x7b, 0x7b,
0x7c, 0x7c, 0x7d, 0x7d, 0x7e, 0x7e, 0x7f, 0x7f,
0x80, 0x80, 0x81, 0x81, 0x82, 0x82, 0x83, 0x83,
0x84, 0x84, 0x85, 0x85, 0x86, 0x86, 0x87, 0x87,
0x88, 0x88, 0x89, 0x89, 0x8a, 0x8a, 0x8b, 0x8b,
0x8c, 0x8c, 0x8d, 0x8d, 0x8e, 0x8e, 0x8f, 0x8f,
0x90, 0x90, 0x91, 0x91, 0x92, 0x92, 0x93, 0x93,
0x94, 0x94, 0x95, 0x95, 0x96, 0x96, 0x97, 0x97,
0x98, 0x98, 0x99, 0x99, 0x9a, 0x9a, 0x9b, 0x9b,
0x9c, 0x9c, 0x9d, 0x9d, 0x9e, 0x9e, 0x9f, 0x9f,
0xa0, 0xa0, 0xa1, 0xa1, 0xa2, 0xa2, 0xa3, 0xa3,
0xa4, 0xa4, 0xa5, 0xa5, 0xa6, 0xa6, 0xa7, 0xa7,
0xa8, 0xa8, 0xa9, 0xa9, 0xaa, 0xaa, 0xab, 0xab,
0xac, 0xac, 0xad, 0xad, 0xae, 0xae, 0xaf, 0xaf,
0xb0, 0xb0, 0xb1, 0xb1, 0xb2, 0xb2, 0xb3, 0xb3,
0xb4, 0xb4, 0xb5, 0xb5, 0xb6, 0xb6, 0xb7, 0xb7,
0xb8, 0xb8, 0xb9, 0xb9, 0xba, 0xba, 0xbb, 0xbb,
0xbc, 0xbc, 0xbd, 0xbd, 0xbe, 0xbe, 0xbf, 0xbf,
0xc0, 0xc0, 0xc1, 0xc1, 0xc2, 0xc2, 0xc3, 0xc3,
0xc4, 0xc4, 0xc5, 0xc5, 0xc6, 0xc6, 0xc7, 0xc7,
0xc8, 0xc8, 0xc9, 0xc9, 0xca, 0xca, 0xcb, 0xcb,
0xcc, 0xcc, 0xcd, 0xcd, 0xce, 0xce, 0xcf, 0xcf,
0xd0, 0xd0, 0xd1, 0xd1, 0xd2, 0xd2, 0xd3, 0xd3,
0xd4, 0xd4, 0xd5, 0xd5, 0xd6, 0xd6, 0xd7, 0xd7,
0xd8, 0xd8, 0xd9, 0xd9, 0xda, 0xda, 0xdb, 0xdb,
0xdc, 0xdc, 0xdd, 0xdd, 0xde, 0xde, 0xdf, 0xdf,
0xe0, 0xe0, 0xe1, 0xe1, 0xe2, 0xe2, 0xe3, 0xe3,
0xe4, 0xe4, 0xe5, 0xe5, 0xe6, 0xe6, 0xe7, 0xe7,
0xe8, 0xe8, 0xe9, 0xe9, 0xea, 0xea, 0xeb, 0xeb,
0xec, 0xec, 0xed, 0xed, 0xee, 0xee, 0xef, 0xef,
0xf0, 0xf0, 0xf1, 0xf1, 0xf2, 0xf2, 0xf3, 0xf3,
0xf4, 0xf4, 0xf5, 0xf5, 0xf6, 0xf6, 0xf7, 0xf7,
0xf8, 0xf8, 0xf9, 0xf9, 0xfa, 0xfa, 0xfb, 0xfb,
0xfc, 0xfc, 0xfd, 0xfd, 0xfe, 0xfe, 0xff, 0xff})
// Return the packet data
Return(BUF1)
}

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15.4.8 Panel Linear Gamma Correction (PLGC)
NOTE:

This section was added to this document revision.
The data for PLGC should be stored in the buffer inside the PlGC method for primary panel and
LGCX, where X = 2, 3, ..N for other internal panel. This buffer contains data for three color
components (Red, Green, and Blue), and each with 1024 entries of 16-bit integer in U12 format.
Primary Panel: PLGC()

Other internal display method:
LGCX(), where X = 2, 3…N. 2 for secondary, 3 for third etc

Parameters
None

Return
This method returns a response buffer containing the inverse gamma correction data.
16 bits

16 bits

Red[0]

Red[1]

Red[2]

...

Red[1023]

Green[0]

Green[1]

Green[2]

...

Green[1023]

Blue[0]

Blue[1]

Blue[2]

...

Blue[1023]

16 bits

The buffer size should be 1024*3*2 = 6144 bytes.

15.4.9 Panel Wide Gamut Mapping Table (PWGM)
NOTE:

This section was added to this document revision.
The data for PWGM should be stored in the buffer inside the PWGM method for primary display
and WGMX, where X = 2, 3.. N for other internal panel. This panel gamut mapping data is for
hardware which supports 17×17×17 gamut mapping. It contains a data header and two tables, one
is 3D table and other is segment table.
Primary display method: PWGM()
Other internal display method: WGMX(), where X = 2, 3…N. 2 for secondary, 3
for third etc

Parameters
None

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Return
This method returns a response buffer containing the panel gamut mapping table data.
Table data header:
32 bits

32 bits
NumSamplesPerColorComponent

NumSegmentsPerColor

3D Table:

16 bits

Red_Comp[0]

16 bits

Red_Comp[2]

...

Red_Comp[N*N*N-1]
Up to 17 entries.

Green_Comp[0]

Green_Comp[2]

...

Green_Comp[N*N*N1]

Blue_Comp[0]

Blue_Comp[1]

Blue_Comp[2]

...

Blue_Comp[N*N*N-1]

173 * 2 Bytes per row
(Component)

Segment Table:

32 bits

Sg_Red_Comp[0]

32 bits
Sg_Red_Comp[2]

32 bits
...

Sg_Red_Comp[N-2]
Up to 16 segments (per 173 table)

Sg_Green_Comp[0]

Sg_Green_Comp[2]

...

Sg_Green_Comp[N-2]

Sg_Blue_Comp[0]

Sg_Blue_Comp[1]

Sg_Blue_Comp[2]

...

Sg_Blue_Comp[N-2]

16 * 4 bytes per row (color
componet)

The maximum buffer size is = 3 x(17 - 1) x 4 + 3 x 17 x 17 x 17 x 2 + 8 = 29678 bytes.

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15.4.10 Panel Dithering Table (DITH)
NOTE:

This section was added to this document revision.
The data for DITH should be stored in the buffer inside the DITH method for primary display and
DITX, where X = 2, 3.. N for other internal panel. Dithering matrix can have one of the two
formats.
Primary display method: DITH()
Other internal display method: DITX(), where X = 2, 3…N. 2 for secondary, 3
for third etc

Parameters
None

Return
This method returns a response buffer containing the panel dithering data.
Format 1:
8 Bits

8 Bits

Element[0,0]

Element[0,1]

Element[0,2]

Element[0,3]

Element[1,0]

Element[1,1]

Element[1,2]

Element[1,3]

Element[2,0]

Element[2,1]

Element[2,2]

Element[2,3]

Element[3,0]

Element[3,1]

Element[3,2]

Element[3,3]

Bit Depth C2

Bit Depth C1

Bit Depth C0

Reserved

Dithering mode (4 bytes) (0: reserved, 1:Spatial, 2:Temporal)

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Display-specific ACPI methods

Format 2:
8 Bits

8 Bits

Element[0,0]

Element[0,1]

Element[0,2]

Element[0,3]

Element[1,0]

Element[1,1]

Element[1,2]

Element[1,3]

Element[2,0]

Element[2,1]

Element[2,2]

Element[2,3]

Element[3,0]

Element[3,1]

Element[3,2]

Element[3,3]

Bit Depth C2

Bit Depth C1

Bit Depth C0

Reserved

8 Bits

There is no dithering mode in Format 2. Default dither mode: spatial.

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16 Registry key entries

The following Windows registry keys can be used to configure the display driver further.
NOTE:

The following registry keys come into effect during bootup.

16.1 CABL
To disable CABL completely, use the following registry key, if this is set to 1, CABL cannot be
enabled in the software. When this entry is removed or is set to 0 then CABL can be enabled as
normal by the OS.
[HKEY_LOCAL_MACHINE\SOFTWARE\QCOM\Drivers\DxKMD\Miniport\BACKLIGHT]
"DisableCABL"=dword:00000001

16.2 SBC
To disable Smooth Backlight Control (SBC) completely, use the following registry key. Note that
after this entry is set to 1, SBC cannot be enabled in the software. When this entry is removed or
is set to 0, SBC can be enabled as normal by the OS.
[HKEY_LOCAL_MACHINE\SOFTWARE\QCOM\Drivers\DxKMD\Miniport\BACKLIGHT]
"DisableSBC"=dword:00000001

16.3 AVI info frame packet
The DisableAviInfoFramePacket registry key can be used to enable and disable AVI Info
Frame Packet. By default, AVI Info Frame Packet is enabled. After changing the register key
value, the system must be rebooted to ensure that the registry key takes effect. If both the ACPI
table and the registry key control the AVI Info Frame Packet enable/disable, the registry key will
come into effect.
[HKEY_LOCAL_MACHINE\SOFTWARE\QCOM\Drivers\DxKMD\Miniport\Display]
"DisableAviInfoFramePacket"=dword:00000001

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Configuration Guide for Display Drivers (ACPI and XML)

Registry key entries

16.4 HDCP
The EnableHDCPInQDI registry key can be used to always enable HDCP. By default, HDCP is
not enabled, and it can be enabled by Microsoft’s video player. After changing the register key
value, the system must be rebooted to make this registry key take effect. If both the ACPI table
and the registry key control HDCP enable/disable, the registry key will come into effect.
[HKEY_LOCAL_MACHINE\SOFTWARE\QCOM\Drivers\DxKMD\Miniport\Display]
" EnableHDCPInQDI"=dword:00000001

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17 OLED power

The display can be powered by the PMIC inverting buck boost (IBB) and LCD/AMOLD Boost
(LAB) modules, shown in Figure 17-1, which supply special voltages. More detailed information
and configuration of the PMIC IBB and LAB modules can be found in the LCD AMOLED Boost
(LAB) and Inverting Buck-Boost Module (80-NJ118-15).

LCD/AMOLED
DISPLAY

SWIRE
VDISN

LCD/AMOLED Boost
Converter (LAB)

CREF
CAP_REF

VPH_PWR

Inverting Buck-Boost
Converter (IBB)

VDISN_FB

VDISP

VPH_PWR

C4
VDISP_FB

VSWP

VSWN

C1
C3

VDISN

VDISP

SCTRL

PMIC
Figure 17-1 PMIC IBB and LAB modules

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Configuration Guide for Display Drivers (ACPI and XML)

OLED power

The display driver can be configured to manage these power supplies. Table 17-1 lists the
configuration for IBB/LAB management.
Table 17-1 IBB/LAB management configuration
Tag
PMIPowerPmicModel

Description
This selects the PMIC module ID that is used to manage IBB/LAB supplies.
Typically, this would be the PMI module that is paired with the PMIC, for
example, on the MSM8994, QDI_PMIC_DEVICEID_8994I (10) should be
used.
Value (decimal)

Definition

QDI_PMIC_DEVICEID_8921

QDI_PMIC_DEVICEID_8038

QDI_PMIC_DEVICEID_8941

QDI_PMIC_DEVICEID_8841

QDI_PMIC_DEVICEID_8026

QDI_PMIC_DEVICEID_8926

QDI_PMIC_DEVICEID_8084

QDI_PMIC_DEVICEID_8962

QDI_PMIC_DEVICEID_8994

QDI_PMIC_DEVICEID_8994I (PMI8994)

QDI_PMIC_DEVICEID_8916

QDI_PMIC_DEVICEID_8110

QDI_PMIC_DEVICEID_8909

QDI_PMIC_DEVICEID_8950

QDI_PMIC_DEVICEID_8950I (PMI8950)

PMIPowerPmicNum

This value is reserved and should not be used.

PMIPowerConfig

This selects the configuration of the PMI module, as multiple configurations
can be used depending on the platform.
Warning: Selecting the wrong value can damage the panel and/or the
PMIC.
Value
(decimal)

80-NB116-2 G

Definition

QDI_PMIC_INTERFACE_CONTROLTYPE_NONE
The module is not in use.

QDI_PMIC_INTERFACE_CONTROLTYPE_IBB_LAB_LCD
IBB/LAB power supplies are enabled, using LCD voltages.

QDI_PMIC_INTERFACE_CONTROLTYPE_IBB_LAB_OLED
IBB/LAB power supplies are enabled, using OLED voltages.

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101

A Specifying the I2C connection in
graphics.asl

To add the I2C connection resource in graphics.asl, the resource information is added in
platform.xml. The GfxXMLToACPI.pl script is used to generate the updated graphics.asl.
The example entry in platform.xml to specify the I2C connection configuration between the
MSM and the panel EEPROM for reading EDID is shown below.

DISPLAY
I2C_DYNAMICEDID_SLAVE
I2C
AddressingMode7Bit
100000
0x50
ControllerInitiated
\\_SB.IC10
I2C Slave used to read EDID information

Table A-1 lists the XML tags and their corresponding descriptions.
Table A-1 XML tags and descriptions
Tag

Description

Owner

Display is the owner of this resource; this field should be used as is

Name

Name of the I2C connection resource; this field should be used as is

Type

Resource type

AddressingMode

To specify 7-bit or 10-bit addressing mode; refer to the ACPI Specification for
details

ConnectionSpeed

Maximum connection speed in Hertz

SlaveAddress

I2C bus address for this connection

SlaveMode

Can be either Controller initiated or Device initiated; see Advanced
Configuration and Power Interface Specification (Revision 5.0 (December
2011)) for more information

ResourceSource

Indicates the GSBI port

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B Sample ACPI configuration for
DCS-based backlight control

///
// BLCP Method - Backlight control method, returns a
//

command buffer for a specific backlight level

//
// Input Parameters
//

Backlight level - Integer from 0% to 100%

//
// Output Parameters
//
// Packet format:
//

+--32bits--+-----variable (8bit alignment)--+

+----------+--------------------------------+

Header

Packet payload

//
//

For DSI Command packets, payload data must be in this format

//
//

+-- 8 bits-+----variable (8bit alignment)----+

| Cmd Type |

+----------+---------------------------------+

Packet Data

//
//

For I2C Command packets, payload data must be in this format

//
//

+-- 16 bits-+----variable (8bit alignment)----+

+-----------+---------------------------------+

Address

Command Data

//
//

All packets must follow with a DWORD header with 0x0

//
Method (BLCP, 1, NotSerialized) {
// Create Response buffer
Name(RBUF, Buffer(0x100){})

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Configuration Guide for Display Drivers (ACPI and XML)

Sample ACPI configuration for DCS-based...

// Store the current byte index offset in local0
Store(0x0, LOCAL0)
// Create the packet header field
CreateField(RBUF, Multiply(LOCAL0, 8), 32, PKHR)
header

// Create the packet

Add(LOCAL0, 4, LOCAL0)
pointer

// Increment the data

// Create the packet payload field
CreateField(RBUF, Multiply(LOCAL0, 8), 32, PKPL)
payload

// Create the packet

// Backlight programming packet
If (LEqual(Arg0, 0))
{
Name (BOFF,

// Backlight off

Buffer() {0x15,

// Command 15

0x53, 0x00})

// Turn off backlight

Store(Sizeof(BOFF), PKHR)

// Store the size of the buffer in the

Store(BOFF, PKPL)

// Store the packet payload

header
Add(LOCAL0, Sizeof(BOFF), LOCAL0)

// Increment the offset

}
Else
{
If (LLessEqual(Arg0, 16))

// Level 0-16%

{
Name (BL1,
Buffer() {0x15,
0x51, 0x0C})

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Configuration Guide for Display Drivers (ACPI and XML)

Sample ACPI configuration for DCS-based...

Store(Sizeof(BL1), PKHR)

// Store the size of the buffer in the

Store(BL1, PKPL)

// Store the packet payload

header
Add(LOCAL0, Sizeof(BL1), LOCAL0)
packet size

// Increment the offset by the

}
ElseIf (LLessEqual(Arg0, 28))

// Level 17-28%

{
Name (BL2,
Buffer() {0x15,
0x51, 0x19})
Store(Sizeof(BL2), PKHR)

// Store the size of the buffer in the

Store(BL2, PKPL)

// Store the packet payload

header
Add(LOCAL0, Sizeof(BL2), LOCAL0)
packet size

// Increment the offset by the

}
ElseIf (LLessEqual(Arg0, 40))

// Level 18-40%

{
Name (BL3,
Buffer() {0x15,
0x51, 0x33})
Store(Sizeof(BL3), PKHR)

// Store the size of the buffer in the

Store(BL3, PKPL)

// Store the packet payload

header
Add(LOCAL0, Sizeof(BL3), LOCAL0)
packet size

// Increment the offset by the

}
ElseIf (LLessEqual(Arg0, 52))

// Level 41-52%

{
Name (BL4,
Buffer() {0x15,
0x51, 0x4C})

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Configuration Guide for Display Drivers (ACPI and XML)

Sample ACPI configuration for DCS-based...

Store(Sizeof(BL4), PKHR)

// Store the size of the buffer in the

Store(BL4, PKPL)

// Store the packet payload

header
Add(LOCAL0, Sizeof(BL4), LOCAL0)

// Increment the offset by the

packet size
}
ElseIf (LLessEqual(Arg0, 64))

// Level 53-64%

{
Name (BL5,
Buffer() {0x15,
0x51, 0x6D})
Store(Sizeof(BL5), PKHR)

// Store the size of the buffer in the

Store(BL5, PKPL)

// Store the packet payload

header
Add(LOCAL0, Sizeof(BL5), LOCAL0)

// Increment the offset by the

packet size
}
ElseIf (LLessEqual(Arg0, 76))

// Level 65-76%

{
Name (BL6,
Buffer() {0x15,
0x51, 0x99})
Store(Sizeof(BL6), PKHR)

// Store the size of the buffer in the

Store(BL6, PKPL)

// Store the packet payload

header
Add(LOCAL0, Sizeof(BL6), LOCAL0)

// Increment the offset by the

packet size
}
ElseIf (LLessEqual(Arg0, 88))

// Level 77-88%

{
Name (BL7,
Buffer() {0x15,
0x51, 0xD3})

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Configuration Guide for Display Drivers (ACPI and XML)

Sample ACPI configuration for DCS-based...

Store(Sizeof(BL7), PKHR)

// Store the size of the buffer in the

Store(BL7, PKPL)

// Store the packet payload

header
Add(LOCAL0, Sizeof(BL7), LOCAL0)
packet size

// Increment the offset by the

}
Else

// Level 89-100%

{
Name (BL8,
Buffer() {0x15,
0x51, 0xFF})
Store(Sizeof(BL8), PKHR)

// Store the size of the buffer in the

header
Store(BL8, PKPL)

// Store the packet payload

Add(LOCAL0, Sizeof(BL8), LOCAL0)
packet size

// Increment the offset by the

}
// Add additonal ON command
Name (BON,

// Backlight on

Buffer() {0x15,

// Command 15

0x53, 0x24})

// Manual backlight control

// Create the packet header field
CreateField(RBUF, Multiply(LOCAL0, 8), 32, PKH2)

// Create the packet

header
Add(LOCAL0, 4, LOCAL0)
data pointer

// Increment the

// Create the packet payload field
CreateField(RBUF, Multiply(LOCAL0, 8), 32, PKP2)
payload
Store(Sizeof(BON), PKH2)
the header

// Create the packet

// Store the size of the buffer in

Store(BON, PKP2)

// Store the packet payload

Add(LOCAL0, Sizeof(BON), LOCAL0)

// Increment the offset by the packet

size
}

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Sample ACPI configuration for DCS-based...

// Add the End of Packet marker
CreateDWordField(RBUF, Multiply(LOCAL0, 8), EOP)
Store(0x0, EOP)
// Return the packet data
Return(RBUF)
}

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C References

C.1 Related documents
Title

Number

Qualcomm Technologies, Inc.
LCD AMOLED Boost (LAB) and Inverting Buck-Boost Module
Hardware Software Application Note

80-NJ118-15

Resources
VESA Enhanced Extended Display Identification Data –
Implementation Guide

Version 1.0 (June 2001)

VESA Enhanced Extended Display Identification Data Standard

(Defines EDID Structure Version 1,
Revision 4) Release A, Revision 2
(September 2006)

MIPI Alliance Specification for D-PHY

Version 1.00.00 (May 2009)

MIPI Alliance Specification for Display Serial Interface

Version 1.02.00 (June 2010)

MIPI Alliance Specification for Display Serial Interface

Version 1.03.00 (August 2011)

Advanced Configuration and Power Interface Specification

Revision 5.0 (December 2011)

C.2 Acronyms and terms
Acronym or term

Definition

ACPI

Advanced Configuration and Power Interface

Assertive Display

BLLP

Blanking low-power period

CABL

Content adaptive backlight level

HBP

Horizontal blanking period

HFP

Horizontal front porch

High speed

HSA

Horizontal sync active

HSIC

High-Speed Inter-Chip Interface

HSP

Horizontal sync period

KMD

Kernel Mode Driver

PBRT

Panel backlight response table

PGCT

Panel gamma correction table

PGMT

Panel gamut mapping table

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Configuration Guide for Display Drivers (ACPI and XML)

Acronym or term

Definition

PGRT

Panel gamma response table

PIGC

Panel inverse gamma correction

PPCC

Panel color correction

PPGC

Panel gamma correction

SBC

Smooth backlight control

WDDM

Windows Display Driver Model

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