ARM V7 M Architecture Application Level Reference Manual ARMv7
ARM-ARMv7-ReferenceManual
ARM-ARMv7-ReferenceManual
ARM-ARMv7-ReferenceManual
ARM-ARMv7-ReferenceManual
ARM-ARMv7-ReferenceManual
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- ARM v7-M Architecture Application Level Reference Manual
- Contents
- Preface
- Application
- Introduction
- Application Level Programmer’s Model
- ARM Architecture Memory Model
- A3.1 Address space
- A3.2 Alignment Support
- A3.3 Endian Support
- A3.4 Synchronization and semaphores
- A3.4.1 Exclusive access instructions and Non Shared memory regions
- A3.4.2 Exclusive access instructions and shared memory regions
- A3.4.3 Size of the tagged memory block
- A3.4.4 Context switch support
- A3.4.5 Load-Exclusive and Store-Exclusive usage restrictions
- A3.4.6 Synchronization primitives and the memory order model
- A3.5 Memory types
- A3.6 Access rights
- A3.7 Memory access order
- A3.7.1 Read and write definitions
- A3.7.2 Observability and completion
- A3.7.3 Ordering requirements for memory accesses
- A3.7.4 Program order for instruction execution
- A3.7.5 Memory barriers
- A3.7.6 Data Memory Barrier (DMB)
- A3.7.7 Data Synchronization Barrier (DSB)
- A3.7.8 Instruction Synchronization Barrier (ISB)
- A3.8 Caches and memory hierarchy
- A3.9 Bit banding
- The Thumb Instruction Set
- A4.1 Instruction set encoding
- A4.2 Instruction encoding for 16-bit Thumb instructions
- A4.3 Instruction encoding for 32-bit Thumb instructions
- A4.3.1 Data processing instructions: immediate, including bitfield and saturate
- A4.3.2 Data processing instructions, non-immediate
- A4.3.3 Load and store single data item, and memory hints
- A4.3.4 Load/store double and exclusive, and table branch
- A4.3.5 Load and store multiple
- A4.3.6 Branches, miscellaneous control instructions
- A4.3.7 Coprocessor instructions
- A4.4 Conditional execution
- A4.5 UNDEFINED and UNPREDICTABLE instruction set space
- A4.6 Usage of 0b1111 as a register specifier
- A4.7 Usage of 0b1101 as a register specifier
- Thumb Instructions
- A5.1 Format of instruction descriptions
- A5.2 Immediate constants
- A5.3 Constant shifts applied to a register
- A5.4 Memory accesses
- A5.5 Memory hints
- A5.6 NOP-compatible hints
- A5.7 Alphabetical list of Thumb instructions
- A5.7.1 ADC (immediate)
- A5.7.2 ADC (register)
- A5.7.3 ADD (immediate)
- A5.7.4 ADD (register)
- A5.7.5 ADD (SP plus immediate)
- A5.7.6 ADD (SP plus register)
- A5.7.7 ADR
- A5.7.8 AND (immediate)
- A5.7.9 AND (register)
- A5.7.10 ASR (immediate)
- A5.7.11 ASR (register)
- A5.7.12 B
- A5.7.13 BFC
- A5.7.14 BFI
- A5.7.15 BIC (immediate)
- A5.7.16 BIC (register)
- A5.7.17 BKPT
- A5.7.18 BL
- A5.7.19 BLX (register)
- A5.7.20 BX
- A5.7.21 CBNZ
- A5.7.22 CBZ
- A5.7.23 CDP, CDP2
- A5.7.24 CLREX
- A5.7.25 CLZ
- A5.7.26 CMN (immediate)
- A5.7.27 CMN (register)
- A5.7.28 CMP (immediate)
- A5.7.29 CMP (register)
- A5.7.30 CPS
- A5.7.31 CPY
- A5.7.32 DBG
- A5.7.33 DMB
- A5.7.34 DSB
- A5.7.35 EOR (immediate)
- A5.7.36 EOR (register)
- A5.7.37 ISB
- A5.7.38 IT
- A5.7.39 LDC, LDC2
- A5.7.40 LDMDB / LDMEA
- A5.7.41 LDMIA / LDMFD
- A5.7.42 LDR (immediate)
- A5.7.43 LDR (literal)
- A5.7.44 LDR (register)
- A5.7.45 LDRB (immediate)
- A5.7.46 LDRB (literal)
- A5.7.47 LDRB (register)
- A5.7.48 LDRBT
- A5.7.49 LDRD (immediate)
- A5.7.50 LDREX
- A5.7.51 LDREXB
- A5.7.52 LDREXH
- A5.7.53 LDRH (immediate)
- A5.7.54 LDRH (literal)
- A5.7.55 LDRH (register)
- A5.7.56 LDRHT
- A5.7.57 LDRSB (immediate)
- A5.7.58 LDRSB (literal)
- A5.7.59 LDRSB (register)
- A5.7.60 LDRSBT
- A5.7.61 LDRSH (immediate)
- A5.7.62 LDRSH (literal)
- A5.7.63 LDRSH (register)
- A5.7.64 LDRSHT
- A5.7.65 LDRT
- A5.7.66 LSL (immediate)
- A5.7.67 LSL (register)
- A5.7.68 LSR (immediate)
- A5.7.69 LSR (register)
- A5.7.70 MCR, MCR2
- A5.7.71 MCRR, MCRR2
- A5.7.72 MLA
- A5.7.73 MLS
- A5.7.74 MOV (immediate)
- A5.7.75 MOV (register)
- A5.7.76 MOV (shifted register)
- A5.7.77 MOVT
- A5.7.78 MRC, MRC2
- A5.7.79 MRRC, MRRC2
- A5.7.80 MRS
- A5.7.81 MSR (register)
- A5.7.82 MUL
- A5.7.83 MVN (immediate)
- A5.7.84 MVN (register)
- A5.7.85 NEG
- A5.7.86 NOP
- A5.7.87 ORN (immediate)
- A5.7.88 ORN (register)
- A5.7.89 ORR (immediate)
- A5.7.90 ORR (register)
- A5.7.91 PLD (immediate)
- A5.7.92 PLD (register)
- A5.7.93 PLI (immediate)
- A5.7.94 PLI (register)
- A5.7.95 POP
- A5.7.96 PUSH
- A5.7.97 RBIT
- A5.7.98 REV
- A5.7.99 REV16
- A5.7.100 REVSH
- A5.7.101 ROR (immediate)
- A5.7.102 ROR (register)
- A5.7.103 RRX
- A5.7.104 RSB (immediate)
- A5.7.105 RSB (register)
- A5.7.106 SBC (immediate)
- A5.7.107 SBC (register)
- A5.7.108 SBFX
- A5.7.109 SDIV
- A5.7.110 SEV
- A5.7.111 SMLAL
- A5.7.112 SMULL
- A5.7.113 SSAT
- A5.7.114 STC, STC2
- A5.7.115 STMDB / STMFD
- A5.7.116 STMIA / STMEA
- A5.7.117 STR (immediate)
- A5.7.118 STR (register)
- A5.7.119 STRB (immediate)
- A5.7.120 STRB (register)
- A5.7.121 STRBT
- A5.7.122 STRD (immediate)
- A5.7.123 STREX
- A5.7.124 STREXB
- A5.7.125 STREXH
- A5.7.126 STRH (immediate)
- A5.7.127 STRH (register)
- A5.7.128 STRHT
- A5.7.129 STRT
- A5.7.130 SUB (immediate)
- A5.7.131 SUB (register)
- A5.7.132 SUB (SP minus immediate)
- A5.7.133 SUB (SP minus register)
- A5.7.134 SVC (formerly SWI)
- A5.7.135 SXTB
- A5.7.136 SXTH
- A5.7.137 TBB
- A5.7.138 TBH
- A5.7.139 TEQ (immediate)
- A5.7.140 TEQ (register)
- A5.7.141 TST (immediate)
- A5.7.142 TST (register)
- A5.7.143 UBFX
- A5.7.144 UDIV
- A5.7.145 UMLAL
- A5.7.146 UMULL
- A5.7.147 USAT
- A5.7.148 UXTB
- A5.7.149 UXTH
- A5.7.150 WFE
- A5.7.151 WFI
- A5.7.152 YIELD
- System
- System Level Programmer’s Model
- System Address Map
- ARMv7-M System Instructions
- Debug
- Debug
- C1.1 Introduction to debug
- C1.2 The Debug Access Port (DAP)
- C1.3 Overview of the ARMv7-M debug features
- C1.4 Debug and reset
- C1.5 Debug event behavior
- C1.6 Debug register support in the SCS
- C1.7 Instrumentation Trace Macrocell (ITM) support
- C1.8 Data Watchpoint and Trace (DWT) support
- C1.9 Embedded Trace (ETM) support
- C1.10 Trace Port Interface Unit (TPIU)
- C1.11 Flash Patch and Breakpoint (FPB) support
- Pseudo-code definition
- AppxA.1 Instruction encoding diagrams and pseudo-code
- AppxA.2 Data Types
- AppxA.3 Expressions
- AppxA.4 Operators and built-in functions
- AppxA.5 Statements and program structure
- AppxA.6 Helper procedures and functions
- AppxA.6.1 ALUWritePC()
- AppxA.6.2 ArchVersion()
- AppxA.6.3 BadReg()
- AppxA.6.4 BigEndian()
- AppxA.6.5 BranchWritePC()
- AppxA.6.6 BreakPoint()
- AppxA.6.7 BXWritePC()
- AppxA.6.8 CallSupervisor()
- AppxA.6.9 ClearEventRegister()
- AppxA.6.10 ClearExclusiveMonitors()
- AppxA.6.11 ConditionPassed()
- AppxA.6.12 Coproc_Accepted()
- AppxA.6.13 Coproc_DoneLoading()
- AppxA.6.14 Coproc_DoneStoring()
- AppxA.6.15 Coproc_GetOneWord()
- AppxA.6.16 Coproc_GetTwoWords()
- AppxA.6.17 Coproc_GetWordToStore()
- AppxA.6.18 Coproc_InternalOperation()
- AppxA.6.19 Coproc_SendLoadedWord()
- AppxA.6.20 Coproc_SendOneWord()
- AppxA.6.21 Coproc_SendTwoWords()
- AppxA.6.22 DataMemoryBarrier()
- AppxA.6.23 DataSynchronizationBarrier()
- AppxA.6.24 DecodeImmShift(), DecodeRegShift()
- AppxA.6.25 EventRegistered()
- AppxA.6.26 EncodingSpecificOperations()
- AppxA.6.27 ExclusiveMonitorsPass()
- AppxA.6.28 Hint_Debug()
- AppxA.6.29 Hint_PreloadData()
- AppxA.6.30 Hint_PreloadInstr()
- AppxA.6.31 Hint_SendEvent()
- AppxA.6.32 Hint_Yield()
- AppxA.6.33 InITBlock()
- AppxA.6.34 InstructionSynchronizationBarrier()
- AppxA.6.35 IntegerZeroDivideTrappingEnabled()
- AppxA.6.36 LastInITBlock()
- AppxA.6.37 LoadWritePC()
- AppxA.6.38 MemA[]
- AppxA.6.39 MemAA[]
- AppxA.6.40 MemU[]
- AppxA.6.41 MemU_unpriv[]
- AppxA.6.42 R[]
- AppxA.6.43 RaiseCoprocessorException()
- AppxA.6.44 RaiseIntegerZeroDivide()
- AppxA.6.45 SetExclusiveMonitors()
- AppxA.6.46 Shift(), Shift_C()
- AppxA.6.47 StartITBlock()
- AppxA.6.48 ThisInstr()
- AppxA.6.49 ThumbExpandImm(), ThumbExpandImmWithC()
- AppxA.6.50 WaitForEvent()
- AppxA.6.51 WaitForInterrupt()
- Legacy Instruction Mnemonics
- CPUID
- Deprecated Features in ARMv7M
- Glossary