C8051F32x

2017-05-01

• Table of Contents
• List of Figures and Tables
• List of Registers
• 1. System Overview
  • Table 1.1. Product Selection Guide
  • Figure 1.1. C8051F320 Block Diagram
  • Figure 1.2. C8051F321 Block Diagram
  • 1.1. CIP-51™ Microcontroller Core
    • 1.1.1. Fully 8051 Compatible
    • 1.1.2. Improved Throughput
    • 1.1.3. Additional Features
    • Figure 1.3. On-Chip Clock and Reset
  • 1.2. On-Chip Memory
    • Figure 1.4. On-Board Memory Map
  • 1.3. Universal Serial Bus Controller
    • Figure 1.5. USB Controller Block Diagram
  • 1.4. Voltage Regulator
  • 1.5. On-Chip Debug Circuitry
    • Figure 1.6. Development/In-System Debug Diagram
  • 1.6. Programmable Digital I/O and Crossbar
    • Figure 1.7. Digital Crossbar Diagram
  • 1.7. Serial Ports
  • 1.8. Programmable Counter Array
    • Figure 1.9. PCA Block Diagram
  • 1.9. 10-Bit Analog to Digital Converter
    • Figure 1.10. 10-Bit ADC Block Diagram
  • 1.10. Comparators
    • Figure 1.11. Comparator0 Block Diagram
• 2. Absolute Maximum Ratings
  • Table 2.1. Absolute Maximum Ratings
• 3. Global Electrical Characteristics
  • Table 3.1. Global Electrical Characteristics
  • Table 3.2. Index to Electrical Characteristics Tables
• 4. Pinout and Package Definitions
  • Table 4.1. Pin Definitions for the C8051F320/1
  • Figure 4.1. LQFP-32 Pinout Diagram (Top View)
  • Figure 4.4. QFN-28 Pinout Diagram (Top View)
• 5. 10-Bit ADC (ADC0)
  • Figure 5.1. ADC0 Functional Block Diagram
  • 5.1. Analog Multiplexer
  • 5.2. Temperature Sensor
    • Figure 5.2. Temperature Sensor Transfer Function
    • Figure 5.3. Temperature Sensor Error with 1-Point Calibration (VREF = 2.40 V)
  • 5.3. Modes of Operation
    • 5.3.1. Starting a Conversion
    • 5.3.2. Tracking Modes
    • Figure 5.4. 10-Bit ADC Track and Conversion Example Timing
    • 5.3.3. Settling Time Requirements
    • Figure 5.5. ADC0 Equivalent Input Circuits
    • SFR Definition 5.1. AMX0P: AMUX0 Positive Channel Select
    • SFR Definition 5.2. AMX0N: AMUX0 Negative Channel Select
    • SFR Definition 5.3. ADC0CF: ADC0 Configuration
    • SFR Definition 5.4. ADC0H: ADC0 Data Word MSB
    • SFR Definition 5.5. ADC0L: ADC0 Data Word LSB
    • SFR Definition 5.6. ADC0CN: ADC0 Control
  • 5.4. Programmable Window Detector
    • SFR Definition 5.7. ADC0GTH: ADC0 Greater-Than Data High Byte
    • SFR Definition 5.8. ADC0GTL: ADC0 Greater-Than Data Low Byte
    • SFR Definition 5.9. ADC0LTH: ADC0 Less-Than Data High Byte
    • SFR Definition 5.10. ADC0LTL: ADC0 Less-Than Data Low Byte
    • 5.4.1. Window Detector In Single-Ended Mode
    • Figure 5.6. ADC Window Compare Example: Right-Justified Single-Ended Data
    • Figure 5.7. ADC Window Compare Example: Left-Justified Single-Ended Data
    • 5.4.2. Window Detector In Differential Mode
    • Figure 5.8. ADC Window Compare Example: Right-Justified Differential Data
    • Figure 5.9. ADC Window Compare Example: Left-Justified Differential Data
    • Table 5.1. ADC0 Electrical Characteristics
• 6. Voltage Reference
  • Figure 6.1. Voltage Reference Functional Block Diagram
  • SFR Definition 6.1. REF0CN: Reference Control
  • Table 6.1. Voltage Reference Electrical Characteristics
• 7. Comparators
  • Figure 7.1. Comparator0 Functional Block Diagram
  • Figure 7.2. Comparator1 Functional Block Diagram
  • Figure 7.3. Comparator Hysteresis Plot
  • SFR Definition 7.1. CPT0CN: Comparator0 Control
  • SFR Definition 7.2. CPT0MX: Comparator0 MUX Selection
  • SFR Definition 7.3. CPT0MD: Comparator0 Mode Selection
  • SFR Definition 7.4. CPT1CN: Comparator1 Control
  • SFR Definition 7.5. CPT1MX: Comparator1 MUX Selection
  • SFR Definition 7.6. CPT1MD: Comparator1 Mode Selection
  • Table 7.1. Comparator Electrical Characteristics
• 8. Voltage Regulator (REG0)
  • Figure 8.1. External Capacitors for Voltage Regulator Input/Output
  • 8.1. Regulator Mode Selection
  • 8.2. VBUS Detection
    • Table 8.1. Voltage Regulator Electrical Specifications
    • Figure 8.2. REG0 Configuration: USB Bus-Powered
    • Figure 8.3. REG0 Configuration: USB Self-Powered
    • Figure 8.4. REG0 Configuration: USB Self-Powered, Regulator Disabled
    • Figure 8.5. REG0 Configuration: No USB Connection
    • SFR Definition 8.1. REG0CN: Voltage Regulator Control
• 9. CIP-51 Microcontroller
  • Figure 9.1. CIP-51 Block Diagram
  • 9.1. Instruction Set
    • 9.1.1. Instruction and CPU Timing
    • 9.1.2. MOVX Instruction and Program Memory
    • Table 9.1. CIP-51 Instruction Set Summary
  • 9.2. Memory Organization
    • Figure 9.2. Memory Map
    • 9.2.1. Program Memory
    • 9.2.2. Data Memory
    • 9.2.3. General Purpose Registers
    • 9.2.4. Bit Addressable Locations
    • 9.2.5. Stack
    • 9.2.6. Special Function Registers
    • Table 9.2. Special Function Register (SFR) Memory Map
    • Table 9.3. Special Function Registers
    • 9.2.7. Register Descriptions
    • SFR Definition 9.1. DPL: Data Pointer Low Byte
    • SFR Definition 9.2. DPH: Data Pointer High Byte
    • SFR Definition 9.3. SP: Stack Pointer
    • SFR Definition 9.4. PSW: Program Status Word
    • SFR Definition 9.5. ACC: Accumulator
    • SFR Definition 9.6. B: B Register
  • 9.3. Interrupt Handler
    • 9.3.1. MCU Interrupt Sources and Vectors
    • 9.3.2. External Interrupts
    • 9.3.3. Interrupt Priorities
    • 9.3.4. Interrupt Latency
    • Table 9.4. Interrupt Summary
    • 9.3.5. Interrupt Register Descriptions
    • SFR Definition 9.7. IE: Interrupt Enable
    • SFR Definition 9.8. IP: Interrupt Priority
    • SFR Definition 9.9. EIE1: Extended Interrupt Enable 1
    • SFR Definition 9.10. EIP1: Extended Interrupt Priority 1
    • SFR Definition 9.11. EIE2: Extended Interrupt Enable 2
    • SFR Definition 9.12. EIP2: Extended Interrupt Priority 2
    • SFR Definition 9.13. IT01CF: INT0/INT1 Configuration
  • 9.4. Power Management Modes
    • 9.4.1. Idle Mode
    • 9.4.2. Stop Mode
    • SFR Definition 9.14. PCON: Power Control
• 10. Reset Sources
  • Figure 10.1. Reset Sources
  • 10.1. Power-On Reset
    • Figure 10.2. Power-On and VDD Monitor Reset Timing
  • 10.2. Power-Fail Reset / VDD Monitor
    • SFR Definition 10.1. VDM0CN: VDD Monitor Control
  • 10.3. External Reset
  • 10.4. Missing Clock Detector Reset
  • 10.5. Comparator0 Reset
  • 10.6. PCA Watchdog Timer Reset
  • 10.7. Flash Error Reset
  • 10.8. Software Reset
  • 10.9. USB Reset
    • SFR Definition 10.2. RSTSRC: Reset Source
    • Table 10.1. Reset Electrical Characteristics
• 11. Flash Memory
  • 11.1. Programming The Flash Memory
    • 11.1.1. Flash Lock and Key Functions
    • 11.1.2. Flash Erase Procedure
    • 11.1.3. Flash Write Procedure
    • Table 11.1. Flash Electrical Characteristics
  • 11.2. Non-volatile Data Storage
  • 11.3. Security Options
    • Figure 11.1. Flash Program Memory Map and Security Byte
    • Table 11.2. Flash Security Summary
  • 11.4. Flash Write and Erase Guidelines
    • 11.4.1. VDD Maintenance and the VDD Monitor
    • 11.4.2. 16.4.2 PSWE Maintenance
    • 11.4.3. System Clock
    • SFR Definition 11.1. PSCTL: Program Store R/W Control
    • SFR Definition 11.2. FLKEY: Flash Lock and Key
    • SFR Definition 11.3. FLSCL: Flash Scale
• 12. External RAM
  • Figure 12.1. External Ram Memory Map
  • 12.1. Accessing User XRAM
  • 12.2. Accessing USB FIFO Space
    • Figure 12.2. XRAM Memory Map Expanded View
    • SFR Definition 12.1. EMI0CN: External Memory Interface Control
• 13. Oscillators
  • Figure 13.1. Oscillator Diagram
  • 13.1. Programmable Internal Oscillator
    • 13.1.1. Programming the Internal Oscillator on C8051F320/1 Devices
    • 13.1.2. Internal Oscillator Suspend Mode
    • SFR Definition 13.1. OSCICN: Internal Oscillator Control
    • SFR Definition 13.2. OSCICL: Internal Oscillator Calibration
  • 13.2. External Oscillator Drive Circuit
    • 13.2.1. Clocking Timers Directly Through the External Oscillator
    • 13.2.2. External Crystal Example
    • 13.2.3. External RC Example
    • 13.2.4. External Capacitor Example
    • SFR Definition 13.3. OSCXCN: External Oscillator Control
  • 13.3. 4x Clock Multiplier
    • SFR Definition 13.4. CLKMUL: Clock Multiplier Control
  • 13.4. System and USB Clock Selection
    • 13.4.1. System Clock Selection
    • 13.4.2. USB Clock Selection
    • Table 13.1. Typical USB Full Speed Clock Settings
    • Table 13.2. Typical USB Low Speed Clock Settings
    • SFR Definition 13.5. CLKSEL: Clock Select
    • Table 13.3. Internal Oscillator Electrical Characteristics
• 14. Port Input/Output
  • Figure 14.1. Port I/O Functional Block Diagram
  • Figure 14.2. Port I/O Cell Block Diagram
  • 14.1. Priority Crossbar Decoder
    • Figure 14.3. Crossbar Priority Decoder with No Pins Skipped
    • Figure 14.4. Crossbar Priority Decoder with Crystal Pins Skipped
  • 14.2. Port I/O Initialization
    • SFR Definition 14.1. XBR0: Port I/O Crossbar Register 0
    • SFR Definition 14.2. XBR1: Port I/O Crossbar Register 1
  • 14.3. General Purpose Port I/O
    • SFR Definition 14.3. P0: Port0 Register
    • SFR Definition 14.4. P0MDIN: Port0 Input Mode Register
    • SFR Definition 14.5. P0MDOUT: Port0 Output Mode Register
    • SFR Definition 14.6. P0SKIP: Port0 Skip Register
    • SFR Definition 14.7. P1: Port1 Register
    • SFR Definition 14.8. P1MDIN: Port1 Input Mode Register
    • SFR Definition 14.9. P1MDOUT: Port1 Output Mode Register
    • SFR Definition 14.10. P1SKIP: Port1 Skip Register
    • SFR Definition 14.11. P2: Port2 Register
    • SFR Definition 14.12. P2MDIN: Port2 Input Mode Register
    • SFR Definition 14.13. P2MDOUT: Port2 Output Mode Register
    • SFR Definition 14.14. P2SKIP: Port2 Skip Register
    • SFR Definition 14.15. P3: Port3 Register
    • SFR Definition 14.16. P3MDIN: Port3 Input Mode Register
    • SFR Definition 14.17. P3MDOUT: Port3 Output Mode Register
    • Table 14.1. Port I/O DC Electrical Characteristics
• 15. Universal Serial Bus Controller (USB)
  • Figure 15.1. USB0 Block Diagram
  • 15.1. Endpoint Addressing
    • Table 15.1. Endpoint Addressing Scheme
  • 15.2. USB Transceiver
    • SFR Definition 15.1. USB0XCN: USB0 Transceiver Control
  • 15.3. USB Register Access
    • Figure 15.2. USB0 Register Access Scheme
    • SFR Definition 15.2. USB0ADR: USB0 Indirect Address
    • SFR Definition 15.3. USB0DAT: USB0 Data
    • Table 15.2. USB0 Controller Registers
    • USB Register Definition 15.4. INDEX: USB0 Endpoint Index
  • 15.4. USB Clock Configuration
    • USB Register Definition 15.5. CLKREC: Clock Recovery Control
  • 15.5. FIFO Management
    • Figure 15.3. USB FIFO Allocation
    • 15.5.1. FIFO Split Mode
    • 15.5.2. FIFO Double Buffering
    • Table 15.3. FIFO Configurations
    • 15.5.1. FIFO Access
    • USB Register Definition 15.6. FIFOn: USB0 Endpoint FIFO Access
  • 15.6. Function Addressing
    • USB Register Definition 15.7. FADDR: USB0 Function Address
  • 15.7. Function Configuration and Control
    • USB Register Definition 15.8. POWER: USB0 Power
    • USB Register Definition 15.9. FRAMEL: USB0 Frame Number Low
    • USB Register Definition 15.10. FRAMEH: USB0 Frame Number High
  • 15.8. Interrupts
    • USB Register Definition 15.11. IN1INT: USB0 IN Endpoint Interrupt
    • USB Register Definition 15.12. OUT1INT: USB0 Out Endpoint Interrupt
    • USB Register Definition 15.13. CMINT: USB0 Common Interrupt
    • USB Register Definition 15.14. IN1IE: USB0 IN Endpoint Interrupt Enable
    • USB Register Definition 15.15. OUT1IE: USB0 Out Endpoint Interrupt Enable
    • USB Register Definition 15.16. CMIE: USB0 Common Interrupt Enable
  • 15.9. The Serial Interface Engine
  • 15.10. Endpoint0
    • 15.10.1. Endpoint0 SETUP Transactions
    • 15.10.2. Endpoint0 IN Transactions
    • 15.10.3. Endpoint0 OUT Transactions
    • USB Register Definition 15.17. E0CSR: USB0 Endpoint0 Control
    • USB Register Definition 15.18. E0CNT: USB0 Endpoint 0 Data Count
  • 15.11. Configuring Endpoints1–3
  • 15.12. Controlling Endpoints1–3 IN
    • 15.12.1. Endpoints1-3 IN Interrupt or Bulk Mode
    • 15.12.2. Endpoints1-3 IN Isochronous Mode
    • USB Register Definition 15.19. EINCSRL: USB0 IN Endpoint Control Low Byte
    • USB Register Definition 15.20. EINCSRH: USB0 IN Endpoint Control High Byte
  • 15.13. Controlling Endpoints1–3 OUT
    • 15.13.1. Endpoints1-3 OUT Interrupt or Bulk Mode
    • 15.13.2. Endpoints1-3 OUT Isochronous Mode
    • USB Register Definition 15.21. EOUTCSRL: USB0 OUT Endpoint Control High Byte
    • USB Register Definition 15.22. EOUTCSRH: USB0 OUT Endpoint Control Low Byte
    • USB Register Definition 15.23. EOUTCNTL: USB0 OUT Endpoint Count Low
    • USB Register Definition 15.24. EOUTCNTH: USB0 OUT Endpoint Count High
    • Table 15.4. USB Transceiver Electrical Characteristics
• 16. SMBus
  • Figure 16.1. SMBus Block Diagram
  • 16.1. Supporting Documents
  • 16.2. SMBus Configuration
    • Figure 16.2. Typical SMBus Configuration
  • 16.3. SMBus Operation
    • Figure 16.3. SMBus Transaction
    • 16.3.1. Arbitration
    • 16.3.2. Clock Low Extension
    • 16.3.3. SCL Low Timeout
    • 16.3.4. SCL High (SMBus Free) Timeout
  • 16.4. Using the SMBus
    • 16.4.1. SMBus Configuration Register
    • Table 16.1. SMBus Clock Source Selection
    • Figure 16.4. Typical SMBus SCL Generation
    • Table 16.2. Minimum SDA Setup and Hold Times
    • SFR Definition 16.1. SMB0CF: SMBus Clock/Configuration
    • 16.4.2. SMB0CN Control Register
    • SFR Definition 16.2. SMB0CN: SMBus Control
    • Table 16.3. Sources for Hardware Changes to SMB0CN
    • 16.4.3. Data Register
    • SFR Definition 16.3. SMB0DAT: SMBus Data
  • 16.5. SMBus Transfer Modes
    • 16.5.1. Master Transmitter Mode
    • Figure 16.5. Typical Master Transmitter Sequence
    • 16.5.2. Master Receiver Mode
    • Figure 16.6. Typical Master Receiver Sequence
    • 16.5.3. Slave Receiver Mode
    • Figure 16.7. Typical Slave Receiver Sequence
    • 16.5.4. Slave Transmitter Mode
    • Figure 16.8. Typical Slave Transmitter Sequence
  • 16.6. SMBus Status Decoding
    • Table 16.4. SMBus Status Decoding
• 17. UART0
  • Figure 17.1. UART0 Block Diagram
  • 17.1. Enhanced Baud Rate Generation
    • Figure 17.2. UART0 Baud Rate Logic
  • 17.2. Operational Modes
    • Figure 17.3. UART Interconnect Diagram
    • 17.2.1. 8-Bit UART
    • Figure 17.4. 8-Bit UART Timing Diagram
    • 17.2.2. 9-Bit UART
    • Figure 17.5. 9-Bit UART Timing Diagram
  • 17.3. Multiprocessor Communications
    • Figure 17.6. UART Multi-Processor Mode Interconnect Diagram
    • SFR Definition 17.1. SCON0: Serial Port 0 Control
    • SFR Definition 17.2. SBUF0: Serial (UART0) Port Data Buffer
    • Table 17.1. Timer Settings for Standard Baud Rates Using The Internal Oscillator
• 18. Enhanced Serial Peripheral Interface (SPI0)
  • Figure 18.1. SPI Block Diagram
  • 18.1. Signal Descriptions
    • 18.1.1. Master Out, Slave In (MOSI)
    • 18.1.2. Master In, Slave Out (MISO)
    • 18.1.3. Serial Clock (SCK)
    • 18.1.4. Slave Select (NSS)
  • 18.2. SPI0 Master Mode Operation
    • Figure 18.2. Multiple-Master Mode Connection Diagram
    • Figure 18.3. 3-Wire Single Master and Slave Mode Connection Diagram
    • Figure 18.4. 4-Wire Single Master Mode and 4-Wire Slave Mode Connection Diagram
  • 18.3. SPI0 Slave Mode Operation
  • 18.4. SPI0 Interrupt Sources
  • 18.5. Serial Clock Timing
    • Figure 18.5. Master Mode Data/Clock Timing
    • Figure 18.6. Slave Mode Data/Clock Timing (CKPHA = 0)
    • Figure 18.7. Slave Mode Data/Clock Timing (CKPHA = 1)
  • 18.6. SPI Special Function Registers
    • SFR Definition 18.1. SPI0CFG: SPI0 Configuration
    • SFR Definition 18.2. SPI0CN: SPI0 Control
    • SFR Definition 18.3. SPI0CKR: SPI0 Clock Rate
    • SFR Definition 18.4. SPI0DAT: SPI0 Data Register
    • Figure 18.8. SPI Master Timing (CKPHA = 0)
    • Figure 18.9. SPI Master Timing (CKPHA = 1)
    • Figure 18.10. SPI Slave Timing (CKPHA = 0)
    • Figure 18.11. SPI Slave Timing (CKPHA = 1)
    • Table 18.1. SPI Slave Timing Parameters
• 19. Timers
  • 19.1. Timer 0 and Timer 1
    • 19.1.1. Mode 0: 13-bit Counter/Timer
    • Figure 19.1. T0 Mode 0 Block Diagram
    • 19.1.2. Mode 1: 16-bit Counter/Timer
    • 19.1.3. Mode 2: 8-bit Counter/Timer with Auto-Reload
    • Figure 19.2. T0 Mode 2 Block Diagram
    • 19.1.4. Mode 3: Two 8-bit Counter/Timers (Timer 0 Only)
    • Figure 19.3. T0 Mode 3 Block Diagram
    • SFR Definition 19.1. TCON: Timer Control
    • SFR Definition 19.2. TMOD: Timer Mode
    • SFR Definition 19.3. CKCON: Clock Control
    • SFR Definition 19.4. TL0: Timer 0 Low Byte
    • SFR Definition 19.5. TL1: Timer 1 Low Byte
    • SFR Definition 19.6. TH0: Timer 0 High Byte
    • SFR Definition 19.7. TH1: Timer 1 High Byte
  • 19.2. Timer 2
    • 19.2.1. 16-bit Timer with Auto-Reload
    • Figure 19.4. Timer 2 16-Bit Mode Block Diagram
    • 19.2.2. 8-bit Timers with Auto-Reload
    • Figure 19.5. Timer 2 8-Bit Mode Block Diagram
    • 19.2.3. USB Start-of-Frame Capture
    • Figure 19.6. Timer 2 SOF Capture Mode (T2SPLIT = ‘0’)
    • Figure 19.7. Timer 2 SOF Capture Mode (T2SPLIT = ‘1’)
    • SFR Definition 19.8. TMR2CN: Timer 2 Control
    • SFR Definition 19.9. TMR2RLL: Timer 2 Reload Register Low Byte
    • SFR Definition 19.10. TMR2RLH: Timer 2 Reload Register High Byte
    • SFR Definition 19.11. TMR2L: Timer 2 Low Byte
    • SFR Definition 19.12. TMR2H Timer 2 High Byte
  • 19.3. Timer 3
    • 19.3.1. 16-bit Timer with Auto-Reload
    • Figure 19.8. Timer 3 16-Bit Mode Block Diagram
    • 19.3.2. 8-bit Timers with Auto-Reload
    • Figure 19.9. Timer 3 8-Bit Mode Block Diagram
    • 19.3.3. USB Start-of-Frame Capture
    • Figure 19.10. Timer 3 SOF Capture Mode (T3SPLIT = ‘0’)
    • Figure 19.11. Timer 3 SOF Capture Mode (T3SPLIT = ‘1’)
    • SFR Definition 19.13. TMR3CN: Timer 3 Control
    • SFR Definition 19.14. TMR3RLL: Timer 3 Reload Register Low Byte
    • SFR Definition 19.15. TMR3RLH: Timer 3 Reload Register High Byte
    • SFR Definition 19.16. TMR3L: Timer 3 Low Byte
    • SFR Definition 19.17. TMR3H Timer 3 High Byte
• 20. Programmable Counter Array (PCA0)
  • Figure 20.1. PCA Block Diagram
  • 20.1. PCA Counter/Timer
    • Table 20.1. PCA Timebase Input Options
    • Figure 20.2. PCA Counter/Timer Block Diagram
  • 20.2. Capture/Compare Modules
    • Table 20.2. PCA0CPM Register Settings for PCA Capture/Compare Modules
    • Figure 20.3. PCA Interrupt Block Diagram
    • 20.2.1. Edge-triggered Capture Mode
    • Figure 20.4. PCA Capture Mode Diagram
    • 20.2.2. Software Timer (Compare) Mode
    • Figure 20.5. PCA Software Timer Mode Diagram
    • 20.2.3. High Speed Output Mode
    • Figure 20.6. PCA High Speed Output Mode Diagram
    • 20.2.4. Frequency Output Mode
    • Figure 20.7. PCA Frequency Output Mode
    • 20.2.5. 8-Bit Pulse Width Modulator Mode
    • Figure 20.8. PCA 8-Bit PWM Mode Diagram
    • 20.2.6. 16-Bit Pulse Width Modulator Mode
    • Figure 20.9. PCA 16-Bit PWM Mode
  • 20.3. Watchdog Timer Mode
    • 20.3.1. Watchdog Timer Operation
    • Figure 20.10. PCA Module 4 with Watchdog Timer Enabled
    • 20.3.2. Watchdog Timer Usage
    • Table 20.3. Watchdog Timer Timeout Intervals1
  • 20.4. Register Descriptions for PCA
    • SFR Definition 20.1. PCA0CN: PCA Control
    • SFR Definition 20.2. PCA0MD: PCA Mode
    • SFR Definition 20.3. PCA0CPMn: PCA Capture/Compare Mode
    • SFR Definition 20.4. PCA0L: PCA Counter/Timer Low Byte
    • SFR Definition 20.5. PCA0H: PCA Counter/Timer High Byte
    • SFR Definition 20.6. PCA0CPLn: PCA Capture Module Low Byte
    • SFR Definition 20.7. PCA0CPHn: PCA Capture Module High Byte
• 21. C2 Interface
  • 21.1. C2 Interface Registers
    • C2 Register Definition 21.1. C2ADD: C2 Address
    • C2 Register Definition 21.2. C2 Device ID
    • C2 Register Definition 21.3. REVID: C2 Revision ID
    • C2 Register Definition 21.4. FPCTL: C2 Flash Programming Control
    • C2 Register Definition 21.5. FPDAT: C2 Flash Programming Data
  • 21.2. C2 Pin Sharing
    • Figure 21.1. Typical C2 Pin Sharing
• Document Change List