C8051F32x

2017-05-01

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C8051F320/1
Full Speed USB, 16 k ISP FLASH MCU Family
High Speed 8051 µC Core
- Pipelined instruction architecture; executes 70% of

Analog Peripherals
- 10-Bit ADC

•
•
•

instructions in 1 or 2 system clocks

Up to 200 ksps
Up to 17 or 13 external single-ended or differential
inputs
VREF from external pin, internal reference, or VDD
Built-in temperature sensor
External conversion start input

- Up to 25 MIPS throughput with 25 MHz clock
- Expanded interrupt handler
Memory
- 2304 bytes internal RAM (1k + 256 + 1k USB FIFO)
- 16 kB Flash; In-system programmable in 512-byte

- Two Comparators
- Internal Voltage Reference
- POR/Brown-Out Detector
USB Function Controller
- USB specification 2.0 compliant
- Full speed (12 Mbps) or low speed (1.5 Mbps)
-

sectors

Digital Peripherals
- 25/21 Port I/O; All 5 V tolerant with high sink current
- Hardware enhanced SPI™, enhanced UART, and

operation
Integrated clock recovery; no external crystal
required for full speed or low speed
Supports eight flexible endpoints
1 kB USB buffer memory
Integrated transceiver; no external resistors required

On-Chip Debug
- On-chip debug circuitry facilitates full speed,
-

non-intrusive in-system debug (no emulator required)
Provides breakpoints, single stepping,
inspect/modify memory and registers
Superior performance to emulation systems using
ICE-chips, target pods, and sockets

Voltage Regulator Input: 4.0 to 5.25 V

10-bit
200 ksps
ADC

+
+
-

TEMP
SENSOR

VREF

SMBus™ serial ports
Four general purpose 16-bit counter/timers
16-bit programmable counter array (PCA) with five
capture/compare modules
Real time clock mode using external clock source
and PCA or timer

Clock Sources
- Internal Oscillator: 0.25% accuracy with clock
-

recovery enabled. Supports all USB and UART
modes
External oscillator: Crystal, RC, C, or Clock
(1 or 2 pin modes)
Can switch between clock sources on-the-fly;
useful in power saving strategies

RoHS Compliant Packages
- 32-pin LQFP (C8051F320)
- 28-pin QFN (C8051F321)
Temperature Range: –40 to +85 °C

ANALOG
PERIPHERALS
A
M
U
X

VREG

PRECISION INTERNAL
OSCILLATOR

DIGITAL I/O
UART
SPI
SMBus
PCA
Timer 0
Timer 1
Timer 2
Timer 3

CROSSBAR

•
•

Port 0
Port 1
Port 2
Port 3

USB Controller /
Transceiver

HIGH-SPEED CONTROLLER CORE
16 kB
ISP FLASH
16
INTERRUPTS

Rev. 1.4 8/09

8051 CPU
(25MIPS)
DEBUG
CIRCUITRY

2304 B
SRAM
POR

WDT

C8051F32x

C8051F320/1

Rev. 1.4

C8051F320/1
Table of Contents
1. System Overview.................................................................................................... 15
1.1. CIP-51™ Microcontroller Core.......................................................................... 18
1.1.1. Fully 8051 Compatible.............................................................................. 18
1.1.2. Improved Throughput ............................................................................... 18
1.1.3. Additional Features .................................................................................. 18
1.2. On-Chip Memory............................................................................................... 19
1.3. Universal Serial Bus Controller ......................................................................... 20
1.4. Voltage Regulator ............................................................................................. 21
1.5. On-Chip Debug Circuitry................................................................................... 21
1.6. Programmable Digital I/O and Crossbar ........................................................... 22
1.7. Serial Ports ....................................................................................................... 23
1.8. Programmable Counter Array ........................................................................... 23
1.9. 10-Bit Analog to Digital Converter..................................................................... 24
1.10.Comparators..................................................................................................... 25
2. Absolute Maximum Ratings .................................................................................. 27
3. Global Electrical Characteristics .......................................................................... 28
4. Pinout and Package Definitions............................................................................ 30
5. 10-Bit ADC (ADC0).................................................................................................. 39
5.1. Analog Multiplexer ............................................................................................ 40
5.2. Temperature Sensor ......................................................................................... 41
5.3. Modes of Operation .......................................................................................... 43
5.3.1. Starting a Conversion............................................................................... 43
5.3.2. Tracking Modes........................................................................................ 44
5.3.3. Settling Time Requirements ..................................................................... 45
5.4. Programmable Window Detector ...................................................................... 50
5.4.1. Window Detector In Single-Ended Mode ................................................. 52
5.4.2. Window Detector In Differential Mode...................................................... 53
6. Voltage Reference .................................................................................................. 55
7. Comparators ......................................................................................................... 57
8. Voltage Regulator (REG0)...................................................................................... 67
8.1. Regulator Mode Selection................................................................................. 67
8.2. VBUS Detection ................................................................................................ 67
9. CIP-51 Microcontroller .......................................................................................... 71
9.1. Instruction Set ................................................................................................... 72
9.1.1. Instruction and CPU Timing ..................................................................... 72
9.1.2. MOVX Instruction and Program Memory ................................................. 73
9.2. Memory Organization........................................................................................ 77
9.2.1. Program Memory...................................................................................... 77
9.2.2. Data Memory............................................................................................ 78
9.2.3. General Purpose Registers ...................................................................... 78
9.2.4. Bit Addressable Locations........................................................................ 78
9.2.5. Stack ....................................................................................................... 78
9.2.6. Special Function Registers....................................................................... 79

Rev. 1.4

C8051F320/1
9.2.7. Register Descriptions ............................................................................... 83
9.3. Interrupt Handler ............................................................................................... 87
9.3.1. MCU Interrupt Sources and Vectors ........................................................ 87
9.3.2. External Interrupts .................................................................................... 88
9.3.3. Interrupt Priorities ..................................................................................... 88
9.3.4. Interrupt Latency ...................................................................................... 89
9.3.5. Interrupt Register Descriptions................................................................. 90
9.4. Power Management Modes .............................................................................. 97
9.4.1. Idle Mode.................................................................................................. 97
9.4.2. Stop Mode ................................................................................................ 97
10. Reset Sources ....................................................................................................... 99
10.1.Power-On Reset ............................................................................................. 100
10.2.Power-Fail Reset / VDD Monitor .................................................................... 101
10.3.External Reset ................................................................................................ 102
10.4.Missing Clock Detector Reset ........................................................................ 102
10.5.Comparator0 Reset ........................................................................................ 102
10.6.PCA Watchdog Timer Reset .......................................................................... 102
10.7.Flash Error Reset ........................................................................................... 102
10.8.Software Reset ............................................................................................... 103
10.9.USB Reset...................................................................................................... 103
11. Flash Memory ..................................................................................................... 106
11.1.Programming The Flash Memory ................................................................... 106
11.1.1.Flash Lock and Key Functions ............................................................... 106
11.1.2.Flash Erase Procedure .......................................................................... 106
11.1.3.Flash Write Procedure ........................................................................... 107
11.2.Non-volatile Data Storage .............................................................................. 107
11.3.Security Options ............................................................................................. 108
11.4.Flash Write and Erase Guidelines .................................................................. 110
11.4.1.VDD Maintenance and the VDD Monitor ............................................... 110
11.4.2.16.4.2 PSWE Maintenance .................................................................... 111
11.4.3.System Clock ......................................................................................... 111
12. External RAM ...................................................................................................... 114
12.1.Accessing User XRAM ................................................................................... 114
12.2.Accessing USB FIFO Space .......................................................................... 114
13. Oscillators ............................................................................................................. 116
13.1.Programmable Internal Oscillator ................................................................... 116
13.1.1.Programming the Internal Oscillator on C8051F320/1 Devices ............. 117
13.1.2.Internal Oscillator Suspend Mode .......................................................... 118
13.2.External Oscillator Drive Circuit...................................................................... 119
13.2.1.Clocking Timers Directly Through the External Oscillator...................... 119
13.2.2.External Crystal Example....................................................................... 119
13.2.3.External RC Example............................................................................. 120
13.2.4.External Capacitor Example................................................................... 120
13.3.4x Clock Multiplier .......................................................................................... 122
13.4.System and USB Clock Selection .................................................................. 123

Rev. 1.4

C8051F320/1
13.4.1.System Clock Selection ......................................................................... 123
13.4.2.USB Clock Selection .............................................................................. 123
14. Port Input/Output ................................................................................................ 126
14.1.Priority Crossbar Decoder .............................................................................. 128
14.2.Port I/O Initialization ....................................................................................... 130
14.3.General Purpose Port I/O ............................................................................... 132
15. Universal Serial Bus Controller (USB)................................................................ 139
15.1.Endpoint Addressing ...................................................................................... 140
15.2.USB Transceiver ............................................................................................ 140
15.3.USB Register Access ..................................................................................... 142
15.4.USB Clock Configuration................................................................................ 146
15.5.FIFO Management ......................................................................................... 147
15.5.1.FIFO Split Mode ..................................................................................... 147
15.5.2.FIFO Double Buffering ........................................................................... 148
15.5.3.FIFO Access .......................................................................................... 148
15.6.Function Addressing....................................................................................... 149
15.7.Function Configuration and Control................................................................ 149
15.8.Interrupts ........................................................................................................ 152
15.9.The Serial Interface Engine ............................................................................ 157
15.10.Endpoint0 ..................................................................................................... 157
15.10.1.Endpoint0 SETUP Transactions .......................................................... 158
15.10.2.Endpoint0 IN Transactions................................................................... 158
15.10.3.Endpoint0 OUT Transactions............................................................... 159
15.11.Configuring Endpoints1–3 ............................................................................ 161
15.12.Controlling Endpoints1–3 IN......................................................................... 161
15.12.1.Endpoints1-3 IN Interrupt or Bulk Mode............................................... 161
15.12.2.Endpoints1-3 IN Isochronous Mode..................................................... 162
15.13.Controlling Endpoints1–3 OUT..................................................................... 164
15.13.1.Endpoints1-3 OUT Interrupt or Bulk Mode........................................... 164
15.13.2.Endpoints1-3 OUT Isochronous Mode................................................. 165
16. SMBus ................................................................................................................... 169
16.1.Supporting Documents ................................................................................... 170
16.2.SMBus Configuration...................................................................................... 170
16.3.SMBus Operation ........................................................................................... 170
16.3.1.Arbitration............................................................................................... 171
16.3.2.Clock Low Extension.............................................................................. 171
16.3.3.SCL Low Timeout................................................................................... 171
16.3.4.SCL High (SMBus Free) Timeout .......................................................... 172
16.4.Using the SMBus............................................................................................ 172
16.4.1.SMBus Configuration Register............................................................... 173
16.4.2.SMB0CN Control Register ..................................................................... 176
16.4.3.Data Register ......................................................................................... 179
16.5.SMBus Transfer Modes.................................................................................. 180
16.5.1.Master Transmitter Mode ....................................................................... 180
16.5.2.Master Receiver Mode ........................................................................... 181

Rev. 1.4

C8051F320/1
16.5.3.Slave Receiver Mode ............................................................................. 182
16.5.4.Slave Transmitter Mode ......................................................................... 183
16.6.SMBus Status Decoding................................................................................. 184
17. UART0.................................................................................................................... 187
17.1.Enhanced Baud Rate Generation................................................................... 188
17.2.Operational Modes ......................................................................................... 188
17.2.1.8-Bit UART ............................................................................................. 189
17.2.2.9-Bit UART ............................................................................................. 190
17.3.Multiprocessor Communications .................................................................... 190
18. Enhanced Serial Peripheral Interface (SPI0)...................................................... 195
18.1.Signal Descriptions......................................................................................... 196
18.1.1.Master Out, Slave In (MOSI).................................................................. 196
18.1.2.Master In, Slave Out (MISO).................................................................. 196
18.1.3.Serial Clock (SCK) ................................................................................. 196
18.1.4.Slave Select (NSS) ................................................................................ 196
18.2.SPI0 Master Mode Operation ......................................................................... 197
18.3.SPI0 Slave Mode Operation ........................................................................... 198
18.4.SPI0 Interrupt Sources ................................................................................... 199
18.5.Serial Clock Timing......................................................................................... 199
18.6.SPI Special Function Registers ...................................................................... 202
19. Timers ................................................................................................................... 209
19.1.Timer 0 and Timer 1 ....................................................................................... 209
19.1.1.Mode 0: 13-bit Counter/Timer ................................................................ 209
19.1.2.Mode 1: 16-bit Counter/Timer ................................................................ 211
19.1.3.Mode 2: 8-bit Counter/Timer with Auto-Reload...................................... 211
19.1.4.Mode 3: Two 8-bit Counter/Timers (Timer 0 Only)................................. 212
19.2.Timer 2 .......................................................................................................... 217
19.2.1.16-bit Timer with Auto-Reload................................................................ 217
19.2.2.8-bit Timers with Auto-Reload................................................................ 218
19.2.3.USB Start-of-Frame Capture.................................................................. 219
19.3.Timer 3 .......................................................................................................... 222
19.3.1.16-bit Timer with Auto-Reload................................................................ 222
19.3.2.8-bit Timers with Auto-Reload................................................................ 223
19.3.3.USB Start-of-Frame Capture.................................................................. 224
20. Programmable Counter Array (PCA0) ................................................................ 227
20.1.PCA Counter/Timer ........................................................................................ 228
20.2.Capture/Compare Modules ............................................................................ 229
20.2.1.Edge-triggered Capture Mode................................................................ 230
20.2.2.Software Timer (Compare) Mode........................................................... 232
20.2.3.High Speed Output Mode....................................................................... 233
20.2.4.Frequency Output Mode ........................................................................ 234
20.2.5.8-Bit Pulse Width Modulator Mode......................................................... 235
20.2.6.16-Bit Pulse Width Modulator Mode....................................................... 236
20.3.Watchdog Timer Mode ................................................................................... 236
20.3.1.Watchdog Timer Operation .................................................................... 237

Rev. 1.4

C8051F320/1
20.3.2.Watchdog Timer Usage ......................................................................... 238
20.4.Register Descriptions for PCA........................................................................ 239
21. C2 Interface ........................................................................................................... 245
21.1.C2 Interface Registers.................................................................................... 245
21.2.C2 Pin Sharing ............................................................................................... 247

Rev. 1.4

C8051F320/1

Rev. 1.4

C8051F320/1
List of Figures and Tables
1. System Overview
Table 1.1. Product Selection Guide ........................................................................ 16
Figure 1.1. C8051F320 Block Diagram .................................................................... 16
Figure 1.2. C8051F321 Block Diagram .................................................................... 17
Figure 1.3. On-Chip Clock and Reset ...................................................................... 19
Figure 1.4. On-Board Memory Map.......................................................................... 20
Figure 1.5. USB Controller Block Diagram............................................................... 21
Figure 1.6. Development/In-System Debug Diagram............................................... 22
Figure 1.7. Digital Crossbar Diagram ....................................................................... 23
Figure 1.8. PCA Block Diagram ............................................................................... 24
Figure 1.9. PCA Block Diagram ............................................................................... 24
Figure 1.10. 10-Bit ADC Block Diagram ................................................................... 25
Figure 1.11. Comparator0 Block Diagram ................................................................ 26
2. Absolute Maximum Ratings
Table 2.1. Absolute Maximum Ratings .................................................................... 27
3. Global Electrical Characteristics
Table 3.1. Global Electrical Characteristics ............................................................. 28
Table 3.2. Index to Electrical Characteristics Tables .............................................. 29
4. Pinout and Package Definitions
Table 4.1. Pin Definitions for the C8051F320/1 ...................................................... 30
Figure 4.1. LQFP-32 Pinout Diagram (Top View) .................................................... 32
Figure 4.2. QFN-28 Pinout Diagram (Top View) ...................................................... 36
5. 10-Bit ADC (ADC0)
Figure 5.1. ADC0 Functional Block Diagram............................................................ 39
Figure 5.2. Temperature Sensor Transfer Function ................................................. 41
Figure 5.3. Temperature Sensor Error with 1-Point Calibration (VREF = 2.40 V).... 42
Figure 5.4. 10-Bit ADC Track and Conversion Example Timing .............................. 44
Figure 5.5. ADC0 Equivalent Input Circuits.............................................................. 45
Figure 5.6. ADC Window Compare Example: Right-Justified Single-Ended Data ... 52
Figure 5.7. ADC Window Compare Example: Left-Justified Single-Ended Data ..... 52
Figure 5.8. ADC Window Compare Example: Right-Justified Differential Data ....... 53
Figure 5.9. ADC Window Compare Example: Left-Justified Differential Data.......... 53
Table 5.1. ADC0 Electrical Characteristics ............................................................. 54
6. Voltage Reference
Figure 6.1. Voltage Reference Functional Block Diagram ....................................... 55
Table 6.1. Voltage Reference Electrical Characteristics ......................................... 56
7. Comparators
Figure 7.1. Comparator0 Functional Block Diagram ................................................ 57
Figure 7.2. Comparator1 Functional Block Diagram ................................................ 58
Figure 7.3. Comparator Hysteresis Plot ................................................................... 59
Table 7.1. Comparator Electrical Characteristics .................................................... 66
8. Voltage Regulator (REG0)

Rev. 1.4

C8051F320/1
Figure 8.1. External Capacitors for Voltage Regulator Input/Output ........................ 67
Table 8.1. Voltage Regulator Electrical Specifications ............................................ 68
Figure 8.2. REG0 Configuration: USB Bus-Powered ............................................... 68
Figure 8.3. REG0 Configuration: USB Self-Powered ............................................... 69
Figure 8.4. REG0 Configuration: USB Self-Powered, Regulator Disabled .............. 69
Figure 8.5. REG0 Configuration: No USB Connection............................................. 70
9. CIP-51 Microcontroller
Figure 9.1. CIP-51 Block Diagram............................................................................ 71
Table 9.1. CIP-51 Instruction Set Summary............................................................ 73
Figure 9.2. Memory Map .......................................................................................... 77
Table 9.2. Special Function Register (SFR) Memory Map...................................... 79
Table 9.3. Special Function Registers .................................................................... 80
Table 9.4. Interrupt Summary ................................................................................. 89
10. Reset Sources
Figure 10.1. Reset Sources...................................................................................... 99
Figure 10.2. Power-On and VDD Monitor Reset Timing ........................................ 100
Table 10.1. Reset Electrical Characteristics .......................................................... 105
11. Flash Memory
Table 11.1. Flash Electrical Characteristics .......................................................... 107
Figure 11.1. Flash Program Memory Map and Security Byte................................. 108
Table 11.2. Flash Security Summary ..................................................................... 109
12. External RAM
Figure 12.1. External Ram Memory Map................................................................ 114
Figure 12.2. XRAM Memory Map Expanded View ................................................. 115
13. Oscillators
Figure 13.1. Oscillator Diagram.............................................................................. 116
Table 13.1. Typical USB Full Speed Clock Settings............................................... 123
Table 13.2. Typical USB Low Speed Clock Settings.............................................. 124
Table 13.3. Internal Oscillator Electrical Characteristics ....................................... 125
14. Port Input/Output
Figure 14.1. Port I/O Functional Block Diagram ..................................................... 126
Figure 14.2. Port I/O Cell Block Diagram ............................................................... 127
Figure 14.3. Crossbar Priority Decoder with No Pins Skipped ............................... 128
Figure 14.4. Crossbar Priority Decoder with Crystal Pins Skipped ........................ 129
Table 14.1. Port I/O DC Electrical Characteristics ................................................ 138
15. Universal Serial Bus Controller (USB)
Figure 15.1. USB0 Block Diagram.......................................................................... 139
Table 15.1. Endpoint Addressing Scheme ............................................................. 140
Figure 15.2. USB0 Register Access Scheme......................................................... 142
Table 15.2. USB0 Controller Registers .................................................................. 144
Figure 15.3. USB FIFO Allocation .......................................................................... 147
Table 15.3. FIFO Configurations ............................................................................ 148
Table 15.4. USB Transceiver Electrical Characteristics ........................................ 168
16. SMBus
Figure 16.1. SMBus Block Diagram ....................................................................... 169

Rev. 1.4

C8051F320/1
Figure 16.2. Typical SMBus Configuration ............................................................. 170
Figure 16.3. SMBus Transaction ............................................................................ 171
Table 16.1. SMBus Clock Source Selection........................................................... 173
Figure 16.4. Typical SMBus SCL Generation......................................................... 174
Table 16.2. Minimum SDA Setup and Hold Times ................................................. 174
Table 16.3. Sources for Hardware Changes to SMB0CN ...................................... 178
Figure 16.5. Typical Master Transmitter Sequence................................................ 180
Figure 16.6. Typical Master Receiver Sequence.................................................... 181
Figure 16.7. Typical Slave Receiver Sequence...................................................... 182
Figure 16.8. Typical Slave Transmitter Sequence.................................................. 183
Table 16.4. SMBus Status Decoding...................................................................... 184
17. UART0
Figure 17.1. UART0 Block Diagram ....................................................................... 187
Figure 17.2. UART0 Baud Rate Logic .................................................................... 188
Figure 17.3. UART Interconnect Diagram .............................................................. 189
Figure 17.4. 8-Bit UART Timing Diagram............................................................... 189
Figure 17.5. 9-Bit UART Timing Diagram............................................................... 190
Figure 17.6. UART Multi-Processor Mode Interconnect Diagram .......................... 191
Table 17.1. Timer Settings for Standard Baud Rates Using The Internal Oscillator ....
194
18. Enhanced Serial Peripheral Interface (SPI0)
Figure 18.1. SPI Block Diagram ............................................................................. 195
Figure 18.2. Multiple-Master Mode Connection Diagram ....................................... 198
Figure 18.3. 3-Wire Single Master and Slave Mode Connection Diagram ............. 198
Figure 18.4. 4-Wire Single Master Mode and 4-Wire Slave Mode Connection Diagram
198
Figure 18.5. Master Mode Data/Clock Timing ........................................................ 200
Figure 18.6. Slave Mode Data/Clock Timing (CKPHA = 0) .................................... 200
Figure 18.7. Slave Mode Data/Clock Timing (CKPHA = 1) .................................... 201
Figure 18.8. SPI Master Timing (CKPHA = 0)........................................................ 206
Figure 18.9. SPI Master Timing (CKPHA = 1)........................................................ 206
Figure 18.10. SPI Slave Timing (CKPHA = 0)........................................................ 207
Figure 18.11. SPI Slave Timing (CKPHA = 1)........................................................ 207
Table 18.1. SPI Slave Timing Parameters ............................................................. 208
19. Timers
Figure 19.1. T0 Mode 0 Block Diagram.................................................................. 210
Figure 19.2. T0 Mode 2 Block Diagram.................................................................. 211
Figure 19.3. T0 Mode 3 Block Diagram.................................................................. 212
Figure 19.4. Timer 2 16-Bit Mode Block Diagram .................................................. 217
Figure 19.5. Timer 2 8-Bit Mode Block Diagram .................................................... 218
Figure 19.6. Timer 2 SOF Capture Mode (T2SPLIT = ‘0’)...................................... 219
Figure 19.7. Timer 2 SOF Capture Mode (T2SPLIT = ‘1’)...................................... 219
Figure 19.8. Timer 3 16-Bit Mode Block Diagram .................................................. 222
Figure 19.9. Timer 3 8-Bit Mode Block Diagram .................................................... 223
Figure 19.10. Timer 3 SOF Capture Mode (T3SPLIT = ‘0’).................................... 224

Rev. 1.4

C8051F320/1
Figure 19.11. Timer 3 SOF Capture Mode (T3SPLIT = ‘1’).................................... 224
20. Programmable Counter Array (PCA0)
Figure 20.1. PCA Block Diagram............................................................................ 227
Table 20.1. PCA Timebase Input Options .............................................................. 228
Figure 20.2. PCA Counter/Timer Block Diagram.................................................... 228
Table 20.2. PCA0CPM Register Settings for PCA Capture/Compare Modules ..... 229
Figure 20.3. PCA Interrupt Block Diagram ............................................................. 230
Figure 20.4. PCA Capture Mode Diagram.............................................................. 231
Figure 20.5. PCA Software Timer Mode Diagram .................................................. 232
Figure 20.6. PCA High Speed Output Mode Diagram............................................ 233
Figure 20.7. PCA Frequency Output Mode ............................................................ 234
Figure 20.8. PCA 8-Bit PWM Mode Diagram ......................................................... 235
Figure 20.9. PCA 16-Bit PWM Mode...................................................................... 236
Figure 20.10. PCA Module 4 with Watchdog Timer Enabled ................................. 237
Table 20.3. Watchdog Timer Timeout Intervals1 ................................................................... 239
21. C2 Interface
Figure 21.1. Typical C2 Pin Sharing....................................................................... 247

Rev. 1.4

C8051F320/1
List of Registers
SFR Definition 5.1. AMX0P: AMUX0 Positive Channel Select . . . . . . . . . . . . . . . . . . 46
SFR Definition 5.2. AMX0N: AMUX0 Negative Channel Select . . . . . . . . . . . . . . . . . . 47
SFR Definition 5.3. ADC0CF: ADC0 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
SFR Definition 5.4. ADC0H: ADC0 Data Word MSB . . . . . . . . . . . . . . . . . . . . . . . . . . 48
SFR Definition 5.5. ADC0L: ADC0 Data Word LSB . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
SFR Definition 5.6. ADC0CN: ADC0 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
SFR Definition 5.7. ADC0GTH: ADC0 Greater-Than Data High Byte . . . . . . . . . . . . . 50
SFR Definition 5.8. ADC0GTL: ADC0 Greater-Than Data Low Byte . . . . . . . . . . . . . 50
SFR Definition 5.9. ADC0LTH: ADC0 Less-Than Data High Byte . . . . . . . . . . . . . . . . 51
SFR Definition 5.10. ADC0LTL: ADC0 Less-Than Data Low Byte . . . . . . . . . . . . . . . 51
SFR Definition 6.1. REF0CN: Reference Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
SFR Definition 7.1. CPT0CN: Comparator0 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
SFR Definition 7.2. CPT0MX: Comparator0 MUX Selection . . . . . . . . . . . . . . . . . . . . 61
SFR Definition 7.3. CPT0MD: Comparator0 Mode Selection . . . . . . . . . . . . . . . . . . . . 62
SFR Definition 7.4. CPT1CN: Comparator1 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
SFR Definition 7.5. CPT1MX: Comparator1 MUX Selection . . . . . . . . . . . . . . . . . . . . 64
SFR Definition 7.6. CPT1MD: Comparator1 Mode Selection . . . . . . . . . . . . . . . . . . . . 65
SFR Definition 8.1. REG0CN: Voltage Regulator Control . . . . . . . . . . . . . . . . . . . . . . 70
SFR Definition 9.1. DPL: Data Pointer Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
SFR Definition 9.2. DPH: Data Pointer High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
SFR Definition 9.3. SP: Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
SFR Definition 9.4. PSW: Program Status Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
SFR Definition 9.5. ACC: Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
SFR Definition 9.6. B: B Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
SFR Definition 9.7. IE: Interrupt Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
SFR Definition 9.8. IP: Interrupt Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
SFR Definition 9.9. EIE1: Extended Interrupt Enable 1 . . . . . . . . . . . . . . . . . . . . . . . . 93
SFR Definition 9.10. EIP1: Extended Interrupt Priority 1 . . . . . . . . . . . . . . . . . . . . . . . 94
SFR Definition 9.11. EIE2: Extended Interrupt Enable 2 . . . . . . . . . . . . . . . . . . . . . . . 95
SFR Definition 9.12. EIP2: Extended Interrupt Priority 2 . . . . . . . . . . . . . . . . . . . . . . . 95
SFR Definition 9.13. IT01CF: INT0/INT1 Configuration . . . . . . . . . . . . . . . . . . . . . . . . 96
SFR Definition 9.14. PCON: Power Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
SFR Definition 10.1. VDM0CN: VDD Monitor Control . . . . . . . . . . . . . . . . . . . . . . . . 101
SFR Definition 10.2. RSTSRC: Reset Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
SFR Definition 11.1. PSCTL: Program Store R/W Control . . . . . . . . . . . . . . . . . . . . . 112
SFR Definition 11.2. FLKEY: Flash Lock and Key . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
SFR Definition 11.3. FLSCL: Flash Scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
SFR Definition 12.1. EMI0CN: External Memory Interface Control . . . . . . . . . . . . . . 115
SFR Definition 13.1. OSCICN: Internal Oscillator Control . . . . . . . . . . . . . . . . . . . . . 118
SFR Definition 13.2. OSCICL: Internal Oscillator Calibration . . . . . . . . . . . . . . . . . . . 118
SFR Definition 13.3. OSCXCN: External Oscillator Control . . . . . . . . . . . . . . . . . . . . 121
SFR Definition 13.4. CLKMUL: Clock Multiplier Control . . . . . . . . . . . . . . . . . . . . . . . 122
SFR Definition 13.5. CLKSEL: Clock Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

Rev. 1.4

C8051F320/1
SFR Definition 14.1. XBR0: Port I/O Crossbar Register 0 . . . . . . . . . . . . . . . . . . . . . 131
SFR Definition 14.2. XBR1: Port I/O Crossbar Register 1 . . . . . . . . . . . . . . . . . . . . . 132
SFR Definition 14.3. P0: Port0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
SFR Definition 14.4. P0MDIN: Port0 Input Mode Register . . . . . . . . . . . . . . . . . . . . . 133
SFR Definition 14.5. P0MDOUT: Port0 Output Mode Register . . . . . . . . . . . . . . . . . 133
SFR Definition 14.6. P0SKIP: Port0 Skip Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
SFR Definition 14.7. P1: Port1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
SFR Definition 14.8. P1MDIN: Port1 Input Mode Register . . . . . . . . . . . . . . . . . . . . . 134
SFR Definition 14.9. P1MDOUT: Port1 Output Mode Register . . . . . . . . . . . . . . . . . 135
SFR Definition 14.10. P1SKIP: Port1 Skip Register . . . . . . . . . . . . . . . . . . . . . . . . . . 135
SFR Definition 14.11. P2: Port2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
SFR Definition 14.12. P2MDIN: Port2 Input Mode Register . . . . . . . . . . . . . . . . . . . . 136
SFR Definition 14.13. P2MDOUT: Port2 Output Mode Register . . . . . . . . . . . . . . . . 136
SFR Definition 14.14. P2SKIP: Port2 Skip Register . . . . . . . . . . . . . . . . . . . . . . . . . . 136
SFR Definition 14.15. P3: Port3 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
SFR Definition 14.16. P3MDIN: Port3 Input Mode Register . . . . . . . . . . . . . . . . . . . . 137
SFR Definition 14.17. P3MDOUT: Port3 Output Mode Register . . . . . . . . . . . . . . . . 137
SFR Definition 15.1. USB0XCN: USB0 Transceiver Control . . . . . . . . . . . . . . . . . . . 141
SFR Definition 15.2. USB0ADR: USB0 Indirect Address . . . . . . . . . . . . . . . . . . . . . . 143
SFR Definition 15.3. USB0DAT: USB0 Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
USB Register Definition 15.4. INDEX: USB0 Endpoint Index . . . . . . . . . . . . . . . . . . . 145
USB Register Definition 15.5. CLKREC: Clock Recovery Control . . . . . . . . . . . . . . . 146
USB Register Definition 15.6. FIFOn: USB0 Endpoint FIFO Access . . . . . . . . . . . . . 148
USB Register Definition 15.7. FADDR: USB0 Function Address . . . . . . . . . . . . . . . . 149
USB Register Definition 15.8. POWER: USB0 Power . . . . . . . . . . . . . . . . . . . . . . . . 151
USB Register Definition 15.9. FRAMEL: USB0 Frame Number Low . . . . . . . . . . . . . 152
USB Register Definition 15.10. FRAMEH: USB0 Frame Number High . . . . . . . . . . . 152
USB Register Definition 15.11. IN1INT: USB0 IN Endpoint Interrupt . . . . . . . . . . . . 153
USB Register Definition 15.12. OUT1INT: USB0 Out Endpoint Interrupt . . . . . . . . . . 154
USB Register Definition 15.13. CMINT: USB0 Common Interrupt . . . . . . . . . . . . . . . 155
USB Register Definition 15.14. IN1IE: USB0 IN Endpoint Interrupt Enable . . . . . . . . 156
USB Register Definition 15.15. OUT1IE: USB0 Out Endpoint Interrupt Enable . . . . . 156
USB Register Definition 15.16. CMIE: USB0 Common Interrupt Enable . . . . . . . . . . 157
USB Register Definition 15.17. E0CSR: USB0 Endpoint0 Control . . . . . . . . . . . . . . . 160
USB Register Definition 15.18. E0CNT: USB0 Endpoint 0 Data Count . . . . . . . . . . . 161
USB Register Definition 15.19. EINCSRL: USB0 IN Endpoint Control Low Byte . . . . 163
USB Register Definition 15.20. EINCSRH: USB0 IN Endpoint Control High Byte . . . 164
USB Register Definition 15.21. EOUTCSRL: USB0 OUT Endpoint Control High Byte . .
166
USB Register Definition 15.22. EOUTCSRH: USB0 OUT Endpoint Control Low Byte . .
167
USB Register Definition 15.23. EOUTCNTL: USB0 OUT Endpoint Count Low . . . . . 167
USB Register Definition 15.24. EOUTCNTH: USB0 OUT Endpoint Count High . . . . 167
SFR Definition 16.1. SMB0CF: SMBus Clock/Configuration . . . . . . . . . . . . . . . . . . . 175
SFR Definition 16.2. SMB0CN: SMBus Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

Rev. 1.4

C8051F320/1
SFR Definition 16.3. SMB0DAT: SMBus Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
SFR Definition 17.1. SCON0: Serial Port 0 Control . . . . . . . . . . . . . . . . . . . . . . . . . . 192
SFR Definition 17.2. SBUF0: Serial (UART0) Port Data Buffer . . . . . . . . . . . . . . . . . 193
SFR Definition 18.1. SPI0CFG: SPI0 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 203
SFR Definition 18.2. SPI0CN: SPI0 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
SFR Definition 18.3. SPI0CKR: SPI0 Clock Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
SFR Definition 18.4. SPI0DAT: SPI0 Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . 205
SFR Definition 19.1. TCON: Timer Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
SFR Definition 19.2. TMOD: Timer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
SFR Definition 19.3. CKCON: Clock Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
SFR Definition 19.4. TL0: Timer 0 Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
SFR Definition 19.5. TL1: Timer 1 Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
SFR Definition 19.6. TH0: Timer 0 High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
SFR Definition 19.7. TH1: Timer 1 High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
SFR Definition 19.8. TMR2CN: Timer 2 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
SFR Definition 19.9. TMR2RLL: Timer 2 Reload Register Low Byte . . . . . . . . . . . . . 221
SFR Definition 19.10. TMR2RLH: Timer 2 Reload Register High Byte . . . . . . . . . . . 221
SFR Definition 19.11. TMR2L: Timer 2 Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
SFR Definition 19.12. TMR2H Timer 2 High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
SFR Definition 19.13. TMR3CN: Timer 3 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
SFR Definition 19.14. TMR3RLL: Timer 3 Reload Register Low Byte . . . . . . . . . . . . 226
SFR Definition 19.15. TMR3RLH: Timer 3 Reload Register High Byte . . . . . . . . . . . 226
SFR Definition 19.16. TMR3L: Timer 3 Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
SFR Definition 19.17. TMR3H Timer 3 High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
SFR Definition 20.1. PCA0CN: PCA Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
SFR Definition 20.2. PCA0MD: PCA Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
SFR Definition 20.3. PCA0CPMn: PCA Capture/Compare Mode . . . . . . . . . . . . . . . 242
SFR Definition 20.4. PCA0L: PCA Counter/Timer Low Byte . . . . . . . . . . . . . . . . . . . 243
SFR Definition 20.5. PCA0H: PCA Counter/Timer High Byte . . . . . . . . . . . . . . . . . . 243
SFR Definition 20.6. PCA0CPLn: PCA Capture Module Low Byte . . . . . . . . . . . . . . . 243
SFR Definition 20.7. PCA0CPHn: PCA Capture Module High Byte . . . . . . . . . . . . . . 244
C2 Register Definition 21.1. C2ADD: C2 Address . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
C2 Register Definition 21.2. C2 Device ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
C2 Register Definition 21.3. REVID: C2 Revision ID . . . . . . . . . . . . . . . . . . . . . . . . . 246
C2 Register Definition 21.4. FPCTL: C2 Flash Programming Control . . . . . . . . . . . . 246
C2 Register Definition 21.5. FPDAT: C2 Flash Programming Data . . . . . . . . . . . . . . 246

Rev. 1.4

C8051F320/1

Rev. 1.4

C8051F320/1
1.

System Overview

C8051F320/1 devices are fully integrated mixed-signal System-on-a-Chip MCUs. Highlighted features are
listed below. Refer to Table 1.1 for specific product feature selection.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•

High-speed pipelined 8051-compatible microcontroller core (up to 25 MIPS)
In-system, full-speed, non-intrusive debug interface (on-chip)
Universal Serial Bus (USB) Function Controller with eight flexible endpoint pipes, integrated transceiver, and 1k FIFO RAM
Supply Voltage Regulator (5-to-3 V)
True 10-bit 200 ksps 17-channel single-ended/differential ADC with analog multiplexer
On-chip Voltage Reference and Temperature Sensor
On-chip Voltage Comparators (2)
Precision programmable 12 MHz internal oscillator and 4x clock multiplier
16 kB of on-chip Flash memory
2304 total bytes of on-chip RAM (256 + 1k + 1k USB FIFO)
SMBus/I2C, Enhanced UART, and Enhanced SPI serial interfaces implemented in hardware
Four general-purpose 16-bit timers
Programmable Counter/Timer Array (PCA) with five capture/compare modules and Watchdog Timer
function
On-chip Power-On Reset, VDD Monitor, and Missing Clock Detector
25/21 Port I/O (5 V tolerant)

With on-chip Power-On Reset, VDD monitor, Voltage Regulator, Watchdog Timer, and clock oscillator,
C8051F320/1 devices are truly stand-alone System-on-a-Chip solutions. The Flash memory can be reprogrammed in-circuit, providing non-volatile data storage, and also allowing field upgrades of the 8051 firmware. User software has complete control of all peripherals and may individually shut down any or all
peripherals for power savings.
The on-chip Silicon Labs 2-Wire (C2) Development Interface allows non-intrusive (uses no on-chip
resources), full speed, in-circuit debugging using the production MCU installed in the final application. This
debug logic supports inspection and modification of memory and registers, setting breakpoints, single
stepping, run and halt commands. All analog and digital peripherals are fully functional while debugging
using C2. The two C2 interface pins can be shared with user functions, allowing in-system debugging without occupying package pins.
Each device is specified for 2.7-to-3.6 V operation over the industrial temperature range (–40 to +85 °C).
(Note that 3.0-to-3.6 V is required for USB communication.) The Port I/O and /RST pins are tolerant of
input signals up to 5 V. C8051F320/1 are available in a 32-pin LQFP or a 28-pin QFN package.

Rev. 1.4

C8051F320/1

USB

Supply Voltage Regulator

SMBus/I2C

Enhanced SPI

UART

Timers (16-bit)

Programmable Counter Array

Digital Port I/Os

10-bit 200ksps ADC

Temperature Sensor

Voltage Reference

Analog Comparators

Package (lead-free, RoHS-compliant)

C8051F320-GQ 25

16 k 2304 



LQFP-32

C8051F321-GM 25

16 k 2304 



QFN-28

5.0V
REGIN

RAM

MIPS (Peak)

Flash Memory

Calibrated Internal Oscillator

Table 1.1. Product Selection Guide

Voltage
Regulator

Enable

OUT
VDD

Analog/Digital
Power

C2D

Debug HW
Reset
/RST/C2CK

BrownOut

External
Oscillator
Circuit

System
Clock

D+
D-

VBUS

D
r
v

8
0
5
1

C
R
O
S
S
B
A
R

16kbyte
FLASH

PCA/
WDT

256 byte
SRAM

D
r
v

SMBus

P
2

SPI

C
o
r SFR Bus
e

D
r
v

Port 2
Latch

P
3
Port 3
Latch

D
r
v

USB Clock

1,2,3,4

CP0

+
-

CP1

+
-

VREF

USB
Transceiver

USB
Controller

VDD
Temp

10-bit
200ksps
ADC

1K byte USB
SRAM

Figure 1.1. C8051F320 Block Diagram

P
1

VREF

2
Clock
Recovery

Port 1
Latch

Timer
0,1,2,3 /
RTC

1K byte
XRAM

XTAL1 XTAL2

12MHz
Internal
Oscillator

P
0

UART

GND

POR

Port 0
Latch

Rev. 1.4

A
M
U
X

AIN0-AIN16
VDD
VREF

P0.0
P0.1
P0.2/XTAL1
P0.3/XTAL2
P0.4
P0.5
P0.6/CNVSTR
P0.7/VREF
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
P3.0/C2D

C8051F320/1

5.0V
REGIN

Voltage
IN
Regulator

Enable

OUT
VDD

Analog/Digital
Power

C2D

Debug HW
Reset
/RST/C2CK

BrownOut

External
Oscillator
Circuit

System
Clock

D+
D-

VBUS

D
r
v

8
0
5
1

C
R
O
S
S
B
A
R

16kbyte
FLASH

PCA/
WDT

256 byte
SRAM

P
1
D
r
v

SMBus

P
2

SPI

C
o
r SFR Bus
e

P0.0
P0.1
P0.2/XTAL1
P0.3/XTAL2
P0.4
P0.5
P0.6/CNVSTR
P0.7/VREF
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P2.0
P2.1
P2.2
P2.3

D
r
v

Port 2
Latch

P
3
Port 3
Latch

P3.0/C2D

D
r
v

VREF

2
Clock
Recovery

Port 1
Latch

Timer
0,1,2,3 /
RTC

1K byte
XRAM

XTAL1 XTAL2

12MHz
Internal
Oscillator

P
0

UART

GND

POR

Port 0
Latch

USB Clock

1,2,3,4

CP0

+
-

CP1

+
-

VREF

USB
Transceiver

USB
Controller

VDD
Temp

10-bit
200ksps
ADC

1K byte USB
SRAM

A
M
U
X

AIN0-AIN11
VDD
VREF

Figure 1.2. C8051F321 Block Diagram

Rev. 1.4

C8051F320/1
1.1.

CIP-51™ Microcontroller Core

1.1.1. Fully 8051 Compatible
The C8051F320/1 family utilizes Silicon Labs' proprietary CIP-51 microcontroller core. The CIP-51 is fully
compatible with the MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used
to develop software. The CIP-51 core offers all the peripherals included with a standard 8052, including
four 16-bit counter/timers, a full-duplex UART with extended baud rate configuration, an enhanced SPI
port, 2304 bytes of on-chip RAM, 128 byte Special Function Register (SFR) address space, and 25/21 I/O
pins.

1.1.2. Improved Throughput
The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the standard 8051 architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24 system
clock cycles to execute with a maximum system clock of 12-to-24 MHz. By contrast, the CIP-51 core executes 70% of its instructions in one or two system clock cycles, with only four instructions taking more than
four system clock cycles.
The CIP-51 has a total of 109 instructions. The table below shows the total number of instructions that
require each execution time.
Clocks to Execute

2/3

3/4

4/5

Number of Instructions

1.1.3. Additional Features
The C8051F320/1 SoC family includes several key enhancements to the CIP-51 core and peripherals to
improve performance and ease of use in end applications.
The extended interrupt handler provides 16 interrupt sources into the CIP-51 (as opposed to 7 for the standard 8051), allowing numerous analog and digital peripherals to interrupt the controller. An interrupt driven
system requires less intervention by the MCU, giving it more effective throughput. The extra interrupt
sources are very useful when building multi-tasking, real-time systems.
Nine reset sources are available: power-on reset circuitry (POR), an on-chip VDD monitor (forces reset
when power supply voltage drops below VRST as given in Table 10.1 on page 105), the USB controller
(USB bus reset or a VBUS transition), a Watchdog Timer, a Missing Clock Detector, a voltage level detection from Comparator0, a forced software reset, an external reset pin, and an errant Flash read/write protection circuit. Each reset source except for the POR, Reset Input Pin, or Flash error may be disabled by
the user in software. The WDT may be permanently enabled in software after a power-on reset during
MCU initialization.
The internal oscillator is factory calibrated to 12 MHz ±1.5%, and the internal oscillator period may be user
programmed in ~0.25% increments. A clock recovery mechanism allows the internal oscillator to be used
with the 4x Clock Multiplier as the USB clock source in Full Speed mode; the internal oscillator can also be
used as the USB clock source in Low Speed mode. External oscillators may also be used with the 4x Clock
Multiplier. An external oscillator drive circuit is also included, allowing an external crystal, ceramic resonator, capacitor, RC, or CMOS clock source to generate the system clock. The system clock may be configured to use the internal oscillator, external oscillator, or the Clock Multiplier output divided by 2. If desired,
the system clock source may be switched on-the-fly between oscillator sources. An external oscillator can
be extremely useful in low power applications, allowing the MCU to run from a slow (power saving) external clock source, while periodically switching to the internal oscillator as needed.

Rev. 1.4

C8051F320/1
VDD

Supply
Monitor
+
-

Enable

Power On
Reset

Comparator 0

Px.x
Px.x

(wired-OR)

Reset
Funnel

PCA
WDT

Software Reset (SWRSF)

Errant
FLASH
Operation

MCD
Enable

Clock
Multiplier

System
Clock

External
Oscillator
Drive

WDT
Enable

Internal
Oscillator

CIP-51
Microcontroller
Core

Enable

XTAL2

/RST

C0RSEF

Missing
Clock
Detector
(oneshot)

XTAL1

'0'

+
-

USB
Controller

VBUS
Transition

System Reset

Clock Select
Extended Interrupt
Handler

Figure 1.3. On-Chip Clock and Reset
1.2.

On-Chip Memory

The CIP-51 has a standard 8051 program and data address configuration. It includes 256 bytes of data
RAM, with the upper 128 bytes dual-mapped. Indirect addressing accesses the upper 128 bytes of general
purpose RAM, and direct addressing accesses the 128 byte SFR address space. The lower 128 bytes of
RAM are accessible via direct and indirect addressing. The first 32 bytes are addressable as four banks of
general purpose registers, and the next 16 bytes can be byte addressable or bit addressable.
Program memory consists of 16 kB of Flash. This memory may be reprogrammed in-system in 512 byte
sectors, and requires no special off-chip programming voltage. See Figure 1.4 for the MCU system memory map.

Rev. 1.4

C8051F320/1
DATA MEMORY (RAM)
INTERNAL DATA ADDRESS SPACE

PROGRAM/DATA MEMORY
(Flash)
0xFF
0x3E00

RESERVED

0x3DFF

0x80
0x7F

Upper 128 RAM
(Indirect Addressing
Only)
(Direct and Indirect
Addressing)

16 K Flash

0x30
0x2F

(In-System
Programmable in 512
Byte Sectors)

0x20
0x1F
0x00

Bit Addressable

Special Function
Register's
(Direct Addressing Only)

Lower 128 RAM
(Direct and Indirect
Addressing)

General Purpose
Registers

EXTERNAL DATA ADDRESS SPACE
0x0000
0xFFFF
Same 2048 bytes as from
0x0000 to 0x07FF, wrapped
on 2 kB boundaries

0x0800
0x07FF
0x0400
0x03FF
0x0000

USB FIFOs
1024 Bytes
XRAM - 1024 Bytes
(accessable using MOVX
instruction)

Figure 1.4. On-Board Memory Map
1.3.

Universal Serial Bus Controller

The Universal Serial Bus Controller (USB0) is a USB 2.0 compliant Full or Low Speed function with integrated transceiver and endpoint FIFO RAM. A total of eight endpoint pipes are available: a bi-directional
control endpoint (Endpoint0) and three pairs of IN/OUT endpoints (Endpoints1-3 IN/OUT).
A 1k block of XRAM is used as dedicated USB FIFO space. This FIFO space is distributed among Endpoints0–3; Endpoint1–3 FIFO slots can be configured as IN, OUT, or both IN and OUT (split mode). The
maximum FIFO size is 512 bytes (Endpoint3).
USB0 can be operated as a Full or Low Speed function. On-chip 4x Clock Multiplier and clock recovery circuitry allow both Full and Low Speed options to be implemented with the on-chip precision oscillator as the
USB clock source. An external oscillator source can also be used with the 4x Clock Multiplier to generate
the USB clock. The CPU clock source is independent of the USB clock.

Rev. 1.4

C8051F320/1
The USB Transceiver is USB 2.0 compliant, and includes on-chip matching and pull-up resistors. The pullup resistors can be enabled/disabled in software, and will appear on the D+ or D– pin according to the software-selected speed setting (Full or Low Speed).

Transceiver

Serial Interface Engine (SIE)
Endpoint0

VDD
IN/OUT

D+
Data
Transfer
Control
D-

Endpoint1
Endpoint2
Endpoint3
OUT

IN
IN

USB
Control,
Status, and
Interrupt
Registers

CIP-51 Core

OUT
IN

OUT

USB FIFOs
(1k RAM)

Figure 1.5. USB Controller Block Diagram
1.4.

Voltage Regulator

1.5.

On-Chip Debug Circuitry

The C8051F320/1 devices include on-chip Silicon Labs 2-Wire (C2) debug circuitry that provides non-intrusive, full speed, in-circuit debugging of the production part installed in the end application.
Silicon Labs' debugging system supports inspection and modification of memory and registers, breakpoints, and single stepping. No additional target RAM, program memory, timers, or communications channels are required. All the digital and analog peripherals are functional and work correctly while debugging.
All the peripherals (except for the USB, ADC, and SMBus) are stalled when the MCU is halted, during single stepping, or at a breakpoint in order to keep them synchronized.
The C8051F320DK development kit provides all the hardware and software necessary to develop application code and perform in-circuit debugging with the C8051F320/1 MCUs. The kit includes software with a
developer's studio and debugger, 8051 assembler and linker, evaluation ‘C’ compiler, and a debug
adapter. It also has a target application board with the C8051F320 MCU installed, the necessary cables for
connection to a PC, and a wall-mount power supply. The development kit contents may also be used to
program and debug the device on the production PCB using the appropriate connections for the programming pins.
The Silicon Labs IDE interface is a vastly superior developing and debugging configuration, compared to
standard MCU emulators that use on-board "ICE Chips" and require the MCU in the application board to

Rev. 1.4

C8051F320/1
be socketed. Silicon Labs' debug paradigm increases ease of use and preserves the performance of the
precision analog peripherals.
AC/DC
Adapter

Target Board

USB Debug Adapter
PWR

SILICON LABORATORIES

RESET P3.7

Run

Stop

Silicon Laboratories
USB DEBUG ADAPTER

Power

USB
Cable

MCU
P1.6

Port 2

Port 0

Port 1

Port 3

Port 4

Figure 1.6. Development/In-System Debug Diagram
1.6.

Programmable Digital I/O and Crossbar

C8051F320 devices include 25 I/O pins (three byte-wide Ports and one 1-bit-wide Port); C8051F321
devices include 21 I/O pins (two byte-wide Ports, one 4-bit-wide Port, and one 1-bit-wide Port). The
C8051F320/1 Ports behave like typical 8051 Ports with a few enhancements. Each Port pin may be configured as an analog input or a digital I/O pin. Pins selected as digital I/Os may additionally be configured for
push-pull or open-drain output. The “weak pull-ups” that are fixed on typical 8051 devices may be globally
disabled, providing power savings capabilities.
The Digital Crossbar allows mapping of internal digital system resources to Port I/O pins (See Figure 1.7).
On-chip counter/timers, serial buses, HW interrupts, comparator outputs, and other digital signals in the
controller can be configured to appear on the Port I/O pins specified in the Crossbar Control registers. This
allows the user to select the exact mix of general purpose Port I/O and digital resources needed for the
particular application.

Rev. 1.4

C8051F320/1
XBR0, XBR1,
PnSKIP Registers

PnMDOUT,
PnMDIN Registers

Priority
Decoder
Highest
Priority

UART

(Internal Digital Signals)

P0
I/O
Cells

P0.0

P1
I/O
Cells

P1.0

P2
I/O
Cells

P2.0

P3.0

P3
I/O
Cells

Note: P2.4-P2.7 only available
on the C8051F320

SPI

CP0
Outputs

CP1
Outputs

Digital
Crossbar

SYSCLK

1
T0, T1

P1.7

P2.7

PCA
Lowest
Priority

P0.7

SMBus

(P0.0-P0.7)

(Port Latches)

8
P1

(P1.0-P1.7)

(P2.0-P2.7)

(P3.0)

Figure 1.7. Digital Crossbar Diagram
1.7.

Serial Ports

The C8051F320/1 Family includes an SMBus/I2C interface, a full-duplex UART with enhanced baud rate
configuration, and an Enhanced SPI interface. Each of the serial buses is fully implemented in hardware
and makes extensive use of the CIP-51's interrupts, thus requiring very little CPU intervention.

1.8.

Programmable Counter Array

An on-chip Programmable Counter/Timer Array (PCA) is included in addition to the four 16-bit general purpose counter/timers. The PCA consists of a dedicated 16-bit counter/timer time base with five programmable capture/compare modules. The PCA clock is derived from one of six sources: the system clock divided
by 12, the system clock divided by 4, Timer 0 overflows, an External Clock Input (ECI), the system clock, or
the external oscillator clock source divided by 8. The external clock source selection is useful for real-time
clock functionality, where the PCA is clocked by an external source while the internal oscillator drives the
system clock.
Each capture/compare module can be configured to operate in one of six modes: Edge-Triggered Capture,
Software Timer, High Speed Output, 8- or 16-bit Pulse Width Modulator, or Frequency Output. Additionally,
Capture/Compare Module 4 offers watchdog timer (WDT) capabilities. Following a system reset, Module 4
is configured and enabled in WDT mode. The PCA Capture/Compare Module I/O and External Clock Input
may be routed to Port I/O via the Digital Crossbar.
Rev. 1.4

C8051F320/1

SYSCLK/12
SYSCLK/4
Timer 0 Overflow
ECI

PCA
CLOCK
MUX

16-Bit Counter/Timer

SYSCLK
External Clock/8

Capture/Compare
Module 0

Capture/Compare
Module 1

Capture/Compare
Module 2

Capture/Compare
Module 3

Capture/Compare
Module 4 / WDT

CEX4

CEX3

CEX2

CEX1

CEX0

ECI

Crossbar

Port I/O

Figure 1.9. PCA Block Diagram
1.9.

10-Bit Analog to Digital Converter

The C8051F320/1 devices include an on-chip 10-bit SAR ADC with a 17-channel differential input multiplexer. With a maximum throughput of 200 ksps, the ADC offers true 10-bit linearity with an INL of ±1LSB.
The ADC system includes a configurable analog multiplexer that selects both positive and negative ADC
inputs. Ports1-3 are available as ADC inputs; additionally, the on-chip Temperature Sensor output and the
power supply voltage (VDD) are available as ADC inputs. User firmware may shut down the ADC to save
power.
Conversions can be started in six ways: a software command, an overflow of Timer 0, 1, 2, or 3, or an
external convert start signal. This flexibility allows the start of conversion to be triggered by software
events, a periodic signal (timer overflows), or external HW signals. Conversion completions are indicated
by a status bit and an interrupt (if enabled). The resulting 10-bit data word is latched into the ADC data
SFRs upon completion of a conversion.
Window compare registers for the ADC data can be configured to interrupt the controller when ADC data is
either within or outside of a specified range. The ADC can monitor a key voltage continuously in background mode, but not interrupt the controller unless the converted data is within/outside the specified
range.

Rev. 1.4

C8051F320/1
Analog Multiplexer

P1.0
Configuration, Control, and Data Registers

P1.7
P2.0
P2.4-2.7
available on
C8051F320

Temp
Sensor

19-to-1
AMUX

Start
Conversion

P2.7
P3.0

AD0BUSY (W)

001

Timer 0 Overflow

010

Timer 2 Overflow

011
100

Timer 1 Overflow
CNVSTR Input

101

Timer 3 Overflow

VDD
(+)

(-)

P1.0

P1.7
P2.0
P2.4-2.7
available on
C8051F320

000

19-to-1
AMUX

10-Bit
SAR

ADC
End of
Conversion
Interrupt

ADC Data
Registers

Window Compare
Logic

Window
Compare
Interrupt

P2.7
P3.0
VREF
GND

Figure 1.10. 10-Bit ADC Block Diagram
1.10. Comparators
C8051F320/1 devices include two on-chip voltage comparators that are enabled/disabled and configured
via user software. Port I/O pins may be configured as comparator inputs via a selection mux. Two comparator outputs may be routed to a Port pin if desired: a latched output and/or an unlatched (asynchronous)
output. Comparator response time is programmable, allowing the user to select between high-speed and
low-power modes. Positive and negative hysteresis are also configurable.
Comparator interrupts may be generated on rising, falling, or both edges. When in IDLE mode, these interrupts may be used as a “wake-up” source. Comparator0 may also be configured as a reset source.
Figure 1.11 shows the Comparator0 block diagram.

Rev. 1.4

C8051F320/1
CP0EN

CPT0CN

CPT0MX

CP0OUT

CMX0N1
CMX0N0

CP0RIF

VDD

CP0FIF
CP0HYP1
CP0HYP0

CP0
Interrupt

CP0HYN1
CP0HYN0

CMX0P1
CMX0P0

CP0
Rising-edge

P1.0

CP0
Falling-edge

P1.4
CP0 +

P2.0

Interrupt
Logic

P2.4

CP0RIE
CP0FIE

+
D

SET

CLR

SET

CLR

Crossbar

P1.1

(SYNCHRONIZER)

P1.5

GND

CP0 -

P2.1

CP0A
Reset
Decision
Tree

Note: P2.4 and P2.5 available
only on C8051F320

CPT0MD

P2.5

CP0RIE
CP0FIE

CP0MD1
CP0MD0

Figure 1.11. Comparator0 Block Diagram

CP0

Rev. 1.4

C8051F320/1
2.

Absolute Maximum Ratings

Table 2.1. Absolute Maximum Ratings
Parameter

Conditions

Min

Typ

Max

Units

–55

—

125

°C

Storage Temperature

–65

—

150

°C

Voltage on any Port I/O Pin or /RST with
respect to GND

–0.3

—

5.8

Voltage on VDD with respect to GND

–0.3

—

4.2

Maximum Total current through VDD and
GND

—

500

Maximum output current sunk by /RST or any
Port pin

—

100

Ambient temperature under bias

Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the devices at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.

Rev. 1.4

C8051F320/1
3.

Global Electrical Characteristics

Table 3.1. Global Electrical Characteristics
–40 to +85 °C, 25 MHz system clock unless otherwise noted.

Parameter

Conditions

Min

Typ

Max

Units

VRST1,2

3.0

3.6

Digital Supply RAM Data
Retention Voltage

1.5

—

SYSCLK (System Clock)3

—

MHz

TSYSH (SYSCLK High Time)

—

TSYSL (SYSCLK Low Time)

—

Specificed Operating Temperature Range

–40

—

+85

°C

Digital Supply Voltage

Digital Supply Current - CPU Active (Normal Mode, fetching instructions from Flash)
IDD4

IDD Supply Sensitivity4
IDD Frequency

Sensitivity4,5

VDD = 3.6 V; F = 25 MHz

—

12.3

13.6

VDD = 3.3 V, F = 24 MHz

—

10.6

11.5

VDD = 3.3 V, F = 6 MHz

—

3.2

—

VDD = 3.3 V, F = 32 kHz

—

VDD = 3.0 V, F = 24 MHz

—

9.0

9.8

VDD = 3.0 V, F = 6 MHz

—

2.7

—

VDD = 3.0 V, F = 32 kHz

—

F = 24 MHz

—

0.66

—

%/V

F = 6 MHz

—

0.63

—

%/V

VDD = 3.0 V, F < 15 MHz, T = 25 °C

—

0.45

—

mA/MHz

VDD = 3.0 V, F > 15 MHz, T = 25 °C

—

0.26

—

mA/MHz

VDD = 3.3 V, F < 15 MHz, T = 25 °C

—

0.53

—

mA/MHz

VDD = 3.3 V, F > 15 MHz, T = 25 °C

—

0.29

—

mA/MHz

Digital Supply Current - CPU and USB Active (USB Transceiver Enabled and Connected to PC)
IDD4

VDD = 3.3 V, F = 24 MHz, Full Speed

—

16.8

—

VDD = 3.0 V, F = 24 MHz, Full Speed

—

14.4

—

VDD = 3.3 V, F = 6 MHz, Low Speed

—

7.2

—

VDD = 3.0 V, F = 6 MHz, Low Speed

—

6.0

—

Digital Supply Current - CPU Inactive (Idle Mode, not fetching instructions from Flash)
Idle IDD4

VDD = 3.6 V; F = 25 Mhz

—

5.8

6.5

VDD = 3.3 V, F = 24 MHz

—

5.2

5.9

VDD = 3.3 V, F = 6 MHz

—

1.7

—

VDD = 3.3 V, F = 32 kHz

—

VDD = 3.0 V, F = 24 MHz

—

4.6

5.2

VDD = 3.0 V, F = 6 MHz

—

1.5

—

VDD = 3.0 V, F = 32 kHz

—

Rev. 1.4

C8051F320/1
Table 3.1. Global Electrical Characteristics (Continued)
–40 to +85 °C, 25 MHz system clock unless otherwise noted.

Parameter

Conditions

Min

Typ

Max

Units

F = 24 MHz

—

0.47

—

%/V

F = 6 MHz

—

0.50

—

%/V

VDD = 3.0 V, F < 1 MHz, T = 25 °C

—

0.25

—

mA/MHz

Idle IDD Supply Sensitivity4
Idle IDD Frequency
Sensitivity 4,6

VDD = 3.0 V, F > 1 MHz, T = 25 °C

—

0.17

—

mA/MHz

VDD = 3.3 V, F < 1 MHz, T = 25 °C

—

0.29

—

mA/MHz

VDD = 3.3 V, F > 1 MHz, T = 25 °C

—

0.20

—

mA/MHz

Oscillator not running,
VDD Monitor disabled

—

<0.1

—

µA

Digital Supply Current
(Stop Mode)

Notes:
1. Given in Table 10.1, “Reset Electrical Characteristics,” on page 105.
2. USB requires a minimum supply voltage of 3.0 V.
3. SYSCLK must be at least 32 kHz to enable debugging.
4. Based on device characterization data; Not production tested.
5. IDD can be estimated for frequencies < 15 MHz by simply multiplying the frequency of interest by the
frequency sensitivity number for that range. When using these numbers to estimate IDD for >15 MHz, the
estimate should be the current at 24 MHz minus the difference in current indicated by the frequency sensitivity
number. For example: VDD = 3.0 V; F = 20 MHz, IDD = 9.0 mA – (24 MHz –
20 MHz) x 0.26 mA/MHz = 7.96 mA.
6. Idle IDD can be estimated for frequencies < 1 MHz by simply multiplying the frequency of interest by the
frequency sensitivity number for that range. When using these numbers to estimate Idle IDD for >1 MHz, the
estimate should be the current at 24 MHz minus the difference in current indicated by the frequency sensitivity
number. For example: VDD = 3.0 V; F = 5 MHz, Idle IDD = 4.6 mA – (24 MHz –
5 MHz) x 0.17 mA/MHz = 1.37 mA.

Table 3.2. Index to Electrical Characteristics Tables
Peripheral Electrical Characteristics

Page #

ADC0 Electrical Characteristics

Voltage Reference Electrical Characteristics

Comparator Electrical Characteristics

Voltage Regulator Electrical Characteristics

Reset Electrical Characteristics

105

Flash Electrical Characteristics

107

Internal Oscillator Electrical Characteristics

125

Port I/O DC Electrical Characteristics

138

Rev. 1.4

C8051F320/1
4.

Pinout and Package Definitions
Table 4.1. Pin Definitions for the C8051F320/1
Name

Pin Numbers
‘F320 ‘F321

Type

Description

Power In 2.7-3.6 V Power Supply Voltage Input.
VDD

GND
/RST/

VBUS

D+
DP0.0
P0.1
P0.2/

4
5
2
1

XTAL1
P0.3/
31

30
29

26
25

CNVSTR
P0.7/

D I/O Bi-directional data signal for the C2 Debug Interface.
Power In 5 V Regulator Input. This pin is the input to the on-chip voltage regulator.
VBUS Sense Input. This pin should be connected to the
D In
VBUS signal of a USB network. A 5 V signal on this pin indicates a USB network connection.
D I/O USB D+.
D I/O USB D–.
D I/O Port 0.0. See Section 14 for a complete description of Port 0.
D I/O Port 0.1.
D I/O Port 0.2.

27
26

External Clock Input. This pin is the external oscillator return
for a crystal or resonator. See Section 13.
Port 0.3.

External Clock Output. This pin is the excitation driver for an
A I/O or external crystal or resonator, or an external clock input for
D In
CMOS, capacitor, or RC oscillator configurations. See Section 13.
D I/O Port 0.4.
D I/O Port 0.5.
Port 0.6.

D I/O

ADC0 External Convert Start Input. See Section 5.
Port 0.7.

VREF

Clock signal for the C2 Debug Interface.
Port 3.0. See Section 14 for a complete description.

A In
D I/O

XTAL2

P1.0

D I/O
D I/O
10

P0.4
P0.5
P0.6/

D I/O

3.3 V Voltage Regulator Output. See Section 8.
Ground.
Device Reset. Open-drain output of internal POR or VDD
monitor. An external source can initiate a system reset by
driving this pin low for at least 15 µs. See Section 10.

C2CK
P3.0/
C2D
REGIN

Power
Out

A I/O External VREF input or output. See Section 6.
D I/O or
Port 1.0. See Section 14 for a complete description of Port 1.
A In

Rev. 1.4

C8051F320/1
Table 4.1. Pin Definitions for the C8051F320/1 (Continued)
Name

Pin Numbers
‘F320 ‘F321

P1.1

P1.2

P1.3

P1.4

P1.5

P1.6

P1.7

P2.0

P2.1

P2.2

P2.3

P2.4

P2.5

P2.6

P2.7

Type
D I/O or
A In
D I/O or
A In
D I/O or
A In
D I/O or
A In
D I/O or
A In
D I/O or
A In
D I/O or
A In
D I/O or
A In
D I/O or
A In
D I/O or
A In
D I/O or
A In
D I/O or
A In
D I/O or
A In
D I/O or
A In
D I/O or
A In

Description
Port 1.1.
Port 1.2.
Port 1.3.
Port 1.4.
Port 1.5.
Port 1.6.
Port 1.7.
Port 2.0. See Section 14 for a complete description of Port 2.
Port 2.1.
Port 2.2.
Port 2.3.
Port 2.4.
Port 2.5.
Port 2.6.
Port 2.7.

Rev. 1.4

P0.2

P0.3

P0.4

P0.5

P0.6

P0.7

P1.0

P1.1

C8051F320/1

P0.1

P1.2

P0.0

P1.3

GND

P1.4

D+

P1.5

D-

P1.6

VDD

P1.7

REGIN

P2.0

VBUS

P2.1

/RST / C2CK

P3.0 / C2D

P2.7

P2.6

P2.5

P2.4

P2.3

P2.2

C8051F320
Top View

Figure 4.1. LQFP-32 Pinout Diagram (Top View)

Rev. 1.4

C8051F320/1

Figure 4.2. LQFP-32 Package Drawing
Table 4.2. LQFP-32 Package Dimensions
Dimension

Min

Nom

Max

A
A1
A2
b
c
D
D1
e
E
E1
L

—
0.05
1.35
0.30
0.09

—
—
1.40
0.37
—
9.00 BSC.
7.00 BSC.
0.80 BSC.
9.00 BSC.
7.00 BSC.
0.60

1.60
0.15
1.45
0.45
0.20

0.45

Rev. 1.4

0.75

C8051F320/1
Table 4.2. LQFP-32 Package Dimensions (Continued)
Dimension
aaa
bbb
ccc
ddd
Q

Min

Nom

Max

0°

0.20
0.20
0.10
0.20
3.5°

7°

Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise
noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to JEDEC outline MS-026, variation BBA.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD020 specification for Small Body Components.

Rev. 1.4

C8051F320/1

Figure 4.3. LQFP-32 Recommended PCB Land Pattern
Table 4.3. LQFP-32 PCB Land Pattern Dimensions
Dimension

Min

Max

Dimension

Min

Max

C1
C2
E

8.40
8.40

8.50
8.50

X1
Y1

0.40
1.25

0.50
1.35

0.80

Notes:
General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. This Land Pattern Design is based on the IPC-7351 guidelines.
Solder Mask Design
3. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder
mask and the metal pad is to be 60μm minimum, all the way around the pad.
Stencil Design
4. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used
to assure good solder paste release.
5. The stencil thickness should be 0.125mm (5 mils).
6. The ratio of stencil aperture to land pad size should be 1:1 for all pads.
Card Assembly
7. A No-Clean, Type-3 solder paste is recommended.
8. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small
Body Components.

Rev. 1.4

P0.2

P0.3

P0.4

P0.5

P0.6

P0.7

P1.0

C8051F320/1

P0.1

P1.1

P0.0

P1.2

GND

P1.3

D+

P1.4

D-

P1.5

VDD

P1.6

P1.7

C8051F321
Top View

GND

P2.2

P2.1

P2.0

10
P3.0 / C2D

9
/RST / C2CK

P2.3

VBUS

REGIN

Figure 4.4. QFN-28 Pinout Diagram (Top View)

Rev. 1.4

C8051F320/1

Figure 4.5. QFN-28 Package Drawing
Table 4.4. QFN-28 Package Dimensions
Dimension

Min

Typ

Max

Dimension

Min

Typ

Max

A
A1
A3
b
D
D2
e
E
E2

0.80
0.00

0.90
0.02
0.25 REF
0.23
5.00 BSC.
3.15
0.50 BSC.
5.00 BSC.
3.15

1.00
0.05

L
L1
aaa
bbb
ddd
eee
Z
Y

0.35
0.00

0.55
—
0.15
0.10
0.05
0.08
0.44
0.18

0.65
0.15

0.18
2.90

2.90

0.30
3.35

3.35

Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MO-220, variation VHHD except for
custom features D2, E2, Z, Y, and L which are toleranced per supplier designation.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body
Components.

Rev. 1.4

C8051F320/1

Figure 4.6. QFN-28 Recommended PCB Land Pattern
Table 4.5. QFN-28 PCB Land Pattern Dimesions
Dimension
C1
C2
E
X1

Min

Max

Dimension

Min

Max

X2
Y1
Y2

3.20
0.85
3.20

3.30
0.95
3.30

4.80
4.80
0.50
0.20

0.30

Notes:
General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.
3. This Land Pattern Design is based on the IPC-7351 guidelines.
Solder Mask Design
4. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder
mask and the metal pad is to be 60μm minimum, all the way around the pad.
Stencil Design
5. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used
to assure good solder paste release.
6. The stencil thickness should be 0.125mm (5 mils).
7. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pins.
8. A 3x3 array of 0.90mm openings on a 1.1mm pitch should be used for the center pad to
assure the proper paste volume (67% Paste Coverage).
Card Assembly
9. A No-Clean, Type-3 solder paste is recommended.
10. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small
Body Components.

Rev. 1.4

C8051F320/1
5.

10-Bit ADC (ADC0)

The ADC0 subsystem for the C8051F320/1 consists of two analog multiplexers (referred to collectively as
AMUX0) with 17 total input selections, and a 200 ksps, 10-bit successive-approximation-register ADC with
integrated track-and-hold and programmable window detector. The AMUX0, data conversion modes, and
window detector are all configurable under software control via the Special Function Registers shown in
Figure 5.1. ADC0 operates in both Single-ended and Differential modes, and may be configured to measure P1.0-P3.0, the Temperature Sensor output, or VDD with respect to P1.0-P3.0, VREF, or GND. The
ADC0 subsystem is enabled only when the AD0EN bit in the ADC0 Control register (ADC0CN) is set to
logic 1. The ADC0 subsystem is in low power shutdown when this bit is logic 0.

P2.4-2.7
available on
C8051F320

19-to-1
AMUX

Start
Conversion

P2.7
P3.0

10-Bit
SAR

(+)

GND

AD0SC0

AD0LJST

AD0SC1

AD0SC2

AD0SC3

AMX0N0

AMX0N1

AMX0N2

AMX0N3

AMX0N4

VREF

AMX0N

AD0SC4

19-to-1
AMUX

ADC0CF

AD0BUSY (W)
Timer 0 Overflow
Timer 2 Overflow
Timer 1 Overflow

100
101

CNVSTR Input
Timer 3 Overflow

REF

SYSCLK

P1.7
P2.0

000
001
010
011

ADC0H

ADC

(-)

P1.0

ADC0L

VDD

P2.7
P3.0

AD0CM0

VDD

Temp
Sensor

P2.4-2.7
available on
C8051F320

AD0CM1

AD0CM2

AD0WINT

AD0INT

P1.7
P2.0

AD0BUSY

AD0EN

AD0TM

AMX0P0

ADC0CN
AMX0P1

AMX0P2

AMX0P4

AMX0P3

AMX0P

P1.0

AD0WINT

ADC0LTH ADC0LTL

Window
Compare
Logic

ADC0GTH ADC0GTL

Figure 5.1. ADC0 Functional Block Diagram

Rev. 1.4

C8051F320/1
5.1.

Analog Multiplexer

AMUX0 selects the positive and negative inputs to the ADC. Any of the following may be selected as the
positive input: P1.0-P3.0, the on-chip temperature sensor, or the positive power supply (VDD). Any of the
following may be selected as the negative input: P1.0-P3.0, VREF, or GND. When GND is selected as
the negative input, ADC0 operates in Single-ended Mode; all other times, ADC0 operates in Differential Mode. The ADC0 input channels are selected in the AMX0P and AMX0N registers as described in
Figure 5.2 and Figure 5.2.
The conversion code format differs between Single-ended and Differential modes. The registers ADC0H
and ADC0L contain the high and low bytes of the output conversion code from the ADC at the completion
of each conversion. Data can be right-justified or left-justified, depending on the setting of the AD0LJST bit
(ADC0CN.0). When in Single-ended Mode, conversion codes are represented as 10-bit unsigned integers.
Inputs are measured from ‘0’ to VREF x 1023/1024. Example codes are shown below for both right-justified and left-justified data. Unused bits in the ADC0H and ADC0L registers are set to ‘0’.
Right-Justified ADC0H:ADC0L
Input Voltage
(AD0LJST = 0)
(Single-Ended)
VREF x 1023/1024
0x03FF
VREF x 512/1024
0x0200
VREF x 256/1024
0x0100
0
0x0000

Left-Justified ADC0H:ADC0L
(AD0LJST = 1)
0xFFC0
0x8000
0x4000
0x0000

When in Differential Mode, conversion codes are represented as 10-bit signed 2’s complement numbers.
Inputs are measured from –VREF to VREF x 511/512. Example codes are shown below for both right-justified and left-justified data. For right-justified data, the unused MSBs of ADC0H are a sign-extension of the
data word. For left-justified data, the unused LSBs in the ADC0L register are set to ‘0’.
Input Voltage
Right-Justified ADC0H:ADC0L
(Differential)
(AD0LJST = 0)
VREF x 511/512
0x01FF
VREF x 256/512
0x0100
0
0x0000
–VREF x 256/512
0xFF00
–VREF
0xFE00

Left-Justified ADC0H:ADC0L
(AD0LJST = 1)
0x7FC0
0x4000
0x0000
0xC000
0x8000

Important Note About ADC0 Input Configuration: Port pins selected as ADC0 inputs should be configured as analog inputs, and should be skipped by the Digital Crossbar. To configure a Port pin for analog
input, set to ‘0’ the corresponding bit in register PnMDIN (for n = 0,1,2,3). To force the Crossbar to skip a
Port pin, set to ‘1’ the corresponding bit in register PnSKIP (for n = 0,1,2). See Section “14. Port Input/Output” on page 126 for more Port I/O configuration details.

Rev. 1.4

C8051F320/1
5.2.

Temperature Sensor

The temperature sensor transfer function is shown in Figure 5.2. The output voltage (VTEMP) is the positive
ADC input when the temperature sensor is selected by bits AMX0P4-0 in register AMX0P. Values for the
Offset and Slope parameters can be found in Table 5.1.

VTEMP = (Gain x TempC) + Offset

Voltage

TempC = (VTEMP - Offset) / Gain
Gain (V / deg C)
Offset (V at 0 Celsius)

Temperature

Figure 5.2. Temperature Sensor Transfer Function
The uncalibrated temperature sensor output is extremely linear and suitable for relative temperature measurements (see Table 5.1 for linearity specifications). For absolute temperature measurements, offset and/
or gain calibration is recommended. Typically a 1-point (offset) calibration includes the following steps:
Step 1. Control/measure the ambient temperature (this temperature must be known).
Step 2. Power the device, and delay for a few seconds to allow for self-heating.
Step 3. Perform an ADC conversion with the temperature sensor selected as the positive input
and GND selected as the negative input.
Step 4. Calculate the offset characteristics, and store this value in non-volatile memory for use
with subsequent temperature sensor measurements.
Figure 5.3 shows the typical temperature sensor error assuming a 1-point calibration at 25 °C. Note that
parameters which affect ADC measurement, in particular the voltage reference value, will also
affect temperature measurement.

Rev. 1.4

Error (degrees C)

C8051F320/1

5.0
0

4.0
0

3.0
0

2.0
0

1.0
0

0.0
0-40.00

-20.00

0.0
0

20.0
0

40.0
0

60.0
0

0.0
0

-1.00

-2.00

-3.00

-4.00

-5.00

Temperature (degrees C)

Figure 5.3. Temperature Sensor Error with 1-Point Calibration (VREF = 2.40 V)

80.0
0

Rev. 1.4

C8051F320/1
5.3.

Modes of Operation

ADC0 has a maximum conversion speed of 200 ksps. The ADC0 conversion clock is a divided version of
the system clock, determined by the AD0SC bits in the ADC0CF register (system clock divided by
(AD0SC + 1) for 0 ≤ AD0SC ≤ 31).

5.3.1. Starting a Conversion
A conversion can be initiated in one of five ways, depending on the programmed states of the ADC0 Start
of Conversion Mode bits (AD0CM2–0) in register ADC0CN. Conversions may be initiated by one of the following:
1.
2.
3.
4.
5.
6.

Writing a ‘1’ to the AD0BUSY bit of register ADC0CN
A Timer 0 overflow (i.e., timed continuous conversions)
A Timer 2 overflow
A Timer 1 overflow
A rising edge on the CNVSTR input signal (pin P0.6)
A Timer 3 overflow

Writing a ‘1’ to AD0BUSY provides software control of ADC0 whereby conversions are performed "ondemand". During conversion, the AD0BUSY bit is set to logic 1 and reset to logic 0 when the conversion is
complete. The falling edge of AD0BUSY triggers an interrupt (when enabled) and sets the ADC0 interrupt
flag (AD0INT). Note: When polling for ADC conversion completions, the ADC0 interrupt flag (AD0INT)
should be used. Converted data is available in the ADC0 data registers, ADC0H:ADC0L, when bit AD0INT
is logic 1. Note that when Timer 2 or Timer 3 overflows are used as the conversion source, Low Byte overflows are used if Timer 2/3 is in 8-bit mode; High byte overflows are used if Timer 2/3 is in 16-bit mode. See
Section “19. Timers” on page 209 for timer configuration.
Important Note About Using CNVSTR: The CNVSTR input pin also functions as Port pin P0.6. When the
CNVSTR input is used as the ADC0 conversion source, Port pin P0.6 should be skipped by the Digital
Crossbar. To configure the Crossbar to skip P0.6, set to ‘1’ Bit6 in register P0SKIP. See Section “14. Port
Input/Output” on page 126 for details on Port I/O configuration.

Rev. 1.4

C8051F320/1
5.3.2. Tracking Modes
The AD0TM bit in register ADC0CN controls the ADC0 track-and-hold mode. In its default state, the ADC0
input is continuously tracked, except when a conversion is in progress. When the AD0TM bit is logic 1,
ADC0 operates in low-power track-and-hold mode. In this mode, each conversion is preceded by a tracking period of 3 SAR clocks (after the start-of-conversion signal). When the CNVSTR signal is used to initiate conversions in low-power tracking mode, ADC0 tracks only when CNVSTR is low; conversion begins
on the rising edge of CNVSTR (see Figure 5.4). Tracking can also be disabled (shutdown) when the device
is in low power standby or sleep modes. Low-power track-and-hold mode is also useful when AMUX settings are frequently changed, due to the settling time requirements described in Section “5.3.3. Settling
Time Requirements” on page 45.

A. ADC0 Timing for External Trigger Source
CNVSTR
(AD0CM[2:0] = 100)
1

10 11 12 13 14

SAR Clocks

AD0TM = 1

AD0TM = 0

Write '1' to AD0BUSY,
Timer 0, Timer 2,
Timer 1, Timer 3 Overflow
(AD0CM[2:0] = 000, 001,010
011, 101)

Low Power
or Convert

Track

Track or Convert

Convert

Low Power
Mode

Convert

Track

B. ADC0 Timing for Internal Trigger Source

10 11 12 13 14 15 16 17

SAR
Clocks
AD0TM = 1

Low Power
or Convert

Track
1

Convert
4

Low Power Mode

10 11 12 13 14

SAR
Clocks
AD0TM = 0

Track or
Convert

Convert

Track

Figure 5.4. 10-Bit ADC Track and Conversion Example Timing

Rev. 1.4

C8051F320/1
5.3.3. Settling Time Requirements
When the ADC0 input configuration is changed (i.e., a different AMUX0 selection is made), a minimum
tracking time is required before an accurate conversion can be performed. This tracking time is determined
by the AMUX0 resistance, the ADC0 sampling capacitance, any external source resistance, and the accuracy required for the conversion. Note that in low-power tracking mode, three SAR clocks are used for
tracking at the start of every conversion. For most applications, these three SAR clocks will meet the minimum tracking time requirements.
Figure 5.5 shows the equivalent ADC0 input circuits for both Differential and Single-ended modes. Notice
that the equivalent time constant for both input circuits is the same. The required ADC0 settling time for a
given settling accuracy (SA) may be approximated by Equation 5.1. When measuring the Temperature
Sensor output or VDD with respect to GND, RTOTAL reduces to RMUX. See Table 5.1 for ADC0 minimum
settling time requirements.

Equation 5.1. ADC0 Settling Time Requirements
n

2
t = ln  ------- × R TOTAL C SAMPLE
SA
Where:
SA is the settling accuracy, given as a fraction of an LSB (for example, 0.25 to settle within 1/4 LSB)
t is the required settling time in seconds
RTOTAL is the sum of the AMUX0 resistance and any external source resistance.
n is the ADC resolution in bits (10).

Differential Mode

Single-Ended Mode

MUX
Select

MUX Select

Px.x

Px.x
RMUX = 5k

RMUX = 5k
CSAMPLE = 5pF

CSAMPLE = 5pF

RCInput= RMUX * CSAMPLE

RCInput= RMUX * CSAMPLE
CSAMPLE = 5pF

Px.x
RMUX = 5k
MUX Select

Figure 5.5. ADC0 Equivalent Input Circuits

Rev. 1.4

C8051F320/1
SFR Definition 5.1. AMX0P: AMUX0 Positive Channel Select
R

R/W

AMX0P4

AMX0P3

AMX0P2

AMX0P1

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

R/W

Reset Value

AMX0P0 00000000
Bit0

SFR Address:

0xBB
Bits7–5: UNUSED. Read = 000b; Write = don’t care.
Bits4–0: AMX0P4–0: AMUX0 Positive Input Selection
AMX0P4–0
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100*
01101*
01110*
01111*
10000
10001–11101
11110
11111
*Note:

ADC0 Positive Input
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P2.0
P2.1
P2.2
P2.3
P2.4*
P2.5*
P2.6*
P2.7*
P3.0
RESERVED
Temp Sensor
VDD

Only applies to C8051F320; selection RESERVED on
C8051F321 devices.

Rev. 1.4

C8051F320/1
SFR Definition 5.2. AMX0N: AMUX0 Negative Channel Select
R

R/W

AMX0N4

AMX0N3

AMX0N2

AMX0N1

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

R/W

Reset Value

AMX0N0 00000000
Bit0

SFR Address:

0xBA
Bits7–5: UNUSED. Read = 000b; Write = don’t care.
Bits4–0: AMX0N4–0: AMUX0 Negative Input Selection.
Note that when GND is selected as the Negative Input, ADC0 operates in Single-ended
mode. For all other Negative Input selections, ADC0 operates in Differential mode.
AMX0N4–0
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100*
01101*
01110*
01111*
10000
10001–11101
11110
11111
*Note:

ADC0 Negative Input
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P2.0
P2.1
P2.2
P2.3
P2.4*
P2.5*
P2.6*
P2.7*
P3.0
RESERVED
VREF
GND (ADC in Single-Ended Mode)

Only applies to C8051F320; selection RESERVED on
C8051F321 devices.

Rev. 1.4

C8051F320/1
SFR Definition 5.3. ADC0CF: ADC0 Configuration
R/W

R/W

AD0SC4

AD0SC3

AD0SC2

AD0SC1

Bit7

Bit6

Bit5

Bit4

R/W

AD0SC0 AD0LJST
Bit3

Bit2

R/W

Reset Value

11111000

Bit1

Bit0

SFR Address:

0xBC
Bits7–3: AD0SC4–0: ADC0 SAR Conversion Clock Period Bits.
SAR Conversion clock is derived from system clock by the following equation, where
AD0SC refers to the 5-bit value held in bits AD0SC4-0. SAR Conversion clock requirements
are given in Table 5.1.

SYSCLK
AD0SC = ---------------------- – 1
CLK SAR
Bit2:

AD0LJST: ADC0 Left Justify Select.
0: Data in ADC0H:ADC0L registers are right-justified.
1: Data in ADC0H:ADC0L registers are left-justified.
Bits1–0: UNUSED. Read = 00b; Write = don’t care.

SFR Definition 5.4. ADC0H: ADC0 Data Word MSB
R/W

R/W

Reset Value

00000000
Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

0xBE
Bits7–0: ADC0 Data Word High-Order Bits.
For AD0LJST = 0: Bits 7-2 are the sign extension of Bit1. Bits 1–0 are the upper 2 bits of the
10-bit ADC0 Data Word.
For AD0LJST = 1: Bits 7–0 are the most-significant bits of the 10-bit ADC0 Data Word.

SFR Definition 5.5. ADC0L: ADC0 Data Word LSB
R/W

R/W

Reset Value

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

00000000
0xBD
Bits7–0: ADC0 Data Word Low-Order Bits.
For AD0LJST = 0: Bits 7–0 are the lower 8 bits of the 10-bit Data Word.
For AD0LJST = 1: Bits 7–6 are the lower 2 bits of the 10-bit Data Word. Bits 5–0 will always
read ‘0’.

Rev. 1.4

C8051F320/1
SFR Definition 5.6. ADC0CN: ADC0 Control
R/W

R/W

AD0EN

AD0TM

Bit7

Bit6

R/W

AD0INT AD0BUSY AD0WINT AD0CM2 AD0CM1
Bit5

Bit4

Bit3

Bit2

Bit1

Reset Value

AD0CM0 00000000
Bit0

(bit addressable)

SFR Address:

0xE8

Bit7:

AD0EN: ADC0 Enable Bit.
0: ADC0 Disabled. ADC0 is in low-power shutdown.
1: ADC0 Enabled. ADC0 is active and ready for data conversions.
Bit6:
AD0TM: ADC0 Track Mode Bit.
0: Normal Track Mode: When ADC0 is enabled, tracking is continuous unless a conversion
is in progress.
1: Low-power Track Mode: Tracking Defined by AD0CM2-0 bits (see below).
Bit5:
AD0INT: ADC0 Conversion Complete Interrupt Flag.
0: ADC0 has not completed a data conversion since the last time AD0INT was cleared.
1: ADC0 has completed a data conversion.
Bit4:
AD0BUSY: ADC0 Busy Bit.
Read:
0: ADC0 conversion is complete or a conversion is not currently in progress. AD0INT is set
to logic 1 on the falling edge of AD0BUSY.
1: ADC0 conversion is in progress.
Write:
0: No Effect.
1: Initiates ADC0 Conversion if AD0CM2–0 = 000b
Bit3:
AD0WINT: ADC0 Window Compare Interrupt Flag.
0: ADC0 Window Comparison Data match has not occurred since this flag was last cleared.
1: ADC0 Window Comparison Data match has occurred.
Bits2–0: AD0CM2–0: ADC0 Start of Conversion Mode Select.
When AD0TM = 0:
000: ADC0 conversion initiated on every write of ‘1’ to AD0BUSY.
001: ADC0 conversion initiated on overflow of Timer 0.
010: ADC0 conversion initiated on overflow of Timer 2.
011: ADC0 conversion initiated on overflow of Timer 1.
100: ADC0 conversion initiated on rising edge of external CNVSTR.
101: ADC0 conversion initiated on overflow of Timer 3.
11x: Reserved.
When AD0TM = 1:
000: Tracking initiated on write of ‘1’ to AD0BUSY and lasts 3 SAR clocks, followed by conversion.
001: Tracking initiated on overflow of Timer 0 and lasts 3 SAR clocks, followed by conversion.
010: Tracking initiated on overflow of Timer 2 and lasts 3 SAR clocks, followed by conversion.
011: Tracking initiated on overflow of Timer 1 and lasts 3 SAR clocks, followed by conversion.
100: ADC0 tracks only when CNVSTR input is logic low; conversion starts on rising CNVSTR
edge.
101: Tracking initiated on overflow of Timer 3 and lasts 3 SAR clocks, followed by conversion.
11x: Reserved.

Rev. 1.4

C8051F320/1
5.4.

Programmable Window Detector

The ADC Programmable Window Detector continuously compares the ADC0 conversion results to userprogrammed limits, and notifies the system when a desired condition is detected. This is especially effective in an interrupt-driven system, saving code space and CPU bandwidth while delivering faster system
response times. The window detector interrupt flag (AD0WINT in register ADC0CN) can also be used in
polled mode. The ADC0 Greater-Than (ADC0GTH, ADC0GTL) and Less-Than (ADC0LTH, ADC0LTL)
registers hold the comparison values. The window detector flag can be programmed to indicate when measured data is inside or outside of the user-programmed limits, depending on the contents of the ADC0
Less-Than and ADC0 Greater-Than registers.
The Window Detector registers must be written with the same format (left/right justified, signed/unsigned)
as that of the current ADC configuration (left/right justified, single-ended/differential).

SFR Definition 5.7. ADC0GTH: ADC0 Greater-Than Data High Byte
R/W

R/W

Reset Value

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

11111111
0xC4
Bits7–0: High byte of ADC0 Greater-Than Data Word.

SFR Definition 5.8. ADC0GTL: ADC0 Greater-Than Data Low Byte
R/W

R/W

Reset Value

11111111
Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

0xC3
Bits7–0: Low byte of ADC0 Greater-Than Data Word.

Rev. 1.4

C8051F320/1
SFR Definition 5.9. ADC0LTH: ADC0 Less-Than Data High Byte
R/W

R/W

Reset Value

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

00000000
0xC6
Bits7–0: High byte of ADC0 Less-Than Data Word.

SFR Definition 5.10. ADC0LTL: ADC0 Less-Than Data Low Byte
R/W

R/W

Reset Value

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

00000000
0xC5
Bits7–0: Low byte of ADC0 Less-Than Data Word.

Rev. 1.4

C8051F320/1
5.4.1. Window Detector In Single-Ended Mode
Figure 5.6 shows two example window comparisons for right-justified, single-ended data, with
ADC0LTH:ADC0LTL = 0x0080 (128d) and ADC0GTH:ADC0GTL = 0x0040 (64d). In single-ended mode,
the input voltage can range from ‘0’ to VREF * (1023/1024) with respect to GND, and is represented by a
10-bit unsigned integer value. In the left example, an AD0WINT interrupt will be generated if the ADC0
conversion word (ADC0H:ADC0L) is within the range defined by ADC0GTH:ADC0GTL and
ADC0LTH:ADC0LTL (if 0x0040 < ADC0H:ADC0L < 0x0080). In the right example, and AD0WINT interrupt
will be generated if the ADC0 conversion word is outside of the range defined by the ADC0GT and
ADC0LT registers (if ADC0H:ADC0L < 0x0040 or ADC0H:ADC0L > 0x0080). Figure 5.7 shows an example using left-justified data with equivalent ADC0GT and ADC0LT register settings.

ADC0H:ADC0L

Input Voltage
(Px.x - GND)
VREF x (1023/1024)

0x03FF

AD0WINT
not affected

AD0WINT=1

0x0081
VREF x (128/1024)

0x0080

0x0081
ADC0LTH:ADC0LTL

VREF x (128/1024)

0x007F

0x0080
0x007F

AD0WINT=1
VREF x (64/1024)

0x0041
0x0040

ADC0GTH:ADC0GTL

VREF x (64/1024)

0x003F

0x0041
0x0040

ADC0GTH:ADC0GTL
AD0WINT
not affected
ADC0LTH:ADC0LTL

0x003F

AD0WINT=1

AD0WINT
not affected
0

0x0000

Figure 5.6. ADC Window Compare Example: Right-Justified Single-Ended Data

ADC0H:ADC0L

Input Voltage
(Px.x - GND)
VREF x (1023/1024)

Input Voltage
(Px.x - GND)
0xFFC0

VREF x (1023/1024)

0xFFC0

AD0WINT
not affected

AD0WINT=1

0x2040
VREF x (128/1024)

0x2000

0x2040
ADC0LTH:ADC0LTL

VREF x (128/1024)

0x1FC0

0x2000
0x1FC0

AD0WINT=1
0x1040
VREF x (64/1024)

0x1000

0x1040
ADC0GTH:ADC0GTL

VREF x (64/1024)

0x0FC0

0x1000

AD0WINT
not affected
ADC0LTH:ADC0LTL

0x0FC0

AD0WINT=1

AD0WINT
not affected
0

ADC0GTH:ADC0GTL

0x0000

Figure 5.7. ADC Window Compare Example: Left-Justified Single-Ended Data

Rev. 1.4

C8051F320/1
5.4.2. Window Detector In Differential Mode
Figure 5.8 shows two example window comparisons for right-justified, differential data, with
ADC0LTH:ADC0LTL = 0x0040 (+64d) and ADC0GTH:ADC0GTH = 0xFFFF (-1d). In differential mode, the
measurable voltage between the input pins is between -VREF and VREF*(511/512). Output codes are represented as 10-bit 2’s complement signed integers. In the left example, an AD0WINT interrupt will be generated if the ADC0 conversion word (ADC0H:ADC0L) is within the range defined by ADC0GTH:ADC0GTL
and ADC0LTH:ADC0LTL (if 0xFFFF (-1d) < ADC0H:ADC0L < 0x0040 (64d)). In the right example, an
AD0WINT interrupt will be generated if the ADC0 conversion word is outside of the range defined by the
ADC0GT and ADC0LT registers (if ADC0H:ADC0L < 0xFFFF (-1d) or ADC0H:ADC0L > 0x0040 (+64d)).
Figure 5.9 shows an example using left-justified data with equivalent ADC0GT and ADC0LT register settings.

ADC0H:ADC0L

Input Voltage
(Px.x - Px.x)
VREF x (511/512)

Input Voltage
(Px.x - Px.x)
0x01FF

VREF x (511/512)

0x01FF

AD0WINT
not affected

AD0WINT=1

0x0041
VREF x (64/512)

0x0040

0x0041
ADC0LTH:ADC0LTL

VREF x (64/512)

0x003F

0x0040
0x003F

AD0WINT=1
0x0000
VREF x (-1/512)

0xFFFF

0x0000
ADC0GTH:ADC0GTL

VREF x (-1/512)

0xFFFE

0xFFFF

ADC0GTH:ADC0GTL
AD0WINT
not affected
ADC0LTH:ADC0LTL

0xFFFE

AD0WINT=1

AD0WINT
not affected
-VREF

0x0200

-VREF

0x0200

Figure 5.8. ADC Window Compare Example: Right-Justified Differential Data

ADC0H:ADC0L

Input Voltage
(Px.x - Px.x)
VREF x (511/512)

Input Voltage
(Px.x - Px.y)
0x7FC0

VREF x (511/512)

0x7FC0

AD0WINT
not affected

AD0WINT=1

0x1040
VREF x (64/512)

0x1000

0x1040
ADC0LTH:ADC0LTL

VREF x (64/512)

0x0FC0

0x1000
0x0FC0

AD0WINT=1
0x0000
VREF x (-1/512)

0xFFC0

0x0000
ADC0GTH:ADC0GTL

VREF x (-1/512)

0xFF80

0xFFC0

0x8000

AD0WINT
not affected
ADC0LTH:ADC0LTL

0xFF80

AD0WINT=1

AD0WINT
not affected
-VREF

ADC0GTH:ADC0GTL

-VREF

0x8000

Figure 5.9. ADC Window Compare Example: Left-Justified Differential Data

Rev. 1.4

C8051F320/1
Table 5.1. ADC0 Electrical Characteristics
VDD = 3.0 V, VREF = 2.40 V, –40 to +85 °C unless otherwise specified.
Parameter

Conditions

Min

Typ

Max

Units

—
—
–15
–15
—

10
±0.5
±0.5
0
–1
10

±1
±1
15
15
—

bits
LSB
LSB
LSB
LSB
ppm/°C

DC Accuracy
Resolution
Integral Nonlinearity
Differential Nonlinearity
Offset Error
Full Scale Error
Offset Temperature Coefficient

Guaranteed Monotonic

Dynamic Performance (10 kHz sine-wave Single-ended input, 1 dB below Full Scale, 200 ksps)
Signal-to-Noise Plus Distortion
Total Harmonic Distortion
Spurious-Free Dynamic Range

53
—
—

55.5
–67
78

—
—
—

dB
dB
dB

—
10
300
—

—
—
—
—

3
—
—
200

MHz
clocks
ns
ksps

0
–VREF
0

—
—

VREF
VREF
VDD

V
V
V

5
—
±0.1

—
—
—

Linearity1

—
—
—

Gain2

—

2.86

—

mV/°C

(Temp = 0 °C)

—

0.776
±8.5

—

Operating Mode, 200 ksps

—

400

900

µA

—

±0.3

Up to the 5 harmonic

Conversion Rate
SAR Conversion Clock
Conversion Time in SAR Clocks
Track/Hold Acquisition Time
Throughput Rate
Analog Inputs
ADC Input Voltage Range
Absolute Pin Voltage with respect
to GND
Input Capacitance
Temperature Sensor

Offset1,2

Single Ended (AIN+ – GND)
Differential (AIN+ – AIN–)
Single Ended or Differential

°C

Power Specifications
Power Supply Current
(VDD supplied to ADC0)
Power Supply Rejection

Notes:
1. Includes ADC offset, gain, and linearity variations.
2. Represents one standard deviation from the mean.

Rev. 1.4

mV/V

C8051F320/1
6.

Voltage Reference

The Voltage reference MUX on C8051F320/1 devices is configurable to use an externally connected voltage reference, the internal reference voltage generator, or the power supply voltage VDD (see Figure 6.1).
The REFSL bit in the Reference Control register (REF0CN) selects the reference source. For the internal
reference or an external source, REFSL should be set to ‘0’; For VDD as the reference source, REFSL
should be set to ‘1’.
The BIASE bit enables the internal ADC bias generator, which is used by the ADC and Internal Oscillator.
This enable is forced to logic 1 when either of the aforementioned peripherals is enabled. The ADC bias
generator may be enabled manually by writing a ‘1’ to the BIASE bit in register REF0CN; see Figure 6.1 for
REF0CN register details. The Reference bias generator (see Figure 6.1) is used by the Internal Voltage
Reference, Temperature Sensor, and Clock Multiplier. The Reference bias is automatically enabled when
any of the aforementioned peripherals are enabled. The electrical specifications for the voltage reference
and bias circuits are given in Table 6.1.
Important Note About the VREF Input: Port pin P0.7 is used as the external VREF input. When using an
external voltage reference, P0.7 should be configured as analog input and skipped by the Digital Crossbar.
To configure P0.7 as analog input, set to ‘0’ Bit7 in register P0MDIN. To configure the Crossbar to skip
P0.7, set to ‘1’ Bit7 in register P0SKIP. Refer to Section “14. Port Input/Output” on page 126 for complete
Port I/O configuration details.
The temperature sensor connects to the ADC0 positive input multiplexer (see Section “5.1. Analog Multiplexer” on page 40 for details). The TEMPE bit in register REF0CN enables/disables the temperature sensor. While disabled, the temperature sensor defaults to a high impedance state and any ADC0
measurements performed on the sensor result in meaningless data.

REFSL
TEMPE
BIASE
REFBE

REF0CN

AD0EN
EN

ADC Bias

To ADC,
Internal Oscillator

IOSCEN

VDD

External
Voltage
Reference
Circuit

EN
VREF

Temp Sensor

To Analog Mux

0
VREF
(to ADC)

GND
VDD

1
CLKMUL
Enable
EN

TEMPE

Reference
Bias

To Clock Multiplier,
Temp Sensor

REFBE
EN

Internal
Reference

Figure 6.1. Voltage Reference Functional Block Diagram

Rev. 1.4

C8051F320/1
SFR Definition 6.1. REF0CN: Reference Control
R/W

R/W

Reset Value

REFSL

TEMPE

BIASE

REFBE

00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

0xD1
Bits7–3: UNUSED. Read = 00000b; Write = don’t care.
Bit3:
REFSL: Voltage Reference Select.
This bit selects the source for the internal voltage reference.
0: VREF pin used as voltage reference.
1: VDD used as voltage reference.
Bit2:
TEMPE: Temperature Sensor Enable Bit.
0: Internal Temperature Sensor off.
1: Internal Temperature Sensor on.
Bit1:
BIASE: Internal Analog Bias Generator Enable Bit.
0: Internal Bias Generator off.
1: Internal Bias Generator on.
Bit0:
REFBE: Internal Reference Buffer Enable Bit.
0: Internal Reference Buffer disabled.
1: Internal Reference Buffer enabled. Internal voltage reference driven on the VREF pin.

Table 6.1. Voltage Reference Electrical Characteristics
VDD = 3.0 V; –40 to +85 °C unless otherwise specified.
Parameter
Conditions
Internal Reference (REFBE = 1)
Output Voltage
25 °C ambient
VREF Short-Circuit Current
VREF Temperature Coefficient
Load Regulation
Load = 0 to 200 µA to GND
VREF Turn-on Time 1
4.7 µF tantalum, 0.1 µF ceramic bypass
VREF Turn-on Time 2
0.1 µF ceramic bypass
VREF Turn-on Time 3
no bypass cap
Power Supply Rejection
External Reference (REFBE = 0)
Input Voltage Range
Input Current
Sample Rate = 200 ksps; VREF = 3.0 V
Bias Generators
ADC Bias Generator
BIASE = ‘1’
Reference Bias Generator

Rev. 1.4

Min

Typ

Max

Units

2.38

2.44

2.50
10

V
mA
ppm/°C

1.5
2
20
10
140

ppm/µA
ms
µs
µs
ppm/V

VDD

V
µA

148
60

µA
µA

12
106
42

C8051F320/1
7.

Comparators

C8051F320/1 devices include two on-chip programmable voltage Comparators: Comparator0 is shown in
Figure 7.1; Comparator1 is shown in Figure 7.2. The two Comparators operate identically with the following exceptions: (1) Their input selections differ as shown in Figure 7.1 and Figure 7.2; (2) Comparator0 can
be used as a reset source.
Each Comparator offers programmable response time and hysteresis, an analog input multiplexer, and two
outputs that are optionally available at the Port pins: a synchronous “latched” output (CP0, CP1), or an
asynchronous “raw” output (CP0A, CP1A). The asynchronous signal is available even when the system
clock is not active. This allows the Comparators to operate and generate an output with the device in
STOP mode. When assigned to a Port pin, the Comparator outputs may be configured as open drain or
push-pull (see Section “14.2. Port I/O Initialization” on page 130). Comparator0 may also be used as a
reset source (see Section “10.5. Comparator0 Reset” on page 102).
The Comparator0 inputs are selected in the CPT0MX register (Figure 7.2). The CMX0P1–CMX0P0 bits
select the Comparator0 positive input; the CMX0N1–CMX0N0 bits select the Comparator0 negative input.
The Comparator1 inputs are selected in the CPT1MX register (Figure 7.5). The CMX1P1–CMX1P0 bits
select the Comparator1 positive input; the CMX1N1–CMX1N0 bits select the Comparator1 negative input.

CPT0CN

CMX0N1
CMX0N0

CP0EN
CP0OUT
CP0RIF

VDD

CP0FIF
CP0HYP1
CP0HYP0
CP0HYN1
CP0HYN0

CP0
Interrupt

CMX0P1
CMX0P0

CP0
Rising-edge

P1.0

CP0
Falling-edge

P1.4
P2.0

CP0 +

Interrupt
Logic

P2.4

CP0RIE
CP0FIE

+
D

P1.5

SET

CLR

CP0

Crossbar
(SYNCHRONIZER)

GND

CP0 -

P2.1

CP0A
Reset
Decision
Tree

P2.5

Note: P2.4 and P2.5 available
only on C8051F320

SET

CLR

P1.1

CPT0MD

CPT0MX

Important Note About Comparator Inputs: The Port pins selected as Comparator inputs should be configured as analog inputs in their associated Port configuration register, and configured to be skipped by the
Crossbar (for details on Port configuration, see Section “14.3. General Purpose Port I/O” on page 132).

CP0RIE
CP0FIE

CP0MD1
CP0MD0

Figure 7.1. Comparator0 Functional Block Diagram

Rev. 1.4

C8051F320/1
Comparator outputs can be polled in software, used as an interrupt source, and/or routed to a Port pin.
When routed to a Port pin, Comparator outputs are available asynchronous or synchronous to the system
clock; the asynchronous output is available even in STOP mode (with no system clock active). When disabled, the Comparator output (if assigned to a Port I/O pin via the Crossbar) defaults to the logic low state,
and supply current falls to less than 100 nA. See Section “14.1. Priority Crossbar Decoder” on page 128
for details on configuring Comparator outputs via the digital Crossbar. Comparator inputs can be externally
driven from –0.25 V to (VDD) + 0.25 V without damage or upset. The complete Comparator electrical specifications are given in Table 7.1.

CPT1CN

CPT1MX

Comparator response time may be configured in software via the CPTnMD registers (see Figure 7.3 and
Figure 7.6). Selecting a longer response time reduces the Comparator supply current. See Table 7.1 for
complete timing and supply current specifications.

CMX1N1
CMX1N0

CP1EN
CP1OUT
CP1RIF
CP1FIF

VDD

CP1HYP1
CP1HYP0
CP1HYN1
CP1HYN0

CP1
Interrupt

CMX1P1
CMX1P0

CP1
Rising-edge

P1.2

CP1
Falling-edge

P1.6
P2.2

CP1 +

Interrupt
Logic

P2.6

CP1

+
D

SET

CLR

SET

CLR

Crossbar

P1.3
P1.7

(SYNCHRONIZER)

CP1 -

GND

P2.3

CPT1MD

P2.7

Note: P2.6 and P2.7 available
only on C8051F320

CP1RIE
CP1FIE

CP1MD1
CP1MD0

Figure 7.2. Comparator1 Functional Block Diagram

CP1RIE
CP1FIE

Rev. 1.4

CP1A

C8051F320/1

VIN+
VIN-

CP0+
CP0-

+
CP0
_

OUT

CIRCUIT CONFIGURATION

Positive Hysteresis Voltage
(Programmed with CP0HYP Bits)

VIN-

INPUTS

Negative Hysteresis Voltage
(Programmed by CP0HYN Bits)

VIN+

VOH

OUTPUT
VOL
Negative Hysteresis
Disabled
Positive Hysteresis
Disabled

Maximum
Negative Hysteresis

Maximum
Positive Hysteresis

Figure 7.3. Comparator Hysteresis Plot
Comparator hysteresis is programmed using Bits3–0 in the Comparator Control Register CPTnCN (shown
in Figure 7.1 and Figure 7.4). The amount of negative hysteresis voltage is determined by the settings of
the CPnHYN bits. As shown in Figure 7.3, settings of 20, 10 or 5 mV of negative hysteresis can be
programmed, or negative hysteresis can be disabled. In a similar way, the amount of positive hysteresis is
determined by the setting the CPnHYP bits.
Comparator interrupts can be generated on both rising-edge and falling-edge output transitions. (For Interrupt enable and priority control, see Section “9.3. Interrupt Handler” on page 87.) The CPnFIF flag is set to
‘1’ upon a Comparator falling-edge, and the CPnRIF flag is set to ‘1’ upon the Comparator rising-edge.
Once set, these bits remain set until cleared by software. The output state of the Comparator can be
obtained at any time by reading the CPnOUT bit. The Comparator is enabled by setting the CPnEN bit to
‘1’, and is disabled by clearing this bit to ‘0’.

Rev. 1.4

C8051F320/1
SFR Definition 7.1. CPT0CN: Comparator0 Control
R/W

R/W

CP0EN

CP0OUT

CP0RIF

CP0FIF

Bit7

Bit6

Bit5

Bit4

R/W

Reset Value

CP0HYP1 CP0HYP0 CP0HYN1 CP0HYN0 00000000
Bit3

Bit2

Bit1

Bit0

SFR Address:

0x9B
Bit7:

CP0EN: Comparator0 Enable Bit.
0: Comparator0 Disabled.
1: Comparator0 Enabled.
Bit6:
CP0OUT: Comparator0 Output State Flag.
0: Voltage on CP0+ < CP0–.
1: Voltage on CP0+ > CP0–.
Bit5:
CP0RIF: Comparator0 Rising-Edge Flag.
0: No Comparator0 Rising Edge has occurred since this flag was last cleared.
1: Comparator0 Rising Edge has occurred.
Bit4:
CP0FIF: Comparator0 Falling-Edge Flag.
0: No Comparator0 Falling-Edge has occurred since this flag was last cleared.
1: Comparator0 Falling-Edge Interrupt has occurred.
Bits3–2: CP0HYP1–0: Comparator0 Positive Hysteresis Control Bits.
00: Positive Hysteresis Disabled.
01: Positive Hysteresis = 5 mV.
10: Positive Hysteresis = 10 mV.
11: Positive Hysteresis = 20 mV.
Bits1–0: CP0HYN1–0: Comparator0 Negative Hysteresis Control Bits.
00: Negative Hysteresis Disabled.
01: Negative Hysteresis = 5 mV.
10: Negative Hysteresis = 10 mV.
11: Negative Hysteresis = 20 mV.

Rev. 1.4

C8051F320/1
SFR Definition 7.2. CPT0MX: Comparator0 MUX Selection
R/W

R/W

Bit7

Bit6

R/W

CMX0N1 CMX0N0
Bit5

Bit4

R/W

CMX0P1

Bit3

Bit2

Bit1

R/W

Reset Value

CMX0P0 00000000
Bit0

SFR Address:

0x9F
Bits7–6: UNUSED. Read = 00b, Write = don’t care.
Bits5–4: CMX0N1–CMX0N0: Comparator0 Negative Input MUX Select.
These bits select which Port pin is used as the Comparator0 negative input.
CMX0N1 CMX0N0
0
0
0
1
1
0
1
1

Negative Input
P1.1
P1.5
P2.1
P2.5*

Bits3–2: UNUSED. Read = 00b, Write = don’t care.
Bits1–0: CMX0P1–CMX0P0: Comparator0 Positive Input MUX Select.
These bits select which Port pin is used as the Comparator0 positive input.
CMX0P1 CMX0P0
0
0
0
1
1
0
1
1

Positive Input
P1.0
P1.4
P2.0
P2.4*

*Note: P2.4 and P2.5 available only on
C8051F320 devices; selection
reserved on C8051F321 devices.

Rev. 1.4

C8051F320/1
SFR Definition 7.3. CPT0MD: Comparator0 Mode Selection
R/W

R/W

CP0RIE

CP0FIE

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

R/W

Reset Value

CP0MD1 CP0MD0 00000010
Bit1

Bit0

SFR Address:

0x9D
Bits7–6: UNUSED. Read = 00b. Write = don’t care.
Bit5:
CP0RIE: Comparator0 Rising-Edge Interrupt Enable.
0: Comparator0 rising-edge interrupt disabled.
1: Comparator0 rising-edge interrupt enabled.
Bit4:
CP0FIE: Comparator0 Falling-Edge Interrupt Enable.
0: Comparator0 falling-edge interrupt disabled.
1: Comparator0 falling-edge interrupt enabled.
Bits3–2: UNUSED. Read = 00b. Write = don’t care.
Bits1–0: CP0MD1–CP0MD0: Comparator0 Mode Select
These bits select the response time for Comparator0.
Mode
0
1
2
3

CP0MD1
0
0
1
1

CP0MD0 CP0 Response Time (TYP)
0
100 ns
1
175 ns
0
320 ns
1
1050 ns

Rev. 1.4

C8051F320/1
SFR Definition 7.4. CPT1CN: Comparator1 Control
R/W

R/W

CP1EN

CP1OUT

CP1RIF

CP1FIF

Bit7

Bit6

Bit5

Bit4

R/W

Reset Value

CP1HYP1 CP1HYP0 CP1HYN1 CP1HYN0 00000000
Bit3

Bit2

Bit1

Bit0

SFR Address:

0x9A
Bit7:

CP1EN: Comparator1 Enable Bit.
0: Comparator1 Disabled.
1: Comparator1 Enabled.
Bit6:
CP1OUT: Comparator1 Output State Flag.
0: Voltage on CP1+ < CP1–.
1: Voltage on CP1+ > CP1–.
Bit5:
CP1RIF: Comparator1 Rising-Edge Flag.
0: No Comparator1 Rising Edge has occurred since this flag was last cleared.
1: Comparator1 Rising Edge has occurred.
Bit4:
CP1FIF: Comparator1 Falling-Edge Flag.
0: No Comparator1 Falling-Edge has occurred since this flag was last cleared.
1: Comparator1 Falling-Edge has occurred.
Bits3–2: CP1HYP1–0: Comparator1 Positive Hysteresis Control Bits.
00: Positive Hysteresis Disabled.
01: Positive Hysteresis = 5 mV.
10: Positive Hysteresis = 10 mV.
11: Positive Hysteresis = 20 mV.
Bits1–0: CP1HYN1–0: Comparator1 Negative Hysteresis Control Bits.
00: Negative Hysteresis Disabled.
01: Negative Hysteresis = 5 mV.
10: Negative Hysteresis = 10 mV.
11: Negative Hysteresis = 20 mV.

Rev. 1.4

C8051F320/1
SFR Definition 7.5. CPT1MX: Comparator1 MUX Selection
R/W

R/W

Bit7

Bit6

R/W

CMX1N1 CMX1N0
Bit5

Bit4

R/W

CMX1P1

Bit3

Bit2

Bit1

R/W

Reset Value

CMX1P0 00000000
Bit0

SFR Address:

0x9E
Bits7–6: UNUSED. Read = 00b, Write = don’t care.
Bits5–4: CMX1N1–CMX1N0: Comparator1 Negative Input MUX Select.
These bits select which Port pin is used as the Comparator1 negative input.
CMX1N1 CMX1N0
0
0
0
1
1
0
1
1

Negative Input
P1.3
P1.7
P2.3
P2.7*

Bits3–2: UNUSED. Read = 00b, Write = don’t care.
Bits1–0: CMX1P1–CMX1P0: Comparator1 Positive Input MUX Select.
These bits select which Port pin is used as the Comparator1 positive input.
CMX1P1 CMX1P0
0
0
0
1
1
0
1
1

Positive Input
P1.2
P1.6
P2.2
P2.6*

*Note: P2.6 and P2.7 available only on
C8051F320 devices; selection
reserved on C8051F321 devices.

Rev. 1.4

C8051F320/1
SFR Definition 7.6. CPT1MD: Comparator1 Mode Selection
R/W

R/W

CP1RIE

CP1FIE

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

R/W

Reset Value

CP1MD1 CP1MD0 00000010
Bit1

Bit0

SFR Address:

0x9C
Bits7–6: UNUSED. Read = 00b, Write = don’t care.
Bit5:
CP1RIE: Comparator1 Rising-Edge Interrupt Enable.
0: Comparator1 rising-edge interrupt disabled.
1: Comparator1 rising-edge interrupt enabled.
Bit4:
CP1FIE: Comparator1 Falling-Edge Interrupt Enable.
0: Comparator1 falling-edge interrupt disabled.
1: Comparator1 falling-edge interrupt enabled.
Bits3–2: UNUSED. Read = 00b. Write = don’t care.
Bits1–0: CP1MD1–CP1MD0: Comparator1 Mode Select.
These bits select the response time for Comparator1.
Mode
0
1
2
3

CP1MD1
0
0
1
1

CP1MD0
0
1
0
1

CP1 Response Time (TYP)
100 ns
175 ns
320 ns
1050 ns

Rev. 1.4

C8051F320/1
Table 7.1. Comparator Electrical Characteristics
VDD = 3.0 V, –40 to +85 °C unless otherwise noted. All specifications apply to both Comparator0 and Comparator1
unless otherwise noted.

Parameter
Response Time:
Mode 0, Vcm* = 1.5 V
Response Time:
Mode 1, Vcm* = 1.5 V
Response Time:
Mode 2, Vcm* = 1.5 V
Response Time:
Mode 3, Vcm* = 1.5 V

Conditions

Min

Typ

Max

Units

CP0+ – CP0– = 100 mV

—

100

—

CP0+ – CP0– = –100 mV

—

250

—

CP0+ – CP0– = 100 mV

—

175

—

CP0+ – CP0– = –100 mV

—

500

—

CP0+ – CP0– = 100 mV

—

320

—

CP0+ – CP0– = –100 mV

—

1100

—

CP0+ – CP0– = 100 mV

—

1050

—

CP0+ – CP0– = –100 mV

Common-Mode Rejection Ratio

—

5200

—

1.5

mV/V

Positive Hysteresis 1

CP0HYP1–0 = 00

—

Positive Hysteresis 2

CP0HYP1–0 = 01

Positive Hysteresis 3

CP0HYP1–0 = 10

Positive Hysteresis 4

CP0HYP1–0 = 11

Negative Hysteresis 1

CP0HYN1–0 = 00

Negative Hysteresis 2

CP0HYN1–0 = 01

Negative Hysteresis 3

CP0HYN1–0 = 10

Negative Hysteresis 4

CP0HYN1–0 = 11

VDD + 0.25

—

Inverting or Non-Inverting Input
Voltage Range

–0.25

Input Capacitance

—

Input Bias Current

—

0.001

—

Input Offset Voltage

–5

—

0.1

—

mV/V

Power Supply
Power Supply Rejection
Power-up Time

Supply Current at DC

—

µs

Mode 0

—

7.6

µA

Mode 1

—

3.2

µA

Mode 2

—

1.3

µA

Mode 3

—

0.4

2.5

µA

*Note: Vcm is the common-mode voltage on CP0+ and CP0-.

Rev. 1.4

C8051F320/1
8.

Voltage Regulator (REG0)

C8051F320/1 devices include a 5-to-3 V voltage regulator (REG0). When enabled, the REG0 output
appears on the VDD pin and can be used to power external devices. REG0 can be enabled/disabled by
software using bit REGEN in register REG0CN. See Table 8.1 for REG0 electrical characteristics.
Note that the VBUS signal must be connected to the VBUS pin when using the device in a USB network.
The VBUS signal should only be connected to the REGIN pin when operating the device as a bus-powered
function. REG0 configuration options are shown in Figure 8.2–Figure 8.5.
The input (VREGIN) and output (VDD) of the voltage regulator should both be protected by adding decoupling and bypass capacitors on each pin to ground. Suggested values for the two capacitors are
4.7 µF + 0.1 µF. These capacitors will increase noise immunity and stabilize the voltage supply.

REG0

VREGIN
4.7 µF

0.1 µF

VDD

VDD
4.7 µF

0.1 µF

Figure 8.1. External Capacitors for Voltage Regulator Input/Output
8.1.

Regulator Mode Selection

REG0 offers a low power mode intended for use when the device is in suspend mode. In this low power
mode, the REG0 output remains as specified; however the REG0 dynamic performance (response time) is
degraded. See Table 8.1 for normal and low power mode supply current specifications. The REG0 mode
selection is controlled via the REGMOD bit in register REG0CN.

8.2.

VBUS Detection

When the USB Function Controller is used (see section Section “15. Universal Serial Bus Controller
(USB)” on page 139), the VBUS signal should be connected to the VBUS pin. The VBSTAT bit (register
REG0CN) indicates the current logic level of the VBUS signal. If enabled, a VBUS interrupt will be generated when the VBUS signal matches the polarity selected by the VBPOL bit in register REG0CN. The
VBUS interrupt is level-sensitive, and has no associated interrupt pending flag. The VBUS interrupt will be
active as long as the VBUS signal matches the polarity selected by VBPOL. See Table 8.1 for VBUS input
parameters.

Rev. 1.4

C8051F320/1
Important Note: When USB is selected as a reset source, a system reset will be generated when the
VBUS signal matches the polarity selected by the VBPOL bit. See Section “10. Reset Sources” on page 99
for details on selecting USB as a reset source.

Table 8.1. Voltage Regulator Electrical Specifications
–40 to +85 °C unless otherwise specified.

Parameter

Conditions

Min

Typ

Max

Units

2.7

—

5.25

3.0

3.3

3.6

Output Current2

—

100

VBUS Detection Input Low Voltage

—

1.0

VBUS Detection Input High Voltage

3.0

—

65
35

111
61

µA

—

mV/mA

Input Voltage Range1
Output Voltage (VDD)2

Output Current = 1 to 100 mA

Normal Mode (REGMOD = 0)
Low Power Mode (REGMOD = 1)

Bias Current
Dropout Voltage (VDO)3

Notes:
1. Input range specified for regulation. When an external regulator is used, REGIN should be tied to VDD.
2. Output current is total regulator output, including any current required by the C8051F320/1.
3. The minimum input voltage is 2.70 V or VDD + VDO (max load), whichever is greater.

C8051F320/1

VBUS

VBUS Sense

From VBUS
REGIN

5V In

Voltage Regulator (REG0)

3V Out
To 3V
Power Net

Device
Power Net

VDD

Figure 8.2. REG0 Configuration: USB Bus-Powered

Rev. 1.4

C8051F320/1

From VBUS

VBUS

VBUS Sense
From 5V
Power Net

REGIN

5V In

Voltage Regulator (REG0)

3V Out
To 3V
Power Net

Device
Power Net

VDD

Figure 8.3. REG0 Configuration: USB Self-Powered

C8051F320/1

From VBUS

VBUS

VBUS Sense
REGIN

5V In

Voltage Regulator (REG0)

3V Out
From 3V
Power Net

Device
Power Net

VDD

Figure 8.4. REG0 Configuration: USB Self-Powered, Regulator Disabled

Rev. 1.4

C8051F320/1

VBUS

VBUS Sense
From 5V
Power Net

REGIN

5V In

Voltage Regulator (REG0)

3V Out
To 3V
Power Net

Device
Power Net

VDD

Figure 8.5. REG0 Configuration: No USB Connection
SFR Definition 8.1. REG0CN: Voltage Regulator Control
R/W

R/W

REGDIS

VBSTAT

VBPOL

Bit7

Bit6

Bit5

R/W

Reset Value

REGMOD Reserved Reserved Reserved Reserved 00000000
Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

0xC9
Bit7:

REGDIS: Voltage Regulator Disable.
0: Voltage Regulator Enabled.
1: Voltage Regulator Disabled.
Bit6:
VBSTAT: VBUS Signal Status.
0: VBUS signal currently absent (device not attached to USB network).
1: VBUS signal currently present (device attached to USB network).
Bit5:
VBPOL: VBUS Interrupt Polarity Select.
This bit selects the VBUS interrupt polarity.
0: VBUS interrupt active when VBUS is low.
1: VBUS interrupt active when VBUS is high.
Bit4:
REGMOD: Voltage Regulator Mode Select.
This bit selects the Voltage Regulator mode. When REGMOD is set to ‘1’, the voltage regulator operates in low power (suspend) mode.
0: USB0 Voltage Regulator in normal mode.
1: USB0 Voltage Regulator in low power mode.
Bits3–0: Reserved. Read = 0000b. Must Write = 0000b.

Rev. 1.4

C8051F320/1
9.

CIP-51 Microcontroller

The MCU system controller core is the CIP-51 microcontroller. The CIP-51 is fully compatible with the
MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used to develop software. The MCU family has a superset of all the peripherals included with a standard 8051. Included are
four 16-bit counter/timers (see description in Section 19), an enhanced full-duplex UART (see description
in Section 17), an Enhanced SPI (see description in Section 18), 256 bytes of internal RAM, 128 byte Special Function Register (SFR) address space (Section 9.2.6), and 25 Port I/O (see description in Section
14). The CIP-51 also includes on-chip debug hardware (see description in Section 21), and interfaces
directly with the analog and digital subsystems providing a complete data acquisition or control-system
solution in a single integrated circuit.
The CIP-51 Microcontroller core implements the standard 8051 organization and peripherals as well as
additional custom peripherals and functions to extend its capability (see Figure 9.1 for a block diagram).
The CIP-51 includes the following features:
- Fully Compatible with MCS-51 Instruction
Set
- 25 MIPS Peak Throughput with 25 MHz
Clock
- 0 to 25 MHz Clock Frequency
- 256 Bytes of Internal RAM

25 Port I/O ('F320) / 21 Port I/O ('F321)
Extended Interrupt Handler
Reset Input
Power Management Modes
On-chip Debug Logic
Program and Data Memory Security

ACCUMULATOR

STACK POINTER

TMP1

TMP2

SRAM
ADDRESS
REGISTER

PSW

ALU

SRAM
(256 X 8)
D8

DATA BUS

B REGISTER

DATA BUS

DATA BUS
SFR_ADDRESS
BUFFER

DATA POINTER

D8
D8

SFR
BUS
INTERFACE

SFR_CONTROL
SFR_WRITE_DATA
SFR_READ_DATA

DATA BUS

PC INCREMENTER

PROGRAM COUNTER (PC)

PRGM. ADDRESS REG.

MEM_ADDRESS

MEM_CONTROL
A16

MEMORY
INTERFACE

MEM_WRITE_DATA
MEM_READ_DATA

PIPELINE
RESET

CONTROL
LOGIC

SYSTEM_IRQs

CLOCK
D8

STOP
IDLE

POWER CONTROL
REGISTER

INTERRUPT
INTERFACE

EMULATION_IRQ

Figure 9.1. CIP-51 Block Diagram

Rev. 1.4

C8051F320/1
Performance
The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the standard 8051 architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24 system
clock cycles to execute, and usually have a maximum system clock of 12 MHz. By contrast, the CIP-51
core executes 70% of its instructions in one or two system clock cycles, with no instructions taking more
than eight system clock cycles.
With the CIP-51's maximum system clock at 25 MHz, it has a peak throughput of 25 MIPS. The CIP-51 has
a total of 109 instructions. The table below shows the total number of instructions that for execution time.
Clocks to Execute

2/3

3/4

4/5

Number of Instructions

Programming and Debugging Support
In-system programming of the Flash program memory and communication with on-chip debug support
logic is accomplished via the Silicon Labs 2-Wire Development Interface (C2). Note that the re-programmable Flash can also be read and changed a single byte at a time by the application software using the
MOVC and MOVX instructions. This feature allows program memory to be used for non-volatile data storage as well as updating program code under software control.
The on-chip debug support logic facilitates full speed in-circuit debugging, allowing the setting of hardware
breakpoints, starting, stopping and single stepping through program execution (including interrupt service
routines), examination of the program's call stack, and reading/writing the contents of registers and memory. This method of on-chip debugging is completely non-intrusive, requiring no RAM, Stack, timers, or
other on-chip resources. C2 details can be found in Section “21. C2 Interface” on page 245.
The CIP-51 is supported by development tools from Silicon Labs and third party vendors. Silicon Labs provides an integrated development environment (IDE) including editor, macro assembler, debugger and programmer. The IDE's debugger and programmer interface to the CIP-51 via the C2 interface to provide fast
and efficient in-system device programming and debugging. Third party macro assemblers and C compilers are also available.

9.1.

Instruction Set

The instruction set of the CIP-51 System Controller is fully compatible with the standard MCS-51™ instruction set. Standard 8051 development tools can be used to develop software for the CIP-51. All CIP-51
instructions are the binary and functional equivalent of their MCS-51™ counterparts, including opcodes,
addressing modes and effect on PSW flags. However, instruction timing is different than that of the standard 8051.

9.1.1. Instruction and CPU Timing
In many 8051 implementations, a distinction is made between machine cycles and clock cycles, with
machine cycles varying from 2 to 12 clock cycles in length. However, the CIP-51 implementation is based
solely on clock cycle timing. All instruction timings are specified in terms of clock cycles.
Due to the pipelined architecture of the CIP-51, most instructions execute in the same number of clock
cycles as there are program bytes in the instruction. Conditional branch instructions take one less clock
cycle to complete when the branch is not taken as opposed to when the branch is taken. Table 9.1 is the
CIP-51 Instruction Set Summary, which includes the mnemonic, number of bytes, and number of clock
cycles for each instruction.

Rev. 1.4

C8051F320/1
9.1.2. MOVX Instruction and Program Memory
The MOVX instruction is typically used to access external data memory (Note: the C8051F320/1 does not
support off-chip data or program memory). In the CIP-51, the MOVX write instruction is used to accesses
external RAM (XRAM) and the on-chip program memory space implemented as re-programmable Flash
memory. The Flash access feature provides a mechanism for the CIP-51 to update program code and use
the program memory space for non-volatile data storage. Refer to Section “11. Flash Memory” on
page 106 for further details.

Table 9.1. CIP-51 Instruction Set Summary
Mnemonic
ADD A, Rn
ADD A, direct
ADD A, @Ri
ADD A, #data
ADDC A, Rn
ADDC A, direct
ADDC A, @Ri
ADDC A, #data
SUBB A, Rn
SUBB A, direct
SUBB A, @Ri
SUBB A, #data
INC A
INC Rn
INC direct
INC @Ri
DEC A
DEC Rn
DEC direct
DEC @Ri
INC DPTR
MUL AB
DIV AB
DA A
ANL A, Rn
ANL A, direct
ANL A, @Ri
ANL A, #data
ANL direct, A
ANL direct, #data
ORL A, Rn
ORL A, direct
ORL A, @Ri
ORL A, #data

Description
Arithmetic Operations
Add register to A
Add direct byte to A
Add indirect RAM to A
Add immediate to A
Add register to A with carry
Add direct byte to A with carry
Add indirect RAM to A with carry
Add immediate to A with carry
Subtract register from A with borrow
Subtract direct byte from A with borrow
Subtract indirect RAM from A with borrow
Subtract immediate from A with borrow
Increment A
Increment register
Increment direct byte
Increment indirect RAM
Decrement A
Decrement register
Decrement direct byte
Decrement indirect RAM
Increment Data Pointer
Multiply A and B
Divide A by B
Decimal adjust A
Logical Operations
AND Register to A
AND direct byte to A
AND indirect RAM to A
AND immediate to A
AND A to direct byte
AND immediate to direct byte
OR Register to A
OR direct byte to A
OR indirect RAM to A
OR immediate to A

Rev. 1.4

Bytes

Clock
Cycles

1
2
1
2
1
2
1
2
1
2
1
2
1
1
2
1
1
1
2
1
1
1
1
1

1
2
2
2
1
2
2
2
1
2
2
2
1
1
2
2
1
1
2
2
1
4
8
1

1
2
1
2
2
3
1
2
1
2

1
2
2
2
2
3
1
2
2
2

C8051F320/1
Table 9.1. CIP-51 Instruction Set Summary (Continued)
Mnemonic

Description

ORL direct, A
ORL direct, #data
XRL A, Rn
XRL A, direct
XRL A, @Ri
XRL A, #data
XRL direct, A
XRL direct, #data
CLR A
CPL A
RL A
RLC A
RR A
RRC A
SWAP A

OR A to direct byte
OR immediate to direct byte
Exclusive-OR Register to A
Exclusive-OR direct byte to A
Exclusive-OR indirect RAM to A
Exclusive-OR immediate to A
Exclusive-OR A to direct byte
Exclusive-OR immediate to direct byte
Clear A
Complement A
Rotate A left
Rotate A left through Carry
Rotate A right
Rotate A right through Carry
Swap nibbles of A
Data Transfer
Move Register to A
Move direct byte to A
Move indirect RAM to A
Move immediate to A
Move A to Register
Move direct byte to Register
Move immediate to Register
Move A to direct byte
Move Register to direct byte
Move direct byte to direct byte
Move indirect RAM to direct byte
Move immediate to direct byte
Move A to indirect RAM
Move direct byte to indirect RAM
Move immediate to indirect RAM
Load DPTR with 16-bit constant
Move code byte relative DPTR to A
Move code byte relative PC to A
Move external data (8-bit address) to A
Move A to external data (8-bit address)
Move external data (16-bit address) to A
Move A to external data (16-bit address)
Push direct byte onto stack
Pop direct byte from stack
Exchange Register with A
Exchange direct byte with A
Exchange indirect RAM with A
Exchange low nibble of indirect RAM with A

MOV A, Rn
MOV A, direct
MOV A, @Ri
MOV A, #data
MOV Rn, A
MOV Rn, direct
MOV Rn, #data
MOV direct, A
MOV direct, Rn
MOV direct, direct
MOV direct, @Ri
MOV direct, #data
MOV @Ri, A
MOV @Ri, direct
MOV @Ri, #data
MOV DPTR, #data16
MOVC A, @A+DPTR
MOVC A, @A+PC
MOVX A, @Ri
MOVX @Ri, A
MOVX A, @DPTR
MOVX @DPTR, A
PUSH direct
POP direct
XCH A, Rn
XCH A, direct
XCH A, @Ri
XCHD A, @Ri

2
3
1
2
1
2
2
3
1
1
1
1
1
1
1

Clock
Cycles
2
3
1
2
2
2
2
3
1
1
1
1
1
1
1

1
2
1
2
1
2
2
2
2
3
2
3
1
2
2
3
1
1
1
1
1
1
2
2
1
2
1
1

1
2
2
2
1
2
2
2
2
3
2
3
2
2
2
3
3
3
3
3
3
3
2
2
1
2
2
2

Bytes

Rev. 1.4

C8051F320/1
Table 9.1. CIP-51 Instruction Set Summary (Continued)
Mnemonic
CLR C
CLR bit
SETB C
SETB bit
CPL C
CPL bit
ANL C, bit
ANL C, /bit
ORL C, bit
ORL C, /bit
MOV C, bit
MOV bit, C
JC rel
JNC rel
JB bit, rel
JNB bit, rel
JBC bit, rel
ACALL addr11
LCALL addr16
RET
RETI
AJMP addr11
LJMP addr16
SJMP rel
JMP @A+DPTR
JZ rel
JNZ rel
CJNE A, direct, rel
CJNE A, #data, rel
CJNE Rn, #data, rel
CJNE @Ri, #data, rel
DJNZ Rn, rel
DJNZ direct, rel
NOP

Description
Boolean Manipulation
Clear Carry
Clear direct bit
Set Carry
Set direct bit
Complement Carry
Complement direct bit
AND direct bit to Carry
AND complement of direct bit to Carry
OR direct bit to carry
OR complement of direct bit to Carry
Move direct bit to Carry
Move Carry to direct bit
Jump if Carry is set
Jump if Carry is not set
Jump if direct bit is set
Jump if direct bit is not set
Jump if direct bit is set and clear bit
Program Branching
Absolute subroutine call
Long subroutine call
Return from subroutine
Return from interrupt
Absolute jump
Long jump
Short jump (relative address)
Jump indirect relative to DPTR
Jump if A equals zero
Jump if A does not equal zero
Compare direct byte to A and jump if not equal
Compare immediate to A and jump if not equal
Compare immediate to Register and jump if not
equal
Compare immediate to indirect and jump if not
equal
Decrement Register and jump if not zero
Decrement direct byte and jump if not zero
No operation

Rev. 1.4

Bytes

Clock
Cycles

1
2
1
2
1
2
2
2
2
2
2
2
2
2
3
3
3

1
2
1
2
1
2
2
2
2
2
2
2
2/3
2/3
3/4
3/4
3/4

2
3
1
1
2
3
2
1
2
2
3
3

3
4
5
5
3
4
3
3
2/3
2/3
3/4
3/4

3/4

4/5

2
3
1

2/3
3/4
1

C8051F320/1

Notes on Registers, Operands and Addressing Modes:
Rn - Register R0-R7 of the currently selected register bank.
@Ri - Data RAM location addressed indirectly through R0 or R1.
rel - 8-bit, signed (two’s complement) offset relative to the first byte of the following instruction. Used by
SJMP and all conditional jumps.
direct - 8-bit internal data location’s address. This could be a direct-access Data RAM location (0x000x7F) or an SFR (0x80-0xFF).
#data - 8-bit constant
#data16 - 16-bit constant
bit - Direct-accessed bit in Data RAM or SFR
addr11 - 11-bit destination address used by ACALL and AJMP. The destination must be within the same
2 kB page of program memory as the first byte of the following instruction.
addr16 - 16-bit destination address used by LCALL and LJMP. The destination may be anywhere within
the 16 kB program memory space.
There is one unused opcode (0xA5) that performs the same function as NOP.
All mnemonics copyrighted © Intel Corporation 1980.

Rev. 1.4

C8051F320/1
9.2.

Memory Organization

The memory organization of the CIP-51 System Controller is similar to that of a standard 8051. There are
two separate memory spaces: program memory and data memory. Program and data memory share the
same address space but are accessed via different instruction types. The CIP-51 memory organization is
shown in Figure 9.2.

DATA MEMORY (RAM)
INTERNAL DATA ADDRESS SPACE

PROGRAM/DATA MEMORY
(Flash)
0xFF
0x3E00
0x3DFF

RESERVED
0x80
0x7F

Upper 128 RAM
(Indirect Addressing
Only)
(Direct and Indirect
Addressing)

16 K Flash
(In-System
Programmable in 512
Byte Sectors)

0x30
0x2F
0x20
0x1F
0x00

Bit Addressable

Special Function
Register's
(Direct Addressing Only)

Lower 128 RAM
(Direct and Indirect
Addressing)

General Purpose
Registers

EXTERNAL DATA ADDRESS SPACE
0x0000
0xFFFF
Same 2048 bytes as from
0x0000 to 0x07FF, wrapped
on 2 kB boundaries

0x0800
0x07FF
0x0400
0x03FF
0x0000

USB FIFOs
1024 Bytes
XRAM - 1024 Bytes
(accessable using MOVX
instruction)

Figure 9.2. Memory Map
9.2.1. Program Memory
The CIP-51 core has a 64k-byte program memory space. The C8051F320/1 implements 16k bytes of this
program memory space as in-system, re-programmable Flash memory, organized in a contiguous block
from addresses 0x0000 to 0x3FFF. Addresses above 0x3DFF are reserved.
Program memory is normally assumed to be read-only. However, the CIP-51 can write to program memory
by setting the Program Store Write Enable bit (PSCTL.0) and using the MOVX instruction. This feature provides a mechanism for the CIP-51 to update program code and use the program memory space for nonvolatile data storage. Refer to Section “11. Flash Memory” on page 106 for further details.

Rev. 1.4

C8051F320/1
9.2.2. Data Memory
The CIP-51 includes 256 of internal RAM mapped into the data memory space from 0x00 through 0xFF.
The lower 128 bytes of data memory are used for general purpose registers and scratch pad memory.
Either direct or indirect addressing may be used to access the lower 128 bytes of data memory. Locations
0x00 through 0x1F are addressable as four banks of general purpose registers, each bank consisting of
eight byte-wide registers. The next 16 bytes, locations 0x20 through 0x2F, may either be addressed as
bytes or as 128 bit locations accessible with the direct addressing mode.
The upper 128 bytes of data memory are accessible only by indirect addressing. This region occupies the
same address space as the Special Function Registers (SFR) but is physically separate from the SFR
space. The addressing mode used by an instruction when accessing locations above 0x7F determines
whether the CPU accesses the upper 128 bytes of data memory space or the SFRs. Instructions that use
direct addressing will access the SFR space. Instructions using indirect addressing above 0x7F access the
upper 128 bytes of data memory. Figure 9.2 illustrates the data memory organization of the CIP-51.

9.2.3. General Purpose Registers
The lower 32 bytes of data memory, locations 0x00 through 0x1F, may be addressed as four banks of general-purpose registers. Each bank consists of eight byte-wide registers designated R0 through R7. Only
one of these banks may be enabled at a time. Two bits in the program status word, RS0 (PSW.3) and RS1
(PSW.4), select the active register bank (see description of the PSW in Figure 9.4). This allows fast context
switching when entering subroutines and interrupt service routines. Indirect addressing modes use registers R0 and R1 as index registers.

9.2.4. Bit Addressable Locations
In addition to direct access to data memory organized as bytes, the sixteen data memory locations at 0x20
through 0x2F are also accessible as 128 individually addressable bits. Each bit has a bit address from
0x00 to 0x7F. Bit 0 of the byte at 0x20 has bit address 0x00 while bit7 of the byte at 0x20 has bit address
0x07. Bit 7 of the byte at 0x2F has bit address 0x7F. A bit access is distinguished from a full byte access by
the type of instruction used (bit source or destination operands as opposed to a byte source or destination).
The MCS-51™ assembly language allows an alternate notation for bit addressing of the form XX.B where
XX is the byte address and B is the bit position within the byte. For example, the instruction:
MOV

C, 22h.3

moves the Boolean value at 0x13 (bit 3 of the byte at location 0x22) into the Carry flag.

9.2.5. Stack
A programmer's stack can be located anywhere in the 256-byte data memory. The stack area is designated using the Stack Pointer (SP, 0x81) SFR. The SP will point to the last location used. The next value
pushed on the stack is placed at SP+1 and then SP is incremented. A reset initializes the stack pointer to
location 0x07. Therefore, the first value pushed on the stack is placed at location 0x08, which is also the
first register (R0) of register bank 1. Thus, if more than one register bank is to be used, the SP should be
initialized to a location in the data memory not being used for data storage. The stack depth can extend up
to 256 bytes.

Rev. 1.4

C8051F320/1
9.2.6. Special Function Registers
The direct-access data memory locations from 0x80 to 0xFF constitute the special function registers
(SFRs). The SFRs provide control and data exchange with the CIP-51's resources and peripherals. The
CIP-51 duplicates the SFRs found in a typical 8051 implementation as well as implementing additional
SFRs used to configure and access the sub-systems unique to the MCU. This allows the addition of new
functionality while retaining compatibility with the MCS-51™ instruction set. Table 9.2 lists the SFRs implemented in the CIP-51 System Controller.
The SFR registers are accessed anytime the direct addressing mode is used to access memory locations
from 0x80 to 0xFF. SFRs with addresses ending in 0x0 or 0x8 (e.g. P0, TCON, SCON0, IE, etc.) are bitaddressable as well as byte-addressable. All other SFRs are byte-addressable only. Unoccupied
addresses in the SFR space are reserved for future use. Accessing these areas will have an indeterminate
effect and should be avoided. Refer to the corresponding pages of the datasheet, as indicated in Table 9.3,
for a detailed description of each register.

Table 9.2. Special Function Register (SFR) Memory Map
F8 SPI0CN
PCA0L
PCA0H
F0
B
P0MDIN
P1MDIN
E8 ADC0CN PCA0CPL1 PCA0CPH1
E0
ACC
XBR0
XBR1
PCA0CPM
D8 PCA0CN PCA0MD
0
D0
PSW
REF0CN
C8 TMR2CN REG0CN TMR2RLL
C0 SMB0CN SMB0CF SMB0DAT
B8
IP
CLKMUL
AMX0N
B0
P3
OSCXCN OSCICN
A8
IE
CLKSEL
EMI0CN
A0
P2
SPI0CFG SPI0CKR
98 SCON0
SBUF0
CPT1CN
90
P1
TMR3CN TMR3RLL
88
TCON
TMOD
TL0
80
P0
SP
DPL
0(8)
1(9)
2(A)

PCA0CPL0 PCA0CPH0 PCA0CPL4
P2MDIN
P3MDIN
PCA0CPL2 PCA0CPH2 PCA0CPL3
IT01CF
PCA0CPM PCA0CPM PCA0CPM
1
2
3
P0SKIP
P1SKIP
TMR2RLH
TMR2L
TMR2H
ADC0GTL ADC0GTH ADC0LTL
AMX0P
ADC0CF
ADC0L
OSCICL

PCA0CPH4 VDM0CN
EIP1
EIP2
PCA0CPH3 RSTSRC
EIE1
EIE2
PCA0CPM
4
P2SKIP
USB0XCN
ADC0LTH
ADC0H
FLSCL

SPI0DAT P0MDOUT P1MDOUT P2MDOUT
CPT0CN CPT1MD CPT0MD CPT1MX
TMR3RLH
TMR3L
TMR3H USB0ADR
TL1
TH0
TH1
CKCON
DPH
3(B)
4(C)
5(D)
6(E)

FLKEY
P3MDOUT
CPT0MX
USB0DAT
PSCTL
PCON
7(F)

(bit addressable)

Rev. 1.4

C8051F320/1
Table 9.3. Special Function Registers
SFRs are listed in alphabetical order. All undefined SFR locations are reserved.

Address

Description

Page

ACC

0xE0

Accumulator

ADC0CF

0xBC

ADC0 Configuration

ADC0CN

0xE8

ADC0 Control

ADC0GTH

0xC4

ADC0 Greater-Than Compare High

ADC0GTL

0xC3

ADC0 Greater-Than Compare Low

ADC0H

0xBE

ADC0 High

ADC0L

0xBD

ADC0 Low

ADC0LTH

0xC6

ADC0 Less-Than Compare Word High

ADC0LTL

0xC5

ADC0 Less-Than Compare Word Low

AMX0N

0xBA

AMUX0 Negative Channel Select

AMX0P

0xBB

AMUX0 Positive Channel Select

0xF0

B Register

CKCON

0x8E

Clock Control

215

CLKSEL

0xA9

Clock Select

124

CLKMUL

0xB9

Clock Multiplier Control

122

CPT0CN

0x9B

Comparator0 Control

CPT0MD

0x9D

Comparator0 Mode Selection

CPT0MX

0x9F

Comparator0 MUX Selection

CPT1CN

0x9A

Comparator1 Control

CPT1MD

0x9C

Comparator1 Mode Selection

CPT1MX

0x9E

Comparator1 MUX Selection

DPH

0x83

Data Pointer High

DPL

0x82

Data Pointer Low

EIE1

0xE6

Extended Interrupt Enable 1

EIE2

0xE7

Extended Interrupt Enable 2

EIP1

0xF6

Extended Interrupt Priority 1

EIP2

0xF7

Extended Interrupt Priority 2

EMI0CN

0xAA

External Memory Interface Control

115

FLKEY

0xB7

Flash Lock and Key

112

FLSCL

0xB6

Flash Scale

113

0xA8

Interrupt Enable

0xB8

Interrupt Priority

Rev. 1.4

C8051F320/1
Table 9.3. Special Function Registers (Continued)
SFRs are listed in alphabetical order. All undefined SFR locations are reserved.

Address

Description

Page

IT01CF

0xE4

INT0/INT1 Configuration

OSCICL

0xB3

Internal Oscillator Calibration

118

OSCICN

0xB2

Internal Oscillator Control

118

OSCXCN

0xB1

External Oscillator Control

121

0x80

Port 0 Latch

133

P0MDIN

0xF1

Port 0 Input Mode Configuration

133

P0MDOUT

0xA4

Port 0 Output Mode Configuration

133

P0SKIP

0xD4

Port 0 Skip

134

0x90

Port 1 Latch

134

P1MDIN

0xF2

Port 1 Input Mode Configuration

134

P1MDOUT

0xA5

Port 1 Output Mode Configuration

135

P1SKIP

0xD5

Port 1 Skip

135

0xA0

Port 2 Latch

135

P2MDIN

0xF3

Port 2 Input Mode Configuration

136

P2MDOUT

0xA6

Port 2 Output Mode Configuration

136

P2SKIP

0xD6

Port 2 Skip

136

0xB0

Port 3 Latch

137

P3MDIN

0xF4

Port 3 Input Mode Configuration

137

P3MDOUT

0xA7

Port 3 Output Mode Configuration

137

PCA0CN

0xD8

PCA Control

240

PCA0CPH0

0xFC

PCA Capture 0 High

244

PCA0CPH1

0xEA

PCA Capture 1 High

244

PCA0CPH2

0xEC

PCA Capture 2 High

244

PCA0CPH3

0xEE

PCA Capture 3High

244

PCA0CPH4

0xFE

PCA Capture 4 High

244

PCA0CPL0

0xFB

PCA Capture 0 Low

243

PCA0CPL1

0xE9

PCA Capture 1 Low

243

PCA0CPL2

0xEB

PCA Capture 2 Low

243

PCA0CPL3

0xED

PCA Capture 3Low

243

PCA0CPL4

0xFD

PCA Capture 4 Low

243

PCA0CPM0

0xDA

PCA Module 0 Mode Register

242

PCA0CPM1

0xDB

PCA Module 1 Mode Register

242

Rev. 1.4

C8051F320/1
Table 9.3. Special Function Registers (Continued)
SFRs are listed in alphabetical order. All undefined SFR locations are reserved.

Address

PCA0CPM2

0xDC

PCA Module 2 Mode Register

242

PCA0CPM3

0xDD

PCA Module 3 Mode Register

242

PCA0CPM4

0xDE

PCA Module 4 Mode Register

242

PCA0H

0xFA

PCA Counter High

243

PCA0L

0xF9

PCA Counter Low

243

PCA0MD

0xD9

PCA Mode

241

PCON

0x87

Power Control

PSCTL

0x8F

Program Store R/W Control

112

PSW

0xD0

Program Status Word

REF0CN

0xD1

Voltage Reference Control

REG0CN

0xC9

Voltage Regulator Control

RSTSRC

0xEF

Reset Source Configuration/Status

104

SBUF0

0x99

UART0 Data Buffer

193

SCON0

0x98

UART0 Control

192

SMB0CF

0xC1

SMBus Configuration

175

SMB0CN

0xC0

SMBus Control

177

SMB0DAT

0xC2

SMBus Data

179

0x81

Stack Pointer

SPI0CFG

0xA1

SPI Configuration

203

SPI0CKR

0xA2

SPI Clock Rate Control

205

SPI0CN

0xF8

SPI Control

204

SPI0DAT

0xA3

SPI Data

205

TCON

0x88

Timer/Counter Control

213

TH0

0x8C

Timer/Counter 0 High

216

TH1

0x8D

Timer/Counter 1 High

216

TL0

0x8A

Timer/Counter 0 Low

216

TL1

0x8B

Timer/Counter 1 Low

216

TMOD

0x89

Timer/Counter Mode

214

TMR2CN

0xC8

Timer/Counter 2 Control

220

TMR2H

0xCD

Timer/Counter 2 High

221

TMR2L

0xCC

Timer/Counter 2 Low

221

TMR2RLH

0xCB

Timer/Counter 2 Reload High

221

Description

Rev. 1.4

Page

C8051F320/1
Table 9.3. Special Function Registers (Continued)
SFRs are listed in alphabetical order. All undefined SFR locations are reserved.

Address

Description

Page

TMR2RLL

0xCA

Timer/Counter 2 Reload Low

221

TMR3CN

0x91

Timer/Counter 3Control

225

TMR3H

0x95

Timer/Counter 3 High

226

TMR3L

0x94

Timer/Counter 3Low

226

TMR3RLH

0x93

Timer/Counter 3 Reload High

226

TMR3RLL

0x92

Timer/Counter 3 Reload Low

226

USB0ADR

0x96

USB0 Indirect Address Register

143

USB0DAT

0x97

USB0 Data Register

144

USB0XCN

0xD7

USB0 Transceiver Control

141

VDM0CN

0xFF

VDD Monitor Control

101

XBR0

0xE1

Port I/O Crossbar Control 0

131

XBR1

0xE2

Port I/O Crossbar Control 1

132

0x84–0x86, 0xAB-0xAF,
0xB4, 0xB5, 0xBF, 0xC7,
0xCE, 0xCF, 0xD2, 0xD3,
0xDF, 0xE3, 0xE5, 0xF5

Reserved

9.2.7. Register Descriptions
Following are descriptions of SFRs related to the operation of the CIP-51 System Controller. Reserved bits
should not be set to logic l. Future product versions may use these bits to implement new features in which
case the reset value of the bit will be logic 0, selecting the feature's default state. Detailed descriptions of
the remaining SFRs are included in the sections of the datasheet associated with their corresponding system function.

SFR Definition 9.1. DPL: Data Pointer Low Byte
R/W

R/W

Reset Value

00000000
Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

0x82
Bits7–0: DPL: Data Pointer Low.
The DPL register is the low byte of the 16-bit DPTR. DPTR is used to access indirectly
addressed memory.

Rev. 1.4

C8051F320/1
SFR Definition 9.2. DPH: Data Pointer High Byte
R/W

R/W

Reset Value

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

00000000
0x83
Bits7–0: DPH: Data Pointer High.
The DPH register is the high byte of the 16-bit DPTR. DPTR is used to access indirectly
addressed memory.

SFR Definition 9.3. SP: Stack Pointer
R/W

R/W

Reset Value

00000111
Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

0x81
Bits7–0: SP: Stack Pointer.
The Stack Pointer holds the location of the top of the stack. The stack pointer is incremented
before every PUSH operation. The SP register defaults to 0x07 after reset.

Rev. 1.4

C8051F320/1
SFR Definition 9.4. PSW: Program Status Word
R/W

R/W

CY
Bit7

R/W

RS1

RS0

Bit6

Bit5

Bit4

Bit3

PARITY

00000000

Bit2

Bit1

Bit0

SFR Address:

(bit addressable)

Reset Value

0xD0

Bit7:

CY: Carry Flag.
This bit is set when the last arithmetic operation resulted in a carry (addition) or a borrow
(subtraction). It is cleared to logic 0 by all other arithmetic operations.
Bit6:
AC: Auxiliary Carry Flag
This bit is set when the last arithmetic operation resulted in a carry into (addition) or a borrow
from (subtraction) the high order nibble. It is cleared to logic 0 by all other arithmetic operations.
Bit5:
F0: User Flag 0.
This is a bit-addressable, general purpose flag for use under software control.
Bits4–3: RS1–RS0: Register Bank Select.
These bits select which register bank is used during register accesses.
RS1
0
0
1
1
Bit2:

Bit1:
Bit0:

RS0
0
1
0
1

Address
0x00–0x07
0x08–0x0F
0x10–0x17
0x18–0x1F

OV: Overflow Flag.
This bit is set to 1 under the following circumstances:
• An ADD, ADDC, or SUBB instruction causes a sign-change overflow.
• A MUL instruction results in an overflow (result is greater than 255).
• A DIV instruction causes a divide-by-zero condition.
The OV bit is cleared to 0 by the ADD, ADDC, SUBB, MUL, and DIV instructions in all other
cases.
F1: User Flag 1.
This is a bit-addressable, general purpose flag for use under software control.
PARITY: Parity Flag.
This bit is set to logic 1 if the sum of the eight bits in the accumulator is odd and cleared if the
sum is even.

Rev. 1.4

C8051F320/1
SFR Definition 9.5. ACC: Accumulator
R/W

R/W

ACC.7

ACC.6

ACC.5

ACC.4

ACC.3

ACC.2

ACC.1

ACC.0

00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

(bit addressable)

Reset Value

0xE0

Bits7–0: ACC: Accumulator.
This register is the accumulator for arithmetic operations.

SFR Definition 9.6. B: B Register
R/W

R/W

Reset Value

B.7

B.6

B.5

B.4

B.3

B.2

B.1

B.0

00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

(bit addressable)

Bits7–0: B: B Register.
This register serves as a second accumulator for certain arithmetic operations.

Rev. 1.4

0xF0

C8051F320/1
9.3.

Interrupt Handler

The CIP-51 includes an extended interrupt system supporting a total of 16 interrupt sources with two priority levels. The allocation of interrupt sources between on-chip peripherals and external inputs pins varies
according to the specific version of the device. Each interrupt source has one or more associated interruptpending flag(s) located in an SFR. When a peripheral or external source meets a valid interrupt condition,
the associated interrupt-pending flag is set to logic 1.
If interrupts are enabled for the source, an interrupt request is generated when the interrupt-pending flag is
set. As soon as execution of the current instruction is complete, the CPU generates an LCALL to a predetermined address to begin execution of an interrupt service routine (ISR). Each ISR must end with an RETI
instruction, which returns program execution to the next instruction that would have been executed if the
interrupt request had not occurred. If interrupts are not enabled, the interrupt-pending flag is ignored by the
hardware and program execution continues as normal. (The interrupt-pending flag is set to logic 1 regardless of the interrupt's enable/disable state.)
Each interrupt source can be individually enabled or disabled through the use of an associated interrupt
enable bit in an SFR (IE-EIE2). However, interrupts must first be globally enabled by setting the EA bit
(IE.7) to logic 1 before the individual interrupt enables are recognized. Setting the EA bit to logic 0 disables
all interrupt sources regardless of the individual interrupt-enable settings.
Note: any instruction which clears the EA bit should be immediately followed by an instruction which has
two or more opcode bytes. For example:
// in 'C':
EA = 0;
EA = 0;

// clear EA bit
// ... followed by another 2-byte opcode

; in assembly:
CLR EA
CLR EA

; clear EA bit
; ... followed by another 2-byte opcode

If an interrupt is posted during the execution phase of a "CLR EA" opcode (or any instruction which clears
the EA bit), and the instruction is followed by a single-cycle instruction, the interrupt may be taken. If the
EA bit is read inside the interrupt service routine, it will return a '0'. When the "CLR EA" opcode is followed
by a multi-cycle instruction, the interrupt will not be taken.
Some interrupt-pending flags are automatically cleared by the hardware when the CPU vectors to the ISR.
However, most are not cleared by the hardware and must be cleared by software before returning from the
ISR. If an interrupt-pending flag remains set after the CPU completes the return-from-interrupt (RETI)
instruction, a new interrupt request will be generated immediately and the CPU will re-enter the ISR after
the completion of the next instruction.

9.3.1. MCU Interrupt Sources and Vectors
The MCU supports 16 interrupt sources. Software can simulate an interrupt by setting any interrupt-pending flag to logic 1. If interrupts are enabled for the flag, an interrupt request will be generated and the CPU
will vector to the ISR address associated with the interrupt-pending flag. MCU interrupt sources, associated vector addresses, priority order and control bits are summarized in Table 9.4 on page 89. Refer to the
datasheet section associated with a particular on-chip peripheral for information regarding valid interrupt
conditions for the peripheral and the behavior of its interrupt-pending flag(s).

Rev. 1.4

C8051F320/1
9.3.2. External Interrupts
The /INT0 and /INT1 external interrupt sources are configurable as active high or low, edge or level sensitive. The IN0PL (/INT0 Polarity) and IN1PL (/INT1 Polarity) bits in the IT01CF register select active high or
active low; the IT0 and IT1 bits in TCON (Section “19.1. Timer 0 and Timer 1” on page 209) select level or
edge sensitive. The table below lists the possible configurations.
IT0
1

IN0PL
0

/INT0 Interrupt
Active low, edge sensitive

IT1
1

IN1PL
0

Active high, edge sensitive

0
0

0
1

Active low, level sensitive
Active high, level sensitive

0
0

0
1

/INT1 Interrupt
Active low, edge sensitive
Active high, edge sensitive
Active low, level sensitive
Active high, level sensitive

/INT0 and /INT1 are assigned to Port pins as defined in the IT01CF register (see Figure 9.13). Note that
/INT0 and /INT0 Port pin assignments are independent of any Crossbar assignments. /INT0 and /INT1 will
monitor their assigned Port pins without disturbing the peripheral that was assigned the Port pin via the
Crossbar. To assign a Port pin only to /INT0 and/or /INT1, configure the Crossbar to skip the selected
pin(s). This is accomplished by setting the associated bit in register XBR0 (see Section “14.1. Priority
Crossbar Decoder” on page 128 for complete details on configuring the Crossbar).
IE0 (TCON.1) and IE1 (TCON.3) serve as the interrupt-pending flags for the /INT0 and /INT1 external
interrupts, respectively. If an /INT0 or /INT1 external interrupt is configured as edge-sensitive, the corresponding interrupt-pending flag is automatically cleared by the hardware when the CPU vectors to the ISR.
When configured as level sensitive, the interrupt-pending flag remains logic 1 while the input is active as
defined by the corresponding polarity bit (IN0PL or IN1PL); the flag remains logic 0 while the input is inactive. The external interrupt source must hold the input active until the interrupt request is recognized. It
must then deactivate the interrupt request before execution of the ISR completes or another interrupt
request will be generated.

9.3.3. Interrupt Priorities
Each interrupt source can be individually programmed to one of two priority levels: low or high. A low priority interrupt service routine can be preempted by a high priority interrupt. A high priority interrupt cannot be
preempted. Each interrupt has an associated interrupt priority bit in an SFR (IP or EIP2) used to configure
its priority level. Low priority is the default. If two interrupts are recognized simultaneously, the interrupt with
the higher priority is serviced first. If both interrupts have the same priority level, a fixed priority order is
used to arbitrate, given in Table 9.4.

Rev. 1.4

C8051F320/1
9.3.4. Interrupt Latency
Interrupt response time depends on the state of the CPU when the interrupt occurs. Pending interrupts are
sampled and priority decoded each system clock cycle. Therefore, the fastest possible response time is 5
system clock cycles: 1 clock cycle to detect the interrupt and 4 clock cycles to complete the LCALL to the
ISR. If an interrupt is pending when a RETI is executed, a single instruction is executed before an LCALL
is made to service the pending interrupt. Therefore, the maximum response time for an interrupt (when no
other interrupt is currently being serviced or the new interrupt is of greater priority) occurs when the CPU is
performing an RETI instruction followed by a DIV as the next instruction. In this case, the response time is
18 system clock cycles: 1 clock cycle to detect the interrupt, 5 clock cycles to execute the RETI, 8 clock
cycles to complete the DIV instruction and 4 clock cycles to execute the LCALL to the ISR. If the CPU is
executing an ISR for an interrupt with equal or higher priority, the new interrupt will not be serviced until the
current ISR completes, including the RETI and following instruction.
Note that the CPU is stalled during Flash write/erase operations and USB FIFO MOVX accesses (see Section “12.2. Accessing USB FIFO Space” on page 114). Interrupt service latency will be increased for interrupts occuring while the CPU is stalled. The latency for these situations will be determined by the standard
interrupt service procedure (as described above) and the amount of time the CPU is stalled.

Bit addressable?

Cleared by HW?

Table 9.4. Interrupt Summary

Enable
Flag

N/A

Always
Enabled

IE0 (TCON.1)

EX0 (IE.0)

TF0 (TCON.5)

ET0 (IE.1)

0x0013

IE1 (TCON.3)

EX1 (IE.2)

0x001B

ET1 (IE.3)

UART0

0x0023

ES0 (IE.4)

Timer 2 Overflow

0x002B

ET2 (IE.5) PT2 (IP.5)

SPI0

0x0033

TF1 (TCON.7)
RI0 (SCON0.0)
TI0 (SCON0.1)
TF2H (TMR2CN.7)
TF2L (TMR2CN.6)
SPIF (SPI0CN.7)
WCOL (SPI0CN.6)
MODF (SPI0CN.5)
RXOVRN
(SPI0CN.4)

ESPI0
(IE.6)

PSPI0
(IP.6)

SMB0

0x003B

SI (SMB0CN.0)

USB0

0x0043

Special

ADC0 Window
Compare

0x004B

AD0WINT
(ADC0CN.3)

ESMB0
(EIE1.0)
EUSB0
(EIE1.1)
EWADC0
(EIE1.2)

PSMB0
(EIP1.0)
PUSB0
(EIP1.1)
PWADC0
(EIP1.2)

Interrupt Source

Interrupt
Vector

Priority
Order

Reset

0x0000

Top

0x0003

0x000B

External Interrupt 0
(/INT0)
Timer 0 Overflow
External Interrupt 1
(/INT1)
Timer 1 Overflow

Pending Flag

None

Rev. 1.4

Priority
Control

Always
Highest
PX0
(IP.0)
PT0 (IP.1)
PX1
(IP.2)
PT1 (IP.3)
PS0
(IP.4)

C8051F320/1

Priority
Order

0x0053

0x005B

Comparator0

0x0063

Comparator1

0x006B

Timer 3 Overflow

0x0073

VBUS Level

0x007B

ADC0 Conversion
Complete
Programmable
Counter Array

Pending Flag

AD0INT (ADC0CN.5)

CF (PCA0CN.7)
CCFn (PCA0CN.n)
CP0FIF (CPT0CN.4)
CP0RIF (CPT0CN.5)
CP1FIF (CPT1CN.4)
CP1RIF (CPT1CN.5)
TF3H (TMR3CN.7)
TF3L (TMR3CN.6)
N/A

Y
N
N
N
N/A

Cleared by HW?

Interrupt
Vector

Interrupt Source

Bit addressable?

Table 9.4. Interrupt Summary (Continued)

Enable
Flag

EADC0
(EIE1.3)
EPCA0
N
(EIE1.4)
ECP0
N
(EIE1.5)
ECP1
N
(EIE1.6)
ET3
N
(EIE1.7)
EVBUS
N/A
(EIE2.0)
N

Priority
Control

PADC0
(EIP1.3)
PPCA0
(EIP1.4)
PCP0
(EIP1.5)
PCP1
(EIP1.6)
PT3
(EIP1.7)
PVBUS
(EIP2.0)

9.3.5. Interrupt Register Descriptions
The SFRs used to enable the interrupt sources and set their priority level are described below. Refer to the
datasheet section associated with a particular on-chip peripheral for information regarding valid interrupt
conditions for the peripheral and the behavior of its interrupt-pending flag(s).

Rev. 1.4

C8051F320/1
SFR Definition 9.7. IE: Interrupt Enable
R/W

R/W

ESPI0

ET2

ES0

ET1

EX1

ET0

EX0

00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

(bit addressable)

Bit7:

Bit6:

Bit5:

Bit4:

Bit3:

Bit2:

Bit1:

Bit0:

Reset Value

0xA8

EA: Enable All Interrupts.
This bit globally enables/disables all interrupts. It overrides the individual interrupt mask settings.
0: Disable all interrupt sources.
1: Enable each interrupt according to its individual mask setting.
ESPI0: Enable Serial Peripheral Interface (SPI0) Interrupt.
This bit sets the masking of the SPI0 interrupts.
0: Disable all SPI0 interrupts.
1: Enable interrupt requests generated by SPI0.
ET2: Enable Timer 2 Interrupt.
This bit sets the masking of the Timer 2 interrupt.
0: Disable Timer 2 interrupt.
1: Enable interrupt requests generated by the TF2L or TF2H flags.
ES0: Enable UART0 Interrupt.
This bit sets the masking of the UART0 interrupt.
0: Disable UART0 interrupt.
1: Enable UART0 interrupt.
ET1: Enable Timer 1 Interrupt.
This bit sets the masking of the Timer 1 interrupt.
0: Disable all Timer 1 interrupt.
1: Enable interrupt requests generated by the TF1 flag.
EX1: Enable External Interrupt 1.
This bit sets the masking of External Interrupt 1.
0: Disable external interrupt 1.
1: Enable interrupt requests generated by the /INT1 input.
ET0: Enable Timer 0 Interrupt.
This bit sets the masking of the Timer 0 interrupt.
0: Disable all Timer 0 interrupt.
1: Enable interrupt requests generated by the TF0 flag.
EX0: Enable External Interrupt 0.
This bit sets the masking of External Interrupt 0.
0: Disable external interrupt 0.
1: Enable interrupt requests generated by the /INT0 input.

Rev. 1.4

C8051F320/1
SFR Definition 9.8. IP: Interrupt Priority
R/W

R/W

PSPI0

PT2

PS0

PT1

PX1

PT0

PX0

10000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

(bit addressable)

Bit7:
Bit6:

Bit5:

Bit4:

Bit3:

Bit2:

Bit1:

Bit0:

UNUSED. Read = 1b, Write = don't care.
PSPI0: Serial Peripheral Interface (SPI0) Interrupt Priority Control.
This bit sets the priority of the SPI0 interrupt.
0: SPI0 interrupt set to low priority level.
1: SPI0 interrupt set to high priority level.
PT2: Timer 2 Interrupt Priority Control.
This bit sets the priority of the Timer 2 interrupt.
0: Timer 2 interrupt set to low priority level.
1: Timer 2 interrupts set to high priority level.
PS0: UART0 Interrupt Priority Control.
This bit sets the priority of the UART0 interrupt.
0: UART0 interrupt set to low priority level.
1: UART0 interrupts set to high priority level.
PT1: Timer 1 Interrupt Priority Control.
This bit sets the priority of the Timer 1 interrupt.
0: Timer 1 interrupt set to low priority level.
1: Timer 1 interrupts set to high priority level.
PX1: External Interrupt 1 Priority Control.
This bit sets the priority of the External Interrupt 1 interrupt.
0: External Interrupt 1 set to low priority level.
1: External Interrupt 1 set to high priority level.
PT0: Timer 0 Interrupt Priority Control.
This bit sets the priority of the Timer 0 interrupt.
0: Timer 0 interrupt set to low priority level.
1: Timer 0 interrupt set to high priority level.
PX0: External Interrupt 0 Priority Control.
This bit sets the priority of the External Interrupt 0 interrupt.
0: External Interrupt 0 set to low priority level.
1: External Interrupt 0 set to high priority level.

Rev. 1.4

Reset Value

0xB8

C8051F320/1
SFR Definition 9.9. EIE1: Extended Interrupt Enable 1
R/W

R/W

Reset Value

ET3

ECP1

ECP0

EPCA0

EADC0

EWADC0

EUSB0

ESMB0

00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

0xE6
Bit7:

Bit6:

Bit5:

Bit4:

Bit3:

Bit2:

Bit1:

Bit0:

ET3: Enable Timer 3 Interrupt.
This bit sets the masking of the Timer 3 interrupt.
0: Disable Timer 3 interrupts.
1: Enable interrupt requests generated by the TF3L or TF3H flags.
ECP1: Enable Comparator1 (CP1) Interrupt.
This bit sets the masking of the CP1 interrupt.
0: Disable CP1 interrupts.
1: Enable interrupt requests generated by the CP1RIF or CP1FIF flags.
ECP0: Enable Comparator0 (CP0) Interrupt.
This bit sets the masking of the CP0 interrupt.
0: Disable CP0 interrupts.
1: Enable interrupt requests generated by the CP0RIF or CP0FIF flags.
EPCA0: Enable Programmable Counter Array (PCA0) Interrupt.
This bit sets the masking of the PCA0 interrupts.
0: Disable all PCA0 interrupts.
1: Enable interrupt requests generated by PCA0.
EADC0: Enable ADC0 Conversion Complete Interrupt.
This bit sets the masking of the ADC0 Conversion Complete interrupt.
0: Disable ADC0 Conversion Complete interrupt.
1: Enable interrupt requests generated by the AD0INT flag.
EWADC0: Enable Window Comparison ADC0 Interrupt.
This bit sets the masking of ADC0 Window Comparison interrupt.
0: Disable ADC0 Window Comparison interrupt.
1: Enable interrupt requests generated by ADC0 Window Compare flag (AD0WINT).
EUSB0: Enable USB0 Interrupt.
This bit sets the masking of the USB0 interrupt.
0: Disable all USB0 interrupts.
1: Enable interrupt requests generated by USB0.
ESMB0: Enable SMBus (SMB0) Interrupt.
This bit sets the masking of the SMB0 interrupt.
0: Disable all SMB0 interrupts.
1: Enable interrupt requests generated by SMB0.

Rev. 1.4

C8051F320/1
SFR Definition 9.10. EIP1: Extended Interrupt Priority 1
R/W

R/W

Reset Value

PT3

PCP1

PCP0

PPCA0

PADC0

PWADC0

PUSB0

PSMB0

00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

0xF6
Bit7:

Bit6:

Bit5:

Bit4:

Bit3:

Bit2:

Bit1:

Bit0:

PT3: Timer 3 Interrupt Priority Control.
This bit sets the priority of the Timer 3 interrupt.
0: Timer 3 interrupts set to low priority level.
1: Timer 3 interrupts set to high priority level.
PCP1: Comparator1 (CP1) Interrupt Priority Control.
This bit sets the priority of the CP1 interrupt.
0: CP1 interrupt set to low priority level.
1: CP1 interrupt set to high priority level.
PCP0: Comparator0 (CP0) Interrupt Priority Control.
This bit sets the priority of the CP0 interrupt.
0: CP0 interrupt set to low priority level.
1: CP0 interrupt set to high priority level.
PPCA0: Programmable Counter Array (PCA0) Interrupt Priority Control.
This bit sets the priority of the PCA0 interrupt.
0: PCA0 interrupt set to low priority level.
1: PCA0 interrupt set to high priority level.
PADC0 ADC0 Conversion Complete Interrupt Priority Control.
This bit sets the priority of the ADC0 Conversion Complete interrupt.
0: ADC0 Conversion Complete interrupt set to low priority level.
1: ADC0 Conversion Complete interrupt set to high priority level.
PWADC0: ADC0 Window Comparator Interrupt Priority Control.
This bit sets the priority of the ADC0 Window interrupt.
0: ADC0 Window interrupt set to low priority level.
1: ADC0 Window interrupt set to high priority level.
PUSB0: USB0 Interrupt Priority Control.
This bit sets the priority of the USB0 interrupt.
0: USB0 interrupt set to low priority level.
1: USB0 interrupt set to high priority level.
PSMB0: SMBus (SMB0) Interrupt Priority Control.
This bit sets the priority of the SMB0 interrupt.
0: SMB0 interrupt set to low priority level.
1: SMB0 interrupt set to high priority level.

Rev. 1.4

C8051F320/1
SFR Definition 9.11. EIE2: Extended Interrupt Enable 2
R/W

R/W

Reset Value

EVBUS

00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

0xE7
Bits7–1: UNUSED. Read = 0000000b. Write = don’t care.
Bit0:
EVBUS: Enable VBUS Level Interrupt.
This bit sets the masking of the VBUS interrupt.
0: Disable all VBUS interrupts.
1: Enable interrupt requests generated by VBUS level sense.

SFR Definition 9.12. EIP2: Extended Interrupt Priority 2
R/W

R/W

Reset Value

PVBUS

00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

0xF7
Bits7–1: UNUSED. Read = 0000000b. Write = don’t care.
Bit0:
PVBUS: VBUS Level Interrupt Priority Control.
This bit sets the priority of the VBUS interrupt.
0: VBUS interrupt set to low priority level.
1: VBUS interrupt set to high priority level.

Rev. 1.4

C8051F320/1
SFR Definition 9.13. IT01CF: INT0/INT1 Configuration
R/W

R/W

Reset Value

IN1PL

IN1SL2

IN1SL1

IN1SL0

IN0PL

IN0SL2

IN0SL1

IN0SL0

00000001

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

0xE4
Note: Refer to Figure 19.1 for INT0/1 edge- or level-sensitive interrupt selection.
Bit7:

IN1PL: /INT1 Polarity
0: /INT1 input is active low.
1: /INT1 input is active high.
Bits6–4: IN1SL2–0: /INT1 Port Pin Selection Bits
These bits select which Port pin is assigned to /INT1. Note that this pin assignment is independent of the Crossbar; /INT1 will monitor the assigned Port pin without disturbing the
peripheral that has been assigned the Port pin via the Crossbar. The Crossbar will not
assign the Port pin to a peripheral if it is configured to skip the selected pin (accomplished by
setting to ‘1’ the corresponding bit in register P0SKIP).
IN1SL2-0
000
001
010
011
100
101
110
111

/INT1 Port Pin
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7

Bit3:

IN0PL: /INT0 Polarity
0: /INT0 interrupt is active low.
1: /INT0 interrupt is active high.
Bits2–0: INT0SL2–0: /INT0 Port Pin Selection Bits
These bits select which Port pin is assigned to /INT0. Note that this pin assignment is independent of the Crossbar. /INT0 will monitor the assigned Port pin without disturbing the
peripheral that has been assigned the Port pin via the Crossbar. The Crossbar will not
assign the Port pin to a peripheral if it is configured to skip the selected pin (accomplished by
setting to ‘1’ the corresponding bit in register P0SKIP).
IN0SL2-0
000
001
010
011
100
101
110
111

/INT0 Port Pin
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7

Rev. 1.4

C8051F320/1
9.4.

Power Management Modes

The CIP-51 core has two software programmable power management modes: Idle and Stop. Idle mode
halts the CPU while leaving the peripherals and clocks active. In Stop mode, the CPU is halted, all interrupts, are inactive, and the internal oscillator is stopped (analog peripherals remain in their selected states;
the external oscillator is not affected). Since clocks are running in Idle mode, power consumption is dependent upon the system clock frequency and the number of peripherals left in active mode before entering
Idle. Stop mode consumes the least power. Figure 1.15 describes the Power Control Register (PCON)
used to control the CIP-51's power management modes.
Although the CIP-51 has Idle and Stop modes built in (as with any standard 8051 architecture), power
management of the entire MCU is better accomplished through system clock and individual peripheral
management. Each analog peripheral can be disabled when not in use and placed in low power mode.
Digital peripherals, such as timers or serial buses, draw little power when they are not in use. Turning off
the oscillators lowers power consumption considerably; however a reset is required to restart the MCU.
The internal oscillator can be placed in Suspend mode (see Section “13. Oscillators” on page 116). In Suspend mode, the internal oscillator is stopped until a non-idle USB event is detected, or the VBUS input signal matches the polarity selected by the VBPOL bit in register REG0CN (Figure 8.1 on Page 70).

9.4.1. Idle Mode
Setting the Idle Mode Select bit (PCON.0) causes the CIP-51 to halt the CPU and enter Idle mode as soon
as the instruction that sets the bit completes execution. All internal registers and memory maintain their
original data. All analog and digital peripherals can remain active during Idle mode.
Idle mode is terminated when an enabled interrupt is asserted or a reset occurs. The assertion of an
enabled interrupt will cause the Idle Mode Selection bit (PCON.0) to be cleared and the CPU to resume
operation. The pending interrupt will be serviced and the next instruction to be executed after the return
from interrupt (RETI) will be the instruction immediately following the one that set the Idle Mode Select bit.
If Idle mode is terminated by an internal or external reset, the CIP-51 performs a normal reset sequence
and begins program execution at address 0x0000.
If enabled, the Watchdog Timer (WDT) will eventually cause an internal watchdog reset and thereby terminate the Idle mode. This feature protects the system from an unintended permanent shutdown in the event
of an inadvertent write to the PCON register. If this behavior is not desired, the WDT may be disabled by
software prior to entering the Idle mode if the WDT was initially configured to allow this operation. This provides the opportunity for additional power savings, allowing the system to remain in the Idle mode indefinitely, waiting for an external stimulus to wake up the system. Refer to Section “10.6. PCA Watchdog Timer
Reset” on page 102 for more information on the use and configuration of the WDT.

9.4.2. Stop Mode
Setting the Stop Mode Select bit (PCON.1) causes the CIP-51 to enter Stop mode as soon as the instruction that sets the bit completes execution. In Stop mode the internal oscillator, CPU, and all digital peripherals are stopped; the state of the external oscillator circuit is not affected. Each analog peripheral (including
the external oscillator circuit) may be shut down individually prior to entering Stop Mode. Stop mode can
only be terminated by an internal or external reset. On reset, the CIP-51 performs the normal reset
sequence and begins program execution at address 0x0000.
If enabled, the Missing Clock Detector will cause an internal reset and thereby terminate the Stop mode.
The Missing Clock Detector should be disabled if the CPU is to be put to in STOP mode for longer than the
MCD timeout of 100 µsec.

Rev. 1.4

C8051F320/1
SFR Definition 9.14. PCON: Power Control
R/W

R/W

Reset Value

GF5

GF4

GF3

GF2

GF1

GF0

STOP

IDLE

00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

0x87
Bits7–2: GF5–GF0: General Purpose Flags 5–0.
These are general purpose flags for use under software control.
Bit1:
STOP: Stop Mode Select.
Setting this bit will place the CIP-51 in Stop mode. This bit will always be read as 0.
1: CPU goes into Stop mode (internal oscillator stopped).
Bit0:
IDLE: Idle Mode Select.
Setting this bit will place the CIP-51 in Idle mode. This bit will always be read as 0.
1: CPU goes into Idle mode. (Shuts off clock to CPU, but clock to Timers, Interrupts, Serial
Ports, and Analog Peripherals are still active.)

Rev. 1.4

C8051F320/1
10. Reset Sources
Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this
reset state, the following occur:
•
•
•
•

CIP-51 halts program execution
Special Function Registers (SFRs) are initialized to their defined reset values
External Port pins are forced to a known state
Interrupts and timers are disabled.

All SFRs are reset to the predefined values noted in the SFR detailed descriptions. The contents of internal
data memory are unaffected during a reset; any previously stored data is preserved. However, since the
stack pointer SFR is reset, the stack is effectively lost even though the data on the stack is not altered.
The Port I/O latches are reset to 0xFF (all logic ones) in open-drain mode. Weak pull-ups are enabled
during and after the reset. For VDD Monitor and Power-On Resets, the /RST pin is driven low until the
device exits the reset state.
On exit from the reset state, the program counter (PC) is reset, and the system clock defaults to the internal oscillator. Refer to Section “13. Oscillators” on page 116 for information on selecting and configuring
the system clock source. The Watchdog Timer is enabled with the system clock divided by 12 as its clock
source (Section “20.3. Watchdog Timer Mode” on page 236 details the use of the Watchdog Timer). Program execution begins at location 0x0000.

VDD

Supply
Monitor
+
-

Enable

Power On
Reset

Comparator 0

Px.x
Px.x

(wired-OR)

Reset
Funnel

PCA
WDT

Software Reset (SWRSF)

Errant
FLASH
Operation

XTAL2

External
Oscillator
Drive

MCD
Enable

Internal
Oscillator

System
Clock

WDT
Enable

CIP-51
Microcontroller
Core

Enable

XTAL1

/RST

C0RSEF

Missing
Clock
Detector
(oneshot)

Clock
Multiplier

'0'

+
-

USB
Controller

VBUS
Transition

System Reset

Clock Select
Extended Interrupt
Handler

Figure 10.1. Reset Sources

Rev. 1.4

C8051F320/1
10.1. Power-On Reset
During power-up, the device is held in a reset state and the /RST pin is driven low until VDD settles above
VRST. A Power-On Reset delay (TPORDelay) occurs before the device is released from reset; this delay is
typically less than 0.3 ms. Figure 10.2. plots the power-on and VDD monitor reset timing.
On exit from a power-on reset, the PORSF flag (RSTSRC.1) is set by hardware to logic 1. When PORSF is
set, all of the other reset flags in the RSTSRC Register are indeterminate (PORSF is cleared by all other
resets). Since all resets cause program execution to begin at the same location (0x0000) software can
read the PORSF flag to determine if a power-up was the cause of reset. The content of internal data memory should be assumed to be undefined after a power-on reset. The VDD monitor is enabled following a
power-on reset.

volts

Software can force a power-on reset by writing ‘1’ to the PINRSF bit in register RSTSRC.

VDD

2.70
2.4

VRST

VD
D

2.0

1.0

Logic HIGH

Logic LOW

/RST

TPORDelay
VDD
Monitor
Reset

Power-On
Reset

Figure 10.2. Power-On and VDD Monitor Reset Timing

100

Rev. 1.4

C8051F320/1
10.2. Power-Fail Reset / VDD Monitor
When a power-down transition or power irregularity causes VDD to drop below VRST, the power supply
monitor will drive the /RST pin low and hold the CIP-51 in a reset state (see Figure 10.2). When VDD
returns to a level above VRST, the CIP-51 will be released from the reset state. Note that even though internal data memory contents are not altered by the power-fail reset, it is impossible to determine if VDD
dropped below the level required for data retention. If the PORSF flag reads ‘1’, the data may no longer be
valid. The VDD monitor is enabled after power-on resets; however its defined state (enabled/disabled) is
not altered by any other reset source. For example, if the VDD monitor is enabled and a software reset is
performed, the VDD monitor will still be enabled after the reset.
Important Note: The VDD monitor must be enabled before it is selected as a reset source. Selecting the
VDD monitor as a reset source before it is enabled and stabilized will cause a system reset. The procedure
for configuring the VDD monitor as a reset source is shown below:
Step 1. Enable the VDD monitor (VDM0CN.7 = ‘1’).
Step 2. Wait for the VDD monitor to stabilize (see Table 10.1 for the VDD Monitor turn-on time).
Step 3. Select the VDD monitor as a reset source (RSTSRC.1 = ‘1’).
See Figure 10.2 for VDD monitor timing. See Table 10.1 for complete electrical characteristics of the VDD
monitor.

SFR Definition 10.1. VDM0CN: VDD Monitor Control
R/W

VDMEN VDDSTAT Reserved Reserved Reserved Reserved Reserved Reserved
Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

Reset Value

Variable
SFR Address:

0xFF
Bit7:

VDMEN: VDD Monitor Enable.
This bit turns the VDD monitor circuit on/off. The VDD Monitor cannot generate system
resets until it is also selected as a reset source in register RSTSRC (Figure 10.2). The VDD
Monitor must be allowed to stabilize before it is selected as a reset source. Selecting the
VDD monitor as a reset source before it has stabilized will generate a system reset.
See Table 10.1 for the minimum VDD Monitor turn-on time. The VDD Monitor is enabled following all POR resets.
0: VDD Monitor Disabled.
1: VDD Monitor Enabled.
Bit6:
VDDSTAT: VDD Status.
This bit indicates the current power supply status (VDD Monitor output).
0: VDD is at or below the VDD monitor threshold.
1: VDD is above the VDD monitor threshold.
Bits5–0: Reserved. Read = Variable. Write = don’t care.

Rev. 1.4

101

C8051F320/1
10.3. External Reset
The external /RST pin provides a means for external circuitry to force the device into a reset state. Asserting an active-low signal on the /RST pin generates a reset; an external pull-up and/or decoupling of the
/RST pin may be necessary to avoid erroneous noise-induced resets. See Table 10.1 for complete /RST
pin specifications. The PINRSF flag (RSTSRC.0) is set on exit from an external reset.

10.4. Missing Clock Detector Reset
The Missing Clock Detector (MCD) is a one-shot circuit that is triggered by the system clock. If more than
100 µs pass between rising edges on the system clock, the one-shot will time out and generate a reset.
After a MCD reset, the MCDRSF flag (RSTSRC.2) will read ‘1’, signifying the MCD as the reset source;
otherwise, this bit reads ‘0’. Writing a ‘1’ to the MCDRSF bit enables the Missing Clock Detector; writing a
‘0’ disables it. The state of the /RST pin is unaffected by this reset.

10.5. Comparator0 Reset
Comparator0 can be configured as a reset source by writing a ‘1’ to the C0RSEF flag (RSTSRC.5). Comparator0 should be enabled and allowed to settle prior to writing to C0RSEF to prevent any turn-on chatter
on the output from generating an unwanted reset. The Comparator0 reset is active-low: if the non-inverting
input voltage (on CP0+) is less than the inverting input voltage (on CP0-), a system reset is generated.
After a Comparator0 reset, the C0RSEF flag (RSTSRC.5) will read ‘1’ signifying Comparator0 as the reset
source; otherwise, this bit reads ‘0’. The state of the /RST pin is unaffected by this reset.
Note: When Comparator0 is not enabled but is enabled as a reset source, a reset will not be generated.

10.6. PCA Watchdog Timer Reset
The programmable Watchdog Timer (WDT) function of the Programmable Counter Array (PCA) can be
used to prevent software from running out of control during a system malfunction. The PCA WDT function
can be enabled or disabled by software as described in Section “20.3. Watchdog Timer Mode” on
page 236; the WDT is enabled and clocked by SYSCLK / 12 following any reset. If a system malfunction
prevents user software from updating the WDT, a reset is generated and the WDTRSF bit (RSTSRC.5) is
set to ‘1’. The state of the /RST pin is unaffected by this reset.

10.7. Flash Error Reset
If a Flash read/write/erase or program read targets an illegal address, a system reset is generated. This
may occur due to any of the following:
•
•
•
•

A Flash write or erase is attempted above user code space. This occurs when PSWE is set to ‘1’ and a
MOVX write operation is attempted above address 0x3DFF.
A Flash read is attempted above user code space. This occurs when a MOVC operation is attempted
above address 0x3DFF.
A Program read is attempted above user code space. This occurs when user code attempts to branch
to an address above 0x3DFF.
A Flash read, write or erase attempt is restricted due to a Flash security setting (see Section
“11.3. Security Options” on page 108).

The FERROR bit (RSTSRC.6) is set following a Flash error reset. The state of the /RST pin is unaffected
by this reset.

102

Rev. 1.4

C8051F320/1
10.8. Software Reset
Software may force a reset by writing a ‘1’ to the SWRSF bit (RSTSRC.4). The SWRSF bit will read ‘1’ following a software forced reset. The state of the /RST pin is unaffected by this reset.

10.9. USB Reset
Writing ‘1’ to the USBRSF bit in register RSTSRC selects USB0 as a reset source. With USB0 selected as
a reset source, a system reset will be generated when either of the following occur:
1. RESET signaling is detected on the USB network. The USB Function Controller (USB0) must
be enabled for RESET signaling to be detected. See Section “15. Universal Serial Bus Controller (USB)” on page 139 for information on the USB Function Controller.
2. The voltage on the VBUS pin matches the polarity selected by the VBPOL bit in register
REG0CN. See Section “8. Voltage Regulator (REG0)” on page 67 for details on the VBUS
detection circuit.
The USBRSF bit will read ‘1’ following a USB reset. The state of the /RST pin is unaffected by this reset.

Rev. 1.4

103

C8051F320/1
SFR Definition 10.2. RSTSRC: Reset Source
R/W

R/W

USBRSF FERROR C0RSEF
Bit7

Bit6

Bit5

R/W

SWRSF
Bit4

R/W

WDTRSF MCDRSF
Bit3

Bit2

R/W

Reset Value

PORSF

PINRSF

Variable

Bit1

Bit0

SFR Address:

0xEF
Bit7:

Bit6:

Bit5:

Bit4:

Bit3:

Bit2:

Bit1:

Bit0:

USBRSF: USB Reset Flag
0: Read: Last reset was not a USB reset; Write: USB resets disabled.
1: Read: Last reset was a USB reset; Write: USB resets enabled.
FERROR: Flash Error Indicator.
0: Source of last reset was not a Flash read/write/erase error.
1: Source of last reset was a Flash read/write/erase error.
C0RSEF: Comparator0 Reset Enable and Flag.
0: Read: Source of last reset was not Comparator0; Write: Comparator0 is not a reset
source.
1: Read: Source of last reset was Comparator0; Write: Comparator0 is a reset source
(active-low).
SWRSF: Software Reset Force and Flag.
0: Read: Source of last reset was not a write to the SWRSF bit; Write: No Effect.
1: Read: Source of last was a write to the SWRSF bit; Write: Forces a system reset.
WDTRSF: Watchdog Timer Reset Flag.
0: Source of last reset was not a WDT timeout.
1: Source of last reset was a WDT timeout.
MCDRSF: Missing Clock Detector Flag.
0: Read: Source of last reset was not a Missing Clock Detector timeout; Write: Missing
Clock Detector disabled.
1: Read: Source of last reset was a Missing Clock Detector timeout; Write: Missing Clock
Detector enabled; triggers a reset if a missing clock condition is detected.
PORSF: Power-On / VDD Monitor Reset Flag.
This bit is set anytime a power-on reset occurs. Writing this bit selects/deselects the VDD
monitor as a reset source. Note: writing ‘1’ to this bit before the VDD monitor is enabled
and stabilized can cause a system reset. See register VDM0CN (Figure 10.1).
0: Read: Last reset was not a power-on or VDD monitor reset; Write: VDD monitor is not a
reset source.
1: Read: Last reset was a power-on or VDD monitor reset; all other reset flags indeterminate; Write: VDD monitor is a reset source.
PINRSF: HW Pin Reset Flag.
0: Source of last reset was not /RST pin.
1: Source of last reset was /RST pin.

Note: For bits that act as both reset source enables (on a write) and reset indicator flags (on a
read), read-modify-write instructions read and modify the source enable only. This applies to
bits: USBRSF, C0RSEF, SWRSF, MCDRSF, PORSF.

104

Rev. 1.4

C8051F320/1
Table 10.1. Reset Electrical Characteristics
-40°C to +85°C unless otherwise specified.
Parameter
/RST Output Low Voltage

Conditions

Min

Typ

IOL = 8.5 mA, VDD = 2.7 V to 3.6 V

/RST Input High Voltage

Units

0.6

0.7 x VDD

/RST Input Low Voltage
/RST Input Pull-Up Current

Max

0.3 x VDD
/RST = 0.0 V

VDD POR Threshold (VRST)

µA

2.40

2.55

2.70

220

500

µs

Missing Clock Detector Timeout

Time from last system clock rising
edge to reset initiation

100

Reset Time Delay

Delay between release of any
reset source and code execution
at location 0x0000

5.0

µs

Minimum /RST Low Time to
Generate a System Reset

µs

VDD Monitor Turn-on Time

100

µs

VDD Monitor Supply Current

Rev. 1.4

µA

105

C8051F320/1

106

Rev. 1.4

C8051F320/1
11. Flash Memory
On-chip, re-programmable Flash memory is included for program code and non-volatile data storage. The
Flash memory can be programmed in-system, a single byte at a time, through the C2 interface or by software using the MOVX instruction. Once cleared to logic 0, a Flash bit must be erased to set it back to logic
1. Flash bytes would typically be erased (set to 0xFF) before being reprogrammed. The write and erase
operations are automatically timed by hardware for proper execution; data polling to determine the end of
the write/erase operation is not required. Code execution is stalled during a Flash write/erase operation.
Refer to Table 11.1 for complete Flash memory electrical characteristics.

11.1. Programming The Flash Memory
The simplest means of programming the Flash memory is through the C2 interface using programming
tools provided by Silicon Labs or a third party vendor. This is the only means for programming a non-initialized device. For details on the C2 commands to program Flash memory, see Section “21. C2 Interface” on
page 245.
To ensure the integrity of Flash contents, it is strongly recommended that the on-chip VDD Monitor
be enabled in any system that includes code that writes and/or erases Flash memory from software.

11.1.1. Flash Lock and Key Functions
Flash writes and erases by user software are protected with a lock and key function. The Flash Lock and
Key Register (FLKEY) must be written with the correct key codes, in sequence, before Flash operations
may be performed. The key codes are: 0xA5, 0xF1. The timing does not matter, but the codes must be
written in order. If the key codes are written out of order, or the wrong codes are written, Flash writes and
erases will be disabled until the next system reset. Flash writes and erases will also be disabled if a Flash
write or erase is attempted before the key codes have been written properly. The Flash lock resets after
each write or erase; the key codes must be written again before a following Flash operation can be performed. The FLKEY register is detailed in Figure 11.2.

11.1.2. Flash Erase Procedure
The Flash memory can be programmed by software using the MOVX write instruction with the address and
data byte to be programmed provided as normal operands. Before writing to Flash memory using MOVX,
Flash write operations must be enabled by: (1) Writing the Flash key codes in sequence to the Flash Lock
register (FLKEY); and (2) Setting the PSWE Program Store Write Enable bit (PSCTL.0) to logic 1 (this
directs the MOVX writes to target Flash memory). The PSWE bit remains set until cleared by software.
A write to Flash memory can clear bits to logic 0 but cannot set them; only an erase operation can set bits
to logic 1 in Flash. A byte location to be programmed must be erased before a new value is written.
The Flash memory is organized in 512-byte pages. The erase operation applies to an entire page (setting
all bytes in the page to 0xFF). To erase an entire 512-byte page, perform the following steps:
Step 1.
Step 2.
Step 3.
Step 4.
Step 5.
Step 6.

Disable interrupts (recommended).
Write the first key code to FLKEY: 0xA5.
Write the second key code to FLKEY: 0xF1.
Set the PSEE bit (register PSCTL).
Set the PSWE bit (register PSCTL).
Using the MOVX instruction, write a data byte to any location within the 512-byte page to
be erased.
Step 7. Clear the PSWE bit (register PSCTL).
Step 8. Clear the PSEE bit (register PSCTI).

Rev. 1.4

106

C8051F320/1
11.1.3. Flash Write Procedure
Flash bytes are programmed by software with the following sequence:
Step 1. Disable interrupts (recommended).
Step 2. Erase the 512-byte Flash page containing the target location, as described in Section
11.1.2.
Step 3. Write the first key code to FLKEY: 0xA5.
Step 4. Write the second key code to FLKEY: 0xF1.
Step 5. Set the PSWE bit (register PSCTL).
Step 6. Clear the PSEE bit (register PSCTL).
Step 7. Using the MOVX instruction, write a single data byte to the desired location within the 512byte sector.
Step 8. Clear the PSWE bit (register PSCTL).
Steps 3-8 must be repeated for each byte to be written. After Flash writes are complete, PSWE should be
cleared so that MOVX instructions do not target program memory.

Table 11.1. Flash Electrical Characteristics
Parameter

Conditions

Min

Flash Size

C8051F320/1

16384*

Endurance

20k

Typ

Max

Units
bytes

100k

Erase/Write

Erase Cycle Time

25 MHz System Clock

Write Cycle Time

25 MHz System Clock

µs

*Note: 512 bytes at location 0x3E00 to 0x3FFF are reserved.

11.2. Non-volatile Data Storage
The Flash memory can be used for non-volatile data storage as well as program code. This allows data
such as calibration coefficients to be calculated and stored at run time. Data is written using the MOVX
write instruction and read using the MOVC instruction. Note: MOVX read instructions always target XRAM.

107

Rev. 1.4

C8051F320/1
11.3. Security Options
The CIP-51 provides security options to protect the Flash memory from inadvertent modification by software as well as to prevent the viewing of proprietary program code and constants. The Program Store
Write Enable (bit PSWE in register PSCTL) and the Program Store Erase Enable (bit PSEE in register
PSCTL) bits protect the Flash memory from accidental modification by software. PSWE must be explicitly
set to ‘1’ before software can modify the Flash memory; both PSWE and PSEE must be set to ‘1’ before
software can erase Flash memory. Additional security features prevent proprietary program code and data
constants from being read or altered across the C2 interface.
A Security Lock Byte located at the last byte of Flash user space offers protection of the Flash program
memory from access (reads, writes, or erases) by unprotected code or the C2 interface. The Flash security
mechanism allows the user to lock n 512-byte Flash pages, starting at page 0 (addresses 0x0000 to
0x01FF), where n is the 1’s compliment number represented by the Security Lock Byte. See example below.
Security Lock Byte:
1’s Compliment:
Flash pages locked:
Addresses locked:

11111101b
00000010b
2
0x0000 to 0x03FF

Important Notes About the Flash Security:
1. Clearing any bit of the Lock Byte to ‘0’ will lock the Flash page containing the Lock Byte (in
addition to the selected pages).
2. Locked pages cannot be read, written, or erased via the C2 interface.
3. Locked pages cannot be read, written, or erased by user firmware executing from unlocked
memory space.
4. User firmware executing in a locked page may read and write Flash memory in any locked or
unlocked page excluding the reserved area.
5. User firmware executing in a locked page may erase Flash memory in any locked or unlocked
page excluding the reserved area and the page containing the Lock Byte.
6. Locked pages can only be unlocked through the C2 interface with a C2 Device Erase command.
7. If a user firmware Flash access attempt is denied (per restrictions #3, #4, and #5 above), a
Flash Error system reset will be generated.
C8051F320/1
Reserved
0x3E00

Locked when any
other Flash pages are
locked

Lock Byte

0x3DFF
0x3DFE
0x3C00

Flash memory organized
in 512-byte pages

Unlocked Flash Pages
Access limit set
according to the Flash
security lock byte

0x0000

Figure 11.1. Flash Program Memory Map and Security Byte

Rev. 1.4

108

C8051F320/1
The level of Flash security depends on the Flash access method. The three Flash access methods that
can be restricted are reads, writes, and erases from the C2 debug interface, user firmware executing on
unlocked pages, and user firmware executing on locked pages. Table 11.2 summarizes the Flash security
features of the 'F320/1 devices.

Table 11.2. Flash Security Summary
Action

C2 Debug
Interface

User Firmware executing from:
an unlocked page

a locked page

Permitted

Not Permitted

FEDR

Permitted

Read or Write page containing Lock Byte
(if no pages are locked)

Permitted

Read or Write page containing Lock Byte
(if any page is locked)

Not Permitted

FEDR

Permitted

Read contents of Lock Byte
(if no pages are locked)

Permitted

Read contents of Lock Byte
(if any page is locked)

Not Permitted

FEDR

Permitted

FEDR

Only C2DE

FEDR

Lock additional pages
(change '1's to '0's in the Lock Byte)

Not Permitted

FEDR

Unlock individual pages
(change '0's to '1's in the Lock Byte)

Not Permitted

FEDR

Read, Write or Erase Reserved Area

Not Permitted

FEDR

Read, Write or Erase unlocked pages
(except page with Lock Byte)
Read, Write or Erase locked pages
(except page with Lock Byte)

Erase page containing Lock Byte
(if no pages are locked)
Erase page containing Lock Byte - Unlock all pages
(if any page is locked)

C2DE - C2 Device Erase (Erases all Flash pages including the page containing the Lock Byte)
FEDR - Not permitted; Causes Flash Error Device Reset (FERROR bit in RSTSRC is '1' after reset)
- All prohibited operations that are performed via the C2 interface are ignored (do not cause device reset).
- Locking any Flash page also locks the page containing the Lock Byte.
- Once written to, the Lock Byte cannot be modified except by performing a C2 Device Erase.
- If user code writes to the Lock Byte, the Lock does not take effect until the next device reset.

109

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C8051F320/1
11.4. Flash Write and Erase Guidelines
Any system which contains routines which write or erase Flash memory from software involves some risk
that the write or erase routines will execute unintentionally if the CPU is operating outside its specified
operating range of VDD, system clock frequency, or temperature. This accidental execution of Flash modifying code can result in alteration of Flash memory contents causing a system failure that is only recoverable by re-Flashing the code in the device.
To help prevent the accidental modification of Flash by firmware, the VDD Monitor must be enabled and
enabled as a reset source on C8051F32x devices for the Flash to be successfully modified. If either the
VDD Monitor or the VDD Monitor reset source is not enabled, a Flash Error Device Reset will be
generated when the firmware attempts to modify the Flash.
The following guidelines are recommended for any system that contains routines which write or erase
Flash from code.

11.4.1. VDD Maintenance and the VDD Monitor
1. If the system power supply is subject to voltage or current "spikes," add sufficient transient
protection devices to the power supply to ensure that the supply voltages listed in the Absolute
Maximum Ratings table are not exceeded.
2. Make certain that the minimum VDD rise time specification of 1 ms is met. If the system cannot
meet this rise time specification, then add an external VDD brownout circuit to the /RST pin of
the device that holds the device in reset until VDD reaches 2.7 V and re-asserts /RST if VDD
drops below 2.7 V.
3. Keep the on-chip VDD Monitor enabled and enable the VDD Monitor as a reset source as
early in code as possible. This should be the first set of instructions executed after the Reset
Vector. For 'C'-based systems, this will involve modifying the startup code added by the 'C'
compiler. See your compiler documentation for more details. Make certain that there are no
delays in software between enabling the VDD Monitor and enabling the VDD Monitor as a
reset source. Code examples showing this can be found in AN201, "Writing to Flash from
Firmware", available from the Silicon Laboratories web site.
4. As an added precaution, explicitly enable the VDD Monitor and enable the VDD Monitor as a
reset source inside the functions that write and erase Flash memory. The VDD Monitor enable
instructions should be placed just after the instruction to set PSWE to a '1', but before the
Flash write or erase operation instruction.
5. Make certain that all writes to the RSTSRC (Reset Sources) register use direct assignment
operators and explicitly DO NOT use the bit-wise operators (such as AND or OR). For example, "RSTSRC = 0x02" is correct, but "RSTSRC |= 0x02" is incorrect.
6. Make certain that all writes to the RSTSRC register explicitly set the PORSF bit to a '1'. Areas
to check are initialization code which enables other reset sources, such as the Missing Clock
Detector or Comparator, for example, and instructions which force a Software Reset. A global
search on "RSTSRC" can quickly verify this.

Rev. 1.4

110

C8051F320/1
11.4.2. 16.4.2 PSWE Maintenance
7. Reduce the number of places in code where the PSWE bit (b0 in PSCTL) is set to a '1'. There
should be exactly one routine in code that sets PSWE to a '1' to write Flash bytes and one routine in code that sets both PSWE and PSEE both to a '1' to erase Flash pages.
8. Minimize the number of variable accesses while PSWE is set to a '1'. Handle pointer address
updates and loop maintenance outside the "PSWE = 1; ... PSWE = 0;" area. Code examples
showing this can be found in AN201, "Writing to Flash from Firmware", available from the Silicon Laboratories web site.
9. Disable interrupts prior to setting PSWE to a '1' and leave them disabled until after PSWE has
been reset to '0'. Any interrupts posted during the Flash write or erase operation will be serviced in priority order after the Flash operation has been completed and interrupts have been
re-enabled by software.
10. Make certain that the Flash write and erase pointer variables are not located in XRAM. See
your compiler documentation for instructions regarding how to explicitly locate variables in different memory areas.
11. Add address bounds checking to the routines that write or erase Flash memory to ensure that
a routine called with an illegal address does not result in modification of the Flash.

11.4.3. System Clock
12. If operating from an external crystal, be advised that crystal performance is susceptible to
electrical interference and is sensitive to layout and to changes in temperature. If the system is
operating in an electrically noisy environment, use the internal oscillator or use an external
CMOS clock.
13. If operating from the external oscillator, switch to the internal oscillator during Flash write or
erase operations. The external oscillator can continue to run, and the CPU can switch back to
the external oscillator after the Flash operation has completed.

111

Rev. 1.4

C8051F320/1
SFR Definition 11.1. PSCTL: Program Store R/W Control
R/W

R/W

Reset Value

Reserved

PSEE

PSWE

00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

0x8F
Bits7–3: Unused: Read = 00000b. Write = don’t care.
Bit2:
Reserved. Read = 0b. Must Write = 0b.
Bit1:
PSEE: Program Store Erase Enable
Setting this bit (in combination with PSWE) allows an entire page of Flash program memory
to be erased. If this bit is logic 1 and Flash writes are enabled (PSWE is logic 1), a write to
Flash memory using the MOVX instruction will erase the entire page that contains the location addressed by the MOVX instruction. The value of the data byte written does not matter.
0: Flash program memory erasure disabled.
1: Flash program memory erasure enabled.
Bit0:
PSWE: Program Store Write Enable
Setting this bit allows writing a byte of data to the Flash program memory using the MOVX
write instruction. The Flash location should be erased before writing data.
0: Writes to Flash program memory disabled.
1: Writes to Flash program memory enabled; the MOVX write instruction targets Flash
memory.

SFR Definition 11.2. FLKEY: Flash Lock and Key
R/W

R/W

Reset Value

00000000
Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

0xB7
Bits7–0: FLKEY: Flash Lock and Key Register
Write:
This register must be written to before Flash writes or erases can be performed. Flash
remains locked until this register is written to with the following key codes: 0xA5, 0xF1. The
timing of the writes does not matter, as long as the codes are written in order. The key codes
must be written for each Flash write or erase operation. Flash will be locked until the next
system reset if the wrong codes are written or if a Flash operation is attempted before the
codes have been written correctly.
Read:
When read, bits 1–0 indicate the current Flash lock state.
00: Flash is write/erase locked.
01: The first key code has been written (0xA5).
10: Flash is unlocked (writes/erases allowed).
11: Flash writes/erases disabled until the next reset.

Rev. 1.4

112

C8051F320/1
SFR Definition 11.3. FLSCL: Flash Scale
R/W

FOSE
Bit7

R/W

Reset Value

Reserved Reserved Reserved Reserved Reserved Reserved Reserved 10000000
Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

0xB6
Bits7:

FOSE: Flash One-shot Enable
This bit enables the Flash read one-shot. When the Flash one-shot disabled, the Flash
sense amps are enabled for a full clock cycle during Flash reads. At system clock frequencies below 10 MHz, disabling the Flash one-shot will increase system power consumption.
0: Flash one-shot disabled.
1: Flash one-shot enabled.
Bits6–0: RESERVED. Read = 000000b. Must Write 000000b.

113

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C8051F320/1
12. External RAM
The C8051F320/1 devices include 2048 bytes of on-chip XRAM. This XRAM space is split into user RAM
(addresses 0x0000 - 0x03FF) and USB0 FIFO space (addresses 0x0400 - 0x07FF).

0xFFFF
Same 2048 bytes as from
0x0000 to 0x07FF, wrapped
on 2 kB boundaries

0x0800
0x07FF
0x0400
0x03FF
0x0000

USB FIFOs
1024 Bytes

Accessed through USB FIFO
registers

XRAM
1024 Bytes

Accessed with the MOVX
instruction

Figure 12.1. External Ram Memory Map
12.1. Accessing User XRAM
XRAM can be accessed using the external move instruction (MOVX) and the data pointer (DPTR), or using
MOVX indirect addressing mode. If the MOVX instruction is used with an 8-bit address operand (such as
@R1), then the high byte of the 16-bit address is provided by the External Memory Interface Control Register (EMI0CN as shown in Figure 12.1). Note: the MOVX instruction is also used for writes to the Flash
memory. See Section “11. Flash Memory” on page 106 for details. The MOVX instruction accesses XRAM
by default.
For any of the addressing modes the upper 5 bits of the 16-bit external data memory address word are
"don't cares". As a result, the 2048-byte RAM is mapped modulo style over the entire 64k external data
memory address range. For example, the XRAM byte at address 0x0000 is also at address 0x0800,
0x1000, 0x1800, 0x2000, etc.
Important Note: The upper 1k of the 2k XRAM functions as USB FIFO space. See Section 12.2 for
details on accessing this memory space.

12.2. Accessing USB FIFO Space
The upper 1k of XRAM functions as USB FIFO space. Figure 12.2 shows an expanded view of the FIFO
space and user XRAM. FIFO space is accessed via USB FIFO registers; see Section “15.5. FIFO Management” on page 147 for more information on accessing these FIFOs. The MOVX instruction should not be
used to load or modify USB data in the FIFO space.
Unused areas of the FIFO space may be used as general purpose XRAM, accessible as described in Section 12.1. The FIFO block operates on the USB clock domain; thus the USB clock must be active when
accessing FIFO space. Note that the number of SYSCLK cycles required by the MOVX instruction is
increased when accessing USB FIFO space.
Important Note: The USB clock must be active when accessing FIFO space.

Rev. 1.4

114

C8051F320/1

0x03FF

0x07FF
Endpoint0
(64 bytes)
0x07C0
0x07BF
Endpoint1
(128 bytes)
0x0740
0x073F
Endpoint2
(256 bytes)

User XRAM Space

User XRAM
(1024 bytes)

(System Clock Domain)

0x0640

USB FIFO Space

0x063F

(USB Clock Domain)

Endpoint3
(512 bytes)
0x0440
0x043F
Free
(64 bytes)
0x0000

0x0400

Figure 12.2. XRAM Memory Map Expanded View
SFR Definition 12.1. EMI0CN: External Memory Interface Control
R/W

R/W

Reset Value

PGSEL2

PGSEL1

PGSEL0

00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

0xAA
Bits7–3: Unused: Read = 00000b. Write = don’t care.
Bits2–0: PGSEL[2:0]: XRAM Page Select Bits.
The XRAM Page Select Bits provide the high byte of the 16-bit external data memory
address when using an 8-bit MOVX command, effectively selecting a 256-byte page of
RAM. The upper 5-bits are "don't cares", so the 2k address blocks are repeated modulo over
the entire 64k external data memory address space.

115

Rev. 1.4

C8051F320/1
13. Oscillators
C8051F320/1 devices include a programmable internal oscillator, an external oscillator drive circuit, and a
4x Clock Multiplier. The internal oscillator can be enabled/disabled and calibrated using the OSCICN and
OSCICL registers, as shown in Figure 13.1. The system clock (SYSCLK) can be derived from the internal
oscillator, external oscillator circuit, or the 4x Clock Multiplier divided by 2. The USB clock (USBCLK) can
be derived from the internal oscillator, external oscillator, or 4x Clock Multiplier. Oscillator electrical specifications are given in Table 13.3 on page 125.

IFCN1
IFCN0

IOSCEN
IFRDY
SUSPEND

Option 3
XTAL2

VDD

CLKSEL
CLKSL1
CLKSL0

OSCICN

USBCLK2
USBCLK1
USBCLK0

OSCICL
Option 2

XTAL2

EN
Programmable
Internal Clock
Generator

Option 1

IOSC
n

XTAL1
EXOSC

Input
Circuit

10MΩ

OSC

SYSCLK

Option 4
XTAL2

XTLVLD

XTAL2

IOSC
EXOSC

x2
IOSC / 2

EXOSC / 2

Clock Multiplier
EXOSC
MULSEL1
MULSEL0

CLKMUL

EXOSC / 3
EXOSC / 4
USBCLK2-0

OSCXCN

MULEN
MULINIT
MULRDY

XFCN2
XFCN1
XFCN0

XTLVLD
XOSCMD2
XOSCMD1
XOSCMD0

USBCLK
EXOSC / 2

Figure 13.1. Oscillator Diagram
13.1. Programmable Internal Oscillator
All C8051F320/1 devices include a programmable internal oscillator that defaults as the system clock after
a system reset. The internal oscillator period can be programmed via the OSCICL register as defined by
Equation 13.1, where fBASE is the frequency of the internal oscillator following a reset, ΔT is the change in
internal oscillator period, and ΔOSCICL is a change to the value held in register OSCICL.

Rev. 1.4

116

C8051F320/1
Equation 13.1. Typical Change in Internal Oscillator Period with OSCICL
1
ΔT ≅ 0.0025 × ------------- × ΔOSCICL
f BASE
On C8051F320/1 devices, OSCICL is factory calibrated to obtain a 12 MHz base frequency (fBASE). Section 13.1.1 details oscillator programming for C8051F320/1 devices. Electrical specifications for the precision internal oscillator are given in Table 13.3 on page 125. Note that the system clock may be derived
from the programmed internal oscillator divided by 1, 2, 4, or 8, as defined by the IFCN bits in register
OSCICN. The divide value defaults to 8 following a reset.

13.1.1. Programming the Internal Oscillator on C8051F320/1 Devices
The OSCICL reset value is factory calibrated to result in a 12 MHz internal oscillator with a ±1.5% accuracy; this frequency is suitable for use as the USB clock (see Section 13.4). Software may modify the frequency of the internal oscillator as described below.
Important Note: Once the internal oscillator frequency has been modified, the internal oscillator may not
be used as the USB clock as described in Section 13.4. The internal oscillator frequency will reset to its
original factory-calibrated frequency following any device reset, at which point the oscillator is suitable for
use as the USB clock.
Software should read and adjust the value of OSCICL according to Equation 13.1 to obtain the desired frequency. The example below shows how to obtain an 11.6 MHz internal oscillator frequency.
fBASE is the internal oscillator reset frequency; TBASE is the reset oscillator period.
fDES is the desired internal oscillator frequency; TDES is the desired oscillator period.

f BASE = 12000000Hz
1
T BASE = ------------------------ s
12000000

f DES = 11600000Hz
1
T DES = ------------------------ s
11600000

The required change in period (ΔTDES) is the difference between the base period and the desired period.

1
1
–9
ΔT DES = ------------------------ – ------------------------ = 2.87 × 10 s
11600000 12000000
Using Equation 13.1 and the above calculations, find ΔOSCICL:

2.87 × 10

–9

1
= 0.0025 × ------------- × ΔOSCICL
f BASE

ΔOSCICL = 13.79
ΔOSCICL is rounded to the nearest integer (14) and added to the reset value of register OSCICL.

117

Rev. 1.4

C8051F320/1
Important Note: If the sum of the reset value of OSCICL and ΔOSCICL is greater than 31 or less than 0,
then the device will not be capable of producing the desired frequency.

13.1.2. Internal Oscillator Suspend Mode
The internal oscillator may be placed in Suspend mode by writing ‘1’ to the SUSPEND bit in register
OSCICN. In Suspend mode, the internal oscillator is stopped until a non-idle USB event is detected (Section 15) or VBUS matches the polarity selected by the VBPOL bit in register REG0CN (Section 8.2). The
transceiver is able to detect non-idle USB events even when it is placed in Suspend mode. On a non-idle
USB event, a Resume interrupt is generated, on receipt of which the PHYEN bit should be set to '1' to reenable the transceiver.

SFR Definition 13.1. OSCICN: Internal Oscillator Control
R/W

R/W

Reset Value

IOSCEN

IFRDY

SUSPEND

IFCN1

IFCN0

10000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

0xB2
Bit7:

IOSCEN: Internal Oscillator Enable Bit.
0: Internal Oscillator Disabled.
1: Internal Oscillator Enabled.
Bit6:
IFRDY: Internal Oscillator Frequency Ready Flag.
0: Internal Oscillator is not running at programmed frequency.
1: Internal Oscillator is running at programmed frequency.
Bit5:
SUSPEND: Force Suspend
Writing a ‘1’ to this bit will force the internal oscillator to be stopped. The oscillator will be restarted on the next non-idle USB event (i.e., RESUME signaling) or VBUS interrupt event
(see Figure 8.1).
Bits4–2: UNUSED. Read = 000b, Write = don't care.
Bits1–0: IFCN1–0: Internal Oscillator Frequency Control Bits.
00: SYSCLK derived from Internal Oscillator divided by 8.
01: SYSCLK derived from Internal Oscillator divided by 4.
10: SYSCLK derived from Internal Oscillator divided by 2.
11: SYSCLK derived from Internal Oscillator divided by 1.

SFR Definition 13.2. OSCICL: Internal Oscillator Calibration
R/W

R/W

Bit7

Bit6

Bit5

R/W

Reset Value

Bit1

Bit0

SFR Address:

OSCCAL
Bit4

Bit3

Bit2

Variable
0xB3

Bits7–5: Unused: Read = varies. Write = don’t care.
Bits4–0: OSCCAL: Oscillator Calibration Value
These bits determine the internal oscillator period as per Equation 13.1.
Note: The contents of this register are undefined when Clock Recovery is enabled. See Section “15.4. USB Clock
Configuration” on page 146 for details on Clock Recovery.

Rev. 1.4

118

C8051F320/1
13.2. External Oscillator Drive Circuit
The external oscillator circuit may drive an external crystal, ceramic resonator, capacitor, or RC network. A
CMOS clock may also provide a clock input. For a crystal or ceramic resonator configuration, the crystal/resonator must be wired across the XTAL1 and XTAL2 pins as shown in Option 1 of Figure 13.1. A
10 MΩ resistor also must be wired across the XTAL1 and XTAL2 pins for the crystal/resonator configuration. In RC, capacitor, or CMOS clock configuration, the clock source should be wired to the XTAL2 pin as
shown in Option 2, 3, or 4 of Figure 13.1. The type of external oscillator must be selected in the OSCXCN
register, and the frequency control bits (XFCN) must be selected appropriately (see Figure 13.3)
Important Note on External Oscillator Usage: Port pins must be configured when using the external
oscillator circuit. When the external oscillator drive circuit is enabled in crystal/resonator mode, Port pins
P0.2 and P0.3 are used as XTAL1 and XTAL2 respectively. When the external oscillator drive circuit is
enabled in capacitor, RC, or CMOS clock mode, Port pin P0.3 is used as XTAL2. The Port I/O Crossbar
should be configured to skip the Port pins used by the oscillator circuit; see Section “14.1. Priority Crossbar
Decoder” on page 128 for Crossbar configuration. Additionally, when using the external oscillator circuit in
crystal/resonator, capacitor, or RC mode, the associated Port pins should be configured as analog inputs.
In CMOS clock mode, the associated pin should be configured as a digital input. See Section “14.2. Port
I/O Initialization” on page 130 for details on Port input mode selection.

13.2.1. Clocking Timers Directly Through the External Oscillator
The external oscillator source divided by eight is a clock option for the timers (Section “19. Timers” on
page 209) and the Programmable Counter Array (PCA) (Section “20. Programmable Counter Array
(PCA0)” on page 227). When the external oscillator is used to clock these peripherals, but is not used as
the system clock, the external oscillator frequency must be less than or equal to the system clock frequency. In this configuration, the clock supplied to the peripheral (external oscillator / 8) is synchronized
with the system clock; the jitter associated with this synchronization is limited to ±0.5 system clock cycles.

13.2.2. External Crystal Example
If a crystal or ceramic resonator is used as an external oscillator source for the MCU, the circuit should be
configured as shown in Figure 13.1, Option 1. The External Oscillator Frequency Control value (XFCN)
should be chosen from the Crystal column of the table in Figure 13.3 (OSCXCN register). For example, a
12 MHz crystal requires an XFCN setting of 111b.
When the crystal oscillator is first enabled, the oscillator amplitude detection circuit requires a settling time
to achieve proper bias. Introducing a delay of 1 ms between enabling the oscillator and checking the
XTLVLD bit will prevent a premature switch to the external oscillator as the system clock. Switching to the
external oscillator before the crystal oscillator has stabilized can result in unpredictable behavior. The recommended procedure is:
Step 1.
Step 2.
Step 3.
Step 4.

Enable the external oscillator.
Wait at least 1 ms.
Poll for XTLVLD => ‘1’.
Switch the system clock to the external oscillator.

Important Note on External Crystals: Crystal oscillator circuits are quite sensitive to PCB layout. The
crystal should be placed as close as possible to the XTAL pins on the device. The traces should be as
short as possible and shielded with ground plane from any other traces which could introduce noise or
interference.

119

Rev. 1.4

C8051F320/1
13.2.3. External RC Example
If an RC network is used as an external oscillator source for the MCU, the circuit should be configured as
shown in Figure 13.1, Option 2. The capacitor should be no greater than 100 pF; however for very small
capacitors, the total capacitance may be dominated by parasitic capacitance in the PCB layout. To determine the required External Oscillator Frequency Control value (XFCN) in the OSCXCN Register, first
select the RC network value to produce the desired frequency of oscillation. If the frequency desired is
100 kHz, let R = 246 kΩ and C = 50 pF:
f = 1.23( 103 ) / RC = 1.23 ( 103 ) / [ 246 x 50 ] = 0.1 MHz = 100 kHz
Referring to the table in Figure 13.3, the required XFCN setting is 010b. Programming XFCN to a higher
setting in RC mode will improve frequency accuracy at an increased external oscillator supply current.

13.2.4. External Capacitor Example
If a capacitor is used as an external oscillator for the MCU, the circuit should be configured as shown in
Figure 13.1, Option 3. The capacitor should be no greater than 100 pF; however for very small capacitors,
the total capacitance may be dominated by parasitic capacitance in the PCB layout. To determine the
required External Oscillator Frequency Control value (XFCN) in the OSCXCN Register, select the capacitor to be used and find the frequency of oscillation from the equations below. Assume VDD = 3.0 V and C
= 50 pF:
f = KF / ( C x VDD ) = KF / ( 50 x 3 ) MHz
f = KF / 150 MHz
If a frequency of roughly 150 kHz is desired, select the K Factor from the table in Figure 13.3 as KF = 22:
f = 22 / 150 = 0.146 MHz, or 146 kHz
Therefore, the XFCN value to use in this example is 011b.

Rev. 1.4

120

C8051F320/1
SFR Definition 13.3. OSCXCN: External Oscillator Control
R

R/W

XTLVLD XOSCMD2 XOSCMD1 XOSCMD0
Bit7

Bit6

Bit5

Bit4

R/W

Reset Value

XFCN2

XFCN1

XFCN0

00000000

Bit3

Bit2

Bit1

Bit0

SFR Address:

0xB1
Bit7:

XTLVLD: Crystal Oscillator Valid Flag.
(Read only when XOSCMD = 11x.)
0: Crystal Oscillator is unused or not yet stable.
1: Crystal Oscillator is running and stable.
Bits6–4: XOSCMD2–0: External Oscillator Mode Bits.
00x: External Oscillator circuit off.
010: External CMOS Clock Mode.
011: External CMOS Clock Mode with divide by 2 stage.
100: RC Oscillator Mode.
101: Capacitor Oscillator Mode.
110: Crystal Oscillator Mode.
111: Crystal Oscillator Mode with divide by 2 stage.
Bit3:
RESERVED. Read = 0, Write = don't care.
Bits2–0: XFCN2–0: External Oscillator Frequency Control Bits.
000–111: See table below:
XFCN
000
001
010
011
100
101
110
111

Crystal (XOSCMD = 11x)
f ≤ 32 kHz
32 kHz < f ≤ 84 kHz
84 kHz < f ≤ 225 kHz
225 kHz < f ≤ 590 kHz
590 kHz < f ≤ 1.5 MHz
1.5 MHz < f ≤ 4 MHz
4 MHz < f ≤ 10 MHz
10 MHz < f ≤ 30 MHz

RC (XOSCMD = 10x)
f ≤ 25 kHz
25 kHz < f ≤ 50 kHz
50 kHz < f ≤ 100 kHz
100 kHz < f ≤ 200 kHz
200 kHz < f ≤ 400 kHz
400 kHz < f ≤ 800 kHz
800 kHz < f ≤ 1.6 MHz
1.6 MHz < f ≤ 3.2 MHz

CRYSTAL MODE (Circuit from Figure 13.1, Option 1; XOSCMD = 11x)
Choose XFCN value to match crystal or resonator frequency.
RC MODE (Circuit from Figure 13.1, Option 2; XOSCMD = 10x)
Choose XFCN value to match frequency range:
f = 1.23(103) / (R * C), where
f = frequency of clock in MHz
C = capacitor value in pF
R = Pull-up resistor value in kΩ
C MODE (Circuit from Figure 13.1, Option 3; XOSCMD = 10x)
Choose K Factor (KF) for the oscillation frequency desired:
f = KF / (C * VDD), where
f = frequency of clock in MHz
C = capacitor value the XTAL2 pin in pF
VDD = Power Supply on MCU in volts

121

Rev. 1.4

C (XOSCMD = 10x)
K Factor = 0.87
K Factor = 2.6
K Factor = 7.7
K Factor = 22
K Factor = 65
K Factor = 180
K Factor = 664
K Factor = 1590

C8051F320/1
13.3. 4x Clock Multiplier
The 4x Clock Multiplier allows a 12 MHz oscillator to generate the 48 MHz clock required for Full Speed
USB communication (see Section “15.4. USB Clock Configuration” on page 146). A divided version of the
Multiplier output can also be used as the system clock. See Section 13.4 for details on system clock and
USB clock source selection.
The 4x Clock Multiplier is configured via the CLKMUL register. The procedure for configuring and enabling
the 4x Clock Multiplier is as follows:
1.
2.
3.
4.
5.
6.

Reset the Multiplier by writing 0x00 to register CLKMUL.
Select the Multiplier input source via the MULSEL bits.
Enable the Multiplier with the MULEN bit (CLKMUL | = 0x80).
Delay for >5 µs.
Initialize the Multiplier with the MULINIT bit (CLKMUL | = 0xC0).
Poll for MULRDY => ‘1’.

Important Note: When using an external oscillator as the input to the 4x Clock Multiplier, the external source must be enabled and stable before the Multiplier is initialized. See Section 13.4 for
details on selecting an external oscillator source.

SFR Definition 13.4. CLKMUL: Clock Multiplier Control
R/W

MULEN
Bit7

R/W

MULINIT MULRDY
Bit6

Bit5

R/W

Bit4

Bit3

Bit2

R/W

MULSEL
Bit1

Bit0

Reset Value

00000000
SFR Address

0xB9
Bit7:

MULEN: Clock Multiplier Enable
0: Clock Multiplier disabled.
1: Clock Multiplier enabled.
Bit6:
MULINIT: Clock Multiplier Initialize
This bit should be a ‘0’ when the Clock Multiplier is enabled. Once enabled, writing a ‘1’ to
this bit will initialize the Clock Multiplier. The MULRDY bit reads ‘1’ when the Clock Multiplier
is stabilized.
Bit5:
MULRDY: Clock Multiplier Ready
This read-only bit indicates the status of the Clock Multiplier.
0: Clock Multiplier not ready.
1: Clock Multiplier ready (locked).
Bits4–2: Unused. Read = 000b; Write = don’t care.
Bits1–0: MULSEL: Clock Multiplier Input Select
These bits select the clock supplied to the Clock Multiplier.
MULSEL
00
01
10
11

Selected Clock
Internal Oscillator
External Oscillator
External Oscillator / 2
RESERVED

Rev. 1.4

122

C8051F320/1
13.4. System and USB Clock Selection
The internal oscillator requires little start-up time and may be selected as the system or USB clock immediately following the OSCICN write that enables the internal oscillator. External crystals and ceramic resonators typically require a start-up time before they are settled and ready for use. The Crystal Valid Flag
(XTLVLD in register OSCXCN) is set to ‘1’ by hardware when the external oscillator is settled. To avoid
reading a false XTLVLD, in crystal mode software should delay at least 1 ms between enabling the
external oscillator and checking XTLVLD. RC and C modes typically require no startup time.

13.4.1. System Clock Selection
The CLKSL[1:0] bits in register CLKSEL select which oscillator source is used as the system clock.
CLKSL[1:0] must be set to 01b for the system clock to run from the external oscillator; however the external oscillator may still clock certain peripherals (timers, PCA, USB) when the internal oscillator is selected
as the system clock. The system clock may be switched on-the-fly between the internal oscillator, external
oscillator, and 4x Clock Multiplier so long as the selected oscillator is enabled and has settled.

13.4.2. USB Clock Selection
The USBCLK[2:0] bits in register CLKSEL select which oscillator source is used as the USB clock. The
USB clock may be derived from the 4x Clock Multiplier output, a divided version of the internal oscillator, or
a divided version of the external oscillator. Note that the USB clock must be 48 MHz when operating USB0
as a Full Speed Function; the USB clock must be 6 MHz when operating USB0 as a Low Speed Function.
See Figure 13.5 for USB clock selection options.
Some example USB clock configurations for Full and Low Speed mode are given below:

Table 13.1. Typical USB Full Speed Clock Settings
Clock Signal
USB Clock
Clock Multiplier Input
Internal Oscillator
Clock Signal
USB Clock
Clock Multiplier Input
External Oscillator

Internal Oscillator
Input Source Selection
Clock Multiplier
Internal Oscillator*
Divide by 1
External Oscillator
Input Source Selection
Clock Multiplier
External Oscillator
Crystal Oscillator Mode
12 MHz Crystal

Register Bit Settings
USBCLK = 000b
MULSEL = 00b
IFCN = 11b
Register Bit Settings
USBCLK = 000b
MULSEL = 01b
XOSCMD = 110b
XFCN = 111b

*Note: Clock Recovery must be enabled for this configuration.

123

Rev. 1.4

C8051F320/1
Table 13.2. Typical USB Low Speed Clock Settings
Clock Signal
USB Clock
Internal Oscillator
Clock Signal
USB Clock
External Oscillator

Internal Oscillator
Input Source Selection
Internal Oscillator/2
Divide by 1
External Oscillator
Input Source Selection
External Oscillator/4
Crystal Oscillator Mode
24 MHz Crystal

SFR Definition 13.5. CLKSEL: Clock Select
R/W

R/W

Bit7

R/W

USBCLK
Bit6

Bit5

Bit4

R/W

Bit3

Bit2

R/W

CLKSL
Bit1

Reset Value

00000000
Bit0

SFR Address

0xA9
Bit 7:
Unused. Read = 0b; Write = don’t care.
Bits6–4: USBCLK2–0: USB Clock Select
These bits select the clock supplied to USB0. When operating USB0 in full-speed mode, the
selected clock should be 48 MHz. When operating USB0 in low-speed mode, the selected
clock should be 6 MHz.
USBCLK
000
001
010
011
100
101
110
111

Selected Clock
4x Clock Multiplier
Internal Oscillator/2
External Oscillator
External Oscillator/2
External Oscillator/3
External Oscillator/4
RESERVED
RESERVED

Bits3–2: Unused. Read = 00b; Write = don’t care.
Bits1–0: CLKSL1–0: System Clock Select
These bits select the system clock source.
CLKSL
00
01
10
11

Selected Clock
Internal Oscillator (as determined by the
IFCN bits in register OSCICN)
External Oscillator
4x Clock Multiplier/2
RESERVED

Rev. 1.4

124

C8051F320/1
Table 13.3. Internal Oscillator Electrical Characteristics
–40 to +85 °C unless otherwise specified.
Parameter

Conditions

Min

Typ

Max

Units

Internal Oscillator Frequency

Reset Frequency

11.82

12.18

MHz

Internal Oscillator Supply
Current (from VDD)

OSCICN.7 = 1

USB Clock Frequency*

µA

Full Speed Mode

47.88

48.12

Low Speed Mode

5.91

6.09

*Note: Applies only to external oscillator sources.

125

450

Rev. 1.4

MHz

C8051F320/1
14. Port Input/Output
Digital and analog resources are available through 25 I/O pins (C8051F320) or 21 I/O pins (C8051F321).
Port pins are organized as shown in Figure 14.1. Each of the Port pins can be defined as general-purpose
I/O (GPIO) or analog input; Port pins P0.0-P2.3 can be assigned to one of the internal digital resources as
shown in Figure 14.3. The designer has complete control over which functions are assigned, limited only
by the number of physical I/O pins. This resource assignment flexibility is achieved through the use of a
Priority Crossbar Decoder. Note that the state of a Port I/O pin can always be read in the corresponding
Port latch, regardless of the Crossbar settings.
The Crossbar assigns the selected internal digital resources to the I/O pins based on the Priority Decoder
(Figure 14.3 and Figure 14.4). The registers XBR0 and XBR1, defined in Figure 14.1 and Figure 14.2, are
used to select internal digital functions.
All Port I/Os are 5 V tolerant (refer to Figure 14.2 for the Port cell circuit). The Port I/O cells are configured
as either push-pull or open-drain in the Port Output Mode registers (PnMDOUT, where n = 0,1,2,3). Complete Electrical Specifications for Port I/O are given in Table 14.1 on page 138.

XBR0, XBR1,
PnSKIP Registers

PnMDOUT,
PnMDIN Registers

Priority
Decoder
Highest
Priority

UART

(Internal Digital Signals)

P0
I/O
Cells

P0.0

P1
I/O
Cells

P1.0

P2
I/O
Cells

P2.0

P3
I/O
Cells

P3.0

2
8

Note: P2.4-P2.7 only available
on the C8051F320

SPI

CP0
Outputs

CP1
Outputs

Digital
Crossbar

SYSCLK

P1.7

P2.7

PCA

1
Lowest
Priority

P0.7

SMBus

T0, T1

(P0.0-P0.7)

(P1.0-P1.7)

(Port Latches)

8
P2

(P2.0-P2.7)

(P3.0)

Figure 14.1. Port I/O Functional Block Diagram

Rev. 1.4

126

C8051F320/1
/WEAK-PULLUP

VDD

PUSH-PULL
/PORT-OUTENABLE

VDD

(WEAK)
PORT
PAD

PORT-OUTPUT

GND

Analog Select
ANALOG INPUT
PORT-INPUT

Figure 14.2. Port I/O Cell Block Diagram

127

Rev. 1.4

C8051F320/1
14.1. Priority Crossbar Decoder
The Priority Crossbar Decoder (Figure 14.3) assigns a priority to each I/O function, starting at the top with
UART0. When a digital resource is selected, the least-significant unassigned Port pin is assigned to that
resource (excluding UART0, which is always at pins 4 and 5). If a Port pin is assigned, the Crossbar skips
that pin when assigning the next selected resource. Additionally, the Crossbar will skip Port pins whose
associated bits in the PnSKIP registers are set. The PnSKIP registers allow software to skip Port pins that
are to be used for analog input, dedicated functions, or GPIO.
Important Note on Crossbar Configuration: If a Port pin is claimed by a peripheral without use of the
Crossbar, its corresponding PnSKIP bit should be set. This applies to P0.7 if VREF is used, P0.3 and/or
P0.2 if the external oscillator circuit is enabled, P0.6 if the ADC is configured to use the external conversion
start signal (CNVSTR), and any selected ADC or Comparator inputs. The Crossbar skips selected pins as
if they were already assigned, and moves to the next unassigned pin. Figure 14.3 shows the Crossbar
Decoder priority with no Port pins skipped (P0SKIP, P1SKIP, P2SKIP = 0x00); Figure 14.4 shows the
Crossbar Decoder priority with the XTAL1 (P0.2) and XTAL2 (P0.3) pins skipped (P0SKIP = 0x0C).

VREF

P1
CNVSTR

PIN I/O

XTAL2

SF Signals

XTAL1

TX0
RX0
SCK
MISO
MOSI
NSS*

*NSS is only pinned out in 4-wire SPI mode

SDA
SCL
CP0
Signals Unavailable

CP0A
CP1
CP1A
SYSCLK
CEX0
CEX1
CEX2
CEX3
CEX4
ECI
T0
T1
0

P0SKIP[0:7]

P1SKIP[0:7]

P2SKIP[0:3]

Port pin potentially available to peripheral
SF Signals Special Function Signals are not assigned by the Crossbar. When these signals are enabled, the Crossbar must
be manually configured to skip their corresponding port pins.

Figure 14.3. Crossbar Priority Decoder with No Pins Skipped

Rev. 1.4

128

C8051F320/1

VREF

P1
CNVSTR

PIN I/O

XTAL2

SF Signals

XTAL1

TX0
RX0
SCK
MISO
MOSI
*NSS is only pinned out in 4-wire SPI mode

NSS*
SDA
SCL
CP0

Signals Unavailable

CP0A
CP1
CP1A
SYSCLK
CEX0
CEX1
CEX2
CEX3
CEX4
ECI
T0
T1
0

P0SKIP[0:7]

P1SKIP[0:7]

P2SKIP[0:3]

Figure 14.4. Crossbar Priority Decoder with Crystal Pins Skipped
Registers XBR0 and XBR1 are used to assign the digital I/O resources to the physical I/O Port pins. Note
that when the SMBus is selected, the Crossbar assigns both pins associated with the SMBus (SDA and
SCL); when the UART is selected, the Crossbar assigns both pins associated with the UART (TX and RX).
UART0 pin assignments are fixed for bootloading purposes: UART TX0 is always assigned to P0.4; UART
RX0 is always assigned to P0.5. Standard Port I/Os appear contiguously after the prioritized functions
have been assigned.
Important Note: The SPI can be operated in either 3-wire or 4-wire modes, depending on the state of the
NSSMD1-NSSMD0 bits in register SPI0CN. According to the SPI mode, the NSS signal may or may not be
routed to a Port pin.

129

Rev. 1.4

C8051F320/1
14.2. Port I/O Initialization
Port I/O initialization consists of the following steps:
Step 1. Select the input mode (analog or digital) for all Port pins, using the Port Input Mode
register (PnMDIN).
Step 2. Select the output mode (open-drain or push-pull) for all Port pins, using the Port Output
Mode register (PnMDOUT).
Step 3. Select any pins to be skipped by the I/O Crossbar using the Port Skip registers (PnSKIP).
Step 4. Assign Port pins to desired peripherals (XBR0, XBR1).
Step 5. Enable the Crossbar (XBARE = ‘1’).
All Port pins must be configured as either analog or digital inputs. Any pins to be used as Comparator or
ADC inputs should be configured as an analog inputs. When a pin is configured as an analog input, its
weak pull-up, digital driver, and digital receiver are disabled. This process saves power and reduces noise
on the analog input. Pins configured as digital inputs may still be used by analog peripherals; however this
practice is not recommended. To configure a Port pin for digital input, write ‘0’ to the corresponding bit in
register PnMDOUT, and write ‘1’ to the corresponding Port latch (register Pn).
Additionally, all analog input pins should be configured to be skipped by the Crossbar (accomplished by
setting the associated bits in PnSKIP). Port input mode is set in the PnMDIN register, where a ‘1’ indicates
a digital input, and a ‘0’ indicates an analog input. All pins default to digital inputs on reset. See Figure 14.4
for the PnMDIN register details.
The output driver characteristics of the I/O pins are defined using the Port Output Mode registers (PnMDOUT). Each Port Output driver can be configured as either open drain or push-pull. This selection is
required even for the digital resources selected in the XBRn registers, and is not automatic. The only
exception to this is the SMBus (SDA, SCL) pins, which are configured as open-drain regardless of the
PnMDOUT settings. When the WEAKPUD bit in XBR1 is ‘0’, a weak pull-up is enabled for all Port I/O configured as open-drain. WEAKPUD does not affect the push-pull Port I/O. Furthermore, the weak pull-up is
turned off on an output that is driving a ‘0’ to avoid unnecessary power dissipation.
Registers XBR0 and XBR1 must be loaded with the appropriate values to select the digital I/O functions
required by the design. Setting the XBARE bit in XBR1 to ‘1’ enables the Crossbar. Until the Crossbar is
enabled, the external pins remain as standard Port I/O (in input mode), regardless of the XBRn Register
settings. For given XBRn Register settings, one can determine the I/O pin-out using the Priority Decode
Table; as an alternative, the Configuration Wizard utility of the Silicon Labs IDE software will determine the
Port I/O pin-assignments based on the XBRn Register settings.
Important Note: The Crossbar must be enabled to use Ports P0, P1, and P2.0-P2.3 as standard Port I/O
in output mode. These Port output drivers are disabled while the Crossbar is disabled. P2.4-P2.7 and P3.0
always function as standard GPIO.

Rev. 1.4

130

C8051F320/1
SFR Definition 14.1. XBR0: Port I/O Crossbar Register 0
R/W

R/W

Reset Value

CP1AE

CP1E

CP0AE

CP0E

SYSCKE

SMB0E

SPI0E

URT0E

00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

0xE1
Bit7:

Bit6:

Bit5:

Bit4:

Bit3:

Bit2:

Bit1:

Bit0:

131

CP1AE: Comparator1 Asynchronous Output Enable
0: Asynchronous CP1 unavailable at Port pin.
1: Asynchronous CP1 routed to Port pin.
CP1E: Comparator1 Output Enable
0: CP1 unavailable at Port pin.
1: CP1 routed to Port pin.
CP0AE: Comparator0 Asynchronous Output Enable
0: Asynchronous CP0 unavailable at Port pin.
1: Asynchronous CP0 routed to Port pin.
CP0E: Comparator0 Output Enable
0: CP0 unavailable at Port pin.
1: CP0 routed to Port pin.
SYSCKE: /SYSCLK Output Enable
0: /SYSCLK unavailable at Port pin.
1: /SYSCLK output routed to Port pin.
SMB0E: SMBus I/O Enable
0: SMBus I/O unavailable at Port pins.
1: SMBus I/O routed to Port pins.
SPI0E: SPI I/O Enable
0: SPI I/O unavailable at Port pins.
1: SPI I/O routed to Port pins.
URT0E: UART I/O Output Enable
0: UART I/O unavailable at Port pin.
1: UART TX0, RX0 routed to Port pins P0.4 and P0.5.

Rev. 1.4

C8051F320/1
SFR Definition 14.2. XBR1: Port I/O Crossbar Register 1
R/W

R/W

WEAKPUD

XBARE

T1E

T0E

ECIE

Bit7

Bit6

Bit5

Bit4

Bit3

R/W

PCA0ME
Bit2

Bit1

Reset Value

00000000
Bit0

SFR Address:

0xE2
Bit7:

WEAKPUD: Port I/O Weak Pull-up Disable.
0: Weak Pull-ups enabled (except for Ports whose I/O are configured as analog input or
push-pull output).
1: Weak Pull-ups disabled.
Bit6:
XBARE: Crossbar Enable.
0: Crossbar disabled; all Port drivers disabled.
1: Crossbar enabled.
Bit5:
T1E: T1 Enable
0: T1 unavailable at Port pin.
1: T1 routed to Port pin.
Bit4:
T0E: T0 Enable
0: T0 unavailable at Port pin.
1: T0 routed to Port pin.
Bit3:
ECIE: PCA0 External Counter Input Enable
0: ECI unavailable at Port pin.
1: ECI routed to Port pin.
Bits2–0: PCA0ME: PCA Module I/O Enable Bits.
000: All PCA I/O unavailable at Port pins.
001: CEX0 routed to Port pin.
010: CEX0, CEX1 routed to Port pins.
011: CEX0, CEX1, CEX2 routed to Port pins.
100: CEX0, CEX1, CEX2, CEX3 routed to Port pins.
101: CEX0, CEX1, CEX2, CEX3, CEX4 routed to Port pins.
110: Reserved.
111: Reserved.

14.3. General Purpose Port I/O
Port pins that remain unassigned by the Crossbar and are not used by analog peripherals can be used for
general purpose I/O. Ports3-0 are accessed through corresponding special function registers (SFRs) that
are both byte addressable and bit addressable. When writing to a Port, the value written to the SFR is
latched to maintain the output data value at each pin. When reading, the logic levels of the Port's input pins
are returned regardless of the XBRn settings (i.e., even when the pin is assigned to another signal by the
Crossbar, the Port register can always read its corresponding Port I/O pin). The exception to this is the
execution of the read-modify-write instructions. The read-modify-write instructions when operating on a
Port SFR are the following: ANL, ORL, XRL, JBC, CPL, INC, DEC, DJNZ and MOV, CLR or SETB, when
the destination is an individual bit in a Port SFR. For these instructions, the value of the register (not the
pin) is read, modified, and written back to the SFR.

Rev. 1.4

132

C8051F320/1
SFR Definition 14.3. P0: Port0 Register
R/W

R/W

Reset Value

P0.7

P0.6

P0.5

P0.4

P0.3

P0.2

P0.1

P0.0

11111111

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

(bit addressable)

0x80

Bits7–0: P0.[7:0]
Write - Output appears on I/O pins per Crossbar Registers (when XBARE = ‘1’).
0: Logic Low Output.
1: Logic High Output (high impedance if corresponding P0MDOUT.n bit = 0).
Read - Always reads ‘0’ if selected as analog input in register P0MDIN. Directly reads Port
pin when configured as digital input.
0: P0.n pin is logic low.
1: P0.n pin is logic high.

SFR Definition 14.4. P0MDIN: Port0 Input Mode Register
R/W

R/W

Reset Value

11111111
Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

0xF1
Bits7–0: Analog Input Configuration Bits for P0.7-P0.0 (respectively).
Port pins configured as analog inputs have their weak pull-up, digital driver, and digital
receiver disabled.
0: Corresponding P0.n pin is configured as an analog input.
1: Corresponding P0.n pin is not configured as an analog input.

SFR Definition 14.5. P0MDOUT: Port0 Output Mode Register
R/W

R/W

Reset Value

00000000
Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

0xA4
Bits7–0: Output Configuration Bits for P0.7–P0.0 (respectively): ignored if corresponding bit in register P0MDIN is logic 0.
0: Corresponding P0.n Output is open-drain.
1: Corresponding P0.n Output is push-pull.
(Note: When SDA and SCL appear on any of the Port I/O, each are open-drain regardless
of the value of P0MDOUT).

133

Rev. 1.4

C8051F320/1
SFR Definition 14.6. P0SKIP: Port0 Skip Register
R/W

R/W

Reset Value

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

00000000
0xD4
Bits7–0: P0SKIP[7:0]: Port0 Crossbar Skip Enable Bits.
These bits select Port pins to be skipped by the Crossbar Decoder. Port pins used as analog inputs (for ADC or Comparator) or used as special functions (VREF input, external oscillator circuit, CNVSTR input) should be skipped by the Crossbar.
0: Corresponding P0.n pin is not skipped by the Crossbar.
1: Corresponding P0.n pin is skipped by the Crossbar.

SFR Definition 14.7. P1: Port1 Register
R/W

R/W

P1.7

P1.6

P1.5

P1.4

P1.3

P1.2

P1.1

P1.0

11111111

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

(bit addressable)

Reset Value

0x90

Bits7–0: P1.[7:0]
Write - Output appears on I/O pins per Crossbar Registers (when XBARE = ‘1’).
0: Logic Low Output.
1: Logic High Output (high impedance if corresponding P1MDOUT.n bit = 0).
Read - Always reads ‘0’ if selected as analog input in register P1MDIN. Directly reads Port
pin when configured as digital input.
0: P1.n pin is logic low.
1: P1.n pin is logic high.

SFR Definition 14.8. P1MDIN: Port1 Input Mode Register
R/W

R/W

Reset Value

11111111
Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR
Address:

0xF2
Bits7–0: Analog Input Configuration Bits for P1.7-P1.0 (respectively).
Port pins configured as analog inputs have their weak pull-up, digital driver, and digital
receiver disabled.
0: Corresponding P1.n pin is configured as an analog input.
1: Corresponding P1.n pin is not configured as an analog input.

Rev. 1.4

134

C8051F320/1
SFR Definition 14.9. P1MDOUT: Port1 Output Mode Register
R/W

R/W

Reset Value

00000000
Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

SFR
Address:

Bit0

0xA5
Bits7–0: Output Configuration Bits for P1.7-P1.0 (respectively): ignored if corresponding bit in register P1MDIN is logic 0.
0: Corresponding P1.n Output is open-drain.
1: Corresponding P1.n Output is push-pull.

SFR Definition 14.10. P1SKIP: Port1 Skip Register
R/W

R/W

Reset Value

00000000
Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

0xD5
Bits7–0: P1SKIP[7:0]: Port1 Crossbar Skip Enable Bits.
These bits select Port pins to be skipped by the Crossbar Decoder. Port pins used as analog inputs (for ADC or Comparator) or used as special functions (VREF input, external oscillator circuit, CNVSTR input) should be skipped by the Crossbar.
0: Corresponding P1.n pin is not skipped by the Crossbar.
1: Corresponding P1.n pin is skipped by the Crossbar.

SFR Definition 14.11. P2: Port2 Register
R/W

R/W

P2.7

P2.6

P2.5

P2.4

P2.3

P2.2

P2.1

P2.0

Reset Value

11111111

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

(bit addressable)

0xA0

Bits7–0: P2.[7:0]
Write - Output appears on I/O pins per Crossbar Registers (when XBARE = ‘1’).
0: Logic Low Output.
1: Logic High Output (high impedance if corresponding P2MDOUT.n bit = 0).
Read - Always reads ‘0’ if selected as analog input in register P2MDIN. Directly reads Port
pin when configured as digital input.
0: P2.n pin is logic low.
1: P2.n pin is logic high.
Note: P2.7–P2.4 only available on C8051F320 devices. Writes to these Ports do not require
XBARE = ‘1’.

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SFR Definition 14.12. P2MDIN: Port2 Input Mode Register
R/W

R/W

Reset Value

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

11111111
0xF3
Bits7–0: Analog Input Configuration Bits for P2.7–P2.0 (respectively).
Port pins configured as analog inputs have their weak pull-up, digital driver, and digital
receiver disabled.
0: Corresponding P2.n pin is configured as an analog input.
1: Corresponding P2.n pin is not configured as an analog input.
Note: P2.7–P2.4 only available on C8051F320 devices.

SFR Definition 14.13. P2MDOUT: Port2 Output Mode Register
R/W

R/W

Reset Value

00000000
Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

0xA6
Bits7–0: Output Configuration Bits for P2.7–P2.0 (respectively): ignored if corresponding bit in register P2MDIN is logic 0.
0: Corresponding P2.n Output is open-drain.
1: Corresponding P2.n Output is push-pull.
Note: P2.7–P2.4 only available on C8051F320 devices.

SFR Definition 14.14. P2SKIP: Port2 Skip Register
R/W

R/W

Bit7

Bit6

Bit5

Bit4

R/W

Reset Value

Bit3

Bit2

Bit1

Bit0

SFR Address:

00000000
0xD6

Bits7–4: Unused. Read = 0000b. Write = don’t care.
Bits3–0: P2SKIP[3:0]: Port2 Crossbar Skip Enable Bits.
These bits select Port pins to be skipped by the Crossbar Decoder. Port pins used as analog inputs (for ADC or Comparator) or used as special functions (VREF input, external oscillator circuit, CNVSTR input) should be skipped by the Crossbar.
0: Corresponding P2.n pin is not skipped by the Crossbar.
1: Corresponding P2.n pin is skipped by the Crossbar.

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SFR Definition 14.15. P3: Port3 Register
R/W

R/W

Reset Value

P3.7

P3.6

P3.5

P3.4

P3.3

P3.2

P3.1

P3.0

11111111

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

(bit addressable)

0xB0

Bits7–0: P3.[7:0]
Write - Output appears on I/O pins.
0: Logic Low Output.
1: Logic High Output (high impedance if corresponding P3MDOUT.n bit = 0).
Read - Always reads ‘0’ if selected as analog input in register P3MDIN. Directly reads Port
pin when configured as digital input.
0: P3.n pin is logic low.
1: P3.n pin is logic high.

SFR Definition 14.16. P3MDIN: Port3 Input Mode Register
R/W

R/W

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

R/W

Reset Value

00000001
Bit0

SFR Address:

0xF4
Bits7–1: UNUSED. Read = 0000000b; Write = don’t care.
Bit0:
Analog Input Configuration Bit for P3.0.
Port pins configured as analog inputs have their weak pull-up, digital driver, and digital
receiver disabled.
0: Corresponding P3.n pin is configured as an analog input.
1: Corresponding P3.n pin is not configured as an analog input.

SFR Definition 14.17. P3MDOUT: Port3 Output Mode Register
R/W

R/W

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

R/W

Reset Value

Bit0

SFR Address:

00000000
0xA7

Bits7–1: UNUSED. Read = 0000000b; Write = don’t care.
Bit0:
Output Configuration Bit for P3.0; ignored if corresponding bit in register P3MDIN is logic 0.
0: Corresponding P3.n Output is open-drain.
1: Corresponding P3.n Output is push-pull.

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Table 14.1. Port I/O DC Electrical Characteristics
VDD = 2.7 to 3.6V, –40 to +85 °C unless otherwise specified.

Parameters

Conditions

Min

Typ

Max

IOH = –3 mA, Port I/O push-pull

VDD – 0.7

—

IOH = –10 µA, Port I/O push-pull

VDD – 0.1

—

IOH = –10 mA, Port I/O push-pull

—

VDD – 0.8

—

IOL = 8.5 mA

—

0.6

IOL = 10 µA

—

0.1

IOL = 25 mA

—

1.0

—

Input High Voltage

2.0

—

Input Low Voltage

—

0.8

Weak Pull-up Off

—

±1

Weak Pull-up On, VIN = 0 V

—

Output High Voltage

Output Low Voltage

Input Leakage Current

Rev. 1.4

Units
V

µA

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15. Universal Serial Bus Controller (USB)
C8051F320/1 devices include a complete Full/Low Speed USB function for USB peripheral implementations*. The USB Function Controller (USB0) consists of a Serial Interface Engine (SIE), USB Transceiver
(including matching resistors and configurable pull-up resistors), 1k FIFO block, and clock recovery mechanism for crystal-less operation. No external components are required. The USB Function Controller and
Transceiver is Universal Serial Bus Specification 2.0 compliant.

Transceiver

Serial Interface Engine (SIE)
Endpoint0

VDD
IN/OUT

D+
Data
Transfer
Control
D-

Endpoint1
Endpoint2
Endpoint3
OUT

IN
IN

USB
Control,
Status, and
Interrupt
Registers

CIP-51 Core

OUT
IN

OUT

USB FIFOs
(1k RAM)

Figure 15.1. USB0 Block Diagram
Note: This document assumes a comprehensive understanding of the USB Protocol. Terms and abbreviations used
in this document are defined in the USB Specification. We encourage you to review the latest version of the
USB Specification before proceeding.
*Note: The C8051F320/1 cannot be used as a USB Host device.

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15.1. Endpoint Addressing
A total of eight endpoint pipes are available. The control endpoint (Endpoint0) always functions as a
bi-directional IN/OUT endpoint. The other endpoints are implemented as three pairs of IN/OUT endpoint
pipes:

Table 15.1. Endpoint Addressing Scheme
Endpoint
Endpoint0
Endpoint1
Endpoint2
Endpoint3

Associated Pipes

USB Protocol Address

Endpoint0 IN

0x00

Endpoint0 OUT

0x00

Endpoint1 IN

0x81

Endpoint1 OUT

0x01

Endpoint2 IN

0x82

Endpoint2 OUT

0x02

Endpoint3 IN

0x83

Endpoint3 OUT

0x03

15.2. USB Transceiver
The USB Transceiver is configured via the USB0XCN register shown in Figure 15.1. This configuration
includes Transceiver enable/disable, pull-up resistor enable/disable, and device speed selection (Full or
Low Speed). When bit SPEED = ‘1’, USB0 operates as a Full Speed USB function, and the on-chip pull-up
resistor (if enabled) appears on the D+ pin. When bit SPEED = ‘0’, USB0 operates as a Low Speed USB
function, and the on-chip pull-up resistor (if enabled) appears on the D- pin. Bits4-0 of register USB0XCN
can be used for Transceiver testing as described in Figure 15.1. The pull-up resistor is enabled only when
VBUS is present (see Section “8.2. VBUS Detection” on page 67 for details on VBUS detection).
Note: The USB clock should be active before the Transceiver is enabled.

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SFR Definition 15.1. USB0XCN: USB0 Transceiver Control
R/W

R/W

PREN

PHYEN

SPEED

Bit7

Bit6

Bit5

R/W

PHYTST1 PHYTST0
Bit4

Reset Value

DFREC

00000000

Bit2

Bit1

Bit0

SFR Address:

Bit3

0xD7
Bit7:

PREN: Internal Pull-up Resistor Enable
The location of the pull-up resistor (D+ or D–) is determined by the SPEED bit.
0: Internal pull-up resistor disabled (device effectively detached from the USB network).
1: Internal pull-up resistor enabled when VBUS is present (device attached to the USB network).
Bit6:
PHYEN: Physical Layer Enable
This bit enables/disables the USB0 physical layer transceiver.
0: Transceiver disabled (suspend).
1: Transceiver enabled (normal).
Bit5:
SPEED: USB0 Speed Select
This bit selects the USB0 speed.
0: USB0 operates as a Low Speed device. If enabled, the internal pull-up resistor appears
on the D– line.
1: USB0 operates as a Full Speed device. If enabled, the internal pull-up resistor appears on
the D+ line.
Bits4–3: PHYTST1–0: Physical Layer Test
These bits can be used to test the USB0 transceiver.
PHYTST[1:0]
00b
01b
10b
11b
Bit2:

Bit1:

Bit0:

Mode
Mode 0: Normal (non-test mode)
Mode 1: Differential ‘1’ Forced
Mode 2: Differential ‘0’ Forced
Mode 3: Single-Ended ‘0’ Forced

D+
X
1
0
0

D–
X
0
1
0

DFREC: Differential Receiver
The state of this bit indicates the current differential value present on the D+ and D– lines
when PHYEN = ‘1’.
0: Differential ‘0’ signaling on the bus.
1: Differential ‘1’ signaling on the bus.
Dp: D+ Signal Status
This bit indicates the current logic level of the D+ pin.
0: D+ signal currently at logic 0.
1: D+ signal currently at logic 1.
Dn: D- Signal Status
This bit indicates the current logic level of the D– pin.
0: D– signal currently at logic 0.
1: D– signal currently at logic 1.

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15.3. USB Register Access
The USB0 controller registers listed in Table 15.2 are accessed through two SFRs: USB0 Address
(USB0ADR) and USB0 Data (USB0DAT). The USB0ADR register selects which USB register is targeted
by reads/writes of the USB0DAT register. See Figure 15.2.
Endpoint control/status registers are accessed by first writing the USB register INDEX with the target endpoint number. Once the target endpoint number is written to the INDEX register, the control/status registers
associated with the target endpoint may be accessed. See the “Indexed Registers” section of Table 15.2
for a list of endpoint control/status registers.
Note: The USB clock must be active when accessing USB registers.
8051
SFRs

USB Controller
Interrupt
Registers
FIFO
Access
Common
Registers
Index
Register

USB0DAT

Endpoint0 Control/
Status Registers
Endpoint1 Control/
Status Registers
Endpoint2 Control/
Status Registers
USB0ADR
Endpoint3 Control/
Status Registers

Figure 15.2. USB0 Register Access Scheme

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SFR Definition 15.2. USB0ADR: USB0 Indirect Address
R/W

R/W

BUSY

AUTORD

Bit7

Bit6

R/W

Bit5

Bit4

Bit3

R/W

Reset Value

Bit1

Bit0

SFR Address:

USBADDR
Bit2

00000000
0x96

Bits7:

BUSY: USB0 Register Read Busy Flag
This bit is used during indirect USB0 register accesses. Software should write ‘1’ to this bit to
initiate a read of the USB0 register targeted by the USBADDR bits (USB0ADR.[5-0]). The
target address and BUSY bit may be written in the same write to USB0ADR. After BUSY is
set to ‘1’, hardware will clear BUSY when the targeted register data is ready in the USB0DAT register. Software should check BUSY for ‘0’ before writing to USB0DAT.
Write:
0: No effect.
1: A USB0 indirect register read is initiated at the address specified by the USBADDR bits.
Read:
0: USB0DAT register data is valid.
1: USB0 is busy accessing an indirect register; USB0DAT register data is invalid.
Bit6:
AUTORD: USB0 Register Auto-read Flag
This bit is used for block FIFO reads.
0: BUSY must be written manually for each USB0 indirect register read.
1: The next indirect register read will automatically be initiated when software reads USB0DAT (USBADDR bits will not be changed).
Bits5–0: USBADDR: USB0 Indirect Register Address
These bits hold a 6-bit address used to indirectly access the USB0 core registers. Table 15.2
lists the USB0 core registers and their indirect addresses. Reads and writes to USB0DAT
will target the register indicated by the USBADDR bits.

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SFR Definition 15.3. USB0DAT: USB0 Data
R/W

R/W

Bit7

Bit6

Bit5

Bit4

R/W

Reset Value

Bit2

Bit1

Bit0

SFR Address:

USB0DAT

00000000

Bit3

0x97
This SFR is used to indirectly read and write USB0 registers.
Write Procedure:
1. Poll for BUSY (USB0ADR.7) => ‘0’.
2. Load the target USB0 register address into the USBADDR bits in register USB0ADR.
3. Write data to USB0DAT.
4. Repeat (Step 2 may be skipped when writing to the same USB0 register).
Read Procedure:
1. Poll for BUSY (USB0ADR.7) => ‘0’.
2. Load the target USB0 register address into the USBADDR bits in register USB0ADR.
3. Write ‘1’ to the BUSY bit in register USB0ADR (steps 2 and 3 can be performed in the
same write).
4. Poll for BUSY (USB0ADR.7) => ‘0’.
5. Read data from USB0DAT.
6. Repeat from Step 2 (Step 2 may be skipped when reading the same USB0 register; Step 3
may be skipped when the AUTORD bit (USB0ADR.6) is logic 1).

Table 15.2. USB0 Controller Registers
USB Register
Name

USB Register
Address

Description

Page Number

Interrupt Registers
IN1INT

0x02

Endpoint0 and Endpoints1-3 IN Interrupt Flags

153

OUT1INT

0x04

Endpoints1-3 OUT Interrupt Flags

154

CMINT

0x06

Common USB Interrupt Flags

155

IN1IE

0x07

Endpoint0 and Endpoints1-3 IN Interrupt Enables

156

OUT1IE

0x09

Endpoints1-3 OUT Interrupt Enables

156

CMIE

0x0B

Common USB Interrupt Enables

157

Common Registers
FADDR

144

0x00

Function Address

149

POWER

0x01

Power Management

151

FRAMEL

0x0C

Frame Number Low Byte

152

FRAMEH

0x0D

Frame Number High Byte

152

INDEX

0x0E

Endpoint Index Selection

145

CLKREC

0x0F

Clock Recovery Control

146

FIFOn

0x20-0x23

Endpoints0-3 FIFOs

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Table 15.2. USB0 Controller Registers (Continued)
USB Register
Name

USB Register
Address

Description

Page Number

Indexed Registers
E0CSR

0x11

EINCSRL

Endpoint0 Control / Status

160

Endpoint IN Control / Status Low Byte

163

EINCSRH

0x12

Endpoint IN Control / Status High Byte

164

EOUTCSRL

0x14

Endpoint OUT Control / Status Low Byte

166

EOUTCSRH

0x15

Endpoint OUT Control / Status High Byte

167

Number of Received Bytes in Endpoint0 FIFO

161

Endpoint OUT Packet Count Low Byte

167

Endpoint OUT Packet Count High Byte

167

E0CNT

0x16

EOUTCNTL
EOUTCNTH

0x17

USB Register Definition 15.4. INDEX: USB0 Endpoint Index
R

Bit7

Bit6

Bit5

Bit4

R/W

Bit3

Bit2

R/W

Reset Value

Bit1

Bit0

USB Address:

EPSEL

00000000
0x0E

Bits7–4: Unused. Read = 0000b; Write = don’t care.
Bits3–0: EPSEL: Endpoint Select
These bits select which endpoint is targeted when indexed USB0 registers are accessed.
INDEX
0x0
0x1
0x2
0x3
0x4–0xF

Target Endpoint
0
1
2
3
Reserved

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15.4. USB Clock Configuration
USB0 is capable of communication as a Full or Low Speed USB function. Communication speed is
selected via the SPEED bit in SFR USB0XCN. When operating as a Low Speed function, the USB0 clock
must be 6 MHz. When operating as a Full Speed function, the USB0 clock must be 48 MHz. Clock options
are described in Section “13. Oscillators” on page 116. The USB0 clock is selected via SFR CLKSEL (see
Figure 13.5 on Page 124).
Clock Recovery circuitry uses the incoming USB data stream to adjust the internal oscillator; this allows
the internal oscillator (and 4x Clock Multiplier) to meet the requirements for USB clock tolerance. Clock
Recovery should be used in the following configurations:
Communication Speed

USB Clock

4x Clock Multiplier Input

Full Speed

4x Clock Multiplier

Internal Oscillator

Low Speed

Internal Oscillator/2

N/A

When operating USB0 as a Low Speed function with Clock Recovery, software must write ‘1’ to the
CRLOW bit to enable Low Speed Clock Recovery. Clock Recovery is typically not necessary in Low Speed
mode.
Single Step Mode can be used to help the Clock Recovery circuitry to lock when high noise levels are present on the USB network. This mode is not required (or recommended) in typical USB environments.

USB Register Definition 15.5. CLKREC: Clock Recovery Control
R/W

R/W

CRE

CRSSEN

CRLOW

Bit7

Bit6

Bit5

R/W

Reserved
Bit4

Bit3

Bit2

Reset Value

00001001
Bit1

Bit0

USB Address:

0x0F
Bit7:

CRE: Clock Recovery Enable.
This bit enables/disables the USB clock recovery feature.
0: Clock recovery disabled.
1: Clock recovery enabled.
Bit6:
CRSSEN: Clock Recovery Single Step.
This bit forces the oscillator calibration into ‘single-step’ mode during clock recovery.
0: Normal calibration mode.
1: Single step mode.
Bit5:
CRLOW: Low Speed Clock Recovery Mode.
This bit must be set to ‘1’ if clock recovery is used when operating as a Low Speed USB
device.
0: Full Speed Mode.
1: Low Speed Mode.
Bits4–0: Reserved. Read = Variable. Must Write = 1001b.

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15.5. FIFO Management
1024 bytes of on-chip XRAM are used as FIFO space for USB0. This FIFO space is split between Endpoints0-3 as shown in Figure 15.3. FIFO space allocated for Endpoints1-3 is configurable as IN, OUT, or
both (Split Mode: half IN, half OUT).

0x07FF
Endpoint0
(64 bytes)
0x07C0
0x07BF
Endpoint1
(128 bytes)
0x0740
0x073F
Configurable as
IN, OUT, or both (Split
Mode)

Endpoint2
(256 bytes)
0x0640
0x063F

Endpoint3
(512 bytes)

0x0440
0x043F
Free
(64 bytes)
0x0400
USB Clock Domain
System Clock Domain
0x03FF
User XRAM
(1024 bytes)
0x0000

Figure 15.3. USB FIFO Allocation
15.5.1. FIFO Split Mode
The FIFO space for Endpoints1-3 can be split such that the upper half of the FIFO space is used by the IN
endpoint, and the lower half is used by the OUT endpoint. For example: if the Endpoint3 FIFO is configured
for Split Mode, the upper 256 bytes (0x0540 to 0x063F) are used by Endpoint3 IN and the lower 256 bytes
(0x0440 to 0x053F) are used by Endpoint3 OUT.
If an endpoint FIFO is not configured for Split Mode, that endpoint IN/OUT pair’s FIFOs are combined to
form a single IN or OUT FIFO. In this case only one direction of the endpoint IN/OUT pair may be used at
a time. The endpoint direction (IN/OUT) is determined by the DIRSEL bit in the corresponding endpoint’s
EINCSRH register (see Figure 15.20).

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15.5.2. FIFO Double Buffering
FIFO slots for Endpoints1-3 can be configured for double-buffered mode. In this mode, the maximum
packet size is halved and the FIFO may contain two packets at a time. This mode is available for Endpoints1-3. When an endpoint is configured for Split Mode, double buffering may be enabled for the IN Endpoint and/or the OUT endpoint. When Split Mode is not enabled, double-buffering may be enabled for the
entire endpoint FIFO. See Table 15.3 for a list of maximum packet sizes for each FIFO configuration.

Table 15.3. FIFO Configurations
Endpoint
Number
0
1
2
3

Split Mode Maximum IN Packet Size (Double Maximum OUT Packet Size (Double
Enabled?
Buffer Disabled/Enabled)
Buffer Disabled/Enabled)
N/A
64
N
128/64
Y
64/32
64/32
N
256/128
Y
128/64
128/64
N
512/256
Y
256/128
256/128

15.5.1. FIFO Access
Each endpoint FIFO is accessed through a corresponding FIFOn register. A read of an endpoint FIFOn
register unloads one byte from the FIFO; a write of an endpoint FIFOn register loads one byte into the endpoint FIFO. When an endpoint FIFO is configured for Split Mode, a read of the endpoint FIFOn register
unloads one byte from the OUT endpoint FIFO; a write of the endpoint FIFOn register loads one byte into
the IN endpoint FIFO.

USB Register Definition 15.6. FIFOn: USB0 Endpoint FIFO Access
R/W

R/W

FIFODATA
Bit7

Bit6

Bit5

Bit4

Bit3

Reset Value

00000000
Bit2

Bit1

Bit0

USB Address:

0x20 - 0x23
USB Addresses 0x20–0x23 provide access to the 4 pairs of endpoint FIFOs:
IN/OUT Endpoint FIFO
0
1
2
3

USB Address
0x20
0x21
0x22
0x23

Writing to the FIFO address loads data into the IN FIFO for the corresponding endpoint.
Reading from the FIFO address unloads data from the OUT FIFO for the corresponding
endpoint.

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15.6. Function Addressing
The FADDR register holds the current USB0 function address. Software should write the host-assigned
7-bit function address to the FADDR register when received as part of a SET_ADDRESS command. A new
address written to FADDR will not take effect (USB0 will not respond to the new address) until the end of
the current transfer (typically following the status phase of the SET_ADDRESS command transfer). The
UPDATE bit (FADDR.7) is set to ‘1’ by hardware when software writes a new address to the FADDR register. Hardware clears the UPDATE bit when the new address takes effect as described above.

USB Register Definition 15.7. FADDR: USB0 Function Address
R

R/W

Update
Bit7

R/W

Function Address
Bit6

Bit5

Bit4

Bit3

Reset Value

00000000
Bit2

Bit1

Bit0

USB Address:

0x00
Bit7:

Update: Function Address Update
Set to ‘1’ when software writes the FADDR register. USB0 clears this bit to ‘0’ when the new
address takes effect.
0: The last address written to FADDR is in effect.
1: The last address written to FADDR is not yet in effect.
Bits6–0: Function Address
Holds the 7-bit function address for USB0. This address should be written by software when
the SET_ADDRESS standard device request is received on Endpoint0. The new address
takes effect when the device request completes.

15.7. Function Configuration and Control
The USB register POWER (Figure 15.8) is used to configure and control USB0 at the device level (enable/
disable, Reset/Suspend/Resume handling, etc.).
USB Reset: The USBRST bit (POWER.3) is set to ‘1’ by hardware when Reset signaling is detected on
the bus. Upon this detection, the following occur:
1. The USB0 Address is reset (FADDR = 0x00).
2. Endpoint FIFOs are flushed.
3. Control/status registers are reset to 0x00 (E0CSR, EINCSRL, EINCSRH, EOUTCSRL,
EOUTCSRH).
4. USB register INDEX is reset to 0x00.
5. All USB interrupts (excluding the Suspend interrupt) are enabled and their corresponding flags
cleared.
6. A USB Reset interrupt is generated if enabled.
Writing a ‘1’ to the USBRST bit will generate an asynchronous USB0 reset. All USB registers are reset to
their default values following this asynchronous reset.
Suspend Mode: With Suspend Detection enabled (SUSEN = ‘1’), USB0 will enter Suspend Mode when
Suspend signaling is detected on the bus. An interrupt will be generated if enabled (SUSINTE = ‘1’). The
Suspend Interrupt Service Routine (ISR) should perform application-specific configuration tasks such as

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disabling appropriate peripherals and/or configuring clock sources for low power modes. See Section
“13. Oscillators” on page 116 for more details on internal oscillator configuration, including the Suspend
mode feature of the internal oscillator.
USB0 exits Suspend mode when any of the following occur: (1) Resume signaling is detected or generated, (2) Reset signaling is detected, or (3) a device or USB reset occurs. If suspended, the internal oscillator will exit Suspend mode upon any of the above listed events.
Resume Signaling: USB0 will exit Suspend mode if Resume signaling is detected on the bus. A Resume
interrupt will be generated upon detection if enabled (RESINTE = ‘1’). Software may force a Remote
Wakeup by writing ‘1’ to the RESUME bit (POWER.2). When forcing a Remote Wakeup, software should
write RESUME = ‘0’ to end Resume signaling 10-15 ms after the Remote Wakeup is initiated (RESUME =
‘1’).
ISO Update: When software writes ‘1’ to the ISOUP bit (POWER.7), the ISO Update function is enabled.
With ISO Update enabled, new packets written to an ISO IN endpoint will not be transmitted until a new
Start-Of-Frame (SOF) is received. If the ISO IN endpoint receives an IN token before a SOF, USB0 will
transmit a zero-length packet. When ISOUP = ‘1’, ISO Update is enabled for all ISO endpoints.
USB Enable: USB0 is disabled following a Power-On-Reset (POR). USB0 is enabled by clearing the
USBINH bit (POWER.4). Once written to ‘0’, the USBINH can only be set to ‘1’ by one of the following: (1)
a Power-On-Reset (POR), or (2) an asynchronous USB0 reset generated by writing ‘1’ to the USBRST bit
(POWER.3).
Software should perform all USB0 configuration before enabling USB0. The configuration sequence
should be performed as follows:
Step 1.
Step 2.
Step 3.
Step 4.
Step 5.

150

Select and enable the USB clock source.
Reset USB0 by writing USBRST= ‘1’.
Configure and enable the USB Transceiver.
Perform any USB0 function configuration (interrupts, Suspend detect).
Enable USB0 by writing USBINH = ‘0’.

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USB Register Definition 15.8. POWER: USB0 Power
R/W

R/W

ISOUD

USBINH

Bit7

Bit6

Bit5

Bit4

R/W

USBRST RESUME
Bit3

Bit2

R/W

Reset Value

SUSMD

SUSEN

00010000

Bit1

Bit0

USB Address:

0x01
Bit7:

ISOUD: ISO Update
This bit affects all IN Isochronous endpoints.
0: When software writes INPRDY = ‘1’, USB0 will send the packet when the next IN token is
received.
1: When software writes INPRDY = ‘1’, USB0 will wait for a SOF token before sending the
packet. If an IN token is received before a SOF token, USB0 will send a zero-length data
packet.
Bits6–5: Unused. Read = 00b. Write = don’t care.
Bit4:
USBINH: USB0 Inhibit
This bit is set to ‘1’ following a power-on reset (POR) or an asynchronous USB0 reset (see
Bit3: RESET). Software should clear this bit after all USB0 and transceiver initialization is
complete. Software cannot set this bit to ‘1’.
0: USB0 enabled.
1: USB0 inhibited. All USB traffic is ignored.
Bit3:
USBRST: Reset Detect
Writing ‘1’ to this bit forces an asynchronous USB0 reset. Reading this bit provides bus reset
status information.
Read:
0: Reset signaling is not present on the bus.
1: Reset signaling detected on the bus.
Bit2:
RESUME: Force Resume
Software can force resume signaling on the bus to wake USB0 from suspend mode. Writing
a ‘1’ to this bit while in Suspend mode (SUSMD = ‘1’) forces USB0 to generate Resume signaling on the bus (a remote Wakeup event). Software should write RESUME = ‘0’ after
10 ms to15 ms to end the Resume signaling. An interrupt is generated, and hardware clears
SUSMD, when software writes RESUME = ‘0’.
Bit1:
SUSMD: Suspend Mode
Set to ‘1’ by hardware when USB0 enters suspend mode. Cleared by hardware when software writes RESUME = ‘0’ (following a remote wakeup) or reads the CMINT register after
detection of Resume signaling on the bus.
0: USB0 not in suspend mode.
1: USB0 in suspend mode.
Bit0:
SUSEN: Suspend Detection Enable
0: Suspend detection disabled. USB0 will ignore suspend signaling on the bus.
1: Suspend detection enabled. USB0 will enter suspend mode if it detects suspend signaling
on the bus.

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USB Register Definition 15.9. FRAMEL: USB0 Frame Number Low
R

Bit7

Bit6

Bit5

Reset Value

Bit2

Bit1

Bit0

USB Address:

Frame Number Low
Bit4

Bit3

00000000
0x0C

Bits7-0:

Frame Number Low
This register contains bits7-0 of the last received frame number.

USB Register Definition 15.10. FRAMEH: USB0 Frame Number High
R

Bit7

Bit6

Bit5

Bit4

Bit3

Reset Value

Bit0

USB Address:

Frame Number High
Bit2

Bit1

00000000
0x0D

Bits7-3:
Bits2-0:

Unused. Read = 0. Write = don’t care.
Frame Number High Byte
This register contains bits10-8 of the last received frame number.

15.8. Interrupts
The read-only USB0 interrupt flags are located in the USB registers shown in Figure 15.11 through
Figure 15.13. The associated interrupt enable bits are located in the USB registers shown in Figure 15.14
through Figure 15.16. A USB0 interrupt is generated when any of the USB interrupt flags is set to ‘1’. The
USB0 interrupt is enabled via the EIE1 SFR (see Section “9.3. Interrupt Handler” on page 87).
Note: Reading a USB interrupt flag register resets all flags in that register to ‘0’.

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USB Register Definition 15.11. IN1INT: USB0 IN Endpoint Interrupt
R

Reset Value

IN3

IN2

IN1

EP0

00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

USB Address:

0x02
Bits7–4: Unused. Read = 0000b. Write = don’t care.
Bit3:
IN3: IN Endpoint 3 Interrupt-pending Flag
This bit is cleared when software reads the IN1INT register.
0: IN Endpoint 3 interrupt inactive.
1: IN Endpoint 3 interrupt active.
Bit2:
IN2: IN Endpoint 2 Interrupt-pending Flag
This bit is cleared when software reads the IN1INT register.
0: IN Endpoint 2 interrupt inactive.
1: IN Endpoint 2 interrupt active.
Bit1:
IN1: IN Endpoint 1 Interrupt-pending Flag
This bit is cleared when software reads the IN1INT register.
0: IN Endpoint 1 interrupt inactive.
1: IN Endpoint 1 interrupt active.
Bit0:
EP0: Endpoint 0 Interrupt-pending Flag
This bit is cleared when software reads the IN1INT register.
0: Endpoint 0 interrupt inactive.
1: Endpoint 0 interrupt active.

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USB Register Definition 15.12. OUT1INT: USB0 Out Endpoint Interrupt
R

Reset Value

OUT3

OUT2

OUT1

00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

USB Address:

0x04
Bits7–4: Unused. Read = 0000b. Write = don’t care.
Bit3:
OUT3: OUT Endpoint 3 Interrupt-pending Flag
This bit is cleared when software reads the OUT1INT register.
0: OUT Endpoint 3 interrupt inactive.
1: OUT Endpoint 3 interrupt active.
Bit2:
OUT2: OUT Endpoint 2 Interrupt-pending Flag
This bit is cleared when software reads the OUT1INT register.
0: OUT Endpoint 2 interrupt inactive.
1: OUT Endpoint 2 interrupt active.
Bit1:
OUT1: OUT Endpoint 1 Interrupt-pending Flag
This bit is cleared when software reads the OUT1INT register.
0: OUT Endpoint 1 interrupt inactive.
1: OUT Endpoint 1 interrupt active.
Bit0:
Unused. Read = 0b; Write = don’t care.

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USB Register Definition 15.13. CMINT: USB0 Common Interrupt
R

Reset Value

SOF

RSTINT

RSUINT

SUSINT

00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

USB Address:

0x06
Bits7–4: Unused. Read = 0000b; Write = don’t care.
Bit3:
SOF: Start of Frame Interrupt
Set by hardware when a SOF token is received. This interrupt event is synthesized by hardware: an interrupt will be generated when hardware expects to receive a SOF event, even if
the actual SOF signal is missed or corrupted.
This bit is cleared when software reads the CMINT register.
0: SOF interrupt inactive.
1: SOF interrupt active.
Bit2:
RSTINT: Reset Interrupt-pending Flag
Set by hardware when Reset signaling is detected on the bus.
This bit is cleared when software reads the CMINT register.
0: Reset interrupt inactive.
1: Reset interrupt active.
Bit1:
RSUINT: Resume Interrupt-pending Flag
Set by hardware when Resume signaling is detected on the bus while USB0 is in suspend
mode.
This bit is cleared when software reads the CMINT register.
0: Resume interrupt inactive.
1: Resume interrupt active.
Bit0:
SUSINT: Suspend Interrupt-pending Flag
When Suspend detection is enabled (bit SUSEN in register POWER), this bit is set by hardware when Suspend signaling is detected on the bus. This bit is cleared when software
reads the CMINT register.
0: Suspend interrupt inactive.
1: Suspend interrupt active.

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USB Register Definition 15.14. IN1IE: USB0 IN Endpoint Interrupt Enable
R/W

R/W

IN3E

IN2E

IN1E

EP0E

Reset Value

00001111

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

USB Address:

0x07
Bits7–4: Unused. Read = 0000b. Write = don’t care.
Bit3:
IN3E: IN Endpoint 3 Interrupt Enable
0: IN Endpoint 3 interrupt disabled.
1: IN Endpoint 3 interrupt enabled.
Bit2:
IN2E: IN Endpoint 2 Interrupt Enable
0: IN Endpoint 2 interrupt disabled.
1: IN Endpoint 2 interrupt enabled.
Bit1:
IN1E: IN Endpoint 1 Interrupt Enable
0: IN Endpoint 1 interrupt disabled.
1: IN Endpoint 1 interrupt enabled.
Bit0:
EP0E: Endpoint 0 Interrupt Enable
0: Endpoint 0 interrupt disabled.
1: Endpoint 0 interrupt enabled.

USB Register Definition 15.15. OUT1IE: USB0 Out Endpoint Interrupt Enable
R/W

R/W

Reset Value

OUT3E

OUT2E

OUT1E

00001110

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

USB
Address:

0x09
Bits7–4: Unused. Read = 0000b. Write = don’t care.
Bit3:
OUT3E: OUT Endpoint 3 Interrupt Enable
0: OUT Endpoint 3 interrupt disabled.
1: OUT Endpoint 3 interrupt enabled.
Bit2:
OUT2E: OUT Endpoint 2 Interrupt Enable
0: OUT Endpoint 2 interrupt disabled.
1: OUT Endpoint 2 interrupt enabled.
Bit1:
OUT1E: OUT Endpoint 1 Interrupt Enable
0: OUT Endpoint 1 interrupt disabled.
1: OUT Endpoint 1 interrupt enabled.
Bit0:
Unused. Read = 0b; Write = don’t’ care.

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USB Register Definition 15.16. CMIE: USB0 Common Interrupt Enable
R/W

R/W

SOFE

Bit7

Bit6

Bit5

Bit4

Bit3

R/W

Reset Value

RSTINTE RSUINTE SUSINTE 00000110
Bit2

Bit1

Bit0

USB Address:

0x0B
Bits7–4: Unused. Read = 0000b; Write = don’t care.
Bit3:
SOFE: Start of Frame Interrupt Enable
0: SOF interrupt disabled.
1: SOF interrupt enabled.
Bit2:
RSTINTE: Reset Interrupt Enable
0: Reset interrupt disabled.
1: Reset interrupt enabled.
Bit1:
RSUINTE: Resume Interrupt Enable
0: Resume interrupt disabled.
1: Resume interrupt enabled.
Bit0:
SUSINTE: Suspend Interrupt Enable
0: Suspend interrupt disabled.
1: Suspend interrupt enabled.

15.9. The Serial Interface Engine
The Serial Interface Engine (SIE) performs all low level USB protocol tasks, interrupting the processor
when data has successfully been transmitted or received. When receiving data, the SIE will interrupt the
processor when a complete data packet has been received; appropriate handshaking signals are automatically generated by the SIE. When transmitting data, the SIE will interrupt the processor when a complete
data packet has been transmitted and the appropriate handshake signal has been received.
The SIE will not interrupt the processor when corrupted/erroneous packets are received.

15.10. Endpoint0
Endpoint0 is managed through the USB register E0CSR (Figure 15.17). The INDEX register must be
loaded with 0x00 to access the E0CSR register.
An Endpoint0 interrupt is generated when:
1. A data packet (OUT or SETUP) has been received and loaded into the Endpoint0 FIFO. The
OPRDY bit (E0CSR.0) is set to ‘1’ by hardware.
2. An IN data packet has successfully been unloaded from the Endpoint0 FIFO and transmitted
to the host; INPRDY is reset to ‘0’ by hardware.
3. An IN transaction is completed (this interrupt generated during the status stage of the transaction).
4. Hardware sets the STSTL bit (E0CSR.2) after a control transaction ended due to a protocol
violation.
5. Hardware sets the SUEND bit (E0CSR.4) because a control transfer ended before firmware
sets the DATAEND bit (E0CSR.3).

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The E0CNT register (Figure 15.18) holds the number of received data bytes in the Endpoint0 FIFO.
Hardware will automatically detect protocol errors and send a STALL condition in response. Firmware may
force a STALL condition to abort the current transfer. When a STALL condition is generated, the STSTL bit
will be set to ‘1’ and an interrupt generated. The following conditions will cause hardware to generate a
STALL condition:
1. The host sends an OUT token during a OUT data phase after the DATAEND bit has been set
to ‘1’.
2. The host sends an IN token during an IN data phase after the DATAEND bit has been set to
‘1’.
3. The host sends a packet that exceeds the maximum packet size for Endpoint0.
4. The host sends a non-zero length DATA1 packet during the status phase of an IN transaction.
Firmware sets the SDSTL bit (E0CSR.5) to ‘1’.

15.10.1.Endpoint0 SETUP Transactions
All control transfers must begin with a SETUP packet. SETUP packets are similar to OUT packets, containing an 8-byte data field sent by the host. Any SETUP packet containing a command field of anything other
than 8 bytes will be automatically rejected by USB0. An Endpoint0 interrupt is generated when the data
from a SETUP packet is loaded into the Endpoint0 FIFO. Software should unload the command from the
Endpoint0 FIFO, decode the command, perform any necessary tasks, and set the SOPRDY bit to indicate
that it has serviced the OUT packet.

15.10.2.Endpoint0 IN Transactions
When a SETUP request is received that requires USB0 to transmit data to the host, one or more IN
requests will be sent by the host. For the first IN transaction, firmware should load an IN packet into the
Endpoint0 FIFO, and set the INPRDY bit (E0CSR.1). An interrupt will be generated when an IN packet is
transmitted successfully. Note that no interrupt will be generated if an IN request is received before firmware has loaded a packet into the Endpoint0 FIFO. If the requested data exceeds the maximum packet
size for Endpoint0 (as reported to the host), the data should be split into multiple packets; each packet
should be of the maximum packet size excluding the last (residual) packet. If the requested data is an integer multiple of the maximum packet size for Endpoint0, the last data packet should be a zero-length packet
signaling the end of the transfer. Firmware should set the DATAEND bit to ‘1’ after loading into the Endpoint0 FIFO the last data packet for a transfer.
Upon reception of the first IN token for a particular control transfer, Endpoint0 is said to be in Transmit
Mode. In this mode, only IN tokens should be sent by the host to Endpoint0. The SUEND bit (E0CSR.4) is
set to ‘1’ if a SETUP or OUT token is received while Endpoint0 is in Transmit Mode.
Endpoint0 will remain in Transmit Mode until any of the following occur:
1. USB0 receives an Endpoint0 SETUP or OUT token.
2. Firmware sends a packet less than the maximum Endpoint0 packet size.
3. Firmware sends a zero-length packet.
Firmware should set the DATAEND bit (E0CSR.3) to ‘1’ when performing (2) and (3) above.
The SIE will transmit a NAK in response to an IN token if there is no packet ready in the IN FIFO (INPRDY
= ‘0’).

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15.10.3.Endpoint0 OUT Transactions
When a SETUP request is received that requires the host to transmit data to USB0, one or more OUT
requests will be sent by the host. When an OUT packet is successfully received by USB0, hardware will set
the OPRDY bit (E0CSR.0) to ‘1’ and generate an Endpoint0 interrupt. Following this interrupt, firmware
should unload the OUT packet from the Endpoint0 FIFO and set the SOPRDY bit (E0CSR.6) to ‘1’.
If the amount of data required for the transfer exceeds the maximum packet size for Endpoint0, the data
will be split into multiple packets. If the requested data is an integer multiple of the maximum packet size
for Endpoint0 (as reported to the host), the host will send a zero-length data packet signaling the end of the
transfer.
Upon reception of the first OUT token for a particular control transfer, Endpoint0 is said to be in Receive
Mode. In this mode, only OUT tokens should be sent by the host to Endpoint0. The SUEND bit (E0CSR.4)
is set to ‘1’ if a SETUP or IN token is received while Endpoint0 is in Receive Mode.
Endpoint0 will remain in Receive mode until:
1. The SIE receives a SETUP or IN token.
2. The host sends a packet less than the maximum Endpoint0 packet size.
3. The host sends a zero-length packet.
Firmware should set the DATAEND bit (E0CSR.3) to ‘1’ when the expected amount of data has been
received. The SIE will transmit a STALL condition if the host sends an OUT packet after the DATAEND bit
has been set by firmware. An interrupt will be generated with the STSTL bit (E0CSR.2) set to ‘1’ after the
STALL is transmitted.

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USB Register Definition 15.17. E0CSR: USB0 Endpoint0 Control
R/W

R/W

SSUEND SOPRDY
Bit7

Bit6

R/W

SDSTL
Bit5

R/W

SUEND DATAEND
Bit4

Bit3

R/W

Reset Value

STSTL

INPRDY

OPRDY

00000000

Bit2

Bit1

Bit0

USB Address:

0x11
Bit7:

Bit6:

Bit5:

Bit4:

Bit3:

Bit2:

Bit1:

Bit0:

160

SSUEND: Serviced Setup End
Write: Software should set this bit to ‘1’ after servicing a Setup End (bit SUEND) event.
Hardware clears the SUEND bit when software writes ‘1’ to SSUEND.
Read: This bit always reads ‘0’.
SOPRDY: Serviced OPRDY
Write: Software should write ‘1’ to this bit after servicing a received Endpoint0 packet. The
OPRDY bit will be cleared by a write of ‘1’ to SOPRDY.
Read: This bit always reads ‘0’.
SDSTL: Send Stall
Software can write ‘1’ to this bit to terminate the current transfer (due to an error condition,
unexpected transfer request, etc.). Hardware will clear this bit to ‘0’ when the STALL handshake is transmitted.
SUEND: Setup End
Hardware sets this read-only bit to ‘1’ when a control transaction ends before software has
written ‘1’ to the DATAEND bit. Hardware clears this bit when software writes ‘1’ to SSUEND.
DATAEND: Data End
Software should write ‘1’ to this bit:
1. When writing ‘1’ to INPRDY for the last outgoing data packet.
2. When writing ‘1’ to INPRDY for a zero-length data packet.
3. When writing ‘1’ to SOPRDY after servicing the last incoming data packet.
This bit is automatically cleared by hardware.
STSTL: Sent Stall
Hardware sets this bit to ‘1’ after transmitting a STALL handshake signal. This flag must be
cleared by software.
INPRDY: IN Packet Ready
Software should write ‘1’ to this bit after loading a data packet into the Endpoint0 FIFO for
transmit. Hardware clears this bit and generates an interrupt under either of the following
conditions:
1. The packet is transmitted.
2. The packet is overwritten by an incoming SETUP packet.
3. The packet is overwritten by an incoming OUT packet.
OPRDY: OUT Packet Ready
Hardware sets this read-only bit and generates an interrupt when a data packet has been
received. This bit is cleared only when software writes ‘1’ to the SOPRDY bit.

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USB Register Definition 15.18. E0CNT: USB0 Endpoint 0 Data Count
R

Bit6

Bit5

Bit4

Bit7

Reset Value

Bit2

Bit1

Bit0

USB Address:

E0CNT
Bit3

00000000
0x16

Bit7:
Unused. Read = 0b; Write = don’t care.
Bits6–0: E0CNT: Endpoint 0 Data Count
This 7-bit number indicates the number of received data bytes in the Endpoint 0 FIFO. This
number is only valid while bit OPRDY is a ‘1’.

15.11. Configuring Endpoints1–3
Endpoints1-3 are configured and controlled through their own sets of the following control/status registers:
IN registers EINCSRL and EINCSRH, and OUT registers EOUTCSRL and EOUTCSRH. Only one set of
endpoint control/status registers is mapped into the USB register address space at a time, defined by the
contents of the INDEX register (Figure 15.4).
Endpoints1-3 can be configured as IN, OUT, or both IN/OUT (Split Mode) as described in Section 15.5.1.
The endpoint mode (Split/Normal) is selected via the SPLIT bit in register EINCSRH.
When SPLIT = ‘1’, the corresponding endpoint FIFO is split, and both IN and OUT pipes are available.
When SPLIT = ‘0’, the corresponding endpoint functions as either IN or OUT; the endpoint direction is
selected by the DIRSEL bit in register EINCSRH.

15.12. Controlling Endpoints1–3 IN
Endpoints1-3 IN are managed via USB registers EINCSRL and EINCSRH. All IN endpoints can be used
for Interrupt, Bulk, or Isochronous transfers. Isochronous (ISO) mode is enabled by writing ‘1’ to the ISO bit
in register EINCSRH. Bulk and Interrupt transfers are handled identically by hardware.
An Endpoint1-3 IN interrupt is generated by any of the following conditions:
1. An IN packet is successfully transferred to the host.
2. Software writes ‘1’ to the FLUSH bit (EINCSRL.3) when the target FIFO is not empty.
3. Hardware generates a STALL condition.

15.12.1.Endpoints1-3 IN Interrupt or Bulk Mode
When the ISO bit (EINCSRH.6) = ‘0’ the target endpoint operates in Bulk or Interrupt Mode. Once an endpoint has been configured to operate in Bulk/Interrupt IN mode (typically following an Endpoint0 SET_INTERFACE command), firmware should load an IN packet into the endpoint IN FIFO and set the INPRDY
bit (EINCSRL.0). Upon reception of an IN token, hardware will transmit the data, clear the INPRDY bit, and
generate an interrupt.
Writing ‘1’ to INPRDY without writing any data to the endpoint FIFO will cause a zero-length packet to be
transmitted upon reception of the next IN token.

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A Bulk or Interrupt pipe can be shut down (or Halted) by writing ‘1’ to the SDSTL bit (EINCSRL.4). While
SDSTL = ‘1’, hardware will respond to all IN requests with a STALL condition. Each time hardware generates a STALL condition, an interrupt will be generated and the STSTL bit (EINCSRL.5) set to ‘1’. The
STSTL bit must be reset to ‘0’ by firmware.
Hardware will automatically reset INPRDY to ‘0’ when a packet slot is open in the endpoint FIFO. Note that
if double buffering is enabled for the target endpoint, it is possible for firmware to load two packets into the
IN FIFO at a time. In this case, hardware will reset INPRDY to ‘0’ immediately after firmware loads the first
packet into the FIFO and sets INPRDY to ‘1’. An interrupt will not be generated in this case; an interrupt will
only be generated when a data packet is transmitted.
When firmware writes ‘1’ to the FCDT bit (EINCSRH.3), the data toggle for each IN packet will be toggled
continuously, regardless of the handshake received from the host. This feature is typically used by Interrupt endpoints functioning as rate feedback communication for Isochronous endpoints. When FCDT = ‘0’,
the data toggle bit will only be toggled when an ACK is sent from the host in response to an IN packet.

15.12.2.Endpoints1-3 IN Isochronous Mode
When the ISO bit (EINCSRH.6) is set to ‘1’, the target endpoint operates in Isochronous (ISO) mode. Once
an endpoint has been configured for ISO IN mode, the host will send one IN token (data request) per
frame; the location of data within each frame may vary. Because of this, it is recommended that double
buffering be enabled for ISO IN endpoints.
Hardware will automatically reset INPRDY (EINCSRL.0) to ‘0’ when a packet slot is open in the endpoint
FIFO. Note that if double buffering is enabled for the target endpoint, it is possible for firmware to load two
packets into the IN FIFO at a time. In this case, hardware will reset INPRDY to ‘0’ immediately after firmware loads the first packet into the FIFO and sets INPRDY to ‘1’. An interrupt will not be generated in this
case; an interrupt will only be generated when a data packet is transmitted.
If there is not a data packet ready in the endpoint FIFO when USB0 receives an IN token from the host,
USB0 will transmit a zero-length data packet and set the UNDRUN bit (EINCSRL.2) to ‘1’.
The ISO Update feature (see Section 15.7) can be useful in starting a double buffered ISO IN endpoint. If
the host has already set up the ISO IN pipe (has begun transmitting IN tokens) when firmware writes the
first data packet to the endpoint FIFO, the next IN token may arrive and the first data packet sent before
firmware has written the second (double buffered) data packet to the FIFO. The ISO Update feature
ensures that any data packet written to the endpoint FIFO will not be transmitted during the current frame;
the packet will only be sent after a SOF signal has been received.

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USB Register Definition 15.19. EINCSRL: USB0 IN Endpoint Control Low Byte
R

R/W

Reset Value

CLRDT

STSTL

SDSTL

FLUSH

UNDRUN

FIFONE

INPRDY

00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

USB Address:

0x11
Bit7:
Bit6:

Bit5:

Bit4:

Bit3:

Bit2:

Bit1:

Bit0:

Unused. Read = 0b; Write = don’t care.
CLRDT: Clear Data Toggle.
Write: Software should write ‘1’ to this bit to reset the IN Endpoint data toggle to ‘0’.
Read: This bit always reads ‘0’.
STSTL: Sent Stall
Hardware sets this bit to ‘1’ when a STALL handshake signal is transmitted. The FIFO is
flushed, and the INPRDY bit cleared. This flag must be cleared by software.
SDSTL: Send Stall.
Software should write ‘1’ to this bit to generate a STALL handshake in response to an IN
token. Software should write ‘0’ to this bit to terminate the STALL signal. This bit has no
effect in ISO mode.
FLUSH: FIFO Flush.
Writing a ‘1’ to this bit flushes the next packet to be transmitted from the IN Endpoint FIFO.
The FIFO pointer is reset and the INPRDY bit is cleared. If the FIFO contains multiple packets, software must write ‘1’ to FLUSH for each packet. Hardware resets the FLUSH bit to ‘0’
when the FIFO flush is complete.
UNDRUN: Data Underrun.
The function of this bit depends on the IN Endpoint mode:
ISO: Set when a zero-length packet is sent after an IN token is received while bit INPRDY =
‘0’.
Interrupt/Bulk: Set when a NAK is returned in response to an IN token.
This bit must be cleared by software.
FIFONE: FIFO Not Empty.
0: The IN Endpoint FIFO is empty.
1. The IN Endpoint FIFO contains one or more packets.
INPRDY: In Packet Ready.
Software should write ‘1’ to this bit after loading a data packet into the IN Endpoint FIFO.
Hardware clears INPRDY due to any of the following:
1. A data packet is transmitted.
2. Double buffering is enabled (DBIEN = ‘1’) and there is an open FIFO packet slot.
3. If the endpoint is in Isochronous Mode (ISO = ‘1’) and ISOUD = ‘1’, INPRDY will read ‘0’
until the next SOF is received.
An interrupt (if enabled) will be generated when hardware clears INPRDY as a result
of a packet being transmitted.

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USB Register Definition 15.20. EINCSRH: USB0 IN Endpoint Control High Byte
R/W

R/W

DBIEN

ISO

Bit7

Bit6

Reset Value

DIRSEL

FCDT

SPLIT

00000000

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

USB Address:

0x12
Bit7:

DBIEN: IN Endpoint Double-buffer Enable.
0: Double-buffering disabled for the selected IN endpoint.
1: Double-buffering enabled for the selected IN endpoint.
Bit6:
ISO: Isochronous Transfer Enable.
This bit enables/disables isochronous transfers on the current endpoint.
0: Endpoint configured for bulk/interrupt transfers.
1: Endpoint configured for isochronous transfers.
Bit5:
DIRSEL: Endpoint Direction Select.
This bit is valid only when the selected FIFO is not split (SPLIT = ‘0’).
0: Endpoint direction selected as OUT.
1: Endpoint direction selected as IN.
Bit4:
Unused. Read = ‘0b’. Write = don’t care.
Bit3:
FCDT: Force Data Toggle.
0: Endpoint data toggle switches only when an ACK is received following a data packet
transmission.
1: Endpoint data toggle forced to switch after every data packet is transmitted, regardless of
ACK reception.
Bit2:
SPLIT: FIFO Split Enable.
When SPLIT = ‘1’, the selected endpoint FIFO is split. The upper half of the selected FIFO is
used by the IN endpoint; the lower half of the selected FIFO is used by the OUT endpoint.
Bits1–0: Unused. Read = 00b; Write = don’t care.

15.13. Controlling Endpoints1–3 OUT
Endpoints1-3 OUT are managed via USB registers EOUTCSRL and EOUTCSRH. All OUT endpoints can
be used for Interrupt, Bulk, or Isochronous transfers. Isochronous (ISO) mode is enabled by writing ‘1’ to
the ISO bit in register EOUTCSRH. Bulk and Interrupt transfers are handled identically by hardware.
An Endpoint1-3 OUT interrupt may be generated by the following:
1. Hardware sets the OPRDY bit (EINCSRL.0) to ‘1’.
2. Hardware generates a STALL condition.

15.13.1.Endpoints1-3 OUT Interrupt or Bulk Mode
When the ISO bit (EOUTCSRH.6) = ‘0’ the target endpoint operates in Bulk or Interrupt mode. Once an
endpoint has been configured to operate in Bulk/Interrupt OUT mode (typically following an Endpoint0
SET_INTERFACE command), hardware will set the OPRDY bit (EOUTCSRL.0) to ‘1’ and generate an
interrupt upon reception of an OUT token and data packet. The number of bytes in the current OUT data
packet (the packet ready to be unloaded from the FIFO) is given in the EOUTCNTH and EOUTCNTL registers. In response to this interrupt, firmware should unload the data packet from the OUT FIFO and reset
the OPRDY bit to ‘0’.

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A Bulk or Interrupt pipe can be shut down (or Halted) by writing ‘1’ to the SDSTL bit (EOUTCSRL.5). While
SDSTL = ‘1’, hardware will respond to all OUT requests with a STALL condition. Each time hardware generates a STALL condition, an interrupt will be generated and the STSTL bit (EOUTCSRL.6) set to ‘1’. The
STSTL bit must be reset to ‘0’ by firmware.
Hardware will automatically set OPRDY when a packet is ready in the OUT FIFO. Note that if double buffering is enabled for the target endpoint, it is possible for two packets to be ready in the OUT FIFO at a time.
In this case, hardware will set OPRDY to ‘1’ immediately after firmware unloads the first packet and resets
OPRDY to ‘0’. A second interrupt will be generated in this case.

15.13.2.Endpoints1-3 OUT Isochronous Mode
When the ISO bit (EOUTCSRH.6) is set to ‘1’, the target endpoint operates in Isochronous (ISO) mode.
Once an endpoint has been configured for ISO OUT mode, the host will send exactly one data per USB
frame; the location of the data packet within each frame may vary, however. Because of this, it is recommended that double buffering be enabled for ISO OUT endpoints.
Each time a data packet is received, hardware will load the received data packet into the endpoint FIFO,
set the OPRDY bit (EOUTCSRL.0) to ‘1’, and generate an interrupt (if enabled). Firmware would typically
use this interrupt to unload the data packet from the endpoint FIFO and reset the OPRDY bit to ‘0’.
If a data packet is received when there is no room in the endpoint FIFO, an interrupt will be generated and
the OVRUN bit (EOUTCSRL.2) set to ‘1’. If USB0 receives an ISO data packet with a CRC error, the data
packet will be loaded into the endpoint FIFO, OPRDY will be set to ‘1’, an interrupt (if enabled) will be generated, and the DATAERR bit (EOUTCSRL.3) will be set to ‘1’. Software should check the DATAERR bit
each time a data packet is unloaded from an ISO OUT endpoint FIFO.

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USB Register Definition 15.21. EOUTCSRL: USB0 OUT Endpoint Control High Byte
W

R/W

Reset Value

CLRDT

STSTL

SDSTL

FLUSH

DATERR

OVRUN

FIFOFUL

OPRDY

00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

USB Address:

0x14
Bit7:

Bit6:

Bit5:

Bit4:

Bit3:

Bit2:

Bit1:

Bit0:

166

CLRDT: Clear Data Toggle
Write: Software should write ‘1’ to this bit to reset the OUT endpoint data toggle to ‘0’.
Read: This bit always reads ‘0’.
STSTL: Sent Stall
Hardware sets this bit to ‘1’ when a STALL handshake signal is transmitted. This flag must
be cleared by software.
SDSTL: Send Stall
Software should write ‘1’ to this bit to generate a STALL handshake. Software should write
‘0’ to this bit to terminate the STALL signal. This bit has no effect in ISO mode.
FLUSH: FIFO Flush
Writing a ‘1’ to this bit flushes the next packet to be read from the OUT endpoint FIFO. The
FIFO pointer is reset and the OPRDY bit is cleared. If the FIFO contains multiple packets,
software must write ‘1’ to FLUSH for each packet. Hardware resets the FLUSH bit to ‘0’
when the FIFO flush is complete.
DATERR: Data Error
In ISO mode, this bit is set by hardware if a received packet has a CRC or bit-stuffing error.
It is cleared when software clears OPRDY. This bit is only valid in ISO mode.
OVRUN: Data Overrun
This bit is set by hardware when an incoming data packet cannot be loaded into the OUT
endpoint FIFO. This bit is only valid in ISO mode, and must be cleared by software.
0: No data overrun.
1: A data packet was lost because of a full FIFO since this flag was last cleared.
FIFOFUL: OUT FIFO Full
This bit indicates the contents of the OUT FIFO. If double buffering is enabled for the endpoint (DBIEN = ‘1’), the FIFO is full when the FIFO contains two packets. If DBIEN = ‘0’, the
FIFO is full when the FIFO contains one packet.
0: OUT endpoint FIFO is not full.
1: OUT endpoint FIFO is full.
OPRDY: OUT Packet Ready
Hardware sets this bit to ‘1’ and generates an interrupt when a data packet is available. Software should clear this bit after each data packet is unloaded from the OUT endpoint FIFO.

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USB Register Definition 15.22. EOUTCSRH: USB0 OUT Endpoint Control Low Byte
R/W

R/W

Reset Value

DBOEN

ISO

00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

USB Address:

0x15
Bit7:

DBOEN: Double-buffer Enable
0: Double-buffering disabled for the selected OUT endpoint.
1: Double-buffering enabled for the selected OUT endpoint.
Bit6:
ISO: Isochronous Transfer Enable
This bit enables/disables isochronous transfers on the current endpoint.
0: Endpoint configured for bulk/interrupt transfers.
1: Endpoint configured for isochronous transfers.
Bits5–0: Unused. Read = 000000b; Write = don’t care.

USB Register Definition 15.23. EOUTCNTL: USB0 OUT Endpoint Count Low
R

Bit7

Bit6

Bit5

Bit4

Reset Value

Bit3

Bit2

Bit1

Bit0

USB Address:

EOCL

00000000
0x16

Bits7–0: EOCL: OUT Endpoint Count Low Byte
EOCL holds the lower 8-bits of the 10-bit number of data bytes in the last received packet in
the current OUT endpoint FIFO. This number is only valid while OPRDY = ‘1’.

USB Register Definition 15.24. EOUTCNTH: USB0 OUT Endpoint Count High
R

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

E0CH
Bit1

Reset Value

00000000
Bit0

USB Address:

0x17
Bits7–2: Unused. Read = 000000b. Write = don’t care.
Bits1–0: EOCH: OUT Endpoint Count High Byte
EOCH holds the upper 2-bits of the 10-bit number of data bytes in the last received packet in
the current OUT endpoint FIFO. This number is only valid while OPRDY = ‘1’.

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Table 15.4. USB Transceiver Electrical Characteristics
VDD = 3.0 to 3.6V, –40 to +85 °C unless otherwise specified.

Parameters

Symbol

Conditions

Min

Typ

Max

Units

Transmitter
Output High Voltage

VOH

Output Low Voltage

VOL

2.8

1.3

Output Crossover Point

VCRS

Output Impedance

ZDRV

Driving High
Driving Low

Pull-up Resistance

RPU

Full Speed (D+ Pull-up)
Low Speed (D– Pull-up)

1.425
1.425

Output Rise Time

Low Speed
Full Speed

Output Fall Time

0.8

2.0

38
38
1.5
1.5

W
1.575
1.575

kΩ
kΩ

75
4

300
20

Low Speed
Full Speed

75
4

300
20

| (D+) – (D–) |

0.2

Receiver
Differential Input
Sensitivity

VDI

Differential Input Common Mode Range

VCM

Input Leakage Current

0.8
Pullups Disabled

Note: Refer to the USB Specification for timing diagrams and symbol definitions.

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16. SMBus
The SMBus I/O interface is a two-wire, bi-directional serial bus. The SMBus is compliant with the System
Management Bus Specification, version 1.1, and compatible with the I2C serial bus. Reads and writes to
the interface by the system controller are byte oriented with the SMBus interface autonomously controlling
the serial transfer of the data. Data can be transferred at up to 1/20th of the system clock as a master or
slave (this can be faster than allowed by the SMBus specification, depending on the system clock used). A
method of extending the clock-low duration is available to accommodate devices with different speed
capabilities on the same bus.
The SMBus interface may operate as a master and/or slave, and may function on a bus with multiple masters. The SMBus provides control of SDA (serial data), SCL (serial clock) generation and synchronization,
arbitration logic, and START/STOP control and generation. Three SFRs are associated with the SMBus:
SMB0CF configures the SMBus; SMB0CN controls the status of the SMBus; and SMB0DAT is the data
register, used for both transmitting and receiving SMBus data and slave addresses.

SMB0CN
MT S S A A A S
A X T T CRC I
SMAOK B K
T O
R L
E D
QO
R E
S
T

SMB0CF
E I B E S S S S
N N U XMMMM
S H S T B B B B
M Y H T F CC
B
OOT S S
L E E 1 0
D

T0 Overflow

T1 Overflow

TMR2H Overflow

TMR2L Overflow

SMBUS CONTROL LOGIC

Interrupt
Request

Arbitration
SCL Synchronization
SCL Generation (Master Mode)
SDA Control
Data Path
IRQ Generation
Control

SCL

FILTER

SCL
Control

C
R
O
S
S
B
A
R

SDA
Control

SMB0DAT
7 6 5 4 3 2 1 0

Port I/O

SDA

FILTER

Figure 16.1. SMBus Block Diagram

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16.1. Supporting Documents
It is assumed the reader is familiar with or has access to the following supporting documents:
1. The I2C-Bus and How to Use It (including specifications), Philips Semiconductor.
2. The I2C-Bus Specification -- Version 2.0, Philips Semiconductor.
3. System Management Bus Specification -- Version 1.1, SBS Implementers Forum.

16.2. SMBus Configuration
Figure 16.2 shows a typical SMBus configuration. The SMBus specification allows any recessive voltage
between 3.0 V and 5.0 V; different devices on the bus may operate at different voltage levels. The bi-directional SCL (serial clock) and SDA (serial data) lines must be connected to a positive power supply voltage
through a pull-up resistor or similar circuit. Every device connected to the bus must have an open-drain or
open-collector output for both the SCL and SDA lines, so that both are pulled high (recessive state) when
the bus is free. The maximum number of devices on the bus is limited only by the requirement that the rise
and fall times on the bus not exceed 300 ns and 1000 ns, respectively.

VDD = 5V

VDD = 3V

VDD = 5V

VDD = 3V

Master
Device

Slave
Device 1

Slave
Device 2

SDA
SCL

Figure 16.2. Typical SMBus Configuration
16.3. SMBus Operation
Two types of data transfers are possible: data transfers from a master transmitter to an addressed slave
receiver (WRITE), and data transfers from an addressed slave transmitter to a master receiver (READ).
The master device initiates both types of data transfers and provides the serial clock pulses on SCL. The
SMBus interface may operate as a master or a slave, and multiple master devices on the same bus are
supported. If two or more masters attempt to initiate a data transfer simultaneously, an arbitration scheme
is employed with a single master always winning the arbitration. Note that it is not necessary to specify one
device as the Master in a system; any device who transmits a START and a slave address becomes the
master for the duration of that transfer.
A typical SMBus transaction consists of a START condition followed by an address byte (Bits7-1: 7-bit
slave address; Bit0: R/W direction bit), one or more bytes of data, and a STOP condition. Each byte that is
received (by a master or slave) must be acknowledged (ACK) with a low SDA during a high SCL (see
Figure 16.3). If the receiving device does not ACK, the transmitting device will read a NACK (not acknowledge), which is a high SDA during a high SCL.
The direction bit (R/W) occupies the least-significant bit position of the address byte. The direction bit is set
to logic 1 to indicate a "READ" operation and cleared to logic 0 to indicate a "WRITE" operation.

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All transactions are initiated by a master, with one or more addressed slave devices as the target. The
master generates the START condition and then transmits the slave address and direction bit. If the transaction is a WRITE operation from the master to the slave, the master transmits the data a byte at a time
waiting for an ACK from the slave at the end of each byte. For READ operations, the slave transmits the
data waiting for an ACK from the master at the end of each byte. At the end of the data transfer, the master
generates a STOP condition to terminate the transaction and free the bus. Figure 16.3 illustrates a typical
SMBus transaction.

SCL

SDA
SLA6

START

SLA5-0

Slave Address + R/W

R/W

ACK

D6-0

Data Byte

NACK

STOP

Figure 16.3. SMBus Transaction
16.3.1. Arbitration
A master may start a transfer only if the bus is free. The bus is free after a STOP condition or after the SCL
and SDA lines remain high for a specified time (see Section “16.3.4. SCL High (SMBus Free) Timeout” on
page 172). In the event that two or more devices attempt to begin a transfer at the same time, an arbitration scheme is employed to force one master to give up the bus. The master devices continue transmitting
until one attempts a HIGH while the other transmits a LOW. Since the bus is open-drain, the bus will be
pulled LOW. The master attempting the HIGH will detect a LOW SDA and lose the arbitration. The winning
master continues its transmission without interruption; the losing master becomes a slave and receives the
rest of the transfer if addressed. This arbitration scheme is non-destructive: one device always wins, and
no data is lost.

16.3.2. Clock Low Extension
SMBus provides a clock synchronization mechanism, similar to I2C, which allows devices with different
speed capabilities to coexist on the bus. A clock-low extension is used during a transfer in order to allow
slower slave devices to communicate with faster masters. The slave may temporarily hold the SCL line
LOW to extend the clock low period, effectively decreasing the serial clock frequency.

16.3.3. SCL Low Timeout
If the SCL line is held low by a slave device on the bus, no further communication is possible. Furthermore,
the master cannot force the SCL line high to correct the error condition. To solve this problem, the SMBus
protocol specifies that devices participating in a transfer must detect any clock cycle held low longer than
25 ms as a “timeout” condition. Devices that have detected the timeout condition must reset the communication no later than 10 ms after detecting the timeout condition.
When the SMBTOE bit in SMB0CF is set, Timer 3 is used to detect SCL low timeouts. Timer 3 is forced to
reload when SCL is high, and allowed to count when SCL is low. With Timer 3 enabled and configured to
overflow after 25 ms (and SMBTOE set), the Timer 3 interrupt service routine can be used to reset (disable
and re-enable) the SMBus in the event of an SCL low timeout.

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16.3.4. SCL High (SMBus Free) Timeout
The SMBus specification stipulates that if the SCL and SDA lines remain high for more that 50 µs, the bus
is designated as free. When the SMBFTE bit in SMB0CF is set, the bus will be considered free if SCL and
SDA remain high for more than 10 SMBus clock source periods. If the SMBus is waiting to generate a
Master START, the START will be generated following this timeout. Note that a clock source is required for
free timeout detection, even in a slave-only implementation.

16.4. Using the SMBus
The SMBus can operate in both Master and Slave modes. The interface provides timing and shifting control for serial transfers; higher level protocol is determined by user software. The SMBus interface provides
the following application-independent features:
•
•
•
•
•
•
•

Byte-wise serial data transfers
Clock signal generation on SCL (Master Mode only) and SDA data synchronization
Timeout/bus error recognition, as defined by the SMB0CF configuration register
START/STOP timing, detection, and generation
Bus arbitration
Interrupt generation
Status information

SMBus interrupts are generated for each data byte or slave address that is transferred. When transmitting,
this interrupt is generated after the ACK cycle so that software may read the received ACK value; when
receiving data, this interrupt is generated before the ACK cycle so that software may define the outgoing
ACK value. See Section “16.5. SMBus Transfer Modes” on page 180 for more details on transmission
sequences.
Interrupts are also generated to indicate the beginning of a transfer when a master (START generated), or
the end of a transfer when a slave (STOP detected). Software should read the SMB0CN (SMBus Control
register) to find the cause of the SMBus interrupt. The SMB0CN register is described in Section
“16.4.2. SMB0CN Control Register” on page 176; Table 16.4 provides a quick SMB0CN decoding reference.
SMBus configuration options include:
•
•
•
•

Timeout detection (SCL Low Timeout and/or Bus Free Timeout)
SDA setup and hold time extensions
Slave event enable/disable
Clock source selection

These options are selected in the SMB0CF register, as described in Section “16.4.1. SMBus Configuration
Register” on page 173.

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16.4.1. SMBus Configuration Register
The SMBus Configuration register (SMB0CF) is used to enable the SMBus Master and/or Slave modes,
select the SMBus clock source, and select the SMBus timing and timeout options. When the ENSMB bit is
set, the SMBus is enabled for all master and slave events. Slave events may be disabled by setting the
INH bit. With slave events inhibited, the SMBus interface will still monitor the SCL and SDA pins; however,
the interface will NACK all received addresses and will not generate any slave interrupts. When the INH bit
is set, all slave events will be inhibited following the next START (interrupts will continue for the duration of
the current transfer).

Table 16.1. SMBus Clock Source Selection
SMBCS
1
0
0
1
1

SMBCS
0
0
1
0
1

SMBus Clock Source
Timer 0 Overflow
Timer 1 Overflow
Timer 2 High Byte Overflow
Timer 2 Low Byte Overflow

The SMBCS1-0 bits select the SMBus clock source, which is used only when operating as a master or
when the Free Timeout detection is enabled. When operating as a master, overflows from the selected
source determine the absolute minimum SCL low and high times as defined in Equation 16.1. Note that the
selected clock source may be shared by other peripherals so long as the timer is left running at all times.
For example, Timer 1 overflows may generate the SMBus and UART baud rates simultaneously. Timer
configuration is covered in Section “19. Timers” on page 209.

Equation 16.1. Minimum SCL High and Low Times
1
T HighMin = T LowMin = ---------------------------------------------f ClockSourceOverflow
The selected clock source should be configured to establish the minimum SCL High and Low times as per
Equation 16.1. When the interface is operating as a master (and SCL is not driven or extended by any
other devices on the bus), the typical SMBus bit rate is approximated by Equation 16.2.

Equation 16.2. Typical SMBus Bit Rate
f ClockSourceOverflow
BitRate = ---------------------------------------------3

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Figure 16.4 shows the typical SCL generation described by Equation 16.2. Notice that THIGH is typically
twice as large as TLOW. The actual SCL output may vary due to other devices on the bus (SCL may be
extended low by slower slave devices, or driven low by contending master devices). The bit rate when
operating as a master will never exceed the limits defined by equation Equation 16.1.

Timer Source
Overflows
SCL

TLow

SCL High Timeout

THigh

Figure 16.4. Typical SMBus SCL Generation
Setting the EXTHOLD bit extends the minimum setup and hold times for the SDA line. The minimum SDA
setup time defines the absolute minimum time that SDA is stable before SCL transitions from low-to-high.
The minimum SDA hold time defines the absolute minimum time that the current SDA value remains stable
after SCL transitions from high-to-low. EXTHOLD should be set so that the minimum setup and hold times
meet the SMBus Specification requirements of 250 ns and 300 ns, respectively. Table 16.2 shows the minimum setup and hold times for the two EXTHOLD settings. Setup and hold time extensions are typically
necessary when SYSCLK is above 10 MHz.

Table 16.2. Minimum SDA Setup and Hold Times
EXTHOLD

Minimum SDA Setup Time
Tlow - 4 system clocks

Minimum SDA Hold Time

3 system clocks

1 system clock + s/w delay*
11 system clocks

12 system clocks

*Note: Setup Time for ACK bit transmissions and the MSB of all data transfers. The s/w
delay occurs between the time SMB0DAT or ACK is written and when SI is cleared.
Note that if SI is cleared in the same write that defines the outgoing ACK value, s/w
delay is zero.

With the SMBTOE bit set, Timer 3 should be configured to overflow after 25 ms in order to detect SCL low
timeouts (see Section “16.3.3. SCL Low Timeout” on page 171). The SMBus interface will force Timer 3 to
reload while SCL is high, and allow Timer 3 to count when SCL is low. The Timer 3 interrupt service routine
should be used to reset SMBus communication by disabling and re-enabling the SMBus.
SMBus Free Timeout detection can be enabled by setting the SMBFTE bit. When this bit is set, the bus will
be considered free if SDA and SCL remain high for more than 10 SMBus clock source periods (see
Figure 16.4). When a Free Timeout is detected, the interface will respond as if a STOP was detected (an
interrupt will be generated, and STO will be set).

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SFR Definition 16.1. SMB0CF: SMBus Clock/Configuration
R/W

R/W

ENSMB

INH

BUSY

Bit7

Bit6

Bit5

R/W

Reset Value

EXTHOLD SMBTOE SMBFTE SMBCS1 SMBCS0 00000000
Bit4

Bit3

Bit2

Bit1

Bit0
SFR
0xC1
Address:

Bit7:

ENSMB: SMBus Enable.
This bit enables/disables the SMBus interface. When enabled, the interface constantly monitors the SDA and SCL pins.
0: SMBus interface disabled.
1: SMBus interface enabled.
Bit6:
INH: SMBus Slave Inhibit.
When this bit is set to logic 1, the SMBus does not generate an interrupt when slave events
occur. This effectively removes the SMBus slave from the bus. Master Mode interrupts are
not affected.
0: SMBus Slave Mode enabled.
1: SMBus Slave Mode inhibited.
Bit5:
BUSY: SMBus Busy Indicator.
This bit is set to logic 1 by hardware when a transfer is in progress. It is cleared to logic 0
when a STOP or free-timeout is sensed.
Bit4:
EXTHOLD: SMBus Setup and Hold Time Extension Enable.
This bit controls the SDA setup and hold times according to .
0: SDA Extended Setup and Hold Times disabled.
1: SDA Extended Setup and Hold Times enabled.
Bit3:
SMBTOE: SMBus SCL Timeout Detection Enable.
This bit enables SCL low timeout detection. If set to logic 1, the SMBus forces Timer 3 to
reload while SCL is high and allows Timer 3 to count when SCL goes low. Timer 3 should be
programmed to generate interrupts at 25 ms, and the Timer 3 interrupt service routine
should reset SMBus communication.
Bit2:
SMBFTE: SMBus Free Timeout Detection Enable.
When this bit is set to logic 1, the bus will be considered free if SCL and SDA remain high for
more than 10 SMBus clock source periods.
Bits1–0: SMBCS1–SMBCS0: SMBus Clock Source Selection.
These two bits select the SMBus clock source, which is used to generate the SMBus bit
rate. The selected device should be configured according to Equation 16.1.
SMBCS1
0
0
1
1

SMBCS0
0
1
0
1

SMBus Clock Source
Timer 0 Overflow
Timer 1 Overflow
Timer 2 High Byte Overflow
Timer 2 Low Byte Overflow

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16.4.2. SMB0CN Control Register
SMB0CN is used to control the interface and to provide status information (see Figure 16.2). The higher
four bits of SMB0CN (MASTER, TXMODE, STA, and STO) form a status vector that can be used to jump
to service routines. MASTER and TXMODE indicate the master/slave state and transmit/receive modes,
respectively.
STA and STO indicate that a START and/or STOP has been detected or generated since the last SMBus
interrupt. STA and STO are also used to generate START and STOP conditions when operating as a master. Writing a ‘1’ to STA will cause the SMBus interface to enter Master Mode and generate a START when
the bus becomes free (STA is not cleared by hardware after the START is generated). Writing a ‘1’ to STO
while in Master Mode will cause the interface to generate a STOP and end the current transfer after the
next ACK cycle. If STO and STA are both set (while in Master Mode), a STOP followed by a START will be
generated.
As a receiver, writing the ACK bit defines the outgoing ACK value; as a transmitter, reading the ACK bit
indicates the value received on the last ACK cycle. ACKRQ is set each time a byte is received, indicating
that an outgoing ACK value is needed. When ACKRQ is set, software should write the desired outgoing
value to the ACK bit before clearing SI. A NACK will be generated if software does not write the ACK bit
before clearing SI. SDA will reflect the defined ACK value immediately following a write to the ACK bit;
however SCL will remain low until SI is cleared. If a received slave address is not acknowledged, further
slave events will be ignored until the next START is detected.
The ARBLOST bit indicates that the interface has lost an arbitration. This may occur anytime the interface
is transmitting (master or slave). A lost arbitration while operating as a slave indicates a bus error condition. ARBLOST is cleared by hardware each time SI is cleared.
The SI bit (SMBus Interrupt Flag) is set at the beginning and end of each transfer, after each byte frame, or
when an arbitration is lost; see Table 16.3 for more details.
Important Note About the SI Bit: The SMBus interface is stalled while SI is set; thus SCL is held low, and
the bus is stalled until software clears SI.
Table 16.3 lists all sources for hardware changes to the SMB0CN bits. Refer to Table 16.4 for SMBus status decoding using the SMB0CN register.

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SFR Definition 16.2. SMB0CN: SMBus Control
R

MASTER TXMODE
Bit7

Bit6

R/W

STA

STO

Bit5

Bit4

ACKRQ ARBLOST
Bit3

Bit2

R/W

Reset Value

ACK

00000000

Bit1

Bit0

Bit Addressable

SFR Address: 0xC0

Bit7:

Bit6:

Bit5:

Bit4:

Bit3:

Bit2:

Bit1:

Bit0:

MASTER: SMBus Master/Slave Indicator.
This read-only bit indicates when the SMBus is operating as a master.
0: SMBus operating in Slave Mode.
1: SMBus operating in Master Mode.
TXMODE: SMBus Transmit Mode Indicator.
This read-only bit indicates when the SMBus is operating as a transmitter.
0: SMBus in Receiver Mode.
1: SMBus in Transmitter Mode.
STA: SMBus Start Flag.
Write:
0: No Start generated.
1: When operating as a master, a START condition is transmitted if the bus is free (If the bus
is not free, the START is transmitted after a STOP is received or a timeout is detected). If
STA is set by software as an active Master, a repeated START will be generated after the
next ACK cycle.
Read:
0: No Start or repeated Start detected.
1: Start or repeated Start detected.
STO: SMBus Stop Flag.
Write:
0: No STOP condition is transmitted.
1: Setting STO to logic 1 causes a STOP condition to be transmitted after the next ACK
cycle. When the STOP condition is generated, hardware clears STO to logic 0. If both STA
and STO are set, a STOP condition is transmitted followed by a START condition.
Read:
0: No Stop condition detected.
1: Stop condition detected (if in Slave Mode) or pending (if in Master Mode).
ACKRQ: SMBus Acknowledge Request
This read-only bit is set to logic 1 when the SMBus has received a byte and needs the ACK
bit to be written with the correct ACK response value.
ARBLOST: SMBus Arbitration Lost Indicator.
This read-only bit is set to logic 1 when the SMBus loses arbitration while operating as a
transmitter. A lost arbitration while a slave indicates a bus error condition.
ACK: SMBus Acknowledge Flag.
This bit defines the out-going ACK level and records incoming ACK levels. It should be written each time a byte is received (when ACKRQ=1), or read after each byte is transmitted.
0: A "not acknowledge" has been received (if in Transmitter Mode) OR will be transmitted (if
in Receiver Mode).
1: An "acknowledge" has been received (if in Transmitter Mode) OR will be transmitted (if in
Receiver Mode).
SI: SMBus Interrupt Flag.
This bit is set by hardware under the conditions listed in Table 16.3. SI must be cleared by
software. While SI is set, SCL is held low and the SMBus is stalled.

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Table 16.3. Sources for Hardware Changes to SMB0CN
Bit

Cleared by Hardware When:
• A STOP is generated.
• Arbitration is lost.

• START is generated.
• SMB0DAT is written before the start of an
SMBus frame.

• A START is detected.
• Arbitration is lost.
• SMB0DAT is not written before the
start of an SMBus frame.

STA

• A START followed by an address byte is
received.

• Must be cleared by software.

• A STOP is detected while addressed as a
slave.
• Arbitration is lost due to a detected STOP.

• A pending STOP is generated.

STO

• A byte has been received and an ACK
response value is needed.

• After each ACK cycle.

MASTER

TXMODE

ACKRQ

ARBLOST

ACK

178

Set by Hardware When:
• A START is generated.

• A repeated START is detected as a MASTER • Each time SI is cleared.
when STA is low (unwanted repeated START).
• SCL is sensed low while attempting to generate a STOP or repeated START condition.
• SDA is sensed low while transmitting a ‘1’
(excluding ACK bits).
• The incoming ACK value is low (ACKNOWLEDGE).

• The incoming ACK value is high (NOT
ACKNOWLEDGE).

• A START has been generated.
• Lost arbitration.
• A byte has been transmitted and an
ACK/NACK received.
• A byte has been received.
• A START or repeated START followed by a
slave address + R/W has been received.
• A STOP has been received.

• Must be cleared by software.

Rev. 1.4

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16.4.3. Data Register
The SMBus Data register SMB0DAT holds a byte of serial data to be transmitted or one that has just been
received. Software may safely read or write to the data register when the SI flag is set. Software should not
attempt to access the SMB0DAT register when the SMBus is enabled and the SI flag is cleared to logic 0,
as the interface may be in the process of shifting a byte of data into or out of the register.
Data in SMB0DAT is always shifted out MSB first. After a byte has been received, the first bit of received
data is located at the MSB of SMB0DAT. While data is being shifted out, data on the bus is simultaneously
being shifted in. SMB0DAT always contains the last data byte present on the bus. In the event of lost arbitration, the transition from master transmitter to slave receiver is made with the correct data or address in
SMB0DAT.

SFR Definition 16.3. SMB0DAT: SMBus Data
R/W

R/W

Reset Value

00000000
Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0
SFR Address: 0xC2

Bits7–0: SMB0DAT: SMBus Data.
The SMB0DAT register contains a byte of data to be transmitted on the SMBus serial interface or a byte that has just been received on the SMBus serial interface. The CPU can read
from or write to this register whenever the SI serial interrupt flag (SMB0CN.0) is set to
logic 1. The serial data in the register remains stable as long as the SI flag is set. When the
SI flag is not set, the system may be in the process of shifting data in/out and the CPU
should not attempt to access this register.

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16.5. SMBus Transfer Modes
The SMBus interface may be configured to operate as master and/or slave. At any particular time, it will be
operating in one of the following four modes: Master Transmitter, Master Receiver, Slave Transmitter, or
Slave Receiver. The SMBus interface enters Master Mode any time a START is generated, and remains in
Master Mode until it loses an arbitration or generates a STOP. An SMBus interrupt is generated at the end
of all SMBus byte frames; however, note that the interrupt is generated before the ACK cycle when operating as a receiver, and after the ACK cycle when operating as a transmitter.

16.5.1. Master Transmitter Mode
Serial data is transmitted on SDA while the serial clock is output on SCL. The SMBus interface generates
the START condition and transmits the first byte containing the address of the target slave and the data
direction bit. In this case the data direction bit (R/W) will be logic 0 (WRITE). The master then transmits
one or more bytes of serial data. After each byte is transmitted, an acknowledge bit is generated by the
slave. The transfer is ended when the STO bit is set and a STOP is generated. Note that the interface will
switch to Master Receiver Mode if SMB0DAT is not written following a Master Transmitter interrupt.
Figure 16.5 shows a typical Master Transmitter sequence. Two transmit data bytes are shown, though any
number of bytes may be transmitted. Notice that the ‘data byte transferred’ interrupts occur after the ACK
cycle in this mode.

SLA

Interrupt

Data Byte

Interrupt

Data Byte

Interrupt

S = START
P = STOP
A = ACK
W = WRITE
SLA = Slave Address

Received by SMBus
Interface
Transmitted by
SMBus Interface

Figure 16.5. Typical Master Transmitter Sequence

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16.5.2. Master Receiver Mode
Serial data is received on SDA while the serial clock is output on SCL. The SMBus interface generates the
START condition and transmits the first byte containing the address of the target slave and the data direction bit. In this case the data direction bit (R/W) will be logic 1 (READ). Serial data is then received from the
slave on SDA while the SMBus outputs the serial clock. The slave transmits one or more bytes of serial
data. After each byte is received, ACKRQ is set to ‘1’ and an interrupt is generated. Software must write
the ACK bit (SMB0CN.1) to define the outgoing acknowledge value (Note: writing a ‘1’ to the ACK bit generates an ACK; writing a ‘0’ generates a NACK). Software should write a ‘0’ to the ACK bit after the last
byte is received, to transmit a NACK. The interface exits Master Receiver Mode after the STO bit is set and
a STOP is generated. Note that the interface will switch to Master Transmitter Mode if SMB0DAT is written
while an active Master Receiver. Figure 16.6 shows a typical Master Receiver sequence. Two received
data bytes are shown, though any number of bytes may be received. Notice that the ‘data byte transferred’
interrupts occur before the ACK cycle in this mode.

SLA

Interrupt

Data Byte

Interrupt

Data Byte

Interrupt
S = START
P = STOP
A = ACK
N = NACK
R = READ
SLA = Slave Address

Received by SMBus
Interface
Transmitted by
SMBus Interface

Figure 16.6. Typical Master Receiver Sequence

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16.5.3. Slave Receiver Mode
Serial data is received on SDA and the clock is received on SCL. When slave events are enabled (INH =
0), the interface enters Slave Receiver Mode when a START followed by a slave address and direction bit
(WRITE in this case) is received. Upon entering Slave Receiver Mode, an interrupt is generated and the
ACKRQ bit is set. Software responds to the received slave address with an ACK, or ignores the received
slave address with a NACK. If the received slave address is ignored, slave interrupts will be inhibited until
the next START is detected. If the received slave address is acknowledged, zero or more data bytes are
received. Software must write the ACK bit after each received byte to ACK or NACK the received byte. The
interface exits Slave Receiver Mode after receiving a STOP. Note that the interface will switch to Slave
Transmitter Mode if SMB0DAT is written while an active Slave Receiver. Figure 16.7 shows a typical Slave
Receiver sequence. Two received data bytes are shown, though any number of bytes may be received.
Notice that the ‘data byte transferred’ interrupts occur before the ACK cycle in this mode.

Interrupt

SLA

Interrupt

Data Byte

Interrupt

Data Byte

Interrupt
S = START
P = STOP
A = ACK
W = WRITE
SLA = Slave Address

Received by SMBus
Interface
Transmitted by
SMBus Interface

Figure 16.7. Typical Slave Receiver Sequence

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16.5.4. Slave Transmitter Mode
Serial data is transmitted on SDA and the clock is received on SCL. When slave events are enabled (INH
= 0), the interface enters Slave Receiver Mode (to receive the slave address) when a START followed by a
slave address and direction bit (READ in this case) is received. Upon entering Slave Transmitter Mode, an
interrupt is generated and the ACKRQ bit is set. Software responds to the received slave address with an
ACK, or ignores the received slave address with a NACK. If the received slave address is ignored, slave
interrupts will be inhibited until a START is detected. If the received slave address is acknowledged, data
should be written to SMB0DAT to be transmitted. The interface enters Slave Transmitter Mode, and transmits one or more bytes of data. After each byte is transmitted, the master sends an acknowledge bit; if the
acknowledge bit is an ACK, SMB0DAT should be written with the next data byte. If the acknowledge bit is
a NACK, SMB0DAT should not be written to before SI is cleared (Note: an error condition may be generated if SMB0DAT is written following a received NACK while in Slave Transmitter Mode). The interface
exits Slave Transmitter Mode after receiving a STOP. Note that the interface will switch to Slave Receiver
Mode if SMB0DAT is not written following a Slave Transmitter interrupt. Figure 16.8 shows a typical Slave
Transmitter sequence. Two transmitted data bytes are shown, though any number of bytes may be transmitted. Notice that the ‘data byte transferred’ interrupts occur after the ACK cycle in this mode.

Interrupt

SLA

Interrupt
Received by SMBus
Interface
Transmitted by
SMBus Interface

Data Byte

Interrupt

S = START
P = STOP
N = NACK
R = READ
SLA = Slave Address

Figure 16.8. Typical Slave Transmitter Sequence

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16.6. SMBus Status Decoding
The current SMBus status can be easily decoded using the SMB0CN register. In the table below, STATUS
VECTOR refers to the four upper bits of SMB0CN: MASTER, TXMODE, STA, and STO. Note that the
shown response options are only the typical responses; application-specific procedures are allowed as
long as they conform to the SMBus specification. Highlighted responses are allowed but do not conform to
the SMBus specification.

Table 16.4. SMBus Status Decoding

ARBLOST

ACK

X A master START was generated.

1100
0

Load slave address + R/W
into SMB0DAT.

Set STA to restart transfer.
A master data or address byte
was transmitted; NACK received. Abort transfer.

A master data or address byte
was transmitted; ACK received.

Rev. 1.4

ACK

ACKRQ
0

Typical Response Options

STA

Status
Vector

Mode
Master Transmitter
184

1110

Current SMbus State

STo

Values
Written

Values Read

Load next data byte into
SMB0DAT.

End transfer with STOP.

End transfer with STOP and
1
start another transfer.

Send repeated START.

Switch to Master Receiver
Mode (clear SI without writ- 0
ing new data to SMB0DAT).

C8051F320/1
Table 16.4. SMBus Status Decoding (Continued)

0100

0101

ACK

Typical Response Options

STA

ACK

ARBLOST

ACKRQ

Status
Vector

Mode
Master Receiver
Slave Transmitter

1000

Current SMbus State

STo

Values
Written

Values Read

Acknowledge received byte;
0
Read SMB0DAT.

Send NACK to indicate last
byte, and send STOP.

Send NACK to indicate last
byte, and send STOP followed by START.

Send ACK followed by
repeated START.

Send ACK and switch to
Master Transmitter Mode
(write to SMB0DAT before
clearing SI).

Send NACK and switch to
Master Transmitter Mode
(write to SMB0DAT before
clearing SI).

A master data byte was received; Send NACK to indicate last
ACK requested.
byte, and send repeated
START.

A slave byte was transmitted;
NACK received.

No action required (expecting STOP condition).

A slave byte was transmitted;
ACK received.

Load SMB0DAT with next
data byte to transmit.

A Slave byte was transmitted;
error detected.

No action required (expecting Master to end transfer).

An illegal STOP or bus error was
X detected while a Slave Transmis- Clear STO.
sion was in progress.

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Table 16.4. SMBus Status Decoding (Continued)

0010

Slave Receiver

0010

0001

Lost arbitration as master; slave
X address received; ACK
requested.

Do not acknowledge
received address.

Acknowledge received
address.

Do not acknowledge
received address.

Reschedule failed transfer;
do not acknowledge received 1
address.

Lost arbitration while attempting a Abort failed transfer.
repeated START.
Reschedule failed transfer.

Lost arbitration while attempting a No action required (transfer
complete/aborted).
STOP.

A STOP was detected while
X addressed as a Slave Transmitter Clear STO.
or Slave Receiver.

0000
1

186

Acknowledge received
address.

Lost arbitration due to a detected Abort transfer.
STOP.
Reschedule failed transfer.
A slave byte was received; ACK
requested.

Acknowledge received byte;
0
Read SMB0DAT.

Do not acknowledge
received byte.

Lost arbitration while transmitting Abort failed transfer.
a data byte as master.
Reschedule failed transfer.

Rev. 1.4

ACK

Typical Response Options

STA

ARBLOST

ACKRQ

Status
Vector

Mode

A slave address was received;
X
ACK requested.

Current SMbus State

STo

Values
Written

Values Read

0
0

C8051F320/1
17. UART0
UART0 is an asynchronous, full duplex serial port offering modes 1 and 3 of the standard 8051 UART.
Enhanced baud rate support allows a wide range of clock sources to generate standard baud rates (details
in Section “17.1. Enhanced Baud Rate Generation” on page 188). Received data buffering allows UART0
to start reception of a second incoming data byte before software has finished reading the previous data
byte.
UART0 has two associated SFRs: Serial Control Register 0 (SCON0) and Serial Data Buffer 0 (SBUF0).
The single SBUF0 location provides access to both transmit and receive registers. Writes to SBUF0
always access the Transmit register. Reads of SBUF0 always access the buffered Receive register;
it is not possible to read data from the Transmit register.
With UART0 interrupts enabled, an interrupt is generated each time a transmit is completed (TI0 is set in
SCON0), or a data byte has been received (RI0 is set in SCON0). The UART0 interrupt flags are not
cleared by hardware when the CPU vectors to the interrupt service routine. They must be cleared manually
by software, allowing software to determine the cause of the UART0 interrupt (transmit complete or receive
complete).
SFR Bus

Write to
SBUF
TB8

SBUF
(TX Shift)

SET
D

CLR

Crossbar

Zero Detector

Stop Bit

Shift

Start

Data

Tx Control

Tx Clock
Send

Tx IRQ

SCON
TI
Serial
Port
Interrupt

MCE
REN
TB8
RB8
TI
RI

SMODE

UART Baud
Rate Generator

Port I/O

Rx IRQ
Rx Clock

Rx Control
Start

Shift

0x1FF

Load
SBUF

RB8

Input Shift Register
(9 bits)
Load SBUF

SBUF
(RX Latch)
Read
SBUF

SFR Bus

Crossbar

Figure 17.1. UART0 Block Diagram

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17.1. Enhanced Baud Rate Generation
The UART0 baud rate is generated by Timer 1 in 8-bit auto-reload mode. The TX clock is generated by
TL1; the RX clock is generated by a copy of TL1 (shown as RX Timer in Figure 17.2), which is not useraccessible. Both TX and RX Timer overflows are divided by two to generate the TX and RX baud rates.
The RX Timer runs when Timer 1 is enabled, and uses the same reload value (TH1). However, an
RX Timer reload is forced when a START condition is detected on the RX pin. This allows a receive to
begin any time a START is detected, independent of the TX Timer state.

Timer 1
TL1

UART
Overflow

TX Clock

Overflow

RX Clock

TH1
Start
Detected

RX Timer

Figure 17.2. UART0 Baud Rate Logic
Timer 1 should be configured for Mode 2, 8-bit auto-reload (see Section “19.1.3. Mode 2: 8-bit
Counter/Timer with Auto-Reload” on page 211). The Timer 1 reload value should be set so that overflows
will occur at two times the desired UART baud rate frequency. Note that Timer 1 may be clocked by one of
six sources: SYSCLK, SYSCLK / 4, SYSCLK / 12, SYSCLK / 48, the external oscillator clock / 8, or an
external input T1. For any given Timer 1 clock source, the UART0 baud rate is determined by
Equation 17.1.

Equation 17.1. UART0 Baud Rate
T1 CLK
1
UartBaudRate = ------------------------------- × --( 256 – T1H ) 2
Where T1CLK is the frequency of the clock supplied to Timer 1, and T1H is the high byte of Timer 1 (reload
value). Timer 1 clock frequency is selected as described in Section “19. Timers” on page 209. A quick reference for typical baud rates and system clock frequencies is given in Table 17.1. Note that the internal
oscillator may still generate the system clock when the external oscillator is driving Timer 1.

17.2. Operational Modes
UART0 provides standard asynchronous, full duplex communication. The UART mode (8-bit or 9-bit) is
selected by the S0MODE bit (SCON0.7). Typical UART connection options are shown below.

188

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C8051F320/1

RS-232
LEVEL
XLTR

RS-232

C8051Fxxx

OR
TX

MCU

C8051Fxxx

Figure 17.3. UART Interconnect Diagram
17.2.1. 8-Bit UART
8-Bit UART mode uses a total of 10 bits per data byte: one start bit, eight data bits (LSB first), and one stop
bit. Data are transmitted LSB first from the TX0 pin and received at the RX0 pin. On receive, the eight data
bits are stored in SBUF0 and the stop bit goes into RB80 (SCON0.2).
Data transmission begins when software writes a data byte to the SBUF0 register. The TI0 Transmit Interrupt Flag (SCON0.1) is set at the end of the transmission (the beginning of the stop-bit time). Data reception can begin any time after the REN0 Receive Enable bit (SCON0.4) is set to logic 1. After the stop bit is
received, the data byte will be loaded into the SBUF0 receive register if the following conditions are met:
RI0 must be logic 0, and if MCE0 is logic 1, the stop bit must be logic 1. In the event of a receive data overrun, the first received 8 bits are latched into the SBUF0 receive register and the following overrun data bits
are lost.
If these conditions are met, the eight bits of data is stored in SBUF0, the stop bit is stored in RB80 and the
RI0 flag is set. If these conditions are not met, SBUF0 and RB80 will not be loaded and the RI0 flag will not
be set. An interrupt will occur if enabled when either TI0 or RI0 is set.

MARK
SPACE

START
BIT

STOP
BIT

BIT TIMES

BIT SAMPLING

Figure 17.4. 8-Bit UART Timing Diagram

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17.2.2. 9-Bit UART
9-bit UART mode uses a total of eleven bits per data byte: a start bit, 8 data bits (LSB first), a programmable ninth data bit, and a stop bit. The state of the ninth transmit data bit is determined by the value in TB80
(SCON0.3), which is assigned by user software. It can be assigned the value of the parity flag (bit P in register PSW) for error detection, or used in multiprocessor communications. On receive, the ninth data bit
goes into RB80 (SCON0.2) and the stop bit is ignored.
Data transmission begins when an instruction writes a data byte to the SBUF0 register. The TI0 Transmit
Interrupt Flag (SCON0.1) is set at the end of the transmission (the beginning of the stop-bit time). Data
reception can begin any time after the REN0 Receive Enable bit (SCON0.4) is set to ‘1’. After the stop bit
is received, the data byte will be loaded into the SBUF0 receive register if the following conditions are met:
(1) RI0 must be logic 0, and (2) if MCE0 is logic 1, the 9th bit must be logic 1 (when MCE0 is logic 0, the
state of the ninth data bit is unimportant). If these conditions are met, the eight bits of data are stored in
SBUF0, the ninth bit is stored in RB80, and the RI0 flag is set to ‘1’. If the above conditions are not met,
SBUF0 and RB80 will not be loaded and the RI0 flag will not be set to ‘1’. A UART0 interrupt will occur if
enabled when either TI0 or RI0 is set to ‘1’.

MARK
SPACE

START
BIT

STOP
BIT

BIT TIMES

BIT SAMPLING

Figure 17.5. 9-Bit UART Timing Diagram
17.3. Multiprocessor Communications
9-Bit UART mode supports multiprocessor communication between a master processor and one or more
slave processors by special use of the ninth data bit. When a master processor wants to transmit to one or
more slaves, it first sends an address byte to select the target(s). An address byte differs from a data byte
in that its ninth bit is logic 1; in a data byte, the ninth bit is always set to logic 0.
Setting the MCE0 bit (SCON0.5) of a slave processor configures its UART such that when a stop bit is
received, the UART will generate an interrupt only if the ninth bit is logic 1 (RB80 = 1) signifying an address
byte has been received. In the UART interrupt handler, software will compare the received address with
the slave's own assigned 8-bit address. If the addresses match, the slave will clear its MCE0 bit to enable
interrupts on the reception of the following data byte(s). Slaves that weren't addressed leave their MCE0
bits set and do not generate interrupts on the reception of the following data bytes, thereby ignoring the
data. Once the entire message is received, the addressed slave resets its MCE0 bit to ignore all transmissions until it receives the next address byte.
Multiple addresses can be assigned to a single slave and/or a single address can be assigned to multiple
slaves, thereby enabling "broadcast" transmissions to more than one slave simultaneously. The master
processor can be configured to receive all transmissions or a protocol can be implemented such that the
master/slave role is temporarily reversed to enable half-duplex transmission between the original master
and slave(s).

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Master
Device

Slave
Device

Slave
Device
V+

Figure 17.6. UART Multi-Processor Mode Interconnect Diagram

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SFR Definition 17.1. SCON0: Serial Port 0 Control
R/W

R/W

Reset Value

S0MODE

MCE0

REN0

TB80

RB80

TI0

RI0

01000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

Bit Addressable

SFR Address: 0x98

Bit7:

Bit6:
Bit5:

Bit4:

Bit3:

Bit2:

Bit1:

Bit0:

192

S0MODE: Serial Port 0 Operation Mode.
This bit selects the UART0 Operation Mode.
0: 8-bit UART with Variable Baud Rate.
1: 9-bit UART with Variable Baud Rate.
UNUSED. Read = 1b. Write = don’t care.
MCE0: Multiprocessor Communication Enable.
The function of this bit is dependent on the Serial Port 0 Operation Mode.
S0MODE = 0: Checks for valid stop bit.
0: Logic level of stop bit is ignored.
1: RI0 will only be activated if stop bit is logic level 1.
S0MODE = 1: Multiprocessor Communications Enable.
0: Logic level of ninth bit is ignored.
1: RI0 is set and an interrupt is generated only when the ninth bit is logic 1.
REN0: Receive Enable.
This bit enables/disables the UART receiver.
0: UART0 reception disabled.
1: UART0 reception enabled.
TB80: Ninth Transmission Bit.
The logic level of this bit will be assigned to the ninth transmission bit in 9-bit UART Mode. It
is not used in 8-bit UART Mode. Set or cleared by software as required.
RB80: Ninth Receive Bit.
RB80 is assigned the value of the STOP bit in Mode 0; it is assigned the value of the 9th
data bit in Mode 1.
TI0: Transmit Interrupt Flag.
Set by hardware when a byte of data has been transmitted by UART0 (after the 8th bit in 8bit UART Mode, or at the beginning of the STOP bit in 9-bit UART Mode). When the UART0
interrupt is enabled, setting this bit causes the CPU to vector to the UART0 interrupt service
routine. This bit must be cleared manually by software.
RI0: Receive Interrupt Flag.
Set to ‘1’ by hardware when a byte of data has been received by UART0 (set at the STOP bit
sampling time). When the UART0 interrupt is enabled, setting this bit to ‘1’ causes the CPU
to vector to the UART0 interrupt service routine. This bit must be cleared manually by software.

Rev. 1.4

C8051F320/1
SFR Definition 17.2. SBUF0: Serial (UART0) Port Data Buffer
R/W

R/W

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

Reset Value

00000000
SFR Address: 0x99

Bits7–0: SBUF0[7:0]: Serial Data Buffer Bits 7–0 (MSB-LSB)
This SFR accesses two registers; a transmit shift register and a receive latch register. When
data is written to SBUF0, it goes to the transmit shift register and is held for serial transmission. Writing a byte to SBUF0 initiates the transmission. A read of SBUF0 returns the contents of the receive latch.

Rev. 1.4

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Table 17.1. Timer Settings for Standard Baud Rates Using The Internal Oscillator

SYSCLK = 24 MHz

SYSCLK = 12 MHz

Target
Actual Baud Rate
Baud Rate Baud Rate
Error
(bps)
(bps)

Oscillator Timer Clock SCA1-SCA0 T1M*
Timer 1
Divide
Source
(pre-scale
Reload
Factor
select)*
Value (hex)

230400

230769

0.16%

SYSCLK

0xE6

115200

115385

0.16%

104

SYSCLK

0xCC

57600

57692

0.16%

208

SYSCLK

0x98

28800

28846

0.16%

416

SYSCLK

0x30

14400

14423

0.16%

832

SYSCLK / 4

0x98

9600

9615

0.16%

1248

SYSCLK / 4

0x64

2400

2404

0.16%

4992

SYSCLK / 12

0x30

1200

1202

0.16%

9984

SYSCLK / 48

0x98

230400

230769

0.16%

104

SYSCLK

0xCC

115200

115385

0.16%

208

SYSCLK

0x98

57600

57692

0.16%

416

SYSCLK

0x30

28800

28846

0.16%

832

SYSCLK / 4

0x98

14400

14423

0.16%

1664

SYSCLK / 4

0x30

9600

9615

0.16%

2496

SYSCLK / 12

0x98

2400

2404

0.16%

9984

SYSCLK / 48

0x98

1200

1202

0.16%

19968

SYSCLK / 48

0x30

X = Don’t care
*Note: SCA1-SCA0 and T1M define the Timer Clock Source. Bit definitions for these values can be found in Section
“19.1. Timer 0 and Timer 1” on page 209.

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18. Enhanced Serial Peripheral Interface (SPI0)
The Enhanced Serial Peripheral Interface (SPI0) provides access to a flexible, full-duplex synchronous
serial bus. SPI0 can operate as a master or slave device in both 3-wire or 4-wire modes, and supports multiple masters and slaves on a single SPI bus. The slave-select (NSS) signal can be configured as an input
to select SPI0 in slave mode, or to disable Master Mode operation in a multi-master environment, avoiding
contention on the SPI bus when more than one master attempts simultaneous data transfers. NSS can
also be configured as a chip-select output in master mode, or disabled for 3-wire operation. Additional general purpose port I/O pins can be used to select multiple slave devices in master mode.

SFR Bus

SYSCLK

SPI0CN
SPIF
WCOL
MODF
RXOVRN
NSSMD1
NSSMD0
TXBMT
SPIEN

SPI0CFG
SPIBSY
MSTEN
CKPHA
CKPOL
SLVSEL
NSSIN
SRMT
RXBMT

SCR7
SCR6
SCR5
SCR4
SCR3
SCR2
SCR1
SCR0

SPI0CKR

Clock Divide
Logic

SPI CONTROL LOGIC
Data Path
Control

SPI IRQ

Pin Interface
Control

MOSI

Tx Data

SPI0DAT

SCK

Transmit Data Buffer

Shift Register

7 6 5 4 3 2 1 0

Rx Data

Pin
Control
Logic

Receive Data Buffer

MISO

C
R
O
S
S
B
A
R

Port I/O

NSS

Read
SPI0DAT

Write
SPI0DAT

SFR Bus

Figure 18.1. SPI Block Diagram

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18.1. Signal Descriptions
The four signals used by SPI0 (MOSI, MISO, SCK, NSS) are described below.

18.1.1. Master Out, Slave In (MOSI)
The master-out, slave-in (MOSI) signal is an output from a master device and an input to slave devices. It
is used to serially transfer data from the master to the slave. This signal is an output when SPI0 is operating as a master and an input when SPI0 is operating as a slave. Data is transferred most-significant bit
first. When configured as a master, MOSI is driven by the MSB of the shift register in both 3- and 4-wire
mode.

18.1.2. Master In, Slave Out (MISO)
The master-in, slave-out (MISO) signal is an output from a slave device and an input to the master device.
It is used to serially transfer data from the slave to the master. This signal is an input when SPI0 is operating as a master and an output when SPI0 is operating as a slave. Data is transferred most-significant bit
first. The MISO pin is placed in a high-impedance state when the SPI module is disabled and when the SPI
operates in 4-wire mode as a slave that is not selected. When acting as a slave in 3-wire mode, MISO is
always driven by the MSB of the shift register.

18.1.3. Serial Clock (SCK)
The serial clock (SCK) signal is an output from the master device and an input to slave devices. It is used
to synchronize the transfer of data between the master and slave on the MOSI and MISO lines. SPI0 generates this signal when operating as a master. The SCK signal is ignored by a SPI slave when the slave is
not selected (NSS = 1) in 4-wire slave mode.

18.1.4. Slave Select (NSS)
The function of the slave-select (NSS) signal is dependent on the setting of the NSSMD1 and NSSMD0
bits in the SPI0CN register. There are three possible modes that can be selected with these bits:
1. NSSMD[1:0] = 00: 3-Wire Master or 3-Wire Slave Mode: SPI0 operates in 3-wire mode, and
NSS is disabled. When operating as a slave device, SPI0 is always selected in 3-wire mode.
Since no select signal is present, SPI0 must be the only slave on the bus in 3-wire mode. This
is intended for point-to-point communication between a master and one slave.
2. NSSMD[1:0] = 01: 4-Wire Slave or Multi-Master Mode: SPI0 operates in 4-wire mode, and
NSS is enabled as an input. When operating as a slave, NSS selects the SPI0 device. When
operating as a master, a 1-to-0 transition of the NSS signal disables the master function of
SPI0 so that multiple master devices can be used on the same SPI bus.
3. NSSMD[1:0] = 1x: 4-Wire Master Mode: SPI0 operates in 4-wire mode, and NSS is enabled as
an output. The setting of NSSMD0 determines what logic level the NSS pin will output. This
configuration should only be used when operating SPI0 as a master device.

See Figure 18.2, Figure 18.3, and Figure 18.4 for typical connection diagrams of the various operational
modes. Note that the setting of NSSMD bits affects the pinout of the device. When in 3-wire master or
3-wire slave mode, the NSS pin will not be mapped by the crossbar. In all other modes, the NSS signal will
be mapped to a pin on the device. See Section “14. Port Input/Output” on page 126 for general purpose
port I/O and crossbar information.

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18.2. SPI0 Master Mode Operation
A SPI master device initiates all data transfers on a SPI bus. SPI0 is placed in master mode by setting the
Master Enable flag (MSTEN, SPI0CN.6). Writing a byte of data to the SPI0 data register (SPI0DAT) when
in master mode writes to the transmit buffer. If the SPI shift register is empty, the byte in the transmit buffer
is moved to the shift register, and a data transfer begins. The SPI0 master immediately shifts out the data
serially on the MOSI line while providing the serial clock on SCK. The SPIF (SPI0CN.7) flag is set to logic
1 at the end of the transfer. If interrupts are enabled, an interrupt request is generated when the SPIF flag
is set. While the SPI0 master transfers data to a slave on the MOSI line, the addressed SPI slave device
simultaneously transfers the contents of its shift register to the SPI master on the MISO line in a full-duplex
operation. Therefore, the SPIF flag serves as both a transmit-complete and receive-data-ready flag. The
data byte received from the slave is transferred MSB-first into the master's shift register. When a byte is
fully shifted into the register, it is moved to the receive buffer where it can be read by the processor by
reading SPI0DAT.
When configured as a master, SPI0 can operate in one of three different modes: multi-master mode, 3-wire
single-master mode, and 4-wire single-master mode. The default, multi-master mode is active when NSSMD1 (SPI0CN.3) = 0 and NSSMD0 (SPI0CN.2) = 1. In this mode, NSS is an input to the device, and is
used to disable the master SPI0 when another master is accessing the bus. When NSS is pulled low in this
mode, MSTEN (SPI0CN.6) and SPIEN (SPI0CN.0) are set to 0 to disable the SPI master device, and a
Mode Fault is generated (MODF, SPI0CN.5 = 1). Mode Fault will generate an interrupt if enabled. SPI0
must be manually re-enabled in software under these circumstances. In multi-master systems, devices will
typically default to being slave devices while they are not acting as the system master device. In multi-master mode, slave devices can be addressed individually (if needed) using general-purpose I/O pins.
Figure 18.2 shows a connection diagram between two master devices in multiple-master mode.
3-wire single-master mode is active when NSSMD1 (SPI0CN.3) = 0 and NSSMD0 (SPI0CN.2) = 0. In this
mode, NSS is not used, and is not mapped to an external port pin through the crossbar. Any slave devices
that must be addressed in this mode should be selected using general-purpose I/O pins. Figure 18.3
shows a connection diagram between a master device in 3-wire master mode and a slave device.
4-wire single-master mode is active when NSSMD1 (SPI0CN.3) = 1. In this mode, NSS is configured as an
output pin, and can be used as a slave-select signal for a single SPI device. In this mode, the output value
of NSS is controlled (in software) with the bit NSSMD0 (SPI0CN.2). Additional slave devices can be
addressed using general-purpose I/O pins. Figure 18.4 shows a connection diagram for a master device in
4-wire master mode and two slave devices.

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Master
Device 1

NSS

GPIO

MISO

MOSI

SCK

GPIO

NSS

Master
Device 2

Figure 18.2. Multiple-Master Mode Connection Diagram

Master
Device

MISO

MOSI

SCK

Slave
Device

Figure 18.3. 3-Wire Single Master and Slave Mode Connection Diagram

Master
Device
GPIO

MISO

MOSI

SCK

NSS

MISO
MOSI

Slave
Device

SCK
NSS

Figure 18.4. 4-Wire Single Master Mode and 4-Wire Slave Mode Connection
Diagram
18.3. SPI0 Slave Mode Operation
When SPI0 is enabled and not configured as a master, it will operate as a SPI slave. As a slave, bytes are
shifted in through the MOSI pin and out through the MISO pin by a master device controlling the SCK signal. A bit counter in the SPI0 logic counts SCK edges. When 8 bits have been shifted through the shift register, the SPIF flag is set to logic 1, and the byte is copied into the receive buffer. Data is read from the
receive buffer by reading SPI0DAT. A slave device cannot initiate transfers. Data to be transferred to the
master device is pre-loaded into the shift register by writing to SPI0DAT. Writes to SPI0DAT are doublebuffered, and are placed in the transmit buffer first. If the shift register is empty, the contents of the transmit
buffer will immediately be transferred into the shift register. When the shift register already contains data,
the SPI will load the shift register with the transmit buffer’s contents after the last SCK edge of the next (or
current) SPI transfer.

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When configured as a slave, SPI0 can be configured for 4-wire or 3-wire operation. The default, 4-wire
slave mode, is active when NSSMD1 (SPI0CN.3) = 0 and NSSMD0 (SPI0CN.2) = 1. In 4-wire mode, the
NSS signal is routed to a port pin and configured as a digital input. SPI0 is enabled when NSS is logic 0,
and disabled when NSS is logic 1. The bit counter is reset on a falling edge of NSS. Note that the NSS signal must be driven low at least 2 system clocks before the first active edge of SCK for each byte transfer.
Figure 18.4 shows a connection diagram between two slave devices in 4-wire slave mode and a master
device.
3-wire slave mode is active when NSSMD1 (SPI0CN.3) = 0 and NSSMD0 (SPI0CN.2) = 0. NSS is not
used in this mode, and is not mapped to an external port pin through the crossbar. Since there is no way of
uniquely addressing the device in 3-wire slave mode, SPI0 must be the only slave device present on the
bus. It is important to note that in 3-wire slave mode there is no external means of resetting the bit counter
that determines when a full byte has been received. The bit counter can only be reset by disabling and reenabling SPI0 with the SPIEN bit. Figure 18.3 shows a connection diagram between a slave device in 3wire slave mode and a master device.

18.4. SPI0 Interrupt Sources
When SPI0 interrupts are enabled, the following four flags will generate an interrupt when they are set to
logic 1:
Note that all of the following bits must be cleared by software.
1. The SPI Interrupt Flag, SPIF (SPI0CN.7) is set to logic 1 at the end of each byte transfer. This
flag can occur in all SPI0 modes.
2. The Write Collision Flag, WCOL (SPI0CN.6) is set to logic 1 if a write to SPI0DAT is attempted
when the transmit buffer has not been emptied to the SPI shift register. When this occurs, the
write to SPI0DAT will be ignored, and the transmit buffer will not be written.This flag can occur
in all SPI0 modes.
3. The Mode Fault Flag MODF (SPI0CN.5) is set to logic 1 when SPI0 is configured as a master,
and for multi-master mode and the NSS pin is pulled low. When a Mode Fault occurs, the
MSTEN and SPIEN bits in SPI0CN are set to logic 0 to disable SPI0 and allow another master
device to access the bus.
4. The Receive Overrun Flag RXOVRN (SPI0CN.4) is set to logic 1 when configured as a slave,
and a transfer is completed and the receive buffer still holds an unread byte from a previous
transfer. The new byte is not transferred to the receive buffer, allowing the previously received
data byte to be read. The data byte which caused the overrun is lost.

18.5. Serial Clock Timing
Four combinations of serial clock phase and polarity can be selected using the clock control bits in the
SPI0 Configuration Register (SPI0CFG). The CKPHA bit (SPI0CFG.5) selects one of two clock phases
(edge used to latch the data). The CKPOL bit (SPI0CFG.4) selects between an active-high or active-low
clock. Both master and slave devices must be configured to use the same clock phase and polarity. SPI0
should be disabled (by clearing the SPIEN bit, SPI0CN.0) when changing the clock phase or polarity. The
clock and data line relationships for master mode are shown in Figure 18.5. For slave mode, the clock and
data relationships are shown in Figure 18.6 and Figure 18.7. Note that CKPHA must be set to ‘0’ on both
the master and slave SPI when communicating between two of the following devices: C8051F04x,
C8051F06x, C8051F12x, C8051F31x, C8051F32x, and C8051F33x
The SPI0 Clock Rate Register (SPI0CKR) as shown in Figure 18.3 controls the master mode serial clock
frequency. This register is ignored when operating in slave mode. When the SPI is configured as a master,
the maximum data transfer rate (bits/sec) is one-half the system clock frequency or 12.5 MHz, whichever is

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slower. When the SPI is configured as a slave, the maximum data transfer rate (bits/sec) for full-duplex
operation is 1/10 the system clock frequency, provided that the master issues SCK, NSS (in 4-wire slave
mode), and the serial input data synchronously with the slave’s system clock. If the master issues SCK,
NSS, and the serial input data asynchronously, the maximum data transfer rate (bits/sec) must be less
than 1/10 the system clock frequency. In the special case where the master only wants to transmit data to
the slave and does not need to receive data from the slave (i.e. half-duplex operation), the SPI slave can
receive data at a maximum data transfer rate (bits/sec) of 1/4 the system clock frequency. This is provided
that the master issues SCK, NSS, and the serial input data synchronously with the slave’s system clock.

SCK
(CKPOL=0, CKPHA=0)

SCK
(CKPOL=0, CKPHA=1)

SCK
(CKPOL=1, CKPHA=0)

SCK
(CKPOL=1, CKPHA=1)

MISO/MOSI

MSB

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

NSS (Must Remain High
in Multi-Master Mode)

Figure 18.5. Master Mode Data/Clock Timing

SCK
(CKPOL=0, CKPHA=0)

SCK
(CKPOL=1, CKPHA=0)

MOSI

MSB

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

MISO

MSB

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

NSS (4-Wire Mode)

Figure 18.6. Slave Mode Data/Clock Timing (CKPHA = 0)

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SCK
(CKPOL=0, CKPHA=1)

SCK
(CKPOL=1, CKPHA=1)

MOSI

MSB

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

MISO

MSB

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

NSS (4-Wire Mode)

Figure 18.7. Slave Mode Data/Clock Timing (CKPHA = 1)

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18.6. SPI Special Function Registers
SPI0 is accessed and controlled through four special function registers in the system controller: SPI0CN
Control Register, SPI0DAT Data Register, SPI0CFG Configuration Register, and SPI0CKR Clock Rate
Register. The four special function registers related to the operation of the SPI0 Bus are described in the
following figures.

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SFR Definition 18.1. SPI0CFG: SPI0 Configuration
R

R/W

Reset Value

SPIBSY

MSTEN

CKPHA

CKPOL

SLVSEL

NSSIN

SRMT

RXBMT

00000111

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0
SFR Address: 0xA1

Bit 7:
Bit 6:

Bit 5:

Bit 4:

Bit 3:

Bit 2:

Bit 1:

Bit 0:

*Note:

SPIBSY: SPI Busy (read only).
This bit is set to logic 1 when a SPI transfer is in progress (Master or slave Mode).
MSTEN: Master Mode Enable.
0: Disable master mode. Operate in slave mode.
1: Enable master mode. Operate as a master.
CKPHA: SPI0 Clock Phase.
This bit controls the SPI0 clock phase.
0: Data centered on first edge of SCK period.*
1: Data centered on second edge of SCK period.*
CKPOL: SPI0 Clock Polarity.
This bit controls the SPI0 clock polarity.
0: SCK line low in idle state.
1: SCK line high in idle state.
SLVSEL: Slave Selected Flag (read only).
This bit is set to logic 1 whenever the NSS pin is low indicating SPI0 is the selected slave. It
is cleared to logic 0 when NSS is high (slave not selected). This bit does not indicate the
instantaneous value at the NSS pin, but rather a de-glitched version of the pin input.
NSSIN: NSS Instantaneous Pin Input (read only).
This bit mimics the instantaneous value that is present on the NSS port pin at the time that
the register is read. This input is not de-glitched.
SRMT: Shift Register Empty (Valid in Slave Mode, read only).
This bit will be set to logic 1 when all data has been transferred in/out of the shift register,
and there is no new information available to read from the transmit buffer or write to the
receive buffer. It returns to logic 0 when a data byte is transferred to the shift register from
the transmit buffer or by a transition on SCK.
NOTE: SRMT = 1 when in Master Mode.
RXBMT: Receive Buffer Empty (Valid in Slave Mode, read only).
This bit will be set to logic 1 when the receive buffer has been read and contains no new
information. If there is new information available in the receive buffer that has not been read,
this bit will return to logic 0.
NOTE: RXBMT = 1 when in Master Mode.
In slave mode, data on MOSI is sampled in the center of each data bit. In master mode, data on MISO is
sampled one SYSCLK before the end of each data bit, to provide maximum settling time for the slave
device. See Table 18.1 for timing parameters.

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SFR Definition 18.2. SPI0CN: SPI0 Control
R/W

R/W

SPIF

WCOL

MODF

Bit7

Bit6

Bit5

R/W

RXOVRN NSSMD1 NSSMD0 TXBMT
Bit4

Bit3

Bit2

Bit1

R/W

Reset Value

SPIEN

00000110

Bit0

Bit Addressable

SFR Address: 0xF8

Bit 7:

SPIF: SPI0 Interrupt Flag.
This bit is set to logic 1 by hardware at the end of a data transfer. If interrupts are enabled,
setting this bit causes the CPU to vector to the SPI0 interrupt service routine. This bit is not
automatically cleared by hardware. It must be cleared by software.
Bit 6:
WCOL: Write Collision Flag.
This bit is set to logic 1 by hardware (and generates a SPI0 interrupt) to indicate that a write
to the SPI0 data register was attempted while the transmit buffer already contained data. It
must be cleared by software.
Bit 5:
MODF: Mode Fault Flag.
This bit is set to logic 1 by hardware (and generates a SPI0 interrupt) when a master mode
collision is detected (NSS is low, MSTEN = 1, and NSSMD[1:0] = 01). This bit is not automatically cleared by hardware. It must be cleared by software.
Bit 4:
RXOVRN: Receive Overrun Flag (Slave Mode only).
This bit is set to logic 1 by hardware (and generates a SPI0 interrupt) when the receive buffer still holds unread data from a previous transfer and the last bit of the current transfer is
shifted into the SPI0 shift register. This bit is not automatically cleared by hardware. It must
be cleared by software.
Bits 3–2: NSSMD1–NSSMD0: Slave Select Mode.
Selects between the following NSS operation modes:
(See Section “18.2. SPI0 Master Mode Operation” on page 197 and Section “18.3. SPI0
Slave Mode Operation” on page 198).
00: 3-Wire Slave or 3-wire Master Mode. NSS signal is not routed to a port pin.
01: 4-Wire Slave or Multi-Master Mode (Default). NSS is always an input to the device.
1x: 4-Wire Single-Master Mode. NSS signal is mapped as an output from the device and will
assume the value of NSSMD0.
Bit 1:
TXBMT: Transmit Buffer Empty.
This bit will be set to logic 0 when new data has been written to the transmit buffer. When
data in the transmit buffer is transferred to the SPI shift register, this bit will be set to logic 1,
indicating that it is safe to write a new byte to the transmit buffer.
Bit 0:
SPIEN: SPI0 Enable.
This bit enables/disables the SPI.
0: SPI disabled.
1: SPI enabled.

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SFR Definition 18.4. SPI0DAT: SPI0 Data Register
R/W

R/W

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

Reset Value

00000000
SFR
0xA3
Address:

Bits 7–0: SPI0DAT: SPI0 Transmit and Receive Data.
The SPI0DAT register is used to transmit and receive SPI0 data. Writing data to SPI0DAT
places the data into the transmit buffer and initiates a transfer when in Master Mode. A read
of SPI0DAT returns the contents of the receive buffer.

SFR Definition 18.3. SPI0CKR: SPI0 Clock Rate
R/W

R/W

Reset Value

SCR7

SCR6

SCR5

SCR4

SCR3

SCR2

SCR1

SCR0

00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0
SFR Address: 0xA2

Bits 7–0: SCR7-SCR0: SPI0 Clock Rate.
These bits determine the frequency of the SCK output when the SPI0 module is configured
for master mode operation. The SCK clock frequency is a divided version of the system
clock, and is given in the following equation, where SYSCLK is the system clock frequency
and SPI0CKR is the 8-bit value held in the SPI0CKR register.

SYSCLK
f SCK = ------------------------------------------------2 × ( SPI0CKR + 1 )
for 0 <= SPI0CKR <= 255
Example: If SYSCLK = 2 MHz and SPI0CKR = 0x04,

2000000
f SCK = -------------------------2 × (4 + 1)

f SCK = 200kHz

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SCK*
T

MCKH

MCKL

MIS

MIH

MISO

MOSI

* SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1.

Figure 18.8. SPI Master Timing (CKPHA = 0)

SCK*
T

MCKH

MCKL

MIS

MIH

MISO

MOSI

* SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1.

Figure 18.9. SPI Master Timing (CKPHA = 1)

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NSS
T

CKL

SCK*
T

CKH

SIS

SIH

MOSI

SEZ

SOH

SDZ

MISO

* SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1.

Figure 18.10. SPI Slave Timing (CKPHA = 0)

NSS
T

CKL

SCK*
T

CKH

SIS

SIH

MOSI

SEZ

SOH

SLH

SDZ

MISO

* SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1.

Figure 18.11. SPI Slave Timing (CKPHA = 1)

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Table 18.1. SPI Slave Timing Parameters
Parameter

Description

Min

Max

Units

Master Mode Timing* (See Figure 18.8 and Figure 18.9)
TMCKH

SCK High Time

1 x TSYSCLK

—

TMCKL

SCK Low Time

1 x TSYSCLK

—

TMIS

MISO Valid to SCK Shift Edge

1 x TSYSCLK + 20

—

TMIH

SCK Shift Edge to MISO Change

—

Slave Mode Timing* (See Figure 18.10 and Figure 18.11)
TSE

NSS Falling to First SCK Edge

2 x TSYSCLK

—

TSD

Last SCK Edge to NSS Rising

2 x TSYSCLK

—

TSEZ

NSS Falling to MISO Valid

—

4 x TSYSCLK

TSDZ

NSS Rising to MISO High-Z

—

4 x TSYSCLK

TCKH

SCK High Time

5 x TSYSCLK

—

TCKL

SCK Low Time

5 x TSYSCLK

—

TSIS

MOSI Valid to SCK Sample Edge

2 x TSYSCLK

—

TSIH

SCK Sample Edge to MOSI Change

2 x TSYSCLK

—

TSOH

SCK Shift Edge to MISO Change

—

4 x TSYSCLK

TSLH

Last SCK Edge to MISO Change (CKPHA = 1
ONLY)

6 x TSYSCLK

8 x TSYSCLK

*Note: TSYSCLK is equal to one period of the device system clock (SYSCLK).

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19. Timers
Each MCU includes four counter/timers: two are 16-bit counter/timers compatible with those found in the
standard 8051, and two are 16-bit auto-reload timer for use with the ADC, SMBus, USB (frame measurements), or for general purpose use. These timers can be used to measure time intervals, count external
events and generate periodic interrupt requests. Timer 0 and Timer 1 are nearly identical and have four primary modes of operation. Timer 2 and Timer 3 offer 16-bit and split 8-bit timer functionality with autoreload.
Timer 0 and Timer 1 Modes:
13-bit counter/timer
16-bit counter/timer
8-bit counter/timer with auto-reload
Two 8-bit counter/timers (Timer 0 only)

Timer 2 Modes:

Timer 3 Modes:

16-bit timer with auto-reload

Two 8-bit timers with
auto-reload

Timers 0 and 1 may be clocked by one of five sources, determined by the Timer Mode Select bits (T1MT0M) and the Clock Scale bits (SCA1-SCA0). The Clock Scale bits define a pre-scaled clock from which
Timer 0 and/or Timer 1 may be clocked (See Figure 19.3 for pre-scaled clock selection).
Timer 0/1 may then be configured to use this pre-scaled clock signal or the system clock. Timer 2 and
Timer 3 may be clocked by the system clock, the system clock divided by 12, or the external oscillator
clock source divided by 8.
Timer 0 and Timer 1 may also be operated as counters. When functioning as a counter, a counter/timer
register is incremented on each high-to-low transition at the selected input pin (T0 or T1). Events with a frequency of up to one-fourth the system clock's frequency can be counted. The input signal need not be periodic, but it should be held at a given level for at least two full system clock cycles to ensure the level is
properly sampled.

19.1. Timer 0 and Timer 1
Each timer is implemented as a 16-bit register accessed as two separate bytes: a low byte (TL0 or TL1)
and a high byte (TH0 or TH1). The Counter/Timer Control register (TCON) is used to enable Timer 0 and
Timer 1 as well as indicate status. Timer 0 interrupts can be enabled by setting the ET0 bit in the IE register
(Section “9.3.5. Interrupt Register Descriptions” on page 90); Timer 1 interrupts can be enabled by setting
the ET1 bit in the IE register (SFR Definition 9.7). Both counter/timers operate in one of four primary
modes selected by setting the Mode Select bits T1M1-T0M0 in the Counter/Timer Mode register (TMOD).
Each timer can be configured independently. Each operating mode is described below.

19.1.1. Mode 0: 13-bit Counter/Timer
Timer 0 and Timer 1 operate as 13-bit counter/timers in Mode 0. The following describes the configuration
and operation of Timer 0. However, both timers operate identically, and Timer 1 is configured in the same
manner as described for Timer 0.
The TH0 register holds the eight MSBs of the 13-bit counter/timer. TL0 holds the five LSBs in bit positions
TL0.4-TL0.0. The three upper bits of TL0 (TL0.7-TL0.5) are indeterminate and should be masked out or
ignored when reading. As the 13-bit timer register increments and overflows from 0x1FFF (all ones) to
0x0000, the timer overflow flag TF0 (TCON.5) is set and an interrupt will occur if Timer 0 interrupts are
enabled.
The C/T0 bit (TMOD.2) selects the counter/timer's clock source. When C/T0 is set to logic 1, high-to-low
transitions at the selected Timer 0 input pin (T0) increment the timer register (Refer to Section

Rev. 1.4

209

C8051F320/1
“14.1. Priority Crossbar Decoder” on page 128 for information on selecting and configuring external I/O
pins). Clearing C/T selects the clock defined by the T0M bit (CKCON.3). When T0M is set, Timer 0 is
clocked by the system clock. When T0M is cleared, Timer 0 is clocked by the source selected by the Clock
Scale bits in CKCON (see Figure 19.3).
Setting the TR0 bit (TCON.4) enables the timer when either GATE0 (TMOD.3) is logic 0 or the input signal
/INT0 is active as defined by bit IN0PL in register INT01CF (see Figure 8.13). Setting GATE0 to ‘1’ allows
the timer to be controlled by the external input signal /INT0 (see Section “9.3.5. Interrupt Register Descriptions” on page 90), facilitating pulse width measurements.
TR0
GATE0
0
X
1
0
1
1
1
1
X = Don't Care

/INT0
X
X
0
1

Counter/Timer
Disabled
Enabled
Disabled
Enabled

Setting TR0 does not force the timer to reset. The timer registers should be loaded with the desired initial
value before the timer is enabled.
TL1 and TH1 form the 13-bit register for Timer 1 in the same manner as described above for TL0 and TH0.
Timer 1 is configured and controlled using the relevant TCON and TMOD bits just as with Timer 0. The
input signal /INT1 is used with Timer 1; the /INT1 polarity is defined by bit IN1PL in register INT01CF (see
Figure 8.13).

CKCON

TMOD

TTTTTTSS
3 3 2 2 1 0 CC
MMMMMM A A
HLHL
1 0

Pre-scaled Clock

G
A
T
E
1

C
/
T
1

T TG
1 1 A
MM T
1 0 E
0

C
/
T
0

INT01CF
T T
0 0
MM
1 0

I
N
1
P
L

I
N
1
S
L
2

I
N
1
S
L
1

I
N
1
S
L
0

I
N
0
P
L

I
N
0
S
L
2

I
N
0
S
L
1

I
N
0
S
L
0

0
0

SYSCLK

1
1

TCLK

TR0

TL0
(5 bits)

TH0
(8 bits)

GATE0
Crossbar

/INT0

IN0PL

XOR

Figure 19.1. T0 Mode 0 Block Diagram

210

Rev. 1.4

TCON

TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0

Interrupt

C8051F320/1
19.1.2. Mode 1: 16-bit Counter/Timer
Mode 1 operation is the same as Mode 0, except that the counter/timer registers use all 16 bits. The
counter/timers are enabled and configured in Mode 1 in the same manner as for Mode 0.

19.1.3. Mode 2: 8-bit Counter/Timer with Auto-Reload
Mode 2 configures Timer 0 and Timer 1 to operate as 8-bit counter/timers with automatic reload of the start
value. TL0 holds the count and TH0 holds the reload value. When the counter in TL0 overflows from all
ones to 0x00, the timer overflow flag TF0 (TCON.5) is set and the counter in TL0 is reloaded from TH0. If
Timer 0 interrupts are enabled, an interrupt will occur when the TF0 flag is set. The reload value in TH0 is
not changed. TL0 must be initialized to the desired value before enabling the timer for the first count to be
correct. When in Mode 2, Timer 1 operates identically to Timer 0.
Both counter/timers are enabled and configured in Mode 2 in the same manner as Mode 0. Setting the
TR0 bit (TCON.4) enables the timer when either GATE0 (TMOD.3) is logic 0 or when the input signal /INT0
is active as defined by bit IN0PL in register INT01CF (see Section “9.3.2. External Interrupts” on page 88
for details on the external input signals /INT0 and /INT1).

CKCON
TTTTTTSS
3 3 2 2 1 0CC
MMMMMM A A
HLHL
1 0

Pre-scaled Clock

TMOD
G
A
T
E
1

C
/
T
1

T TG
1 1 A
MM T
1 0 E
0

C
/
T
0

INT01CF
T T
0 0
MM
1 0

I
N
1
P
L

I
N
1
S
L
2

I
N
1
S
L
1

I
N
1
S
L
0

I
N
0
P
L

I
N
0
S
L
2

I
N
0
S
L
1

I
N
0
S
L
0

0
0

SYSCLK

1
1

T0
TL0
(8 bits)
TCON

TCLK

TR0
Crossbar

GATE0
TH0
(8 bits)

/INT0

IN0PL

TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0

Interrupt

Reload

XOR

Figure 19.2. T0 Mode 2 Block Diagram

Rev. 1.4

211

C8051F320/1
19.1.4. Mode 3: Two 8-bit Counter/Timers (Timer 0 Only)
In Mode 3, Timer 0 is configured as two separate 8-bit counter/timers held in TL0 and TH0. The
counter/timer in TL0 is controlled using the Timer 0 control/status bits in TCON and TMOD: TR0, C/T0,
GATE0 and TF0. TL0 can use either the system clock or an external input signal as its timebase. The TH0
register is restricted to a timer function sourced by the system clock or prescaled clock. TH0 is enabled
using the Timer 1 run control bit TR1. TH0 sets the Timer 1 overflow flag TF1 on overflow and thus controls
the Timer 1 interrupt.
Timer 1 is inactive in Mode 3. When Timer 0 is operating in Mode 3, Timer 1 can be operated in Modes 0,
1 or 2, but cannot be clocked by external signals nor set the TF1 flag and generate an interrupt. However,
the Timer 1 overflow can be used to generate baud rates for the SMBus and/or UART, and/or initiate ADC
conversions. While Timer 0 is operating in Mode 3, Timer 1 run control is handled through its mode settings. To run Timer 1 while Timer 0 is in Mode 3, set the Timer 1 Mode as 0, 1, or 2. To disable Timer 1,
configure it for Mode 3.

CKCON

TMOD

T T T T T TSS
3 3 2 2 1 0 CC
MMMMMM A A
HLHL
1 0

Pre-scaled Clock

G
A
T
E
1

C
/
T
1

T T
1 1
MM
1 0

G
A
T
E
0

C
/
T
0

T T
0 0
MM
1 0

0
TR1

SYSCLK

TH0
(8 bits)

1
TCON

1
T0
TL0
(8 bits)
TR0
Crossbar

/INT0

GATE0

IN0PL

XOR

Figure 19.3. T0 Mode 3 Block Diagram

212

Rev. 1.4

TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0

Interrupt
Interrupt

C8051F320/1
SFR Definition 19.1. TCON: Timer Control
R/W

R/W

Reset Value

TF1

TR1

TF0

TR0

IE1

IT1

IE0

IT0

00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

(bit addressable)

Bit7:

Bit6:

Bit5:

Bit4:

Bit3:

Bit2:

Bit1:

Bit0:

0x88

TF1: Timer 1 Overflow Flag.
Set by hardware when Timer 1 overflows. This flag can be cleared by software but is automatically cleared when the CPU vectors to the Timer 1 interrupt service routine.
0: No Timer 1 overflow detected.
1: Timer 1 has overflowed.
TR1: Timer 1 Run Control.
0: Timer 1 disabled.
1: Timer 1 enabled.
TF0: Timer 0 Overflow Flag.
Set by hardware when Timer 0 overflows. This flag can be cleared by software but is automatically cleared when the CPU vectors to the Timer 0 interrupt service routine.
0: No Timer 0 overflow detected.
1: Timer 0 has overflowed.
TR0: Timer 0 Run Control.
0: Timer 0 disabled.
1: Timer 0 enabled.
IE1: External Interrupt 1.
This flag is set by hardware when an edge/level of type defined by IT1 is detected. It can be
cleared by software but is automatically cleared when the CPU vectors to the External Interrupt 1 service routine if IT1 = 1. When IT1 = 0, this flag is set to ‘1’ when /INT1 is active as
defined by bit IN1PL in register IT01CF (see SFR Definition 9.13).
IT1: Interrupt 1 Type Select.
This bit selects whether the configured /INT1 interrupt will be edge or level sensitive. /INT1
is configured active low or high by the IN1PL bit in the IT01CF register (see SFR Definition
9.13).
0: /INT1 is level triggered.
1: /INT1 is edge triggered.
IE0: External Interrupt 0.
This flag is set by hardware when an edge/level of type defined by IT0 is detected. It can be
cleared by software but is automatically cleared when the CPU vectors to the External Interrupt 0 service routine if IT0 = 1. When IT0 = 0, this flag is set to ‘1’ when /INT0 is active as
defined by bit IN0PL in register IT01CF (see SFR Definition 9.13).
IT0: Interrupt 0 Type Select.
This bit selects whether the configured /INT0 interrupt will be edge or level sensitive. /INT0
is configured active low or high by the IN0PL bit in register IT01CF (see SFR Definition
9.13).
0: /INT0 is level triggered.
1: /INT0 is edge triggered.

Rev. 1.4

213

C8051F320/1
SFR Definition 19.2. TMOD: Timer Mode
R/W

R/W

Reset Value

GATE1

C/T1

T1M1

T1M0

GATE0

C/T0

T0M1

T0M0

00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

0x89
Bit7:

GATE1: Timer 1 Gate Control.
0: Timer 1 enabled when TR1 = 1 irrespective of /INT1 logic level.
1: Timer 1 enabled only when TR1 = 1 AND /INT1 is active as defined by bit IN1PL in register IT01CF (see SFR Definition 9.13).
Bit6:
C/T1: Counter/Timer 1 Select.
0: Timer Function: Timer 1 incremented by clock defined by T1M bit (CKCON.3).
1: Counter Function: Timer 1 incremented by high-to-low transitions on external input pin
(T1).
Bits5–4: T1M1–T1M0: Timer 1 Mode Select.
These bits select the Timer 1 operation mode.
T1M1
0
0

T1M0
0
1

Mode
Mode 0: 13-bit counter/timer
Mode 1: 16-bit counter/timer
Mode 2: 8-bit counter/timer with autoreload
Mode 3: Timer 1 inactive

Bit3:

GATE0: Timer 0 Gate Control.
0: Timer 0 enabled when TR0 = 1 irrespective of /INT0 logic level.
1: Timer 0 enabled only when TR0 = 1 AND /INT0 is active as defined by bit IN0PL in register IT01CF (see SFR Definition 9.13).
Bit2:
C/T0: Counter/Timer Select.
0: Timer Function: Timer 0 incremented by clock defined by T0M bit (CKCON.2).
1: Counter Function: Timer 0 incremented by high-to-low transitions on external input pin
(T0).
Bits1–0: T0M1–T0M0: Timer 0 Mode Select.
These bits select the Timer 0 operation mode.

214

T0M1
0
0

T0M0
0
1

Mode
Mode 0: 13-bit counter/timer
Mode 1: 16-bit counter/timer
Mode 2: 8-bit counter/timer with autoreload
Mode 3: Two 8-bit counter/timers

Rev. 1.4

C8051F320/1
SFR Definition 19.3. CKCON: Clock Control
R/W

R/W

Reset Value

T3MH

T3ML

T2MH

T2ML

T1M

T0M

SCA1

SCA0

00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

0x8E
Bit7:

T3MH: Timer 3 High Byte Clock Select.
This bit selects the clock supplied to the Timer 3 high byte if Timer 3 is configured in split 8bit timer mode. T3MH is ignored if Timer 3 is in any other mode.
0: Timer 3 high byte uses the clock defined by the T3XCLK bit in TMR3CN.
1: Timer 3 high byte uses the system clock.
Bit6:
T3ML: Timer 3 Low Byte Clock Select.
This bit selects the clock supplied to Timer 3. If Timer 3 is configured in split 8-bit timer
mode, this bit selects the clock supplied to the lower 8-bit timer.
0: Timer 3 low byte uses the clock defined by the T3XCLK bit in TMR3CN.
1: Timer 3 low byte uses the system clock.
Bit5:
T2MH: Timer 2 High Byte Clock Select.
This bit selects the clock supplied to the Timer 2 high byte if Timer 2 is configured in split 8bit timer mode. T2MH is ignored if Timer 2 is in any other mode.
0: Timer 2 high byte uses the clock defined by the T2XCLK bit in TMR2CN.
1: Timer 2 high byte uses the system clock.
Bit4:
T2ML: Timer 2 Low Byte Clock Select.
This bit selects the clock supplied to Timer 2. If Timer 2 is configured in split 8-bit timer
mode, this bit selects the clock supplied to the lower 8-bit timer.
0: Timer 2 low byte uses the clock defined by the T2XCLK bit in TMR2CN.
1: Timer 2 low byte uses the system clock.
Bit3:
T1M: Timer 1 Clock Select.
This select the clock source supplied to Timer 1. T1M is ignored when C/T1 is set to logic 1.
0: Timer 1 uses the clock defined by the prescale bits, SCA1-SCA0.
1: Timer 1 uses the system clock.
Bit2:
T0M: Timer 0 Clock Select.
This bit selects the clock source supplied to Timer 0. T0M is ignored when C/T0 is set to
logic 1.
0: Counter/Timer 0 uses the clock defined by the prescale bits, SCA1-SCA0.
1: Counter/Timer 0 uses the system clock.
Bits1–0: SCA1–SCA0: Timer 0/1 Prescale Bits.
These bits control the division of the clock supplied to Timer 0 and/or Timer 1 if configured
to use prescaled clock inputs.
SCA1
0
0
1
1

SCA0
0
1
0
1

Prescaled Clock
System clock divided by 12
System clock divided by 4
System clock divided by 48
External clock divided by 8

Note: External clock divided by 8 is synchronized with the
system clock.

Rev. 1.4

215

C8051F320/1
SFR Definition 19.4. TL0: Timer 0 Low Byte
R/W

R/W

Reset Value

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

00000000
0x8A
Bits 7–0: TL0: Timer 0 Low Byte.
The TL0 register is the low byte of the 16-bit Timer 0.

SFR Definition 19.5. TL1: Timer 1 Low Byte
R/W

R/W

Reset Value

00000000
Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

0x8B
Bits 7–0: TL1: Timer 1 Low Byte.
The TL1 register is the low byte of the 16-bit Timer 1.

SFR Definition 19.6. TH0: Timer 0 High Byte
R/W

R/W

Reset Value

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

00000000
0x8C
Bits 7–0: TH0: Timer 0 High Byte.
The TH0 register is the high byte of the 16-bit Timer 0.

SFR Definition 19.7. TH1: Timer 1 High Byte
R/W

R/W

Reset Value

00000000
Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

0x8D
Bits 7–0: TH1: Timer 1 High Byte.
The TH1 register is the high byte of the 16-bit Timer 1.

216

Rev. 1.4

C8051F320/1
19.2. Timer 2
Timer 2 is a 16-bit timer formed by two 8-bit SFRs: TMR2L (low byte) and TMR2H (high byte). Timer 2 may
operate in 16-bit auto-reload mode, (split) 8-bit auto-reload mode, or USB Start-of-Frame (SOF) capture
mode. The Timer 2 operation mode is defined by the T2SPLIT (TMR2CN.3) and T2SOF (TMR2CN.4) bits.
Timer 2 may be clocked by the system clock, the system clock divided by 12, or the external oscillator
source divided by 8. The external clock mode is ideal for real-time clock (RTC) functionality, where the
internal oscillator drives the system clock while Timer 2 (and/or the PCA) is clocked by an external precision oscillator. Note that the external oscillator source divided by 8 is synchronized with the system clock.

19.2.1. 16-bit Timer with Auto-Reload
When T2SPLIT = ‘0’ and T2SOF = ‘0’, Timer 2 operates as a 16-bit timer with auto-reload. Timer 2 can be
clocked by SYSCLK, SYSCLK divided by 12, or the external oscillator clock source divided by 8. As the
16-bit timer register increments and overflows from 0xFFFF to 0x0000, the 16-bit value in the Timer 2
reload registers (TMR2RLH and TMR2RLL) is loaded into the Timer 2 register as shown in Figure 19.4,
and the Timer 2 High Byte Overflow Flag (TMR2CN.7) is set. If Timer 2 interrupts are enabled (if IE.5 is
set), an interrupt will be generated on each Timer 2 overflow. Additionally, if Timer 2 interrupts are enabled
and the TF2LEN bit is set (TMR2CN.5), an interrupt will be generated each time the lower 8 bits (TMR2L)
overflow from 0xFF to 0x00.

CKCON
TTTTTTSS
3 3 2 2 1 0CC
T2XCLK M M M M M M A A
HLHL
1 0

TL2
Overflow

0
TR2

External Clock / 8
SYSCLK

To ADC,
SMBus

To SMBus

TCLK

TMR2L

TMR2H
TMR2CN

SYSCLK / 12

TF2H
TF2L
TF2LEN
T2SOF
T2SPLIT
TR2

Interrupt

T2XCLK

TMR2RLL TMR2RLH
Reload

Figure 19.4. Timer 2 16-Bit Mode Block Diagram

Rev. 1.4

217

C8051F320/1
19.2.2. 8-bit Timers with Auto-Reload
When T2SPLIT = ‘1’ and T2SOF = ‘0’, Timer 2 operates as two 8-bit timers (TMR2H and TMR2L). Both 8bit timers operate in auto-reload mode as shown in Figure 19.5. TMR2RLL holds the reload value for
TMR2L; TMR2RLH holds the reload value for TMR2H. The TR2 bit in TMR2CN handles the run control for
TMR2H. TMR2L is always running when configured for 8-bit Mode.
Each 8-bit timer may be configured to use SYSCLK, SYSCLK divided by 12, or the external oscillator clock
source divided by 8. The Timer 2 Clock Select bits (T2MH and T2ML in CKCON) select either SYSCLK or
the clock defined by the Timer 2 External Clock Select bit (T2XCLK in TMR2CN), as follows:
T2MH
0
0
1

T2XCLK
0
1
X

TMR2H Clock Source
SYSCLK / 12
External Clock / 8
SYSCLK

T2ML
0
0
1

T2XCLK
0
1
X

TMR2L Clock Source
SYSCLK / 12
External Clock / 8
SYSCLK

The TF2H bit is set when TMR2H overflows from 0xFF to 0x00; the TF2L bit is set when TMR2L overflows
from 0xFF to 0x00. When Timer 2 interrupts are enabled (IE.5), an interrupt is generated each time
TMR2H overflows. If Timer 2 interrupts are enabled and TF2LEN (TMR2CN.5) is set, an interrupt is generated each time either TMR2L or TMR2H overflows. When TF2LEN is enabled, software must check the
TF2H and TF2L flags to determine the source of the Timer 2 interrupt. The TF2H and TF2L interrupt flags
are not cleared by hardware and must be manually cleared by software.

CKCON
TTTTTTSS
3 3 2 2 1 0 CC
MMMMMMA A
HLHL
1 0

T2XCLK

SYSCLK / 12

External Clock / 8

TMR2RLH

Reload

To SMBus

0
TCLK
TR2

TMR2H

TMR2RLL
SYSCLK

Reload

TMR2CN

TF2H
TF2L
TF2LEN
T2SOF
T2SPLIT
TR2
T2XCLK

1
TCLK

TMR2L

To ADC,
SMBus

Figure 19.5. Timer 2 8-Bit Mode Block Diagram

218

Rev. 1.4

Interrupt

C8051F320/1
19.2.3. USB Start-of-Frame Capture
When T2SOF = ‘1’, Timer 2 operates in USB Start-of-Frame (SOF) capture mode. When T2SPLIT = ‘0’,
Timer 2 counts up and overflows from 0xFFFF to 0x0000. Each time a USB SOF is received, the contents
of the Timer 2 registers (TMR2H:TMR2L) are latched into the Timer 2 Reload registers
(TMR2RLH:TMR2RLL). A Timer 2 interrupt is generated if enabled. This mode can be used to calibrate the
system clock or external oscillator against the known USB host SOF clock.
TMR2CN
T
F
2
H

T
F
2
L

TTTT
F 2 2R
2SS2
LOP
EF L
N
I
T

SYSCLK / 12

T
2
X
C
L
K

CKCON
TTTTTTSS
3 3 2 2 1 0 CC
MMMMMM A A
HLHL
1 0
To SMBus

TL2
Overflow

0
TR2

External Clock / 8

TCLK

TMR2L

SYSCLK

To ADC,
SMBus

TMR2H

1
USB
Start-of-Frame
(SOF)

Capture

TMR2RLL TMR2RLH

Interrupt

Enable

Figure 19.6. Timer 2 SOF Capture Mode (T2SPLIT = ‘0’)
When T2SPLIT = ‘1’, the Timer 2 registers (TMR2H and TMR2L) act as two 8-bit counters. Each counter
counts up independently and overflows from 0xFF to 0x00. Each time a USB SOF is received, the contents
of the Timer 2 registers are latched into the Timer 2 Reload registers (TMR2RLH and TMR2RLL). A
Timer 2 interrupt is generated if enabled.

TMR2CN
T
F
2
H

T
F
2
L

TTTT
F 2 2R
2 SS2
LOP
EF L
N I
T

T
2
X
C
L
K

SYSCLK / 12

External Clock / 8

CKCON
TTTTTTSS
3 3 2 2 1 0 CC
MMMMMM A A
HLHL
1 0

TMR2RLH

Capture

Enable

Interrupt

0
TCLK

TMR2H

TR2

To SMBus

TMR2RLL

Capture

SYSCLK
USB
Start-of-Frame
(SOF)

1
TCLK

TMR2L

To ADC,
SMBus

Figure 19.7. Timer 2 SOF Capture Mode (T2SPLIT = ‘1’)

Rev. 1.4

219

C8051F320/1
SFR Definition 19.8. TMR2CN: Timer 2 Control
R/W

R/W

Reset Value

TF2H

TF2L

TF2LEN

T2SOF

T2SPLIT

TR2

T2XCLK

00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

(bit addressable)

Bit7:

Bit6:

Bit5:

Bit4:

Bit3:

Bit2:

Bit1:
Bit0:

220

0xC8

TF2H: Timer 2 High Byte Overflow Flag.
Set by hardware when the Timer 2 high byte overflows from 0xFF to 0x00. In 16 bit mode,
this will occur when Timer 2 overflows from 0xFFFF to 0x0000. When the Timer 2 interrupt is
enabled, setting this bit causes the CPU to vector to the Timer 2 interrupt service routine.
TF2H is not automatically cleared by hardware and must be cleared by software.
TF2L: Timer 2 Low Byte Overflow Flag.
Set by hardware when the Timer 2 low byte overflows from 0xFF to 0x00. When this bit is
set, an interrupt will be generated if TF2LEN is set and Timer 2 interrupts are enabled. TF2L
will set when the low byte overflows regardless of the Timer 2 mode. This bit is not automatically cleared by hardware.
TF2LEN: Timer 2 Low Byte Interrupt Enable.
This bit enables/disables Timer 2 Low Byte interrupts. If TF2LEN is set and Timer 2 interrupts are enabled, an interrupt will be generated when the low byte of Timer 2 overflows.
0: Timer 2 Low Byte interrupts disabled.
1: Timer 2 Low Byte interrupts enabled.
T2SOF: Timer 2 Start-Of-Frame Capture Enable
0: SOF Capture disabled.
1: SOF Capture enabled. Each time a USB SOF is received, the contents of the Timer 2 registers (TMR2H and TMR2L) are latched into the Timer 2 reload registers (TMR2RLH and
TMR2RLH), and a Timer 2 interrupt is generated (if enabled).
T2SPLIT: Timer 2 Split Mode Enable.
When this bit is set, Timer 2 operates as two 8-bit timers with auto-reload.
0: Timer 2 operates in 16-bit auto-reload mode.
1: Timer 2 operates as two 8-bit auto-reload timers.
TR2: Timer 2 Run Control.
This bit enables/disables Timer 2. In 8-bit mode, this bit enables/disables TMR2H only;
TMR2L is always enabled in this mode.
0: Timer 2 disabled.
1: Timer 2 enabled.
UNUSED. Read = 0b. Write = don’t care.
T2XCLK: Timer 2 External Clock Select.
This bit selects the external clock source for Timer 2. If Timer 2 is in 8-bit mode, this bit
selects the external oscillator clock source for both timer bytes. However, the Timer 2 Clock
Select bits (T2MH and T2ML in register CKCON) may still be used to select between the
external clock and the system clock for either timer.
0: Timer 2 external clock selection is the system clock divided by 12.
1: Timer 2 external clock selection is the external clock divided by 8. Note that the external
oscillator source divided by 8 is synchronized with the system clock.

Rev. 1.4

C8051F320/1
SFR Definition 19.9. TMR2RLL: Timer 2 Reload Register Low Byte
R/W

R/W

Reset Value

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

00000000
0xCA
Bits 7–0: TMR2RLL: Timer 2 Reload Register Low Byte.
TMR2RLL holds the low byte of the reload value for Timer 2 when operating in auto-reload
mode, or the captured value of the TMR2L register in capture mode.

SFR Definition 19.10. TMR2RLH: Timer 2 Reload Register High Byte
R/W

R/W

Reset Value

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

00000000
0xCB
Bits 7–0: TMR2RLH: Timer 2 Reload Register High Byte.
The TMR2RLH holds the high byte of the reload value for Timer 2 when operating in autoreload mode, or the captured value of the TMR2H register in capture mode.

SFR Definition 19.11. TMR2L: Timer 2 Low Byte
R/W

R/W

Reset Value

00000000
Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

0xCC
Bits 7–0: TMR2L: Timer 2 Low Byte.
In 16-bit mode, the TMR2L register contains the low byte of the 16-bit Timer 2. In 8-bit mode,
TMR2L contains the 8-bit low byte timer value.

SFR Definition 19.12. TMR2H Timer 2 High Byte
R/W

R/W

Reset Value

00000000
Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

0xCD
Bits 7–0: TMR2H: Timer 2 High Byte.
In 16-bit mode, the TMR2H register contains the high byte of the 16-bit Timer 2. In 8-bit
mode, TMR2H contains the 8-bit high byte timer value.

Rev. 1.4

221

C8051F320/1
19.3. Timer 3
Timer 3 is a 16-bit timer formed by two 8-bit SFRs: TMR3L (low byte) and TMR3H (high byte). Timer 3 may
operate in 16-bit auto-reload mode, (split) 8-bit auto-reload mode, or USB Start-of-Frame (SOF) capture
mode. The Timer 3 operation mode is defined by the T3SPLIT (TMR3CN.3) and T3SOF (TMR2CN.4) bits.
Timer 3 may be clocked by the system clock, the system clock divided by 12, or the external oscillator
source divided by 8. The external clock mode is ideal for real-time clock (RTC) functionality, where the
internal oscillator drives the system clock while Timer 3 (and/or the PCA) is clocked by an external precision oscillator. Note that the external oscillator source divided by 8 is synchronized with the system clock.

19.3.1. 16-bit Timer with Auto-Reload
When T3SPLIT (TMR3CN.3) is zero, Timer 3 operates as a 16-bit timer with auto-reload. Timer 3 can be
clocked by SYSCLK, SYSCLK divided by 12, or the external oscillator clock source divided by 8. As the
16-bit timer register increments and overflows from 0xFFFF to 0x0000, the 16-bit value in the Timer 3
reload registers (TMR3RLH and TM3RLL) is loaded into the Timer 3 register as shown in Figure 19.4, and
the Timer 3 High Byte Overflow Flag (TMR3CN.7) is set. If Timer 3 interrupts are enabled, an interrupt will
be generated on each Timer 3 overflow. Additionally, if Timer 3 interrupts are enabled and the TF3LEN bit
is set (TMR3CN.5), an interrupt will be generated each time the lower 8 bits (TMR3L) overflow from 0xFF
to 0x00.

CKCON
T3XCLK

SYSCLK / 12

TTTTTTSS
3 3 2 2 1 0 CC
MMMMMM A A
HLHL
1 0
To ADC

0
0

SYSCLK

TCLK

TMR3L

TMR3H
TMR3CN

TR3

External Clock / 8

TF3H
TF3L
TF3LEN
T3SOF
T3SPLIT
TR3
T3XCLK

TMR3RLL TMR3RLH
Reload

Figure 19.8. Timer 3 16-Bit Mode Block Diagram

222

Rev. 1.4

Interrupt

C8051F320/1
19.3.2. 8-bit Timers with Auto-Reload
When T3SPLIT is set, Timer 3 operates as two 8-bit timers (TMR3H and TMR3L). Both 8-bit timers operate in auto-reload mode as shown in Figure 19.5. TMR3RLL holds the reload value for TMR3L; TMR3RLH
holds the reload value for TMR3H. The TR3 bit in TMR3CN handles the run control for TMR3H. TMR3L is
always running when configured for 8-bit Mode.
Each 8-bit timer may be configured to use SYSCLK, SYSCLK divided by 12, or the external oscillator clock
source divided by 8. The Timer 3 Clock Select bits (T3MH and T3ML in CKCON) select either SYSCLK or
the clock defined by the Timer 3 External Clock Select bit (T3XCLK in TMR3CN), as follows:
T3MH
0
0
1

T3XCLK
0
1
X

TMR3H Clock Source
SYSCLK / 12
External Clock / 8
SYSCLK

T3ML
0
0
1

T3XCLK
0
1
X

TMR3L Clock Source
SYSCLK / 12
External Clock / 8
SYSCLK

The TF3H bit is set when TMR3H overflows from 0xFF to 0x00; the TF3L bit is set when TMR3L overflows
from 0xFF to 0x00. When Timer 3 interrupts are enabled, an interrupt is generated each time TMR3H overflows. If Timer 3 interrupts are enabled and TF3LEN (TMR3CN.5) is set, an interrupt is generated each
time either TMR3L or TMR3H overflows. When TF3LEN is enabled, software must check the TF3H and
TF3L flags to determine the source of the Timer 3 interrupt. The TF3H and TF3L interrupt flags are not
cleared by hardware and must be manually cleared by software.

CKCON
TTTTTTSS
3 3 2 2 1 0 CC
MMMMMM A A
HLHL
1 0

T3XCLK

SYSCLK / 12

TMR3RLH

Reload

To ADC
0

TCLK
TR3

TMR3H

TMR3RLL
SYSCLK

Reload

TMR3CN

External Clock / 8

TF3H
TF3L
TF3LEN
T3SOF
T3SPLIT
TR3

Interrupt

T3XCLK

1
TCLK

TMR3L

Figure 19.9. Timer 3 8-Bit Mode Block Diagram

Rev. 1.4

223

C8051F320/1
19.3.3. USB Start-of-Frame Capture
When T3SOF = ‘1’, Timer 3 operates in USB Start-of-Frame (SOF) capture mode. When T3SPLIT = ‘0’,
Timer 3 counts up and overflows from 0xFFFF to 0x0000. Each time a USB SOF is received, the contents
of the Timer 3 registers (TMR3H:TMR3L) are latched into the Timer 3 Reload registers
(TMR3RLH:TMR3RLL). A Timer 3 interrupt is generated if enabled. This mode can be used to calibrate the
system clock or external oscillator against the known USB host SOF clock.
TMR3CN
T
F
3
H

T
F
3
L

TTTT
F 3 3R
3SS3
LOP
EF L
N I
T

SYSCLK / 12

T
3
X
C
L
K

CKCON
TTTTTTSS
3 3 2 2 1 0CC
MMMMMM A A
HLHL
1 0

0
0
TCLK

TR3

External Clock / 8

TMR3L

TMR3H

To ADC

SYSCLK

USB
Start-of-Frame
(SOF)

Capture

Enable

TMR3RLL TMR3RLH

Interrupt

Figure 19.10. Timer 3 SOF Capture Mode (T3SPLIT = ‘0’)
When T3SPLIT = ‘1’, the Timer 3 registers (TMR3H and TMR3L) act as two 8-bit counters. Each counter
counts up independently and overflows from 0xFF to 0x00. Each time a USB SOF is received, the contents
of the Timer 3 registers are latched into the Timer 3 Reload registers (TMR3RLH and TMR3RLL). A
Timer 3 interrupt is generated if enabled.
TMR3CN
T
F
3
H

T
F
3
L

TTTT
F 3 3R
3SS3
LOP
EF L
N I
T

T
3
X
C
L
K

SYSCLK / 12

External Clock / 8

CKCON
TTTTTTSS
3 3 2 2 1 0CC
MMMMMM A A
HLHL
1 0

TMR3RLH

Capture

Enable

0
TCLK
TR3

TMR3H

To ADC

TMR3RLL

Capture

SYSCLK
USB
Start-of-Frame
(SOF)

1
TCLK

TMR3L

Figure 19.11. Timer 3 SOF Capture Mode (T3SPLIT = ‘1’)

224

Rev. 1.4

Interrupt

C8051F320/1
SFR Definition 19.13. TMR3CN: Timer 3 Control
R/W

R/W

Reset Value

TF3H

TF3L

TF3LEN

T3SOF

T3SPLIT

TR3

T3XCLK

00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

0x91
Bit7:

Bit6:

Bit5:

Bit4:

Bit3:

Bit2:

Bit1:
Bit0:

TF3H: Timer 3 High Byte Overflow Flag.
Set by hardware when the Timer 3 high byte overflows from 0xFF to 0x00. In 16 bit mode,
this will occur when Timer 3 overflows from 0xFFFF to 0x0000. When the Timer 3 interrupt is
enabled, setting this bit causes the CPU to vector to the Timer 3 interrupt service routine.
TF3H is not automatically cleared by hardware and must be cleared by software.
TF3L: Timer 3 Low Byte Overflow Flag.
Set by hardware when the Timer 3 low byte overflows from 0xFF to 0x00. When this bit is
set, an interrupt will be generated if TF3LEN is set and Timer 3 interrupts are enabled. TF3L
will set when the low byte overflows regardless of the Timer 3 mode. This bit is not automatically cleared by hardware.
TF3LEN: Timer 3 Low Byte Interrupt Enable.
This bit enables/disables Timer 3 Low Byte interrupts. If TF3LEN is set and Timer 3 interrupts are enabled, an interrupt will be generated when the low byte of Timer 3 overflows.
This bit should be cleared when operating Timer 3 in 16-bit mode.
0: Timer 3 Low Byte interrupts disabled.
1: Timer 3 Low Byte interrupts enabled.
T3SOF: Timer 3 Start-Of-Frame Capture Enable
0: SOF Capture disabled.
1: SOF Capture enabled. Each time a USB SOF is received, the contents of the Timer 3 registers (TMR3H and TMR3L) are latched into the Timer3 reload registers (TMR3RLH and
TMR3RLH), and a Timer 3 interrupt is generated (if enabled).
T3SPLIT: Timer 3 Split Mode Enable.
When this bit is set, Timer 3 operates as two 8-bit timers with auto-reload.
0: Timer 3 operates in 16-bit auto-reload mode.
1: Timer 3 operates as two 8-bit auto-reload timers.
TR3: Timer 3 Run Control.
This bit enables/disables Timer 3. In 8-bit mode, this bit enables/disables TMR3H only;
TMR3L is always enabled in this mode.
0: Timer 3 disabled.
1: Timer 3 enabled.
UNUSED. Read = 0b. Write = don’t care.
T3XCLK: Timer 3 External Clock Select.
This bit selects the external clock source for Timer 3. If Timer 3 is in 8-bit mode, this bit
selects the external oscillator clock source for both timer bytes. However, the Timer 3 Clock
Select bits (T3MH and T3ML in register CKCON) may still be used to select between the
external clock and the system clock for either timer.
0: Timer 3 external clock selection is the system clock divided by 12.
1: Timer 3 external clock selection is the external clock divided by 8. Note that the external
oscillator source divided by 8 is synchronized with the system clock.

Rev. 1.4

225

C8051F320/1
SFR Definition 19.14. TMR3RLL: Timer 3 Reload Register Low Byte
R/W

R/W

Reset Value

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

00000000
0x92
Bits 7–0: TMR3RLL: Timer 3 Reload Register Low Byte.
TMR3RLL holds the low byte of the reload value for Timer 3 when operating in auto-reload
mode, or the captured value of the TMR3L register when operating in capture mode.

SFR Definition 19.15. TMR3RLH: Timer 3 Reload Register High Byte
R/W

R/W

Reset Value

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

00000000
0x93
Bits 7–0: TMR3RLH: Timer 3 Reload Register High Byte.
The TMR3RLH holds the high byte of the reload value for Timer 3 when operating in autoreload mode, or the captured value of the TMR3H register when operating in capture mode.

SFR Definition 19.16. TMR3L: Timer 3 Low Byte
R/W

R/W

Reset Value

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

00000000
0x94
Bits 7–0: TMR3L: Timer 3 Low Byte.
In 16-bit mode, the TMR3L register contains the low byte of the 16-bit Timer 3. In 8-bit mode,
TMR3L contains the 8-bit low byte timer value.

SFR Definition 19.17. TMR3H Timer 3 High Byte
R/W

R/W

Reset Value

00000000
Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

0x95
Bits 7–0: TMR3H: Timer 3 High Byte.
In 16-bit mode, the TMR3H register contains the high byte of the 16-bit Timer 3. In 8-bit
mode, TMR3H contains the 8-bit high byte timer value.

226

Rev. 1.4

C8051F320/1
20. Programmable Counter Array (PCA0)
The Programmable Counter Array (PCA0) provides enhanced timer functionality while requiring less CPU
intervention than the standard 8051 counter/timers. The PCA consists of a dedicated 16-bit counter/timer
and five 16-bit capture/compare modules. Each capture/compare module has its own associated I/O line
(CEXn) which is routed through the Crossbar to Port I/O when enabled (See Section “14.1. Priority Crossbar Decoder” on page 128 for details on configuring the Crossbar). The counter/timer is driven by a programmable timebase that can select between six sources: system clock, system clock divided by four,
system clock divided by twelve, the external oscillator clock source divided by 8, Timer 0 overflow, or an
external clock signal on the ECI input pin. Each capture/compare module may be configured to operate
independently in one of six modes: Edge-Triggered Capture, Software Timer, High-Speed Output, Frequency Output, 8-Bit PWM, or 16-Bit PWM (each mode is described in Section “20.2. Capture/Compare
Modules” on page 229). The external oscillator clock option is ideal for real-time clock (RTC) functionality,
allowing the PCA to be clocked by a precision external oscillator while the internal oscillator drives the system clock. The PCA is configured and controlled through the system controller's Special Function Registers. The PCA block diagram is shown in Figure 20.1.
Note: The PCA Module 4 may be used as a watchdog timer (WDT), and is enabled in this mode following a system
reset. Access to certain PCA registers is restricted while WDT mode is enabled. See Section 20.3 for details
SYSCLK/12
SYSCLK/4
Timer 0 Overflow
ECI

PCA
CLOCK
MUX

16-Bit Counter/Timer

SYSCLK
External Clock/8

Capture/Compare
Module 0

Capture/Compare
Module 1

Capture/Compare
Module 2

Capture/Compare
Module 3

Capture/Compare
Module 4 / WDT

CEX4

CEX3

CEX2

CEX1

CEX0

ECI

Crossbar

Port I/O

Figure 20.1. PCA Block Diagram

Rev. 1.4

227

C8051F320/1
20.1. PCA Counter/Timer
The 16-bit PCA counter/timer consists of two 8-bit SFRs: PCA0L and PCA0H. PCA0H is the high byte
(MSB) of the 16-bit counter/timer and PCA0L is the low byte (LSB). Reading PCA0L automatically latches
the value of PCA0H into a “snapshot” register; the following PCA0H read accesses this “snapshot” register.
Reading the PCA0L Register first guarantees an accurate reading of the entire 16-bit PCA0 counter.
Reading PCA0H or PCA0L does not disturb the counter operation. The CPS2-CPS0 bits in the PCA0MD
register select the timebase for the counter/timer as shown in Table 20.1.
When the counter/timer overflows from 0xFFFF to 0x0000, the Counter Overflow Flag (CF) in PCA0CN is
set to logic 1 and an interrupt request is generated if CF interrupts are enabled. Setting the ECF bit in
PCA0MD to logic 1 enables the CF flag to generate an interrupt request. The CF bit is not automatically
cleared by hardware when the CPU vectors to the interrupt service routine, and must be cleared by software (Note: PCA0 interrupts must be globally enabled before CF interrupts are recognized. PCA0 interrupts are globally enabled by setting the EA bit (IE.7) and the EPCA0 bit in EIE1 to logic 1). Clearing the
CIDL bit in the PCA0MD register allows the PCA to continue normal operation while the CPU is in Idle
mode.

Table 20.1. PCA Timebase Input Options
CPS2

CPS1

CPS0

Timebase

System clock divided by 12

System clock divided by 4

Timer 0 overflow

High-to-low transitions on ECI (max rate = system clock divided
by 4)

System clock

External oscillator source divided by 8*

Reserved

*Note: External oscillator source divided by 8 is synchronized with the system clock.

IDLE

PCA0MD
CWW
I D D
D T L
L E C
K

C
P
S
2

C
P
S
1

CE
PC
SF
0

PCA0CN
CC
FR

C
C
F
4

C
C
F
3

C
C
F
2

C
C
F
1

C
C
F
0

To SFR Bus
PCA0L
read

Snapshot
Register
SYSCLK/12
SYSCLK/4
Timer 0 Overflow
ECI
SYSCLK
External Clock/8

000
001
010

011

PCA0H

PCA0L

Overflow

To PCA Interrupt System
CF

100
101

To PCA Modules

Figure 20.2. PCA Counter/Timer Block Diagram
228

Rev. 1.4

C8051F320/1
20.2. Capture/Compare Modules
Each module can be configured to operate independently in one of six operation modes: Edge-triggered
Capture, Software Timer, High Speed Output, Frequency Output, 8-Bit Pulse Width Modulator, or 16-Bit
Pulse Width Modulator. Each module has Special Function Registers (SFRs) associated with it in the CIP51 system controller. These registers are used to exchange data with a module and configure the module's
mode of operation.
Table 20.2 summarizes the bit settings in the PCA0CPMn registers used to select the PCA capture/compare module’s operating modes. Setting the ECCFn bit in a PCA0CPMn register enables the module's
CCFn interrupt. Note: PCA0 interrupts must be globally enabled before individual CCFn interrupts are recognized. PCA0 interrupts are globally enabled by setting the EA bit and the EPCA0 bit to logic 1. See
Figure 20.3 for details on the PCA interrupt configuration.

Table 20.2. PCA0CPM Register Settings for PCA Capture/Compare Modules
PWM16 ECOM

CAPP CAPN

MAT

TOG

PWM

ECCF

X
X
X
0
1

1
1
1
1
1

0
0
0
0
0

1
1
X
X
X

0
1
1
0
0

0
0
1
1
1

X
X
X
X
X

Operation Mode
Capture triggered by positive edge
on CEXn
Capture triggered by negative
edge on CEXn
Capture triggered by transition on
CEXn
Software Timer
High Speed Output
Frequency Output
8-Bit Pulse Width Modulator
16-Bit Pulse Width Modulator

Note: X = Don’t Care

Rev. 1.4

229

C8051F320/1
(for n = 0 to 4)

PCA0CPMn
P ECCMT P E
WC A A AOWC
MOPP TGMC
1 MP N n n n F
6 n n n
n
n

PCA0CN
CC
FR

CCCCC
CCCCC
FFFFF
4 3 2 1 0

PCA0MD
C WW
I DD
DT L
LEC
K

CCCE
PPPC
SSSF
2 1 0

PCA Counter/
Timer Overflow

ECCF0
EPCA0

PCA Module 0
(CCF0)

ECCF1

EA
0

Interrupt
Priority
Decoder

PCA Module 1
(CCF1)

ECCF2
0

PCA Module 2
(CCF2)

ECCF3
0

PCA Module 3
(CCF3)

ECCF4

PCA Module 4
(CCF4)

0
1

Figure 20.3. PCA Interrupt Block Diagram
20.2.1. Edge-triggered Capture Mode
In this mode, a valid transition on the CEXn pin causes the PCA to capture the value of the PCA counter/
timer and load it into the corresponding module's 16-bit capture/compare register (PCA0CPLn and
PCA0CPHn). The CAPPn and CAPNn bits in the PCA0CPMn register are used to select the type of transition that triggers the capture: low-to-high transition (positive edge), high-to-low transition (negative edge),
or either transition (positive or negative edge). When a capture occurs, the Capture/Compare Flag (CCFn)
in PCA0CN is set to logic 1 and an interrupt request is generated if CCF interrupts are enabled. The CCFn
bit is not automatically cleared by hardware when the CPU vectors to the interrupt service routine, and
must be cleared by software. If both CAPPn and CAPNn bits are set to logic 1, then the state of the Port
pin associated with CEXn can be read directly to determine whether a rising-edge or falling-edge caused
the capture.

230

Rev. 1.4

C8051F320/1
PCA Interrupt

PCA0CPMn
P ECCMT P E
WC A A AOWC
MOPP TGMC
1 MP N n n n F
6 n n n
n
n
0 0 0 x

Port I/O

Crossbar

CEXn

CCCCC
CCCCC
FFFFF
4 3 2 1 0

(to CCFn)

x 0

PCA0CN
CC
FR

PCA0CPLn

PCA0CPHn

Capture
0
1
PCA
Timebase

PCA0L

PCA0H

Figure 20.4. PCA Capture Mode Diagram
Note: The CEXn input signal must remain high or low for at least 2 system clock cycles to be recognized by the
hardware.

Rev. 1.4

231

C8051F320/1
20.2.2. Software Timer (Compare) Mode
In Software Timer mode, the PCA counter/timer value is compared to the module's 16-bit capture/compare
register (PCA0CPHn and PCA0CPLn). When a match occurs, the Capture/Compare Flag (CCFn) in
PCA0CN is set to logic 1 and an interrupt request is generated if CCF interrupts are enabled. The CCFn bit
is not automatically cleared by hardware when the CPU vectors to the interrupt service routine, and must
be cleared by software. Setting the ECOMn and MATn bits in the PCA0CPMn register enables Software
Timer mode.
Important Note About Capture/Compare Registers: When writing a 16-bit value to the PCA0 Capture/
Compare registers, the low byte should always be written first. Writing to PCA0CPLn clears the ECOMn bit
to ‘0’; writing to PCA0CPHn sets ECOMn to ‘1’.

Write to
PCA0CPLn

0
ENB

Reset
Write to
PCA0CPHn

PCA Interrupt

ENB

PCA0CPMn
P ECCMT P E
WC A A AOWC
MOP P TGMC
1 MP N n n n F
6 n n n
n
n
x

0 0

PCA0CN
PCA0CPLn

CC
FR

PCA0CPHn

0 0 x
Enable

16-bit Comparator

PCA
Timebase

PCA0L

Match

PCA0H

Figure 20.5. PCA Software Timer Mode Diagram

232

CCCCC
CCCCC
FFFFF
4 3 2 1 0

Rev. 1.4

0
1

C8051F320/1
20.2.3. High Speed Output Mode
In High Speed Output mode, a module’s associated CEXn pin is toggled each time a match occurs
between the PCA Counter and the module's 16-bit capture/compare register (PCA0CPHn and
PCA0CPLn) Setting the TOGn, MATn, and ECOMn bits in the PCA0CPMn register enables the HighSpeed Output mode.
Important Note About Capture/Compare Registers: When writing a 16-bit value to the PCA0 Capture/
Compare registers, the low byte should always be written first. Writing to PCA0CPLn clears the ECOMn bit
to ‘0’; writing to PCA0CPHn sets ECOMn to ‘1’.

Write to
PCA0CPLn

0
ENB

Reset
Write to
PCA0CPHn

PCA0CPMn
P ECCMT P E
WC A A A OWC
MOPP TGMC
1 MP N n n n F
6 n n n
n
n

ENB

0 0

0 x
PCA Interrupt

PCA0CN
PCA0CPLn

Enable

CC
FR

PCA0CPHn

16-bit Comparator

Match

CCCCC
CCCCC
FFFFF
4 3 2 1 0

0
1

TOGn

Toggle

PCA
Timebase

0 CEXn
1

PCA0L

Crossbar

Port I/O

PCA0H

Figure 20.6. PCA High Speed Output Mode Diagram

Rev. 1.4

233

C8051F320/1
20.2.4. Frequency Output Mode
Frequency Output Mode produces a programmable-frequency square wave on the module’s associated
CEXn pin. The capture/compare module high byte holds the number of PCA clocks to count before the output is toggled. The frequency of the square wave is then defined by Equation 20.1.

Equation 20.1. Square Wave Frequency Output
F PCA
F CEXn = ----------------------------------------2 × PCA0CPHn
Note: A value of 0x00 in the PCA0CPHn register is equal to 256 for this equation.

Where FPCA is the frequency of the clock selected by the CPS2-0 bits in the PCA mode register, PCA0MD.
The lower byte of the capture/compare module is compared to the PCA counter low byte; on a match,
CEXn is toggled and the offset held in the high byte is added to the matched value in PCA0CPLn. Frequency Output Mode is enabled by setting the ECOMn, TOGn, and PWMn bits in the PCA0CPMn register.

Write to
PCA0CPLn

0
ENB

Reset

PCA0CPMn
Write to
PCA0CPHn

ENB

P ECCMT P E
WC A A AOWC
MOPP TGMC
1 MP N n n n F
6 nnn
n
n
x

0 0 0

PCA0CPLn

8-bit Adder

PCA0CPHn

Adder
Enable

TOGn

Toggle

x
Enable

PCA Timebase

8-bit
Comparator

match

0 CEXn
1

PCA0L

Figure 20.7. PCA Frequency Output Mode

234

Rev. 1.4

Crossbar

Port I/O

C8051F320/1
20.2.5. 8-Bit Pulse Width Modulator Mode
Each module can be used independently to generate a pulse width modulated (PWM) output on its associated CEXn pin. The frequency of the output is dependent on the timebase for the PCA counter/timer. The
duty cycle of the PWM output signal is varied using the module's PCA0CPLn capture/compare register.
When the value in the low byte of the PCA counter/timer (PCA0L) is equal to the value in PCA0CPLn, the
output on the CEXn pin will be set. When the count value in PCA0L overflows, the CEXn output will be
reset (see Figure 20.8). Also, when the counter/timer low byte (PCA0L) overflows from 0xFF to 0x00,
PCA0CPLn is reloaded automatically with the value stored in the module’s capture/compare high byte
(PCA0CPHn) without software intervention. Setting the ECOMn and PWMn bits in the PCA0CPMn register
enables 8-Bit Pulse Width Modulator mode. The duty cycle for 8-Bit PWM Mode is given by Equation 20.2.
Important Note About Capture/Compare Registers: When writing a 16-bit value to the PCA0 Capture/
Compare registers, the low byte should always be written first. Writing to PCA0CPLn clears the ECOMn bit
to ‘0’; writing to PCA0CPHn sets ECOMn to ‘1’.

Equation 20.2. 8-Bit PWM Duty Cycle
( 256 – PCA0CPHn )
DutyCycle = --------------------------------------------------256
Using Equation 20.2, the largest duty cycle is 100% (PCA0CPHn = 0), and the smallest duty cycle is
0.39% (PCA0CPHn = 0xFF). A 0% duty cycle may be generated by clearing the ECOMn bit to ‘0’.

Write to
PCA0CPLn

PCA0CPHn

ENB

Reset
Write to
PCA0CPHn

ENB

PCA0CPMn
P ECCMT P E
WC A A AOWC
MOPP TGMC
1 MP N n n n F
6 n n n
n
n
0

0 0 x 0

PCA0CPLn

x
Enable

8-bit
Comparator

match

R
PCA Timebase

SET

CLR

CEXn

Crossbar

Port I/O

PCA0L
Overflow

Figure 20.8. PCA 8-Bit PWM Mode Diagram

Rev. 1.4

235

C8051F320/1
20.2.6. 16-Bit Pulse Width Modulator Mode
A PCA module may also be operated in 16-Bit PWM mode. In this mode, the 16-bit capture/compare module defines the number of PCA clocks for the low time of the PWM signal. When the PCA counter matches
the module contents, the output on CEXn is asserted high; when the counter overflows, CEXn is asserted
low. To output a varying duty cycle, new value writes should be synchronized with PCA CCFn match interrupts. 16-Bit PWM Mode is enabled by setting the ECOMn, PWMn, and PWM16n bits in the PCA0CPMn
register. For a varying duty cycle, match interrupts should be enabled (ECCFn = 1 AND MATn = 1) to help
synchronize the capture/compare register writes. The duty cycle for 16-Bit PWM Mode is given by
Equation 20.3.
Important Note About Capture/Compare Registers: When writing a 16-bit value to the PCA0 Capture/
Compare registers, the low byte should always be written first. Writing to PCA0CPLn clears the ECOMn bit
to ‘0’; writing to PCA0CPHn sets ECOMn to ‘1’.

Equation 20.3. 16-Bit PWM Duty Cycle
( 65536 – PCA0CPn )
DutyCycle = ----------------------------------------------------65536
Using Equation 20.3, the largest duty cycle is 100% (PCA0CPn = 0), and the smallest duty cycle is
0.0015% (PCA0CPn = 0xFFFF). A 0% duty cycle may be generated by clearing the ECOMn bit to ‘0’.

Write to
PCA0CPLn

0
ENB

Reset
Write to
PCA0CPHn

ENB

PCA0CPMn
P ECCMT P E
WC A A AOWC
MOPP TGMC
1 MP N n n n F
6 n n n
n
n
1

0 0 x 0

PCA0CPHn

PCA0CPLn

x
Enable

16-bit Comparator

match

R
PCA Timebase

PCA0H

SET

CLR

CEXn

Crossbar

Port I/O

PCA0L
Overflow

Figure 20.9. PCA 16-Bit PWM Mode
20.3. Watchdog Timer Mode
A programmable watchdog timer (WDT) function is available through the PCA Module 4. The WDT is used
to generate a reset if the time between writes to the WDT update register (PCA0CPH4) exceed a specified
limit. The WDT can be configured and enabled/disabled as needed by software.
With the WDTE and/or WDLCK bits set to ‘1’ in the PCA0MD register, Module 4 operates as a watchdog
timer (WDT). The Module 4 high byte is compared to the PCA counter high byte; the Module 4 low byte
holds the offset to be used when WDT updates are performed. The Watchdog Timer is enabled on
reset. Writes to some PCA registers are restricted while the Watchdog Timer is enabled.

236

Rev. 1.4

C8051F320/1
20.3.1. Watchdog Timer Operation
While the WDT is enabled:
•
•
•
•
•
•

PCA counter is forced on.
Writes to PCA0L and PCA0H are not allowed.
PCA clock source bits (CPS2-CPS0) are frozen.
PCA Idle control bit (CIDL) is frozen.
Module 4 is forced into Watchdog Timer mode.
Writes to the Module 4 mode register (PCA0CPM4) are disabled.

While the WDT is enabled, writes to the CR bit will not change the PCA counter state; the counter will run
until the WDT is disabled. The PCA counter run control (CR) will read zero if the WDT is enabled but user
software has not enabled the PCA counter. If a match occurs between PCA0CPH4 and PCA0H while the
WDT is enabled, a reset will be generated. To prevent a WDT reset, the WDT may be updated with a write
of any value to PCA0CPH4. Upon a PCA0CPH4 write, PCA0H plus the offset held in PCA0CPL4 is loaded
into PCA0CPH4 (See Figure 20.10).
PCA0MD
CWW
I DD
DT L
L E C
K

CCCE
PPPC
SSSF
2 1 0

PCA0CPH4

Enable

PCA0CPL4

Write to
PCA0CPH4

8-bit Adder

8-bit
Comparator

PCA0H

Match

Reset

PCA0L Overflow

Adder
Enable

Figure 20.10. PCA Module 4 with Watchdog Timer Enabled

Rev. 1.4

237

C8051F320/1
Note that the 8-bit offset held in PCA0CPH4 is compared to the upper byte of the 16-bit PCA counter. This
offset value is the number of PCA0L overflows before a reset. Up to 256 PCA clocks may pass before the
first PCA0L overflow occurs, depending on the value of the PCA0L when the update is performed. The
total offset is then given (in PCA clocks) by Equation 20.4, where PCA0L is the value of the PCA0L register
at the time of the update.

Equation 20.4. Watchdog Timer Offset in PCA Clocks
Offset = ( 256 × PCA0CPL4 ) + ( 256 – PCA0L )
The WDT reset is generated when PCA0L overflows while there is a match between PCA0CPH4 and
PCA0H. Software may force a WDT reset by writing a ‘1’ to the CCF4 flag (PCA0CN.4) while the WDT is
enabled.

20.3.2. Watchdog Timer Usage
To configure the WDT, perform the following tasks:
1.
2.
3.
4.

Disable the WDT by writing a ‘0’ to the WDTE bit.
Select the desired PCA clock source (with the CPS2-CPS0 bits).
Load PCA0CPL4 with the desired WDT update offset value.
Configure the PCA Idle mode (set CIDL if the WDT should be suspended while the CPU is in
Idle mode).
5. Enable the WDT by setting the WDTE bit to ‘1’.
6. (optional) Lock the WDT (prevent WDT disable until the next system reset) by setting the
WDLCK bit to ‘1’.
7. Write a value to PCA0CPH4 to reload the WDT.

The PCA clock source and Idle mode select cannot be changed while the WDT is enabled. The watchdog
timer is enabled by setting the WDTE or WDLCK bits in the PCA0MD register. When WDLCK is set, the
WDT cannot be disabled until the next system reset. If WDLCK is not set, the WDT is disabled by clearing
the WDTE bit.
The WDT is enabled following any reset. The PCA0 counter clock defaults to the system clock divided by
12, PCA0L defaults to 0x00, and PCA0CPL4 defaults to 0x00. Using Equation 20.4, this results in a WDT
timeout interval of 256 PCA clock cycles (3072 system clock cycles). Table 20.3 lists some example timeout intervals for typical system clocks.

238

Rev. 1.4

C8051F320/1
Table 20.3. Watchdog Timer Timeout Intervals1
System Clock (Hz)

PCA0CPL4

Timeout Interval (ms)

24,000,000

255

32.8

24,000,000

128

16.5

24,000,000

4.2

12,000,000

255

65.5

12,000,000

128

33.0

12,000,000

8.4

4,000,000

255

196.6

4,000,000

128

99.1

4,000,000

25.3

1,500,0002

255

524.3

1,500,000

128

264.2

1,500,0002

67.6

32,768

255

24,000

32,768

128

12,093.75

32,768

3,093.75

Notes:
1. Assumes SYSCLK / 12 as the PCA clock source, and a PCA0L value
of 0x00 at the update time.
2. Internal oscillator reset frequency.

20.4. Register Descriptions for PCA
Following are detailed descriptions of the special function registers related to the operation of the PCA.

Rev. 1.4

239

C8051F320/1
SFR Definition 20.1. PCA0CN: PCA Control
R/W

R/W

Reset Value

CCF4

CCF3

CCF2

CCF1

CCF0

00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

(bit addressable)

Bit7:

Bit6:

Bit5:
Bit4:

Bit3:

Bit2:

Bit1:

Bit0:

240

0xD8

CF: PCA Counter/Timer Overflow Flag.
Set by hardware when the PCA Counter/Timer overflows from 0xFFFF to 0x0000. When the
Counter/Timer Overflow (CF) interrupt is enabled, setting this bit causes the CPU to vector
to the PCA interrupt service routine. This bit is not automatically cleared by hardware and
must be cleared by software.
CR: PCA Counter/Timer Run Control.
This bit enables/disables the PCA Counter/Timer.
0: PCA Counter/Timer disabled.
1: PCA Counter/Timer enabled.
UNUSED. Read = 0b, Write = don't care.
CCF4: PCA Module 4 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF4 interrupt is
enabled, setting this bit causes the CPU to vector to the PCA interrupt service routine. This
bit is not automatically cleared by hardware and must be cleared by software.
CCF3: PCA Module 3 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF3 interrupt is
enabled, setting this bit causes the CPU to vector to the PCA interrupt service routine. This
bit is not automatically cleared by hardware and must be cleared by software.
CCF2: PCA Module 2 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF2 interrupt is
enabled, setting this bit causes the CPU to vector to the PCA interrupt service routine. This
bit is not automatically cleared by hardware and must be cleared by software.
CCF1: PCA Module 1 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF1 interrupt is
enabled, setting this bit causes the CPU to vector to the PCA interrupt service routine. This
bit is not automatically cleared by hardware and must be cleared by software.
CCF0: PCA Module 0 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF0 interrupt is
enabled, setting this bit causes the CPU to vector to the PCA interrupt service routine. This
bit is not automatically cleared by hardware and must be cleared by software.

Rev. 1.4

C8051F320/1
SFR Definition 20.2. PCA0MD: PCA Mode
R/W

R/W

CIDL

WDTE

Bit7

Bit6

Reset Value

WDLCK

CPS2

CPS1

CPS0

ECF

01000000

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

0xD9
Bit7:

CIDL: PCA Counter/Timer Idle Control.
Specifies PCA behavior when CPU is in Idle Mode.
0: PCA continues to function normally while the system controller is in Idle Mode.
1: PCA operation is suspended while the system controller is in Idle Mode.
Bit6:
WDTE: Watchdog Timer Enable
If this bit is set, PCA Module 4 is used as the watchdog timer.
0: Watchdog Timer disabled.
1: PCA Module 4 enabled as Watchdog Timer.
Bit5:
WDLCK: Watchdog Timer Lock
This bit enables and locks the Watchdog Timer. When WDLCK is set to ‘1’, the Watchdog
Timer may not be disabled until the next system reset.
0: Watchdog Timer unlocked.
1: Watchdog Timer enabled and locked.
Bit4:
UNUSED. Read = 0b, Write = don't care.
Bits3–1: CPS2–CPS0: PCA Counter/Timer Pulse Select.
These bits select the timebase source for the PCA counter.
CPS2
0
0
0

CPS1
0
0
1

CPS0
0
1
0

1
1
1
1

0
0
1
1

0
1
0
1

Timebase
System clock divided by 12
System clock divided by 4
Timer 0 overflow
High-to-low transitions on ECI (max rate = system clock
divided by 4)
System clock
External clock divided by 8*
Reserved
Reserved

*Note: External oscillator source divided by 8 is synchronized with the system clock.

Bit0:

ECF: PCA Counter/Timer Overflow Interrupt Enable.
This bit sets the masking of the PCA Counter/Timer Overflow (CF) interrupt.
0: Disable the CF interrupt.
1: Enable a PCA Counter/Timer Overflow interrupt request when CF (PCA0CN.7) is set.

Note: When the WDTE bit is set to ‘1’, the PCA0MD register cannot be modified. To change the
contents of the PCA0MD register, the Watchdog Timer must first be disabled.

Rev. 1.4

241

C8051F320/1
SFR Definition 20.3. PCA0CPMn: PCA Capture/Compare Mode
R/W

R/W

Reset Value

PWM16n

ECOMn

CAPPn

CAPNn

MATn

TOGn

PWMn

EECFn

00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

0xDA, 0xDB, 0xDC, 0xDD, 0xDE

PCA0CPMn Address:

Bit7:

Bit6:

Bit5:

Bit4:

Bit3:

Bit2:

Bit1:

Bit0:

242

PCA0CPM0 = 0xDA (n = 0), PCA0CPM1 = 0xDB (n = 1),
PCA0CPM2 = 0xDC (n = 2), PCA0CPM3 = 0xDD (n = 3),
PCA0CPM4 = 0xDE (n = 4)

PWM16n: 16-bit Pulse Width Modulation Enable.
This bit selects 16-bit mode when Pulse Width Modulation mode is enabled (PWMn = 1).
0: 8-bit PWM selected.
1: 16-bit PWM selected.
ECOMn: Comparator Function Enable.
This bit enables/disables the comparator function for PCA module n.
0: Disabled.
1: Enabled.
CAPPn: Capture Positive Function Enable.
This bit enables/disables the positive edge capture for PCA module n.
0: Disabled.
1: Enabled.
CAPNn: Capture Negative Function Enable.
This bit enables/disables the negative edge capture for PCA module n.
0: Disabled.
1: Enabled.
MATn: Match Function Enable.
This bit enables/disables the match function for PCA module n. When enabled, matches of the
PCA counter with a module's capture/compare register cause the CCFn bit in PCA0MD register
to be set to logic 1.
0: Disabled.
1: Enabled.
TOGn: Toggle Function Enable.
This bit enables/disables the toggle function for PCA module n. When enabled, matches of the
PCA counter with a module's capture/compare register cause the logic level on the CEXn pin to
toggle. If the PWMn bit is also set to logic 1, the module operates in Frequency Output Mode.
0: Disabled.
1: Enabled.
PWMn: Pulse Width Modulation Mode Enable.
This bit enables/disables the PWM function for PCA module n. When enabled, a pulse width
modulated signal is output on the CEXn pin. 8-bit PWM is used if PWM16n is cleared; 16-bit
mode is used if PWM16n is set to logic 1. If the TOGn bit is also set, the module operates in Frequency Output Mode.
0: Disabled.
1: Enabled.
ECCFn: Capture/Compare Flag Interrupt Enable.
This bit sets the masking of the Capture/Compare Flag (CCFn) interrupt.
0: Disable CCFn interrupts.
1: Enable a Capture/Compare Flag interrupt request when CCFn is set.

Rev. 1.4

C8051F320/1
SFR Definition 20.4. PCA0L: PCA Counter/Timer Low Byte
R/W

R/W

Reset Value

00000000
Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

0xF9
Bits 7–0: PCA0L: PCA Counter/Timer Low Byte.
The PCA0L register holds the low byte (LSB) of the 16-bit PCA Counter/Timer.

SFR Definition 20.5. PCA0H: PCA Counter/Timer High Byte
R/W

R/W

Reset Value

00000000
Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

0xFA
Bits 7–0: PCA0H: PCA Counter/Timer High Byte.
The PCA0H register holds the high byte (MSB) of the 16-bit PCA Counter/Timer.

SFR Definition 20.6. PCA0CPLn: PCA Capture Module Low Byte
R/W

R/W

Reset Value

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

00000000
0xFB, 0xE9, 0xEB, 0xED, 0xFD

PCA0CPLn Address:

PCA0CPL0 = 0xFB (n = 0), PCA0CPL1 = 0xE9 (n = 1),
PCA0CPL2 = 0xEB (n = 2), PCA0CPL3 = 0xED (n = 3),
PCA0CPL4 = 0xFD (n = 4)

Bits7–0: PCA0CPLn: PCA Capture Module Low Byte.
The PCA0CPLn register holds the low byte (LSB) of the 16-bit capture module n.

Rev. 1.4

243

C8051F320/1
SFR Definition 20.7. PCA0CPHn: PCA Capture Module High Byte
R/W

R/W

Reset Value

00000000
Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

0xFC, 0xEA, 0xEC,0xEE, 0xFE

PCA0CPHn Address:

PCA0CPH0 = 0xFC (n = 0), PCA0CPH1 = 0xEA (n = 1),
PCA0CPH2 = 0xEC (n = 2), PCA0CPH3 = 0xEE (n = 3),
PCA0CPH4 = 0xFE (n = 4)

Bits7–0: PCA0CPHn: PCA Capture Module High Byte.
The PCA0CPHn register holds the high byte (MSB) of the 16-bit capture module n.

244

Rev. 1.4

C8051F320/1
21. C2 Interface
C8051F320/1 devices include an on-chip Silicon Labs 2-Wire (C2) debug interface to allow Flash programming and in-system debugging with the production part installed in the end application. The C2 interface
uses a clock signal (C2CK) and a bi-directional C2 data signal (C2D) to transfer information between the
device and a host system. See the C2 Interface Specification for details on the C2 protocol.

21.1. C2 Interface Registers
The following describes the C2 registers necessary to perform Flash programming through the C2 interface. All C2 registers are accessed through the C2 interface as described in the C2 Interface Specification.

C2 Register Definition 21.1. C2ADD: C2 Address
Reset Value

00000000
Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

Bits7–0: The C2ADD register is accessed via the C2 interface to select the target Data register for
C2 Data Read and Data Write commands.
Address
0x00
0x01

Description
Selects the Device ID register for Data Read instructions
Selects the Revision ID register for Data Read instructions
Selects the C2 Flash Programming Control register for Data
Read/Write instructions
Selects the C2 Flash Programming Data register for Data
Read/Write instructions

0x02
0xB4

C2 Register Definition 21.2. C2 Device ID
Reset Value

00001001
Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

This read-only register returns the 8-bit device ID: 0x09 (C8051F320/1).

Rev. 1.4

245

C8051F320/1
C2 Register Definition 21.3. REVID: C2 Revision ID
Reset Value

00000000
Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

This read-only register returns the 8-bit revision ID: 0x01 (Revision B).

C2 Register Definition 21.4. FPCTL: C2 Flash Programming Control
Reset Value

00000000
Bit7

Bits7–0

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

FPCTL: Flash Programming Control Register.
This register is used to enable Flash programming via the C2 interface. To enable C2 Flash
programming, the following codes must be written in order: 0x02, 0x01. Note that once C2
Flash programming is enabled, a system reset must be issued to resume normal operation.

C2 Register Definition 21.5. FPDAT: C2 Flash Programming Data
Reset Value

00000000
Bit7

Bits7-0:

Bit6

Bit4

Bit3

Bit2

Bit1

Bit0

FPDAT: C2 Flash Programming Data Register.
This register is used to pass Flash commands, addresses, and data during C2 Flash
accesses. Valid commands are listed below.
Code
0x06
0x07
0x08
0x03

246

Bit5

Command
Flash Block Read
Flash Block Write
Flash Page Erase
Device Erase

Rev. 1.4

C8051F320/1
21.2. C2 Pin Sharing
The C2 protocol allows the C2 pins to be shared with user functions so that in-system debugging and
Flash programming functions may be performed. This is possible because C2 communication is typically
performed when the device is in the halt state, where all on-chip peripherals and user software are stalled.
In this halted state, the C2 interface can safely ‘borrow’ the C2CK (/RST) and C2D (P3.0) pins. In most
applications, external resistors are required to isolate C2 interface traffic from the user application. A typical isolation configuration is shown in Figure 21.1.

C8051Fxxx

/Reset (a)

C2CK

Input (b)

C2D

Output (c)

C2 Interface Master

Figure 21.1. Typical C2 Pin Sharing
The configuration in Figure 21.1 assumes the following:
1. The user input (b) cannot change state while the target device is halted.
2. The /RST pin on the target device is used as an input only.
Additional resistors may be necessary depending on the specific application.

Rev. 1.4

247

C8051F320/1
DOCUMENT CHANGE LIST
Revision 1.1 to Revision 1.2
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•

•
•
•
•
•
•
•

Updated document with RoHS compliant information.
Updated Table 3.1, “Global Electrical Characteristics,” on page 28.
Updated package drawings in Section “4. Pinout and Package Definitions” on page 30.
Updated Figure “5.4 10-Bit ADC Track and Conversion Example Timing” on page 44. ADC takes 14
SAR clocks to convert a sample.
Added Max and Min values for Offset and Full Scale Error in Table 5.1, “ADC0 Electrical Characteristics,” on page 54.
Updated Bias Generator specifications in Table 6.1, “Voltage Reference Electrical Characteristics,” on
page 56.
Added Max values for Comparator supply current in Table 7.1, “Comparator Electrical Characteristics,”
on page 66.
Updated Section “8. Voltage Regulator (REG0)” with decoupling and bypass capacitor requirements.
Updated Table 8.1, “Voltage Regulator Electrical Specifications,” on page 68.
Updated how to clear the EA bit in Section “9.3. Interrupt Handler”.
Added Table 11.2, “Flash Security Summary,” on page 109.
Added Section “11.4. Flash Write and Erase Guidelines” on page 110.
Updated Internal Oscillator Suspend Mode behavior in Section “13.1.2. Internal Oscillator Suspend
Mode”.
Updated OSCICN reset value in SFR Definition 13.1. “OSCICN: Internal Oscillator Control” on
page 118.
Corrected maximum SMBus transfer speed in Section “16. SMBus”.
Updated Table 16.4, “SMBus Status Decoding,” on page 184.
- Slave Transmitter (0101 0XX)
- Slave Receiver (0001 00X)
Replaced Tables 17.1 though 17.6 with a single table (Table 17.1, “Timer Settings for Standard Baud
Rates Using The Internal Oscillator,” on page 194).
Updated WCOL bit description in SFR Definition 18.2. “SPI0CN: SPI0 Control” on page 204.
Updated references to IT01CF in SFR Definition 19.1. TCON: Timer Control and SFR
Definition 19.2. TMOD: Timer Mode.
Added Step 7 to Watchdog Timer Usage in Section “20.3.2. Watchdog Timer Usage”.
Changed sample system clock frequencies in Table 20.3, “Watchdog Timer Timeout Intervals1,” on
page 239.
Removed references to boundary scan in Section “21. C2 Interface”.
Various formatting fixes.

Revision 1.2 to Revision 1.3
•
•
•

Removed references to "Boundary Scan" in the C2 chapter.
Updated package drawings to reflect JEDEC-standard nomenclature and supplier variations.
Relaxed maximum VBUS Detection Input Threshold specification in Table 5.1 from 4.0 to 2.9 V.

Revision 1.3 to Revision 1.4
•
•
•
•

248

Updated Table 8.1 on page 68.
Updated Table 15.2 on page 144.
Removed USB Register Definition INMAX.
Removed USB Register Definition OUTMAX.

Rev. 1.4

C8051F320/1
NOTES:

Rev. 1.4

249

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thereof, "the world’s most energy friendly microcontrollers", Ember®, EZLink®, EZMac®, EZRadio®, EZRadioPRO®, DSPLL®, ISOmodem ®, Precision32®, ProSLIC®, SiPHY®,
USBXpress® and others are trademarks or registered trademarks of Silicon Laboratories Inc. ARM, CORTEX, Cortex-M3 and THUMB are trademarks or registered trademarks of
ARM Holdings. Keil is a registered trademark of ARM Limited. All other products or brand names mentioned herein are trademarks of their respective holders.

Silicon Laboratories Inc.
400 West Cesar Chavez
Austin, TX 78701
USA

http://www.silabs.com

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