ARMv6 M Architecture Reference Manual DDI0419C Arm V6m

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ARMv6-M Architecture
Reference Manual

ARMv6-M Architecture Reference Manual
Copyright © 2007-2008, 2010 ARM Limited. All rights reserved.
Release Information
The following changes have been made to this document.
Change History
Date

Issue

Confidentiality

Change

March 2007

Non-Confidential

First release

September 2008

Non-Confidential, Restricted Access

Additions to the System Control Block, power management support,
corrections to errata and clarifications

September 2010

Non-confidential

Additions to describe the Unprivileged/Privileged Extension and the
Protected Memory System Architecture (PMSA) Extension. Also extensive
clarification and reorganization.

Proprietary Notice
This ARM Architecture Reference Manual is protected by copyright and the practice or implementation of the
information herein may be protected by one or more patents or pending applications. No part of this ARM Architecture
Reference Manual may be reproduced in any form by any means without the express prior written permission of ARM.
No license, express or implied, by estoppel or otherwise to any intellectual property rights is granted by this ARM
Architecture Reference Manual.
Your access to the information in this ARM Architecture Reference Manual is conditional upon your acceptance that you
will not use or permit others to use the information for the purposes of determining whether implementations of the ARM
architecture infringe any third party patents.
This ARM Architecture Reference Manual is provided “as is”. ARM makes no representations or warranties, either
express or implied, included but not limited to, warranties of merchantability, fitness for a particular purpose, or
non-infringement, that the content of this ARM Architecture Reference Manual is suitable for any particular purpose or
that any practice or implementation of the contents of the ARM Architecture Reference Manual will not infringe any third
party patents, copyrights, trade secrets, or other rights.
This ARM Architecture Reference Manual may include technical inaccuracies or typographical errors.
To the extent not prohibited by law, in no event will ARM be liable for any damages, including without limitation any
direct loss, lost revenue, lost profits or data, special, indirect, consequential, incidental or punitive damages, however
caused and regardless of the theory of liability, arising out of or related to any furnishing, practicing, modifying or any
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Words and logos marked with ® or TM are registered trademarks or trademarks of ARM Limited, except as otherwise
stated below in this proprietary notice. Other brands and names mentioned herein may be the trademarks of their
respective owners.
Copyright © 2007-2008, 2010 ARM Limited
110 Fulbourn Road Cambridge, England CB1 9NJ
Restricted Rights Legend: Use, duplication or disclosure by the United States Government is subject to the restrictions
set forth in DFARS 252.227-7013 (c)(1)(ii) and FAR 52.227-19.

ARM DDI 0419C
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This document is Non-Confidential but any disclosure by you is subject to you providing notice to and the
acceptance by the recipient of, the conditions set out above.

In this document, where the term ARM is used to refer to the company it means “ARM or any of its subsidiaries as
appropriate”.

Note
The term ARM is also used to refer to versions of the ARM architecture, for example ARMv6 refers to version 6 of the
ARM architecture. The context makes it clear when the term is used in this way.

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iii

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Contents
ARMv6-M Architecture Reference Manual

Preface
About this manual ............................................................................... xvi
Using this manual .............................................................................. xvii
Conventions ........................................................................................ xix
Additional reading ................................................................................ xx
Feedback ............................................................................................ xxi

Part A
Chapter A1

Application Level Architecture
Introduction
A1.1
A1.2

Chapter A2

Application Level Programmers’ Model
A2.1
A2.2
A2.3
A2.4
A2.5

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About the ARM architecture profiles .............................................. A1-26
Privileged and unprivileged execution ............................................ A1-27

About the application level programmers’ model ...........................
ARM processor data types and arithmetic .....................................
Registers and execution state ........................................................
Exceptions, faults and interrupts ....................................................
Coprocessor support ......................................................................

A2-30
A2-31
A2-36
A2-39
A2-40

Contents

Chapter A3

ARM Architecture Memory Model
A3.1
A3.2
A3.3
A3.4
A3.5
A3.6
A3.7
A3.8

Chapter A4

Chapter B1

Thumb instruction set encoding ..................................................... A5-82
16-bit Thumb instruction encoding ................................................. A5-84
32-bit Thumb instruction encoding ................................................. A5-91

Format of instruction descriptions .................................................. A6-94
Standard assembler syntax fields .................................................. A6-98
Conditional execution ..................................................................... A6-99
Shifts applied to a register ........................................................... A6-101
Memory accesses ........................................................................ A6-103
Hint Instructions ........................................................................... A6-104
Alphabetical list of ARMv6-M Thumb instructions ........................ A6-105

System Level Architecture
System Level Programmers’ Model
B1.1
B1.2
B1.3
B1.4
B1.5

A4-66
A4-68
A4-70
A4-71
A4-74
A4-75
A4-77
A4-78
A4-79

Thumb Instruction Details
A6.1
A6.2
A6.3
A6.4
A6.5
A6.6
A6.7

Part B

About the instruction set ................................................................
Unified Assembler Language .........................................................
Branch instructions ........................................................................
Data-processing instructions ..........................................................
Status register access instructions ................................................
Load and store instructions ............................................................
Load Multiple and Store Multiple instructions ................................
Miscellaneous instructions .............................................................
Exception-generating instructions ..................................................

The Thumb Instruction Set Encoding
A5.1
A5.2
A5.3

Chapter A6

A3-42
A3-43
A3-44
A3-47
A3-48
A3-56
A3-58
A3-63

The ARMv6-M Instruction Set
A4.1
A4.2
A4.3
A4.4
A4.5
A4.6
A4.7
A4.8
A4.9

Chapter A5

Address space ...............................................................................
Alignment support ..........................................................................
Endian support ...............................................................................
Synchronization and semaphores ..................................................
Memory types and attributes and the memory order model ..........
Access rights ..................................................................................
Memory access order ....................................................................
Caches and memory hierarchy ......................................................

Introduction to the system level ...................................................
About the ARMv6-M memory mapped architecture .....................
Overview of system level terminology and operation ...................
Registers ......................................................................................
ARMv6-M exception model ..........................................................

B1-204
B1-205
B1-206
B1-211
B1-218

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Contents

Chapter B2

System Memory Model
B2.1
B2.2
B2.3
B2.4
B2.5

Chapter B3

Chapter C1

Appendix A

C1-316
C1-318
C1-320
C1-323
C1-324
C1-328
C1-341
C1-351

ARMv6-M CoreSight Infrastructure IDs
CoreSight infrastructure IDs for an ARMv6-M implementation .................
AppxA-360

Deprecated and Obsolete Features
Deprecated features of the ARMv6-M architecture ................ AppxB-364
Obsolete features of the ARMv6-M architecture .................... AppxB-365

ARMv7-M Differences
C.1
C.2
C.3

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Introduction to ARMv6-M debug ..................................................
The Debug Access Port ...............................................................
Overview of the ARMv6-M debug features ..................................
Debug and reset ..........................................................................
Debug event behavior ..................................................................
Debug register support in the SCS ..............................................
The Data Watchpoint and Trace unit ...........................................
Breakpoint Unit ............................................................................

Appendices

B.1
B.2

Appendix C

About the ARMv6-M system instructions ..................................... B4-304
ARMv6-M system instruction descriptions ................................... B4-305

ARMv6-M Debug

A.1

Appendix B

B3-258
B3-262
B3-275
B3-281
B3-289

Debug Architecture
C1.1
C1.2
C1.3
C1.4
C1.5
C1.6
C1.7
C1.8

Part D

The system address map .............................................................
System Control Space (SCS) .......................................................
The system timer, SysTick ...........................................................
Nested Vectored Interrupt Controller, NVIC .................................
Protected Memory System Architecture, PMSAv6 .......................

ARMv6-M System Instructions
B4.1
B4.2

Part C

B2-246
B2-247
B2-251
B2-254
B2-255

System Address Map
B3.1
B3.2
B3.3
B3.4
B3.5

Chapter B4

About the system memory model .................................................
Declarations and support functions ..............................................
Memory accesses ........................................................................
Control of the endianness model in ARMv6-M .............................
Barrier support for system correctness ........................................

ARMv6-M and ARMv7-M compatibility .................................. AppxC-368
About the ARMv6-M and ARMv7-M architecture profiles ...... AppxC-369
Instruction support ................................................................. AppxC-370

vii

Contents

C.4
C.5
C.6
C.7

Appendix D

Instruction encoding diagrams and pseudocode ...................
Limitations of pseudocode .....................................................
Data types ..............................................................................
Expressions ...........................................................................
Operators and built-in functions .............................................
Statements and program structure ........................................
Miscellaneous helper procedures and functions ....................

AppxE-386
AppxE-388
AppxE-389
AppxE-393
AppxE-395
AppxE-401
AppxE-406

Pseudocode Index
F.1
F.2

Appendix G

Thumb instruction mnemonics ............................................... AppxD-380
Pre-UAL pseudo-instruction NOP .......................................... AppxD-384

Pseudocode Definition
E.1
E.2
E.3
E.4
E.5
E.6
E.7

Appendix F

AppxC-371
AppxC-373
AppxC-375
AppxC-377

Legacy Instruction Mnemonics
D.1
D.2

Appendix E

Programmers’ model support .................................................
Memory model support ..........................................................
System Control Space register support .................................
Debug support .......................................................................

Pseudocode operators and keywords .................................... AppxF-410
Pseudocode functions and procedures .................................. AppxF-414

ARM core registers ............................................................... AppxG-422
Memory mapped system registers ........................................ AppxG-423
Memory mapped debug registers ......................................... AppxG-424

Glossary

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List of Tables
ARMv6-M Architecture Reference Manual

Table A3-1
Table A3-2
Table A4-1
Table A4-2
Table A4-3
Table A4-4
Table A4-5
Table A4-6
Table A4-7
Table A4-8
Table A5-1
Table A5-2
Table A5-3
Table A5-4
Table A5-5
Table A5-6
Table A5-7
Table A5-8
Table A5-9
Table A5-10
Table A5-11
Table A6-1

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Change History .................................................................................................... ii
Load-store and element size association ..................................................... A3-46
Summary of memory attributes .................................................................... A3-49
Branch instructions ....................................................................................... A4-70
Standard data-processing instructions ......................................................... A4-71
Shift instructions ........................................................................................... A4-72
Packing and unpacking instructions ............................................................. A4-73
Miscellaneous data-processing instructions ................................................. A4-73
Load and store instructions .......................................................................... A4-75
Load Multiple and Store Multiple instructions ............................................... A4-77
Miscellaneous instructions ........................................................................... A4-78
16-bit Thumb instruction encoding ............................................................... A5-84
16-bit Thumb encoding ................................................................................ A5-85
16-bit Thumb data processing instructions .................................................. A5-86
Special data instructions and branch and exchange .................................... A5-87
16-bit Thumb Load and store instructions .................................................... A5-88
Miscellaneous 16-bit instructions ................................................................. A5-89
Hint instructions ............................................................................................ A5-90
Conditional branch and Supervisor Call instructions .................................... A5-90
32-bit Thumb encoding ................................................................................ A5-91
Branch and miscellaneous control instructions ............................................ A5-91
Miscellaneous control instructions ............................................................... A5-92
Condition codes ........................................................................................... A6-99

List of Tables

Table A6-2
Table B1-1
Table B1-2
Table B1-3
Table B1-4
Table B1-5
Table B1-6
Table B1-7
Table B3-1
Table B3-2
Table B3-3
Table B3-4
Table B3-5
Table B3-6
Table B3-7
Table B3-8
Table B3-9
Table B3-10
Table B3-11
Table B3-12
Table B3-13
Table B3-14
Table B3-15
Table B3-16
Table B3-17
Table B3-18
Table B3-19
Table B3-20
Table B3-21
Table B3-22
Table B3-23
Table B3-24
Table B3-25
Table B3-26
Table B3-27
Table B3-28
Table B3-29
Table B3-30
Table B3-31
Table B3-32
Table B4-1
Table C1-1
Table C1-2
Table C1-3
Table C1-4
Table C1-5
Table C1-6

MOV (shift, register shift) equivalences) ....................................................
Mode, privilege and stack relationship .......................................................
Mnemonics for combinations of xPSR registers ........................................
Exception numbers ....................................................................................
Vector table format .....................................................................................
Exception return behavior ..........................................................................
List of supported faults ...............................................................................
Lockup conditions ......................................................................................
ARMv6-M address map .............................................................................
Subdivision of the System region of the ARMv6-M address map ..............
SCS address space regions .......................................................................
System control and ID register summary ...................................................
CPUID Base Register bit assignments ......................................................
ICSR bit assignments .................................................................................
VTOR bit assignments ...............................................................................
AIRCR bit assignments ..............................................................................
SCR bit assignments ..................................................................................
CCR bit assignments .................................................................................
SHPR2 Register bit assignments ...............................................................
SHPR3 Register bit assignments ...............................................................
SysTick register summary ..........................................................................
SYST_CSR bit assignments ......................................................................
SYST_RVR bit assignments ......................................................................
SYST_CVR bit assignments ......................................................................
SYST_CALIB Register bit assignments .....................................................
NVIC register summary ..............................................................................
NVIC_ISER bit assignments ......................................................................
NVIC_ICER bit assignments ......................................................................
NVIC_ISPR bit assignments ......................................................................
NVIC_ICPR bit assignments ......................................................................
NVIC_IPRn bit assignments .......................................................................
MPU register summary ..............................................................................
MPU_TYPE Register bit assignments .......................................................
MPU_CTRL Register bit assignments .......................................................
MPU_RNR bit assignments .......................................................................
MPU_RBAR bit assignments .....................................................................
MPU_RASR bit assignments .....................................................................
TEX, C, B, and S encoding ........................................................................
Access permissions field encoding ............................................................
Execute Never encoding ............................................................................
Special register field encoding ...................................................................
PPB debug related regions ........................................................................
Determining the debug support in an ARMv6-M implementation ...............
ROM table entry format ..............................................................................
ARMv6-M DAP accessible ROM table .......................................................
ARM debug authentication signals .............................................................
Debug related event status ........................................................................

A6-157
B1-206
B1-213
B1-220
B1-220
B1-228
B1-237
B1-239
B3-259
B3-260
B3-262
B3-263
B3-265
B3-266
B3-268
B3-269
B3-270
B3-272
B3-273
B3-273
B3-276
B3-277
B3-279
B3-279
B3-280
B3-283
B3-284
B3-285
B3-286
B3-287
B3-288
B3-293
B3-294
B3-295
B3-297
B3-298
B3-299
B3-301
B3-301
B3-302
B4-304
C1-316
C1-317
C1-319
C1-319
C1-320
C1-324

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List of Tables

Table C1-7
Table C1-8
Table C1-9
Table C1-10
Table C1-11
Table C1-12
Table C1-13
Table C1-14
Table C1-15
Table C1-16
Table C1-17
Table C1-18
Table C1-19
Table C1-20
Table C1-21
Table C1-22
Table C1-23
Table C1-24
Table A-1
Table A-2
Table C-1
Table C-2
Table D-1
Table F-1
Table F-2
Table G-1
Table G-2
Table G-3

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Debug stepping control using the DHCSR ................................................. C1-326
DCB register summary ............................................................................... C1-328
SHCSR bit assignments ............................................................................. C1-329
DFSR bit assignments ............................................................................... C1-330
DHCSR bit assignments ............................................................................ C1-332
DCRSR bit assignments ............................................................................ C1-336
DCRDR bit assignments ............................................................................ C1-337
DEMCR bit assignments ............................................................................ C1-339
General DWT function support ................................................................... C1-342
DWT register summary .............................................................................. C1-345
DWT_CTRL register bit assignments ......................................................... C1-346
DWT_PCSR bit assignments ..................................................................... C1-347
DWT_COMPx register bit assignments ...................................................... C1-348
DWT_MASKx register bit assignments ...................................................... C1-349
DWT_FUNCTIONx register bit assignments .............................................. C1-350
BPU register summary ............................................................................... C1-352
BP_CTRL register bit assignments ............................................................ C1-353
BP_COMPx register bit assignments ......................................................... C1-354
Component and Peripheral ID register formats .................................... AppxA-360
ARMv6-M CoreSight management registers ........................................ AppxA-361
ARMv6-M and ARMv7-M software compatibility .................................. AppxC-368
Programmers’ model feature comparison ............................................ AppxC-371
Pre-UAL assembly syntax .................................................................... AppxD-380
Pseudocode operators and keywords .................................................. AppxF-410
Pseudocode functions and procedures ................................................ AppxF-414
ARM core register index ...................................................................... AppxG-422
Memory-mapped control register index ............................................... AppxG-423
Memory-mapped debug register index ............................................... AppxG-424

List of Tables

xii

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List of Figures
ARMv6-M Architecture Reference Manual

Figure A3-1
Figure A3-2
Figure A3-3
Figure A3-4
Figure A3-5
Figure A3-6
Figure B1-1
Figure B1-2
Figure B3-1
Figure B3-2
Figure B3-3
Figure B3-4
Figure B3-5
Figure B3-6
Figure B3-7
Figure B3-8
Figure B3-9
Figure B3-10
Figure B3-11
Figure B3-12
Figure B3-13
Figure B3-14
Figure B3-15

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Little-endian byte format ............................................................................... A3-44
Big-endian byte format ................................................................................. A3-44
Little-endian memory system ....................................................................... A3-45
Big-endian memory system .......................................................................... A3-45
Instruction byte order in memory .................................................................. A3-46
Memory ordering restrictions ........................................................................ A3-60
xPSR register layout .................................................................................. B1-212
PRIMASK register bit assignments ............................................................ B1-214
CPUID Base Register bit assignments ...................................................... B3-264
ICSR bit assignments ................................................................................. B3-265
VTOR bit assignments ............................................................................... B3-267
AIRCR bit assignments .............................................................................. B3-268
SCR bit assignments .................................................................................. B3-270
CCR bit assignments ................................................................................. B3-271
SHPR2 Register bit assignments ............................................................... B3-272
SHPR3 Register bit assignments ............................................................... B3-273
SYST_CSR bit assignments ...................................................................... B3-277
SYST_RVR bit assignments ...................................................................... B3-278
SYST_CVR bit assignments ...................................................................... B3-279
SYST_CALIB Register bit assignments ..................................................... B3-280
NVIC_ISER bit assignments ...................................................................... B3-284
NVIC_ICER bit assignments ...................................................................... B3-285
NVIC_ISPR bit assignments ...................................................................... B3-286

xiii

List of Figures

Figure B3-16
Figure B3-17
Figure B3-18
Figure B3-19
Figure B3-20
Figure B3-21
Figure B3-22
Figure C1-1
Figure C1-2
Figure C1-3
Figure C1-4
Figure C1-5
Figure C1-6
Figure C1-7
Figure C1-8
Figure C1-9
Figure C1-10
Figure C1-11
Figure C1-12
Figure C1-13
Figure C1-14

xiv

NVIC_ICPR bit assignments ......................................................................
NVIC_IPRn bit assignments .......................................................................
MPU_TYPE Register bit assignments .......................................................
MPU_CTRL Register bit assignments .......................................................
MPU_RNR bit assignments .......................................................................
MPU_RBAR bit assignments .....................................................................
MPU_RASR bit assignments .....................................................................
DBGRESTART / DBGRESTARTED handshake .......................................
SHCSR bit assignments .............................................................................
DFSR bit assignments ...............................................................................
DHCSR bit assignments ............................................................................
DCRSR bit assignments ............................................................................
DCRDR bit assignments ............................................................................
DEMCR bit assignments ............................................................................
DWT_CTRL register bit assignments .........................................................
DWT_PCSR bit assignments .....................................................................
DWT_COMPx register bit assignments .....................................................
DWT_MASKx register bit assignments ......................................................
DWT_FUNCTIONx register bit assignments ..............................................
BP_CTRL register bit assignments ............................................................
BP_COMPx register bit assignments .........................................................

B3-287
B3-288
B3-294
B3-295
B3-296
B3-297
B3-299
C1-321
C1-329
C1-330
C1-332
C1-335
C1-337
C1-339
C1-346
C1-347
C1-348
C1-348
C1-349
C1-352
C1-354

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Preface

This preface introduces the ARM®v6-M Architecture Reference Manual. It contains the following sections:
•
About this manual on page xvi
•
Using this manual on page xvii
•
Conventions on page xix
•
Additional reading on page xx
•
Feedback on page xxi.

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Preface

About this manual
This manual documents a substantially reduced version of the ARMv7 Microcontroller profile. This
architecture variant aligns strongly with the ARMv6 Thumb instruction set and is known as ARMv6-M. See
page A1-25 for short-form definitions of all the ARMv7 profiles and how they relate to ARMv6-M.
Part A describes the application level programming model and memory model along with the instruction set
as visible to the application programmer. This information is required to program applications or to develop
the toolchain components. That is, the compiler, linker, assembler, and disassembler, but not the debugger.

Note
The ARM® architecture supports a common procedure calling standard, the ARM Architecture Procedure
Calling Standard (AAPCS).
Part B describes the system level programming model and system level support instructions required for
system correctness. The system level supports the ARMv6-M exception model. It also provides features for
configuration and control of processor resources and management of memory access rights.
This information, together with Part A, is required for operating system and/or system support software. It
includes details of the exception model, memory protection, that is management of access rights, and
integrated system component support.
Part B is profile specific. ARMv6-M and ARMv7-M share a new programmers’ model and as such have
some fundamental differences at the system level from the other ARM architecture profiles. As ARMv6-M
is a memory-mapped architecture, the system memory map is documented here.
Part C describes the debug features that support the ARMv6-M debug architecture, and the programming
interface to the debug environment.
This information, together with Parts A and B, is required to write a debugger. Part C is profile specific and
includes several debug features unique within the architecture to the Microcontroller profile.
The appendices provide information that relates to, but is not part of, the ARMv6-M architecture profile
specification.

xvi

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Preface

Using this manual
The information in this manual is organized into four parts, as described in this section.

Part A, Application level architecture
Part A describes the application level view of the architecture. It contains the following chapters:
Chapter A1 Introduction
Introduces the ARM architecture profiles, including the Microcontroller (M) profile, and
the relationship between the ARMv6-M and ARMv7-M architecture profiles.
Chapter A2 Application Level Programmers’ Model
Gives an application-level view of the ARMv6-M programmers’ model, including a
summary of the exception model.
Chapter A3 ARM Architecture Memory Model
Gives an application-level view of the ARMv6-M memory model, including the ARM
memory attributes and memory ordering model.
Chapter A4 The ARMv6-M Instruction Set
Describes the ARMv6-M Thumb® instruction set.
Chapter A5 The Thumb Instruction Set Encoding
Describes the encoding of the Thumb instruction set.
Chapter A6 Thumb Instruction Details
Provides detailed reference material on each Thumb instruction, arranged alphabetically by
instruction mnemonic, including summary information for system-level instructions.

Part B, System level architecture
Part B describes the system level view of the architecture. It contains the following chapters:
Chapter B1 System Level Programmers’ Model
Gives a system-level view of the ARMv6-M programmers’ model, including the exception
model.
Chapter B2 System Memory Model
Provides a pseudocode description of the ARMv6-M memory model.
Chapter B3 System Address Map
Describes the ARMv6-M system address map, including the memory-mapped registers and
the optional Protected Memory System Architecture (PMSA).

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xvii

Preface

Chapter B4 ARMv6-M System Instructions
Provides detailed reference material on the system level instructions.

Part C, Debug architecture
Part C describes the Debug architecture. It contains the following chapter:
Chapter C1 ARMv6-M Debug
Describes the ARMv6-M debug architecture.

Part D, Appendices
This manual contains the following appendices:
Appendix A ARMv6-M CoreSight Infrastructure IDs
Summarizes the ARM CoreSight™ compatible ID registers used for ARM architecture
infrastructure identification.
Appendix D Legacy Instruction Mnemonics
Describes the legacy mnemonics and their Unified Assembler Language (UAL)
equivalents..
Appendix B Deprecated and Obsolete Features
Lists the features of the ARMv6-M architecture that are deprecated or obsolete.
Appendix C ARMv7-M Differences
Summarizes the differences between the ARMv6-M and ARMv7-M Microcontroller
profiles.
Appendix E Pseudocode Definition
Provides the formal definition of the pseudocode used in this manual.
Appendix F Pseudocode Index
Index to definitions of pseudocode operators, keywords, functions, and procedures.
Appendix G Register Index
An index to register descriptions in the manual.
Glossary
Glossary of terms used in this manual. The glossary does not include terms associated with
the pseudocode.

xviii

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Conventions
This manual employs typographic and other conventions intended to improve its ease of use.

Typographic conventions
The typographical conventions are:
italic

Highlights important notes, introduces special terminology, and denotes internal
cross-references and citations.

bold

Denotes signal names and is used for terms in descriptive lists, where appropriate.

monospace

Used for assembler syntax descriptions, pseudocode, and source code examples.
Also used in the main text for instruction mnemonics and for references to other
items appearing in assembler syntax descriptions, pseudocode, and source code
examples.

SMALL CAPITALS

Used for a few terms that have specific technical meanings, and are included in the
Glossary.

Signals
In general this specification does not define processor signals, but it does include some signal examples and
recommendations. The signal conventions are:
Signal level

The level of an asserted signal depends on whether the signal is active-HIGH or
active-LOW. Asserted means:
•
HIGH for active-HIGH signals
•
LOW for active-LOW signals.

Lower-case n

At the start or end of a signal name denotes an active-LOW signal.

Numbers
Numbers are normally written in decimal. Binary numbers are preceded by 0b, and hexadecimal numbers
by 0x. Both are written in a monospaced font.

Pseudocode descriptions
This manual uses a form of pseudocode to provide precise descriptions of the specified functionality. This
pseudocode is written in a monospaced font, and is described in Appendix E Pseudocode Definition.

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Preface

Additional reading
This section lists relevant publications from ARM and third parties.

See the Infocenter, http://infocenter.arm.com, for access to ARM documentation.
ARM publications
•
•
•
•
•

ARMv7-M Architecture Reference Manual (ARM DDI 0403)
ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition.(ARM DDI 0406)
Procedure Call Standard for the ARM Architecture (ARM GENC 003534)
ARM Debug Interface v5 Architecture Specification (ARM IHI 0031)
CoreSight Architecture Specification (ARM IHI 0029).

Other publications
The following book is referred to in this manual, or provide more information:
•

Memory Consistency Models for Shared Memory-Multiprocessors, Kourosh Gharachorloo, Stanford
University Technical Report CSL-TR-95-685.

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Feedback
ARM welcomes feedback on its documentation.

Feedback on this book
If you have comments on the content of this manual, send e-mail to errata@arm.com. Give:
•
the title
•
the number, ARM DDI 0419C
•
the page numbers to which your comments apply
•
a concise explanation of your comments.
ARM also welcomes general suggestions for additions and improvements.

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Preface

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Part A
Application Level Architecture

Chapter A1
Introduction

This chapter introduces the ARM architecture profiles, and the ARMv6-M profile that this manual defines.
It contains the following sections:
•
About the ARM architecture profiles on page A1-26
•
Privileged and unprivileged execution on page A1-27.

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Introduction

A1.1

About the ARM architecture profiles
ARMv7 is documented as a set of architecture profiles, defined as follows:
ARMv7-A

the application profile for systems supporting the ARM and Thumb instruction sets, and
requiring virtual address support in the memory management model.

ARMv7-R

the realtime profile for systems supporting the ARM and Thumb instruction sets, and
requiring physical address only support in the memory management model.

ARMv7-M

the microcontroller profile for systems supporting only the Thumb instruction set, and
where overall size and deterministic operation for an implementation are more important
than absolute performance.

While profiles were formally introduced with the ARMv7 development, the A-profile and R-profile have
existed implicitly in earlier versions, associated with the Virtual Memory System Architecture (VMSA) and
Protected Memory System Architecture (PMSA) respectively.
ARMv6-M is a subset of ARMv7-M, that provides:
•
a lightweight version of the ARMv7-M programming model
•
the Debug Extension that includes architecture extensions for debug support, see Chapter C1
ARMv6-M Debug.
•
ARMv6 Thumb 16-bit instruction set compatibility at the application level
•
an optional Unprivileged/Privileged Extension, see Privileged and unprivileged execution on
page A1-27
•
an optional PMSA Extension, see Protected Memory System Architecture, PMSAv6 on page B3-289.

Note
ARMv6-M is upwardly compatible with ARMv7-M, meaning that application level and system level
software developed for ARMv6-M can execute unmodified on ARMv7-M. ARMv7-M to ARMv6-M
compatibility is not an architecture requirement. Many of the system level registers defined to support
ARMv7-M features are reserved in ARMv6-M. Software must treat values read from reserved registers as
UNKNOWN. Hardware must implement these values as RAZ/WI.

A1.1.1

Instruction Set Architecture (ISA)
ARMv6-M supports the Thumb instruction set, including a small number of 32-bit instructions introduced
to the architecture as part of the Thumb-2 technology in ARMv6T2.
ARMv6-M supports the 16-bit Thumb instructions from ARMv7-M, in addition to the 32-bit BL, DMB, DSB,
ISB, MRS and MSR instructions.

A1-26

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A1.2

Privileged and unprivileged execution
In ARMv7-M, software can run either at privileged or unprivileged level. In systems implemented with the
ARMv6-M base architecture, all software runs at privileged level.
By adding the Unprivileged/Privileged Extension, ARMv6-M systems can use the same privilege levels as
ARMv7-M while still having the benefit of very low gate count.
In addition, with the same privilege levels as ARMv7-M, ARMv6-M systems can use the optional Memory
Protection Unit (MPU) that the PMSA Extension provides.
The ARMv6-M implementation options are:
•
ARMv6-M base architecture only
•
ARMv6-M base architecture + Unprivileged/Privileged Extension
•
ARMv6-M base architecture + Unprivileged/Privileged Extension + PMSA Extension.

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Introduction

A1-28

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Chapter A2
Application Level Programmers’ Model

This chapter provides an application-level view of the ARMv6-M programmers’ model. It contains the
following sections:
•
About the application level programmers’ model on page A2-30
•
ARM processor data types and arithmetic on page A2-31
•
Registers and execution state on page A2-36
•
Exceptions, faults and interrupts on page A2-39
•
Coprocessor support on page A2-40.

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Application Level Programmers’ Model

A2.1

About the application level programmers’ model
This chapter contains the programmers’ model information required for developing applications. See
Chapter B1 System Level Programmers’ Model for system information required to service and support
application execution under an operating system.

A2.1.1

Privileged execution
System level support requires access to all features and facilities of the architecture, a level of access
generally referred to as privileged operation. When an operating system supports both privileged and
unprivileged operation, an application usually runs unprivileged.
An application running unprivileged:
•

means the operating system can allocate system resources to the application, as either private or
shared resources

•

provides a degree of protection from other processes and tasks, and so helps protect the operating
system from malfunctioning applications.

An ARMv6-M implementation only supports privileged operation, unless it includes the
Unprivileged/Privileged Extension, in which case the implementation supports both unprivileged and
privileged operation.

A2.1.2

Interaction with the system level architecture
Thread mode is the fundamental mode for application execution in ARMv6-M and is selected on reset.
Thread mode can raise a supervisor call using the SVC instruction, generating a Supervisor call exception,
SVCall. Alternatively, if running privileged, Thread mode can handle system access and control directly.
All exceptions execute in Handler mode. SVCall handlers manage resources, such as interaction with
peripherals, memory allocation and management of software stacks, on behalf of the application.
In ARMv6-M implementations that include the Unprivileged/Privileged Extension:
•

execution in Handler mode is always privileged

•

execution in Thread mode can be privileged or unprivileged, depending on the value of
CONTROL.nPRIV.

This chapter only provides system level information that is required to understand application level
operation. Where appropriate it:

A2-30

•

provides an overview of the system level information

•

provides references to the system level descriptions in Chapter B1 System Level Programmers’
Model and elsewhere.

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A2.2

ARM processor data types and arithmetic
ARM processors support the following data types in memory:
Byte
8 bits
Halfword
16 bits
Word
32 bits
Doubleword 64 bits.
Processor registers are 32 bits in size. The Thumb instruction set contains instructions supporting the
following data types held in registers:
•
32-bit pointers
•
unsigned or signed 32-bit integers
•
unsigned 16-bit or 8-bit integers, held in zero-extended form
•
signed 16-bit or 8-bit integers, held in sign-extended form
•
unsigned or signed 64-bit integers held in two registers.
Load and store operations can transfer bytes, halfwords, or words to and from memory. Loads of bytes or
halfwords zero-extend or sign-extend the data as it is loaded, as specified in the appropriate load instruction.
The instruction sets include load and store operations that transfer two or more words to and from memory.
You can load and store 64-bit integers using these instructions.
When any of the data types is described as unsigned, the N-bit data value represents a non-negative integer
in the range 0 to 2N-1, using normal binary format.
When any of these types is described as signed, the N-bit data value represents an integer in the range -2N-1
to +2N-1-1, using two's complement format.
ARMv6-M has no direct instruction support for 64-bit integers.

Note
ARMv7-M has limited support for 64-bit integers. Most 64-bit operations require sequences of two or more
instructions to synthesize them.

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Application Level Programmers’ Model

A2.2.1

Integer arithmetic
The instruction set provides a wide variety of operations on the values in registers, including bitwise logical
operations, shifts, additions, subtractions, and multiplication. This manual describes these operations using
pseudocode, usually in one of the following ways:
•

Using the pseudocode operators and built-in functions defined in Operators and built-in functions on
page AppxE-395.

•

Using pseudocode helper functions defined in the main text.

•

Using a sequence of the form:
1.

Using the SInt(), UInt(), and Int() built-in functions defined in Converting bitstrings to
integers on page AppxE-398 to convert the bitstring contents of the instruction operands to the
unbounded integers that they represent as two's complement or unsigned integers. Converting
bitstrings to integers on page AppxE-398 defines these functions.

Using mathematical operators, built-in functions and helper functions on those unbounded
integers to calculate other two’s complement or unsigned integers.

Using the bitstring extraction operator defined in Bitstring extraction on page AppxE-396 to
convert an unbounded integer result into a bitstring result that can be written to a register.

Appendix E Pseudocode Definition describes the ARM pseudocode.

Shift and rotate operations
ARMv6-M instructions use the following types of shift and rotate operations:
Logical Shift Left
(LSL) moves each bit of a bitstring left by a specified number of bits. Zeros are shifted in at
the right end of the bitstring. Bits that are shifted off the left end of the bitstring are
discarded, except that the last such bit can be produced as a carry output.
Logical Shift Right
(LSR) moves each bit of a bitstring right by a specified number of bits. Zeros are shifted in
at the left end of the bitstring. Bits that are shifted off the right end of the bitstring are
discarded, except that the last such bit can be produced as a carry output.
Arithmetic Shift Right
(ASR) moves each bit of a bitstring right by a specified number of bits. Copies of the leftmost
bit are shifted in at the left end of the bitstring. Bits that are shifted off the right end of the
bitstring are discarded, except that the last such bit can be produced as a carry output.
Rotate Right (ROR) moves each bit of a bitstring right by a specified number of bits. Each bit that is shifted
off the right end of the bitstring is re-introduced at the left end. The last bit shifted off the
the right end of the bitstring can be produced as a carry output.

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Pseudocode details of shift and rotate operations
These shift and rotate operations are supported in pseudocode by the following functions:
// LSL_C()
// =======
(bits(N), bit) LSL_C(bits(N) x, integer shift)
assert shift > 0;
extended_x = x : Zeros(shift);
result = extended_x;
carry_out = extended_x;
return (result, carry_out);
// LSL()
// =====
bits(N) LSL(bits(N) x, integer shift)
assert shift >= 0;
if shift == 0 then
result = x;
else
(result, -) = LSL_C(x, shift);
return result;
// LSR_C()
// =======
(bits(N), bit) LSR_C(bits(N) x, integer shift)
assert shift > 0;
extended_x = ZeroExtend(x, shift+N);
result = extended_x;
carry_out = extended_x;
return (result, carry_out);
// LSR()
// =====
bits(N) LSR(bits(N) x, integer shift)
assert shift >= 0;
if shift == 0 then
result = x;
else
(result, -) = LSR_C(x, shift);
return result;
// ASR_C()
// =======
(bits(N), bit) ASR_C(bits(N) x, integer shift)
assert shift > 0;
extended_x = SignExtend(x, shift+N);
result = extended_x;
carry_out = extended_x;

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Application Level Programmers’ Model

return (result, carry_out);
// ASR()
// =====
bits(N) ASR(bits(N) x, integer shift)
assert shift >= 0;
if shift == 0 then
result = x;
else
(result, -) = ASR_C(x, shift);
return result;
// ROR_C()
// =======
(bits(N), bit) ROR_C(bits(N) x, integer shift)
assert shift != 0;
m = shift MOD N;
result = LSR(x,m) OR LSL(x,N-m);
carry_out = result;
return (result, carry_out);
// ROR()
// =====
bits(N) ROR(bits(N) x, integer shift)
if n == 0 then
result = x;
else
(result, -) = ROR_C(x, shift);
return result;
// RRX_C()
// =======
(bits(N), bit) RRX_C(bits(N) x, bit carry_in)
result = carry_in : x;
carry_out = x<0>;
return (result, carry_out);
// RRX()
// =====
bits(N) RRX(bits(N) x, bit carry_in)
(result, -) = RRX_C(x, carry_in);
return result;

Note
ARMv6-M does not support the RRX instruction and therefore does not use the RRX_C() or RRX() functions.
Pseudocode functions that are common with ARMv7-M reference these functions, but they are never called
in ARMv6-M operation.

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Pseudocode details of addition and subtraction
In pseudocode, addition and subtraction can be performed on any combination of unbounded integers and
bitstrings, provided that if they are performed on two bitstrings, the bitstrings must be identical in length.
The result is another unbounded integer if both operands are unbounded integers, and a bitstring of the same
length as the bitstring operand(s) otherwise. For the precise definition of these operations, see Addition and
subtraction on page AppxE-399.
The main addition and subtraction instructions can produce status information about both unsigned carry
and signed overflow conditions. This status information can be used to synthesize multi-word additions and
subtractions. In pseudocode the AddWithCarry() function provides an addition with a carry input and carry
and overflow outputs:
// AddWithCarry()
// ==============
(bits(N), bit, bit) AddWithCarry(bits(N) x, bits(N) y, bit carry_in)
unsigned_sum = UInt(x) + UInt(y) + UInt(carry_in);
signed_sum
= SInt(x) + SInt(y) + UInt(carry_in);
result
= unsigned_sum; // same value as signed_sum
carry_out
= if UInt(result) == unsigned_sum then '0' else '1';
overflow
= if SInt(result) == signed_sum then '0' else '1';
return (result, carry_out, overflow);

An important property of the AddWithCarry() function is that if:
(result, carry_out, overflow) = AddWithCarry(x, NOT(y), carry_in)

then:
•

If carry_in == '1', then result == x-y with overflow == '1' if signed overflow occurred during the
subtraction and carry_out == '1' if unsigned borrow did not occur during the subtraction. That is, if
x >= y.

•

If carry_in == '0', then result == x-y-1 with overflow == '1' if signed overflow occurred during
the subtraction and carry_out == '1' if unsigned borrow did not occur during the subtraction. That
is, if x > y.

Together, these mean that the carry_in and carry_out bits in AddWithCarry() calls can act as NOT borrow
flags for subtractions and also as carry flags for additions.

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A2-35

Application Level Programmers’ Model

A2.3

Registers and execution state
The application level programmers’ model provides details of the general-purpose and special-purpose
registers visible to the application programmer, the ARM memory model, and the instruction set used to
load registers from memory, store registers to memory, or manipulate data within the registers.
Applications often interact with external events. A summary of the types of events recognized in the
architecture, along with the mechanisms provided in the architecture to interact with events, is included in
Exceptions, faults and interrupts on page A2-39. How events are handled is a system level topic described
in ARMv6-M exception model on page B1-218.

A2.3.1

ARM core registers
There are thirteen general-purpose 32-bit registers, R0-R12, and an additional three 32-bit registers that
have special names and usage models:
SP

Stack Pointer, used a pointer to the active stack. For usage restrictions see Use of 0b1101 as
a register specifier on page A5-83. This is preset to the top of the Main stack on reset. See
The SP registers on page B1-211 for more information. SP is sometimes referred to as R13.

Link Register stores the Return Link. This is a value that relates to the return address from
a subroutine that is entered using a Branch with Link instruction. The LR register is also
updated on exception entry, see Exception entry behavior on page B1-224. LR is sometimes
referred to as R14.

Note
LR can be used for other purposes when it is not required to support a return from a
subroutine.
PC

Program Counter, see Use of 0b1111 as a register specifier on page A5-82 for more
information. The PC is loaded with the Reset handler start address on reset. PC is sometimes
referred to as R15.

Pseudocode details of ARM core register operations
In pseudocode, the R[] function is used to:
•
Read or write R0-R12, SP, and LR, using n == 0-12, 13, and 14 respectively.
•
Read the PC, using n == 15.
This function has prototypes:
bits(32) R[integer n]
assert n >= 0 && n <= 15;
R[integer n] = bits(32) value
assert n >= 0 && n <= 14;

A2-36

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Application Level Programmers’ Model

See Pseudocode details for ARM core register access on page B1-216 for more information about the R[]
function. Writing an address to the PC causes either a simple branch to that address or an interworking
branch that, in ARMv6-M, must select the Thumb instruction set to execute after the branch.

Note
The following pseudocode defines behavior in ARMv6-M and the M-profile in general. It is much simpler
than the equivalent pseudo-function definitions that apply to other ARM architecture profiles.
A simple branch is performed by the BranchWritePC() function:
// BranchWritePC()
// ===============
BranchWritePC(bits(32) address)
BranchTo(address<31:1>:’0’);

The BXWritePC() and BLXWritePC() functions each perform an interworking branch:
// BXWritePC()
// ===========
BXWritePC(bits(32) address)
if CurrentMode == Mode_Handler && address<31:28> == '1111' then
ExceptionReturn(address<27:0>);
else
EPSR.T = address<0>; // if EPSR.T == 0, a HardFault
// is taken on the next instruction
BranchTo(address<31:1>:'0');
// BLXWritePC()
// ============
BLXWritePC(bits(32) address)
EPSR.T = address<0>; // if EPSR.T == 0, a HardFault is taken on the next instruction
BranchTo(address<31:1>:’0’);

The LoadWritePC() and ALUWritePC() functions are used for two cases where the behavior was systematically
modified between architecture versions. The functions simplify to aliases of the branch functions in the
M-profile architecture variants:
// LoadWritePC()
// =============
LoadWritePC(bits(32) address)
BXWritePC(address);
// ALUWritePC()
// ============
ALUWritePC(bits(32) address)

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A2-37

Application Level Programmers’ Model

BranchWritePC(address);

A2.3.2

The Application Program Status Register
Program status is reported in the 32-bit APSR. The APSR bit assignments are:
31 30 29 28 27

N Z C V

Reserved

APSR bit fields are in the following categories:
•

•

Reserved bits are allocated to system features or are available for future expansion. See The
special-purpose program status registers, xPSR on page B1-212 for more information about
currently allocated reserved bits. Application level software must ignore values read from reserved
bits, and preserve their value on a write. The bits are defined as UNK/SBZP.
Flags that many instructions can update:
N, bit [31] Negative condition code flag. Set to bit [31] of the result of the instruction. If the result
is regarded as a two's complement signed integer, then N is set to 1 if the result is negative
and set to 0 if it is positive or zero.
Z, bit [30] Zero condition code flag. Set to 1 if the result of the instruction is zero, and to 0 otherwise.
A result of zero often indicates an equal result from a comparison.
C, bit [29] Carry condition code flag. Set to 1 if the instruction results in a carry condition, for
example an unsigned overflow on an addition.
V, bit [28] Overflow condition code flag. Set to 1 if the instruction results in an overflow condition,
for example a signed overflow on an addition.

Note
The instruction descriptions in Chapter A6 Thumb Instruction Details and Chapter B4 ARMv6-M System
Instructions indicate whether an instruction updates these flags, and if so, which flags are updated and the
conditions that determine each update.

A2.3.3

Execution state support
ARMv6-M only executes Thumb instructions, and therefore always executes instructions in Thumb state.
See Chapter A6 Thumb Instruction Details for a list of the instructions supported.
In addition to normal program execution, a Debug state exists when the Debug Extension is implemented –
see Chapter C1 ARMv6-M Debug for more details.

A2-38

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Application Level Programmers’ Model

A2.4

Exceptions, faults and interrupts
An exception can be caused by the execution of an exception generating instruction or triggered as a
response to a system behavior such as an interrupt, alignment fault or memory system fault. Synchronous
and asynchronous exceptions can occur within the architecture.

A2.4.1

System-related events
The following types of exception are system related:
•
Supervisor calls that applications use to request a service from the underlying operating system.
Using the SVC instruction, the application can instigate a supervisor call for a service requiring
privileged access to the system.
•
Instruction execution related errors.
•
Data memory access errors on any load or store.
•
Usage faults from a variety of execution state related errors, such as executing an UNDEFINED
instruction.
In general, faults are synchronous to the associated executing instruction. Some system errors can cause an
imprecise exception where it is reported at a time bearing no fixed relationship, that is, asynchronously, to
the instruction that caused it.
Interrupts are always treated as events that are asynchronous to the program flow.
An ARMv6-M implementation includes:
•

A deferred Supervisor call, PendSV. A handler uses this when it requires service from a Supervisor,
typically an underlying operating system. The PendSV handler executes when the processor takes the
associated exception. PendSV is supported by the ICSR, see Interrupt Control State Register, ICSR
on page B3-265. See Exceptions on page B1-207 for the definition of a pending exception.

Note
An application must use the SVC instruction if it requires a supervisor call that is synchronous to
program execution.
•

A Nested Vectored Interrupt Controller (NVIC) for external interrupts. See Nested Vectored Interrupt
Controller, NVIC on page B3-281 for information.

•

A BKPT instruction that generates a debug event if the Debug Extension is supported and enabled, see
Debug event behavior on page C1-324 for more information.

•

An optional system timer, SysTick, and associated interrupt. See The system timer, SysTick on
page B3-275 for information.

For power or performance reasons, software might want to notify the system that an action is complete, or
provide a hint to the system that it can suspend operation of the current task. The ARMv6-M architecture
provides instruction support for the following:
•
Send Event and Wait for Event instructions, see SEV on page A6-174 and WFE on page A6-197
•
the Wait For Interrupt instruction,. see WFI on page A6-198.
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Application Level Programmers’ Model

A2.5

Coprocessor support
ARMv6-M does not support coprocessors.

A2-40

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Chapter A3
ARM Architecture Memory Model

This chapter gives an application-level view of the ARMv6-M memory model. It contains the following
sections:
•
Address space on page A3-42
•
Alignment support on page A3-43
•
Endian support on page A3-44
•
Synchronization and semaphores on page A3-47
•
Memory types and attributes and the memory order model on page A3-48
•
Access rights on page A3-56
•
Memory access order on page A3-58
•
Caches and memory hierarchy on page A3-63.

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ARM Architecture Memory Model

A3.1

Address space
ARMv6-M is a memory-mapped architecture. The system address map on page B3-258 describes the
ARMv6-M address map.
The ARMv6-M architecture uses a single, flat address space of 232 8-bit bytes, covering 4GB. Byte
addresses are treated as unsigned numbers, running from 0 to 232 - 1.
This address space is regarded as consisting of 230 32-bit words, each of whose addresses is word-aligned,
meaning that the address is divisible by 4. The word whose word-aligned address is A consists of the four
bytes with addresses A, A+1, A+2 and A+3. The address space can also be considered as consisting of 231
16-bit halfwords, each of whose addresses is halfword-aligned, meaning that the address is divisible by 2.
The halfword whose halfword-aligned address is A consists of the two bytes with addresses A and A+1.
For ARMv6-M, instruction fetches are always halfword-aligned and data accesses are always naturally
aligned.
Address calculations are normally performed using ordinary integer instructions. This means that they wrap
around if they overflow or underflow the address space. Another way of describing this is that any address
calculation is reduced modulo 232.
Normal sequential execution of instructions effectively calculates:
(address_of_current_instruction) + (size_of_executed_instruction)

after each instruction to determine the instruction to execute next. If this calculation overflows the top of
the address space, the result is UNPREDICTABLE. In ARMv6-M this condition cannot occur because the top
of memory is defined to always have the eXecute Never (XN) memory attribute associated with it. See The
system address map on page B3-258 for more information. An access violation is reported if this scenario
occurs.
The information in this section only applies to instructions that are executed, including those that fail their
condition code check. Most ARM implementations prefetch instructions ahead of the currently-executing
instruction.
LDM, POP, PUSH, and STM instructions access a sequence of words at increasing memory addresses, effectively

incrementing a memory address by 4 for each register load or store. If this calculation overflows the top of
the address space, the result is UNPREDICTABLE.

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A3.2

Alignment support
ARMv6-M always generates a fault when an unaligned access occurs.
Writes to the PC are restricted according to the rules that Use of 0b1111 as a register specifier on page A5-82
describes.

A3.2.1

Alignment behavior
Address alignment affects data accesses and updates to the PC.

Alignment and data access
The following data accesses always generate an alignment fault:
•
Non word-aligned LDM and POP
•
Non word-aligned STM and PUSH
•
Non halfword-aligned LDR{S}H and STRH
•
Non word-aligned LDR and STR.

Alignment and updates to the PC
All instruction fetches are halfword-aligned.
For exception entry and return:
•
exception entry using a vector with bit [0] clear produces an invalid execution state
•
execution of a reserved EXC_RETURN is UNPREDICTABLE
•
loading an unaligned value from the stack into the PC on an exception return is UNPREDICTABLE.
For all other cases where the PC is updated:
•

Bit [0] of the value is ignored when loading the PC using an ADD or MOV instruction.

•

A BLX, BX, or POP instruction produces an invalid execution state if bit [0] of the value written to the
PC is zero.

Note
Attempting to execute an instruction while in an invalid execution state causes either a HardFault exception
or a Lockup condition.

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A3.3

Endian support
The address space rules, defined in Address space on page A3-42, require that for an address A:
•
the word at address A consists of the bytes at addresses A, A+1, A+2 and A+3
•
the halfword at address A consists of the bytes at addresses A and A+1
•
the halfword at address A+2 consists of the bytes at addresses A+2 and A+3
•
the word at address A therefore consists of the halfwords at addresses A and A+2.
However, this does not fully specify the mappings between words, halfwords and bytes. A memory system
uses either a little-endian or a big-endian mapping scheme that defines the endianness of the memory
system.
In a little-endian memory system:
•
a byte or halfword at address A is the least significant byte or halfword within the word at that address
•
a byte at a halfword address A is the least significant byte within the halfword at that address.
Figure A3-1 shows a little-endian mapping between bytes from memory and the interpreted value in an
ARM register.
31

Word at
Address A

24 23

16 15

8 7

Byte {Addr + 2}

Byte {Addr + 1}

Byte {Addr + 0}

Halfword at Address A

Byte {Addr + 1}

Byte {Addr + 0}

Byte {Addr + 3}

Figure A3-1 Little-endian byte format
In a big-endian memory system:
•
a byte or halfword at address A is the most significant byte or halfword within the word at that address
•
a byte at a halfword address A is the most significant byte within the halfword at that address.
Figure A3-2 shows a big-endian mapping between bytes from memory and the interpreted value in an ARM
register.
31
Word at
Address A

24 23
Byte {Addr + 0}

16 15

8 7

Byte {Addr + 1}

Byte {Addr + 2}

Byte {Addr + 3}

Halfword at Address A

Byte {Addr + 0}

Byte {Addr + 1}

Figure A3-2 Big-endian byte format
For a word address A, Figure A3-3 on page A3-45 and Figure A3-4 on page A3-45 show how the word at
address A, the halfwords at address A and A+2, and the bytes at addresses A, A+1, A+2 and A+3 map onto
each other for each endianness.

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MSByte

MSByte-1

LSByte+1

LSByte

Word at Address A

Halfword at Address A+2

Byte at Address A+3

Halfword at Address A

Byte at Address A+2

Byte at Address A+1

Byte at Address A

Figure A3-3 Little-endian memory system
MSByte

MSByte-1

LSByte+1

LSByte

Word at Address A

Halfword at Address A

Byte at Address A

Halfword at Address A+2

Byte at Address A+1

Byte at Address A+2

Byte at Address A+3

Figure A3-4 Big-endian memory system
The big-endian and little-endian mapping schemes determine the order in which the bytes of a word or
halfword are interpreted.
For example, loading a 4-byte word from address 0x1000 results in accessing the bytes contained at memory
locations 0x1000, 0x1001, 0x1002 and 0x1003, regardless of the mapping scheme used. The mapping scheme
determines the significance of those bytes.

A3.3.1

Controlling endianness in ARMv6-M
In ARMv6-M, it is IMPLEMENTATION DEFINED whether the selection of big-endian or little-endian memory
mapping is fixed, or is determined from a control input on a reset. The endian mapping has the following
restrictions:
•
The endianness setting only applies to data accesses. Instruction fetches are always little endian.
•
Loads and stores to the Private Peripheral Bus (PPB) are always little endian. See General rules for
PPB register accesses on page B3-260 for more information.
For information on endian control and status see Control of the endianness model in ARMv6-M on
page B2-254.

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Instruction alignment and byte ordering
ARMv6-M enforces 16-bit alignment on all instructions. This means that 32-bit instructions are treated as
two halfwords, hw1 and hw2, with hw1 at the lower address.
In instruction encoding diagrams, hw1 is shown to the left of hw2. This results in the encoding diagrams
reading more naturally. Figure A3-5 shows the byte order of a 32-bit Thumb instruction.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
32-bit Thumb instruction, hw1
32-bit Thumb instruction, hw2
Byte at Address A+1
Byte at Address A
Byte at Address A+3
Byte at Address A+2

Figure A3-5 Instruction byte order in memory

A3.3.2

Element size and endianness
The effect of the endianness mapping on data applies to the size of the elements being transferred in the load
and store instructions. Table A3-1 shows the element size of each of the load and store instructions.
Table A3-1 Load-store and element size association

A3.3.3

Instruction class

Instructions

Element size

Load or store byte

LDR{S}B, STRB

byte

Load or store halfword

LDR{S}H, STRH

halfword

Load or store word

LDR, STR

word

Load or store multiple words

LDM, STM, PUSH, POP

word

Instructions to reverse bytes in a general-purpose register
When an application or device driver has to interface to memory-mapped peripheral registers or shared
memory structures that are not the same endianness as that of the internal data structures, or the endianness
of the OS, an efficient way of being able to explicitly transform the endianness of the data is required.
ARMv6-M provides instructions for the following byte transformations:
REV

Reverse word, four bytes, register, for transforming 32-bit representations.

REVSH

Reverse halfword and sign extend, for transforming signed 16-bit representations.

REV16

Reverse packed halfwords in a register for transforming unsigned 16-bit representations.

See the instruction definitions in Chapter A6 Thumb Instruction Details for more information.

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A3.4

Synchronization and semaphores
Exclusive access instructions support non-blocking shared-memory synchronization primitives that enable
calculation to be performed on the semaphore between the read and write phases, and scale for
multi-processor system designs.
ARMv6-M does not support exclusive accesses.

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A3.5

Memory types and attributes and the memory order model
The ARM architecture defines a set of memory attributes with the characteristics required to support all
memory and devices in the system memory map. The ordering of accesses for regions of memory is also
defined by the memory attributes.
The following mutually-exclusive main memory type attributes describe the memory regions:
•
Normal
•
Device
•
Strongly-ordered.
Memory used for program execution and data storage generally complies with Normal memory. Examples
of Normal memory technology are:
•
Preprogrammed Flash. Updating Flash memory can impose stricter ordering rules.
•
ROM.
•
SRAM.
•
SDRAM and DDR memory.
System peripherals, or I/O, generally conform to different access rules that are defined as Strongly-ordered
or Device memory. Examples of I/O accesses are:
•

FIFOs where consecutive accesses add, or write, and remove, or read, queued values

•

interrupt controller registers where an access can be used as an interrupt acknowledge that changes
the state of the controller itself

•

memory controller configuration registers that set up the timing of areas of Normal memory

•

memory-mapped peripherals where accessing memory locations causes side effects in the system.

In addition to the main memory type attributes, the Shareable attribute indicates whether Normal or Device
memory is private to a single processor, or accessible from multiple processors or other bus master
resources, such as an intelligent peripheral with DMA capability.
Strongly-ordered memory is required where it is necessary to ensure strict ordering of the access relative to
what occurred in program order before the access and after it. Strongly-ordered memory always assumes
the resource is Shareable.

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Table A3-2 provides a summary of the memory attributes.
Table A3-2 Summary of memory attributes
Memory type
attribute

Shareable
attribute

Strongly-ordered

Shareable

All memory accesses to Strongly-ordered
memory occur in program order. All
Strongly-ordered accesses are assumed to be
Shareable.

Device

Shareable

Handles memory mapped peripherals that are
shared by several processors.

Non-Shareable

Handles memory mapped peripherals that are
used only by a single processor.

Normal

A3.5.1

Other
attribute

Description

Shareable

Non-cacheable
Write-Through cacheable
Write-Back cacheable

Handles Normal memory that is shared between
several processors.

Non-Shareable

Non-cacheable
Write-Through cacheable
Write-Back cacheable

Handles Normal memory that is used only by a
single processor.

Atomicity in the ARM architecture
Atomicity is a feature of memory accesses, described as atomic accesses. The ARM architecture description
refers to two types of atomicity, defined in:
•
Single-copy atomicity
•
Multi-copy atomicity on page A3-50.

Single-copy atomicity
A read or write operation is single-copy atomic if the following conditions are both true:
•

After any number of write operations to an operand, the value of the operand is the value written by
one of the write operations. It is impossible for part of the value of the operand to come from one
write operation and another part of the value to come from a different write operation.

•

When a read operation and a write operation are made to the same operand, the value obtained by the
read operation is one of:
—
the value of the operand before the write operation
—
the value of the operand after the write operation.
It is never the case that the value of the read operation is partly the value of the operand before the
write operation and partly the value of the operand after the write operation.

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The only ARMv6-M explicit ARM processor accesses that exhibit single-copy atomicity are:
•
all byte transactions
•
all halfword transactions to 16-bit aligned locations
•
all word transactions to 32-bit aligned locations.
LDM, STM, PUSH and POP operations are seen as a sequence of 32-bit transactions aligned to 32 bits. Each of

these 32-bit transactions are guaranteed to exhibit single-copy atomicity. Sub-sequences of two or more
32-bit transactions from the sequence might not exhibit single-copy atomicity.
When an access is not single-copy atomic, it is executed as a sequence of smaller accesses, each of which
is single-copy atomic, at least at the byte level.
For implicit accesses:
•

cache linefills and evictions have no effect on the atomicity of explicit transactions or instruction
fetches

•

instruction fetches are single-copy atomic at 16-bit granularity.

Multi-copy atomicity
In a multiprocessing system, writes to a memory location are Multi-copy atomic if the following conditions
are both true:
•

all writes to the same location are serialized, that is they are observed in the same order by all copies
of the location

•

a read of a location does not return the value of a write until all copies of the location have seen that
write.

Writes to Normal memory are not multi-copy atomic.
All writes to Device and Strongly-Ordered memory that are single-copy atomic are also multi-copy atomic.
All write accesses to the same location are serialized. Write accesses to Normal memory can be repeated up
to the point that another write to the same address is observed.
For Normal memory, serialization of writes does not prohibit the merging of writes.

A3.5.2

Normal memory
Normal memory is idempotent, meaning that it exhibits the following properties:
•
read transactions can be repeated with no side effects
•
repeated read transactions return the last value written to the resource being read
•
read transactions can prefetch additional memory locations with no side effects
•
write transactions can be repeated with no side effects, provided that the location is unchanged
between the repeated writes
•
unaligned accesses are supported
•
transactions can be merged prior to accessing the target memory system.

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Normal memory can be read and write, or read-only. The Normal memory attribute is further defined as
being Shareable or Non-Shareable, and describes most memory used in a system.
Accesses to Normal memory conform to the weakly-ordered model of memory ordering. A description of
the weakly-ordered model is contained in standard texts describing memory ordering issues. See Memory
Consistency Models for Shared Memory-Multiprocessors for more information.
All explicit accesses must correspond to the ordering requirements of accesses described in Memory access
order on page A3-58.
Instructions that conform to the sequence of transactions classification as defined in Atomicity in the ARM
architecture on page A3-49 can be abandoned if an exception occurs during the sequence of transactions.
The instruction is restarted on return from the exception, and one or more of the memory locations can be
accessed multiple times. For Normal memory, this can result in repeated write transactions to a location that
has been changed between the repeated writes.

Non-Shareable Normal memory
For a Normal memory region, the Non-shareable attribute identifies Normal memory that is likely to be
accessed only by a single processor.
A region of memory marked as Non-shareable Normal does not have any requirement to make the effect of
a cache transparent for data or instruction accesses. If other observers share the memory system, software
must use cache maintenance operations if the presence of caches might lead to coherency issues when
communicating between the observers. This cache maintenance requirement is in addition to the barrier
operations that are required to ensure memory ordering.
For Non-shareable Normal memory, the Load Exclusive and Store Exclusive synchronization primitives do
not take account of the possibility of accesses by more than one observer.

Shareable Normal memory
For Normal memory, the Shareable memory attribute describes Normal memory that is expected to be
accessed by multiple processors or other system masters.
A region of Normal memory with the Sharable attribute is one for which the effect of interposing a cache,
or caches, on the memory system is entirely transparent to data accesses in the same shareability domain.
Explicit software management is required to ensure the coherency of instruction caches.
Implementations can use a variety of mechanisms to support this management requirement, from not
caching accesses in Shareable regions to more complex hardware schemes for cache coherency for those
regions.
For Shareable Normal memory, the Load-Exclusive and Store-Exclusive synchronization primitives take
account of the possibility of accesses by more than one observer in the same Shareability domain.

Note
The Shareable concept enables system designers to specify the locations in Normal memory that must have
coherency requirements. However, to facilitate porting of software, software developers must not assume
that specifying a memory region as Non-shareable permits software to make assumptions about the
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incoherency of memory locations between different processors in a shared memory system. Such
assumptions are not portable between different multiprocessing implementations that make use of the
Shareable concept. Any multiprocessing implementation might implement caches that, inherently, are
shared between different processing elements.

Write-through cacheable, Write-back cacheable and Non-cacheable Normal
memory
In addition to marking a region of Normal memory as being Shareable or Non-Shareable, regions can also
be marked as being one of:
•
cacheable write-through
•
cacheable write-back
•
non-cacheable.
This marking is independent of the marking of a region of memory as being Shareable or Non-Shareable. It
indicates the required handling of the data region for reasons other than those to handle the requirements of
shared data. As a result, it is acceptable for a region of memory that is marked as being cacheable and
shareable not to be held in the cache in an implementation that handles shared regions by not caching the
data.

A3.5.3

Device memory
The Device memory type attribute defines memory locations where an access to the location can cause side
effects, or where the value returned for a load can vary depending on the number of loads performed.
Memory-mapped peripherals and I/O locations are examples of memory regions normally marked as being
Device memory.
For explicit accesses from the processor to memory marked as Device:
•
all accesses occur at their program size
•
the number of accesses is the number specified by the program.
An implementation must not perform more accesses to a Device memory location than are specified by a
simple sequential execution of the program, except as a result of an exception. This section describes this
permitted effect of an exception.
The architecture does not permit speculative accesses to memory marked as Device.
Address locations marked as Device are Non-cacheable. While writes to Device memory can be buffered,
writes can be merged only where the merge maintains all of the following:
•
the number of accesses
•
the order of the accesses
•
the size of each access.
Multiple accesses to the same address must not change the number of accesses to that address. Coalescing
of accesses is not permitted for accesses to Device memory.

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When a Device memory operation has side effects that apply to Normal memory regions, software must use
a memory barrier to ensure correct operation. For example, after programming the configuration registers
of a memory controller, software must perform a barrier operation before it relies on the effect of that
programming on memory accesses.
All explicit accesses to Device memory must comply with the ordering requirements of accesses described
in Memory access order on page A3-58.
An instruction that generates a sequence of accesses as described in Atomicity in the ARM architecture on
page A3-49 might be abandoned as a result of an exception being taken during the sequence of accesses. On
return from the exception the instruction is restarted, and therefore one or more of the memory locations
might be accessed multiple times. This can result in repeated write accesses to a location that has been
changed between the write accesses.

Note
Software must not use an instruction that generates a sequence of accesses to access Device memory if the
instruction might restart after an exception and repeat any accesses. For more information see Exceptions
in Load Multiple and Store Multiple operations on page B1-231.

Shareable attribute for Device memory regions
Device memory regions can be given the Shareable attribute. This means that a region of Device memory
is either:
•
Shareable Device memory
•
Non-shareable Device memory.
Non-shareable Device memory is defined as only accessible by a single processor. An example of a system
supporting Shareable and Non-shareable Device memory is an implementation that supports both:
•
a local bus for its private peripherals
•
system peripherals implemented on the main shared system bus.
Such a system might have more predictable access times for local peripherals such as watchdog timers or
interrupt controllers. In particular, a specific address in a Non-shareable Device memory region might
access a different physical peripheral for each processor.

A3.5.4

Strongly-ordered memory
The Strongly-ordered memory type attribute defines memory locations where an access to the location can
cause side effects, or where the value returned for a load can vary depending on the number of loads
performed. Examples of memory regions normally marked as being Strongly-ordered are memory-mapped
peripherals and I/O locations.
For explicit accesses from the processor to memory marked as Strongly-ordered:
•
all accesses occur at their program size
•
the number of accesses is the number specified by the program.

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An implementation must not perform more accesses to a Strongly-ordered memory location than are
specified by a simple sequential execution of the program, except as a result of an exception. This section
describes this permitted effect of an exception.
The architecture does not permit speculative data accesses to memory marked as Strongly-ordered.
Address locations in Strongly-ordered memory are not held in a cache, and are always treated as Shareable
memory locations.
All explicit accesses to Strongly-ordered memory must correspond to the ordering requirements of accesses
described in Memory access order on page A3-58.
An instruction that generates a sequence of accesses as described in Atomicity in the ARM architecture on
page A3-49 might be abandoned as a result of an exception being taken during the sequence of accesses. On
return from the exception the instruction is restarted, and therefore one or more of the memory locations
might be accessed multiple times. This can result in repeated write accesses to a location that has been
changed between the write accesses.

Note
Software must not use an instruction that generates a sequence of accesses to access Strongly-ordered
memory if the instruction might restart after an exception and repeat any write accesses. For more
information see Exceptions in Load Multiple and Store Multiple operations on page B1-231.

A3.5.5

Memory access restrictions
The following restrictions apply to memory accesses:

A3-54

•

For any access X, the bytes accessed by X must all have the same memory type attribute, otherwise,
the behavior of the access is UNPREDICTABLE. That is, unaligned accesses that span a boundary
between different memory types are UNPREDICTABLE.

•

For any two memory accesses X and Y, where X and Y are generated by the same instruction, X and
Y must all have the same memory type attribute, otherwise, the results are UNPREDICTABLE. For
example, an LDM or STM that spans a boundary between Normal and Device memory is
UNPREDICTABLE.

•

An instruction that generates and unaligned memory access to Device or Strongly-ordered memory
is UNPREDICTABLE.

•

For instructions that generate accesses to Device or Strongly-ordered memory, implementations must
not change the sequence of accesses specified by the pseudocode of the instruction. This includes not
changing:
—

the number of accesses

—

the time order of the accesses at any particular memory-mapped peripheral

—

the data sizes and other properties of each access.

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In addition, processor implementations expect any attached memory system to be able to identify the
memory type of an access, and to obey similar restrictions with regard to the number, time order, data
sizes and other properties of the access.
Exceptions to this rule are:
—

A processor implementation can break this rule, provided that the information it does supply
to the memory system enables the original number, time order, and other details of the accesses
to be reconstructed. In addition, the implementation must place a requirement on attached
memory systems to do this reconstruction when the accesses are to Device or Strongly-ordered
memory.
For example, the word loads generated by an LDM can be paired into 64-bit accesses by an
implementation with a 64-bit bus. This is because the instruction semantics ensure that the
64-bit access is always a word load from the lower address followed by a word load from the
higher address, provided a requirement is placed on memory systems to unpack the two word
loads where the access is to Device or Strongly-ordered memory.

—

Any implementation technique that produces results that cannot be observed to be different
from those described here is legitimate.

•

In ARMv6-M, it is IMPLEMENTATION DEFINED if interrupts are taken during the execution of a
multi-word instruction that uses LDM, STM, PUSH or POP. Memory accesses might repeat if a multi-word
instruction is restarted after an exception, therefore ARM recommends that multi-word instructions
are not used to access memory marked as Device or Strongly-ordered. See Exceptions in Load
Multiple and Store Multiple operations on page B1-231 for information about the architecture
constraints associated with LDM and STM, and the exception model.

•

Multi-access instructions that load or store the PC must only access Normal memory. If they access
Device or Strongly-ordered memory the results are UNPREDICTABLE.

•

Instruction fetches must only access Normal memory. If they access Device or Strongly-ordered
memory, the results are UNPREDICTABLE. For example, instruction fetches must not be performed to
areas of memory containing read-sensitive devices, because there is no ordering requirement between
instruction fetches and explicit accesses.

To ensure correctness, read-sensitive locations must be marked as non-executable, see Privilege level access
controls for instruction accesses on page A3-56. In ARMv6-M implementations that do not include the
PMSA Extension, accessibility is fixed as part of the memory map. See The system address map on
page B3-258 and Protected Memory System Architecture, PMSAv6 on page B3-289 for more details.

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A3.6

Access rights
Access rights consist of the following classes:
•
rights for data accesses
•
rights for instruction prefetching.
Access rights can be restricted to permit only privileged execution. This restriction is useful only in an
ARMv6-M implementation that includes the Unprivileged/Privileged Extension.
Instruction or data access violations cause a HardFault exception. When an implementation includes the
Unprivileged/Privileged Extension, memory accesses that do not match all access conditions of a region
address match, or a default memory map match, generate a fault. MPU registers require privileged memory
accesses for reads and writes. Unprivileged accesses generate a HardFault.
See PMSAv6 MPU operation on page B3-290 for more information.

A3.6.1

Privilege level access controls for data accesses
The ARM architecture memory attributes can define that a memory region is:
•
not accessible to any accesses
•
accessible only to privileged accesses
•
accessible to privileged and unprivileged accesses.

Note
In an ARMv6-M implementation that does not include the Unprivileged/Privileged Extension, accesses are
always privileged.
Not all combinations of memory attributes for reads and writes are supported by all systems that define the
memory attributes.

A3.6.2

Privilege level access controls for instruction accesses
The ARM architecture memory attributes can define that a region of memory is:
•
not accessible for execution, meaning prefetching from addresses in the region must not occur
•
accessible for execution by privileged processes only
•
accessible for execution by privileged and unprivileged processes.

Note
In an ARMv6-M implementation that does not include the Unprivileged/Privileged Extension, accesses are
always privileged.
A memory region is described, independently, as being:
•
accessible for reads by a privileged read access, or by privileged and unprivileged read access
•
suitable for execution.

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This means there is a linkage between the memory attributes that define the accessibility to explicit memory
accesses, and those that define whether a region can be executed.
If execution is attempted from any memory location that the attributes prohibit, an instruction execution
error occurs.

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A3.7

Memory access order
The memory types defined in Memory types and attributes and the memory order model on page A3-48
have associated memory ordering rules to provide system compatibility for software between different
implementations. The rules are defined to accommodate the increasing difficulty of ensuring linkage
between the completion of memory accesses and the execution of instructions within a complex
high-performance system, while also enabling simple systems and implementations to meet the criteria with
predictable behavior.
The memory order model determines:
•
when side effects are guaranteed to be visible
•
the requirements for memory consistency.
Shareable memory indicating whether a region of memory is shared between multiple processors, and
therefore requires an appearance of cache transparency in an ordering model, is supported. Implementations
remain free to choose the mechanisms to implement this functionality.
Additional attributes and behaviors relate to the memory system architecture. These features are defined in
other areas of this manual, see Access rights on page A3-56 and Table B3-1 on page B3-259 for information
about access permissions and the system memory map respectively.
More information about the memory order model is given in the following subsections:
•
Reads and writes
•
Ordering requirements for memory accesses on page A3-60
•
Memory barriers on page A3-61.

A3.7.1

Reads and writes
Memory accesses are either reads or writes.

Reads
Reads are defined as memory operations that have the semantics of a load. For ARMv6-M and Thumb these
are:
LDR{S}B, LDR{S}H, LDR
•
•
LDM, POP

Writes
Writes are defined as operations that have the semantics of a store. For ARMv6-M and Thumb these are:
STRB, STRH, STR
•
•
STM, PUSH

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Memory synchronization primitives
Synchronization primitives are required to ensure correct operation of system semaphores within the
memory order model.
Synchronization primitive instructions are not supported in ARMv6-M. To implement atomic semaphores,
system software must provide the necessary access guarantees, for example by disabling interrupts or
executing an appropriate kernel handler.

Observability and completion
The concept of observability applies to all memory, however, the concept of global observability only
applies to Shareable memory. Normal, Device and Strongly-ordered memory are defined in Memory types
and attributes and the memory order model on page A3-48.
For all memory:
•

a write to a location in memory is said to be observed by an observer when a subsequent read of the
location by the same observer returns the value written by the write

•

a write to a location in memory is said to be globally observed for a shareability domain when a
subsequent read of the location by any observer within that shareability domain that is capable of
observing the write returns the value written by the write

•

a read of a location in memory is said to be observed by an observer when a subsequent write to the
location by the same observer has no effect on the value returned by the read

•

a read of a location in memory is said to be globally observed for a shareability domain when a
subsequent write to the location by any observer within that shareability domain that is capable of
observing the write has no effect on the value returned by the read.

Additionally, for Strongly-ordered memory:
•

A read or write to a memory mapped location in a peripheral that exhibits side-effects is said to be
observed, and globally observed, only when the read or write:
—

meets the general conditions listed

—

can begin to affect the state of the memory-mapped peripheral

—

can trigger all associated side effects, whether they affect other peripheral devices, processors,
or memory.

For all memory, a read or write is defined to be complete when it is globally observed:
•

A branch predictor maintenance operation is defined to be complete when the effects of operation are
globally observed.

To determine when any side effects have completed, it is necessary to poll a location associated with the
device, for example, a status register.

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ARM Architecture Memory Model

Side effect completion in Strongly-ordered and Device memory
For all memory-mapped peripherals, where the side-effects of a peripheral are required to be visible to the
entire system, the peripheral must provide an IMPLEMENTATION DEFINED location that can be read to
determine when all side effects are complete.
This is a key element of the architected memory order model.

A3.7.2

Ordering requirements for memory accesses
ARMv6-M defines access restrictions in the memory ordering permitted, depending on the memory
attributes of the accesses involved. Figure A3-6 shows the memory ordering between two explicit accesses
A1 and A2, where A1, as listed in the first column, occurs before A2, as listed in the first row, in program
order.
The symbols used in Figure A3-6 are as follows:
<

Accesses must be globally observed in program order, that is, A1 must be globally observed
strictly before A2.

(blank)

Accesses can be globally observed in any order, provided that the requirements of
uniprocessor semantics, for example respecting dependencies between instructions within a
single processor, are maintained.
Normal
access

Non-shareable

Shareable

Stronglyordered
access

Normal access

Device access, Non-shareable

Device access, Shareable

Strongly-ordered access

A2
A1

Device access

Figure A3-6 Memory ordering restrictions
There are no ordering requirements for implicit accesses to any type of memory.

Program order for instruction execution
Program order of instruction execution is the order of the instructions in the control flow trace. Explicit
memory accesses in an execution can be either:
Strictly Ordered
Denoted by <. Must occur strictly in order.
Ordered
Denoted by <=. Must occur either in order, or simultaneously.

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Multiple load and store instructions, such as LDM, POP, STM, and PUSH generate multiple word accesses, each
of which is a separate access for the purpose of determining ordering.
The rules for determining program order for two accesses A1 and A2 are:
If A1 and A2 are generated by two different instructions:
•

A1 < A2 if the instruction that generates A1 occurs before the instruction that generates A2 in
program order

•

A2 < A1 if the instruction that generates A2 occurs before the instruction that generates A1 in
program order.

If A1 and A2 are generated by the same instruction:
•

•

A3.7.3

If A1 and A2 are two word loads generated by an LDM or POP instruction, or two word stores generated
by an STM or PUSH instruction, excluding LDM or POP instructions whose register list includes the PC:
—

A1 <= A2 if the address of A1 is less than the address of A2

—

A2 <= A1 if the address of A2 is less than the address of A1.

If A1 and A2 are two word loads generated by an LDM or POP instruction whose register list includes
the PC, the program order of the memory operations is not defined.

Memory barriers
Memory barrier is the general term applied to an instruction, or sequence of instructions, used to force
synchronization events by a processor with respect to retiring load or store instructions. A memory barrier
is used to guarantee completion of preceding load or store instructions to the programmers’ model, flushing
of any prefetched instructions prior to the event, or both. ARMv6-M includes three explicit barrier
instructions to support the memory order model.
•
DMB, see Data Memory Barrier (DMB) on page A3-62
•
DSB, see Data Synchronization Barrier (DSB) on page A3-62
•
ISB, see Instruction Synchronization Barrier (ISB) on page A3-62.
Memory barriers affect explicit reads and writes to the memory system generated by load and store
instructions being executed in the processor. Reads and writes generated by DMA transactions and
instruction fetches are not explicit accesses.

Note
For information on barriers and correctness for system configuration in the M-profile, see Barrier support
for system correctness on page B2-255.

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ARM Architecture Memory Model

Data Memory Barrier (DMB)
The DMB instruction is a data memory barrier. DMB exhibits the following behavior:
•

All explicit memory accesses by instructions occurring in program order before this instruction are
globally observed before any explicit memory accesses because of instructions occurring in program
order after this instruction are observed.

•

The DMB instruction has no effect on the ordering of other instructions executing on the processor.

As such, DMB ensures the apparent order of the explicit memory operations before and after the instruction,
without ensuring their completion. For details on the DMB instruction, see DMB on page A6-133.

Data Synchronization Barrier (DSB)
The DSB instruction operation acts as a special kind of DMB. The DSB operation completes when all explicit
memory accesses before this instruction complete.
In addition, no instruction subsequent to the DSB can execute until the DSB completes. For details on the DSB
instruction, see DSB on page A6-134.

Instruction Synchronization Barrier (ISB)
The ISB instruction flushes the pipeline in the processor, so that all instructions following the pipeline flush
are fetched from memory after the instruction has been completed. It ensures that the effects of context
altering operations, such as branch predictor maintenance operations, in addition to all changes to the
special-purpose registers where applicable, executed before the ISB instruction are visible to the instructions
fetched after the ISB. See The special-purpose CONTROL register on page B1-215 for more information.
In addition, the ISB instruction ensures that any branches that appear in program order after the ISB are
always written into the branch prediction logic with the context that is visible after the ISB. This is required
to ensure correct execution of the instruction stream.
Any context altering operations appearing in program order after the ISB only take effect after the ISB has
been executed. This is because of the behavior of the context altering instructions.
ARM implementations are free to choose how far ahead of the current point of execution they prefetch
instructions; either a fixed or a dynamically varying number of instructions. In addition to being free to
choose how many instructions to prefetch, an ARM implementation can choose the possible future
execution path to prefetch along. For example, after a branch instruction, it can choose to prefetch either the
instruction following the branch or the instruction at the branch target. This is known as branch prediction.
A potential problem with all forms of instruction prefetching is that the instruction in memory can be
changed after it was prefetched but before it is executed. If this happens, the modification to the instruction
in memory does not normally prevent the already prefetched copy of the instruction from executing to
completion. Use the ISB and memory barrier instructions, DMB or DSB as appropriate, to force execution
ordering where necessary.
For details on the ISB instruction, see ISB on page A6-136.

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A3.8

Caches and memory hierarchy
Support for caches in ARMv6-M is limited to memory attributes.These can be exported on a supporting bus
protocol such as AMBA AHB or AMBA AXI to support system caches.
In situations where a breakdown in coherency can occur, software must manage the caches using cache
maintenance operations that are memory mapped and IMPLEMENTATION DEFINED.

A3.8.1

Introduction to caches
A cache is a block of high-speed memory locations containing both address information and the associated
data. The purpose is to increase the average speed of a memory access. Caches operate on two principles of
locality:
Spatial locality

an access to one location is likely to be followed by accesses from adjacent
locations, for example sequential instruction execution or usage of a data structure

Temporal locality

an access to an area of memory is likely to be repeated within a short time period,
for example execution of a code loop.

To minimize the quantity of control information stored, the spatial locality property is used to group several
locations together under the same TAG. This logical block is commonly known as a cache line. When data
is loaded into a cache, access times for subsequent loads and stores are reduced, resulting in overall
performance benefits. An access to information already in a cache is known as a cache hit, and other
accesses are called cache misses.
Normally, caches are self-managing, with the updates occurring automatically. Whenever the processor
wants to access a cacheable location, the cache is checked. If the access is a cache hit, the access occurs
immediately, otherwise a location is allocated and the cache line loaded from memory. Different cache
topologies and access policies are possible, however they must comply with the memory coherency model
of the underlying architecture.
Caches introduce a number of potential problems, mainly because of:
•
memory accesses occurring at times other than when the programmer would normally expect them
•
the existence of multiple physical locations where a data item can be held.

A3.8.2

Implication of caches to the application programmer
Caches are largely invisible to the application programmer, but can become visible because of a breakdown
in coherency. Such a breakdown can occur when:
•
memory locations are updated by other agents in the systems
•
memory updates made from the application code must be made visible to other agents in the system.
For example:
In systems with a DMA that reads memory locations that are held in the data cache of a processor, a
breakdown of coherency occurs when the processor has written new data in the data cache, but the DMA
reads the old data held in memory.

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In a Harvard architecture of caches, a breakdown of coherency occurs when new instruction data has been
written into the data cache or to memory, but the instruction cache still contains the old instruction data.

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The ARMv6-M Instruction Set

This chapter describes the ARMv6-M Thumb instruction set. It contains the following sections:
•
About the instruction set on page A4-66
•
Unified Assembler Language on page A4-68
•
Branch instructions on page A4-70
•
Data-processing instructions on page A4-71
•
Status register access instructions on page A4-74
•
Load and store instructions on page A4-75
•
Load Multiple and Store Multiple instructions on page A4-77
•
Miscellaneous instructions on page A4-78
•
Exception-generating instructions on page A4-79.

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A4.1

About the instruction set
ARMv6-M supports the Thumb instruction set including a small number of 32-bit instructions introduced
with Thumb-2 technology, see 32-bit Thumb instruction encoding on page A5-91. The 16-bit instruction
support is equivalent to the Thumb instruction set support in ARMv6 prior to the introduction of Thumb-2
technology. This chapter describes the functionality available in the ARMv6-M Thumb instruction set, and
the UAL that can be assembled to either the Thumb or ARM instruction sets.
Thumb instructions are either 16-bit or 32-bit, and are aligned on a two-byte boundary. 16-bit and 32-bit
instructions can be intermixed freely. However:
•

Most 16-bit instructions can only access eight of the general purpose registers, R0-R7. These are
known as the low registers.

•

A small number of 16-bit instructions can access the high registers, R8-R15.

The ARM and Thumb instruction sets are designed to interwork freely. Because ARMv6-M only supports
Thumb instructions, interworking instructions in ARMv6-M must only reference Thumb state execution,
see ARMv6-M and interworking support for more details.
In addition, see:
•
Chapter A5 The Thumb Instruction Set Encoding for encoding details of the Thumb instruction set
•
Chapter A6 Thumb Instruction Details for detailed descriptions of the instructions.

A4.1.1

ARMv6-M and interworking support
Thumb interworking is held as bit [0] of an interworking address. Interworking addresses are used in the
following instructions: BX, BLX, or POP that loads the PC.
ARMv6-M only supports the Thumb instruction execution state, therefore the value of address bit [0] must
be 1 in interworking instructions, otherwise a fault occurs. All instructions ignore bit [0] and write bits
[31:1]:’0’ when updating the PC.
16-bit instructions that update the PC behave as follows:
•

ADD (register) and MOV (register) branch within Thumb state without interworking

Note
The use of Rd as the PC in the ADD (SP plus register) 16-bit instruction is deprecated.
•

B, or the B instruction, branches without interworking

•

BLX (register) and BX interwork on the value in Rm

•

POP interworks on the value loaded to the PC

•

BKPT and SVC cause exceptions and are not considered to be interworking instructions.

For more details, see the description of the BXWritePC() function in Pseudocode details of ARM core register
operations on page A2-36.

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The 32-bit BL instruction branches to Thumb state based on the instruction encoding and is not based on bit
[0] of the value written to the PC. It is the only 32-bit instruction in ARMv6-M that updates the PC.

A4.1.2

Conditional execution
Conditionally executed means that the instruction only has its normal effect on the programmers’ model
operation and memory if the N, Z, C and V flags in the APSR satisfy a condition specified in the instruction.
If the flags do not satisfy this condition, the instruction acts as a NOP, that is, execution advances to the next
instruction as normal, including any relevant checks for exceptions being taken, but has no other effect.
Conditional execution in ARMv6-M can only be achieved using a 16-bit conditional branch instruction,
with a branch range of –256 to +254 bytes. See B on page A6-119 for details.
See Conditional execution on page A6-99 for more information about conditional execution.

Note
The Thumb instruction set in other architecture variants supports additional conditional execution
capabilities:
•
a 32-bit conditional branch with a larger branch range
•
a Compare and Branch on Zero and a Compare and Branch on Nonzero instructions,
•
an If-Then (IT) instruction.
These instructions are not supported in ARMv6-M.

A4.1.3

Permanently UNDEFINED encodings
All versions of the ARM architecture define some encodings as permanently UNDEFINED. That is,
permanently UNDEFINED encodings are defined in the 16-bit and 32-bit Thumb encodings. From issue C of
this manual, ARM defines an assembler mnemonic for these instructions, see UDF on page A6-193.

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The ARMv6-M Instruction Set

A4.2

Unified Assembler Language
This document uses the ARM UAL. This assembly language syntax provides a canonical form for all ARM
and Thumb instructions. ARM Limited recommends the use of UAL for flexibility and maximum
portability across all ARM architecture variants.
UAL describes the syntax for the mnemonic and the operands of each instruction. In addition, it assumes
that instructions and data items can be given labels. It does not specify the syntax to be used for labels, nor
what assembler directives and options are available. See your assembler documentation for these details.

Note
Most earlier Thumb assembly language mnemonics are not supported. See Appendix D Legacy Instruction
Mnemonics for details.
UAL includes instruction selection rules that specify the instruction encoding that is selected when more
than one can provide the required functionality.
Syntax options exist to ensure that a particular encoding is selected. These are useful when disassembling
code, to ensure that subsequent assembly produces the original code, and in some other situations.
ARMv6-M only supports a single width of instruction for any given mnemonic. This makes the selection
syntax valid but less relevant in the ARMv6-M case. The selection syntax might be useful for code sharing
cases with other architecture variants.

A4.2.1

Use of labels in UAL instruction syntax
The UAL syntax for some instructions includes the label of an instruction or a literal data item that is at a
fixed offset from the instruction being specified. The assembler must:
1.

Calculate the PC or Align(PC,4) value of the instruction. The PC value of an instruction is its address
plus 4 for a Thumb instruction, or plus 8 for an ARM instruction. The Align(PC,4) value of an
instruction is its PC value ANDed with 0xFFFFFFFC to force it to be word-aligned. There is no
difference between the PC and Align(PC,4) values for an ARM instruction, but there can be for a
Thumb instruction.

Calculate the offset from the PC or Align(PC,4) value of the instruction to the address of the labelled
instruction or literal data item.

Assemble a PC-relative encoding of the instruction, that is, one that reads its PC or Align(PC,4) value
and adds the calculated offset to form the required address.

Note
For instructions that encode a subtraction operation, if the instruction cannot encode the calculated
offset, but can encode minus the calculated offset, the instruction encoding specifies a subtraction of
minus the calculated offset.

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The syntax of the following instructions includes a label:
•

B and BL. The assembler syntax for these instructions always specifies the label of the instruction that
they branch to. Their encodings specify a sign-extended immediate offset that is added to the PC value

of the instruction to form the target address of the branch.
•

The assembler syntax of the LDR instruction can specify the label of a literal data item that is to be
loaded. The encoding of the instruction specifies a zero-extended immediate offset that is added to
the Align(PC,4) value of the instruction to form the address of the data item.

•

ADR. The assembler syntax for this instruction can specify the label of an instruction or literal data

item whose address is to be calculated. Its encoding specifies a zero-extended immediate offset that
is added to the Align(PC,4) value of the instruction to form the address of the data item.

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The ARMv6-M Instruction Set

A4.3

Branch instructions
Table A4-1 summarizes the branch instructions supported in the ARMv6-M Thumb instruction set.
Table A4-1 Branch instructions
Instruction

Usage

Range

B on page A6-119

Branch to target address

+/–2KB

BL on page A6-123

Call a subroutine

+/–16MB

BLX (register) on page A6-124

Call a subroutinea

Any

BX on page A6-125

Branch to target addressa

Any

a. In ARMv6-M, the interworking address must maintain Thumb
execution state, otherwise a fault occurs.

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A4.4

Data-processing instructions
Core data-processing instructions belong to one of the following groups:

A4.4.1

•

Standard data-processing instructions. This group perform basic data-processing operations, and
share a common format with some variations.

•

Shift instructions on page A4-72.

•

Multiply instructions on page A4-73.

•

Packing and unpacking instructions on page A4-73.

•

Miscellaneous data-processing instructions on page A4-73.

Standard data-processing instructions
These instructions generally have a destination register Rd, a first operand register Rn, and a second operand
Rm.
In addition to placing a result in the destination register, most of these instructions set the condition code
flags, according to the result of the operation. If an instruction does not set a flag, the existing value of that
flag, from a previous instruction, is preserved.
Table A4-2 summarizes the main data-processing instructions in the Thumb instruction set. The instructions
are classified and described as applicable in two sections in Chapter A6 Thumb Instruction Details, one
section for each of the following:
INSTRUCTION (immediate) where the second operand is a modified immediate constant.
•
INSTRUCTION (register) where the second operand is a register, or a register shifted by a constant.
•
Table A4-2 Standard data-processing instructions

Mnemonic

Instruction

Notes

ADC

Add with Carry

ADD

Add

ARMv6-M provides register and small immediate versions only.

ADR

Form PC-relative Address

First operand is the PC. Second operand is an immediate constant.

AND

Bitwise AND

BIC

Bitwise Bit Clear

CMN

Compare Negative

Sets flags. Like ADD but with no destination register.

CMP

Compare

Sets flags. Like SUB but with no destination register.

EOR

Bitwise Exclusive OR

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Table A4-2 Standard data-processing instructions (continued)
Mnemonic

Instruction

Notes

MOV

Copies operand to destination

Has only one operand. Constant support is limited to loading an
8-bit immediate value in ARMv6-M. If the operand is a shifted
register, the instruction is an LSL, LSR, ASR, or ROR instruction
instead. See Shift instructions for details.

MVN

Bitwise NOT

Has only one operand. ARMv6-M does not support any immediate
or shift options.

ORR

Bitwise OR

RSB

Reverse Subtract

Subtracts first operand from second operand. ARMv6-M only
supports an immediate value of 0.

SBC

Subtract with Carry

SUB

Subtract

TST

Test

Sets flags. Like AND but with no destination register.

A4.4.2

Shift instructions
Table A4-3 lists the shift instructions in the Thumb instruction set.
Table A4-3 Shift instructions
Instructiona

See

Arithmetic Shift Right

ASR (immediate) on page A6-117

Arithmetic Shift Right

ASR (register) on page A6-118

Logical Shift Left

LSL (immediate) on page A6-150

Logical Shift Left

LSL (register) on page A6-151

Logical Shift Right

LSR (immediate) on page A6-152

Logical Shift Right

LSR (register) on page A6-153

Rotate Right

ROR (register) on page A6-171

a. ARMv6-M does not support RRX, Rotate Right with Extend.

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A4.4.3

Multiply instructions
The only multiply instruction supported in ARMv6-M performs a 32x32 multiply that generates a 32-bit
result, see MUL on page A6-159. The instruction can operate on signed or unsigned quantities.

A4.4.4

Packing and unpacking instructions
Table A4-4 lists the packing and upacking instructions in the Thumb instruction set.
Table A4-4 Packing and unpacking instructions

A4.4.5

Instruction

See

Operation

Signed Extend Byte

SXTB on page A6-190

Extend 8 bits to 32

Signed Extend Halfword

SXTH on page A6-191

Extend 16 bits to 32

Unsigned Extend Byte

UXTB on page A6-195

Extend 8 bits to 32

Unsigned Extend Halfword

UXTH on page A6-196

Extend 16 bits to 32

Miscellaneous data-processing instructions
Table A4-5 lists the miscellaneous data-processing instructions in the Thumb instruction set. Immediate
values in these instructions are simple binary numbers.
Table A4-5 Miscellaneous data-processing instructions

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Instruction

See

Notes

Byte-Reverse Word

REV on page A6-168

Byte-Reverse Packed Halfword

REV16 on page A6-169

Byte-Reverse Signed Halfword

REVSH on page A6-170

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The ARMv6-M Instruction Set

A4.5

Status register access instructions
The MRS and MSR instructions move the contents of the Application Program Status Register, APSR, to or
from a general-purpose register.
The APSR is described in The Application Program Status Register on page A2-38.
The condition flags in the APSR are normally set by executing data-processing instructions, and are
normally used to control the execution of conditional branch instructions. However, you can set the flags
explicitly using the MSR instruction, and you can read the current state of the flags explicitly using the MRS
instruction.
For details of the system level use of status register access instructions, see Chapter B4 ARMv6-M System
Instructions.

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A4.6

Load and store instructions
Table A4-6 summarizes the general-purpose register load and store instructions in the Thumb instruction
set. See also Load Multiple and Store Multiple instructions on page A4-77.
Load and store instructions have several options for addressing memory. See Addressing modes on
page A4-76 for more information.
Table A4-6 Load and store instructions

A4.6.1

Data type

Load

Store

32-bit word

LDR

STR

16-bit halfword

STRH

16-bit unsigned halfword

LDRH

16-bit signed halfword

LDRSH

8-bit byte

STRB

8-bit unsigned byte

LDRB

8-bit signed byte

LDRSB

Halfword and byte loads and stores
Halfword and byte stores store the least significant halfword or byte from the register, to 16 or 8 bits of
memory respectively. There is no distinction between signed and unsigned stores.
Halfword and byte loads load 16 or 8 bits from memory into the least significant halfword or byte of a
register. Unsigned loads zero-extend the loaded value to 32 bits, and signed loads sign-extend the value to
32 bits.

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The ARMv6-M Instruction Set

A4.6.2

Addressing modes
The address for a load or store is formed from two parts: a value from a base register, and an offset.
In ARMv6-M, the base register is one of the R0-R7, SP or PC general-purpose registers.
For loads, the base register can be the PC. This permits PC-relative addressing for position-independent
code. Instructions marked (literal) in their title in Chapter A6 Thumb Instruction Details are PC-relative
loads.
In ARMv6-M, the address offset takes one of two formats:
Immediate

The offset is an unsigned number that can be added to or subtracted from the base
register value. Immediate offset addressing is useful for accessing data elements
that are a fixed distance from the start of the data object, such as structure fields,
stack offsets and input/output registers.

The offset is a value from a general-purpose register. This register cannot be the PC.
The value can be added to, or subtracted from, the base register value. Register
offsets are useful for accessing arrays or blocks of data.

For more information on address mode support in ARMv6-M, see Memory accesses on page A6-103.

Note
Support for one or both formats and the range of permitted immediate values is instruction encoding
dependent. See Chapter A6 Thumb Instruction Details for full details for each instruction.

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A4.7

Load Multiple and Store Multiple instructions
Load Multiple instructions load a subset of the general-purpose registers from memory.
Store Multiple instructions store a subset of the general-purpose registers to memory.
The memory locations are consecutive word-aligned words. The addresses used are obtained from a base
register, and are either above or below the value in the base register. The base register can be updated by the
total size of the data transferred. See the appropriate instruction behavior for exact details.
Table A4-7 summarizes the ARMv6-M Thumb Load Multiple and Store Multiple instructions.
Table A4-7 Load Multiple and Store Multiple instructions
Instruction

Description

Load Multiple, Increment After or Full Descending

LDM, LDMIA, LDMFD on page A6-137

Pop multiple registers off the stack

POP on page A6-165

Push multiple registers onto the stack a

PUSH on page A6-167

Store Multiple, Increment After or Empty Ascending

STM, STMIA, STMEA on page A6-175

a. This instruction decrements the base register before the memory access and updates the base register.

A4.7.1

Loads to the PC
The POP instruction can be used to load a value into the PC. The value loaded is treated as an interworking
address, as described by the LoadWritePC() pseudocode function in Pseudocode details of ARM core register
operations on page A2-36.

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The ARMv6-M Instruction Set

A4.8

Miscellaneous instructions
Table A4-8 summarizes the miscellaneous instructions in the ARMv6-M Thumb instruction set.
Table A4-8 Miscellaneous instructions

A4-78

Instruction

See

Data Memory Barrier

DMB on page A6-133

Data Synchronization Barrier

DSB on page A6-134

Instruction Synchronization Barrier

ISB on page A6-136

No Operation

NOP on page A6-163

Send Event

SEV on page A6-174

Supervisor Call

SVC on page A6-189

Wait for Event

WFE on page A6-197

Wait for Interrupt

WFI on page A6-198

Yield

YIELD on page A6-199

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The ARMv6-M Instruction Set

A4.9

Exception-generating instructions
The following instructions are intended specifically to cause a processor exception to occur:
•

The Supervisor Call SVC, formerly SWI, instruction is used to cause an SVCall exception to occur. This
is the main mechanism in the ARM architecture for unprivileged code to make calls to privileged
Operating System code. See ARMv6-M exception model on page B1-218 for details.

Note
In an ARMv6-M implementation that does not include the Unprivileged/Privileged Extension,
execution is always privileged. However in such an implementation, application code might use
supervisor calls to maintain a software hierarchy with a system kernel.
•

ARM DDI 0419C
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The Breakpoint (BKPT) instruction provides for software breakpoints. It can cause a running system
to halt depending on the debug configuration. See Debug event behavior on page C1-324 for more
details.

A4-79

The ARMv6-M Instruction Set

A4-80

ARM DDI 0419C
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Chapter A5
The Thumb Instruction Set Encoding

This chapter describes how the Thumb instruction set uses the ARM programmers’ model. It contains the
following sections:
•
Thumb instruction set encoding on page A5-82
•
16-bit Thumb instruction encoding on page A5-84
•
32-bit Thumb instruction encoding on page A5-91.

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A5-81

The Thumb Instruction Set Encoding

A5.1

Thumb instruction set encoding
The Thumb instruction stream is a sequence of halfword-aligned halfwords. Each Thumb instruction is
either a single 16-bit halfword in that stream, or a 32-bit instruction consisting of two consecutive halfwords
in that stream.
If bits [15:11] of the halfword being decoded take any of the following values, the halfword is the first
halfword of a 32-bit instruction:
0b11101
•
•
0b11110
•
0b11111.
Otherwise, the halfword is a 16-bit instruction.
See 16-bit Thumb instruction encoding on page A5-84 for details of the encoding of 16-bit Thumb
instructions.
See 32-bit Thumb instruction encoding on page A5-91 for details of the encoding of 32-bit Thumb
instructions.

A5.1.1

UNDEFINED and UNPREDICTABLE instruction set space
An attempt to execute an unallocated instruction results in either:
•
Unpredictable behavior. The instruction is described as UNPREDICTABLE.
•
An Undefined Instruction exception. The instruction is described as UNDEFINED.
An instruction is UNDEFINED if it is declared as UNDEFINED in an instruction description, or in this chapter.
An instruction is UNPREDICTABLE if:
•
a bit marked (0) or (1) in the encoding diagram of an instruction is not 0 or 1 respectively, and the
pseudocode for that encoding does not indicate that a different special case applies
•
it is declared as UNPREDICTABLE in an instruction description or in this chapter.
Unless otherwise specified, Thumb instructions present in other architecture variants are UNDEFINED in
ARMv6-M.

A5.1.2

Use of 0b1111 as a register specifier
The use of 0b1111 as a register specifier is not normally permitted in Thumb instructions. When a value of
0b1111 is permitted, a variety of meanings is possible. For register reads, these meanings are:

A5-82

•

Read the PC value, that is, the address of the current instruction + 4. Some instructions read the PC
value implicitly, without the use of a register specifier, for example the conditional branch instruction
B.

•

Read the word-aligned PC value, that is, the address of the current instruction + 4, with bits [1:0]
forced to zero. This enables instructions such as ADR and LDR (literal) instructions to use PC-relative
data addressing. The register specifier is implicit in the ARMv6-M encodings of these instructions.

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The Thumb Instruction Set Encoding

For register writes, these meanings are:
•

The PC can be specified as the destination register of an instruction. Thumb interworking defines
whether bit [0] of the address is ignored or determines the instruction execution state. If it selects the
execution state after the branch, bit [0] must have the value 1.
Instructions can write the PC either implicitly, for example, B, or by using a register mask
rather than a register specifier (POP). The address to branch to can be a loaded value such as POP, a
register value, such as BX, or the result of a calculation, such as ADD.

•

A5.1.3

Discard the result of a calculation. This is done in some cases when one instruction is a special case
of another, more general instruction, but with the result discarded. In these cases, the instructions are
listed on separate pages, with a special case in the pseudocode for the more general instruction
cross-referencing the other page. This use does not apply to ARMv6-M encodings.

Use of 0b1101 as a register specifier
R13 is defined in the Thumb instruction set so that its use is primarily as a stack pointer, aligning R13 with
the ARM Architecture Procedure Call Standard (AAPCS), the architecture usage model supported by the
PUSH and POP instructions.

R13<1:0> definition
Bits [1:0] of R13 are treated as Should Be Zero or Preserved (SBZP). Writing a non-zero value to bits [1:0]
results in UNPREDICTABLE behavior. Reading bits [1:0] returns zero.

R13 instruction support
R13 instruction support in ARMv6-M is restricted to the following:
•

R13 as the source or destination register of a MOV (register) instruction:
MOV
MOV

•

SP,Rm
Rd,SP

Adjusting R13 up or down by a multiple of its alignment:
SUB (SP minus immediate)
ADD (SP plus immediate)
ADD (SP plus register)

// where Rm is a multiple of 4

•

R13 as the first operand in an ADD (SP plus register) where Rd is not the SP.

•

R13 as the first operand in a CMP (register) instruction. CMP can be useful for stack checking.

•

R13 as the address in a POP or PUSH instruction.

The restrictions affect:
•
the high register form of ADD (register) and CMP (register), where the use of R13 as is deprecated
•
the ADD (SP plus register) where Rd == 13 and Rm is not word-aligned.

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A5-83

The Thumb Instruction Set Encoding

A5.2

16-bit Thumb instruction encoding
The encoding of 16-bit Thumb instructions is:
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
opcode

Table A5-1 shows the allocation of 16-bit instruction encodings.
Table A5-1 16-bit Thumb instruction encoding

A5-84

opcode

Instruction or instruction class

00xxxx

Shift (immediate), add, subtract, move, and compare on page A5-85

010000

Data processing on page A5-86

010001

Special data instructions and branch and exchange on page A5-87

01001x

Load from Literal Pool, see LDR (literal) on page A6-141

0101xx
011xxx
100xxx

Load/store single data item on page A5-88

10100x

Generate PC-relative address, see ADR on page A6-115

10101x

Generate SP-relative address, see ADD (SP plus immediate) on page A6-111

1011xx

Miscellaneous 16-bit instructions on page A5-89

11000x

Store multiple registers, see STM, STMIA, STMEA on page A6-175

11001x

Load multiple registers, see LDM, LDMIA, LDMFD on page A6-137

1101xx

Conditional branch, and Supervisor Call on page A5-90

11100x

Unconditional Branch, see B on page A6-119

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The Thumb Instruction Set Encoding

A5.2.1

Shift (immediate), add, subtract, move, and compare
The encoding of Shift (immediate), add, subtract, move, and compare instructions is:
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0
opcode

Table A5-2 shows the allocation of encodings in this space.
Table A5-2 16-bit Thumb encoding
opcode

Instruction

See

000xx

Logical Shift Left a

LSL (immediate) on page A6-150

001xx

Logical Shift Right

LSR (immediate) on page A6-152

010xx

Arithmetic Shift Right

ASR (immediate) on page A6-117

01100

Add register

ADD (register) on page A6-109

01101

Subtract register

SUB (register) on page A6-187

01110

Add 3-bit immediate

ADD (immediate) on page A6-107

01111

Subtract 3-bit immediate

SUB (immediate) on page A6-185

100xx

Move

MOV (immediate) on page A6-154

101xx

Compare

CMP (immediate) on page A6-127

110xx

Add 8-bit immediate

ADD (immediate) on page A6-107

111xx

Subtract 8-bit immediate

SUB (immediate) on page A6-185

a. When opcode is 0b00000, and bits[8:6] are 0b000, this encoding is MOV
(register), see MOV (register) on page A6-155.

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A5-85

The Thumb Instruction Set Encoding

A5.2.2

Data processing
The encoding of data processing instructions is:
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 1 0 0 0 0
opcode

Table A5-3 shows the allocation of encodings in this space.
Table A5-3 16-bit Thumb data processing instructions

A5-86

opcode

Instruction

See

0000

Bitwise AND

AND (register) on page A6-116

0001

Exclusive OR

EOR (register) on page A6-135

0010

Logical Shift Left

LSL (register) on page A6-151

0011

Logical Shift Right

LSR (register) on page A6-153

0100

Arithmetic Shift Right

ASR (register) on page A6-118

0101

Add with Carry

ADC (register) on page A6-106

0110

Subtract with Carry

SBC (register) on page A6-173

0111

Rotate Right

ROR (register) on page A6-171

1000

Set flags on bitwise AND

TST (register) on page A6-192

1001

Reverse Subtract from 0

RSB (immediate) on page A6-172

1010

Compare Registers

CMP (register) on page A6-129

1011

Compare Negative

CMN (register) on page A6-126

1100

Logical OR

ORR (register) on page A6-164

1101

Multiply Two Registers

MUL on page A6-159

1110

Bit Clear

BIC (register) on page A6-121

1111

Bitwise NOT

MVN (register) on page A6-161

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The Thumb Instruction Set Encoding

A5.2.3

Special data instructions and branch and exchange
The encoding of special data instructions, and branch and exchange instructions, is:
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 1 0 0 0 1
opcode

Table A5-4 shows the allocation of encodings in this space.
Table A5-4 Special data instructions and branch and exchange

ARM DDI 0419C
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opcode

Instruction

See

00xx

Add Registers

ADD (register) on page A6-109

0100

UNPREDICTABLE

0101
011x

Compare Registers

CMP (register) on page A6-129

10xx

Move Registers

MOV (register) on page A6-155

110x

Branch and Exchange

BX on page A6-125

111x

Branch with Link and Exchange

BLX (register) on page A6-124

A5-87

The Thumb Instruction Set Encoding

A5.2.4

Load/store single data item
The encoding of Load/store single data item instructions is:
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
opA
opB

These instructions have one of the following values in opA:
0b0101
•
•
0b011x
•
0b100x.
Table A5-5 shows the allocation of encodings in this space.
Table A5-5 16-bit Thumb Load and store instructions

A5-88

opA

opB

Instruction

See

0101

000

Store Register

STR (register) on page A6-179

0101

001

Store Register Halfword

STRH (register) on page A6-183

0101

010

Store Register Byte

STRB (register) on page A6-181

0101

011

Load Register Signed Byte

LDRSB (register) on page A6-148

0101

100

Load Register

LDR (register) on page A6-143

0101

101

Load Register Halfword

LDRH (register) on page A6-147

0101

110

Load Register Byte

LDRB (register) on page A6-145

0101

111

Load Register Signed Halfword

LDRSH (register) on page A6-149

0110

0xx

Store Register

STR (immediate) on page A6-177

0110

1xx

Load Register

LDR (immediate) on page A6-139

0111

0xx

Store Register Byte

STRB (immediate) on page A6-180

0111

1xx

Load Register Byte

LDRB (immediate) on page A6-144

1000

0xx

Store Register Halfword

STRH (immediate) on page A6-182

1000

1xx

Load Register Halfword

LDRH (immediate) on page A6-146

1001

0xx

Store Register SP relative

STR (immediate) on page A6-177

1001

1xx

Load Register SP relative

LDR (immediate) on page A6-139

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The Thumb Instruction Set Encoding

A5.2.5

Miscellaneous 16-bit instructions
The encoding of miscellaneous 16-bit instructions is:
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 0 1 1
opcode

Table A5-6 shows the allocation of encodings in this space. Other encodings in this space are UNDEFINED.
Table A5-6 Miscellaneous 16-bit instructions

ARM DDI 0419C
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opcode

Instruction

See

00000xx

Add Immediate to SP

ADD (SP plus immediate) on page A6-111

00001xx

Subtract Immediate from SP

SUB (SP minus immediate) on page A6-188

001000x

Signed Extend Halfword

SXTH on page A6-191

001001x

Signed Extend Byte

SXTB on page A6-190

001010x

Unsigned Extend Halfword

UXTH on page A6-196

001011x

Unsigned Extend Byte

UXTB on page A6-195

010xxxx

Push Multiple Registers

PUSH on page A6-167

0110011

Change Processor State

CPS on page B4-306

101000x

Byte-Reverse Word

REV on page A6-168

101001x

Byte-Reverse Packed Halfword

REV16 on page A6-169

101011x

Byte-Reverse Signed Halfword

REVSH on page A6-170

110xxxx

Pop Multiple Registers

POP on page A6-165

1110xxx

Breakpoint

BKPT on page A6-122

1111xxx

Hints

Hint instructions on page A5-90

A5-89

The Thumb Instruction Set Encoding

Hint instructions
The encoding of hint instructions is:
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 0 1 1 1 1 1 1
opA
opB

Table A5-7 shows the allocation of encodings in this space.
Other encodings in this space are unallocated hints. They execute as NOPs, but software must not use them.
Table A5-7 Hint instructions
opA

opB

Instruction

See

xxxx

not 0000

UNDEFINEDa

0000

No Operation hint

NOP on page A6-163

0001

0000

Yield hint

YIELD on page A6-199

0010

0000

Wait for Event hint

WFE on page A6-197

0011

0000

Wait for Interrupt hint

WFI on page A6-198

0100

0000

Send Event hint

SEV on page A6-174

a. The If-Then (IT) instruction is not supported in ARMv6-M. The
encoding space is UNDEFINED.

A5.2.6

Conditional branch, and Supervisor Call
The encoding of 16-bit Thumb conditional branch and Supervisor Call instructions is:
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 0 1
opcode

Table A5-8 shows the allocation of encodings in this space.
Table A5-8 Conditional branch and Supervisor Call instructions
opcode

Instruction

See

not 111x

Conditional branch

B on page A6-119

1110

Permanently UNDEFINED

UDF on page A6-193a

1111

Supervisor Call

SVC on page A6-189

a. Issue C of this manual first defines an assembler mnemonic for these encodings

A5-90

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The Thumb Instruction Set Encoding

A5.3

32-bit Thumb instruction encoding
The encoding of 32-bit Thumb instructions is:
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 op1
op

For 32-bit Thumb encoding, op1 != 0b00. If op1 == 0b00, a 16-bit instruction is encoded, see 16-bit Thumb
instruction encoding on page A5-84.
Table A5-9 shows the allocation of ARMv6-M Thumb encodings in this space.
Table A5-9 32-bit Thumb encoding

A5.3.1

op1

Instruction class

UNDEFINED

See Branch and miscellaneous control

UNDEFINED

Branch and miscellaneous control
The encoding of branch and miscellaneous control instructions is:
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 0
op1
1
op2

Table A5-10 shows the allocation of encodings in this space. Other encodings in this space are UNDEFINED.
Table A5-10 Branch and miscellaneous control instructions
op2

op1

Instruction

See

0x0

011100x

Move to Special Register

MSR (register) on page B4-310

0x0

0111011

Miscellaneous control instructions on page A5-92

0x0

011111x

Move from Special Register

MRS on page B4-308

010

1111111

Permanently UNDEFINED

UDF on page A6-193

1x1

Branch with Link

BL on page A6-123

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A5-91

The Thumb Instruction Set Encoding

Miscellaneous control instructions
The encoding of miscellaneous control instructions is:
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 0 0 1 1 1 0 1 1
1 0
0
op

Table A5-11 shows the allocation of encodings in this space. Other encodings in this space are UNDEFINED
in ARMv6-M.
Table A5-11 Miscellaneous control instructions

A5-92

Instruction

See

0100

Data Synchronization Barrier

DSB on page A6-134

0101

Data Memory Barrier

DMB on page A6-133

0110

Instruction Synchronization Barrier

ISB on page A6-136

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Chapter A6
Thumb Instruction Details

This chapter describes each instruction in the ARMv6-M Thumb instruction set. It contains the following
sections:
•
Format of instruction descriptions on page A6-94
•
Standard assembler syntax fields on page A6-98
•
Conditional execution on page A6-99
•
Shifts applied to a register on page A6-101
•
Memory accesses on page A6-103
•
Hint Instructions on page A6-104
•
Alphabetical list of ARMv6-M Thumb instructions on page A6-105.

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A6-93

Thumb Instruction Details

A6.1

Format of instruction descriptions
The instruction descriptions in the alphabetical lists of instructions in Alphabetical list of ARMv6-M Thumb
instructions on page A6-105 normally use the following format:
•
instruction section title
•
introduction to the instruction
•
instruction encoding(s) with architecture information
•
assembler syntax
•
pseudocode describing how the instruction operates
•
exception information
•
notes, where applicable.
Each of these items is described in more detail in the following subsections.
A few instruction descriptions describe alternative mnemonics for other instructions and use an abbreviated
and modified version of this format.

A6.1.1

Instruction section title
The instruction section title gives the base mnemonic for the instructions described in the section. When one
mnemonic has multiple forms described in separate instruction sections, this is followed by a short
description of the form in parentheses. The most common use of this is to distinguish between forms of an
instruction in which one of the operands is an immediate value and forms in which it is a register.
Parenthesized text is also used to document the former mnemonic in some cases where a mnemonic has been
replaced entirely by another mnemonic in the new assembler syntax.

A6.1.2

Introduction to the instruction
The instruction section title is followed by text that briefly describes the main features of the instruction.
This description is not necessarily complete and is not definitive. If there is any conflict between it and the
more detailed information that follows, the latter takes priority.

A6.1.3

Instruction encodings
The Encodings subsection contains a list of one or more instruction encodings. For reference purposes, each
Thumb instruction encoding is labelled, T1, T2, T3...
Each instruction encoding description consists of:
•

A6-94

Information about which architecture variants include the particular encoding of the instruction.
Thumb instructions present since ARMv4T are labelled as all versions of the Thumb instruction set,
otherwise:
—

ARMv5T* means all variants of ARM Architecture version 5 that include Thumb instruction
support.

—

ARMv6-M means a Thumb-only variant of the ARM architecture microcontroller profile that
is compatible with ARMv6 Thumb support prior to the introduction of Thumb-2 technology.
Copyright © 2007-2008, 2010 ARM Limited. All rights reserved.
Non-Confidential

ARM DDI 0419C
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Thumb Instruction Details

—

ARMv7-M means a Thumb-only variant of the ARM architecture microcontroller profile that
provides enhanced performance and functionality compared to ARMv6-M, through the use of
Thumb-2 technology and additional system features such as fault handling support.

Note
This manual does not provide architecture variant information about non-M profile variants of
ARMv6 and ARMv7. For such information, see the ARM Architecture Reference Manual, ARMv7-A
and ARMv7-R edition.
•

An assembly syntax that ensures that the assembler selects the encoding in preference to any other
encoding. In some cases, multiple syntaxes are given. The correct one to use is sometimes indicated
by annotations to the syntax. In other cases, the correct one to use can be determined by looking at
the assembler syntax description and using it to determine which syntax corresponds to the
instruction being disassembled.
There can be more than one syntax that ensures re-assembly to any particular encoding, and the exact
set of syntaxes that do so usually depends on the register numbers, immediate constants and other
operands to the instruction.
The assembly syntax documented for the encoding is chosen to be the simplest one that ensures
selection of that encoding for all operand combinations supported by that encoding.
The assembly syntax given for an encoding is therefore a suitable one for a disassembler to
disassemble that encoding to. However, disassemblers might want to use simpler syntaxes when they
are suitable for the operand combination, to produce more readable disassembled code.

A6.1.4

•

An encoding diagram. This is half-width for 16-bit Thumb encodings and full-width for 32-bit
Thumb encodings. The 32-bit Thumb encodings use a double vertical line between the two halfwords
to act as a reminder that 32-bit Thumb encodings use the byte order of a sequence of two halfwords
rather than of a word, as described in Instruction alignment and byte ordering on page A3-46.

•

Encoding-specific pseudocode. This is pseudocode that translates the encoding-specific instruction
fields into inputs to the encoding-independent pseudocode in the later Operation subsection, and that
picks out any special cases in the encoding. For a detailed description of the pseudocode used and of
the relationship between the encoding diagram, the encoding-specific pseudocode and the
encoding-independent pseudocode, see Appendix E Pseudocode Definition.

Assembler syntax
The Assembly syntax subsection describes the standard UAL syntax for the instruction.
Each syntax description consists of the following elements:
•

ARM DDI 0419C
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One or more syntax prototype lines written in a typewriter font, using the conventions described in
Assembler syntax prototype line conventions on page A6-96. Each prototype line documents the
mnemonic and, where appropriate, operand parts of a full line of assembler code. When there is more
than one such line, each prototype line is annotated to indicate required results of the
encoding-specific pseudocode. For each instruction encoding, this information can be used to
determine whether any instructions matching that encoding are available when assembling that
syntax, and if so, which ones.
Copyright © 2007-2008, 2010 ARM Limited. All rights reserved.
Non-Confidential

A6-95

Thumb Instruction Details

•

The line where: followed by descriptions of all of the variable or optional fields of the prototype
syntax line.
Some syntax fields are standardized across all or most instructions. These fields are described in
Standard assembler syntax fields on page A6-98.
By default, syntax fields that specify registers, such as , , or , are permitted to be any of
R0-R12 or LR in Thumb instructions. These require that the encoding-specific pseudocode sets the
corresponding integer variable, such as d, n, or t, to the corresponding register number, that is, 0-12
for R0-R12, or 14 for LR. This can normally be done by setting the corresponding bitfield in the
instruction, named Rd, Rn, Rt..., to the binary encoding of that number. In the case of 16-bit Thumb
encodings, this bitfield is normally of length 3 and so the encoding is only available when one of
R0-R7 was specified in the assembler syntax. It is also common for such encodings to use a bitfield
name such as Rdn. This indicates that the encoding is only available if and specify the same
register, and that the register number of that register is encoded in the bitfield if they do.
The description of a syntax field that specifies a register sometimes extends or restricts the permitted
range of registers or documents other differences from the default rules for such fields. Typical
extensions are to permit the use of one or both of the SP and the PC, using register numbers 13 and
15 respectively.

Note
The pre-UAL Thumb assembler syntax is incompatible with UAL and is not documented in the instruction
sections, see Appendix D Legacy Instruction Mnemonics.

Assembler syntax prototype line conventions
The following conventions are used in assembler syntax prototype lines and their subfields:
< >

Any item bracketed by < and > is a short description of a type of value to be supplied by the
user in that position. A longer description of the item is normally supplied by subsequent
text. Such items often correspond to a similarly named field in an encoding diagram for an
instruction. When the correspondence requires the binary encoding of an integer value or
register number to be substituted into the instruction encoding, it is not described explicitly.
For example, if the assembler syntax for a Thumb instruction contains an item and the
instruction encoding diagram contains a 4-bit field named Rn, the number of the register
specified in the assembler syntax is encoded in binary in the instruction field.
If the correspondence between the assembler syntax item and the instruction encoding is
more complex than simple binary encoding of an integer or register number, the item
description indicates how it is encoded. This is often done by specifying a required output
from the encoding-specific pseudocode, such as add = TRUE. The assembler must only use
encodings that produce that output.

{ }

Any item bracketed by { and } is optional. A description of the item and of how its presence
or absence is encoded in the instruction is normally supplied by subsequent text.
Many instructions have an optional destination register. Unless otherwise stated, if such a
destination register is omitted, it is the same as the immediately following source register in
the instruction syntax.

A6-96

ARM DDI 0419C
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Thumb Instruction Details

spaces

Single spaces are used for clarity, to separate items. When a space is obligatory in the
assembler syntax, two or more consecutive spaces are used.

+/-

This indicates an optional + or - sign. If neither is coded, + is assumed.

All other characters must be encoded precisely as they appear in the assembler syntax. Apart from { and },
the special characters described here do not appear in the basic forms of assembler instructions documented
in this manual. The { and } characters must be encoded in a few places as part of a variable item. When this
happens, the description of the variable item indicates how they must be used.

A6.1.5

Pseudocode describing how the instruction operates
The Operation subsection contains encoding-independent pseudocode that describes the main operation of
the instruction. For a detailed description of the pseudocode used and of the relationship between the
encoding diagram, the encoding-specific pseudocode and the encoding-independent pseudocode, see
Appendix E Pseudocode Definition.

A6.1.6

Exception information
The Exceptions subsection contains a list of the exceptional conditions that can be caused by execution of
the instruction.
Processor exceptions are listed as follows:
•

Resets and interrupts, including NMI, PendSV and SysTick, are not listed. They can occur before or
after the execution of any instruction, and in some cases during the execution of an instruction, but
they are not in general caused by the instruction concerned.

•

HardFault exceptions are listed for all instructions that perform explicit data memory accesses.
All instruction fetches can cause HardFault exceptions. These are not caused by execution of the
instruction and so are not listed.

•

HardFault exceptions can occur for the following reasons and are listed in the appropriate
instructions:
—
Thumb interworking information that indicates a change of execution state
—
execution of a BKPT instruction where the Debug Extension is not supported or enabled.
HardFault exceptions also occur when pseudocode indicates that the instruction is UNDEFINED. These
exceptions are not listed.

•

The SVCall exception is listed for the SVC instruction.

Note
For a summary of the different types of HardFault exceptions see Fault behavior on page B1-236.

A6.1.7

Notes
Where appropriate, additional notes about the instruction appear under additional subheadings.

ARM DDI 0419C
ID092410

A6-97

Thumb Instruction Details

A6.2

Standard assembler syntax fields
The following assembler syntax fields are standard across all or most instructions:

Is an optional field. It specifies the condition under which the instruction is executed. If
is omitted, it defaults to always (AL). For details see Conditional execution on page A4-67.

Note
B is the only conditional instruction supported in ARMv6-M. Instances of shown in
other instructions must be omitted or defined as AL and their corresponding pseudocode
function ConditionPassed() in the operation section always returns TRUE.

Specifies optional assembler qualifiers on the instruction. The following qualifiers are
defined:
.N

Meaning narrow, specifies that the assembler must select a 16-bit encoding for
the instruction. If this is not possible, an assembler error is produced.

Meaning wide, specifies that the assembler must select a 32-bit encoding for the
instruction. If this is not possible, an assembler error is produced.

If neither .W nor .N is specified, the assembler can select either 16-bit or 32-bit encodings.
If both are available, it must select a 16-bit encoding. In a few cases, more than one encoding
of the same length can be available for an instruction. The rules for selecting between such
encodings are instruction-specific and are part of the instruction description.

Note
With the exception of UDF, ARMv6-M only supports either 16-bit encodings or 32-bit
encodings for a given instruction. The .N and .W qualifiers are optional and produce
assembler errors if incorrectly used.

A6-98

ARM DDI 0419C
ID092410

Thumb Instruction Details

A6.3

Conditional execution
In Thumb instructions, the condition, if it is not AL, is normally encoded in a preceding IT instruction.
However, ARMv6-M does not support the IT instruction. This means that:
•
the suffix must be omitted or AL in all instruction mnemonics except B
•
in the pseudocode in this manual:
—
any reference to InITBlock() returns FALSE
—
any reference to LastInITBlock() returns FALSE.
In ARMv6-M, the B instruction can be executed conditionally, based on the values of the APSR condition
flags. Table A6-1 shows the available conditions, and associated encodings of the 4-bit cond field, for this
instruction.
Table A6-1 Condition codes
cond

Mnemonic extension

Meaning

Condition flags

0000

Equal

Z == 1

0001

Not equal

Z == 0

0010

CS a

Carry set

C == 1

0011

CC b

Carry clear

C == 0

0100

Minus, negative

N == 1

0101

Plus, positive or zero

N == 0

0110

Overflow

V == 1

0111

No overflow

V == 0

1000

Unsigned higher

C == 1 and Z == 0

1001

Unsigned lower or same

C == 0 or Z == 1

1010

Signed greater than or equal

N == V

1011

Signed less than

N != V

1100

Signed greater than

Z == 0 and N == V

1101

Signed less than or equal

Z == 1 or N != V

1110c

None (AL) d

Always (unconditional)

Any

a.
b.
c.
d.

ARM DDI 0419C
ID092410

HS (unsigned higher or same) is a synonym for CS.
LO (unsigned lower) is a synonym for CC.

This value is never encoded in any ARMv6-M Thumb instruction.
AL is an optional mnemonic extension for always.

A6-99

Thumb Instruction Details

A6.3.1

Pseudocode details of conditional execution
The CurrentCond() pseudocode function has prototype:
bits(4) CurrentCond()

and returns the 4-bit cond field of the encoding for the Branch instruction. See B on page A6-119 for more
information.
The ConditionPassed() function uses this condition specifier and the APSR condition flags to determine
whether the instruction must be executed:
// ConditionPassed()
// =================
boolean ConditionPassed()
cond = CurrentCond();
// Evaluate base condition.
case cond<3:1> of
when '000' result = (APSR.Z
when '001' result = (APSR.C
when '010' result = (APSR.N
when '011' result = (APSR.V
when '100' result = (APSR.C
when '101' result = (APSR.N
when '110' result = (APSR.N
when '111' result = TRUE;

==
==
==
==
==
==
==

'1');
'1');
'1');
'1');
'1') && (APSR.Z == '0');
APSR.V);
APSR.V) && (APSR.Z == '0');

//
//
//
//
//
//
//
//

EQ
CS
MI
VS
HI
GE
GT
AL

or
or
or
or
or
or
or

NE
CC
PL
VC
LS
LT
LE

// Condition flag values in the set '111x' indicate the instruction is always executed.
// Otherwise, invert condition if necessary.
if cond<0> == '1' && cond != '1111' then
result = !result;
return result;

A6-100

ARM DDI 0419C
ID092410

Thumb Instruction Details

A6.4

Shifts applied to a register
Shifts only apply to the ASR, LSL, LSR, and ROR data-processing instructions in ARMv6-M. Other instructions
are declared with shift type SRType_LSL and a shift value of zero where shift operations are supported by
additional encodings in other architecture variants.

A6.4.1

Shift operations
// DecodeImmShift()
// ================
(SRType, integer) DecodeImmShift(bits(2) type, bits(5) imm5)
case type of
when '00'
shift_t = SRType_LSL; shift_n = UInt(imm5);
when '01'
shift_t = SRType_LSR; shift_n = if imm5 == '00000' then 32 else UInt(imm5);
when '10'
shift_t = SRType_ASR; shift_n = if imm5 == '00000' then 32 else UInt(imm5);
when '11'
if imm5 == '00000' then
shift_t = SRType_RRX; shift_n = 1;
else
shift_t = SRType_ROR; shift_n = UInt(imm5);
return (shift_t, shift_n);
// DecodeRegShift()
// ================
SRType DecodeRegShift(bits(2) type)
case type of
when '00' shift_t = SRType_LSL;
when '01' shift_t = SRType_LSR;
when '10' shift_t = SRType_ASR;
when '11' shift_t = SRType_ROR;
return shift_t;
// Shift()
// =======
bits(N) Shift(bits(N) value, SRType type, integer amount, bit carry_in)
(result, -) = Shift_C(value, type, amount, carry_in);
return result;
// Shift_C()
// =========
(bits(N), bit) Shift_C(bits(N) value, SRType type, integer amount, bit carry_in)
assert !(type == SRType_RRX && amount != 1);
if amount == 0 then

ARM DDI 0419C
ID092410

A6-101

Thumb Instruction Details

(result, carry_out) = (value, carry_in);
else
case type of
when SRType_LSL
(result, carry_out)
when SRType_LSR
(result, carry_out)
when SRType_ASR
(result, carry_out)
when SRType_ROR
(result, carry_out)
when SRType_RRX
(result, carry_out)

= LSL_C(value, amount);
= LSR_C(value, amount);
= ASR_C(value, amount);
= ROR_C(value, amount);
= RRX_C(value, carry_in);

return (result, carry_out);

A6-102

ARM DDI 0419C
ID092410

Thumb Instruction Details

A6.5

Memory accesses
The following addressing mode is commonly permitted in ARMv6-M for memory access instructions:
Offset addressing
The offset value is added to or subtracted from an address obtained from the base register.
The result is used as the address for the memory access. The base register is unaltered.
The assembly language syntax for this mode is:
[,]
is the base register and can be:

•
•

an immediate constant, such as or
an index register, .

For information about unaligned access and endianness, see:
•
Alignment support on page A3-43
•
Endian support on page A3-44.
ARMv6-M does not support exclusive access to memory, see Synchronization and semaphores on
page A3-47.

ARM DDI 0419C
ID092410

A6-103

Thumb Instruction Details

A6.6

Hint Instructions
Two classes of hint instruction exist within the Thumb instruction set:
•
memory hints
•
NOP-compatible hints.
Only 16-bit versions of the NOP-compatible hints are supported in ARMv6-M. For information on the
16-bit encodings see Hint instructions on page A5-90.

A6-104

ARM DDI 0419C
ID092410

Thumb Instruction Details

A6.7

Alphabetical list of ARMv6-M Thumb instructions
Every ARMv6-M Thumb instruction is listed in this section. See Format of instruction descriptions on
page A6-94 for details of the format used.

ARM DDI 0419C
ID092410

A6-105

Thumb Instruction Details

A6.7.1

ADC (register)
Add with Carry (register) adds a register value, the carry flag value, and an optionally-shifted register value,
and writes the result to the destination register. It updates the condition flags based on the result.
Encoding T1

All versions of the Thumb instruction set.

ADCS ,

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 1 0 0 0 0 0 1 0 1
Rm
Rdn
d = UInt(Rdn); n = UInt(Rdn); m = UInt(Rm);
(shift_t, shift_n) = (SRType_LSL, 0);

setflags = !InITBlock();

Assembler syntax
ADCS{} {,} ,

where:
S

The instruction updates the flags.

{}

See Standard assembler syntax fields on page A6-98.

The destination register. If is omitted, this register is the same as .

The register that contains the first operand.

The register that is optionally shifted and used as the second operand.

Operation
if ConditionPassed() then
EncodingSpecificOperations();
shifted = Shift(R[m], shift_t, shift_n, APSR.C);
(result, carry, overflow) = AddWithCarry(R[n], shifted, APSR.C);
R[d] = result;
if setflags then
APSR.N = result<31>;
APSR.Z = IsZeroBit(result);
APSR.C = carry;
APSR.V = overflow;

Exceptions
None.

A6-106

ARM DDI 0419C
ID092410

Thumb Instruction Details

A6.7.2

ADD (immediate)
This instruction adds an immediate value to a register value, and writes the result to the destination register.
It updates the condition flags based on the result.
Encoding T1

All versions of the Thumb instruction set.

ADDS ,,#

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 1 1 1 0 imm3
Rn
Rd
d = UInt(Rd);

n = UInt(Rn);

Encoding T2

setflags = !InITBlock();

imm32 = ZeroExtend(imm3, 32);

All versions of the Thumb instruction set.

ADDS ,#

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 1 1 0
Rdn
imm8
d = UInt(Rdn);

n = UInt(Rdn);

setflags = !InITBlock();

imm32 = ZeroExtend(imm8, 32);

Assembler syntax
ADDS{} {,} , #

All encodings permitted

where:
S

The instruction updates the flags.

{}

See Standard assembler syntax fields on page A6-98.

The destination register. If is omitted, this register is the same as .

The register that contains the first operand. If the SP is specified for , see ADD (SP plus
immediate) on page A6-111. If the PC is specified for , see ADR on page A6-115.

The immediate value to be added to the value obtained from . The range of permitted
values is 0-7 for encoding T1, and 0-255 for encoding T2.
Encoding T1 is preferred to encoding T2 if is specified and encoding T2 is preferred to
encoding T1 if is omitted.

ARM DDI 0419C
ID092410

A6-107

Thumb Instruction Details

Operation
if ConditionPassed() then
EncodingSpecificOperations();
(result, carry, overflow) = AddWithCarry(R[n], imm32, '0');
R[d] = result;
if setflags then
APSR.N = result<31>;
APSR.Z = IsZeroBit(result);
APSR.C = carry;
APSR.V = overflow;

Exceptions
None.

A6-108

ARM DDI 0419C
ID092410

Thumb Instruction Details

A6.7.3

ADD (register)
This instruction adds a register value and an optionally-shifted register value, and writes the result to the
destination register. Encoding T1 updates the condition flags based on the result.
Encoding T1

All versions of the Thumb instruction set.

ADDS ,,

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 1 1 0 0
Rm
Rn
Rd
d = UInt(Rd); n = UInt(Rn); m = UInt(Rm);
(shift_t, shift_n) = (SRType_LSL, 0);

Encoding T2

setflags = !InITBlock();

All versions of the Thumb instruction set.

ADD ,

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 1 0 0 0 1 0 0
Rm
Rdn
DN
if (DN:Rdn) == '1101' || Rm == '1101' then SEE ADD (SP plus register);
d = UInt(DN:Rdn); n = d; m = UInt(Rm); setflags = FALSE; (shift_t, shift_n) = (SRType_LSL, 0);
if n == 15 && m == 15 then UNPREDICTABLE;
if d == 15 && InITBlock() && !LastInITBlock() then UNPREDICTABLE;

Assembler syntax
ADD{S}{}

{,} ,

where:
S

If present, specifies that the instruction updates the flags. Otherwise, the instruction does not
update the flags.

{}

See Standard assembler syntax fields on page A6-98.

The destination register. If is omitted, this register is the same as and encoding T2
is preferred to encoding T1 if both are available. If is specified, encoding T1 is
preferred to encoding T2. If R is not the PC, the PC can be used in encoding T2.

The register that contains the first operand. If the SP is specified for , see ADD (SP plus
register) on page A6-113. If R is not the PC, the PC can be used in encoding T2.

The register that is used as the second operand. The PC can be used in encoding T2.

ARM DDI 0419C
ID092410

A6-109

Thumb Instruction Details

Operation
if ConditionPassed() then
EncodingSpecificOperations();
shifted = Shift(R[m], shift_t, shift_n, APSR.C);
(result, carry, overflow) = AddWithCarry(R[n], shifted, '0');
if d == 15 then
ALUWritePC(result); // setflags is always FALSE here
else
R[d] = result;
if setflags then
APSR.N = result<31>;
APSR.Z = IsZeroBit(result);
APSR.C = carry;
APSR.V = overflow;

Exceptions
None.

A6-110

ARM DDI 0419C
ID092410

Thumb Instruction Details

A6.7.4

ADD (SP plus immediate)
This instruction adds an immediate value to the SP value, and writes the result to the destination register.
Encoding T1

All versions of the Thumb instruction set.

ADD ,SP,#

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 0 1 0 1
Rd
imm8
d = UInt(Rd);

setflags = FALSE;

Encoding T2

imm32 = ZeroExtend(imm8:’00’, 32);

All versions of the Thumb instruction set.

ADD SP,SP,#

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 0 1 1 0 0 0 0 0
imm7
d = 13;

setflags = FALSE;

imm32 = ZeroExtend(imm7:’00’, 32);

Assembler syntax
ADD{}

{,} SP, #

where:
{}

See Standard assembler syntax fields on page A6-98.

The destination register. If is omitted, this register is SP.

The immediate value to be added to the value obtained from . Permitted values are
multiples of 4 in the range 0-1020 for encoding T1and multiples of 4 in the range 0-508 for
encoding T2.

ARM DDI 0419C
ID092410

A6-111

Thumb Instruction Details

Operation
if ConditionPassed() then
EncodingSpecificOperations();
(result, carry, overflow) = AddWithCarry(SP, imm32, '0');
R[d] = result;
// no flag setting form of the instruction supported

Exceptions
None.

A6-112

ARM DDI 0419C
ID092410

Thumb Instruction Details

A6.7.5

ADD (SP plus register)
This instruction adds a register value to the SP value, and writes the result to the destination register.
Encoding T1

All versions of the Thumb instruction set.

ADD , SP,

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 1 0 0 0 1 0 0
1 1 0 1 Rdm
DM
d = UInt(DM:Rdm); m = UInt(DM:Rdm); setflags = FALSE;
if d == 15 && InITBlock() && !LastInITBlock() then UNPREDICTABLE;
(shift_t, shift_n) = (SRType_LSL, 0);

Encoding T2

All versions of the Thumb instruction set.

ADD SP,

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 1 0 0 0 1 0 0 1
Rm
1 0 1
if Rm == ‘1101’ then SEE encoding T1;
d = 13; m = UInt(Rm); setflags = FALSE;
(shift_t, shift_n) = (SRType_LSL, 0);

Assembler syntax
ADD{}

{,} SP,

where:
{}

See Standard assembler syntax fields on page A6-98.

The destination register. If is omitted, this register is SP.

The register that is used as the second operand. This register can be the SP, but such
instructions are deprecated and the instruction can only be ADD SP,SP,SP.

ARM DDI 0419C
ID092410

A6-113

Thumb Instruction Details

Operation
if ConditionPassed() then
EncodingSpecificOperations();
shifted = Shift(R[m], shift_t, shift_n, APSR.C);
(result, carry, overflow) = AddWithCarry(SP, shifted, '0');
if d == 15 then
ALUWritePC(result);
else
R[d] = result;
// no flag setting form of the instruction supported

Exceptions
None.

A6-114

ARM DDI 0419C
ID092410

Thumb Instruction Details

A6.7.6

ADR
Address to Register adds an immediate value to the PC value, and writes the result to the destination register.
Encoding T1
ADR

All versions of the Thumb instruction set.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 0 1 0 0
Rd
imm8
d = UInt(Rd);

imm32 = ZeroExtend(imm8:’00’, 32);

add = TRUE;

Assembler syntax
ADR{}

ADD{}

, PC, #

Normal syntax
Alternative syntax

where:
{}

See Standard assembler syntax fields on page A6-98.

The destination register.

The label of an instruction or literal data item whose address is to be loaded into . The
assembler calculates the required value of the offset from the Align(PC,4) value of the ADR
instruction to this label.
Only a positive value is permitted with imm32 equal to the offset. Permitted values of the
offset are multiples of four in the range 0 to 1020 for encoding T1.

In the alternative syntax forms:

The offset value for the ADD form. Permitted values are multiples of four in the range 0 to
1020 for encoding T1.

Note
It is recommended that the alternative syntax form is avoided where possible.

Operation
if ConditionPassed() then
EncodingSpecificOperations();
result = if add then (Align(PC,4) + imm32) else (Align(PC,4) - imm32);
R[d] = result;

Exceptions
None.

ARM DDI 0419C
ID092410

A6-115

Thumb Instruction Details

A6.7.7

AND (register)
This instruction performs a bitwise AND of a register value and an optionally-shifted register value, and
writes the result to the destination register. It updates the condition flags based on the result.
Encoding T1
ANDS

All versions of the Thumb instruction set.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 1 0 0 0 0 0 0 0 0
Rm
Rdn
d = UInt(Rdn); n = UInt(Rdn); m = UInt(Rm);
(shift_t, shift_n) = (SRType_LSL, 0);

setflags = !InITBlock();

Assembler syntax
ANDS{}

{,} ,

where:
S

The instruction updates the flags.

{}

See Standard assembler syntax fields on page A6-98.

The destination register. If is omitted, this register is the same as .

The register that contains the first operand.

The register that is used as the second operand.

Operation
if ConditionPassed() then
EncodingSpecificOperations();
(shifted, carry) = Shift_C(R[m], shift_t, shift_n, APSR.C);
result = R[n] AND shifted;
R[d] = result;
if setflags then
APSR.N = result<31>;
APSR.Z = IsZeroBit(result);
APSR.C = carry;
// APSR.V unchanged

Exceptions
None.

A6-116

ARM DDI 0419C
ID092410

Thumb Instruction Details

A6.7.8

ASR (immediate)
Arithmetic Shift Right (immediate) shifts a register value right by an immediate number of bits, shifting in
copies of its sign bit, and writes the result to the destination register. It updates the condition flags based on
the result.
Encoding T1
ASRS

All versions of the Thumb instruction set.

,,#

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 1 0
imm5
Rm
Rd
d = UInt(Rd); m = UInt(Rm); setflags = !InITBlock();
(-, shift_n) = DecodeImmShift('10', imm5);

Assembler syntax
ASRS{}

, , #

where:
S

The instruction updates the flags.

{}

See Standard assembler syntax fields on page A6-98.

The destination register.

The register that contains the first operand.

The shift amount, in the range 1 to 32. See Shifts applied to a register on page A6-101.

Operation
if ConditionPassed() then
EncodingSpecificOperations();
(result, carry) = Shift_C(R[m], SRType_ASR, shift_n, APSR.C);
R[d] = result;
if setflags then
APSR.N = result<31>;
APSR.Z = IsZeroBit(result);
APSR.C = carry;
// APSR.V unchanged

Exceptions
None.

ARM DDI 0419C
ID092410

A6-117

Thumb Instruction Details

A6.7.9

ASR (register)
Arithmetic Shift Right (register) shifts a register value right by a variable number of bits, shifting in copies
of its sign bit, and writes the result to the destination register. The variable number of bits is read from the
bottom byte of a register. It updates the condition flags based on the result.
Encoding T1
ASRS

All versions of the Thumb instruction set.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 1 0 0 0 0 0 1 0 0
Rm
Rdn
d = UInt(Rdn);

n = UInt(Rdn);

m = UInt(Rm);

setflags = !InITBlock();

Assembler syntax
ASRS{}

, ,

where:
S

The instruction updates the flags.

{}

See Standard assembler syntax fields on page A6-98.

The destination register.

The register that contains the first operand.

The register whose bottom byte contains the amount to shift by.

Operation
if ConditionPassed() then
EncodingSpecificOperations();
shift_n = UInt(R[m]<7:0>);
(result, carry) = Shift_C(R[n], SRType_ASR, shift_n, APSR.C);
R[d] = result;
if setflags then
APSR.N = result<31>;
APSR.Z = IsZeroBit(result);
APSR.C = carry;
// APSR.V unchanged

Exceptions
None.

A6-118

ARM DDI 0419C
ID092410

Thumb Instruction Details

A6.7.10 B
Branch causes a branch to a target address.
Encoding T1
B

All versions of the Thumb instruction set.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 0 1
cond
imm8
if cond == '1110' then UNDEFINED;
if cond == '1111' then SEE SVC;
imm32 = SignExtend(imm8:'0', 32);
if InITBlock() then UNPREDICTABLE;

Encoding T2

All versions of the Thumb instruction set.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 0 0
imm11
imm32 = SignExtend(imm11:'0', 32);
if InITBlock() && !LastInITBlock() then UNPREDICTABLE;

Assembler syntax
B{}{}

where:
{}

See Standard assembler syntax fields on page A6-98.

Note
•
•
•

Encoding T1 is conditional.
For encoding T1, must not be AL or omitted.
For ARMv6-M, for encoding T2, must be AL or omitted.

The label of the instruction that is to be branched to. The assembler calculates the required
value of the offset from the PC value of the B instruction to this label, then selects an
encoding that sets imm32 to that offset.
Permitted offsets are even numbers in the range -256 to 254 for encoding T1 and -2048 to
2046 for encoding T2.

ARM DDI 0419C
ID092410

A6-119

Thumb Instruction Details

Operation
if ConditionPassed() then
EncodingSpecificOperations();
BranchWritePC(PC + imm32);

Exceptions
None.

A6-120

ARM DDI 0419C
ID092410

Thumb Instruction Details

A6.7.11 BIC (register)
Bit Clear (register) performs a bitwise AND of a register value and the complement of an optionally-shifted
register value, and writes the result to the destination register. It updates the condition flags based on the
result.
Encoding T1
BICS

All versions of the Thumb instruction set.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 1 0 0 0 0 1 1 1 0
Rm
Rdn
d = UInt(Rdn); n = UInt(Rdn); m = UInt(Rm);
(shift_t, shift_n) = (SRType_LSL, 0);

setflags = !InITBlock();

Assembler syntax
BICS{}

{,} ,

where:
S

The instruction updates the flags.

{}

See Standard assembler syntax fields on page A6-98.

The destination register. If is omitted, this register is the same as .

The register that contains the first operand.

The register that is used as the second operand.

Operation
if ConditionPassed() then
EncodingSpecificOperations();
(shifted, carry) = Shift_C(R[m], shift_t, shift_n, APSR.C);
result = R[n] AND NOT(shifted);
R[d] = result;
if setflags then
APSR.N = result<31>;
APSR.Z = IsZeroBit(result);
APSR.C = carry;
// APSR.V unchanged

Exceptions
None.

ARM DDI 0419C
ID092410

A6-121

Thumb Instruction Details

A6.7.12 BKPT
Breakpoint causes a HardFault exception or a debug halt to occur depending on the presence and
configuration of the debug support.
Encoding T1
BKPT

ARMv5T*, ARMv6-M, ARMv7-M

M profile specific behavior

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 0 1 1 1 1 1 0
imm8
imm32 = ZeroExtend(imm8, 32);
// imm32 is for assembly/disassembly only and is ignored by hardware.

Assembler syntax
BKPT{}

{#}

where:
{}

See Standard assembler syntax fields on page A6-98.

Specifies an 8-bit value that is stored in the instruction. This value is ignored by the ARM
hardware, but can be used by a debugger to store additional information about the
breakpoint.

Operation
EncodingSpecificOperations();
BKPTInstrDebugEvent();

Exceptions
HardFault.

A6-122

ARM DDI 0419C
ID092410

Thumb Instruction Details

A6.7.13 BL
Branch with Link (immediate) calls a subroutine at a PC-relative address.
Encoding T1
BL

All versions of the Thumb instruction set.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 0 S
imm10
1 1 J1 1 J2
imm11
I1 = NOT(J1 EOR S); I2 = NOT(J2 EOR S); imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);
if InITBlock() && !LastInITBlock() then UNPREDICTABLE;

Assembler syntax
BL{}

where:
{}

See Standard assembler syntax fields on page A6-98.

The label of the instruction that is to be branched to.
The assembler calculates the required value of the offset from the PC value of the BL
instruction to this label, then selects an encoding that sets imm32 to that offset. Permitted
offsets are even numbers in the range -16777216 to 16777214.

Operation
if ConditionPassed() then
EncodingSpecificOperations();
next_instr_addr = PC;
LR = next_instr_addr<31:1> : '1';
BranchWritePC(PC + imm32);

Exceptions
None.

Note
Before the introduction of Thumb-2 technology, J1 and J2 in encodings T1 and T2 were both 1, resulting in
a smaller branch range. The instructions could be executed as two separate 16-bit instructions, with the first
instruction instr1 setting LR to PC + SignExtend(instr1<10:0>:'000000000000', 32) and the second
instruction completing the operation. It is no longer possible to split the BL instruction into two 16-bit
instructions in ARMv6T2, ARMv6-M and ARMv7.

ARM DDI 0419C
ID092410

A6-123

Thumb Instruction Details

A6.7.14 BLX (register)
Branch with Link and Exchange calls a subroutine at an address and instruction set specified by a register.
ARMv6-M only supports Thumb execution. An attempt to change the instruction execution state causes an
exception on the instruction at the target address.
Encoding T1
BLX

ARMv5T*, ARMv6-M, ARMv7-M

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 1 0 0 0 1 1 1 1
Rm
(0) (0) (0)
m = UInt(Rm);
if m == 15 then UNPREDICTABLE;
if InITBlock() && !LastInITBlock() then UNPREDICTABLE;

Assembler syntax
BLX{}

where:
{}

See Standard assembler syntax fields on page A6-98.

The register that contains the branch target address and instruction set selection bit.

Operation
if ConditionPassed() then
EncodingSpecificOperations();
target = R[m];
next_instr_addr = PC - 2;
LR = next_instr_addr<31:1> : '1';
BLXWritePC(target);

Exceptions
HardFault.

A6-124

ARM DDI 0419C
ID092410

Thumb Instruction Details

A6.7.15 BX
Branch and Exchange causes a branch to an address and instruction set specified by a register. ARMv6-M
only supports Thumb execution. An attempt to change the instruction execution state causes an exception
on the instruction at the target address.
BX can also be used for an exception return, see Exception return behavior on page B1-227.

Encoding T1
BX

All versions of the Thumb instruction set.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 1 0 0 0 1 1 1 0
Rm
(0) (0) (0)
m = UInt(Rm);
if InITBlock() && !LastInITBlock() then UNPREDICTABLE;
if m==15 then UNPREDICTABLE;

Assembler syntax
BX{}

where:
{}

See Standard assembler syntax fields on page A6-98.

The register that contains the branch target address and instruction set selection bit.

Operation
if ConditionPassed() then
EncodingSpecificOperations();
BXWritePC(R[m]);

Exceptions
HardFault.

ARM DDI 0419C
ID092410

A6-125

Thumb Instruction Details

A6.7.16 CMN (register)
Compare Negative (register) adds a register value and an optionally-shifted register value. It updates the
condition flags based on the result, and discards the result.
Encoding T1
CMN

All versions of the Thumb instruction set.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 1 0 0 0 0 1 0 1 1
Rm
Rn
n = UInt(Rn); m = UInt(Rm);
(shift_t, shift_n) = (SRType_LSL, 0);

Assembler syntax
CMN{}

where:
{}

See Standard assembler syntax fields on page A6-98.

The register that contains the first operand.

The register that is used as the second operand.

Operation
if ConditionPassed() then
EncodingSpecificOperations();
shifted = Shift(R[m], shift_t, shift_n, APSR.C);
(result, carry, overflow) = AddWithCarry(R[n], shifted, '0');
APSR.N = result<31>;
APSR.Z = IsZeroBit(result);
APSR.C = carry;
APSR.V = overflow;

Exceptions
None.

A6-126

ARM DDI 0419C
ID092410

Thumb Instruction Details

A6.7.17 CMP (immediate)
Compare (immediate) subtracts an immediate value from a register value. It updates the condition flags
based on the result, and discards the result.
Encoding T1
CMP

All versions of the Thumb instruction set.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 1 0 1
Rn
imm8
n = UInt(Rn);

imm32 = ZeroExtend(imm8, 32);

Assembler syntax
CMP{}

, #

where:
{}

See Standard assembler syntax fields on page A6-98.

The register that contains the operand.

The immediate value to be added to the value obtained from . The range of permitted
values is 0-255 for encoding T1.

ARM DDI 0419C
ID092410

A6-127

Thumb Instruction Details

Operation
if ConditionPassed() then
EncodingSpecificOperations();
(result, carry, overflow) = AddWithCarry(R[n], NOT(imm32), '1');
APSR.N = result<31>;
APSR.Z = IsZeroBit(result);
APSR.C = carry;
APSR.V = overflow;

Exceptions
None.

A6-128

ARM DDI 0419C
ID092410

Thumb Instruction Details

A6.7.18 CMP (register)
Compare (register) subtracts an optionally-shifted register value from a register value. It updates the
condition flags based on the result, and discards the result.
Encoding T1
CMP

All versions of the Thumb instruction set.
and both from R0-R7

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 1 0 0 0 0 1 0 1 0
Rm
Rn
n = UInt(Rn); m = UInt(Rm);
(shift_t, shift_n) = (SRType_LSL, 0);

Encoding T2

All versions of the Thumb instruction set.
and not both from R0-R7

CMP ,

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 1 0 0 0 1 0 1 N
Rm
Rn
n = UInt(N:Rn); m = UInt(Rm);
(shift_t, shift_n) = (SRType_LSL, 0);
if n < 8 && m < 8 then UNPREDICTABLE;
if n == 15 || m == 15 then UNPREDICTABLE;

Assembler syntax
CMP{}

where:
{}

See Standard assembler syntax fields on page A6-98.

The register that contains the first operand. The SP can be used.

The register that is optionally shifted and used as the second operand. The SP can be used,
but use of the SP is deprecated.

ARM DDI 0419C
ID092410

A6-129

Thumb Instruction Details

Operation
if ConditionPassed() then
EncodingSpecificOperations();
shifted = Shift(R[m], shift_t, shift_n, APSR.C);
(result, carry, overflow) = AddWithCarry(R[n], NOT(shifted), '1');
APSR.N = result<31>;
APSR.Z = IsZeroBit(result);
APSR.C = carry;
APSR.V = overflow;

Exceptions
None.

A6-130

ARM DDI 0419C
ID092410

Thumb Instruction Details

A6.7.19 CPS
Change Processor State is a system instruction, see CPS on page B4-306.

ARM DDI 0419C
ID092410

A6-131

Thumb Instruction Details

A6.7.20 CPY
Copy is a pre-UAL synonym for MOV (register).

Assembler syntax
CPY

This is equivalent to:
MOV

Exceptions
None.

A6-132

ARM DDI 0419C
ID092410

Thumb Instruction Details

A6.7.21 DMB
Data Memory Barrier acts as a memory barrier. It ensures that all explicit memory accesses that appear in
program order before the DMB instruction are observed before any explicit memory accesses that appear in
program order after the DMB instruction. It does not affect the ordering of any other instructions executing on
the processor.
Encoding T1
DMB

ARMv6-M, ARMv7-M

Source Exif Data:
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ARMv6 M Architecture Reference Manual DDI0419C Arm V6m

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ARMv6-M_Architecture_Manual

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