ECL_SSI_Symbols ECL SSI Symbols
User Manual: Pdf ECL_SSI_Symbols
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MC101
MC100
Quad 2·ln NOR
with strobe
Altn
E
5
4
MC102
Quad 2·ln NOR
Quad OR/NOR
}
i~2 5~2
Oa5
4B!N 2 4 0 4
a3a
12 c
2
12 c 0
5
6~
7B2"
10Bl"1~OS4CO
~9~
7V ' 70'
F
6
10~
o
"~'~,a'4
12d,D
13 a1d
"
m
a3c
MC100
~
11
o
12
F
1513 Q 1 5
a3d
o 9
MC101
MC10S
[g
15
C101
d
0
12
15
13
0
a6d
9
4
,'----.
.
2
11
L
10
12
0
e
5
7
b1c
S3
0
1
C105
b2a
b2c
7
H
9
9
10
14
H
12
14
12
13
15
C10~
b4c
4~2
5~3
v 0
w
12~14
c
V
o
SDD
15
o MC11
6
5
4
10~Z
~3C 14
13~
~3d 15
12
MC115
Tpd =3.3
Project
ECl SSI Datasheet
10
15 11
13
=
0 15
U.210
Alternative
o
9
9
c MC117
11 e
10
14
v
13 s
s
15
c4
!O::
[ (8)
" (8) .
5
4 a
a
7
6
9
~
FIC~t
G
V c11
c10b 3
o 2
MC117
14
u
13~V 15
12
s
c5a
] (8)
R
4
9 5c1 1 7 S (
9
5 $aC 1 1 73 (S) 10
148 ) 11
e
a
11
u
10
7
0 2 C5b.1 3 y v 15
12
6
12
s
13 s
9
s
e5c
s
c10c 14
u
v
15
vn
Tpd=3.8
SE211
Alternative
C117
10
11
u
12
c
11~13
~:J
19 b10b
FICAP
::ih~3
~~~2
2
~:J
MC110
UC111,J
Tpd = 3.8(11 0 Tpd = 3.8(111
Tpd = 2.8(210 Tpd = 2.8(211
Tpd = 1.SeSE) Tpd = 1.SeSE)
est
est
r(8)
3
11
Z
Dual3·ln
3·0utNOR
~~~~!I
3
Tpd =3.3
4
a
5 a
6
7
~2
~3
Dual3·ln
3·0utOR
14
[
X
Z
Selective MC2ttJ
~:I
0
b7a
MC111
MC211
SE211
(Selective MC2tO)
MC117
Dual 2·3 In OR·AND/
OR·AND·INVERT
9'
7
MC110
MC210
SE210
C109
Tpd=4.0
14
Tpd =4.2
C109 1~~14 :9;
13
Quad Line
Receiver
:~
Tpd =4.3(114)
Tpd =3.6(114)
(Diff. Input)
Tpd =3.3(116)
10
11_b6b
12
0
13
MC11S
V
1.3 c2c
.~
10
MC107
11 '
XEROX
b58
14
4
0
!Br' 7B2
15
Tpd=3.3
Triple Line
Receiver
T(2~4)=4.S
Te2~9) = S.1
both EST.
b5~
3
~'0' C10. 12~15
a7
6
b6a
02
5
4
V
2
R 1 2 a - 15
0 9
10d
11
f i \14 13
aSd
14
0
a9d
13-0
0 9
10
MC104
Q,04
C
Altn
2
C106
MC114
MC116
Quad Ex·OR
b4b
9
Dual 4·5 In
OR/NOR
,
. 7
Tpd =3.3
MC113
b4a
0
MC109
3
/
6e 6
10b
a9b 3 -0
/
7
11
OC
A
10
B
10-0
a9c 14
11
Tpd = 3.3 est
MC107
Trip2·ln
Ex·OR
Ex·NOR
P
S
11
Tpd =3.3
:B
:&
2
E!'48 ~ b'a '1~ 1B ~B!:
~ i~' ,g b2: , 1;&,2
10 14e 9jb!"
13~"2ff5 ,;~
C10. 15jBf
b1a
0
6
10a
4-0
A
3
1S 3
0
10
15
C10
MC102
MC106
75
aSb
>
13~M912B15
7c
aSc
12
Trip 4·3·3 In
NOR
Trip 2·3·2 In
OR/NOR
c
M 1 2 a >9
11
13
0
\
a7b
o 3
6B
7
o
11
14
2 4
3
3
10BF
14
10[211
a6c
a5c
14
Tpd =3.3
Tpd = 3.3 est
4
B
5
0
a6b
7
5 7a
5't)sa2 {:;:\2
U
4
C
a7a
7 a5b
1~31:l4dO9
13
~OO
o
A 5»Altn/
\
26BF
6~
3 7 4bo
S6
3
6
a3b
F
10
5 a5a
Quad 2·ln AND
Altn
AItn
4 BF2
a6a
o
MC104
Quad2·ln OR
4a 5
Altn
{
MC103
MC117
Connect only one C pin on
bits lice, blob the other C pin
File
Designer
MC-1.sil
S.T.Chang
Rev
B
Date
9/12/78
Page
1
MC1660
MC1662
Dual 4 input OR/NOR gate
,....,
Ouad 2 input NOR gate
I
0
~~~U14 ~~B6 15
11- a1b 15 11 a2b 14
10
0
MC1660
Ouad 2 input OR gate
D
F
D
F
C
:E>-' :B'
:&-3 :B3
~B!U
3
5 a1a 2
4
MC1664
10
~E>'
':)3S'4
b1 15
11~~
7
c MC1672
10~C
a5co 14
12&D
a3d
15
13
MC1662
F
1 2a4d
B .15
13
MC1662
11
1 1a6c
&
\14
o
10
12~C
a5do 15
13
a \15
a6d
13
MC1688
"~7
b3a
6
13\~14
Dual Clocked R-S Flip-Flop
Dual Clocked Latch
b4a
v
9'
c
b
3
7~
6
7
'~~' ~!~3
b4b 2
b2
15
11~~
7
c MC1674
MC1668
~
0
14 b3b
16
15- 0 3 15
16
MC1688 1
i(8)
MC1666
6
FLATPAK ONLY
6j~
Tpd =2.8
c
2
4~
5 b
'0£1"
11
1~
8
Tpd = 2.8
Ouad Line Receiver
FLATPAK ONLY
3
MC1664
MC1692
Dual 4/5 input OR/NOR gate
5d~j(8)
b2a 2
o
12
MC1664
Tpd = 1.9
MC1674
Triple 2 inpuEXNOR gate
\
03 :&3
Tpd= 1.9
MC1672
Triple 2 input EXOR gate
C
F
1 °a4c
B14
11
Tpd = 1.9
:&'
{3>'
10E>-D
a3c
14
11
MC1660
\
c
14
10~
0
11 b
MC1688
13~
c
15
FLATPAK ONLY
12 b5
Tpd = 1.2 est
Tpd = 1.9
MC1670
Master-5lave D type Flip-Flop
MC1692
MC1690
Very Fast D type Flip-Flop
(a follows D when C is HIGH)
j(8)
5
so 2
c1a
7 C
0. 3
R
MC1666
4
~(8)
So
~
-
9
15
c1b
C O· 14
5
.• C
- ---
MC1668
9
12 C
110501-15
0. 14
R
13
Tpd= 2.8
Tpd = 2.8
Datashee
MECL III DATASHEET
----------------------
12-
01 0 2
02
7
c4
9 C1 0 • 3
'- C2 MC1690
Of-'
0. 3
CCR
MC1670
-
Tpd=2.9
Tpd = 2.3
Tsetup = 0.5 est
Tsetup
Thold
File
Project
2
S
4
9 c2b
C
11 ,..--
7 C c3
4
13
XEROX
11.- 0
0._3
R
k(8)
b
5
7 c2a
R
SDD
C
6. 0 So 2
MC-10.sil
= 0.5 est
Thold
Designer
Rev
K. Pier
B
est
=0.5
est
= 0.5 est
Date
9/10/76
Page
10 end
MC12l
MC124
MC123
OR-AND INVERT
S
4
./
6
5
4
~E>' ~B'
Sea)
3
11 a1b
10
2
9
10
14 a1c
13
Tpd =3.a
1512
13
MC123
High speed
Line Receiver
V
1
2
3
4
5
6
7
8
Cx
0
7
11' MC216
0
12 V1
11 V
V
9~6
a7b
10~7
o
V
P1
P2
P3
P4
P5
P6
P7
P8
13~15
o
Tpd = 2.7(est.)
(Diff. Input)
Tpd = 2.3(est.}
V1 V2
H
V1>V2
H
H
V1(8)
9
~
.
P2
P3
P4
P5
P6
P7
P8
14
13
SE212
MC125
Tpd=6
'2
PLAT's
automatic
assignment
terminator
Dual3·ln OR-AND
10
Crystal Oscillator
SOD
4
5
TERM
H
O'tn
Ec10_ 13
EclQ 12
TTtlQ
MC12061
Xtal1
a17
Xtal2
SIN)'
SINo'
SINi
SINo
XEROX
SIP
3
VEE1
TVEE
6
6
6.8
6.8
3
L
1
16 VCC1
11 EVCC
TVCC
1+
313+
Augat
platform
I(a}
Frombtol
for pin# 1 to 8
MCl18
#(8)
6+
7+
67-
1(6)
Otn+1 O'tn+ 1
C
T(2+-6} = 5.7
Tpd
1
2.- P1
9
11 a5b o
10
c
13
14~
15 a4d
PLAT
1650 (high Impedance Inputs)
1651 (low Impedance inputs)
12~14
Out
2
4
tl
I
11
In
T(a)
0 2
0' 3MC1650 a7a
4
13
15
MC123
7
6 a5ao
10~
~4C 12
14
SIP package
~~O
5~3·
11
G
a2c
S'
K
6~
7 ~4b
5
12
15
SIP
Dual A/D Comparator
W
2G
2b
X(a)
9,
1
Tpd =3.a
MC1650, MC165l
4~2
a
3
10
High speed
Dual OR/NOR
2~4
I
7
12Ei 14B
a10
v
2
+
x
:t:> "B
3
MC2l6
a3a
6 co2
T
4
(Selective MC212)
Quad Transl
ECLtoTTL
5B'
Triple 4-3-3
Bus Driver
4-wlde OR-AND/
MC2l2
SE2l2
MC125
Quad Transl
TTLtoECL
~;~C:18
15
2
MC118 10
d8c
15
12~ ~8C
Connect only one c pin on
bitslice, blob the other c pin
File
Project
ECl SSI Datasheet
MC·2.sil
Designer
S.T.Chang
Rev
C
Date
9/7/7a
Page
2
--- ------------------
F10000 O(S)
FOO
11~14
1
FOO
11
14
HO 15 10~15
10 DO
D1
Hi 2
9 D2
FOO
a1 H2 3
7
D3
H3
9{:]2
K(S)
6 FOO
FOO
5 DS
FOO
6 DS
PE'
5 PE' a2f
CC CCMR
7[;}3
CC CC MR
FOO
13 412
13' 4 12
4 bit Shift Register
C~~
F10016
O(S)
F16
.
CO
HO
Hi
H2
H3
11
10 DO
9 D1
7 D2
D3
5 F16
PE' b1a
C MRCE'
13 12 6
11~14
4
14
15
2
3
F16
10~15
F16
MR PE'
H X
L L
L L t
L
H
L
H
L ~
L
C
G
ODE
X rese - all outputs low
Tpd = 5.5
Tw' = 3.8(clock pulse width)
Ts = 1.7 (data setup)
Th = 1.1 (data hold)
Tse = 6.0 (PE' setup)
tt baral elload
aral elload
tt
L Ir;hift left
L tt Ir;hift left
X hold
H hold
L
(all times estimates)
O(S)
d
11Q14
b3b
4 bit Binary Counter
9{;D2
F16
CE
7f:}3
F16
L
H
L
H
X
X
M(8)
F16 b2t
5 PE'
CO' 1-4
C MR CE'
13 12 6
PE' MR P
UNCTION
L tt oaral elload
L tt ara elload
tt coun
H
tt hold
H
ast rs aDen slaves hold
)(
X rase
t(S)
5 PE' co 4b3t
C MRCE' F16
13 12 6
Tpd = 5.5
Tw = 3.5(clock pulse width)
Ts = 2.2 (data setup)
Th = 1.1 (data hold)
Tse = 2.S(PE' and CE' setup)
A(S)
obsolete:
Dual Latch
MC130
(~
I
N(S)
c
c
12
c2d
~
7 S 2 10
MC130
Dsa 15 7 D S a 2
D a
CC
c1b
6 cia
c2c
9
C
11
6 C
3
14
C
.3
9 CCRa'
a'
a'
R
R MC130
MC130
4
13
4
b
5
SE231 (Selective MC231)
C
MC131
5
MC231
7 Dsa 2
b
7+
D a
6 d1a
C
9. CC a'
R
4
D
L"
H
C
L
L
L
X
X
X
X
X 'H
X
X Ii
S R
X X
X X h
L
L
H
H
L
L
H
L
L
L
L
H
H
H
a
a
On+1
CC
9
I FUNCTION
MC130
Tpd = 4.1
Ts = 2.S est
Th = 1.7 est
a folio sD
a folio sO
h
s
s
r
r
in
r;J
old
Id
t
t
set
set
eter inate
A(S)
obsolete:
X
X
X H H
d2c
D .... C .... .li
X
L L
6
C Q,3
tt L
L
~
10
S
R MC131 L t L L
2
D a 15
t
H
L
4
d1b
H t
L
11
N(S)
3
X X
H
C a' 14
X X
L
MC131 R
d2d
MC131
X
H
13
X
H
CC
C
I
R
L a
L L
L L
L H
L H
L h
H L
H
H
I I
d,3d MC131
CC
9
Dual D type Master-Slave Flip-flop
indeterminate
an + 1
I FUNCTION
Id
mo p/
moiv
mo
m mo Iv.
s t
r set
in ete iminate
in ete minate
h
m
m
m
MC131
MC231
SE231
Tpd = 5.0
Ts = 2.S
Th = 1.7
Tpd = 3.7
Ts = 1.1
Th =O.S
Tpd= 2.5
Ts = 1.1
Th =O.S
(all times estimates)
9
A(S)
MC135
N(S)
(
4
5
5
5
~
~
7 J'S a 2
7
e2d
10 J'S a 15 J'S a 2
~g135
e1a
e1b
CC
e2c
9
11 K' Q' 14 6 K' a' 3
6 K' a' 3
R
R
R
MC135
MC135
4
4
I I
-:;'
RS Truth Table
R
L
L
H
H
n+1
n
L
H I
1.
H i det
7
XEROX
SOD
Project
Datashee
obsolete:
Dual J-K Master Slave Flip-Flop
ECl MSI data sheet
CC
9
Clocked JK Truth Table
J' K' On+1
L
n'
H
L
H H
n
MC·3.sil
Designer
K. Pier
MC135
Tpd = 4.6
Trs = 5.aR, 5 to Q)
Ts = 2.S est
Th 1.7 est
=
clock = tt on CC
File
~
Rev
B
Date
5/15/78
Page
3
MC136
-
U
CO -~
3
BO
HO
2
B1
H1
15
B2 a1 H2
14
B3
H3
MC136
9
7 5U'
--'
5
6
11
12
SU'SD'
6~2
L
L
MC136
L
H
H
11~1512_~14 L H
5{;;J3
MC136
L
MC136
13
MC136
MC136
4
5U'
CO'
SO'
C a21 CI'
13
10
10
MC141
O(S)
~~ ~'4' ~~: .~ Mb::"~2
b1
02 2
031-3
MC141
~-
SR'
10 SL'
C OL DR
4' 5 13
MC141
7 SR'
10 SL' b21
C OL DR
4
5 13
MC160
f
15_
14
13
12
11
10
~MC141
6
Inputs asumed to vary In
BO B1 B2 B3
H
H
L
L
X
X
X
X
X
X
X
X
X
X
X X
X
X
X
X
x
X
X
X
L
L
X
X
X
X
X
X
X
X
X
X
H
X
X
X
X
CI' C HO H1 H2 H3
X
L
L
L
H
H
X
X
L
L
L
L
X
X
H
X
X
X
X
tt
"
L"
"
tt
"tt
"
"
"
tt
H
H
H
H
H
H
H
L
L
L
L
H
H
H
H
H
H
H
H
L
L
L
L
H
H
H
H
H
H
H
L
L
L
H
L
H
L
H
L
H
H
H
H
H
L
H
L
H
CO'
L
Load
H
H
cou~p
L
H
H
Hold
H
L
Load
H
H
Count
L
Down
H
sequence from top to bottom
Tpd = 11 .5
Tsd = 3.9(data setup)
Tss = S.3{select setup)
Tsc = 4.1 (CI' setup)
Thc = 3.4 (CI' Id)
(all times estimates)
4 bit Shift Register
12~1411~15
...-__--.v
02
6 03
H
H
H
L
L
L
L
L
L
H
L
H
H
H
H
9
7
CI'
9
L
0(8)
so'
C
Hexadecimal Counter
O(S)
D,....:r:~I1~~::r-~i=~-ad~----r-:D~~~/~~j..:.+-i1}
Tpd = 4.2
Tsd = 2.8(data setup)
Tss = 5.5(select setup)
Thd = 1 .7(data hold)
Ths = 1 .1 (select hold)
rSL:-:R_'rS:=,L_'
b2e
3
MC 141
""L;:;-r.-,,::sI;:n-¥;iif,:-t7:ri~ajh~t:..- _ _ _-t~0~i;;.;-1~(nf7.}::t
t-'H~£7-~St:~7;if:.tI:.::e""ft'-- _ _ _ _-H0:;;ii:+:T'.:.:(n~
t-'H~rH~ro~/d~ _ _ _ _ _~~O=i~m~}~
F(S)
ALL OUTPUTS EXIST AFTER CLOCK
clock = tt on C
(all times estimates)
12-bit Parity Generator/Checker
MC160
=
Sum of high Inputs
000 2
~
6~-
Even
Odd
Tpd =S.3
Output
est
low
High
cl
5
4
3
h
obsolete:
Binary 1 Of B decoder-low true outputs
MC161
8(8)
MC161 6
00'
dl
5
14
01'
4
54
02'
3
03' 1-13
9
S2
04'
12
05'
7 Sl
11
06'
07' 10
E'
15
E'
MC162 6
00
el
14
01 5
S4
02 I-~
3
9
03
13
52
04
12
05
7. 51
11
06
10
07
E'
2
XEROX
SDD
S4
L
L
H
H
L
00' 01' 02' 03' 04' 05' 06' 07'
L
H
H
L
L
L
L
H
H
H
H
X
X
X
X
L
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
L
H
H
Tpd = 6.6
-
E'
E'
2'
15
2
MC162
9(S)
(~.
E' E' S1 S2
L
L
L
L
L
H
L
L
L
L
H
L
L
L
L
L
L
H
L
L
L
L
L
H
H
X
X
X
H
X
MC161 6
00' 5
14 d2 01'
S4 02' 4
3
9
03'
52 04' 13
est 7
05' _~2
S1 06' 11
10
07'
E'
15
E' E' S1 S2
L
L
L
L
L
H
L
L
L
L
L
H
L
L
L
L
L
H
L
L
L
L
L
H
H
X
X
X
H
X
S4
L
L
H
H
L
L
H
H
X
X
L
L
L
L
H
H
H
H
X
X
00 01 02 03 Q4 05 06 07
L
H L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
.
~
L
L
H
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
g
obsolete:
Binary 1 Of B decoder - high true outputs
L
L
L
L
H
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
Tpd = 6.4
MC162 6
QO
5
e2
14
01 4
S4 02
3
9
03
S2 04 1-!3
12
7
05
Sl 06 11
07 1-10
E'
L
H
L
2
E'
15
L
Project
File
Designer
Rev
Datashee t ECl MSI datasheet
MC-4.sil
K. Pier
B
Date
2/3/77
Page
4
- . ------------- - - - - - - - - - - - - - - -
MC163
()
Error Detection/Correction Circuit
n
9
~.
6
10
12
~.
5
11
MC163 15
POA
BO
B1 POBr2
B2
B3
P1 14
B4
B5
P2 r13
B6
B7
P3 3
al
MC164
~,
4
3
11
12
13,
14,
01
02
15
03
Z
04
05 bl
06
07
MC164
10
9 54
7, 52
51 E'
2
Tpd = 7.5
est
(, denotes EXOR)
MU164
I
~, 00
6
~,
4
3
11
12
@(s)
8 line Multiplexer
00
01
02
15
03
Z
04
05 b2
1~,
Midas
14, 06
07
multiplexer
MU164
10
ONLY
9 54
52
7
51 E'
2•
E'
S1 S2 S4 Z
L
L
L
L
L
L
L
L
H
L
H
L
H
L
H
L
H
X
L
L
H
H
L
L
H
H
L
L
L
L
H
H
H
H
X
X
DO
D1
D2
D3
D4
D5
D6
D7
L
Tpdd = 4.S (data)
Tpds =6.5 (select)
Tpde = 3.1 (enable)
(all estimates)
8 input Priority Encode, with latch
MC165
k
MC165
00 ANY 14
01
02
03
HO r15
04 c1
2
05
H1
9 06
6 07
H2 3
C
4
/")
POA = 81,82,84,87
P08 = BO, 83, 85, 86
P1 = 81,83,85,87
P2 = 82, 83, 8S, 87
P3 = 84, 85, 86, 87
5
7
13
10
11
12
DO
H
L
L
L
L
L
L
L
L
D1
X
H
L
L
L
L
L
L
L
D2
X
X
H
L
L
L
L
L
L
D3
X
X
X
H
L
L
L
L
L
D4 D5 D6
X
X X
X
X X
X
X X
X
X X
H
X
X
X
L
H
L
L
H
L
L
L
L
L
L
D7ANY
X H
X H
X H
X H
X H
X H
X H
H
H
L
L
HO
L
L
L
L
H
H
H
H
L
H1
L
L
H
H
L
L
H
H
L
H2
L
H
L
H
L
H
L
H
L
Tpdd = 16.5 (data)
Tpdc = 5.3 (clock)
Ts =5.1
Th =0.0
(all estimates)
Outputs held when C is high
MC171
Dual Binary to 1-ot-4 Decoder -low true outputs
j
MC171
14
EQ'
d1
2
9 ER'
7. 52
Sl E'
15 •
QO
Q1
Q2
Q3
13
12
11
.10
MC172
14
EQ
e1
()
~,
9 ER
7 S2
Sl E'
15
XEROX
SDD
L
L
L
H
i
QO r~3
Q1 12
Q2 11
Q3 10
RO
Rl
R2
R3
L
L
L
RO 6
R1 5
R2 4
R3·3
MC172
E'
6
5
r!
3
EO' ER'
L
L
L
L
L
L
L
L
H
L
H
L
X
X
L
H
L
H
L
L
X
L
L
H
H
L
L
X
L
H
H
H
L
H
H
H
L
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
L
H
H
H
L
H
H
H
H
L
H
H
L
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
L
H
H
H
Tpd=6.4
Dual Binary to 1-0f-4 Decoder - high true outputs
E'
EO ER S1 S2 QO 01 02 03 RO R1 R2 R3
L
L
L
L
L
L
H
H
H
H
H
L
H
X
Project
Datashee
S1 S2 QO'01'02'03'RO'R1'R2'R3'
H
H
H
H
H
L
X
L
H
L
H
L
L
X
L
L
H
H
L
L
X
H
L
L
L
L
H
L
L
H
L
L
L
L
L
L
L
L
L
H
L
H
L
L
L
L
L
L
L
File
ECl MSI datasheet
MC,5.siI
H
L
L
L
H
L
L
L
L
H
L
L
L
L
L
L
H
L
L
L
L
L
L
L
H
L
L
L
Tpd =6.4
Designer
Rev
K. Pier
A
Date
7/28/76
Page
5
MC173
U(S)
2
5
6·
3
4
12
13
10
11
MC173
DO
00t-1
BO a1
2
D1
01
B1
D2
02t-15
B2
14
D3
03
B3
SB C
9
obsolete:
Quad 2-input Multiplexer/Latch
5 MC173
Q 1
6 D
B a2b
MC173 15
13 B a2d Q
3 DMC173
0 2
4 B
a2c
MC173 14
1~.
Q
11 o
B a2e
Qi(n+ t!
Bi(n}
J
Di('1l J
Qi(nL J
SB C
IH !L i
L
IX
L
H
obsolete:
5 X1
OX 2
X2
6. X3
13
b1
11 YO
12 Y1
OY 15
10 Y2
Y3
7
82
81
E'
14
V(S}
MC174
XO
X1 OXt-2
X2
X3 b2b
V(S)
MC174
13 XO
9 MC174 W(S}
1 ~. X1
OX 15
1~. X2
7- S1
S2 b2d
10 X3 b2c
E'
14
OXI-2
6 X3 b3b
3
5
4
6
E' S1 S2 OX
H
X X L
L
L
XO
L
L
H
L
X1
L
L
X2
H
L
H
H
X3
O(S)
5~2
(
14
YO
Y1
Y2
Y3
Tpdd = 4.S(data}
Tpde = 3.2(enable}
Tpds = 6.4(select)
e
obsolete:
rc;;]
~MC176
10[";;"113
6~3
~
~
7~4 12~15
~
C
E(S)
11~14
MC174
E'
L
O(S)
~~-
MC176
5 DO 00 2
6 D1 Q1 3
7 D2 Q2 4
10 D3 Q3 13
1~. D4 Q4 14
12. D5 Q5t-15
C
c1
f(S}
...------,
~~t~~ b3d
OY
Hex D Master-S/ave Flip-Flop
MC176
e(S}
!~- xo
~~
Dual 4 to 1 Multiplexer
4
7~MC173
Tpdd = 5.3 (data)
Tpdc = 6.S (clock)
Tpds = 6.7 (select)
Thd = 2.S (hold data)
Ths = 1 .7 (hold select)
7(S)
MC174
9
5~1
C a2f
MC173
7'
.......--..,m
3 XOMC174
9.rs;----,
6~
1~. D
~7_ SB
deS)
C{S)
I
D
I tt iL
Itt iH
MC1761
9
Qi(n+ 11
Qt(n}
I
L
I
H
.J
Tpd =5.0
Ts. = 2.S
Th = 1.7
C C2hJ
9'
est
est
~
9
B
~V2
6)rt.,
C195
)~")~
d1c
4
d1e
10)~ 12)~
d1d
13
d1f
MC11 w(S)
9 Invde~r, May be omitted
14
15
alternate view:
XEROX
SDD
! (S)
613>3
s
s
7
84 1 1
e1c
e1e814
9
U(S)
11~14
4
10~13 12~15
MC197
e29
Enable
2
7 e2c
6 e2b
3
10 e2d
xes)
v(S)
v(S)
v(s)
v(S}
v(S)
v(S}
6B>3
10~1312~15
Z(S}
~ ~ ~
~ ~ ~
5 e2h
MC195J
d31
Buffer
est
5~2 7~4 11~14
! (S)
!CS)
9
S
6
83
1 °e1d
8 S13 128S
e1b
e1f 15
MC197
---',
7 d2c
Hex AND gate
MC197
2
~
U(S)
58>2
,
DO
:V
Tpd =4.2
Hex Inverter/Buffer
MC195
4
11
e2e
14
13 12 e2f
15
Tpdd = 4.2 (data)
Tpde = 5.3 (enable)
Project
File
Designer
Rev
Data8hee~ ECl MSI datasheet
MC·6.sil
K. Pier
B
----
-
Date
est
est
Page
2/3/77
6
---
---
- 0-
MC140
MC142
MC14S
13
2
~.
~
01
AO
A1
MCM140
MCM142
MCM14S 0 (S)
~5 13~15
~
DOf-'
2
A1 MC140
7 A2
A3
1~. A4
a2c
9 A5
W' E' E'
12 5 4
W' E' E'
12
5
4
F145A
MC145
9
~
AO
A1
A2
~~0145A
.
./
~
2
~~ 11
15
14
Z(S)
~
~
b2d
15
F145A
10
9
~-
12~14
O(S)
11~15
F145A
AO
A1
A2 b2f
A3
CE' WE'
3 13'
~
MC147
MCM147
s
~
5~2
(setup times)
Tsd =0
Tse=3.5
Tsa=5.5
Thd = 3.5
(hold times)
The =0
Tha =3.5
(all times estimates)
B
16 x 4 Register File
4~1
b1
Tace = 14(E' access)
Taad = 11(Ai access, MCM142)
Taad = 17(Ai access, MCM140, 148)
Tw' = 11 (write pulse width)
Te' = 15 (enable pulse width)
(MCM 140 drives 90 ohm loads)
F10145A
MCM145 O(S)
.-__..,r
5 00
00
4.
01
01
11,. 02
02
12 03
03
CE' WE'
3'13'
,
yeS)
AO
~
A2 a1
10 A3
A4
9. A5
MCM142
1~.
64 Bit Random Access Memory
obsolete:
a(S)
b(S) 10 AO
F10145:
5 0 Q 2
b3b
9
MCM145 7 A1 b3t
Tace = 6.6E' access)
6 A2
Taad = 9.~Ai access)
A3
Tsd =5.0 Thd = -1.0
CE' WE'
Tw' = 4.4(write pulse width)
Tse = 5.0 The = 0.5
3 13'
Te' = 4.4 (enable pulse width)
Tsa = 3.9 Tha = 1.0
Twr. = 6.6 (ce,we output recover)
MCM145:
Tsd, Tse relative toend-o#-WE'
Tace = 10(E' access)
Tsd = 0
Thd = 5.0
Taad = 15(Ai access)
Tse = 5.0 The = 5.0 all est
Tw' = 11 (write pulse width)
Tsa = 5.0 Tha = 5.0
Te' = 11 (enable pulse width) Twr = 11.0
128 x 1 bit Random Access Memory
MCM147
MC147
15
01
DO
O(S)
4
AO
4
AO
3
A1
3
2
A1 MC147
A2 c1
2
5
A2
A3
~. A3 c2c
6 A4
~. A4
7
A5
7
10
1'0 A5
A6
A6
W' E' E'
W' E' E'
12 14 13
12' 14' 13'
11
MC149 MCM149
MC150 MCM150
Tace = 8.SE' access)
Taad = 14(Ai access)
Tw' = 8.8(write pulse width)
Te' = 11 (enable pulse width)
Tsd = 1.0
Tse = 1.0
Tsa =4.0
(setup times)
All UNUSED INPUTS MUST BE
TIED TO VEE
Thd = 1 .0
The = 1.0
Tha = 3.0
(hold times)
(all times estimates)
256 x 4 bit Programmable ROM
•
4
MCM149
2 AO
00 15
3 A1
01 14
9 A2
:. A3
1~. A4 d1
12
6 A5
02r'
5
7 A6
03 11
A7
MCM149
MCM150
Tace = 13
Taad=32
Tace= 10.5
Taad=30
(all times estimates)
_CE'
13
F415A
F10415A
O(S)
15~1
~
--...
Hs
F415A
3 AO
A1
~. A2
5 A3
6 A4 e2c
7 A5
9
10 A6
A7
11,_ AS
12_ A9
L-
CE' WE'
14 13
XEROX
SOD
15_
2
2
3
4
5
6
7
9
10
11, •
12
3
01
AO
A1 e1
A2
A3
DC 1
A4
A5
A6
A7
AS
F415A
A9
CE' WE'
14
1024 x 1 bit Random Access Memory
Tace = 10(E' access)
Taad = 35(Ai access) •
Tw' = 25 (write pulse width)
Te' = 35 (enable pulse width)
• a 25ns Taad, 20 ns. Tw' par' is available
(all times estimates)
(setup times)
Thd =5
The =5
Tha =2
(hold times)
13
File
Project
Datashee
Tsd =5
Tse =5
Tsa =8
ECl MSI datasheet
MC-7.sil
- - - - - - - - - - - - - - - - - - - - - - - - -- --
Designer
Rev
K. Pier
B
Date
2/14/77
----------------
Page
7
MC179
o
MC179
CIN
GIOCOUT
PIO
GI1 CMD
PI1
Gg
GI2
PI2
4
Pg
14' GI3
'. PI3
a1
Look Ahead Carry Block
Tp~
11
5
13
9
12
7
10
=6
est
=
3
Pg
PO + P1 + P2 + P3
Gg = (G3 + P2 + P1 + PO)(G2 + P1 + PO)(G1 + PO)GO
CMD = (CIN + P3 + P2)(G3 + P2)G2
COUT = y
X(Y
L
L
L
H
l
L
H
L
Tpdd =9.0
Tpde = 3.8
est
est
Quad 2-t0-1 multiplexers
MC159 14
10
0'
11 0
B d4b
6(8)
MC159
DO
1
00'
MC159
BO
12
o
Q' ~15
01
2
13
B d4c
Q1'
B1
02
MC159
02' ..15
1~. B2
2
Q'
~- o
1~. 03
14 4
11
B d4d
03'
B3
d2
SB E'
MC159
1
o
0'
7
9
6~B d4e
5
6
3
4
12
E'
H
L
L
L
L
Di Si SS Qi
QI'
L
H
l
H
l
x x x
L X l
H X L
X L H
X H H
159
e!!!l!
L
H
L
H
158
onlv
159
onbL
MC15S
MC159
Tpdd =3.6 Tpdd =3.6
Tpds =5.0 Tpds=5.0
Tpde=5.0
all times est
5(8)
~.
7
SB
E' d4f
MC159
MC170
D(S)
3
7
4
9
\
a1
5
10
6
11
12
2 carry inputs
2
A
a
SUM OF PINS 3-12
EVEN
f0015
000
SUM OF ALL INPUTS
EVEN
CI
14
XEROX
SOD
9 bit parity circuit with
MC110
000
CI
13
?
?
PIN 15
?
?
L
H
all times est
Project
Datashee
PIN 2
L
H
TpdA =6.6
TpdB=9.9
Tpdcarry = 3.3
File
ECl MS. datasheet
MC-9.sil
Designer
Rev
K. Pier
E
- - - - - - - - - - ---
----
----
Date
2/3/77
Page
9
--, 10
(
MC175
Quint Latch
( (8)
Q (8)
MC175
14
DO
00 15
01
01 2
02
02 3
03
03
04r 4
04
, 12·
\.J 13
9
5.
F470
AO
A1
A2
A3
A4
A5
A6 b01c
A7
AS
A9
A10
A 11
10
11
12
13
14.
5
MC175 15
a01c
17~1
l.ruwJ
% (8)
Q (8)
AO
A1
19 MB071
23
c01b
A2 c01f
A3
A4
A5
A6
A7MB071
18 MB071
22
c01c
17 MB071
21
c01d
BSO'
BS1'
BS2'
BS3'WE'
16 MB071
20
c01e
SDD
= 35
= 15
= 25
= 55
=
= 10
= 5
= 5
= 5
= 15
= 20
= 15
I
)
=
=
=
=
=
=
Project
ECl SSI Oatasheet
----------- -
CC CC MR Q(n+1
L
H
X
X
L
L
H
X
L
L
X
H
L
L
L
L
L
H
O(n)
O(n
X
X
H
X
X
H
H
H
L
L
Tpdd
Tpde
Tpdr
Ts
Th
(8)
= 3.6
=
=
4.4
4.2
3.7
=
= 2.2
(data)
(clock)
(reset)
(setup)
(hold)
256 x 1 random access memory
F414
A access
-
CEaccess
write pulse
1
2
3
4
9
10
setup data
hold data
setupaddr
setupCE
holdCE
write disable
write recover
Taad
Taee
Tw'
Tsd
Thd
Tsa
Tha
Tsee
Thee
Twd
Twr
Teer
Q (8)
(8)
13~15
AO
A1
A2
A3
~
F414
A4
A5
1!. A6
12 A7
hold addr
b02c
5 CSO'
6 CS1'
7 CS2'
WE'
14
CE recover
Taad = 10.0
4,5
Tabs
8.0
Tw'
Tsd
2.0
Thd
2.0
Tsa
= 2.0
Tha
= 2.0
Tsbs = 2.0
Thbs = 2.0
Twd
5.0
Twr
9.0
4.5
Tbsr
=
2
XEROX
I MC175
D
Icc cc MRI a019
6
7 11
256 x 4 random access memory
MB071
6
5
4
3
MC175 4
a01f
Taad
Taee
Tw'
Tsd
Thd
Tsa
Tha
Tsee
Thee
Twd
Twr
Teer
Q (8)
CE' WE'
16 15
7
S
9
10·
11
12
13
14
MC175 3
a01e
4K x 1 random access memory
$ (8)
~S
12
711
F470
2
3
4
5
6
9
13 MC175 2
a01d
a01
CCCCMR
6
10 MC175 14
a01b
O/Tpackage
+ platform
write pulse
setup data
hold data
setup addr
hold addr
setup BS
11
19'
21'
20
17
16
22
15
F181K
0
H
E c02b
F181K
CIN'
OE' G' 10 23 F181 K
FO
P' 9
14 0
H
F1 CO' 8
E c02c
F2
F3 c02f
24 F181K
13'
hold BS
I,
0
5
4
3
HI-'
E c02d
write disable
write recover
BS recover
1 F181K
2
12 0
HI-'
~- E c02e
File
Designer
MC11.sil
K. Pier
-----------
=
6
= 7
write pulse
=
1
setup data
=
2
=
= 2
= 1
= 2
= 8
= 10
= 6
1
hold data
setup addr
hold addr
setup CE
holdCE
write disable
write recover
CE recover
0.4 wide DIP package
2 (8)
A access
& (8)
A access
CEaccess
100K series 4 bit ALU
F181K
BSaccess
= 10
Tdh
Teh
Tfh
Teinh
Teio
Tdpg
Tepg
Tfpg
Tdeo
Teeo
Tfeo
Toeh
Rev
A
=6.5
=6.5
= 6.5
= 4.7
=3.6
= 4.1
=4.1
OtoH
Eto H
Fto H
CINtoH
CIN to CO
Oto P,G
Eto P,G
= 4.1
Fto P,G
= 5.4
= 5.4
EtoCO
=5.4
= 2.1
Date
9/7/78
OtoCO
FtoCO
OEto H
Page
11
Source Exif Data:
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