EE Core Instruction Set Manual
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- EE CORE INSTRUCTION SET MANUAL
- About This Manual
- Changes Since Release of 5th Edition
- Notational Convention
- CPU Instruction Set
- ADD : Add Word
- ADDI : Add Immediate Word
- ADDIU : Add Immediate Unsigned Word
- ADDU : Add Unsigned Word
- AND : And
- ANDI : Add Immediate
- BEQ : Branch on Equal
- BEQL : Branch on Equal Likely
- BGEZ : Branch on Greater Than or Equal to Zero
- BGEZAL : Branch on Greater Than or Equal to Zero and Link
- BGEZALL : Branch on Greater Than or Equal to Zero and Link Likely
- BGEZL : Branch on Greater Than or Equal to Zero Likely
- BGTZ : Branch on Greater Than Zero
- BGTZL : Branch on Greater Than Zero Likely
- BLEZ : Branch on Less Than or Equal to Zero
- BLEZL : Branch on Less Than or Equal to Zero Likely
- BLTZ : Branch on Less Than Zero
- BLTZAL : Branch on Less Than Zero and Link
- BLTZALL : Branch on Less Than Zero and Link Likely
- BLTZL : Branch on Less Than Zero Likely
- BNE : Branch on Not Equal
- BNEL : Branch on Not Equal Likely
- BREAK : Breakpoint
- DADD : Doubleword Add
- DADDI : Doubleword Add Immediate
- DADDIU : Doubleword Add Immediate Unsigned
- DADDU : Doubleword Add Unsigned
- DIV : Divide Word
- DIVU : Divide Unsigned Word
- DSLL : Doubleword Shift Left Logical
- DSLL32 : Doubleword Shift Left Logical Plus 32
- DSLLV : Doubleword Shift Left Logical Variable
- DSRA : Doubleword Shift Right Arithmetic
- DSRA32 : Doubleword Shift Right Arithmetic Plus 32
- DSRAV : Doubleword Shift Right Arithmetic Variable
- DSRL : Doubleword Shift Right Logical
- DSRL32 : Doubleword Shift Right Logical Plus 32
- DSRLV : Doubleword Shift Right Logical Variable
- DSUB : Doubleword Subtract
- DSUBU : Doubleword Subtract Unsigned
- J : Jump
- JAL : Jump and Link
- JALR : Jump and Link Register
- JR : Jump Register
- LB : Load Byte
- LBU : Load Byte Unsigned
- LD : Load Doubleword
- LDL : Load Doubleword Left
- LDR : Load Doubleword Right
- LH : Load Halfword
- LHU : Load Halfword Unsigned
- LUI : Load Upper Immediate
- LW : Load Word
- LWL : Load Word Left
- LWR : Load Word Right
- LWU : Load Word Unsigned
- MFHI : Move from HI Register
- MFLO : Move from LO Register
- MOVN : Move Conditional on Not Zero
- MOVZ : Move Conditional on Zero
- MTHI : Move to HI Register
- MTLO : Move to LO Register
- MULT : Multiply Word
- MULTU : Multiply Unsigned Word
- NOR : Not Or
- OR : Or
- ORI : Or immediate
- PREF : Prefetch
- SB : Store Byte
- SD : Store Doubleword
- SDL : Store Doubleword Left
- SDR : Store Doubleword Right
- SH : Store Halfword
- SLL : Shift Word Left Logical
- SLLV : Shift Word Left Logical Variable
- SLT : Set on Less Than
- SLTI : Set on Less Than Immediate
- SLTIU : Set on Less Than Immediate Unsigned
- SLTU : Set on Less Than Unsigned
- SRA : Shift Word Right Arithmetic
- SRAV : Shift Word Right Arithmetic Variable
- SRL : Shift Word Right Logical
- SRLV : Shift Word Right Logical Variable
- SUB : Subtract Word
- SUBU : Subtract Unsigned Word
- SW : Store Word
- SWL : Store Word Left
- SWR : Store Word Right
- SYNC.stype : Synchronize Shared Memory
- SYSCALL : System Call
- TEQ : Trap if Equal
- TEQI : Trap if Equal Immediate
- TGE : Trap if Greater or Equal
- TGEI : Trap if Greater or Equal Immediate
- TGEIU : Trap if Greater or Equal Immediate Unsigned
- TGEU : Trap if Greater or Equal Unsigned
- TLT : Trap if Less Than
- TLTI : Trap if Less Than Immediate
- TLTIU : Trap if Less Than Immediate Unsigned
- TLTU : Trap if Less Than Unsigned
- TNE : Trap if Not Equal
- TNEI : Trap if Not Equal Immediate
- XOR : Exclusive OR
- XORI : Exclusive OR Immediate
- EE Core-Specific Instruction Set
- DIV1 : Divide Word Pipeline 1
- DIVU1 : Divide Unsigned Word Pipeline 1
- LQ : Load Quadword
- MADD : Multiply-Add word
- MADD1 : Multiply-Add word Pipeline 1
- MADDU : Multiply-Add Unsigned word
- MADDU1 : Multiply-Add Unsigned word Pipeline 1
- MFHI1 : Move From HI1 Register
- MFLO1 : Move From LO1 Register
- MFSA : Move from Shift Amount Register
- MTHI1 : Move To HI1 Register
- MTLO1 : Move To LO1 Register
- MTSA : Move to Shift Amount Register
- MTSAB : Move Byte Count to Shift Amount Register
- MTSAH : Move Halfword Count to Shift Amount Register
- MULT : Multiply Word
- MULT1 : Multiply Word Pipeline 1
- MULTU : Multiply Unsigned Word
- MULTU1 : Multiply Unsigned Word Pipeline 1
- PABSH : Parallel Absolute Halfword
- PABSW : Parallel Absolute Word
- PADDB : Parallel Add Byte
- PADDH : Parallel Add Halfword
- PADDSB : Parallel Add with Signed Saturation Byte
- PADDSH : Parallel Add with Signed Saturation Halfword
- PADDSW : Parallel Add with Signed Saturation Word
- PADDUB : Parallel Add with Unsigned Saturation Byte
- PADDUH : Parallel Add with Unsigned Saturation Halfword
- PADDUW : Parallel Add with Unsigned Saturation Word
- PADDW : Parallel Add Word
- PADSBH : Parallel Add/Subtract Halfword
- PAND : Parallel And
- PCEQB : Parallel Compare for Equal Byte
- PCEQH : Parallel Compare for Equal Halfword
- PCEQW : Parallel Compare for Equal Word
- PCGTB : Parallel Compare for Greater Than Byte
- PCGTH : Parallel Compare for Greater Than Halfword
- PCGTW : Parallel Compare for Greater Than Word
- PCPYH : Parallel Copy Halfword
- PCPYLD : Parallel Copy Lower Doubleword
- PCPYUD : Parallel Copy Upper Doubleword
- PDIVBW : Parallel Divide Broadcast Word
- PDIVUW : Parallel Divide Unsigned Word
- PDIVW : Parallel Divide Word
- PEXCH : Parallel Exchange Center Halfword
- PEXCW : Parallel Exchange Center Word
- PEXEH : Parallel Exchange Even Halfword
- PEXEW : Parallel Exchange Even Word
- PEXT5 : Parallel Extend from 5 bits
- PEXTLB : Parallel Extend Lower from Byte
- PEXTLH : Parallel Extend Lower from Halfword
- PEXTLW : Parallel Extend Lower from Word
- PEXTUB : Parallel Extend Upper from Byte
- PEXTUH : Parallel Extend Upper from Halfword
- PEXTUW : Parallel Extend Upper from Word
- PHMADH : Parallel Horizontal Multiply-Add Halfword
- PHMSBH : Parallel Horizontal Multiply-Subtract Halfword
- PINTEH : Parallel Interleave Even Halfword
- PINTH : Parallel Interleave Halfword
- PLZCW : Parallel Leading Zero or one Count Word
- PMADDH : Parallel Multiply-Add Halfword
- PMADDUW : Parallel Multiply-Add Unsigned Word
- PMADDW : Parallel Multiply-Add Word
- PMAXH : Parallel Maximize Halfword
- PMAXW : Parallel Maximize Word
- PMFHI : Parallel Move From HI Register
- PMFHL.LH : Parallel Move From HI/LO Register
- PMFHL.LW : Parallel Move From HI/LO Register
- PMFHL.SH : Parallel Move From HI/LO Register
- PMFHL.SLW : Parallel Move From HI/LO Register
- PMFHL.UW : Parallel Move From HI/LO Register
- PMFLO : Parallel Move From LO Register
- PMINH : Parallel Minimize Halfword
- PMINW : Parallel Minimize Word
- PMSUBH : Parallel Multiply-Subtract Halfword
- PMSUBW : Parallel Multiply-Subtract Word
- PMTHI : Parallel Move To HI Register
- PMTHL.LW : Parallel Move To HI/LO Register
- PMTLO : Parallel Move To LO Register
- PMULTH : Parallel Multiply Halfword
- PMULTUW : Parallel Multiply Unsigned Word
- PMULTW : Parallel Multiply Word
- PNOR : Parallel Not Or
- POR : Parallel Or
- PPAC5 : Parallel Pack to 5 bits
- PPACB : Parallel Pack to Byte
- PPACH : Parallel Pack to Halfword
- PPACW : Parallel Pack to Word
- PREVH : Parallel Reverse Halfword
- PROT3W : Parallel Rotate 3 Words Left
- PSLLH : Parallel Shift Left Logical Halfword
- PSLLVW : Parallel Shift Left Logical Variable Word
- PSLLW : Parallel Shift Left Logical Word
- PSRAH : Parallel Shift Right Arithmetic Halfword
- PSRAVW : Parallel Shift Right Arithmetic Variable Word
- PSRAW : Parallel Shift Right Arithmetic Word
- PSRLH : Parallel Shift Right Logical Halfword
- PSRLVW : Parallel Shift Right Logical Variable Word
- PSRLW : Parallel Shift Right Logical Word
- PSUBB : Parallel Subtract Byte
- PSUBH : Parallel Subtract Halfword
- PSUBSB : Parallel Subtract with Signed saturation Byte
- PSUBSH : Parallel Subtract with Signed Saturation Halfword
- PSUBSW : Parallel Subtract with Signed Saturation Word
- PSUBUB : Parallel Subtract with Unsigned Saturation Byte
- PSUBUH : Parallel Subtract with Unsigned Saturation Halfword
- PSUBUW : Parallel Subtract with Unsigned Saturation Word
- PSUBW : Parallel Subtract Word
- PXOR : Parallel Exclusive OR
- QFSRV : Quadword Funnel Shift Right Variable
- SQ : Store Quadword
- System Control Coprocessor (COP0) Instruction Set
- BC0F : Branch on Coprocessor 0 False
- BC0FL : Branch on Coprocessor 0 False Likely
- BC0T : Branch on Coprocessor 0 True
- BC0TL : Branch on Coprocessor 0 True Likely
- CACHE BFH : Cache Operation (BTAC Flush)
- CACHE BHINBT : Cache Operation (Hit Invalidate BTAC)
- CACHE BXLBT : Cache Operation (Index Load BTAC)
- CACHE BXSBT : Cache Operation (Index Store BTAC)
- CACHE DHIN : Cache Operation (Hit Invalidate)
- CACHE DHWBIN : Cache Operation (Hit Writeback Invalidate)
- CACHE DHWOIN : Cache Operation (Hit Writeback Without Invalidate)
- CACHE DXIN : Cache Operation (Index Invalidate)
- CACHE DXLDT : Cache Operation (Index Load Data)
- CACHE DXLTG : Cache Operation (Index Load Tag)
- CACHE DXSDT : Cache Operation (Index Store Data)
- CACHE DXSTG : Cache Operation (Index Store Tag)
- CACHE DXWBIN : Cache Operation (Index Writeback Invalidate)
- CACHE IFL : Cache Operation (Fill)
- CACHE IHIN : Cache Operation (Hit Invalidate)
- CACHE IXIN : Cache Operation (Index Invalidate)
- CACHE IXLDT : Cache Operation (Index Load Data)
- CACHE IXLTG : Cache Operation (Index Load Tag)
- CACHE IXSDT : Cache Operation (Index Store Data)
- CACHE IXSTG : Cache Operation (Index Store Tag)
- DI : Disable Interrupt
- EI : Enable Interrupt
- ERET : Exception Return
- MFBPC : Move from Breakpoint Control Register
- MFC0 : Move from System Control Coprocessor
- MFDAB : Move from Data Address Breakpoint Register
- MFDABM : Move from Data Address Breakpoint Mask Register
- MFDVB : Move from Data value Breakpoint Register
- MFDVBM : Move from Data Value Breakpoint Mask Register
- MFIAB : Move from Instruction Address Breakpoint Register
- MFIABM : Move from Instruction Address Breakpoint Mask Register
- MFPC : Move from Performance Counter
- MFPS : Move from Performance Event Specifier
- MTBPC : Move to Breakpoint Control Register
- MTC0 : Move to System Control Coprocessor
- MTDAB : Move to Data Address Breakpoint Register
- MTDABM : Move to Data Address Breakpoint Mask Register
- MTDVB : Move to Data Value Breakpoint Register
- MTDVBM : Move to Data Value Breakpoint Mask Register
- MTIAB : Move to Instruction Address Breakpoint Register
- MTIABM : Move to Instruction Address Breakpoint Mask Register
- MTPC : Move to Performance Counter
- MTPS : Move to Performance Event Specifier
- TLBP : Probe TLB for Matching Entry
- TLBR : Read Indexed TLB Entry
- TLBWI : Write Index TLB Entry
- TLBWR : Write Random TLB Entry
- COP1 (FPU) Instruction Set
- ABS.S : Floating Point Absolute Value
- ADD.S : Floating Point ADD
- ADDA.S : Floating Point Add to Accumulator
- BC1F : Branch on FP False
- BC1FL : Branch on FP False Likely
- BC1T : Branch on FP True
- BC1TL : Branch on FP True Likely
- C.EQ.S : Floating Point Compare
- C.F.S : Floating Point Compare
- C.LE.S : Floating Point Compare
- C.LT.S : Floating Point Compare
- CFC1 : Move Control Word from Floating Point
- CTC1 : Move Control Word to Floating Point
- CVT.S.W : Fixed-point Convert to Single Floating Point
- CVT.W.S : Floating Point Convert to Word Fixed-point
- DIV.S : Floating Point Divide
- LWC1 : Load Word to Floating Point
- MADD.S : Floating Point Multiply-ADD
- MADDA.S : Floating Point Multiply-Add
- MAX.S : Floating Point Maximum
- MFC1 : Move Word from Floating Point
- MIN.S : Floating Point Minimum
- MOV.S : Floating Point Move
- MSUB.S : Floating Point Multiply and Subtract
- MSUBA.S : Floating Point Multiply and Subtract from Accumulator
- MTC1 : Move Word to Floating Point
- MUL.S : Floating Point Multiply
- MULA.S : Floating Point Multiply to Accumulator
- NEG.S : Floating Point Negate
- RSQRT.S : Floating Point Reciprocal Square Root
- SQRT.S : Floating Point Square Root
- SUB.S : Floating Point Subtract
- SUBA.S : Floating Point Subtract to Accumulator
- SWC1 : Store Word from Floating Point
- Appendix Instruction Set List
- Computational Instructions
- Integer Addition and Subtraction
- Floating Point Addition and Subtraction
- Integer Multiplication and Division
- Floating Point Multiplication and Division
- Integer Multiply-Add
- Floating Point Multiply-Add
- Shift Operation
- Logical Operation
- Comparison Operation
- Maximum / Minimum Value
- Data Format Conversion
- Exchange
- Random Number
- Other Operations
- Data Transfer Instructions
- Program Control Instructions
- Other Instructions
- Computational Instructions
- Appendix OpCode Encoding