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EE Core Instruction Set Manual

Copyright © 2002 Sony Computer Entertainment Inc.
All Rights Reserved.
SCE Confidential

SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

© 2002 Sony Computer Entertainment Inc.
Publication date: April 2002
Sony Computer Entertainment Inc.
1-1, Akasaka 7-chome, Minato-ku
Tokyo 107-0052 Japan
Sony Computer Entertainment America
919 East Hillsdale Blvd.
Foster City, CA 94404, U.S.A.
Sony Computer Entertainment Europe
30 Golden Square
London W1F 9LD, U.K.
The EE Core Instruction Set Manual is supplied pursuant to and subject to the terms of the Sony Computer
Entertainment PlayStation® license agreements.
The EE Core Instruction Set Manual is intended for distribution to and use by only Sony Computer
Entertainment licensed Developers and Publishers in accordance with the PlayStation® license agreements.
Unauthorized reproduction, distribution, lending, rental or disclosure to any third party, in whole or in part, of
this book is expressly prohibited by law and by the terms of the Sony Computer Entertainment PlayStation®
license agreements.
Ownership of the physical property of the book is retained by and reserved by Sony Computer Entertainment.
Alteration to or deletion, in whole or in part, of the book, its presentation, or its contents is prohibited.
The information in the EE Core Instruction Set Manual is subject to change without notice. The content of this
book is Confidential Information of Sony Computer Entertainment.
and PlayStation® are registered trademarks, and GRAPHICS SYNTHESIZERTM and
EMOTION ENGINETM are trademarks of Sony Computer Entertainment Inc. All other trademarks are property
of their respective owners and/or their licensors.
®

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About This Manual
The "EE Core Instruction Set Manual" is a comprehensive reference for the Emotion Engine instruction set.
- Chapter 1 "Notational Convention" describes the format used in this manual to describe the instructions.
- Chapter 2 "CPU Instruction Set" describes the 64-bit instructions that conform to the MIPS architecture, in
alphabetical order.
- Chapter 3 "EE Core-Specific Instruction Set" describes the instructions that are extensions to the MIPS
architecture, including 128-bit multimedia instructions, in alphabetical order.
- Chapter 4 "System Control Coprocessor (COP0) Instruction Set" describes the COP0 instructions, which
perform address translation, cache control, exception handling and breakpoint functions, in alphabetical
order.
- Chapter 5 "COP1 (FPU) Instruction Set" describes the COP1 instructions, which perform floating-point
operations, in alphabetical order. Note: the EE Core also executes COP2 instructions that perform fourparallel floating-point operations (vector operations). For COP2 instructions, refer to the "VU User's
Manual".
- Chapter 6 "Appendix" shows the instructions (including. COP2 instructions) classified by functions.
- Chapter 7 "Appendix" shows the instructions organized by bit pattern of the instruction codes.
Changes Since Release of 5th Edition
Since release of the 5th Edition of the EE Core Instruction Set Manual, the following changes have been made.
Note that each of these changes is indicated by a revision bar in the margin of the affected page.
Ch. 2: CPU Instruction Set
• A correction was made to “Operation” in the J instruction on page 65.
• A correction was made to “Operation” in the JAL instruction on page 66.
Ch. 3: EE Core-Specific Instruction Set
• Information was added to “Restrictions” in the DIVU1 instruction on page 140.
• A correction was made to “Description” in the MTSA instruction on page 151.
• Information was added to “Operation” in the PADDH instruction on page 161.
• A correction was made to the description (first paragraph) in the PINTEH instruction on page 213.
Ch. 5: COP1 (FPU) Instruction Set
• Information was added to “Description” in the BC1TL instruction on page 348.
• The “Restrictions” section was added to the CFC1 instruction on page 353.
• A correction was made to “Restrictions” in the CTC1 instruction on page 354.
• A correction was made to “Description” in the CVT.W.S instruction on page 356
• A correction was made to the “Operation Code” figure in the MIN.S instruction on page 365.

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Glossary
Term
EE
EE Core
COP0
COP1
COP2
GS
GIF
IOP
SBUS
VPU (VPU0/VPU1)
VU (VU0/VU1)
VIF (VIF0/VIF1)
VIFcode
SPR
IPU
word
qword
Slice
Packet
Transfer list
Tag
DMAtag
GS primitive
Context
GIFtag
Display list

Definition
Emotion Engine. CPU of the PlayStation 2.
Generalized computation and control unit of EE. Core of the CPU.
EE Core system control coprocessor.
EE Core floating-point operation coprocessor. Also referred to as FPU.
Vector operation unit coupled as a coprocessor of EE Core. VPU0.
Graphics Synthesizer.
Graphics processor connected to EE.
EE Interface unit to GS.
Processor connected to EE for controlling input/output devices.
Bus connecting EE to IOP.
Vector operation unit.
EE contains 2 VPUs: VPU0 and VPU1.
VPU core operation unit.
VPU data decompression unit.
Instruction code for VIF.
Quick-access data memory built into EE Core (Scratchpad memory).
EE Image processor unit.
Unit of data length: 32 bits
Unit of data length: 128 bits
Physical unit of DMA transfer: 8 qwords or less
Data to be handled as a logical unit for transfer processing.
A group of packets transferred in serial DMA transfer processing.
Additional data indicating data size and other attributes of packets.
Tag positioned first in DMA packet to indicate address/size of data and address
of the following packet.
Data to indicate image elements such as point and triangle.
A set of drawing information (e.g. texture, distant fog color, and dither matrix)
applied to two or more primitives uniformly. Also referred to as the drawing
environment.
Additional data to indicate attributes of GS primitives.
A group of GS primitives to indicate batches of images.

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Contents
1. Notational Convention ......................................................................................................................................................... 17
1.1. Instruction Format of Each Instruction ..................................................................................................................... 18
1.1.1. Mnemonic................................................................................................................................................................ 18
1.1.2. Instruction Encoding Picture ............................................................................................................................... 18
1.1.3. Format ..................................................................................................................................................................... 19
1.1.4. Description Section................................................................................................................................................ 19
1.1.5. Restrictions Section................................................................................................................................................ 19
1.1.6. Exception Section .................................................................................................................................................. 19
1.1.7. Operation Section .................................................................................................................................................. 19
1.1.8. Programming Notes Section................................................................................................................................. 19
1.2. Notational Convention of Pseudocode ...................................................................................................................... 20
1.2.1. Pseudocode Symbol ............................................................................................................................................... 20
1.2.2. Pseudocode Functions........................................................................................................................................... 20
2. CPU Instruction Set .............................................................................................................................................................. 23
ADD : Add Word ........................................................................................................................................................ 24
ADDI : Add Immediate Word................................................................................................................................... 25
ADDIU : Add Immediate Unsigned Word .............................................................................................................. 26
ADDU : Add Unsigned Word ................................................................................................................................... 27
AND : And ................................................................................................................................................................... 28
ANDI : Add Immediate .............................................................................................................................................. 29
BEQ : Branch on Equal .............................................................................................................................................. 30
BEQL : Branch on Equal Likely ................................................................................................................................ 31
BGEZ : Branch on Greater Than or Equal to Zero ............................................................................................... 32
BGEZAL : Branch on Greater Than or Equal to Zero and Link......................................................................... 33
BGEZALL : Branch on Greater Than or Equal to Zero and Link Likely........................................................... 34
BGEZL : Branch on Greater Than or Equal to Zero Likely................................................................................. 35
BGTZ : Branch on Greater Than Zero .................................................................................................................... 36
BGTZL : Branch on Greater Than Zero Likely ...................................................................................................... 37
BLEZ : Branch on Less Than or Equal to Zero...................................................................................................... 38
BLEZL : Branch on Less Than or Equal to Zero Likely ....................................................................................... 39
BLTZ : Branch on Less Than Zero........................................................................................................................... 40
BLTZAL : Branch on Less Than Zero and Link .................................................................................................... 41
BLTZALL : Branch on Less Than Zero and Link Likely ...................................................................................... 42
BLTZL : Branch on Less Than Zero Likely............................................................................................................. 43
BNE : Branch on Not Equal ...................................................................................................................................... 44
BNEL : Branch on Not Equal Likely........................................................................................................................ 45
BREAK : Breakpoint................................................................................................................................................... 46
DADD : Doubleword Add......................................................................................................................................... 47
DADDI : Doubleword Add Immediate ................................................................................................................... 48
DADDIU : Doubleword Add Immediate Unsigned .............................................................................................. 49
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DADDU : Doubleword Add Unsigned ....................................................................................................................50
DIV : Divide Word.......................................................................................................................................................51
DIVU : Divide Unsigned Word..................................................................................................................................53
DSLL : Doubleword Shift Left Logical .....................................................................................................................54
DSLL32 : Doubleword Shift Left Logical Plus 32...................................................................................................55
DSLLV : Doubleword Shift Left Logical Variable ..................................................................................................56
DSRA : Doubleword Shift Right Arithmetic............................................................................................................57
DSRA32 : Doubleword Shift Right Arithmetic Plus 32..........................................................................................58
DSRAV : Doubleword Shift Right Arithmetic Variable .........................................................................................59
DSRL : Doubleword Shift Right Logical...................................................................................................................60
DSRL32 : Doubleword Shift Right Logical Plus 32 ................................................................................................61
DSRLV : Doubleword Shift Right Logical Variable................................................................................................62
DSUB : Doubleword Subtract ....................................................................................................................................63
DSUBU : Doubleword Subtract Unsigned ...............................................................................................................64
J : Jump...........................................................................................................................................................................65
JAL : Jump and Link ....................................................................................................................................................66
JALR : Jump and Link Register ..................................................................................................................................67
JR : Jump Register.........................................................................................................................................................68
LB : Load Byte ..............................................................................................................................................................69
LBU : Load Byte Unsigned .........................................................................................................................................70
LD : Load Doubleword ...............................................................................................................................................71
LDL : Load Doubleword Left ....................................................................................................................................72
LDR : Load Doubleword Right..................................................................................................................................74
LH : Load Halfword.....................................................................................................................................................76
LHU : Load Halfword Unsigned................................................................................................................................77
LUI : Load Upper Immediate .....................................................................................................................................78
LW : Load Word...........................................................................................................................................................79
LWL : Load Word Left................................................................................................................................................80
LWR : Load Word Right .............................................................................................................................................82
LWU : Load Word Unsigned......................................................................................................................................84
MFHI : Move from HI Register .................................................................................................................................85
MFLO : Move from LO Register...............................................................................................................................86
MOVN : Move Conditional on Not Zero ................................................................................................................87
MOVZ : Move Conditional on Zero .........................................................................................................................88
MTHI : Move to HI Register......................................................................................................................................89
MTLO : Move to LO Register....................................................................................................................................90
MULT : Multiply Word................................................................................................................................................91
MULTU : Multiply Unsigned Word...........................................................................................................................92
NOR : Not Or...............................................................................................................................................................93
OR : Or ..........................................................................................................................................................................94
ORI : Or immediate .....................................................................................................................................................95
PREF : Prefetch ............................................................................................................................................................96
SB : Store Byte...............................................................................................................................................................97
SD : Store Doubleword ...............................................................................................................................................98
SDL : Store Doubleword Left.....................................................................................................................................99
SDR : Store Doubleword Right ............................................................................................................................... 101
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SH : Store Halfword ..................................................................................................................................................103
SLL : Shift Word Left Logical ..................................................................................................................................104
SLLV : Shift Word Left Logical Variable................................................................................................................105
SLT : Set on Less Than .............................................................................................................................................106
SLTI : Set on Less Than Immediate........................................................................................................................107
SLTIU : Set on Less Than Immediate Unsigned...................................................................................................108
SLTU : Set on Less Than Unsigned ........................................................................................................................109
SRA : Shift Word Right Arithmetic .........................................................................................................................110
SRAV : Shift Word Right Arithmetic Variable.......................................................................................................111
SRL : Shift Word Right Logical................................................................................................................................112
SRLV : Shift Word Right Logical Variable .............................................................................................................113
SUB : Subtract Word .................................................................................................................................................114
SUBU : Subtract Unsigned Word ............................................................................................................................115
SW : Store Word.........................................................................................................................................................116
SWL : Store Word Left..............................................................................................................................................117
SWR : Store Word Right ...........................................................................................................................................119
SYNC.stype : Synchronize Shared Memory ...........................................................................................................121
SYSCALL : System Call.............................................................................................................................................122
TEQ : Trap if Equal...................................................................................................................................................123
TEQI : Trap if Equal Immediate .............................................................................................................................124
TGE : Trap if Greater or Equal ...............................................................................................................................125
TGEI : Trap if Greater or Equal Immediate..........................................................................................................126
TGEIU : Trap if Greater or Equal Immediate Unsigned.....................................................................................127
TGEU : Trap if Greater or Equal Unsigned ..........................................................................................................128
TLT : Trap if Less Than............................................................................................................................................129
TLTI : Trap if Less Than Immediate ......................................................................................................................130
TLTIU : Trap if Less Than Immediate Unsigned .................................................................................................131
TLTU : Trap if Less Than Unsigned.......................................................................................................................132
TNE : Trap if Not Equal ..........................................................................................................................................133
TNEI : Trap if Not Equal Immediate.....................................................................................................................134
XOR : Exclusive OR .................................................................................................................................................135
XORI : Exclusive OR Immediate............................................................................................................................136
3. EE Core-Specific Instruction Set ......................................................................................................................................137
DIV1 : Divide Word Pipeline 1................................................................................................................................138
DIVU1 : Divide Unsigned Word Pipeline 1...........................................................................................................140
LQ : Load Quadword ................................................................................................................................................141
MADD : Multiply-Add word....................................................................................................................................142
MADD1 : Multiply-Add word Pipeline 1 ...............................................................................................................143
MADDU : Multiply-Add Unsigned word...............................................................................................................144
MADDU1 : Multiply-Add Unsigned word Pipeline 1 ..........................................................................................145
MFHI1 : Move From HI1 Register .........................................................................................................................146
MFLO1 : Move From LO1 Register .......................................................................................................................147
MFSA : Move from Shift Amount Register ...........................................................................................................148
MTHI1 : Move To HI1 Register..............................................................................................................................149
MTLO1 : Move To LO1 Register............................................................................................................................150
MTSA : Move to Shift Amount Register ................................................................................................................151
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MTSAB : Move Byte Count to Shift Amount Register........................................................................................ 152
MTSAH : Move Halfword Count to Shift Amount Register .............................................................................. 153
MULT : Multiply Word............................................................................................................................................. 154
MULT1 : Multiply Word Pipeline 1 ........................................................................................................................ 155
MULTU : Multiply Unsigned Word........................................................................................................................ 156
MULTU1 : Multiply Unsigned Word Pipeline 1 ................................................................................................... 157
PABSH : Parallel Absolute Halfword ..................................................................................................................... 158
PABSW : Parallel Absolute Word ........................................................................................................................... 159
PADDB : Parallel Add Byte..................................................................................................................................... 160
PADDH : Parallel Add Halfword ........................................................................................................................... 161
PADDSB : Parallel Add with Signed Saturation Byte .......................................................................................... 162
PADDSH : Parallel Add with Signed Saturation Halfword................................................................................. 164
PADDSW : Parallel Add with Signed Saturation Word....................................................................................... 166
PADDUB : Parallel Add with Unsigned Saturation Byte .................................................................................... 168
PADDUH : Parallel Add with Unsigned Saturation Halfword........................................................................... 170
PADDUW : Parallel Add with Unsigned Saturation Word................................................................................. 172
PADDW : Parallel Add Word.................................................................................................................................. 174
PADSBH : Parallel Add/Subtract Halfword ......................................................................................................... 175
PAND : Parallel And................................................................................................................................................. 176
PCEQB : Parallel Compare for Equal Byte ........................................................................................................... 177
PCEQH : Parallel Compare for Equal Halfword.................................................................................................. 179
PCEQW : Parallel Compare for Equal Word........................................................................................................ 181
PCGTB : Parallel Compare for Greater Than Byte .............................................................................................. 183
PCGTH : Parallel Compare for Greater Than Halfword .................................................................................... 185
PCGTW : Parallel Compare for Greater Than Word........................................................................................... 187
PCPYH : Parallel Copy Halfword ........................................................................................................................... 189
PCPYLD : Parallel Copy Lower Doubleword....................................................................................................... 190
PCPYUD : Parallel Copy Upper Doubleword ...................................................................................................... 191
PDIVBW : Parallel Divide Broadcast Word.......................................................................................................... 192
PDIVUW : Parallel Divide Unsigned Word .......................................................................................................... 194
PDIVW : Parallel Divide Word ............................................................................................................................... 196
PEXCH : Parallel Exchange Center Halfword...................................................................................................... 198
PEXCW : Parallel Exchange Center Word ............................................................................................................ 199
PEXEH : Parallel Exchange Even Halfword ........................................................................................................ 200
PEXEW : Parallel Exchange Even Word .............................................................................................................. 201
PEXT5 : Parallel Extend from 5 bits ...................................................................................................................... 202
PEXTLB : Parallel Extend Lower from Byte ........................................................................................................ 203
PEXTLH : Parallel Extend Lower from Halfword .............................................................................................. 204
PEXTLW : Parallel Extend Lower from Word..................................................................................................... 205
PEXTUB : Parallel Extend Upper from Byte........................................................................................................ 206
PEXTUH : Parallel Extend Upper from Halfword.............................................................................................. 207
PEXTUW : Parallel Extend Upper from Word .................................................................................................... 208
PHMADH : Parallel Horizontal Multiply-Add Halfword.................................................................................... 209
PHMSBH : Parallel Horizontal Multiply-Subtract Halfword .............................................................................. 211
PINTEH : Parallel Interleave Even Halfword ...................................................................................................... 213
PINTH : Parallel Interleave Halfword.................................................................................................................... 214
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PLZCW : Parallel Leading Zero or one Count Word...........................................................................................215
PMADDH : Parallel Multiply-Add Halfword ........................................................................................................216
PMADDUW : Parallel Multiply-Add Unsigned Word .........................................................................................218
PMADDW : Parallel Multiply-Add Word ..............................................................................................................220
PMAXH : Parallel Maximize Halfword ..................................................................................................................222
PMAXW : Parallel Maximize Word.........................................................................................................................224
PMFHI : Parallel Move From HI Register .............................................................................................................226
PMFHL.LH : Parallel Move From HI/LO Register.............................................................................................227
PMFHL.LW : Parallel Move From HI/LO Register ............................................................................................228
PMFHL.SH : Parallel Move From HI/LO Register .............................................................................................229
PMFHL.SLW : Parallel Move From HI/LO Register ..........................................................................................231
PMFHL.UW : Parallel Move From HI/LO Register............................................................................................233
PMFLO : Parallel Move From LO Register...........................................................................................................234
PMINH : Parallel Minimize Halfword ....................................................................................................................235
PMINW : Parallel Minimize Word ..........................................................................................................................237
PMSUBH : Parallel Multiply-Subtract Halfword ...................................................................................................239
PMSUBW : Parallel Multiply-Subtract Word .........................................................................................................241
PMTHI : Parallel Move To HI Register..................................................................................................................243
PMTHL.LW : Parallel Move To HI/LO Register.................................................................................................244
PMTLO : Parallel Move To LO Register ...............................................................................................................245
PMULTH : Parallel Multiply Halfword...................................................................................................................246
PMULTUW : Parallel Multiply Unsigned Word....................................................................................................248
PMULTW : Parallel Multiply Word.........................................................................................................................250
PNOR : Parallel Not Or............................................................................................................................................252
POR : Parallel Or .......................................................................................................................................................253
PPAC5 : Parallel Pack to 5 bits ................................................................................................................................254
PPACB : Parallel Pack to Byte .................................................................................................................................256
PPACH : Parallel Pack to Halfword........................................................................................................................257
PPACW : Parallel Pack to Word ..............................................................................................................................258
PREVH : Parallel Reverse Halfword.......................................................................................................................259
PROT3W : Parallel Rotate 3 Words Left................................................................................................................260
PSLLH : Parallel Shift Left Logical Halfword........................................................................................................261
PSLLVW : Parallel Shift Left Logical Variable Word ...........................................................................................262
PSLLW : Parallel Shift Left Logical Word..............................................................................................................263
PSRAH : Parallel Shift Right Arithmetic Halfword...............................................................................................264
PSRAVW : Parallel Shift Right Arithmetic Variable Word ..................................................................................265
PSRAW : Parallel Shift Right Arithmetic Word.....................................................................................................266
PSRLH : Parallel Shift Right Logical Halfword .....................................................................................................267
PSRLVW : Parallel Shift Right Logical Variable Word.........................................................................................268
PSRLW : Parallel Shift Right Logical Word ...........................................................................................................269
PSUBB : Parallel Subtract Byte ................................................................................................................................270
PSUBH : Parallel Subtract Halfword.......................................................................................................................271
PSUBSB : Parallel Subtract with Signed saturation Byte ......................................................................................272
PSUBSH : Parallel Subtract with Signed Saturation Halfword ............................................................................274
PSUBSW : Parallel Subtract with Signed Saturation Word ..................................................................................276
PSUBUB : Parallel Subtract with Unsigned Saturation Byte................................................................................278
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PSUBUH : Parallel Subtract with Unsigned Saturation Halfword...................................................................... 280
PSUBUW : Parallel Subtract with Unsigned Saturation Word............................................................................ 282
PSUBW : Parallel Subtract Word............................................................................................................................. 284
PXOR : Parallel Exclusive OR................................................................................................................................. 285
QFSRV : Quadword Funnel Shift Right Variable................................................................................................. 286
SQ : Store Quadword................................................................................................................................................ 287
4. System Control Coprocessor (COP0) Instruction Set ................................................................................................... 289
BC0F : Branch on Coprocessor 0 False ................................................................................................................. 290
BC0FL : Branch on Coprocessor 0 False Likely ................................................................................................... 291
BC0T : Branch on Coprocessor 0 True.................................................................................................................. 292
BC0TL : Branch on Coprocessor 0 True Likely.................................................................................................... 293
CACHE BFH : Cache Operation (BTAC Flush).................................................................................................. 294
CACHE BHINBT : Cache Operation (Hit Invalidate BTAC) ........................................................................... 295
CACHE BXLBT : Cache Operation (Index Load BTAC).................................................................................. 296
CACHE BXSBT : Cache Operation (Index Store BTAC) .................................................................................. 297
CACHE DHIN : Cache Operation (Hit Invalidate)............................................................................................. 298
CACHE DHWBIN : Cache Operation (Hit Writeback Invalidate)................................................................... 299
CACHE DHWOIN : Cache Operation (Hit Writeback Without Invalidate)................................................... 300
CACHE DXIN : Cache Operation (Index Invalidate)......................................................................................... 301
CACHE DXLDT : Cache Operation (Index Load Data).................................................................................... 302
CACHE DXLTG : Cache Operation (Index Load Tag) ..................................................................................... 303
CACHE DXSDT : Cache Operation (Index Store Data).................................................................................... 304
CACHE DXSTG : Cache Operation (Index Store Tag)...................................................................................... 305
CACHE DXWBIN : Cache Operation (Index Writeback Invalidate)............................................................... 306
CACHE IFL : Cache Operation (Fill) .................................................................................................................... 307
CACHE IHIN : Cache Operation (Hit Invalidate)............................................................................................... 308
CACHE IXIN : Cache Operation (Index Invalidate)........................................................................................... 309
CACHE IXLDT : Cache Operation (Index Load Data) ..................................................................................... 310
CACHE IXLTG : Cache Operation (Index Load Tag) ....................................................................................... 311
CACHE IXSDT : Cache Operation (Index Store Data)...................................................................................... 312
CACHE IXSTG : Cache Operation (Index Store Tag) ....................................................................................... 313
DI : Disable Interrupt ............................................................................................................................................... 314
EI : Enable Interrupt................................................................................................................................................. 315
ERET : Exception Return........................................................................................................................................ 316
MFBPC : Move from Breakpoint Control Register.............................................................................................. 317
MFC0 : Move from System Control Coprocessor ................................................................................................ 318
MFDAB : Move from Data Address Breakpoint Register................................................................................... 319
MFDABM : Move from Data Address Breakpoint Mask Register .................................................................... 320
MFDVB : Move from Data value Breakpoint Register........................................................................................ 321
MFDVBM : Move from Data Value Breakpoint Mask Register......................................................................... 322
MFIAB : Move from Instruction Address Breakpoint Register ......................................................................... 323
MFIABM : Move from Instruction Address Breakpoint Mask Register ........................................................... 324
MFPC : Move from Performance Counter............................................................................................................ 325
MFPS : Move from Performance Event Specifier ................................................................................................ 326
MTBPC : Move to Breakpoint Control Register................................................................................................... 327
MTC0 : Move to System Control Coprocessor..................................................................................................... 328
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MTDAB : Move to Data Address Breakpoint Register............................................................................................329
MTDABM : Move to Data Address Breakpoint Mask Register..............................................................................330
MTDVB : Move to Data Value Breakpoint Register................................................................................................331
MTDVBM : Move to Data Value Breakpoint Mask Register..............................................................................332
MTIAB : Move to Instruction Address Breakpoint Register...............................................................................333
MTIABM : Move to Instruction Address Breakpoint Mask Register.................................................................334
MTPC : Move to Performance Counter .................................................................................................................335
MTPS : Move to Performance Event Specifier......................................................................................................336
TLBP : Probe TLB for Matching Entry..................................................................................................................337
TLBR : Read Indexed TLB Entry............................................................................................................................338
TLBWI : Write Index TLB Entry ............................................................................................................................339
TLBWR : Write Random TLB Entry ......................................................................................................................340
5. COP1 (FPU) Instruction Set..............................................................................................................................................341
ABS.S : Floating Point Absolute Value ...................................................................................................................342
ADD.S : Floating Point ADD..................................................................................................................................343
ADDA.S : Floating Point Add to Accumulator.....................................................................................................344
BC1F : Branch on FP False ......................................................................................................................................345
BC1FL : Branch on FP False Likely ........................................................................................................................346
BC1T : Branch on FP True.......................................................................................................................................347
BC1TL : Branch on FP True Likely ........................................................................................................................348
C.EQ.S : Floating Point Compare ...........................................................................................................................349
C.F.S : Floating Point Compare ...............................................................................................................................350
C.LE.S : Floating Point Compare ............................................................................................................................351
C.LT.S : Floating Point Compare.............................................................................................................................352
CFC1 : Move Control Word from Floating Point.................................................................................................353
CTC1 : Move Control Word to Floating Point......................................................................................................354
CVT.S.W : Fixed-point Convert to Single Floating Point ....................................................................................355
CVT.W.S : Floating Point Convert to Word Fixed-point.....................................................................................356
DIV.S : Floating Point Divide..................................................................................................................................357
LWC1 : Load Word to Floating Point.....................................................................................................................358
MADD.S : Floating Point Multiply-ADD ..............................................................................................................359
MADDA.S : Floating Point Multiply-Add..............................................................................................................361
MAX.S : Floating Point Maximum ..........................................................................................................................363
MFC1 : Move Word from Floating Point...............................................................................................................364
MIN.S : Floating Point Minimum............................................................................................................................365
MOV.S : Floating Point Move..................................................................................................................................366
MSUB.S : Floating Point Multiply and Subtract ....................................................................................................367
MSUBA.S : Floating Point Multiply and Subtract from Accumulator................................................................369
MTC1 : Move Word to Floating Point....................................................................................................................371
MUL.S : Floating Point Multiply..............................................................................................................................372
MULA.S : Floating Point Multiply to Accumulator ..............................................................................................373
NEG.S : Floating Point Negate................................................................................................................................374
RSQRT.S : Floating Point Reciprocal Square Root...............................................................................................375
SQRT.S : Floating Point Square Root .....................................................................................................................376
SUB.S : Floating Point Subtract ...............................................................................................................................377
SUBA.S : Floating Point Subtract to Accumulator................................................................................................378
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SWC1 : Store Word from Floating Point ............................................................................................................... 379
6. Appendix Instruction Set List ........................................................................................................................................... 381
6.1. Computational Instructions ....................................................................................................................................... 382
6.1.1. Integer Addition and Subtraction ...................................................................................................................... 382
6.1.2. Floating Point Addition and Subtraction.......................................................................................................... 382
6.1.3. Integer Multiplication and Division .................................................................................................................. 383
6.1.4. Floating Point Multiplication and Division...................................................................................................... 383
6.1.5. Integer Multiply-Add........................................................................................................................................... 384
6.1.6. Floating Point Multiply-Add .............................................................................................................................. 384
6.1.7. Shift Operation..................................................................................................................................................... 384
6.1.8. Logical Operation ................................................................................................................................................ 385
6.1.9. Comparison Operation ....................................................................................................................................... 385
6.1.10. Maximum / Minimum Value ........................................................................................................................... 386
6.1.11. Data Format Conversion.................................................................................................................................. 386
6.1.12. Exchange............................................................................................................................................................. 386
6.1.13. Random Number............................................................................................................................................... 387
6.1.14. Other Operations............................................................................................................................................... 387
6.2. Data Transfer Instructions......................................................................................................................................... 388
6.2.1. Instructions for Transferring between Registers ............................................................................................. 388
6.2.2. Load....................................................................................................................................................................... 388
6.2.3. Store....................................................................................................................................................................... 389
6.2.4. Special Data Transfer .......................................................................................................................................... 389
6.3. Program Control Instructions ................................................................................................................................... 391
6.3.1. Conditional Branch.............................................................................................................................................. 391
6.3.2. Jump ...................................................................................................................................................................... 391
6.3.3. Subroutine Call..................................................................................................................................................... 391
6.3.4. Break / Trap......................................................................................................................................................... 392
6.4. Other Instructions....................................................................................................................................................... 393
7. Appendix OpCode Encoding............................................................................................................................................ 395
7.1. CPU Instructions......................................................................................................................................................... 396
7.1.1. Instructions encoded by OpCode field............................................................................................................. 396
7.1.2. SPECIAL Instruction Class................................................................................................................................ 397
7.1.3. REGIMM Instruction Class............................................................................................................................... 398
7.2. EE Core-Specific Instructions................................................................................................................................... 399
7.2.1. MMI Instruction Class ........................................................................................................................................ 399
7.2.2. MMI0 Instruction Class ...................................................................................................................................... 400
7.2.3. MMI1 Instruction Class ...................................................................................................................................... 401
7.2.4. MMI2 Instruction Class ...................................................................................................................................... 402
7.2.5. MMI3 Instruction Class ...................................................................................................................................... 403
7.3. COP0 Instructions ...................................................................................................................................................... 404
7.3.1. COP0 Instruction Class ...................................................................................................................................... 404
7.3.2. BC0 Instruction Class.......................................................................................................................................... 404
7.3.3. C0 Instruction Class ............................................................................................................................................ 405
7.4. COP1 Instructions ...................................................................................................................................................... 406
7.4.1. COP1 Instruction Class ...................................................................................................................................... 406
7.4.2. BC1 Instruction Class.......................................................................................................................................... 406
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7.4.3. S Instruction Class................................................................................................................................................407
7.4.4. W Instruction Class..............................................................................................................................................408

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1. Notational Convention

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1.1. Instruction Format of Each Instruction
The description of each instruction uses the following format.

AD D : Add W ord
M IP S I
To add 32-bit integers. Traps if overflow occurs.

O peration C ode
31

26

25

21

20

16

15

11

10

6

5

0

SPEC IA L
000000

rs

rt

rd

0
00000

ADD
100000

6

5

5

5

5

6

Form at
A D D rd, rs, rt

D escription
G PR[rd] ← G PR[rs] + G PR[rt]
A dds the 32-bit value in G PR[rt] to the 32-bit value in G PR[rs]. The result is stored in G PR[rd]. If
the addition results in 32-bit 2’s com plem ent overflow , then the contents of G PR[rd] are not
changed and an Integer O verflow exception occurs.

R estrictions
If G PR[rt] and G PR[rs] are not sign-extended 32-bit values (bits 63..31 equal), then the result of the
operation is undefined.

Exceptions
Integer O verflow

O peration
If (N otW ordV alue(G PR[rs] 63..0) or N otW ordV alue(G PR[rt] 63..0)) then U ndefinedResult() endif
tem p ← G PR[rs] 63..0 + G PR [rt] 63..0
if (32_bit_arithm etic_overflow ) then
SignalException (IntegerO verflow )
else
G PR[rd]63..0 ← sign_extend(tem p31..0)
endif

Program m ing N otes
A D D U perform s the sam e arithm etic operation but does not trap on overflow .

1.1.1. Mnemonic
Page headings show the instruction mnemonic, a brief description of the function, and the MIPS architecture
level. "EE Core" indicates the EE Core-specific instructions. Of these instructions, those that use 128-bit
registers are described as "128-bit MMI".

1.1.2. Instruction Encoding Picture
This picture illustrates the bit formats of an instruction word. Upper case and lower case in the field names
indicate constant fields and opcode fields, and variable fields respectively. Unused fields whose values are fixed
to zero are shown by "0".
The numbers above the field name indicates bit positions and the number below the field name indicates the
field width.

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1.1.3. Format
This section indicates the instruction formats for the assembler. Lower case indicates variables, corresponding to
variable fields in the encoding picture.

1.1.4. Description Section
This section describes the instruction function and operation. If possible, the outline of the operation is
expressed in one-line pseudocode. The notational conventions of pseudocode are described later.

1.1.5. Restrictions Section
This section shows the restrictions on instruction execution. These include alignment for memory addresses, the
range of valid values of operands, order of execution with other instructions, and so on.

1.1.6. Exception Section
This section shows the exceptions that can be caused by the instructions. However, it omits exceptions caused
by instruction fetch, performance counters, breakpoints, asynchronous external events (e.g. interrupt) and Bus
Error.

1.1.7. Operation Section
This section describes the instruction operations in pseudocode, resembling Pascal. The notational conventions
of pseudocode are described later.

1.1.8. Programming Notes Section
This section shows the supplementary information about programming when using the instruction.

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1.2. Notational Convention of Pseudocode
The "Description" and "Operation" sections describe the operations that each instruction performs using a
pseudocode resembling Pascal. The notational conventions of the pseudocode are as follows.

1.2.1. Pseudocode Symbol
Special symbols used in the pseudocode notation are as follows.
Symbol
Meaning
Assignment.
←
Tests of equality and inequality.
= ≠
||
Bit string concatenation.
Xy
Bit string formed by y copies of 1-bit value X.
Xy..z
Substring of bit-y through bit-z of bit string X.
+X
DIV
MOD
/
<
NOT
NOR
XOR
AND
OR
GPRLEN
GPR[x]
HI0,LO0
HI1,LO1
HI,LO
CPR[z,x]
CCR[z,x]
CPCOND[z]
I:,
I+1:
PC

PSIZE

Two's complement or floating point add and subtraction.
Two's complement or floating point multiplication.
Two's complement integer division.
Two's complement modulo.
Floating point division.
Two's complement comparison operation (less than).
Bitwise logical NOT.
Bitwise logical NOR.
Bitwise logical XOR.
Bitwise logical AND.
Bitwise logical OR.
The length in bits of the CPU general purpose registers.
CPU general purpose register x.
Lower 64 bits of both HI and LO registers that are extended to 128 bits.
Upper 64 bits of both HI and LO registers that are extended to 128 bits.
128-bit HI and LO registers.
If clear in the context, HI0 and LO0 registers may be described as simply HI and LO
according to the existing MIPS term.
General purpose register x of Coprocessor unit z
Control register x of Coprocessor unit z
Conditional signal of Coprocessor unit z
Label
When the timing between the instruction operation and the operation prior to and
subsequent to the instruction is required to be stipulated (e.g. the branch delay slot during
the branch instruction), it is shown in the beginning of each line.
The Program Counter Value.
It is the address of the instruction word and automatically incremented by 4 every time
an instruction is executed. When any values are assigned to a pseudocode, the instruction
in the address is performed following the instruction in the branch delay slot.
Bit length of Physical address (=32)

1.2.2. Pseudocode Functions
The main functions used in the pseudocode are described below.

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(pAddr, CCA) ← AddressTranslation (vAddr, IorD, LorS)
Address Translation
pAddr:
Physical Address
CCA:
Cache Coherence Algorithm
vAddr:
Virtual Address
IorD:
Instruction access or Data access
LorS:
Load access or Store access
Translates a virtual address to a physical address and cache coherence algorithm (that determines which
cache line is used). If the virtual address is in the unmapped address space, the physical address and CCA are
determined directly by the virtual address. If the virtual address is in the mapped address space, the TLB is
used to determine the physical address and CCA. An exception is taken if a page fault or a breach of access
right occurs.
MemElem ← LoadMemory(CCA, AccessLength, pAddr, vAddr, IorD)
Loads Data
MemElem:
Data that is aligned with 128-bit width
CCA:
Cache Coherence Algorithm
AccessLength:
Data Size (in bytes)
pAddr:
Physical Address
vAddr:
Virtual Address
IorD:
Instruction access or Data access
Loads a value from memory.
Uses the address of the minimum value of the byte addresses in the data object. The low-order 2 to 4 bits,
together with AccessLength, indicate which bytes within MemElem are given to the processor. If the access
is an uncached type, only applicable bytes are read from memory and valid within MemElem. If the access is
a cached type and the data is not present in the cache, data of the cache line size is read from memory.
StoreMemory (CCA, AccessLength, MemElem, pAddr, vAddr)
CCA:
Cache Coherence Algorithm
AccessLength:
Data Size (in bytes)
MemElem:
128-bit Data
pAddr:
Physical Address
vAddr:
Virtual Address
Store a value to memory.
MemElem is aligned to fixed-width data. If the store is partial, only applicable bytes are valid. The low-order
three bits of pAddr and AccessLength indicate the valid bytes.
SignalException (Exception)
Exception; The exception condition that exists.
Sends exception condition signals. An exception that suspends the instruction occurs and the pseudocode
does not return from this function call.
UndefinedResult()
Indicates that the result of the operation is undefined.
NullifyCurrentInstruction ()
Nullifies the present instruction. The instructions in the delay slot of Branch-Likely instructions are nullified
when not branching but is used for describing the operation.

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2. CPU Instruction Set
This chapter describes the instructions that can be performed in User mode, in alphabetical order. Instructions
shown in this chapter conform to the MIPS architecture and, the general-purpose registers are 64-bit wide.

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ADD : Add Word
MIPS I
To add 32-bit integers. Traps if overflow occurs.
Operation Code
31

26

25

21

20

16

15

11

10

6

5

0

SPECIAL
000000

rs

rt

rd

0
00000

ADD
100000

6

5

5

5

5

6

Format
ADD rd, rs, rt
Description
GPR[rd] ← GPR[rs] + GPR[rt]
Adds the 32-bit value in GPR[rt] to the 32-bit value in GPR[rs]. The result is stored in GPR[rd]. If the
addition results in 32-bit 2's complement overflow, then the contents of GPR[rd] are not changed and an
Integer Overflow exception occurs.
Restrictions
If GPR[rt] and GPR[rs] are not sign-extended 32-bit values (bits 63..31 equal), then the result of the
operation is undefined.
Exceptions
Integer Overflow
Operation
if (NotWordValue(GPR[rs] 63..0) or NotWordValue(GPR[rt] 63..0)) then UndefinedResult() endif
temp ← GPR[rs] 63..0 + GPR[rt] 63..0
if (32_bit_arithmetic_overflow) then
SignalException (IntegerOverflow)
else
GPR[rd]63..0 ← sign_extend(temp31..0)
endif
Programming Notes
ADDU performs the same arithmetic operation but does not trap on overflow.

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ADDI : Add Immediate Word
MIPS I
To add a constant to a 32-bit integer. Traps if overflow occurs.
Operation Code
31

26

25

21

20

16

15

0

SPECIAL
000000

rs

rt

immediate

6

5

5

16

Format
ADDI rt, rs, immediate
Description
GPR[rt] ← GPR[rs] + immediate
Adds the value of the immediate field as a 16-bit signed integer to the 32-bit integer value in GPR[rs]. The
result is stored in GPR[rt]. If the addition results in 32-bit 2's complement overflow, then the contents of
GPR[rt] are not changed and an Integer Overflow exception occurs.
Restrictions
If GPR[rs] is not a sign-extended 32-bit value (bits 63..31 equal), then the result of the operation is
undefined.
Exceptions
Integer Overflow
Operation
if(NotWordValue(GPR[rs] 63..0)) then UndefinedResult() endif
temp ← GPR[rs] 63..0 + sign_extend (immediate)
if (32_bit_arithmetic_overflow) then
SignalException (IntegerOverflow)
else
GPR[rt]63..0 ← sign_extend(temp31..0)
endif
Programming Notes
ADDIU performs the same arithmetic operation but does not trap on overflow.

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ADDIU : Add Immediate Unsigned Word
MIPS I
To add a constant to a 32-bit integer.
Operation Code
31

26

25

21

20

16

15

0

ADDIU
001001

rs

rt

immediate

6

5

5

16

Format
ADDIU rt, rs, immediate
Description
GPR[rt] ← GPR[rs] + immediate
Adds the value of the immediate field as a 16-bit signed integer to the 32-bit integer value in GPR[rs]. The
result is stored in GPR[rt]. If overflow occurs, it is ignored.
Restrictions
If GPR[rs] is not a sign-extended 32-bit value (bits 63..31 equal), then the result of the operation is
undefined.
Exceptions
None
Operation
if (NotWordValue(GPR[rs] 63..0)) then UndefinedResult() endif
temp ← GPR[rs] 63..0 + sign_extend(immediate)
GPR[rt] 63..0 ← sign_extend(temp31..0)
Programming Notes
This instruction is not an unsigned operation in the strict sense and performs 32-bit modulo arithmetic that
ignores overflow. It is appropriate for integer arithmetic that ignores overflow such as address or C language
arithmetic.

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ADDU : Add Unsigned Word
MIPS I
To add 32-bit integers.
Operation Code
31

26

25

21

20

16

15

11

10

6

5

0

SPECIAL
000000

rs

rt

rd

0
00000

ADDU
100001

6

5

5

5

5

6

Format
ADDU rd, rs, rt
Description
GPR[rd] ← GPR[rs] + GPR[rt]
Adds the 32-bit value in GPR[rt] to the 32-bit value in GPR[rs]. The result is stored in GPR[rd]. If overflow
occurs, it is ignored.
Restrictions
If GPR[rt] and GPR[rs] are not sign-extended 32-bit values (bits 63..31 equal), then the result of the
operation is undefined.
Exceptions
None
Operation
if (NotWordValue(GPR[rs] 63..0) or NotWordValue(GPR[rt] 63..0)) then UndefinedResult() endif
temp ← GPR[rs] 63..0 + GPR[rt] 63..0
GPR[rt] 63..0 ← sign_extend(temp31..0)
Programming Notes
This instruction is not an unsigned operation in the strict sense and performs 32-bit modulo arithmetic that
ignores overflow. It is appropriate for integer arithmetic that ignores overflow such as address or C language
arithmetic.

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AND : And
MIPS I
To perform a bitwise AND.
Operation Code
31

26

25

21

20

16

15

11

10

6

5

0

SPECIAL
000000

rs

rt

rd

0
00000

AND
100100

6

5

5

5

5

6

Format
AND rd, rs, rt
Description
GPR[rd] ← GPR[rs] AND GPR[rt]
Performs a bitwise AND between GPR[rs] and GPR[rt]. The result is stored in GPR[rd].
The truth table value for AND is as follows:
X
0
0
1
1

Y
0
1
0
1

X AND Y
0
0
0
1

Exceptions
None
Operation
GPR[rd] 63..0 ← GPR[rs] 63..0 AND GPR[rt] 63..0

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ANDI : Add Immediate
MIPS I
To perform a bitwise AND.
Operation Code
31

26

25

21

20

16

15

0

ANDI
001100

rs

rt

immediate

6

5

5

16

Format
ANDI rt, rs, immediate
Description
GPR[rt] ← GPR[rs] AND immediate
Performs a bitwise AND between the contents of GPR[rs] and the value of a zero- extended immediate
value. The result is stored in GPR[rt].
The truth table value for AND is as follows:
X
0
0
1
1

Y
0
1
0
1

X AND Y
0
0
0
1

Exceptions
None
Operation
GPR[rt]63..0 ← (048 || immediate) AND GPR[rs]63..0

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BEQ : Branch on Equal
MIPS I
To compare two GPRs and do a PC-relative conditional branch according to the result.
Operation Code
31

26

25

21

20

16

15

0

BEQ
000100

rs

rt

offset

6

5

5

16

Format
BEQ rs, rt, offset
Description
if (GPR[rs] = GPR[rt]) then branch
Compares the contents of GPR[rs] and GPR[rt]. If they are equal, branches to the target address after the
instruction in the branch delay slot is executed. If they are not equal, continues execution including the
instruction in the branch delay slot.
The target address is the address obtained from adding an 18-bit signed offset, (the offset field shifted left 2
bits) to the address of the instruction in the branch delay slot (the instruction following the BEQ
instruction).
Exceptions
None
Operation
Ι:
Ι+1:

tgt_offset ← sign_extend(offset || 02)
condition ← (GPR[rs] 63..0 = GPR[rt] 63..0)
if condition then
PC ← PC + tgt_offset
endif

Programming Notes
Since the offset is an 18-bit signed offset, the conditional branch range is ±128 KB. Use J or JR instructions
to branch to more distant addresses.

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BEQL : Branch on Equal Likely
MIPS II
To compare two GPRs and do a PC-relative conditional branch according to the result. Executes the delay slot
only if the branch is taken.
Operation Code
31

26

25

21

20

16

15

0

BEQL
010100

rs

rt

offset

6

5

5

16

Format
BEQL rs, rt, offset
Description
if (GPR[rs] = GPR[rt]) then branch_likely
Compares the contents of GPR[rs] and GPR[rt]. If they are equal, branches to the target address after the
instruction in the branch delay slot is executed. If they are not equal, cancels the instruction in the branch
delay slot.
The target address is the address obtained from adding an 18-bit signed offset (the offset field shifted left 2
bits), to the address of the instruction in the branch delay slot (the instruction following the BEQL
instruction).
Exceptions
None
Operation
Ι:
Ι+1:

tgt_offset ← sign_extend(offset || 02)
condition ← (GPR[rs] 63..0 = GPR[rt] 63..0)
if condition then
PC ← PC + tgt_offset
else
NullifyCurrentInstruction ()
endif

Programming Notes
Since the offset is an 18-bit signed offset, the conditional branch range is ±128 KB. Use J or JR instructions
to branch to more distant addresses.

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BGEZ : Branch on Greater Than or Equal to Zero
MIPS I
To do a PC-relative branch according to the values of a GPR.
Operation Code
31

26

25

21

20

16

15

0

REGIMM
000001

rs

BGEZ
00001

offset

6

5

5

16

Format
BGEZ rs, offset
Description
if (GPR[rs] >= 0) then branch
If the value of GPR[rs] is greater than or equal to zero (sign bit is 0), branches to the target address after the
instruction in the delay slot is executed. If the value of GPR[rs] is less than zero, continues execution,
including the instruction in the branch delay slot.
The target address is the address obtained from adding an 18-bit signed offset (the offset field shifted left 2
bits) to the address of the instruction in the branch delay slot (the instruction following the BGEZ
instruction).
Exceptions
None
Operation
Ι:
Ι+1:

tgt_offset ← sign_extend(offset || 02)
condition ← GPR[rs] 63..0 >= 0
if condition then
PC ← PC + tgt_offset
endif

Programming Notes
Since the offset is an 18-bit signed offset, the conditional branch range is ±128 KB. Use J or JR instructions
to branch to more distant addresses.

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BGEZAL : Branch on Greater Than or Equal to Zero and Link
MIPS I
To do a PC-relative conditional procedure call according to the values of a GPR.
Operation Code
31

26

25

21

20

16

15

0

REGIMM
000001

rs

BGEZAL
10001

offset

6

5

5

16

Format
BGEZAL rs, offset
Description
if (GPR[rs] >= 0) then procedure_call
Stores the address of the instruction following the branch delay slot as the return address link in GPR[31]. If
the value of GPR[rs] is greater than or equal to zero (sign bit is 0), branches to the target address after the
instruction in the delay slot is executed. If the value of GPR[rs] is less than zero, continues execution
including the instruction in the branch delay slot.
The target address is the address obtained from adding an 18-bit signed offset (the offset field shifted left 2
bits) to the address of the instruction in the branch delay slot (the instruction following the BGEZAL
instruction).
Restrictions
GPR[31] must not be used for the source register rs and the result of such an execution is undefined. This
restriction permits an exception handler to resume execution by re-executing the branch even when an
exception occurs in the branch delay slot.
Exceptions
None
Operation
Ι:

Ι+1:

tgt_offset ← sign_extend(offset || 02)
condition ← GPR[rs]63..0 >= 0
GPR[31]63..0 ← PC + 8
if condition then
PC ← PC + tgt_offset
endif

Programming Notes
Since the offset is an 18-bit signed offset, the conditional branch range is ±128 KB. Use
JAL or JALR instructions to call a subroutine to more distant addresses.

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BGEZALL : Branch on Greater Than or Equal to Zero and Link Likely
MIPS II
To do a PC-relative conditional procedure call according to the values of a GPR. Executes the instruction in the
branch delay slot only if the branch is taken.
Operation Code
31

26

25

21

20

16

15

0

REGIMM
000001

rs

BGEZALL
10011

offset

6

5

5

16

Format
BGEZALL rs, offset
Description
if (GPR[rs] >= 0) then procedure_call_likely
Stores the address of the instruction following the branch delay slot as the return address link in GPR[31]. If
the value of GPR[rs] is greater than or equal to zero (sign bit is 0), branches to the target address after the
instruction in the branch delay slot is executed. If the value of GPR[rs] is not greater than or equal to zero,
cancels the instruction in the branch delay slot and continues execution.
The target address is the address obtained from adding an 18-bit signed offset (the offset field shifted left 2
bits) to the address of the instruction in the branch delay slot (the instruction following the BGEZALL
instruction).
Restrictions
GPR[31] must not be used for the source register rs and the result of such execution is undefined. This
restriction permits an exception handler to resume execution by re-executing the branch even when an
exception occurs in the branch delay slot.
Exceptions
None
Operation
Ι:

Ι+1:

tgt_offset ← sign_extend (offset || 02)
condition ← GPR[rs]63..0 >= 0
GPR[31]63..0 ← PC + 8
if condition then
PC ← PC + tgt_offset
else
NullifyCurrentInstruction ()
endif

Programming Notes
Since the offset is an 18-bit signed offset, the conditional branch range is ±128 KB. Use JAL or JALR
instructions to call a subroutine to more distant addresses.

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BGEZL : Branch on Greater Than or Equal to Zero Likely
MIPS II
To do a PC-relative branch according to the values of a GPR. Executes the instruction in the branch delay slot
only if the branch is taken.
Operation Code
31

26

25

21

20

16

15

0

REGIMM
000001

rs

BGEZL
00011

offset

6

5

5

16

Format
BGEZL rs, offset
Description
if (GPR[rs] >= 0) then branch_likely
If the value of GPR[rs] is greater than or equal to zero (sign bit is 0), branches to the target address after the
instruction in the delay slot is executed. If the value of GPR[rs] is not greater than or equal to zero, cancels
the instruction in the branch delay slot and continues execution.
The target address is the address obtained from adding an 18-bit signed offset (the offset field shifted left 2
bits) to the address of the instruction in the branch delay slot (the instruction following the BGEZL
instruction).
Exceptions
None
Operation
Ι:
Ι+1:

tgt_offset ← sign_extend (offset || 02)
condition ← GPR[rs]63..0 >= 0
if condition then
PC ← PC + tgt_offset
else
NullifyCurrentInstruction ()
endif

Programming Notes
Since the offset is an 18-bit signed offset, the conditional branch range is ±128 KB. Use J or JR instructions
to branch to more distant addresses.

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BGTZ : Branch on Greater Than Zero
MIPS I
To do a PC-relative branch according to the values of a GPR.
Operation Code
31

26

25

21

20

16

15

0

BGTZ
000111

rs

0
00000

offset

6

5

5

16

Format
BGTZ rs, offset
Description
if (GPR[rs] > 0) then branch
If the value of GPR[rs] is greater than zero (sign bit is zero but value is not zero), branches to the target
address after the instruction in the delay slot is executed. If the value of GPR[rs] is less than or equal to zero,
continues execution including the instruction in the branch delay slot.
The target address is the address obtained from adding an 18-bit signed offset (the offset field shifted left 2
bits) to the address of the instruction in the branch delay slot (the instruction following the BGTZ
instruction).
Exceptions
None
Operation
Ι:
Ι+1:

tgt_offset ← sign_extend(offset || 02)
condition ← GPR[rs] 63..0 > 0
if condition then
PC ← PC + tgt_offset
endif

Programming Notes
Since the offset is an 18-bit signed offset, the conditional branch range is ±128 KB. Use J or JR instructions
to branch to more distant addresses.

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EE Core Instruction Set Manual Version 6.0

BGTZL : Branch on Greater Than Zero Likely
MIPS II
To do a PC-relative branch according to the values of a GPR. Executes the instruction in the branch delay slot
only if the branch is taken.
Operation Code
31

26

25

21

20

16

15

0

BGTZL
010111

rs

0
00000

offset

6

5

5

16

Format
BGTZL rs, offset
Description
if (GPR[rs] > 0) then branch_likely
If the value of GPR[rs] is greater than zero (sign bit is zero but value not zero), branches to the target
address after the instruction in the delay slot is executed. If the value of GPR[rs] is less than or equal to zero,
cancels the instruction in the branch delay slot and continues execution.
The target address is the address obtained from adding an 18-bit signed offset (the offset field shifted left 2
bits) to the address of the instruction in the branch delay slot (the instruction following the BGTZL
instruction).
Exceptions
None
Operation
Ι:
Ι+1:

tgt_offset ← sign_extend (offset || 02)
condition ← GPR[rs] 63..0 > 0
if condition then
PC ← PC + tgt_offset
else
NullifyCurrentInstruction ()
endif

Programming Notes
Since the offset is an 18-bit signed offset, the conditional branch range is ±128 KB. Use J or JR instructions
to branch to more distant addresses.

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EE Core Instruction Set Manual Version 6.0

BLEZ : Branch on Less Than or Equal to Zero
MIPS I
To do a PC-relative branch according to the values of a GPR.
Operation Code
31

26

25

21

20

16

15

0

BLEZ
000110

rs

0
00000

offset

6

5

5

16

Format
BLEZ rs, offset
Description
if (GPR[rs] <= 0) then branch
If the value of GPR[rs] is less than or equal to zero (sign bit is one or value is zero), branches to the target
address after the instruction in the delay slot is executed. If the value of GPR[rs] is greater than zero,
continues execution including the instruction in the branch delay slot.
The target address is the address obtained from adding an 18-bit signed offset (the offset field shifted left 2
bits) to the address of the instruction in the branch delay slot (the instruction following the BLEZ
instruction).
Exceptions
None
Operation
I:
I+1:

tgt_offset ← sign_extend (offset ||02)
condition ← GPR[rs]63..0 <= 0
if condition then
PC ← PC + tgt_offset
endif

Programming Notes
Since the offset is an 18-bit signed offset, the conditional branch range is ±128 KB. Use J or JR instructions
to branch to more distant addresses.

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EE Core Instruction Set Manual Version 6.0

BLEZL : Branch on Less Than or Equal to Zero Likely
MIPS I
To do a PC-relative branch according to the values of a GPR. Executes the instruction in the branch delay slot
only if the branch is taken.
Operation Code
31

26

25

21

20

16

15

0

BLEZL
010110

rs

0
00000

offset

6

5

5

16

Format
BLEZL rs, offset
Description
If the value of GPR[rs] is less than or equal to zero (sign bit is one or value is zero), branches to the target
address after the instruction in the delay slot is executed. If the value of GPR[rs] is greater than zero, cancels
the instruction in the branch delay slot and continues execution.
The target address is the address obtained from adding an 18-bit signed offset (the offset field shifted left 2
bits) to the address of the instruction in the branch delay slot (the instruction following the BLEZL
instruction).
Exceptions
None
Operation
I:
I+1:

tgt_offset ← sign_extend(offset ||02)
condition ← GPR[rs]63..0 <= 0
if condition then
PC ← PC + tgt_offset
else
NullifyCurrentInstruction ()
endif

Programming Notes
Since the offset is an 18-bit signed offset, the conditional branch range is ±128 KB. Use J or JR instructions
to branch to more distant addresses.

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EE Core Instruction Set Manual Version 6.0

BLTZ : Branch on Less Than Zero
MIPS I
To do a PC-relative branch according to the values of a GPR.
Operation Code
31

26

25

21

20

16

15

0

REGIMM
000001

rs

BLTZ
00000

offset

6

5

5

16

Format
BLTZ rs, offset
Description
if (GPR[rs] < 0) then branch
If the value of GPR[rs] is less than zero (sign bit is one and value is not zero), branches to the target address
after the instruction in the delay slot is executed. If the value of GPR[rs] is greater than or equal to zero,
continues execution including the instruction in the branch delay slot.
The target address is the address obtained from adding an 18-bit signed offset (the offset field shifted left 2
bits) to the address of the instruction in the branch delay slot (the instruction following the BLTZ
instruction).
Exceptions
None
Operation
I:
I+1:

tgt_offset ← sign_extend (offset ||02)
condition ← GPR[rs]63..0 < 0
if condition then
PC ← PC + tgt_offset
endif

Programming Notes
Since the offset is an 18-bit signed offset, the conditional branch range is ±128 KB. Use J or JR instructions
to branch to more distant addresses.

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SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

BLTZAL : Branch on Less Than Zero and Link
MIPS I
To do a PC-relative conditional procedure call according to the values of a GPR.
Operation Code
31

26

25

21

20

16

15

0

REGIMM
000001

rs

BLTZAL
10000

offset

6

5

5

16

Format
BLTZAL rs, offset
Description
if (GPR[rs] < 0) then procedure_call
Stores the address of the instruction following the branch delay slot as the return address link in GPR[31]. If
the value of GPR[rs] is less than zero (sign bit is 1), branches to the target address after the instruction in the
delay slot is executed. If the value of GPR[rs] is greater than or equal to zero, continues execution including
the instruction in the branch delay slot.
The target address is the address obtained from adding an 18-bit signed offset (the offset field shifted left 2
bits) to the address of the instruction in the branch delay slot (the instruction following the BLTZAL
instruction).
Restrictions
GPR[31] must not be used for the source register rs and the result of such execution is undefined. This
restriction permits an exception handler to resume execution by re-executing the branch even when an
exception occurs in the branch delay slot.
Exceptions
None
Operation
I:

I+1:

tgt_offset ← sign_extend (offset || 02)
condition ← GPR[rs] 63..0 < 0
GPR[31] 63..0 ← PC + 8
if condition then
PC ← PC + tgt_offset
endif

Programming Notes
Since the offset is an 18-bit signed offset, the conditional branch range is ±128 KB. Use JAL or JALR
instructions to call a subroutine to more distant addresses.

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EE Core Instruction Set Manual Version 6.0

BLTZALL : Branch on Less Than Zero and Link Likely
MIPS II
To do a PC-relative conditional procedure call according to the values of a GPR. Executes the instruction in the
branch delay slot only if the branch is taken.
Operation Code
31

26

25

21

20

16

15

0

REGIMM
000001

rs

BLTZALL
10010

offset

6

5

5

16

Format
BLTZALL rs, offset
Description
if (GPR[rs] < 0) then procedure_call_likely
Stores the address of the instruction following the branch delay slot as the return address link in GPR[31]. If
the value of GPR[rs] is less than zero (sign bit is 1), branches to the target address after the instruction in the
delay slot is executed. If the value of GPR[rs] is greater than or equal to zero, continues execution including
the instruction in the branch delay slot.
The target address is the address obtained from adding an 18-bit signed offset (the offset field shifted left 2
bits) to the address of the instruction in the branch delay slot (the instruction following the BLTZALL
instruction).
Restrictions
GPR[31] must not be used for the source register rs and the result of such execution is undefined. This
restriction permits an exception handler to resume execution by re-executing the branch even when an
exception occurs in the branch delay slot.
Exceptions
None
Operation
I:

I+1:

tgt_offset ← sign_extend (offset ||02)
condition ← GPR[rs] 63..0 < 0
GPR[31] 63..0 ← PC+8
if condition then
PC ← PC + tgt_offset
else
NullifyCurrentInstruction ()
endif

Programming Notes
Since the offset is an 18-bit signed offset, the conditional branch range is ±128 KB. Use JAL or JALR
instructions to call a subroutine to more distant addresses.

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EE Core Instruction Set Manual Version 6.0

BLTZL : Branch on Less Than Zero Likely
MIPS II
To do a PC-relative conditional branch according to the values of a GPR. Executes the instruction in the branch
delay slot only if the branch is taken.
Operation Code
31

26

25

21

20

16

15

0

REGIMM
000001

rs

BLTZL
00010

offset

6

5

5

16

Format
BLTZL rs, offset
Description
if (GPR[rs] < 0) then branch_likely
If the value of GPR[rs] is less than zero (sign bit is 1), branches to the target address after the instruction in
the delay slot is executed. If the value of GPR[rs] is greater than or equal to zero, cancels the instruction in
the branch delay slot and continues execution.
The target address is the address obtained from adding an 18-bit signed offset (the offset field shifted left 2
bits) to the address of the instruction in the branch delay slot (the instruction following the BLTZL
instruction).
Exceptions
None
Operation
I:
I+1:

tgt_offset ← sign_extend (offset ||02)
condition ← GPR[rs] 63..0 < 0
if condition then
PC ← PC + tgt_offset
else
NullifyCurrentInstruction ()
endif

Programming Notes
Since the offset is an 18-bit signed offset, the conditional branch range is ±128 KB. Use J or JR instructions
to branch to more distant addresses.

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EE Core Instruction Set Manual Version 6.0

BNE : Branch on Not Equal
MIPS I
To compare the value of GPRs and then do a PC-relative conditional branch according to the result.
Operation Code
31

26

25

21

20

16

15

0

BNE
000101

rs

rt

offset

6

5

5

16

Format
BNE rs, rt, offset
Description
if (GPR[rs] ≠ GPR[rt]) then branch
If the values of GPR[rs] and GPR[rt] are not equal, branches to the target address after the instruction in the
branch delay slot is executed. If they are equal, continues execution including the instruction in the branch
delay slot.
The target address is the address obtained from adding an 18-bit signed offset (the offset field shifted left 2
bits) to the address of the instruction in the branch delay slot (the instruction following the BNE
instruction).
Exceptions
None
Operation
I:
I+1:

tgt_offset ← sign_extend(offset ||02)
condition ← (GPR[rs] 63..0 ≠ GPR[rt] 63..0)
if condition then
PC ← PC + tgt_offset
endif

Programming Notes
Since the offset is an 18-bit signed offset, the conditional branch range is ±128 KB. Use J or JR instructions
to branch to more distant addresses.

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SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

BNEL : Branch on Not Equal Likely
MIPS II
To compare the value of GPRs and then do a PC-relative conditional branch according to the result. Executes
the instruction in the delay slot only if the branch is taken.
Operation Code
31

26

25

21

20

16

15

0

BNEL
010101

rs

rt

offset

6

5

5

16

Format
BNEL rs, rt, offset
Description
if (GPR[rs] ≠ GPR[rt]) then branch_likely
If the values of GPR[rs] and GPR[rt] are not equal, branches to the target address after the instruction in the
branch delay slot is executed. If they are equal, cancels the instruction in the branch delay slot and continues
execution.
The target address is the address obtained from adding an 18-bit signed offset (the offset field shifted left 2
bits) to the address of the instruction in the branch delay slot (the instruction following the BNEL
instruction).
Exceptions
None
Operation
Ι:
Ι+1:

tgt_offset ← sign_extend (offset || 02)
condition ← (GPR[rs] 63..0 ≠ GPR[rt] 63..0)
if condition then
PC ← PC + tgt_offset
else
NullifyCurrentInstruction ()
endif

Programming Notes
Since the offset is an 18-bit signed offset, the conditional branch range is ±128 KB. Use J or JR instructions
to branch to more distant addresses.

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SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

BREAK : Breakpoint
MIPS I
To cause a Breakpoint exception.
Operation Code
31

26

25

6

5

0

SPECIAL
000000

code

BREAK
001101

6

20

6

Format
BREAK
Description
A breakpoint exception occurs, immediately and unconditionally transferring control to the exception
handler.
The code field is available to be used for software parameters.
However, no special way for the exception handler to acquire the value of the code field is provided. It must
be retrieved by determining the address of an instruction word from the EPC register, etc.
Exceptions
Breakpoint
Operation
SignalException (Breakpoint)

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EE Core Instruction Set Manual Version 6.0

DADD : Doubleword Add
MIPS III
To add 64-bit integers. Traps if overflow occurs.
Operation Code
31

26

25

21

20

16

15

11

10

6

5

0

SPECIAL
000000

rs

rt

rd

0
00000

DADD
101100

6

5

5

5

5

6

Format
DADD rd, rs, rt
Description
GPR[rd] ← GPR[rs] + GPR[rt]
Adds the 64-bit value in GPR[rt] to the 64-bit value in GPR[rs]. The result is stored in GPR[rd]. If the
addition results in 64-bit 2's complement arithmetic overflow, then the contents of GPR[rd] are not changed
and an Integer Overflow exception occurs.
Exceptions
Integer Overflow
Operation
temp ← GPR[rs] 63..0 + GPR[rt] 63..0
if (64_bit_arithmetic_overflow) then
SignalException (IntegerOverflow)
else
GPR[rd] 63..0 ← temp
endif
Programming Notes
DADDU performs the same arithmetic operation but does not trap on overflow.

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EE Core Instruction Set Manual Version 6.0

DADDI : Doubleword Add Immediate
MIPS III
To add a 16-bit immediate value to a 64-bit integers. Traps if overflow occurs.
Operation Code
31

26

25

21

20

16

15

0

DADDI
011000

rs

rt

immediate

6

5

5

16

Format
DADDI rt, rs, immediate
Description
GPR[rt] ← GPR[rs] + immediate
Adds the value of the immediate field as a 16-bit signed integer to the 64-bit integer value in GPR[rs]. The
result is stored in GPR[rt]. If the addition results in 64-bit 2's complement overflow, then the contents of
GPR[rt] are not changed and an Integer Overflow exception occurs.
Exceptions
Integer Overflow
Operation
temp ← GPR[rs] 63..0 + sign_extend(immediate)
if (64_bit_arithmetic_overflow) then
SignalException (IntegerOverflow)
else
GPR[rt] 63..0 ← temp
endif
Programming Notes
DADDIU performs the same arithmetic operation but does not trap on overflow.

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SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

DADDIU : Doubleword Add Immediate Unsigned
MIPS III
To add a 16-bit immediate value to a 64-bit integer.
Operation Code
31

26

25

21

20

16

15

0

DADDIU
011001

rs

rt

immediate

6

5

5

16

Format
DADDIU rt, rs, immediate
Description
GPR[rt] ← GPR[rs] + immediate
Adds the value of the immediate field as a 16-bit signed integer to the 64-bit integer value in GPR[rs]. The
result is stored in GPR[rt]. Regardless of the result, an Integer Overflow exception does not occur.
Exceptions
None
Operation
GPR[rt] 63..0 ← GPR[rs] 63..0 + sign_extend(immediate)
Programming Notes
This instruction is not an unsigned operation in the strict sense and performs 64-bit modulo arithmetic that
ignores overflow. It is appropriate for integer arithmetic that ignores overflow such as address or C language
arithmetic.

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EE Core Instruction Set Manual Version 6.0

DADDU : Doubleword Add Unsigned
MIPS III
To add 64-bit integers.
Operation Code
31

26

25

21

20

16

15

11

10

6

5

0

SPECIAL
000000

rs

rt

rd

0
00000

DADDU
101101

6

5

5

5

5

6

Format
DADDU rd, rs, rt
Description
rd ← GPR[rs] + rt
Adds the 64-bit value in GPR[rt] to the 64-bit value in GPR[rs]. The result is stored in GPR[rd]. Regardless
of the result, an Integer Overflow exception does not occur.
Exceptions
None
Operation
GPR[rd] 63..0 ← GPR[rs] 63..0 + GPR[rt] 63..0
Programming Notes
This instruction is not an unsigned operation in the strict sense and performs 64-bit modulo arithmetic that
ignores overflow. It is appropriate for integer arithmetic that ignores overflow such as address or C language
arithmetic.

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EE Core Instruction Set Manual Version 6.0

DIV : Divide Word
MIPS I
To divide 32-bit signed integers.
Operation Code
31

26

25

21

20

16

15

6

5

0

SPECIAL
000000

rs

rt

0
00 0000 0000

DIV
011010

6

5

5

10

6

Format
DIV rs, rt
Description
(LO, HI) ← GPR[rs] / GPR[rt]
The 32-bit value in GPR[rs] is divided by the 32-bit value in GPR[rt]. The 32-bit quotient is stored in the LO
register and the 32-bit remainder is stored in the HI register. Both GPR[rs] and GPR[rt] are treated as signed
values. The sign of the quotient and remainder are determined as shown in the table below.
Dividend GPR[rs]
Divisor GPR[rt]
Quotient LO
Remainder HI
Positive
Positive
Positive
Positive
Positive
Negative
Negative
Positive
Negative
Positive
Negative
Negative
Negative
Negative
Positive
Negative
No arithmetic exception such as divide-by-zero or overflow occurs under any circumstances.
Restrictions
If GPR[rt] or GPR[rs] are not sign-extended 32-bit values (bits 63..31 equal), then the result of the operation
is undefined (Bits 63 to 32 are not used for the operation itself, but this restriction is applied). Also, if the
value of GPR[rt] is zero, the value of the arithmetic result is undefined.
Exceptions
None
Operation
if (NotWordValue (GPR[rs]) or NotWordValue (GPR[rt])) then UndefinedResult() endif
quotient ← GPR[rs]31..0 DIV GPR[rt]31..0
LO63..0 ← sign_extend(quotient31..0)
remainder ← GPR[rs]31..0 MOD GPR[rt]31..0
HI63..0 ← sign_extend(remainder31..0)
Programming Notes
In the EE Core, the integer divide operation proceeds asynchronously. An attempt to read the contents of
the LO or HI register before the divide operation finishes will result in interlock. Other CPU instructions
can execute without delay. Therefore, scheduling the divide operation appropriately will improve
performance.
Normally, when 0x80000000(−2147483648), the signed minimum value, is divided by 0xFFFFFFFF(−1), the
operation will result in overflow. However, in this instruction an overflow exception does not occur and the
result will be as follows:
Quotient: 0x80000000 (−2147483648), and remainder: 0x00000000 (0)
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If overflow or divide-by-zero must be detected, then add an instruction that detects these conditions
following the divide instruction. Since the divide instruction is asynchronous, the divide operation and check
can be executed in parallel. If overflow or divide-by-zero is detected, then to signal the problem to the
system software is possible by generating exceptions using an appropriate code value with a BREAK
instruction.

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EE Core Instruction Set Manual Version 6.0

DIVU : Divide Unsigned Word
MIPS I
To divide 32-bit unsigned integers.
Operation Code
31

26

25

21

20

16

15

6

5

0

SPECIAL
000000

rs

rt

0
00 0000 0000

DIVU
011011

6

5

5

10

6

Format
DIVU rs, rt
Description
(LO, HI) ← GPR[rs] / GPR[rt]
The 32-bit value in GPR[rs] is divided by the 32-bit value in GPR[rt]. The 32-bit quotient is stored in the LO
register and the 32-bit remainder is stored in the HI register. Both GPR[rs] and GPR[rt] are treated as
unsigned values.
No arithmetic exception such as divide-by-zero or overflow occurs under any circumstances.
Restrictions
If GPR[rt] or GPR[rs] are not sign-extended 32-bit values (bits 63..31 equal), then the result of the operation
is undefined (Bits 63 to 32 are not used for the operation itself, but this restriction is applied). Also, if the
value of GPR[rt] is zero, the value of arithmetic operation is undefined.
Exceptions
None
Operation
if (NotWordValue(GPR[rs]) or NotWordValue (GPR[rt])) then UndefinedResult() endif
quotient ← (0 || GPR[rs]31..0) DIV (0 || GPR[rt]31..0)
LO63..0 ← sign_extend(quotient31..0)
remainder ← (0 || GPR[rs]31..0) MOD (0 || GPR[rt]31..0)
HI63..0 ← sign_extend(remainder31..0)
Programming Notes
See "Programming Notes" for the DIV instruction.

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EE Core Instruction Set Manual Version 6.0

DSLL : Doubleword Shift Left Logical
MIPS III
To left shift a doubleword. The shift amount is a fixed value (0-31 bits) specified by sa.
Operation Code
31

26

25

21

20

16

15

11

10

6

5

0

SPECIAL
000000

0
00000

rt

rd

sa

DSLL
111000

6

5

5

5

5

6

Format
DSLL rd, rt, sa
Description
GPR[rd] ← GPR[rt]<< sa
Shifts the 64-bit data in GPR[rt] left by the bit count specified by sa, inserting zeros into the emptied bits.
The result is stored in GPR[rd].
Exceptions
None
Operation
s ← 0 || sa
GPR[rd] 63..0 ←GPR[rt](63-s)..0 || 0s

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EE Core Instruction Set Manual Version 6.0

DSLL32 : Doubleword Shift Left Logical Plus 32
MIPS III
To left shift a doubleword. The shift amount is a fixed value (32-63 bits) specified by sa.
Operation Code
31

26

25

21

20

16

15

11

10

6

5

0

SPECIAL
000000

0
00000

rt

rd

sa

DSLL32
111100

6

5

5

5

5

6

Format
DSLL32 rd, rt, sa
Description
GPR[rd] ← GPR[rt]<< (sa + 32)
Shifts the 64-bit data in GPR[rt] left by the bit count specified by sa + 32, inserting zeros into the emptied
bits. The result is stored in GPR[rd].
Exceptions
None
Operation
s ← 1 || sa
/* s = 32 + sa */
GPR[rd] 63..0 ← GPR[rt](63-s)..0 || 0s

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EE Core Instruction Set Manual Version 6.0

DSLLV : Doubleword Shift Left Logical Variable
MIPS III
To left shift a doubleword. The shift amount is a variable (specified by a GPR).
Operation Code
31

26

25

21

20

16

15

11

10

6

5

0

SPECIAL
000000

rs

rt

rd

0
00000

DSLLV
010100

6

5

5

5

5

6

Format
DSLLV rd, rt, rs
Description
GPR[rd] ← GPR[rt]<< GPR[rs]
Shifts the 64-bit data in GPR[rt] left by the bit count (0-63) specified by the low-order 6 bits in GPR[rs],
inserting zeros into the emptied bits. The result is stored in GPR[rd].
Exceptions
None
Operation
s ← 0 || GPR[rs]5..0
GPR[rd] 63..0 ← GPR[rt](63-s)..0 || 0s

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EE Core Instruction Set Manual Version 6.0

DSRA : Doubleword Shift Right Arithmetic
MIPS III
To arithmetic right shift a doubleword. The shift amount is a fixed value (0-31 bits) specified by sa.
Operation Code
31

26

25

21

20

16

15

11

10

6

5

0

SPECIAL
000000

0
00000

rt

rd

sa

DSRA
111011

6

5

5

5

5

6

Format
DSRA rd, rt, sa
Description
GPR[rd] ← GPR[rt]>> sa (arithmetic)
Shifts the 64-bit data in GPR[rt] right by the bit count (0-31) specified by sa, duplicating the sign bit (bit 63)
into the emptied bits. The result is stored in GPR[rd].
Exceptions
None
Operation
s ← 0 || sa
GPR[rd] 63..0 ← (GPR[rt]63)s || GPR[rt]63..s

© SCEI
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SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

DSRA32 : Doubleword Shift Right Arithmetic Plus 32
MIPS III
To arithmetic right shift a doubleword. The shift amount is a fixed value (32-63 bits) specified by sa.
Operation Code
31

26

25

21

20

16

15

11

10

6

5

0

SPECIAL
000000

0
00000

rt

rd

sa

DSRA32
111111

6

5

5

5

5

6

Format
DSRA32 rd, rt, sa
Description
GPR[rd] ← GPR[rt]>> (sa + 32) (arithmetic)
Shifts the 64-bit data in GPR[rt] right by the bit count (0-31) specified by sa + 32, duplicating the sign bit (bit
63) into the emptied bits. The result is stored in GPR[rd].
Exceptions
None
Operation
s ← 1 || sa
/* s = 32 + sa */
GPR[rd] 63..0 ← (GPR[rt]63) s || GPR[rt]63..s

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SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

DSRAV : Doubleword Shift Right Arithmetic Variable
MIPS III
To arithmetic right shift a doubleword. The shift amount is a variable value (0-63 bits) specified by a GPR.
Operation Code
31

26

25

21

20

16

15

11

10

6

5

0

SPECIAL
000000

rs

rt

rd

0
00000

DSRAV
010111

6

5

5

5

5

6

Format
DSRAV rd, rt, rs
Description
GPR[rd] ← GPR[rt]>> GPR[rs] (arithmetic)
Shifts the 64-bit data in GPR[rt] right by the bit count specified by the low-order 6-bits in GPR[rs],
duplicating the sign bit (bit 63) into the emptied bits. The result is stored in GPR[rd].
Exceptions
None
Operation
s ← GPR[rs]5..0
GPR[rd] 63..0 ← (GPR[rt]63) s || GPR[rt]63..s

© SCEI
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SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

DSRL : Doubleword Shift Right Logical
MIPS III
To logical right shift a doubleword. The shift amount is a fixed value (0-31 bit) specified by sa.
Operation Code
31

26

25

21

20

16

15

11

10

6

5

0

SPECIAL
000000

0
00000

rt

rd

sa

DSRL
111010

6

5

5

5

5

6

Format
DSRL rd, rt, sa
Description
GPR[rd] ← GPR[rt]>> sa (logical)
Shifts the 64-bit data in GPR[rt] right by the bit count (0-31) specified by sa, inserting zeros into the emptied
bits. The result is stored in GPR[rd].
Exceptions
None
Operation
s ← 0 || sa
GPR[rd] 63..0 ← 0 s || GPR[rt]63..s

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SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

DSRL32 : Doubleword Shift Right Logical Plus 32
MIPS III
To logical right shift a doubleword. The shift amount is a fixed value (32-63 bits) specified by sa.
Operation Code
31

26

25

21

20

16

15

11

10

6

5

0

SPECIAL
000000

0
00000

rt

rd

sa

DSRL32
111110

6

5

5

5

5

6

Format
DSRL32 rd, rt, sa
Description
GPR[rd] ← GPR[rt]>> (sa + 32) (logical)
Shifts the 64-bit data in GPR[rt] right by the bit count (32-63) specified by sa, inserting zeros into the
emptied bits. The result is stored in GPR[rd].
Exceptions
None
Operation
s ← 1 || sa

/* s = 32 + sa * /

GPR[rd] 63..0 ← 0 || GPR[rt]63..s
s

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SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

DSRLV : Doubleword Shift Right Logical Variable
MIPS III
To logical right shift a doubleword. The shift amount is a variable value (0-63 bits) specified by a GPR.
Operation Code
31

26

25

21

20

16

15

11

10

6

5

0

SPECIAL
000000

rs

rt

rd

0
00000

DSRLV
010110

6

5

5

5

5

6

Format
DSRLV rd, rt, rs
Description
GPR[rd] ← GPR[rt]>> GPR[rs] (logical)
Shifts the 64-bit data in GPR[rt] right by the bit count (0-63) specified by the low-order 6 bits in GPR[rs],
inserting zeros into the emptied bits. The result is stored in GPR[rd].
Exceptions
None
Operation
s ← GPR[rs]5..0
GPR[rd] 63..0 ← 0s || GPR[rt]63..s

© SCEI
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SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

DSUB : Doubleword Subtract
MIPS III
To subtract 64-bit integers. Traps if overflow occurs.
Operation Code
31

26

25

21

20

16

15

11

10

6

5

0

SPECIAL
000000

rs

rt

rd

0
00000

DSUB
101110

6

5

5

5

5

6

Format
DSUB rd, rs, rt
Description
GPR[rd] ← GPR[rs] — GPR[rt]
Subtracts the 64-bit value in GPR[rt] from the 64-bit value in GPR[rs]. The result is stored in GPR[rd]. If the
operation results in 64-bit 2's complement arithmetic overflow, then the contents of GPR[rd] are not
changed and an Integer Overflow exception occurs.
Exceptions
Integer Overflow
Operation
temp ← GPR[rs] 63..0 — GPR[rt] 63..0
if (64_bit_arithmetic_overflow) then
SignalException (IntegerOverflow)
else
GPR[rd] 63..0 ← temp
endif
Programming Notes
DSUBU performs the same arithmetic operation but does not trap on overflow.

© SCEI
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SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

DSUBU : Doubleword Subtract Unsigned
MIPS III
To subtract 64-bit integers.
Operation Code
31

26

25

21

20

16

15

11

10

6

5

0

SPECIAL
000000

rs

rt

rd

0
00000

DSUBU
101111

6

5

5

5

5

6

Format
DSUBU rd, rs, rt
Description
GPR[rd] ← GPR[rs] — GPR[rt]
Subtracts the 64-bit value in GPR[rt] from the 64-bit value in GPR[rs]. The result is stored in GPR[rd].
Regardless of the arithmetic result, an Integer Overflow exception does not occur.
Exceptions
None
Operation
GPR[rd] 63..0 ← GPR[rs] 63..0 — GPR[rt] 63..0
Programming Notes
This instruction is not an unsigned operation in the strict sense and performs 64-bit modulo arithmetic that
ignores overflow. It is appropriate for integer arithmetic that ignores overflow such as address or C language
arithmetic.

© SCEI
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SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

J : Jump
MIPS I
To do an unconditional branch by an absolute address within a 256 MB region.
Operation Code
31

26

25

0

J
000010

offset

6

26

Format
J target
Description
Executes the instruction in the branch delay slot and then branches to the target address unconditionally.
The target address is the address adding the high-order bits of the instruction address in the branch delay slot
(the address of the J instruction itself + 4) to the 28-bit value obtained by shifting the offset left 2 bits. That
is, though it is not PC-relative, the branch target is restricted to a memory region aligned on a 256 MB
boundary, the same region as the current PC region.
Exceptions
None
Operation
I:
I+1:

(Explicit Operation: None)
PC ← PC31..28 || offset || 02

Programming Notes
The J instruction can branch to any addresses within a 256 MB region, while conditional branch instructions
such as BEQ are limited to ±128 KB.
If the J instruction is in the last word of a 256 MB region, the branch target is restricted to the following 256
MB region, because the basis of the branch is not the J instruction itself but the following instruction. Note
that this is an exceptional case.

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SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

JAL : Jump and Link
MIPS I
To call a subroutine by an absolute address within a 256 MB region.
Operation Code
31

26

25

0

JAL
000011

instr_index

6

26

Format
JAL target
Description
Stores the address of the instruction following the branch delay slot (the address of the J instruction itself +
8) in GPR[31] and branches to the target address after the instruction in the delay slot is executed.
The target address is the address adding the high-order bits of the instruction address in the branch delay slot
(the address of J instruction itself + 4) to the 28-bit value obtained by shifting the instr_index left 2 bits. That
is, though it is not PC-relative, the branch target is restricted to a memory region aligned on a 256 MB
boundary, the same region as the current PC region.
Exceptions
None
Operation
I:
I+1:

GPR[31] 63..0 ← zero_extend(PC + 8)
PC ← PC31..28 || instr_index || 02

Programming Notes
The JAL instruction can call subroutines in any addresses within a 256 MB region, while the range of
conditional branch instructions such as BGEZAL are limited to ±128 KB.
If the JAL instruction is in the last word of a 256 MB region, the branch target is restricted to the following
256 MB region, because the basis of the branch is not the JAL instruction itself but the following instruction.
Note that this is an exceptional case.

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SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

JALR : Jump and Link Register
MIPS I
To call a subroutine at the address specified by a GPR.
Operation Code
31

26

25

21

20

16

15

11

10

6

5

0

SPECIAL
000000

rs

0
00000

rd

0
00000

JALR
001001

6

5

5

5

5

6

Format
JALR rs
JALR rd, rs

(rd = 31 implied)

Description
GPR[rd] ← return_addr, PC ← GPR[rs]
Stores the address of the instruction following the branch delay slot (the address of the J instruction itself +
8) in GPR[rd] and branches to the target address after the instruction in the delay slot is executed. The target
address is the value of GPR[rs].
Restrictions
rs and rd have to specify different registers. If they specify the same register, the result of the execution is
undefined. This restriction permits an exception handler to resume execution by re-executing the branch
when an exception occurs in the branch delay slot.
The value of GPR[rs] must be naturally aligned. If either of the two least-significant bits is not zero, an
Address Error exception occurs when the instruction of the branch target is fetched (not when the JALR
instruction is executed).
Exceptions
None
Operation
I:
I+1:

temp ← GPR[rs] 31..0
GPR[rd] 63..0 ← zero_extend(PC + 8)
PC ← temp

Programming Notes
The JALR instruction is the only instruction that can specify the link register. All other link instructions use
GPR[31]. The default register for the link register (GPR[rd]) is GPR[31] in the JALR instruction.

© SCEI
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SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

JR : Jump Register
MIPS I
To branch to the address specified by a GPR.
Operation Code
31

26

25

21

20

6

5

0

SPECIAL
000000

rs

0
000 0000 0000 0000

JR
001000

6

5

15

6

Format
JR rs
Description
PC ← GPR[rs]
Branches to the target address after the instruction in the delay slot is executed. The target address is the
value of GPR[rs].
Restrictions
The value of GPR[rs] must be naturally aligned. If either of the two least-significant bits is not zero, an
Address Error exception occurs when the instruction of the branch target is fetched (not when the JR
instruction is executed).
Exceptions
None
Operation
I:
I+1:

temp ← GPR[rs] 31..0
PC ← temp

© SCEI
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SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

LB : Load Byte
MIPS I
To load a byte from memory as a signed value.
Operation Code
31

26

25

21

20

16

15

0

LB
100000

base

rt

offset

6

5

5

16

Format
LB rt, offset (base)
Description
GPR[rt] ← memory [GPR[base] + offset]
Adds the offset as a 16-bit signed number to the value of GPR[base] to form the effective address. Fetches
the byte at the address, sign-extends it and stores it in GPR[rt].
Exceptions
TLB Refill, TLB Invalid, Address Error
Operation (128-bit bus)
vAddr ← sign_extend(offset) + GPR[base] 31..0
(pAddr, uncached) ← AddressTranslation (vAddr, DATA, LOAD)
pAddr ← pAddr(PSIZE-1)..0
memquad ← LoadMemory (uncached, BYTE, pAddr, vAddr, DATA)
byte ← vAddr3..0
GPR[rt]63..0 ← sign_extend(memquad(7+8*byte)..8*byte)

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SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

LBU : Load Byte Unsigned
MIPS I
To load a byte from memory as an unsigned value.
Operation Code
31

26

25

21

20

16

15

0

LBU
100100

base

rt

offset

6

5

5

16

Format
LBU rt, offset(base)
Description
GPR[rt] ← memory [GPR[base] + offset]
Adds the offset as a 16-bit signed number to the value of GPR[base] to form the effective address. Fetches
the byte at the address, zero-extends it and stores it in GPR[rt].
Exceptions
TLB Refill, TLB Invalid, Address Error
Operation (128-bit bus)
vAddr ← sign_extend(offset) + GPR[base] 31..0
(pAddr, uncached) ← AddressTranslation(vAddr, DATA, LOAD)
pAddr ← pAddr(PSIZE-1)..0
memquad ← LoadMemory (uncached, BYTE, pAddr, vAddr, DATA)
byte ← vAddr3..0
GPR[rt]63..0 ← zero_extend (memquad(7+8*byte)..8*byte)

© SCEI
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SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

LD : Load Doubleword
MIPS III
To load a doubleword from memory.
Operation Code
31

26

25

21

20

16

15

0

LD
110111

base

rt

offset

6

5

5

16

Format
LD rt, offset (base)
Description
GPR[rt] ← memory [GPR[base] + offset]
Adds the offset as a 16-bit signed number to the value of GPR[base] to form the effective address. Fetches
the doubleword at the address and stores it in GPR[rt].
Restrictions
The effective address must be aligned on a doubleword boundary. If any of the three least-significant bits of
the effective addresses are non-zero, an Address Error exception occurs.
Exceptions
TLB Refill, TLB Invalid, Address Error
Operation (128-bit bus)
vAddr ← sign_extend (offset) + GPR [base] 31..0
3

if (vAddr2..0) ≠ 0 then SignalException (AddressError) endif
(pAddr, uncached) ← AddressTranslation (vAddr, DATA, LOAD)
pAddr ← pAddr(PSIZE-1)..0
byte ← vAddr3..0
memquad ← LoadMemory (uncached, DOUBLEWORD, pAddr, vAddr, DATA)
GPR[rt]63..0 ← memquad(63+8*byte)..8*byte

© SCEI
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SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

LDL : Load Doubleword Left
MIPS III
To load the upper part of an unaligned doubleword.
Operation Code
31

26

25

21

20

16

15

0

LDL
011010

base

rt

offset

6

5

5

16

Format
LDL rt, offset (base)
Description
GPR[rt] ← GPR[rt] MERGE memory [GPR[base] + offset]
Adds the offset as a 16-bit signed number to the value of GPR[base] to form the effective address. Stores the
low-order bytes starting from the effective address in the aligned doubleword including the address into the
upper part of GPR[rt]. The low-order bytes of GPR[rt] that are not loaded are not changed.
LDL $24,10 ($0)
$24

$24

a

10

b

9

c

8

d

d

e

f

e

f

g

g

h

h

Address8

15

14

13

12

11

10

9

8

Address0

7

6

5

4

3

2

1

0

An Address Error exception due to alignment of the effective address does not occur.
LDL and LDR instructions in a pair are used to load an 8-byte block that does not conform to the
doubleword alignment.
Exceptions
TLB Refill, TLB Invalid, Address Error
Operation (128-bit bus)
vAddr ← sign_extend(offset) + GPR[base] 31..0
(pAddr, uncached) ← AddressTranslation (vAddr, DATA, LOAD)
3

pAddr ← pAddr(PSIZE-1)..3 || 0
byte ← 0 || vAddr2..0
doubleword ← vAddr3
memquad ← LoadMemory (uncached, byte, pAddr, vAddr, DATA)
GPR[rt]63..0 ← memquad(7+8*byte+64*doubleword)..(64*doubleword) || GPR[rt](55-8*byte)..0
The relation between the low-order 4 bits of the effective address vAddr and bytes that are to be loaded is
illustrated below.

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SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

MSB 63
a

Register
Address

vAddr3..0

0 LSB
b

c

d

e

f

g

h

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Contents of registers after instruction
(Shaded is unchanged)

Access
Type

bit 63

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

pAddr3..0

bit 0

b
0
1
2
3
4
5
6
b
8
9
10
11
12
13
14

c
c
0
1
2
3
4
5
c
c
8
9
10
11
12
13

d
d
d
0
1
2
3
4
d
d
d
8
9
10
11
12

e
e
e
e
0
1
2
3
e
e
e
e
8
9
10
11

f
f
f
f
f
0
1
2
f
f
f
f
f
8
9
10

g
g
g
g
g
g
0
1
g
g
g
g
g
g
8
9

h
h
h
h
h
h
h
0
h
h
h
h
h
h
h
8

7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0

0
0
0
0
0
0
0
0
8
8
8
8
8
8
8
8

Programming Notes
In the LDL instruction, the contents of GPR[rt] are referenced. However, since bypassing is performed
internally, even when loading the value in GPR[rt] in the preceding instruction, a NOP does not need to be
inserted between the instruction and the LDL instruction.

© SCEI
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SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

LDR : Load Doubleword Right
MIPS III
To load the lower part of an unaligned doubleword.
Operation Code
31

26

25

21

20

16

15

0

LDR
011011

base

rt

offset

6

5

5

16

Format
LDR rt, offset (base)
Description
GPR[rt] ← GPR[rt] MERGE memory [GPR[base] + offset]
Adds the offset as a 16-bit signed number to the value of GPR[base] to form the effective address. Stores the
high-order bytes starting from the effective address in the aligned doubleword including the address into the
lower part of GPR[rt]. The high-order bytes of GPR[rt] that are not loaded are not changed.
LDR$24,3($0)
$24

$24

a

a

b

b

c

c

d

7

e

6

f

5

g

4

h

3

Address8

15

14

13

12

11

10

9

8

Address0

7

6

5

4

3

2

1

0

An Address Error exception due to alignment of the effective address does not occur.
LDR and LDL instructions in a pair are used to load an 8-byte block that does not conform to doubleword
alignment.
Exceptions
TLB Refill, TLB Invalid, Address Error
Operation (128-bit bus)
vAddr ← sign_extend(offset) + GPR[base] 31..0
(pAddr, uncached) ← AddressTranslation (vAddr, DATA, LOAD)
pAddr ← pAddr(PSIZE-1)..0
byte ← 0 || vAddr2..0
doubleword ← vAddr3
memquad ← LoadMemory (uncached, byte, pAddr, vAddr, DATA)
GPR[rt]63..0 ← GPR[rt]63..(64-8*byte) || memquad(63+64*doubleword)..(64*doubleword+8*byte)
The relation between the low-order 4 bits of the effective address vAddr and bytes that are to be loaded is
illustrated below.

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SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

MSB 63
Register
Address

vAddr3..0

0 LSB

a

b

c

d

e

f

g

h

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Contents of registers after instruction
(Shaded is unchanged)

Access
Type

bit 63

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

7
a
a
a
a
a
a
a
15
a
a
a
a
a
a
a

pAddr3..0

bit 0

6
7
b
b
b
b
b
b
14
15
b
b
b
b
b
b

5
6
7
c
c
c
c
c
13
14
15
c
c
c
c
c

4
5
6
7
d
d
d
d
12
13
14
15
d
d
d
d

3
4
5
6
7
e
e
e
11
12
13
14
15
e
e
e

2
3
4
5
6
7
f
f
10
11
12
13
14
15
f
f

1
2
3
4
5
6
7
g
9
10
11
12
13
14
15
g

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

Programming Notes
In the LDR instruction, the contents of GPR[rt] are referenced. However, since bypassing is performed
internally, even when loading the value in GPR[rt] in the preceding instruction, a NOP does not need to be
inserted between the instruction and the LDR instruction.

© SCEI
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SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

LH : Load Halfword
MIPS I
To load a halfword from memory as a signed value.
Operation Code
31

26

25

21

20

16

15

0

LH
100001

base

rt

offset

6

5

5

16

Format
LH rt, offset(base)
Description
GPR[rt] ← memory [GPR[base] + offset]
Adds the offset as a 16-bit signed number to the value of GPR[base] to form the effective address. Loads the
halfword data at the address, sign-extends it and stores it in GPR[rt].
Restrictions
The effective address must conform to halfword alignment. That is, if the least-significant bit of the address
is non-zero, an Address Error exception occurs.
Exceptions
TLB Refill, TLB Invalid, Address Error
Operation (128-bit bus)
vAddr ← sign_extend (offset) + GPR[base] 31..0
if (vAddr0) ≠ 0 then SignalException (AddressError) endif
(pAddr, uncached) ← AddressTranslation (vAddr, DATA, LOAD)
pAddr ← pAddr(PSIZE-1)..0
memquad ← LoadMemory (uncached, HALFWORD, pAddr, vAddr, DATA)
byte ← vAddr3..0
GPR[rt]63..0 ← sign_extend (memquad(15+8*byte)..8*byte)

© SCEI
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EE Core Instruction Set Manual Version 6.0

LHU : Load Halfword Unsigned
MIPS I
To load a halfword from memory as an unsigned value.
Operation Code
31

26

25

21

20

16

15

0

LHU
100101

base

rt

offset

6

5

5

16

Format
LHU rt, offset (base)
Description
GPR[rt] ← memory [GPR[base] + offset]
Adds the offset as a 16-bit signed number to the value of GPR[base] to form the effective address. Loads the
halfword at the address, zero-extends it and stores it in GPR[rt].
Restrictions
The effective address must conform to halfword alignment. That is, if the least-significant bit of the address
is non-zero, an Address Error exception occurs.
Exceptions
TLB Refill, TLB Invalid, Address Error
Operation (128-bit bus)
vAddr ← sign_extend (offset) + GPR[base] 31..0
if (vAddr0) ≠ 0 then SignalException (AddressError) endif
(pAddr, uncached) ← AddressTranslation (vAddr, DATA, LOAD)
pAddr ← pAddr(PSIZE-1)..0
memquad ← LoadMemory (uncached, HALFWORD, pAddr, vAddr, DATA)
byte ← vAddr3..0
GPR[rt]63..0 ← zero_extend (memquad(15+8*byte)..8*byte)

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SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

LUI : Load Upper Immediate
MIPS I
To load a constant into the upper half of a word.
Operation Code
31

26

25

21

20

16

15

0

LUI
001111

0
00000

rt

immediate

6

5

5

16

Format
LUI rt, immediate
Description
GPR[rt] ← immediate || 016
Shifts the 16-bit immediate value left 16 bits, adds 16 bits of low-order zeros, sign-extends it and stores it in
GPR[rt].
Exceptions
None
Operation
GPR[rt] 63..0 ← sign_extend (immediate || 016)

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SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

LW : Load Word
MIPS I
To load a word from memory as a signed value.
Operation Code
31

26

25

21

20

16

15

0

LW
100011

base

rt

offset

6

5

5

16

Format
LW rt, offset (base)
Description
GPR[rt] ← memory [GPR[base] + offset]
Adds the offset as a 16-bit signed number to the value of GPR[base] to form the effective address. Loads the
word data at the address, sign-extends it and stores it in GPR[rt].
Restrictions
The effective address must conform to halfword alignment. That is, if the two least-significant bits of the
address are non-zero, an Address Error exception occurs.
Exceptions
TLB Refill, TLB Invalid, Address Error
Operation (128-bit bus)
vAddr ← sign_extend (offset) + GPR[base] 31..0
if (vAddr1..0) ≠ 02 then SignalException (AddressError) endif
(pAddr, uncached) ← AddressTranslation (vAddr, DATA, LOAD)
pAddr ← pAddr(PSIZE-1)..0
memquad ← LoadMemory (uncached, WORD, pAddr, vAddr, DATA)
byte ← vAddr3..0
GPR[rt] 63..0 ← sign_extend (memquad(31+8*byte)..8*byte)

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SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

LWL : Load Word Left
MIPS I
To load the upper part of an unsigned word.
Operation Code
31

26

25

21

20

16

15

0

LWL
100010

base

rt

offset

6

5

5

16

Format
LWL rt, offset (base)
Description
GPR[rt] ← GPR[rt] MERGE memory [GPR[base] + offset]
Adds the offset as a 16-bit signed number to the value of GPR[base] to form the effective address that is
considered to be the most-significant byte of the target word. Loads the low-order bytes of the aligned word
that contains the most-significant byte into the corresponding bytes of GPR[rt]. The high-order words of
GPR[rt] are sign-extended and the low-order bytes of GPR[rt] that are not loaded are not changed.
LWL $24,4($0)
$24

$24

H

G

F

E

← Sign-extend

D

4

C

C

B

B

A

A

Address8

15

14

13

12

11

10

9

8

Address0

7

6

5

4

3

2

1

0

An Address Error exception due to alignment of the effective address does not occur.
LWL and LWR instructions in a pair are used to load the 4-byte blocks that do not conform to word
alignment.
Exceptions
TLB Refill, TLB Invalid, Address Error
Operation (128-bit bus)
vAddr ← sign_extend (offset) + GPR[base] 31..0
(pAddr, uncached) ← AddressTranslation (vAddr, DATA, LOAD)
pAddr ← pAddr(PSIZE-1)..3 || 03
byte ← 02 || vAddr1..0
word ← vAddr3..2
memquad ← LoadMemory (uncached, byte, pAddr, vAddr, DATA)
temp ← memquad(32*word+8*byte+7)..32*word || GPR[rt](23-8*byte)..0
GPR[rt] 63..0 ← (temp31)32 || temp
The relation between the low-order 4 bits of the effective address vAddr and bytes that are to be loaded is
illustrated below.

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SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

MSB 63
a

Register
Address

vAddr3..0

0 LSB
b

d

e

f

g

h

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Contents of registers after instruction
(Shaded is unchanged)
bit 63

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

c

Sign extension of 0←
Sign extension of 1←
Sign extension of 2←
Sign extension of 3←
Sign extension of 4←
Sign extension of 5←
Sign extension of 6←
Sign extension of 7←
Sign extension of 8←
Sign extension of 9←
Sign extension of 10←
Sign extension of 11←
Sign extension of 12←
Sign extension of 13←
Sign extension of 14←
Sign extension of 15←

32

Access
Type

31

pAddr3..0

bit 0

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

f
0
1
2
f
4
5
6
f
8
9
10
f
12
13
14

g
g
0
1
g
g
4
5
g
g
8
9
g
g
12
13

h
h
h
0
h
h
h
4
h
h
h
8
h
h
h
12

0
1
2
3
0
1
2
3
0
1
2
3
0
1
2
3

0
0
0
0
4
4
4
4
8
8
8
8
12
12
12
12

Programming Notes
In the LWL instruction, the contents of GPR[rt] are referenced. However, since bypassing is performed
internally, even when loading the value in GPR[rt] in the preceding instruction, a NOP does not need to be
inserted between the instruction and the LWL instruction.
An instruction that treats an unaligned word as unsigned is not provided.

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SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

LWR : Load Word Right
MIPS I
To load the lower part of an unsigned word.
Operation Code
31

26

25

21

20

16

15

0

LWR
100110

base

rt

offset

6

5

5

16

Format
LWR rt, offset (base)
Description
GPR[rt] ← GPR[rt] MERGE memory [GPR[base] + offset]
Adds the offset as a 16-bit signed number to the value of GPR[base] to form the effective address that is
considered to be the least-significant byte of the target word. Loads the high-order bytes in the aligned word
that contains the least-significant byte into the corresponding bytes of GPR[rt]. Bytes of GPR[rt] that are not
loaded are not changed. But if the sign bit (bit 31) is loaded, they are sign-extended to bits 63 to 32.
LWR $24,1($0)
$24

$24

H

H

G

G

F

F

E

E

D

D

C

3

B

2

A

1

Address8

15

14

13

12

11

10

9

8

Address0

7

6

5

4

3

2

1

0

An Address Error exception due to alignment of the effective address does not occur.
LWR and LWL instructions in a pair are used to load 4-byte blocks that do not conform to word alignment.
Exceptions
TLB Refill, TLB Invalid, Address Error
Operation (128-bit bus)
vAddr ← sign_extend (offset) + GPR[base]31..0
(pAddr, uncached) ← AddressTranslation (vAddr, DATA, LOAD)
pAddr ← pAddr(PSIZE-1)..0
byte ← 0 || vAddr1..0
word ← vAddr3..2
memquad ← LoadMemory (uncached, byte, pAddr, vAddr, DATA)
temp ← GPR[rt]31..(32-8*byte) || memquad(31+32*word)..(32*word+8*byte)
if byte = 4 then
/* If loads bit 31, then sign-extends */
utemp ← (temp31)32
else
utemp ← GPR[rt]63..32
/* Otherwise, the high-order 4 bytes are not changed */
endif
GPR[rt] 63..0 ← utemp || temp
The relation between the low-order 4 bits of the effective address vAddr and bytes that are to be loaded is
illustrated below.

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SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

MSB 63
a

Register
Address

vAddr3..0

0 LSB
b

d

e

f

g

h

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Contents of registers after instruction
(Shaded is unchanged)
bit 63

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

c

a
a
a
a
a
a
a
a
a
a
a
a

Sign extension of 3←
b
c
d
b
c
d
b
c
d
Sign extension of 7←
b
c
d
b
c
d
b
c
d
Sign extension of 11←
b
c
d
b
c
d
b
c
d
Sign extension of 15←
b
c
d
b
c
d
b
c
d

32

Access
Type

31

3
e
e
e
7
e
e
e
11
e
e
e
15
e
e
e

pAddr3..0

bit 0

2
3
f
f
6
7
f
f
10
11
f
f
14
15
f
f

1
2
3
g
5
6
7
g
9
10
11
g
13
14
15
g

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

3
2
1
0
3
2
1
0
3
2
1
0
3
2
1
0

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

Programming Notes
In the LWL instruction, the contents of GPR[rt] are referenced. However, since bypassing is performed
internally, even when loading the value in GPR[rt] in the preceding instruction, a NOP does not need to be
inserted between the instruction and the LWL instruction.
An instruction that treats an unaligned word data as unsigned is not provided.

© SCEI
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SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

LWU : Load Word Unsigned
MIPS I
To load a word from memory as an unsigned value.
Operation Code
31

26

25

21

20

16

15

0

LWU
100111

base

rt

offset

6

5

5

16

Format
LWU rt, offset (base)
Description
GPR[rt] ← memory [GPR[base] + offset]
Adds the offset as a 16-bit signed number to the value of GPR[base] to form the effective address. Loads the
word data at the address, zero-extends it and stores it in GPR[rt].
Restrictions
The effective address must conform to word alignment. That is, if the two least-significant bits of the
address are non-zero, an Address Error exception occurs.
Exceptions
TLB Refill, TLB Invalid, Address Error
Operation (128-bit bus)
vAddr ← sign_extend (offset) + GPR[base] 31..0
if (vAddr1..0) ≠ 02 then SignalException (AddressError) endif
(pAddr, uncached) ← AddressTranslation (vAddr, DATA, LOAD)
pAddr ← pAddr(PSIZE-1)..0
memquad ← LoadMemory (uncached, WORD, pAddr, vAddr, DATA)
byte ← vAddr3..0
GPR[rt] 63..0 ← 032 || memquad(31+8*byte)..8*byte

© SCEI
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SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

MFHI : Move from HI Register
MIPS I
To move the contents of the HI register to a GPR.
Operation Code
31

26

25

16

15

11

10

6

5

0

SPECIAL
000000

0
00 0000 0000

rd

0
00000

MFHI
010000

6

10

5

5

6

Format
MFHI rd
Description
GPR[rd] ← HI
Stores the contents of HI register, which keeps the results of multiplication and division, in GPR[rd].
Exceptions
None
Operation
GPR[rd]63..0 ← HI63..0
Programming Notes
The HI register holds the upper part of the result from multiplication or multiply-accumulate or the
remainder from division.
Since an interlock works in EE Core, multiplication and division instructions can be directly followed by an
MFHI instruction.

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SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

MFLO : Move from LO Register
MIPS I
To move the contents of the LO register to a GPR.
Operation Code
31

26

25

16

15

11

10

6

5

0

SPECIAL
000000

0
00 0000 0000

rd

0
00000

MFLO
010010

6

10

5

5

6

Format
MFLO rd
Description
rd ← LO
Stores the contents of the LO register, which keeps the results of multiplication and division, in GPR[rd].
Exceptions
None
Operation
GPR[rd] 63..0 ← LO63..0
Programming Notes
The LO register holds the lower part of the result from multiplication or multiply accumulate or the quotient
from division.
Since an interlock works in EE Core, multiplication and division instructions can be directly followed by an
MFLO instruction.

© SCEI
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SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

MOVN : Move Conditional on Not Zero
MIPS IV
To move data between GPRs according to the value of a GPR.
Operation Code
31

26

25

21

20

16

15

11

10

6

5

0

SPECIAL
000000

rs

rt

rd

0
00000

MOVN
001011

6

5

5

5

5

6

Format
MOVN rd, rs, rt
Description
if (GPR[rt] ≠ 0) then GPR[rd] ← GPR[rs]
Checks the value of GPR[rt]. If it is not equal to zero, moves the contents of GPR[rs] to GPR[rd].
Exceptions
None
Operation
if GPR[rt] 63..0 ≠ 0 then
GPR[rd] 63..0 ← GPR[rs] 63..0
endif

© SCEI
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SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

MOVZ : Move Conditional on Zero
MIPS IV
To move data between GPRs according to the value of a GPR.
Operation Code
31

26

25

21

20

16

15

11

10

6

5

0

SPECIAL
000000

rs

rt

rd

0
00000

MOVZ
001010

6

5

5

5

5

6

Format
MOVZ rd, rs, rt
Description
if (GPR[rt] = 0) then GPR[rd] ← GPR[rs]
Checks the value of GPR[rt]. If the value is equal to zero, moves the contents of GPR[rs] to GPR[rd].
Exceptions
None
Operation
if GPR[rt] 63..0 = 0 then
GPR[rd] 63..0 ← GPR[rs] 63..0
endif

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SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

MTHI : Move to HI Register
MIPS I
To move the contents of a GPR to the HI register.
Operation Code
31

26

25

21

20

6

5

0

SPECIAL
000000

rs

0
000 0000 0000 0000

MTHI
010001

6

5

15

6

Format
MTHI rs
Description
HI ← GPR[rs]
Stores the contents of GPR[rs] to the HI register.
Exceptions
None
Operation
HI63..0 ← GPR[rs] 63..0
Programming Notes
The HI register holds the upper part of the result from multiplication or multiply-accumulate or the
remainder from division.

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SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

MTLO : Move to LO Register
MIPS I
To move the contents of a GPR to the LO register.
Operation Code
31

26

25

21

20

6

5

0

SPECIAL
000000

rs

0
000 0000 0000 0000

MTLO
010011

6

5

15

6

Format
MTLO rs
Description
LO ← GPR[rs]
Stores the contents of GPR[rs] in the LO register.
Exceptions
None
Operation
LO63..0 ← GPR[rs] 63..0
Programming Notes
The LO register holds the lower part of the result from multiplication or multiply-accumulate or the quotient
from division.

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SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

MULT : Multiply Word
MIPS I
To multiply 32-bit signed integers.
Operation Code
31

26

25

21

20

16

15

6

5

0

SPECIAL
000000

rs

rt

0
00 0000 0000

MULT
011000

6

5

5

10

6

Format
MULT rs, rt
Description
(LO, HI) ← GPR[rs] × GPR[rt]
Multiplies the 32-bit value in GPR[rt] by the 32-bit value in GPR[rs] as signed integer values. The low-order
32 bits and the high-order 32 bits of the 64-bit result are stored in the LO and HI registers respectively.
Restrictions
If GPR[rt] and GPR[rs] are not sign-extended 32-bit values (bits 63..31 equal), then the result of the
operation is undefined.
Exceptions
None. No arithmetic exception occurs.
Operation
if (NotWordValue (GPR[rs]) or NotWordValue (GPR[rt])) then UndefinedResult() endif
prod ← GPR[rs]31..0 × GPR[rt]31..0
LO63..0 ← (prod31)32 || prod31..0
HI63..0 ← (prod63)32 || prod63..32
Programming Notes
In the EE Core, the integer multiply operation proceeds asynchronously. An attempt to read the contents of
the LO or HI register before the multiply operation finishes will result in an interlock. Other CPU
instructions can execute without delay. Therefore, scheduling the multiply operation appropriately will
improve performance.
Even when the result of the multiply operation overflows, the Overflow exception does not occur. If
Overflow must be detected, an explicit check is necessary.
In the EE Core, the MULT instruction has been extended to three-operand instruction that can store the
result of operation in a GPR as well. See "3. EE Core-Specific Instruction Set" about the usage as a threeoperand instruction.

© SCEI
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SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

MULTU : Multiply Unsigned Word
MIPS I
To multiply 32-bit unsigned integers.
Operation Code
31

26

25

21

20

16

15

6

5

0

SPECIAL
000000

rs

rt

0
00 0000 0000

MULTU
011001

6

5

5

10

6

Format
MULTU rs, rt
Description
(LO, HI) ← GPR[rs] × GPR[rt]
Multiplies the 32-bit value in GPR[rt] by the 32-bit value in GPR[rs] as unsigned integer values. The loworder 32-bit and the high-order 32-bit of a 64-bit result are stored in the LO and HI registers respectively.
Restrictions
GPR[rt] and GPR[rs] are not sign-extended 32-bit values (bits 63..31 equal), then the result of the operation
is undefined.
Exceptions
None. No arithmetic exception occurs.
Operation
if (NotWordValue (GPR[rs]) or NotWordValue (GPR[rt])) then UndefinedResult() endif
prod ← (0 || GPR[rs]31..0 ) × (0 || GPR[rt]31..0)
LO63..0 ← (prod31)32 || prod31..0
HI63..0 ← (prod63)32 || prod63..32
Programming Notes
In the EE Core, the integer multiply operation proceeds asynchronously. An attempt to read the contents of
the LO or HI register before the multiply operation finishes will result in an interlock. Other CPU
instructions can execute without delay. Therefore, scheduling the multiply operation appropriately will
improve performance.
Even when the result of a multiply operation overflows, an Overflow exception does not occur. If Overflow
must to be detected, an explicit check is necessary.
In EE Core, the MULTU instruction has been extended to be a three-operand instruction that can store the
result of operation in a GPR as well. See "3. EE Core-Specific Instruction Set" about the usage as a threeoperand instruction.

© SCEI
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SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

NOR : Not Or
MIPS I
To perform a bitwise logical NOT OR.
Operation Code
31

26

25

21

20

16

15

11

10

6

5

0

SPECIAL
000000

rs

rt

rd

0
00000

NOR
100111

6

5

5

5

5

6

Format
NOR rd, rs, rt
Description
GPR[rd] ← GPR[rs] NOR GPR[rt]
Performs a bitwise logical NOR between the contents of GPR[rs] and GPR[rt]. The result is stored in
GPR[rd].
The truth table value for NOR is as follows;
X
0
0
1
1

Y
0
1
0
1

X NOR Y
1
0
0
0

Exceptions
None
Operation
GPR[rd] 63..0 ← GPR[rs] 63..0 NOR GPR[rt] 63..0

© SCEI
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SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

OR : Or
MIPS I
To perform a bitwise logical OR.
Operation Code
31

26

25

21

20

16

15

11

10

6

5

0

SPECIAL
000000

rs

rt

rd

0
00000

OR
100101

6

5

5

5

5

6

Format
OR rd, rs, rt
Description
GPR[rd] ← GPR[rs] OR GPR[rt]
Performs a bitwise logical OR between the contents of GPR[rs] and GPR[rt]. The result is stored in
GPR[rd].
The truth table value for OR is as follows:
X
0
0
1
1

Y
0
1
0
1

X OR Y
0
1
1
1

Exceptions
None
Operation
GPR[rd] 63..0 ← GPR[rs] 63..0 OR GPR[rt] 63..0

© SCEI
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SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

ORI : Or immediate
MIPS I
To perform a bitwise logical OR between a constant and a GPR.
Operation Code
31

26

25

21

20

16

15

0

ORI
001101

rs

rt

immediate

6

5

5

16

Format
ORI rt, rs, immediate
Description
GPR[rt] ← GPR[rs] OR immediate
Performs a bitwise logical OR between the sign-extended value of the 16-bit immediate field and the
contents of GPR[rs]. The result is stored in GPR[rt].
The truth table value for OR is as follows:
X
0
0
1
1

Y
0
1
0
1

X OR Y
0
1
1
1

Exceptions
None
Operation
GPR[rt] 63..0 ← (048 || immediate) OR GPR[rs] 63..0

© SCEI
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SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

PREF : Prefetch
MIPS IV
To prefetch data from memory.
Operation Code
31

26

25

21

20

16

15

0

PREF
110011

base

hint

offset

6

5

5

16

Format
PREF hint, offset(base)
Description
prefetch_memory(GPR[base]+offset)
The data at the effective address, obtained by adding the offset as a 16-bit signed integer to the value of
GPR[base], is read into the cache, if possible. It does not affect the meaning of the program but can help
improve its performance.
The value of hint is to specify the details of the Prefetch operation as defined in the following table.
Value

Name

Prefetch Operation

0

load

Read into cache for loading data.

1-31

(Reserved)

(Same in case specifies 0)

Addressing-related exceptions do not occur. If an exception should be generated, it is ignored and Prefetch
does not take place. However, operations such as a writeback of a dirty cache line might take place.
Exceptions
None
Operation
vAddr ← GPR[base] + sign_extend (offset)
(pAddr, uncached) ← AddressTranslation (vAddr, DATA, LOAD)
Prefetch (uncached, pAddr, vAddr, DATA, hint)
Programming Notes
Prefetch does not take place on uncached memory access locations. Prefetch, from memory locations not
present in the TLB, is not allowed. Memory pages that have not been accessed recently may not present in
the TLB, so prefetch may not be effective. In addition, prefetch may not take place when the bus is used for
read operations such as data cache miss, uncached load, and load to the uncached accelerated buffer.

© SCEI
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SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

SB : Store Byte
MIPS I
To store a byte in a GPR to memory.
Operation Code
31

26

25

21

20

16

15

0

SB
101000

base

rt

offset

6

5

5

16

Format
SB rt, offset (base)
Description
memory [GPR[base] + offset] ← GPR[rt]
Stores the least-significant byte of GPR[rt] in memory at the effective address obtained by adding the offset
as a 16-bit signed integer to the value of GPR[base].
Exceptions
TLB Refill, TLB Invalid, TLB Modified, Address Error
Operation (128-bit bus)
vAddr ← sign_extend (offset) + GPR[base]31..0
(pAddr, uncached) ← AddressTranslation (vAddr, DATA, STORE)
pAddr ← pAddr(PSIZE-1)..0
byte ← vAddr3..0
dataquad ← GPR[rt](127-8*byte)..0 || 08*byte
StoreMemory (uncached, BYTE, dataquad, pAddr, vAddr, DATA)

© SCEI
-97-

SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

SD : Store Doubleword
MIPS III
To store a doubleword in a GPR to memory.
Operation Code
31

26

25

21

20

16

15

0

SD
111111

base

rt

offset

6

5

5

16

Format
SD rt, offset (base)
Description
memory [GPR[base] + offset] ← GPR[rt]
Stores the 64-bit value of GPR[rt] in memory at the effective address obtained by adding the offset as a 16bit signed integer to the value of GPR[base].
Restrictions
The effective address must conform to doubleword alignment. That is, if any of the three least-significant
bits of the address are non-zero, an Address Error exception occurs.
Exceptions
TLB Refill, TLB Invalid, TLB Modified, Address Error
Operation (128-bit bus)
vAddr ← sign_extend (offset) + GPR[base]
if (vAddr2..0) ≠ 03 then SignalException (AddressError) endif
(pAddr, uncached) ← AddressTranslation (vAddr, DATA, STORE)
pAddr ← pAddr(PSIZE-1)..0
byte ← vAddr3..0
dataquad ← GPR[rt](127-8*byte)..0 || 08*byte
StoreMemory (uncached, DOUBLEWORD, dataquad, pAddr, vAddr, DATA)

© SCEI
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SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

SDL : Store Doubleword Left
MIPS III
To load the upper part of a doubleword to an unaligned memory address.
Operation Code
31

26

25

21

20

16

15

0

SDL
101100

base

rt

offset

6

5

5

16

Format
SDL rt, offset (base)
Description
memory [GPR[base] + offset] ← GPR[rt]
Adds the offset as a 16-bit signed number to the value of GPR[base] to form the effective address. Stores the
high-order bytes of GPR[rt] in the lower part of the aligned doubleword starting with the effective address.
SDL $24,10($0)

$24

a

b

c

d

e

f

g

Address8

15

14

13

12

11

10

9

8

Address0

7

6

5

4

3

2

1

0

Address8

15

14

13

12

11

a

b

c

Address0

7

6

5

4

3

2

1

0

h

Address Error exceptions due to the alignment of the effective address do not occur.
SDL and SDR instructions in a pair are used to store doubleword data in an 8-byte block that does not
conform to doubleword alignment.
Exceptions
TLB Refill, TLB Invalid, TLB Modified, Address Error
Operation (128-bit bus)
vAddr ← sign_extend (offset) + GPR[base]31..0
(pAddr, uncached) ← AddressTranslation (vAddr, DATA, STORE)
pAddr ← pAddr(PSIZE-1)..3 || 03
byte ← 0 || vAddr2..0
if (vAddr3 = 0) then
dataquad ← 064 || 0(56-8*byte) || GPR[rt]63..(56-8*byte)
else
dataquad ← 0(56-8*byte) || GPR[rt]63..(56-8*byte) || 064
endif
StoreMemory (uncached, byte, dataquad, pAddr, vAddr, DATA)
The relation between the low-order 4 bits of the effective address vAddr and bytes that are to be stored is
illustrated below.

© SCEI
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SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

MSB 63
Register

a

Address

vAddr3..0

0 LSB
b

c

d

e

f

g

h

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Contents of registers after instruction
(Shaded is unchanged)

Access
Type

bit 63

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
a

14
14
14
14
14
14
14
14
14
14
14
14
14
14
a
b

pAddr3..0

bit 0

13
13
13
13
13
13
13
13
13
13
13
13
13
a
b
c

12
12
12
12
12
12
12
12
12
12
12
12
a
b
c
d

11
11
11
11
11
11
11
11
11
11
11
a
b
c
d
e

10 9
10 9
10 9
10 9
10 9
10 9
10 9
10 9
10 9
10 a
a b
b c
c d
d e
e f
f g

8
8
8
8
8
8
8
8
a
b
c
d
e
f
g
h

7
7
7
7
7
7
7
a
7
7
7
7
7
7
7
7

6
6
6
6
6
6
a
b
6
6
6
6
6
6
6
6

© SCEI
-100-

5
5
5
5
5
a
b
c
5
5
5
5
5
5
5
5

4
4
4
4
a
b
c
d
4
4
4
4
4
4
4
4

3
3
3
a
b
c
d
e
3
3
3
3
3
3
3
3

2
2
a
b
c
d
e
f
2
2
2
2
2
2
2
2

1
a
b
c
d
e
f
g
1
1
1
1
1
1
1
1

a
b
c
d
e
f
g
h
0
0
0
0
0
0
0
0

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

0
0
0
0
0
0
0
0
8
8
8
8
8
8
8
8

SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

SDR : Store Doubleword Right
MIPS III
To load the lower part of a doubleword to an unaligned memory address.
Operation Code
31

26

25

21

20

16

15

0

SDR
101101

base

rt

offset

6

5

5

16

Format
SDR rt, offset (base)
Description
memory [GPR[base] + offset] ← GPR[rt]
Adds the offset as a 16-bit signed number to the value of GPR[base] to form the effective address. Stores the
lower-order bytes of GPR[rt] in the upper part of the aligned doubleword starting with the effective address.
SDL $24,3($0)

$24

a

b

c

d

e

f

g

Address8

15

14

13

12

11

10

9

8

Address0

7

6

5

4

3

2

1

0

Address8

15

14

13

12

11

10

9

8

Address0

d

e

f

g

h

2

1

0

h

Address Error exceptions due to alignment of the effective address do not occur.
SDR and SDL instructions in a pair are used to store the doubleword data in an 8-byte block that does not
conform to doubleword alignment.
Exceptions
TLB Refill, TLB Invalid, TLB Modified, Address Error
Operation (128-bit bus)
vAddr ← sign_extend (offset) + GPR[base]31..0
(pAddr, uncached) ← AddressTranslation (vAddr, DATA, STORE)
pAddr ← pAddr(PSIZE-1)..3 || 03
byte ← vAddr2..0
if(vAddr3 = 0) then
dataquad ← 064 || GPR[rt](63-8*byte)..0 || 08*byte
else
dataquad ← GPR[rt](63-8*byte)..0 || 08*byte || 064
endif
StoreMemory (uncached, DOUBLEWORD-byte, dataquad, pAddr, vAddr, DATA)
The relation between the low-order 4 bits of the effective address vAddr and bytes that are to be stored is
illustrated below.

© SCEI
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SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

MSB 63
a

Register
Address

vAddr3..0

0 LSB
b

c

d

e

15

14

13

12

11

10

9

15

14

13

12

11

10

9

f
8
8

g

h

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

Contents of registers after instruction
(Shaded is unchanged)
bit 63

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

15
15
15
15
15
15
15
15
a
b
c
d
e
f
g
h

14
14
14
14
14
14
14
14
b
c
d
e
f
g
h
14

Access
Type

pAddr3..0

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

8
8
8
8
8
8
8
8
0
0
0
0
0
0
0
0

bit 0

13
13
13
13
13
13
13
13
c
d
e
f
g
h
13
13

12
12
12
12
12
12
12
12
d
e
f
g
h
12
12
12

11
11
11
11
11
11
11
11
e
f
g
h
11
11
11
11

10
10
10
10
10
10
10
10
f
g
h
10
10
10
10
10

9
9
9
9
9
9
9
9
g
h
9
9
9
9
9
9

8
8
8
8
8
8
8
8
h
8
8
8
8
8
8
8

a
b
c
d
e
f
g
h
7
7
7
7
7
7
7
7

© SCEI
-102-

b
c
d
e
f
g
h
6
6
6
6
6
6
6
6
6

c
d
e
f
g
h
5
5
5
5
5
5
5
5
5
5

d
e
f
g
h
4
4
4
4
4
4
4
4
4
4
4

e
f
g
h
3
3
3
3
3
3
3
3
3
3
3
3

f
g
h
2
2
2
2
2
2
2
2
2
2
2
2
2

g
h
1
1
1
1
1
1
1
1
1
1
1
1
1
1

h
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

SH : Store Halfword
MIPS I
To store a halfword in memory.
Operation Code
31

26

25

21

20

16

15

0

SH
101001

base

rt

offset

6

5

5

16

Format
SH rt, offset (base)
Description
memory [GPR[base] + offset] ← GPR[rt]
Stores the least-significant 16-bit values of GPR[rt] in memory at the effective address obtained by adding
the offset as a 16-bit signed integer to the value of GPR[base].
Restrictions
The effective address must conform to halfword alignment. If the least-significant bit of the address is not
zero, an Address Error exception occurs.
Exceptions
TLB Refill, TLB Modified, Address Error
Operation (128-bit bus)
vAddr ← sign_extend(offset) + GPR[base]31..0
if (vAddr0) ≠ 0 then SignalException (AddressError) endif
(pAddr, uncached) ← AddressTranslation (vAddr, DATA, STORE)
pAddr ← pAddr(PSIZE-1)..0
byte ← vAddr3..0
dataquad ← GPR[rt](127-8*byte)..0 || 08*byte
StoreMemory (uncached, HALFWORD, dataquad, pAddr, vAddr, DATA)

© SCEI
-103-

SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

SLL : Shift Word Left Logical
MIPS I
To left shift a word. The shift amount is a fixed value (0-31 bits) specified by sa.
Operation Code
31

26

25

21

20

16

15

11

10

6

5

0

SPECIAL
000000

0
00000

rt

rd

sa

SLL
000000

6

5

5

5

5

6

Format
SLL rd, rt, sa
Description
GPR[rd] ← GPR[rt] << sa
Shifts the 32-bit data in GPR[rt] left by the bit count specified by sa, inserting zeros into the emptied bits.
The 32-bit result is sign-extended into 64-bit destination register and stored in GPR[rd].
Restrictions
None. Unlike nearly all other word operations, the input operand does not have to be a sign-extended 32-bit
value (bits 63..32 equal).
Exceptions
None
Operation
s ← sa
temp ← GPR[rt](31-s)..0 || 0s
GPR[rd]63..0 ← sign_extend (temp31..0)
Programming Notes
If sa is zero, GPR[rt] is truncated to 32-bits and sign extended to 64-bits to store in GPR[rd].

© SCEI
-104-

SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

SLLV : Shift Word Left Logical Variable
MIPS I
To left shift a word. The shift amount is specified by a GPR (0-31 bits).
Operation Code
31

26

25

21

20

16

15

11

10

6

5

0

SPECIAL
000000

rs

rt

rd

0
00000

SLLV
000100

6

5

5

5

5

6

Format
SLLV rd, rt, rs
Description
GPR[rd] ← GPR[rt] << GPR[rs]
Shifts the lower 32-bit of GPR[rt] left by the bit count specified by the low-order five bits of GPR[rs],
inserting zeros into the emptied bits. The 32-bit result is sign-extended and stored in GPR[rd].
Restrictions
None. Unlike nearly all other word operations, the input operand does not have to be a sign-extended 32-bit
value (bits 63..32 equal).
Exceptions
None
Operation
s ← GPR[rs]4..0
temp ← GPR[rt](31-s)..0 || 0s
GPR[rd]63..0 ← sign_extend(temp31..0)

© SCEI
-105-

SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

SLT : Set on Less Than
MIPS I
To compare the value of GPRs as signed integers.
Operation Code
31

26

25

21

20

16

15

11

10

6

5

0

SPECIAL
000000

rs

rt

rd

0
00000

SLT
101010

6

5

5

5

5

6

Format
SLT rd, rs, rt
Description
GPR[rd] ← (GPR[rs] < GPR[rt])
Compares the contents of GPR[rs] and GPR[rt] as signed integers. If GPR[rs] is less than GPR[rt], stores 1
in GPR[rd]. Otherwise, stores 0 in GPR[rd].
Exceptions
None. An Integer Overflow exception does not occur due to the arithmetic comparison.
Operation
if GPR[rs]63..0 < GPR[rt] 63..0 then
GPR[rd] 63..0 ← 0GPRLEN-1 || 1
else
GPR[rd] 63..0 ← 0GPRLEN
endif

© SCEI
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SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

SLTI : Set on Less Than Immediate
MIPS I
To compare a GPR with a constant as signed integers.
Operation Code
31

26

25

21

20

16

15

0

SLTI
001010

rs

rt

immediate

6

5

5

16

Format
SLTI rt, rs, immediate
Description
GPR[rt] ← (GPR[rs] < immediate)
Compares the contents of GPR[rs] with immediate value as signed integers. If GPR[rs] is less than
immediate, stores 1 in GPR[rd]. Otherwise, stores 0 in GPR[rd].
Exceptions
None. An Integer Overflow exception does not occur due to the arithmetic comparison.
Operation
if GPR[rs] 63..0 < sign_extend (immediate) then
GPR[rd] 63..0 ← 0GPRLEN-1 || 1
else
GPR[rd] 63..0 ← 0GPRLEN
endif

© SCEI
-107-

SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

SLTIU : Set on Less Than Immediate Unsigned
MIPS I
To compare a GPR with a constant unsigned integer.
Operation Code
31

26

25

21

20

16

15

0

SLTIU
001011

rs

rt

immediate

6

5

5

16

Format
SLTIU rt, rs, immediate
Description
GPR[rt] ← (GPR[rs] < immediate)
Compares the contents of GPR[rs] with the sign-extended immediate value as unsigned integers. If GPR[rs]
is less than immediate, stores 1 in GPR[rd]. Otherwise, stores 0 in GPR[rd].
Exceptions
None. An Integer Overflow exception does not occur due to the arithmetic comparison.
Operation
if (0 || GPR[rs] 63..0) < (0 || sign_extend (immediate)) then
GPR[rd] 63..0 ← 0GPRLEN-1 || 1
else
GPR[rd] 63..0 ← 0GPRLEN
endif
Programming Notes
Because the 16-bit immediate is sign-extended before comparison, the range of numeric values that the
immediate represents is not sequential, but split into two areas; around the smallest and largest 64-bit
unsigned integers. That is [0,32767] and [max_unsigned-32767, max_unsigned], respectively.

© SCEI
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SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

SLTU : Set on Less Than Unsigned
MIPS I
To compare the value of GPRs as unsigned integers.
Operation Code
31

26

25

21

20

16

15

11

10

6

5

0

SPECIAL
000000

rs

rt

rd

0
00000

SLTU
101011

6

5

5

5

5

6

Format
SLTU rd, rs, rt
Description
GPR[rd] ← (GPR[rs] < GPR[rt])
Compares the contents of GPR[rs] and GPR[rt] as unsigned integers. If GPR[rs] is less than GPR[rt], stores
1 in GPR[rd]. Otherwise, stores 0 in GPR[rd].
Exceptions
None. An Integer Overflow exception due to the arithmetic comparison does not occur.
Operation
if (0 || GPR[rs] 63..0) < (0 || GPR[rt] 63..0) then
GPR[rd] 63..0 ← 0GPRLEN-1 || 1
else
GPR[rd] 63..0 ← 0GPRLEN
endif

© SCEI
-109-

SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

SRA : Shift Word Right Arithmetic
MIPS I
To arithmetic right shift a word. The shift amount is a fixed value (0-31 bits) specified by sa.
Operation Code
31

26

25

21

20

16

15

11

10

6

5

0

SPECIAL
000000

0
00000

rt

rd

sa

SRA
000011

6

5

5

5

5

6

Format
SRA rd, rt, sa
Description
GPR[rd] ← GPR[rt] >> sa (arithmetic)
Shifts the lower 32 bits of GPR[rt] right by the bit count specified by sa, duplicating the sign bit (bit 31) into
the emptied bits. The 32-bit result is sign-extended and stored in GPR[rd].
Restrictions
If GPR[rt] is not a sign-extended 32-bit value (bits 63..31 equal), then the result of the operation is
undefined.
Exceptions
None
Operation
if (NotWordValue (GPR[rt] 63..0 )) then UndefinedResult () endif
s ← sa
temp ← (GPR[rt]31)s || GPR[rt]31..s
GPR[rd] 63..0 ← sign_extend (temp31..0)

© SCEI
-110-

SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

SRAV : Shift Word Right Arithmetic Variable
MIPS I
To arithmetic right shift a word. The shift amount is specified by a GPR (0-31 bits).
Operation Code
31

26

25

21

20

16

15

11

10

6

5

0

SPECIAL
000000

rs

rt

rd

0
00000

SRAV
000111

6

5

5

5

5

6

Format
SRAV rd, rt, rs
Description
GPR[rd] ← GPR[rt] >> GPR[rs]
(arithmetic)
Shifts the lower 32 bits of GPR[rt] right by the bit count specified by the low-order five bits of GPR[rs],
inserting the sign bit (bit 31) into the emptied bits. The 32-bit result is sign-extended and stored in GPR[rd].
Restrictions
If the value of GPR[rt] is not a sign-extended 32-bit value (bits 63..31 equal), then the result of the operation
is undefined.
Exceptions
None
Operation
if (NotWordValue (GPR[rt] 63..0 )) then UndefinedResult () endif
s ← GPR[rs]4..0
temp ← (GPR[rt]31)s || GPR[rt]31..s
GPR[rd] 63..0 ← sign_extend (temp31..0)

© SCEI
-111-

SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

SRL : Shift Word Right Logical
MIPS I
To logical right shift a word. The shift amount is a fixed value (0-31 bits) specified by sa.
Operation Code
31

26

25

21

20

16

15

11

10

6

5

0

SPECIAL
000000

0
00000

rt

rd

sa

SRL
000010

6

5

5

5

5

6

Format
SRL rd, rt, sa
Description
GPR[rd] ← GPR[rt] >> sa (logical)
Shifts the low-order 32 bits of GPR[rt] right by the bit count specified by sa, inserting zeros into the emptied
bits. The 32-bit result is sign-extended and stored in GPR[rd].
Restrictions
If the value of GPR[rt] is not a sign-extended 32-bit value (bits 63..31 equal), then the result of the operation
is undefined.
Exceptions
None
Operation
if (NotWordValue (GPR[rt] 63..0)) then UndefinedResult () endif
s ← sa
temp ← 0s || GPR[rt]31..s
GPR[rd] 63..0 ← sign_extend(temp31..0)

© SCEI
-112-

SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

SRLV : Shift Word Right Logical Variable
MIPS I
To logical right shift a word. The shift amount is specified by a GPR (0-31 bits).
Operation Code
31

26

25

21

20

16

15

11

10

6

5

0

SPECIAL
000000

rs

rt

rd

0
00000

SRLV
000110

6

5

5

5

5

6

Format
SRLV rd, rt, rs
Description
GPR[rd] ← GPR[rt] >> GPR[rs]
(logical)
Shifts the low-order 32 bits of GPR[rt] right by the bit count specified by the low-order five bits of GPR[rs],
inserting zeros into the emptied bits. The 32-bit result is sign-extended and stored in GPR[rd].
Restrictions
If the value of GPR[rt] is not a sign-extended 32-bit value (bits 63..31 equal), then the result of the operation
is undefined.
Exceptions
None
Operation
if (NotWordValue (GPR[rt] 63..0)) then UndefinedResult () endif
s ← GPR[rs]4..0
temp ← 0s || GPR[rt]31..s
GPR[rd] 63..0 ← sign_extend (temp31..0)

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SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

SUB : Subtract Word
MIPS I
To subtract 32-bit integers. Traps if overflow occurs.
Operation Code
31

26

25

21

20

16

15

11

10

6

5

0

SPECIAL
000000

rs

rt

rd

0
00000

SUB
100010

6

5

5

5

5

6

Format
SUB rd, rs, rt
Description
GPR[rd] ← GPR[rs] — GPR[rt]
Subtracts the low-order 32-bit value in GPR[rt] from the lower 32-bit value in GPR[rs]. The 32-bit result is
sign-extended and stored in GPR[rd]. If the subtraction results in 32-bit 2's complement arithmetic overflow,
then the contents of GPR[rd] are not changed and an Integer Overflow exception occurs.
Restrictions
If the values of GPR[rs] and GPR[rt] are not sign-extended 32-bit values (bits 63..31 equal), then the result of
the operation is undefined.
Exceptions
Integer Overflow
Operation
if (NotWordValue (GPR[rs] 63..0) or NotWordValue (GPR[rt] 63..0)) then UndefinedResult () endif
temp ← GPR[rs] 63..0 — GPR[rt] 63..0
if (32_bit_arithmetic_overflow) then
SignalException (IntegerOverflow)
else
GPR[rd] 63..0 ← sign_extend (temp31..0)
endif
Programming Notes
SUBU performs the same arithmetic operation, but does not trap on overflow.

© SCEI
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SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

SUBU : Subtract Unsigned Word
MIPS I
To subtract 32-bit integers and ignore overflow.
Operation Code
31

26

25

21

20

16

15

11

10

6

5

0

SPECIAL
000000

rs

rt

rd

0
00000

SUBU
100011

6

5

5

5

5

6

Format
SUBU rd, rs, rt
Description
GPR[rd] ← GPR[rs] — GPR[rt]
Subtracts the low-order 32-bit value in GPR[rt] from the low-order 32-bit value in GPR[rs]. The 32-bit result
is sign-extended and stored in GPR[rd]. If overflow occurs, ignores it.
Restrictions
If the values of GPR[rs] and GPR[rt] are not sign-extended 32-bit values (bits 63..31 equal), then the result of
the operation is undefined.
Exceptions
None
Operation
if (NotWordValue (GPR[rs] 63..0) or NotWordValue (GPR[rt] 63..0)) then UndefinedResult () endif
temp ← GPR[rs] 63..0 — GPR[rt] 63..0
GPR[rd] 63..0 ← sign_extend (temp31..0)
Programming Notes
This instruction is not an unsigned operation in the strict sense, and performs 32-bit modulo arithmetic that
ignores overflow. It is appropriate for integer arithmetic that ignores overflow such as address or C language
arithmetic.

© SCEI
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SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

SW : Store Word
MIPS I
To store a word data in memory.
Operation Code
31

26

25

21

20

16

15

0

SW
101011

base

rt

offset

6

5

5

16

Format
SW rt, offset (base)
Description
memory [GPR[base] + offset] ← GPR[rt]
Stores the low-order 32-bit value of GPR[rt] in memory at the effective address obtained by adding the
offset as a 16-bit signed integer to the contents of GPR[base].
Restrictions
The effective address must conform to word alignment. If both of the least-significant bits of the address are
non-zero, an Address Error exception occurs.
Exceptions
TLB Refill, TLB Invalid, TLB Modified, Address Error
Operation (128-bit bus)
vAddr ← sign_extend (offset) + GPR[base]
if ( vAddr1..0) ≠ 02 then SignalException (AddressError) endif
(pAddr, uncached) ← AddressTranslation (vAddr, DATA, STORE)
pAddr ← pAddr(PSIZE-1)..0
byte ← vAddr3..0
dataquad ← GPR[rt](127-8*byte)..0 || 08*byte
StoreMemory (uncached, WORD, dataquad, pAddr, vAddr, DATA)

© SCEI
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SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

SWL : Store Word Left
MIPS I
To store the upper part of a word at an unaligned memory address.
Operation Code
31

26

25

21

20

16

15

0

SWL
101010

base

rt

offset

6

5

5

16

Format
SWL rt, offset (base)
Description
memory [GPR[base] + offset] ← GPR[rt]
Adds the offset as a 16-bit signed number to the value of GPR[base] to form the effective address. Stores the
high-order bytes of GPR[rt] in the lower part of the address in an aligned word including the address.
SWL $24,6($0)

$24

-

-

-

-

a

b

c

Address8

15

14

13

12

11

10

9

8

Address0

7

6

5

4

3

2

1

0

Address8

15

14

13

12

11

10

9

8

Address0

7

a

b

c

3

2

1

0

d

An Address Error exception due to alignment of the effective address does not occur.
SWL and SWR instructions in a pair are used to store the word data in a 4-byte block that does not conform
to word alignment.
Exceptions
TLB Refill, TLB Invalid, TLB Modified, Address Error
Operation
vAddr ← sign_extend (offset) + GPR[base]
(pAddr, uncached) ← AddressTranslation (vAddr, DATA, STORE)
pAddr ← pAddr(PSIZE-1)..2 || 02
byte ← vAddr1..0
if (vAddr3..2 = 002) then
dataquad ← 096 || 0(24-8*byte) || GPR[rt]31..(24-8*byte)
elseif (vAddr3..2 = 012) then
dataquad ← 064 || 0(24-8*byte) || GPR[rt]31..(24-8*byte) || 032
elseif (vAddr3..2 = 102) then
dataquad ← 032 || 0(24-8*byte) || GPR[rt]31..(24-8*byte) || 032
elseif (vAddr3..2 = 112) then
dataquad ← 0(24-8*byte) || GPR[rt]31..(24-8*byte) || 064
endif
StoreMemory (uncached, byte, dataquad, pAddr, vAddr, DATA)
The relation between the low-order 4 bits of the effective address vAddr and bytes that are to be stored is
illustrated below.
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SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

MSB 63
-

Register
Address

vAddr3..0

0 LSB
-

-

-

a

b

c

d

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Contents of registers after instruction
(Shaded is unchanged)
bit 63

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
a

14
14
14
14
14
14
14
14
14
14
14
14
14
14
a
b

Access
Type

pAddr3..0

0
1
2
3
0
1
2
3
0
1
2
3
0
1
2
3

0
0
0
0
4
4
4
4
8
8
8
8
12
12
12
12

bit 0

13
13
13
13
13
13
13
13
13
13
13
13
13
a
b
c

12
12
12
12
12
12
12
12
12
12
12
12
a
b
c
d

11
11
11
11
11
11
11
11
11
11
11
a
11
11
11
11

10
10
10
10
10
10
10
10
10
10
a
b
10
10
10
10

9
9
9
9
9
9
9
9
9
a
b
c
9
9
9
9

8
8
8
8
8
8
8
8
a
b
c
d
8
8
8
8

7
7
7
7
7
7
7
a
7
7
7
7
7
7
7
7

© SCEI
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6
6
6
6
6
6
a
b
6
6
6
6
6
6
6
6

5
5
5
5
5
a
b
c
5
5
5
5
5
5
5
5

4
4
4
4
a
b
c
d
4
4
4
4
4
4
4
4

3
3
3
a
3
3
3
3
3
3
3
3
3
3
3
3

2
2
a
b
2
2
2
2
2
2
2
2
2
2
2
2

1
a
b
c
1
1
1
1
1
1
1
1
1
1
1
1

a
b
c
d
0
0
0
0
0
0
0
0
0
0
0
0

SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

SWR : Store Word Right
MIPS I
To store the lower part of a word at an unaligned memory address.
Operation Code
31

26

25

21

20

16

15

0

SWR
101110

base

rt

offset

6

5

5

16

Format
SWR rt, offset (base)
Description
memory [GPR[base] + offset] ← GPR[rt]
Adds the offset as a 16-bit signed number to the value of GPR[base] to form the effective address. Stores the
low-order bytes of GPR[rt] in the upper part of the address in an aligned word including the address.
SWL $24,3($0)

$24

-

-

-

-

a

b

c

Address8

15

14

13

12

11

10

9

8

Address0

7

6

5

4

3

2

1

0

Address8

15

14

13

12

11

10

9

8

Address0

7

6

5

4

d

2

1

0

d

An Address Error exception due to alignment of the effective address does not occur.
SWR and SWL instructions in a pair are used to store the word in a 4-byte block that does not conform to
word alignment.
Exceptions
TLB Refill, TLB Invalid, TLB Modified, Address Error
Operation
vAddr ← sign_extend (offset) + GPR[base]
(pAddr, uncached) ← AddressTranslation (vAddr, DATA, STORE)
pAddr ← pAddr(PSIZE-1)..2 || 02
byte ← vAddr1..0
if (vAddr3..2 = 002) then
dataquad ← 096 || GPR[rt](31-8*byte)..0 || 08*byte
else if (vAddr3..2 = 012) then
dataquad ← 064 || GPR[rt](31-8*byte)..0 || 08*byte || 032
else if (vAddr3..2 = 102) then
dataquad ← 032 || GPR[rt](31-8*byte)..0 || 08*byte || 064
else if (vAddr3..2 = 112) then
dataquad ← GPR[rt](31-8*byte)..0 || 08*byte || 096
endif
StoreMemory (uncached, WORD-byte, dataquad, pAddr, vAddr, DATA)
The relation between the low-order 4 bits of the effective address vAddr and bytes that are to be stored is
illustrated below.
© SCEI
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SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

MSB 63
Register

-

Address

vAddr3..0

0 LSB
-

-

-

a

b

c

d

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Contents of registers after instruction
(Shaded is unchanged)
bit 63

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

15
15
15
15
15
15
15
15
15
15
15
15
a
b
c
d

14
14
14
14
14
14
14
14
14
14
14
14
b
c
d
14

Access
Type

pAddr3..0

3
2
1
0
3
2
1
0
3
2
1
0
3
2
1
0

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

bit 0

13
13
13
13
13
13
13
13
13
13
13
13
c
d
13
13

12
12
12
12
12
12
12
12
12
12
12
12
d
12
12
12

11
11
11
11
11
11
11
11
a
b
c
d
11
11
11
11

10 9
10 9
10 9
10 9
10 9
10 9
10 9
10 9
b c
c d
d 9
10 9
10 9
10 9
10 9
10 9

8
8
8
8
8
8
8
8
d
8
8
8
8
8
8
8

7
7
7
7
a
b
c
d
7
7
7
7
7
7
7
7

© SCEI
-120-

6
6
6
6
b
c
d
6
6
6
6
6
6
6
6
6

5
5
5
5
c
d
5
5
5
5
5
5
5
5
5
5

4
4
4
4
d
4
4
4
4
4
4
4
4
4
4
4

a
b
c
d
3
3
3
3
3
3
3
3
3
3
3
3

b
c
d
2
2
2
2
2
2
2
2
2
2
2
2
2

c
d
1
1
1
1
1
1
1
1
1
1
1
1
1
1

d
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

SYNC.stype : Synchronize Shared Memory
MIPS II
To wait until a memory access or a pipeline operation during the execution is completed.
Operation Code
31

26

25

11

10

6

5

0

SPECIAL
000000

0
000 0000 0000 0000

stype

SYNC
001111

6

15

5

6

Format
SYNC
SYNC.L
SYNC.P

(stype = 0xxxx)
(stype = 0xxxx)
(stype = 1xxxx)

Description
The SYNC instruction synchronizes memory accesses or pipeline operations.
The SYNC and SYNC.L instructions wait until the preceding loads or stores are completed. The completion
of loads indicates when the data is written into the destination register and the completion of stores indicates
when the data is written into the data cache or the scratch-pad RAM or when the data is sent on the
processor bus and the SYSDACK* signal is asserted. Also, they flush the uncached accelerated buffer and
writeback buffer. In this way, load and store instructions issued before SYNC or SYNC.L are guaranteed to
execute before load and store instructions following SYNC or SYNC.L are executed, in orderly sequence.
The SYNC.P instruction waits until the preceding instruction is completed with the exception of multiply,
divide, multicycle COP1 or COP2 operations or a pending load.
Restrictions
The SYNC instruction (SYNC.P or SYNC.L) is not allowed to execute in a branch delay slot, (the instruction
immediately following a branch instruction).
Exceptions
None
Operation
SyncOperation(stype)

© SCEI
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SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

SYSCALL : System Call
MIPS I
To cause a System Call exception.
Operation Code
31

26

25

6

5

0

SPECIAL
000000

code

SYSCALL
001100

6

20

6

Format
SYSCALL
Description
A system call exception occurs, immediately and unconditionally transferring control to the exception
handler. The code field is available and can be used for software parameters.
However, no special way for the exception handler to acquire the value of the code field is provided. It must
be retrieved by determining the address of an instruction word from the EPC register, etc.
Exceptions
System Call
Operation
SignalException (SystemCall)

© SCEI
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SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

TEQ : Trap if Equal
MIPS II
To compare the values of two GPRs and take a Trap exception according to the result.
Operation Code
31

26

25

21

20

16

15

6

5

0

SPECIAL
000000

rs

rt

code

TEQ
110100

6

5

5

10

6

Format
TEQ rs, rt
Description
if (GPR[rs] = GPR[rt]) then Trap
Compares the contents of GPR[rs] and GPR[rt]. If they are equal, takes a trap exception.
The code field is available and can be used for software parameters.
However, no special way for the exception handler to acquire the value of the code field is provided. It must
be retrieved by determining the address of an instruction word from the EPC register, etc.
Exceptions
Trap
Operation
if GPR[rs]63..0 = GPR[rt] 63..0 then
SignalException (Trap)
endif

© SCEI
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SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

TEQI : Trap if Equal Immediate
MIPS II
To compare a GPR with a constant and take a Trap exception according to the result.
Operation Code
31

26

25

21

20

16

15

0

REGIMM
000001

rs

TEQI
01100

immediate

6

5

5

16

Format
TEQI rs, immediate
Description
if (GPR[rs] = immediate) then Trap
Compares the contents of GPR[rs] with the value of a sign-extended immediate. If they are equal, takes a
Trap exception.
Exceptions
Trap
Operation
if GPR[rs] 63..0 = sign_extend (immediate) then
SignalException (Trap)
endif

© SCEI
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SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

TGE : Trap if Greater or Equal
MIPS II
To compare the values of two GPRs and take a Trap exception according to the result.
Operation Code
31

26

25

21

20

16

15

6

5

0

SPECIAL
000000

rs

rt

code

TGE
110000

6

5

5

10

6

Format
TGE rs, rt
Description
if (GPR[rs] >= GPR[rt]) then Trap
Compares the values of GPR[rs] and GPR[rt]. If GPR[rs] is greater than or equal to GPR[rt], takes a trap
exception.
The code field is available and can be used as software parameters.
However, no special way for the exception handler to acquire the value of the code is provided. The value of
the code field must be retrieved by determining the address of an instruction word from the EPC register,
etc.
Exceptions
Trap
Operation
if GPR[rs]63..0 >= GPR[rt]63..0 then
SignalException(Trap)
endif

© SCEI
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SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

TGEI : Trap if Greater or Equal Immediate
MIPS II
To compare a GPR with a constant and take a Trap exception according to the result.
Operation Code
31

26

25

21

20

16

15

0

REGIMM
000001

rs

TGEI
01000

immediate

6

5

5

16

Format
TGEI rs, immediate
Description
if (GPR[rs] >= immediate) then Trap
Compares the values of GPR[rs] with the value of the sign-extended immediate field. If GPR[rs] is greater
than or equal to immediate, takes a Trap exception.
Exceptions
Trap
Operation
if GPR[rs]63..0 >= sign_extend(immediate) then
SignalException(Trap)
endif

© SCEI
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SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

TGEIU : Trap if Greater or Equal Immediate Unsigned
MIPS II
To compare a GPR with a constant and take a Trap exception according to the result.
Operation Code
31

26

25

21

20

16

15

0

REGIMM
000001

rs

TGEIU
01001

immediate

6

5

5

16

Format
TGEIU rs, immediate
Description
if (GPR[rs] >= immediate) then Trap
Compares the value of GPR[rs] with the value of the sign-extended immediate field as unsigned integers. If
GPR[rs] is greater than or equal to immediate, takes a Trap exception.
Exceptions
Trap
Operation
if (0 || GPR[rs]63..0) >= (0 || sign_extend(immediate)) then
SignalException(Trap)
endif
Programming Notes
Because the immediate is treated as an unsigned integer after it is sign-extended, the range of numeric values
that the immediate represents is not sequential, but split into two areas; around the smallest and largest 64-bit
unsigned integers. That is [0,32767] and [max_unsigned-32767, max_unsigned], respectively.

© SCEI
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SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

TGEU : Trap if Greater or Equal Unsigned
MIPS II
To compare the values of two GPRs and take a Trap exception according to the result.
Operation Code
31

26

25

21

20

16

15

6

5

0

SPECIAL
000000

rs

rt

code

TGEU
110001

6

5

5

10

6

Format
TGEU rs, rt
Description
if (GPR[rs] >= GPR[rt]) then Trap
Compares the values of GPR[rs] and GPR[rt] as unsigned integers. If GPR[rs] is greater than or equal to
GPR[rt], takes a trap exception.
The code field is available and can be used for software parameters.
However, no special way for the exception handler to acquire the value of the code is provided. It must be
retrieved by determining the address of an instruction word from the EPC register, etc.
Exceptions
Trap
Operation
if (0 || GPR[rs]63..0)) >= (0 || GPR[rt]63..0) then
SignalException(Trap)
endif

© SCEI
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SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

TLT : Trap if Less Than
MIPS II
To compare the values of two GPRs and take a Trap exception according to the result.
Operation Code
31

26

25

21

20

16

15

6

5

0

SPECIAL
000000

rs

rt

code

TLT
110010

6

5

5

10

6

Format
TLT rs, rt
Description
if (GPR[rs] < GPR[rt]) then Trap
Compares the values of GPR[rs] and GPR[rt]. If GPR[rs] is less than GPR[rt], takes a trap exception.
The code field is available and can be used for software parameters.
However, no special way for the exception handler to acquire the value of the code is provided. It must be
retrieved by determining the address of an instruction word from the EPC register, etc.
Exceptions
Trap
Operation
if GPR[rs]63..0 < GPR[rt]63..0 then
SignalException(Trap)
endif

© SCEI
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SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

TLTI : Trap if Less Than Immediate
MIPS II
To compare a GPR with a constant and take a Trap exception according to the result.
Operation Code
31

26

25

21

20

16

15

0

REGIMM
000001

rs

TLTI
01010

immediate

6

5

5

16

Format
TLTI rs, immediate
Description
if (GPR[rs] < immediate) then Trap
Compares the value of GPR[rs] with the value of a sign-extended immediate. If GPR[rs] is less than
immediate, takes a Trap exception.
Exceptions
Trap
Operation
if GPR[rs]63..0 < sign_extend(immediate) then
SignalException(Trap)
endif

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EE Core Instruction Set Manual Version 6.0

TLTIU : Trap if Less Than Immediate Unsigned
MIPS II
To compare a GPR with a constant and take a Trap exception according to the result.
Operation Code
31

26

25

21

20

16

15

0

REGIMM
000001

rs

TLTIU
01011

immediate

6

5

5

16

Format
TLTIU rs, immediate
Description
if (GPR[rs] < immediate) then Trap
Compares the values of GPR[rs] with the value of a sign-extended immediate as unsigned integers. If
GPR[rs] is less than immediate, takes a Trap exception.
Exceptions
Trap
Operation
if (0 || GPR[rs]63..0) < (0 || sign_extend(immediate)) then
SignalException(Trap)
endif
Programming Notes
Because the immediate field is treated as an unsigned integer after it is sign-extended, the range of numeric
values that the immediate represents is not sequential, but split into two areas; around the smallest and
largest 64-bit unsigned integers. That is [0,32767] and [max_unsigned-32767, max_unsigned], respectively.

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EE Core Instruction Set Manual Version 6.0

TLTU : Trap if Less Than Unsigned
MIPS II
To compare the values of two GPRs and take a Trap exception according to the result.
Operation Code
31

26

25

21

20

16

15

6

5

0

SPECIAL
000000

rs

rt

code

TLTU
110011

6

5

5

10

6

Format
TLTU rs, rt
Description
if (GPR[rs] < GPR[rt]) then Trap
Compares the values of GPR[rs] and GPR[rt] as unsigned integers. If GPR[rs] is less than GPR[rt], takes a
trap exception.
The code field is available and can be used for software parameters.
However, no special way for the exception handler to acquire the value of the code is provided. It must be
retrieved by determining the address of an instruction word from the EPC register, etc.
Exceptions
Trap
Operation
if (0 || GPR[rs]63..0) < (0 || GPR[rt]63..0) then
SignalException(Trap)
endif

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EE Core Instruction Set Manual Version 6.0

TNE : Trap if Not Equal
MIPS II
To compare the values of two GPRs and take a Trap exception according to the result.
Operation Code
31

26

25

21

20

16

15

6

5

0

SPECIAL
000000

rs

rt

code

TNE
110110

6

5

5

10

6

Format
TNE rs, rt
Description
if (GPR[rs] ≠ GPR[rt]) then Trap
Compares the values of GPR[rs] and GPR[rt]. If they are not equal, takes a trap exception.
The code field is available and can be used for software parameters.
However, no special way for the exception handler to acquire the value of the code is provided. It must be
retrieved by determining the address of an instruction word from the EPC register, etc.
Exceptions
Trap
Operation
if GPR[rs]63..0 ≠ GPR[rt]63..0 then
SignalException(Trap)
endif

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EE Core Instruction Set Manual Version 6.0

TNEI : Trap if Not Equal Immediate
MIPS II
To compare a GPR with a constant and take a Trap exception according to the result.
Operation Code
31

26

25

21

20

16

15

0

REGIMM
000001

rs

TNEI
01110

immediate

6

5

5

16

Format
TNEI rs, immediate
Description
if (rs ≠ immediate) then Trap
Compares the value of GPR[rs] with the value of a sign-extended immediate. If they are not equal, takes a
Trap exception.
Exceptions
Trap
Operation
if GPR[rs]63..0 ≠ sign_extend(immediate) then
SignalException(Trap)
endif

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EE Core Instruction Set Manual Version 6.0

XOR : Exclusive OR
MIPS I
To calculate a bitwise logical EXCLUSIVE OR.
Operation Code
31

26

25

21

20

16

15

11

10

6

5

0

SPECIAL
000000

rs

rt

rd

0
00000

XOR
100110

6

5

5

5

5

6

Format
XOR rd, rs, rt
Description
GPR[rd] ← GPR[rs] XOR GPR[rt]
Calculates a bitwise logical XOR between the contents of GPR[rs] and GPR[rt]. The result is stored in
GPR[rd].
The truth table values for XOR are as follows:
X
0
0
1
1

Y
0
1
0
1

X XOR Y
0
1
1
0

Exceptions
None
Operation
GPR[rd]63..0 ← GPR[rs]63..0 XOR GPR[rt]63..0

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EE Core Instruction Set Manual Version 6.0

XORI : Exclusive OR Immediate
MIPS I
To calculate a bitwise logical EXCLUSIVE OR.
Operation Code
31

26

25

21

20

16

15

0

XORI
001110

rs

rt

immediate

6

5

5

16

Format
XORI rt, rs, immediate
Description
GPR[rt] ← GPR[rs] XOR immediate
Calculates a bitwise logical XOR between the value of the zero-extended immediate and contents of
GPR[rs]. The result is stored in GPR[rt].
X
0
0
1
1

Y
0
1
0
1

X XOR Y
0
1
1
0

Exceptions
None
Operation
GPR[rt]63..0 ← GPR[rs]63..0 XOR zero_extend (immediate)

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EE Core Instruction Set Manual Version 6.0

3. EE Core-Specific Instruction Set
This chapter describes the details of special CPU instructions that are part of the extended EE Core instruction
set. These instructions are classified into the following three types:
• Three-operand Multiply and Multiply-Add instructions
• Multiply and Multiply-Add instructions using logical pipeline 1 (I1 pipe)
• Multimedia instructions (128-bit instructions)

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EE Core Instruction Set Manual Version 6.0

DIV1 : Divide Word Pipeline 1
EE Core
To divide 32-bit signed integers. This operation is executed in logical pipeline 1.
Operation Code
31

26

25

21

20

16

15

6

5

0

MMI
011100

rs

rt

0
00 0000 0000

DIV1
011010

6

5

5

10

6

Format
DIV1 rs, rt
Description
(LO1, HI1) ← GPR[rs] / GPR[rt]
Divides the 32-bit value in GPR[rs] by the 32-bit value in GPR[rt]. The 32-bit quotient and the 32-bit
remainder are stored in the LO1(LO127...64) and HI1(HI127...64) registers respectively. Both GPR[rs] and
GPR[rt] are treated as signed values. The sign of the quotient and remainder are determined as shown in the
following table:
Dividend
GPR[rs]
Positive
Positive
Negative
Negative

Divisor GPR[rt]

Quotient LO

Remainder HI

Positive
Negative
Positive
Negative

Positive
Negative
Negative
Positive

Positive
Positive
Negative
Negative

Restrictions
If GPR[rt] and GPR[rs] are not sign-extended 32-bit values (bits 63..31 equal), then the result is undefined.
Also, if the value in GPR[rt] is zero, the arithmetic result is undefined.
Exceptions
None. If the divisor is zero, an exception does not occur on overflow.
Operation
if (NotWordValue(GPR[rs]) or NotWordValue(GPR[rt])) then UndefinedResult() endif
quotient
← GPR[rs]31..0 DIV GPR[rt]31..0
remainder
← GPR[rs]31..0 MOD GPR[rt]31..0
← (quotient 31)32 || quotient 31..0
LO127..64
← (remainder 31)32 || remainder 31..0
HI127..64
Programming Notes
In the EE Core, the integer divide operation proceeds asynchronously. An attempt to read the contents of
the LO or HI register before the divide operation finishes will result in interlock. Other CPU instructions
can execute without delay. Therefore, scheduling the divide operation appropriately can improve
performance.
When 0x80000000(–2147483648), the signed minimum value, is divided by 0xFFFFFFFF(–1), the operation
will result in an overflow. However, in this instruction an overflow exception does not occur and the
following results will be returned.
Quotient: 0x80000000 (–2147483648), and remainder: 0x00000000 (0)

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EE Core Instruction Set Manual Version 6.0

If an overflow or divide-by-zero is required to be detected, then add an instruction that detects these
conditions following the divide instruction. Since the divide instruction is asynchronous, the divide operation
and check can be executed in parallel. If an overflow or divide-by-zero is detected, then the system software
can be informed of the problem by generating an exception using an appropriate code value with a BREAK
instruction.

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EE Core Instruction Set Manual Version 6.0

DIVU1 : Divide Unsigned Word Pipeline 1
EE Core
To divide 32-bit unsigned integers. This operation is executed in logical pipeline 1.
Operation Code
31

26

25

21

20

16

15

6

5

0

MMI
011100

rs

rt

0
00 0000 0000

DIVU1
011011

6

5

5

10

6

Format
DIVU1 rs, rt
Description
(LO1, HI1) ← GPR[rs] / GPR[rt]
Divides the 32-bit value in GPR[rs] by the 32-bit value in GPR[rt]. The 32-bit quotient and the 32-bit
remainder are stored in the LO1(LO127...64) and HI1(HI127...64) registers respectively. Both GPR[rs] and
GPR[rt] are treated as unsigned values.
Restrictions
If GPR[rt] and GPR[rs] are not sign-extended 32-bit values (bits 63..31 equal), then the result is undefined.
Also, if the value in GPR[rt] is zero, the arithmetic result is undefined.
Exceptions
None. Even if the divisor is zero, an exception does not occur.
Operation
if (NotWordValue(GPR[rs]) or NotWordValue(GPR[rt])) then UndefinedResult() endif
quotient
← (0 || GPR[rs]31..0) DIV (0 || GPR[rt]31..0)
remainder
← (0 || GPR[rs]31..0) MOD (0 || GPR[rt]31..0)
← (quotient 31)32 || quotient 31..0
LO127..64
← (remainder 31)32 || remainder 31..0
HI127..64
Programming Notes
In the EE Core, the integer divide operation proceeds asynchronously. An attempt to read the contents of
the LO or HI register before the divide operation finishes will result in interlock. Other CPU instructions
can execute without delay. Therefore, scheduling the divide operation appropriately can improve
performance.
If divide-by-zero is required to be detected, then add an instruction that detects this condition following the
divide instruction. Since the divide instruction is asynchronous, the divide operation and check can be
executed in parallel. If an overflow or divide-by-zero is detected, then the system software can be informed
of the problem by generating an exception using an appropriate code value with a BREAK instruction.

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EE Core Instruction Set Manual Version 6.0

LQ : Load Quadword
128-bit MMI
To load a 128-bit data from memory.
Operation Code
31

26

25

21

20

16

15

0

LQ
011110

base

rt

offset

6

5

5

16

Format
LQ rt, offset (base)
Description
GPR[rt] ← memory [GPR[base] + offset]
Adds the offset as a 16-bit signed number to the value in GPR[base] to form the effective address. Loads the
128-bit data at the address and stores it in GPR[rt].
The least-significant four bits of the effective address are masked to zero when accessing memory.
Therefore, the effective address does not have to conform to the natural alignment.
Exceptions
TLB Refill, TLB Invalid, Address Error (excluding Address Error due to alignment)
Operation
vAddr
vAddr3..0 = 04
(pAddr, uncached)
memquad
GPR[rt]127..0

← sign_extend (offset) + GPR [base]
← AddressTranslation (vAddr, DATA, LOAD)
← LoadMemory (uncached, QUADWORD, pAddr, vAddr, DATA)
← memquad

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EE Core Instruction Set Manual Version 6.0

MADD : Multiply-Add word
EE Core
To multiply 32-bit values in GPRs and add to the HI and LO registers.
Operation Code
31

26

25

21

20

16

15

11

10

6

5

0

MMI
011100

rs

rt

rd

0
00000

MADD
000000

6

5

5

5

5

6

Format
MADD rs, rt
MADD rd, rs, rt
Description
(GPR[rd], HI, LO) ← (HI, LO) + GPR[rs] × GPR[rt]
Multiplies the 32-bit value in GPR[rs] by the 32-bit value in GPR[rt] as signed integers. Adds the resulting
64-bit product to the values of the HI and LO registers and stores the high-order 32-bit result in HI0 and the
low-order 32-bit result in LO0 and GPR[rd].
If rd is omitted in assembly language, zero is used for the default value. Since GPR[0] is the register whose
value is fixed to zero, the arithmetic result will be stored only in the HI and LO registers.
Restrictions
If GPR[rt] and GPR[rs] are not sign-extended 32-bit values (bits 63..31 equal), then the result is undefined.
Exceptions
None
Operation
if (NotWordValue(GPR[rs]) or NotWordValue(GPR[rt])) then UndefinedResult() endif
prod
LO63..0
HI63..0
GPR[rd]63..0

← (HI31..0 || LO31..0) + GPR[rs]31..0 × GPR[rt]31..0
← (prod 31)32 || prod31..0
← (prod 63)32 || prod63..32
← (prod 31)32  prod31..0

Programming Notes
In the EE Core, the multiply accumulate operation proceeds asynchronously. An attempt to read the
contents of the LO/HI/GPR[rd] registers before the operation finishes will result in interlock. Other CPU
instructions can execute in parallel with the multiply accumulate operation. Therefore, scheduling the
multiply accumulate operation appropriately can improve performance of the software.

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EE Core Instruction Set Manual Version 6.0

MADD1 : Multiply-Add word Pipeline 1
EE Core
To multiply the 32-bit values in GPRs and add to the HI and LO registers. This operation is executed in logical
pipeline 1.
Operation Code
31

26

25

21

20

16

15

11

10

6

5

0

MMI
011100

rs

rt

rd

0
00000

MADD1
100000

6

5

5

5

5

6

Format
MADD1 rs, rt
MADD1 rd, rs, rt
Description
(GPR[rd], HI1, LO1) ← (HI1, LO1) + GPR[rs] × GPR[rt]
Multiplies the 32-bit value in GPR[rs] by the 32-bit value in GPR[rt] as signed integers. Adds the resulting
64-bit product to the values of the HI1(HI127..64) and LO1(LO127..64) registers and stores the high-order 32-bit
result in the HI0 register and the low-order 32-bit result in the LO0 register and GPR[rd].
If rd is omitted in assembly language, zero is used for the default value. Since GPR[0] is the register whose
value is fixed to zero, the arithmetic result will be stored only in the HI1 and LO1 registers.
Restrictions
If GPR[rt] and GPR[rs] are not sign-extended 32-bit values (bits 63..31 equal), then the result is undefined.
Exceptions
None
Operation
if (NotWordValue(GPR[rs]) or NotWordValue(GPR[rt])) then UndefinedResult() endif
prod
LO127..64
HI127..64
GPR[rd]63..0

← (HI95..64 || LO95..64) + GPR[rs]31..0 × GPR[rt]31..0
← (prod 31)32 || prod31..0
← (prod 63)32 || prod63..32
← (prod 31)32 || prod31..0

Programming Notes
In the EE Core, the multiply accumulate operation proceeds asynchronously. An attempt to read the
contents of the LO/HI/GPR[rd] registers before the operation finishes will result in interlock. Other CPU
instructions can execute in parallel with the multiply accumulate operation. Therefore, scheduling the
multiply accumulate operation appropriately can improve performance of the software.

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EE Core Instruction Set Manual Version 6.0

MADDU : Multiply-Add Unsigned word
EE Core
To multiply the 32-bit values in GPRs as unsigned integers and add to the HI and LO registers.
Operation Code
31

26

25

21

20

16

15

11

10

6

5

0

MMI
011100

rs

rt

rd

0
00000

MADDU
000001

6

5

5

5

5

6

Format
MADDU rs, rt
MADDU rd, rs, rt
Description
(GPR[rd], HI, LO) ← (HI, LO) + GPR[rs] × GPR[rt]
Multiplies the 32-bit value in GPR[rs] by the 32-bit value in GPR[rt] as unsigned integers. Adds the resulting
64-bit product to the values of the HI and LO registers and stores the high-order 32-bit result in the HI0
register and the low-order 32-bit result in the LO0 register and GPR[rd].
If rd is omitted in assembly language, zero is used for the default value. Since GPR[0] is the register whose
value is fixed to zero, the arithmetic result will be stored only in the HI and LO registers.
Restrictions
If GPR[rt] and GPR[rs] are not sign-extended 32-bit values (bits 63..31 equal), then the result is undefined.
Exceptions
None
Operation
if (NotWordValue(GPR[rs]) or NotWordValue(GPR[rt])) then UndefinedResult() endif
prod
LO63..0
HI63..0
GPR[rd] 63..0

← (HI31..0 || LO31..0) + (0 || GPR[rs]31..0) × (0 || GPR[rt]31..0)
← (prod 31)32 || prod31..0
← (prod 63)32 || prod63..32
← (prod 31)32 || prod31..0

Programming Notes
In the EE Core, the multiply accumulate operation proceeds asynchronously. An attempt to read the
contents of the LO/HI/GPR[rd] registers before the operation finishes will result in interlock. Other CPU
instructions can execute in parallel with the multiply accumulate operation. Therefore, scheduling the
multiply accumulate operation appropriately can improve performance of the software.

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EE Core Instruction Set Manual Version 6.0

MADDU1 : Multiply-Add Unsigned word Pipeline 1
EE Core
To multiply the 32-bit values in GPRs as unsigned integers and add to the HI and LO registers. This operation is
executed in pipeline 1.
Operation Code
31

26

25

21

20

16

15

11

10

6

5

0

MMI
011100

rs

rt

rd

0
00000

MADDU1
100001

6

5

5

5

5

6

Format
MADDU1 rs, rt
MADDU1 rd, rs, rt
Description
(GPR[rd], HI1, LO1) ← (HI1, LO1) + GPR[rs] × GPR[rt]
Multiplies the 32-bit value in GPR[rs] by the 32-bit value in GPR[rt] as unsigned integers. Adds the resulting
64-bit product to the values of the HI1 (HI127..64) and LO1 (LO127..64) registers and stores the high-order 32bit result in the HI1 register and the low-order 32-bit result in the LO1 register and GPR[rd].
If rd is omitted in assembly language, zero is used for the default value. Since GPR[0] is the register whose
value is fixed to zero, the arithmetic result will be stored only in the HI1 and LO1 registers.
Restrictions
If GPR[rt] and GPR[rs] are not sign-extended 32-bit values (bits 63..31 equal), then the result is undefined.
Exceptions
None
Operation
if (NotWordValue(GPR[rs]) or NotWordValue(GPR[rt])) then UndefinedResult() endif
prod
LO127..64
HI127..64
GPR[rd]63..0

← (HI95..64 || LO95..64) + (0 || GPR[rs]31..0) × (0 || GPR[rt]31..0)
← (prod 31)32 || prod31..0
← (prod 63)32 || prod63..32
← (prod 31)32 || prod31..0

Programming Notes
In the EE Core, the multiply accumulate operation proceeds asynchronously. An attempt to read the
contents of the LO/HI/GPR[rd] registers before the operation finishes will result in interlock. Other CPU
instructions can execute in parallel with the multiply accumulate operation. Therefore, scheduling the
multiply accumulate operation appropriately can improve performance of the software.

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EE Core Instruction Set Manual Version 6.0

MFHI1 : Move From HI1 Register
EE Core
To move the contents of the HI1 register to a GPR.
Operation Code
31

26

25

16

15

11

10

6

5

0

MMI
011100

0
00 0000 0000

rd

0
00000

MFHI1
010000

6

10

5

5

6

Format
MFHI1 rd
Description
GPR[rd] ← HI1
Copies the contents of the HI1 (=HI127...64) register in GPR[rd].
Exceptions
None
Operation
GPR[rd]63..0 ← HI127..64

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EE Core Instruction Set Manual Version 6.0

MFLO1 : Move From LO1 Register
EE Core
To move the contents of the LO1 register to a GPR.
Operation Code
31

26

25

16

15

11

10

6

5

0

MMI
011100

0
00 0000 0000

rd

0
00000

MFLO1
010010

6

10

5

5

6

Format
MFLO1 rd
Description
GPR[rd] ← LO1
Copies the contents of the LO1 (=LO127...64) register in GPR[rd].
Exceptions
None
Operation
GPR[rd]63..0 ← LO127..64

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EE Core Instruction Set Manual Version 6.0

MFSA : Move from Shift Amount Register
EE Core
To save the contents of the SA register in a GPR.
Operation Code
31

26

25

16

15

11

10

6

5

0

SPECIAL
000000

0
00 0000 0000

rd

0
00000

MFSA
101000

6

10

5

5

6

Format
MFSA rd
Description
GPR[rd] ← SA
Copies the contents of the SA register, which holds the funnel shift amount, in GPR[rd]. This instruction is
provided for saving the SA register during a context switch. Since the value of the SA register is encoded in a
special manner, the software cannot use the resulting value in GPR[rd]. Uses the MTSA instruction to
restore the saved values in SA.
Exceptions
None
Operation
GPR[rd]63..0 ← SA
Programming Notes
This instruction operates only in pipeline 0.

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EE Core Instruction Set Manual Version 6.0

MTHI1 : Move To HI1 Register
EE Core
To move the value of a GPR to the HI1 register.
Operation Code
31

26

25

21

20

6

5

0

MMI
011100

rs

0
000 0000 0000 0000

MTHI1
010001

6

5

15

6

Format
MTHI1 rs
Description
HI1 ← GPR[rs]
Copies the contents of GPR[rs] to the HI1 (=HI127...64) register.
Exceptions
None
Operation
HI127..64 ← GPR[rs]63..0

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EE Core Instruction Set Manual Version 6.0

MTLO1 : Move To LO1 Register
EE Core
To move the value of a GPR to the LO1 register.
Operation Code
31

26

25

21

20

6

5

0

MMI
011100

rs

0
000 0000 0000 0000

MTLO1
010001

6

5

15

6

Format
MTLO1 rs
Description
LO1 ← GPR[rs]
Copies the contents of GPR[rs] to the LO1 (=LO127...64) register.
Exceptions
None
Operation
LO127..64 ← GPR[rs]63..0

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EE Core Instruction Set Manual Version 6.0

MTSA : Move to Shift Amount Register
EE Core
To restore the saved values in a GPR into the SA register.
Operation Code
31

26

25

21

20

6

5

0

SPECIAL
000000

rs

0
000 0000 0000 0000

MTSA
101001

6

5

15

6

Format
MTSA rs
Description
SA ← GPR[rs]
Copies the contents of GPR[rs] into the SA register, which holds the funnel shift amount.
This instruction is provided for restoring the values of SA saved with the MFSA instruction during a context
switch.
The contents of GPR[rs] must be the value saved with the MFSA instruction. Otherwise, the result of the
QFSRV instruction is undefined. That is, setting the funnel shift amount newly with the MTSA instruction is
not allowed. Use the MTSAB and MTSAH instructions to do this.
Restrictions
The three instructions prior to the MTSA instruction must not access SA register. That is, placing a MFSA,
MTSAB, MTSAH or QFSRV instruction in the three steps preceding the MTSA instruction is not allowed.
Exceptions
None
Operation
SA ← GPR[rs]63..0
Programming Notes
The MTSA instruction operates only in logical pipeline 0.

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EE Core Instruction Set Manual Version 6.0

MTSAB : Move Byte Count to Shift Amount Register
EE Core
To set a byte shift count in the SA register.
Operation Code
31

26

25

21

20

16

15

0

REGIMM
000001

rs

11000

immediate

6

5

5

16

Format
MTSAB rs, immediate
Description
SA ← (GPR[rs] XOR immediate) × 8
Calculates a bitwise logical XOR between the least-significant four bits of GPR[rs] and those of the
immediate value. The result is stored in SA as a byte shift amount.
Restrictions
The three instructions prior to the MTSAB instruction must not read the SA register; that is, they must not
be the MFSA or QFSRV instruction.
Exceptions
None
Operation
SA ← (GPR[rs]3..0 XOR immediate3..0) × 8
Programming Notes
The MTSAB instruction operates only in logical pipeline 0.
Specifying rs or immediate differs as follows:
mtsab
0, 5 // Sets shifts amount to "5 bytes" .
mtsab
5, 0 // Sets the contents of GPR[5] as a byte shift amount.

© SCEI
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SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

MTSAH : Move Halfword Count to Shift Amount Register
EE Core
To set a halfword shift count in the SA register.
Operation Code
31

26

25

21

20

16

15

0

REGIMM
000001

rs

11001

immediate

6

5

5

16

Format
MTSAH rs, immediate
Description
SA ← (GPR[rs] XOR immediate) × 16
Calculates a bitwise logical XOR between the least-significant three bits of GPR[rs] and those of the
immediate value. The result is stored into SA as a halfword shift amount.
Restrictions
The three instructions prior to the MTSAB instruction must not read the SA register; that is, they must not
be the MFSA or QFSRV instruction.
Exceptions
None
Operation
SA ← (GPR[rs]2..0 XOR immediate2..0) × 16
Programming Notes
The MTSAH instruction operates only in logical pipeline 0.
Specifying rs or immediate differs as follows:
mtsah
0, 5 // Sets shifts amount to "5 halfwords"
mtsah
5, 0 // Sets the contents of GPR[5] as a byte shift amount.

© SCEI
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SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

MULT : Multiply Word
EE Core
To multiply 32-bit signed integers.
Operation Code
31

26

25

21

20

16

15

11

10

6

5

0

SPECIAL
000000

rs

rt

rd

0
00000

MULT
011000

6

5

5

5

5

6

Format
MULT rd, rs, rt
MULT rs, rt
Description
(GPR[rd], LO, HI) ← GPR[rs] × GPR[rt]
Multiplies the 32-bit value in GPR[rt] by the 32-bit value in GPR[rs] as signed integers. The low-order 32 bits
and the high-order 32 bits of the 64-bit result are stored in the LO register and GPR[rd], and the HI register,
respectively.
Restrictions
If GPR[rt] and GPR[rs] are not sign-extended 32-bit values (bits 63..31 equal), then the result is undefined.
Exceptions
None. No arithmetic exception occurs.
Operation
if (NotWordValue(GPR[rs]) or NotWordValue(GPR[rt])) then UndefinedResult() endif
prod
LO63..0
HI63..0
GPR[rd] 63..0

← GPR[rs]31..0 × GPR[rt]31..0
← (prod 31)32 || prod31..0
← (prod 63)32 || prod63..32
← (prod 31)32 || prod31..0

Programming Notes
In the EE Core, the integer multiply operation proceeds asynchronously. An attempt to read the contents of
the LO/HI/GPR[rd] registers before the multiply operation finishes will result in interlock. Other CPU
instructions can execute in parallel. Therefore, scheduling the multiply operation appropriately can improve
performance.
Even when the result of the multiply operation overflows, an overflow exception does not occur. If an
overflow is required to be detected, an explicit check is necessary.
If rd is omitted in assembly language, zero is used for the default value. Since GPR[0] is the register whose
value is fixed to zero, the arithmetic result will be stored only in the HI and LO registers. That is, the result is
the same as the MULT instruction in the MIPS I level.

© SCEI
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SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

MULT1 : Multiply Word Pipeline 1
EE Core
To multiply 32-bit signed integers. This operation is executed in logical pipeline 1.
Operation Code
31

26

25

21

20

16

15

11

10

6

5

0

MMI
011100

rs

rt

rd

0
00000

MULT1
011000

6

5

5

5

5

6

Format
MULT1 rd, rs, rt
MULT1 rs, rt
Description
(GPR[rd], LO1, HI1) ← GPR[rs] × GPR[rt]
Multiplies the 32-bit value in GPR[rt] by the 32-bit value in GPR[rs] as signed integer values. The low-order
32 bits and the high-order 32 bits of the resulting 64-bit value are stored in the LO1(LO127..64) register and
GPR[rd], and the HI1(HI127..64) register respectively.
Restrictions
If GPR[rt] and GPR[rs] are not sign-extended 32-bit values (bits 63..31 equal), then the result is undefined.
Exceptions
None. No arithmetic exception occurs.
Operation
if (NotWordValue(GPR[rs]) or NotWordValue(GPR[rt])) then UndefinedResult() endif
prod
LO127..64
HI127..64
GPR[rd]63..0

← GPR[rs]31..0 × GPR[rt]31..0
← (prod 31)32 || prod 31..0
← (prod 63)32 || prod 63..32
← (prod 31)32 || prod31..0

Programming Notes
In the EE Core, the integer multiply operation proceeds asynchronously. An attempt to read the contents of
the LO/HI/GPR[rd] registers before the multiply operation finishes will result in interlock. Other CPU
instructions can execute in parallel. Therefore, scheduling the multiply operation appropriately can improve
performance.
Even when the result of the multiply operation overflows, an overflow exception does not occur. If
Overflow is required to be detected, an explicit check is necessary.

© SCEI
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SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

MULTU : Multiply Unsigned Word
EE Core
To multiply 32-bit signed integers.
Operation Code
31

26

25

21

20

16

15

11

10

6

5

0

SPECIAL
000000

rs

rt

rd

0
00000

MULTU
011001

6

5

5

5

5

6

Format
MULTU rd, rs, rt
MULTU rs, rt
Description
(LO, HI) ← GPR[rs] × GPR[rt]
Multiplies the 32-bit value in GPR[rt] by the 32-bit value in GPR[rs] as unsigned integer values. The loworder 32 bits and the high-order 32 bits of the resulting 64-bit value are stored in the LO and HI registers
respectively.
No arithmetic exception occurs under any circumstances.
Restrictions
If GPR[rt] and GPR[rs] are not sign-extended 32-bit values (bits 63..31 equal), then the result is undefined.
Exceptions
None
Operation
if (NotWordValue(GPR[rs]) or NotWordValue(GPR[rt])) then UndefinedResult() endif
prod
LO63..0
HI 63..0
GPR[rd] 63..0

← (0 || GPR[rs]31..0) × (0 || GPR[rt]31..0)
← (prod 31)32 || prod31..0
← (prod 63)32 || prod63..32
← (prod 31)32 || prod31..0

Programming Notes
See "Programming Notes" for the MULT instruction.

© SCEI
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SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

MULTU1 : Multiply Unsigned Word Pipeline 1
EE Core
To multiply 32-bit unsigned integers. This operation is executed in logical pipeline 1.
Operation Code
31

26

25

21

20

16

15

11

10

6

5

0

MMI
011100

rs

rt

rd

0
00000

MULTU1
011001

6

5

5

5

5

6

Format
MULTU1 rd, rs, rt
MULTU1 rs, rt
Description
(GPR[rd], LO1, HI1) ← GPR[rs] × GPR[rt]
Multiplies the 32-bit value in GPR[rt] by the 32-bit value in GPR[rs] as unsigned integers. The low-order 32
bits and the high-order 32 bits of the resulting 64-bit value are stored in the LO1(LO127..64) register and
GPR[rd], and the HI1(HI127..64) register, respectively.
Restrictions
If GPR[rt] and GPR[rs] are not sign-extended 32-bit values (bits 63..31 equal), then the result is undefined.
Exceptions
None
Operation
if (NotWordValue(GPR[rs]) or NotWordValue(GPR[rt])) then UndefinedResult() endif
prod
LO127..64
HI127..64
GPR[rd]63..0

← ( 0 || GPR[rs]31..0) × (0 || GPR[rt]31..0)
← (prod 31)32 || prod 31..0
← (prod 63)32 || prod 63..32
← (prod 31)32 || prod 31..0

Programming Notes
See "Programming Notes" for the MULT1 instruction.

© SCEI
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SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

PABSH : Parallel Absolute Halfword
128-bit MMI
To calculate the absolute value of eight 16-bit integers in parallel.
Operation Code
31

26

25

21

20

16

15

11

10

6

5

0

MMI
011100

0
00000

rt

rd

PABSH
00101

MMI1
101000

6

5

5

5

5

6

Format
PABSH rd, rt
Description
GPR[rd] ← |GPR[rt]|
Splits the 128-bit value in GPR[rt] into eight 16-bit signed integers, calculates their absolute values and stores
them in the corresponding halfwords in GPR[rd].
If a value is 0x8000(–32768), the operation will result in an overflow. However, the result is truncated to
0x7FFF(+32767) and an overflow exception does not occur.
Exceptions
None
Operation
GPR[rd]15..0
GPR[rd]31..16
GPR[rd]47..32
GPR[rd]63..48
GPR[rd]79..64
GPR[rd]95..80
GPR[rd]111..96
GPR[rd]127..112
127

rt

← |GPR[rt]15..0|
← |GPR[rt]31..16|
← |GPR[rt]47..32|
← |GPR[rt]63..48|
← |GPR[rt]79..64|
← |GPR[rt]95..80|
← |GPR[rt]111..96|
← |GPR[rt]127..112|

112 111

A7

127

rd

96 95

A6

112 111

 A7 

80 79

A5

96 95

 A6 

64 63

A4

80 79

 A5 

48 47

A3

64 63

 A4 

© SCEI
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32 31

A2

48 47

 A3 

 A2 

16 15

A1

32 31

0

A0

16 15

 A1 

 A0 

0

SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

PABSW : Parallel Absolute Word
EE Core
To calculate the absolute value of four 32-bit integers in parallel.
Operation Code
31

26

25

21

20

16

15

11

10

6

5

0

MMI
011100

0
00000

rt

rd

PABSW
00001

MMI1
101000

6

5

5

5

5

6

Format
PABSW rd, rt
Description
GPR[rd] ← |GPR[rt]|
Splits the 128-bit value in GPR[rt] into four 32-bit signed integers, calculates their absolute values and stores
them in the corresponding words in GPR[rd].
If a value is 0x80000000 (–2147483648), the operation will result in an overflow. However, the result is
truncated to 0x7FFFFFFF (+2147483647) and an overflow exception does not occur.
Exceptions
None
Operation
GPR[rd]31..0
GPR[rd]63..32
GPR[rd]95..64
GPR[rd]127..96
127

rt

96 95

A3

127

rd

←  GPR[rt]31..0 
←  GPR[rt]63..32 
←  GPR[rt]95..64 
←  GPR[rt]127..96 
64 63

A2

96 95

 A3 

32 31

A1

64 63

 A2 

0

A0

32 31

 A1 

0

 A0 

© SCEI
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SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

PADDB : Parallel Add Byte
128-bit MMI
To add 16 pairs of 8-bit integers in parallel.
Operation Code
31

26

25

21

20

16

15

11

10

6

5

0

MMI
011100

rs

rt

rd

PADDB
01000

MMI0
001000

6

5

5

5

5

6

Format
PADDB rd, rs, rt
Description
GPR[rd] ← GPR[rs] + GPR[rt]
Splits the 128-bit values in GPR[rs] and GPR[rt] into sixteen 8-bit integers, adds the data in GPR[rs] to the
corresponding data in GPR[rt] and stores them in the corresponding bytes in GPR[rd].
Exceptions
None. Even when the result of the arithmetic operation overflows or underflows, an overflow exception
does not occur.
Operation
GPR[rd]7..0
GPR[rd]15..8

← (GPR[rs]7..0 + GPR[rt]7..0)7..0
← (GPR[rs]15..8 + GPR[rt]15..8)7..0

(The same operations follow every 8 bits)
← (GPR[rs]127..120 + GPR[rt]127..120)7..0

GPR[rd]127..120

127 120119 112 111 104 103 96 95 88 87 80 79 72 71 64 63 56 55 48 47 40 39 32 31 24 23 16 15

rs A15 A14 A13

+

+

+

A12 A11 A10

+

+

+

B12 B11 B10

A8

A7

A6

A5

A4

A3

A2

A1

A0

+

+

+

+

+

+

+

+

+

+

B9

B8

B7

B6

B5

B4

B3

B2

127 120119 112 111 104 103 96 95 88 87 80 79 72 71 64 63 56 55 4847 40 39 32 31 24 23

rd

A15
+
B15

A14
+
B14

A13
+
B13

A12
+
B12

A11
+
B11

A10
+
B10

0

A9

127 120119 112 111 104 103 96 95 88 87 80 79 72 71 64 63 56 55 48 47 40 39 32 31 24 23 16 15

rt B15 B14 B13

87

A9
+
B9

A8
+
B8

© SCEI
-160-

A7
+
B7

A6
+
B6

A5
+
B5

A4
+
B4

A3
+
B3

A2
+
B2

87

B1

16 15

B0

87
A1
+
B1

0

0
A0
+
B0

SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

PADDH : Parallel Add Halfword
128-bit MMI
To add 8 pairs of 16-bit integers in parallel.
Operation Code
31

26

25

21

20

16

15

11

10

6

5

0

MMI
011100

rs

rt

rd

PADDH
00100

MMI0
001000

6

5

5

5

5

6

Format
PADDH rd, rs, rt
Description
GPR[rd] ← GPR[rs] + GPR[rt]
Splits the 128-bit values in GPR[rs] and GPR[rt] into eight 16-bit integers, adds the data in GPR[rs] to the
corresponding data in GPR[rt] and stores them in the corresponding halfwords in GPR[rd].
Exceptions
None
Operation
GPR[rd]15..0
GPR[rd]31..16
GPR[rd]47..32
GPR[rd]63..48
GPR[rd]79..64
GPR[rd]95..80
GPR[rd]111..96
GPR[rd]127..112
127

rs

← (GPR[rs]15..0 + GPR[rt]15..0)15..0
← (GPR[rs]31..16 + GPR[rt]31..16)15..0
← (GPR[rs]47..32 + GPR[rt]47..32)15..0
← (GPR[rs]63..48 + GPR[rt]63..48)15..0
← (GPR[rs]79..64 + GPR[rt]79..64)15..0
← (GPR[rs]95..80 + GPR[rt]95..80)15..0
← (GPR[rs]111..96 + GPR[rt]111..96)15..0
← (GPR[rs]127..112 + GPR[rt]127..112)15..0

112 111

A7

A6

+
127

rt

rd

A7+B7

A6+B6

A5+B5

32 31

A2

+
64 63

B4

80 79

48 47

A3

+
80 79

B5

96 95

64 63

A4

+
96 95

B6

112 111

80 79

A5

+
112 111

B7

127

96 95

B3

64 63

A4+B4

A1

+
48 47

A3+B3

+
16 15

B1

32 31

A2+B2

0

A0

+
32 31

B2

48 47

16 15

0

B0

16 15

A1+B1

0

A0+B0

© SCEI
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SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

PADDSB : Parallel Add with Signed Saturation Byte
128-bit MMI
To add 16 pairs of 8-bit signed integers with saturation in parallel.
Operation Code
31

26

25

21

20

16

15

11

10

6

5

0

MMI
011100

rs

rt

rd

PADDSB
11000

MMI0
001000

6

5

5

5

5

6

Format
PADDSB rd, rs, rt
Description
GPR[rd] ← GPR[rs] + GPR[rt]
Splits the 128-bit values in GPR[rs] and GPR[rt] into sixteen 8-bit signed integers, adds the data in GPR[rs]
to the corresponding data in GPR[rt] and stores them in the corresponding bytes in GPR[rd].
Arithmetic results beyond the range of a signed 8-bit integer are saturated as follows:
Overflow
: → 0x7F
Underflow : → 0x80
Exceptions
None
Operation
if ((GPR[rs]7..0 + GPR[rt]7..0) > 0x7F) then
← 0x7F
GPR[rd]7..0
else if (0x100 <= (GPR[rs]7..0 + GPR[rt]7..0) < 0x180) then
← 0x80
GPR[rd]7..0
else
← (GPR[rs]7..0 + GPR[rt]7..0)7..0
GPR[rd]7..0
endif
if ((GPR[rs]15..8 + GPR[rt]15..8) > 0x7F) then
← 0x7F
GPR[rd]15..8
else if (0x100 <= (GPR[rs]15..8 + GPR[rt]15..8) < 0x180) then
← 0x80
GPR[rd]15..8
else
← (GPR[rs]15..8 + GPR[rt]15..8)7..0
GPR[rd]15..8
endif
(The same operations follow every 8 bits)
if ((GPR[rs]127..120 + GPR[rt]127..120) > 0x7F) then
← 0x7F
GPR[rd]127..120
else if (0x100 <= (GPR[rs]127..120 + GPR[rt]127..120) < 0x180) then
← 0x80
GPR[rd]127..120
else
← (GPR[rs]127..120 + GPR[rt]127..120)7..0
GPR[rd]127..120
endif

© SCEI
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SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

127 120119 112111 104103 96 95 88 87 80 79 72 71 64 63 56 55 48 47 40 39 32 31 24 23 16 15 8 7
0
rs A15 A14 A13 A12 A11 A10 A9 A8
A7 A6
A5 A4
A3 A2 A1 A0
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
127 120119 112111 104103 96 95 88 87 80 79 72 71 64 63 56 55 48 47 40 39 32 31 24 23 16 15 8 7 0
rt B15 B14 B13

B12

B11 B10

B9

B8

B7

B6

B5

B4

B3

B2

B1

B0

Saturation

127 120119 112111 104103 96 95 88 87 80 79 72 71 64 63 56 55 48 47 40 39 32 31 24 23 16 15 8 7 0
15 A14 A13 A12
A11 A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
rd A+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
B15 B14 B13 B12
B11 B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0

© SCEI
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SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

PADDSH : Parallel Add with Signed Saturation Halfword
128-bit MMI
To add 8 pairs of 16-bit signed integers with saturation in parallel.
Operation Code
31

26

25

21

20

16

15

11

10

6

5

0

MMI
011100

rs

rt

rd

PADDSH
10100

MMI0
001000

6

5

5

5

5

6

Format
PADDSH rd, rs, rt
Description
GPR[rd] ← GPR[rs] + GPR[rt]
Splits the 128-bit values in GPR[rs] and GPR[rt] into eight 16-bit signed integers, adds the data in GPR[rs] to
the corresponding data in GPR[rt] and stores them in the corresponding halfwords in GPR[rd].
Arithmetic results beyond the range of a signed 16-bit integer are saturated as follows:
Overflow
: → 0x7FFF
Underflow : → 0x8000
Exceptions
None
Operation
if ((GPR[rs]15..0 + GPR[rt]15..0) > 0x7FFF) then
← 0x7FFF
GPR[rd]15..0
else if (0x10000 <= (GPR[rs]15..0 + GPR[rt]15..0) < 0x18000) then
← 0x8000
GPR[rd]15..0
else
← (GPR[rs]15..0 + GPR[rt]15..0)15..0
GPR[rd]15..0
endif
if ((GPR[rs]31..16 + GPR[rt]31..16) > 0x7FFF) then
← 0x7FFF
GPR[rd]31..16
else if (0x10000 <= (GPR[rs]31..16 + GPR[rt]31..16) < 0x18000) then
← 0x8000
GPR[rd]31..16
else
← (GPR[rs]31..16 + GPR[rt]31..16)15..0
GPR[rd]31..16
endif
(The same operations follow every 16 bits)
if ((GPR[rs]127..112 + GPR[rt]127..112) > 0x7FFF) then
← 0x7FFF
GPR[rd]127..112
else if (0x10000 <= (GPR[rs]127..112 + GPR[rt]127..112) < 0x18000) then
← 0x8000
GPR[rd]127..112
else
← (GPR[rs]127..112 + GPR[rt]127..112)15..0
GPR[rd]127..112
endif

© SCEI
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SCE CONFIDENTIAL

127

rs

EE Core Instruction Set Manual Version 6.0

112 111

A7

A6

+
127

rt

96 95

A5

+
112 111

B7

80 79

A4

+
96 95

B6

64 63

A3

+
80 79

B5

48 47

A2

+
64 63

B4

32 31

A1

+
48 47

B3

16 15

A0

+
32 31

B2

0

+
16 15

B1

0

B0

Saturation
127

rd

112 111

A7+B7

96 95

A6+B6

80 79

A5+B5

64 63

A4+B4

48 47

A3+B3

32 31

A2+B2

16 15

A1+B1

0

A0+B0

© SCEI
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SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

PADDSW : Parallel Add with Signed Saturation Word
128-bit MMI
To add 4 pairs of 32-bit signed integers with saturation in parallel.
Operation Code
31

26

25

21

20

16

15

11

10

6

5

0

MMI
011100

rs

rt

rd

PADDSW
10000

MMI0
001000

6

5

5

5

5

6

Format
PADDSW rd, rs, rt
Description
GPR[rd] ← GPR[rs] + GPR[rt]
Splits the 128-bit values in GPR[rs] and GPR[rt] into four 32-bit signed integers, adds the data in GPR[rs] to
the corresponding data in GPR[rt] and stores them in the corresponding words in GPR[rd].
Arithmetic results beyond the range of a signed 32-bit integer are saturated as follows:
Overflow
: → 0x7FFFFFFF
Underflow : → 0x80000000
Exceptions
None
Operation
if ((GPR[rs]31..0 + GPR[rt]31..0) > 0x7FFFFFFF) then
← 0x7FFFFFFF
GPR[rd]31..0
else if (0x100000000 <= (GPR[rs]31..0 + GPR[rt]31..0) < 0x80000000) then
← 0x80000000
GPR[rd]31..0
else
← (GPR[rs]31..0 + GPR[rt]31..0)31..0
GPR[rd]31..0
endif
if ((GPR[rs]63..32 + GPR[rt]63..32) > 0x7FFFFFFF) then
← 0x7FFFFFFF
GPR[rd]63..32
else if (0x100000000 <= (GPR[rs]63..32 + GPR[rt]63..32) < 0x80000000) then
← 0x80000000
GPR[rd]63..32
else
← (GPR[rs]63..32 + GPR[rt]63..32)31..0
GPR[rd]63..32
endif
if ((GPR[rs]95..64 + GPR[rt]95..64) > 0x7FFFFFFF) then
← 0x7FFFFFFF
GPR[rd]95..64
else if (0x100000000 <= (GPR[rs]95..64 + GPR[rt]95..64) < 0x80000000) then
← 0x80000000
GPR[rd]95..64
else
← (GPR[rs]95..64 + GPR[rt]95..64)31..0
GPR[rd]95..64
endif
if ((GPR[rs]127..96 + GPR[rt]127..96) > 0x7FFFFFFF) then
← 0x7FFFFFFF
GPR[rd]127..96
else if (0x100000000 <= (GPR[rs]127..96 + GPR[rt]127..96) < 0x80000000) then
← 0x80000000
GPR[rd]127..96
© SCEI
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SCE CONFIDENTIAL

else
GPR[rd]127..96
endif
127

rs

EE Core Instruction Set Manual Version 6.0

← (GPR[rs]127..96 + GPR[rt]127..96)31..0
96 95

A3
127

rt

+

64 63

A2
96 95

B3

+

32 31

A1
64 63

B2

+

0

A0
32 31

B1

+

0

B0

Saturation
127

rd

96 95

A3+B3

64 63

A2+B2

32 31

A1+B1

0

A0+B0

© SCEI
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SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

PADDUB : Parallel Add with Unsigned Saturation Byte
128-bit MMI
To add 16 pairs of 8-bit unsigned integers with saturation in parallel.
Operation Code
31

26

25

21

20

16

15

11

10

6

5

0

MMI
011100

rs

rt

rd

PADDUB
11000

MMI1
101000

6

5

5

5

5

6

Format
PADDUB rd, rs, rt
Description
GPR[rd] ← GPR[rs] + GPR[rt]
Splits the 128-bit values in GPR[rs] and GPR[rt] into sixteen 8-bit unsigned integers, adds the data in
GPR[rs] to the corresponding data in GPR[rt] and stores them in the corresponding bytes in GPR[rd].
Arithmetic results beyond the range of an unsigned 8-bit integer are saturated as follows:
Overflow
: → 0xFF
Exceptions
None
Operation
if ((GPR[rs]7..0 + GPR[rt]7..0) > 0xFF) then
← 0xFF
GPR[rd]7..0
else
← (GPR[rs]7..0 + GPR[rt]7..0)7..0
GPR[rd]7..0
endif
if ((GPR[rs]15..8 + GPR[rt]15..8) > 0xFF) then
← 0xFF
GPR[rd]15..8
else
GPR[rd]15..8
← (GPR[rs]15..8 + GPR[rt]15..8)7..0
endif
(The same operations follow every 8 bits)
if ((GPR[rs]127..120 + GPR[rt]127..120) > 0xFF) then
← 0xFF
GPR[rd]127..120
else
← (GPR[rs]127..120 + GPR[rt]127..120)7..0
GPR[rd]127..120
endif

© SCEI
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SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

0
127 120119 112 111 104 103 96 95 88 87 80 79 72 71 64 63 56 55 48 47 40 39 32 31 24 23 16 15 8 7
rs A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2
A1 A0
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
0
127 120119 112 111 104 103 96 95 88 87 80 79 72 71 64 63 56 55 48 47 40 39 32 31 24 23 16 15 8 7
rt B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4
B3 B2 B1 B0
Saturation

0
127 120119 112 111 104 103 96 95 88 87 80 79 72 71 64 63 56 55 48 47 40 39 32 31 24 23 16 15 8 7
A0
15 A14 A13 A12 A11 A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
rd A+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
B15 B14 B13 B12 B11 B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0

© SCEI
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SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

PADDUH : Parallel Add with Unsigned Saturation Halfword
128-bit MMI
To add 8 pairs of 16-bit unsigned integers with saturation in parallel.
Operation Code
31

26

25

21

20

16

15

11

10

6

5

0

MMI
011100

rs

rt

rd

PADDUH
10100

MMI1
101000

6

5

5

5

5

6

Format
PADDUH rd, rs, rt
Description
GPR[rd] ← GPR[rs] + GPR[rt]
Splits the 128-bit values in GPR[rs] and GPR[rt] into eight 16-bit unsigned integers, adds the data in GPR[rs]
to the corresponding data in GPR[rt] and stores them in the corresponding bytes in GPR[rd].
Arithmetic results beyond the range of an unsigned 16-bit integer are saturated as follows;
Overflow
: → 0xFFFF
Exceptions
None
Operation
if ((GPR[rs]15..0 + GPR[rt]15..0) > 0xFFFF) then
← 0xFFFF
GPR[rd]15..0
else
← (GPR[rs]15..0 + GPR[rt]15..0)15..0
GPR[rd]15..0
endif
if ((GPR[rs]31..16 + GPR[rt]31..16) > 0xFFFF) then
← 0xFFFF
GPR[rd]31..16
else
GPR[rd]31..16
← (GPR[rs]31..16 + GPR[rt]31..16)15..0
endif
(The same operations follow every 16 bits)
if ((GPR[rs]127..112 + GPR[rt]127..112) > 0xFFFF) then
← 0xFFFF
GPR[rd]127..112
else
← (GPR[rs]127..112 + GPR[rt]127..112)15..0
GPR[rd]127..112
endif

© SCEI
-170-

SCE CONFIDENTIAL

127

rs

EE Core Instruction Set Manual Version 6.0

112 111

A7

A6

+
127

rt

96 95

A5

+
112 111

B7

80 79

A4

+
96 95

B6

64 63

A3

+
80 79

B5

48 47

A2

+
64 63

B4

32 31

A1

+
48 47

B3

16 15

A0

+
32 31

B2

0

+
16 15

B1

0

B0

Saturation
127

rd

112 111

A7+B7

96 95

A6+B6

80 79

A5+B5

64 63

A4+B4

48 47

A3+B3

32 31

A2+B2

16 15

A1+B1

0

A0+B0

© SCEI
-171-

SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

PADDUW : Parallel Add with Unsigned Saturation Word
128-bit MMI
To add 4 pairs of 32-bit unsigned integers with saturation in parallel.
Operation Code
31

26

25

21

20

16

15

11

10

6

5

0

MMI
011100

rs

rt

rd

PADDUW
10000

MMI1
101000

6

5

5

5

5

6

Format
PADDUW rd, rs, rt
Description
GPR[rd] ← GPR[rs] + GPR[rt]
Splits the 128-bit values in GPR[rs] and GPR[rt] into four 32-bit unsigned integers, adds the data in GPR[rs]
to the corresponding data in GPR[rt] and stores them in the corresponding words in GPR[rd].
Arithmetic results beyond the range of an unsigned 32-bit integer are saturated as follows:
Overflow
: → 0xFFFFFFFF
Exceptions
None
Operation
if ((GPR[rs]31..0 + GPR[rt]31..0) > 0xFFFFFFFF) then
← 0xFFFFFFFF
GPR[rd]31..0
else
← (GPR[rs]31..0 + GPR[rt]31..0)31..0
GPR[rd]31..0
endif
if ((GPR[rs]63..32 + GPR[rt]63..32) > 0xFFFFFFFF) then
← 0xFFFFFFFF
GPR[rd]63..32
else
GPR[rd]63..32
← (GPR[rs]63..32 + GPR[rt]63..32)31..0
endif
if ((GPR[rs]95..64 + GPR[rt]95..64) > 0xFFFFFFFF) then
← 0xFFFFFFFF
GPR[rd]95..64
else
← (GPR[rs]95..64 + GPR[rt]95..64)31..0
GPR[rd]95..64
endif
if ((GPR[rs]127..96 + GPR[rt]127..96) > 0xFFFFFFFF) then
← 0xFFFFFFFF
GPR[rd]127..96
else
← (GPR[rs]127..96 + GPR[rt]127..96)31..0
GPR[rd]127..96
endif

© SCEI
-172-

SCE CONFIDENTIAL

127

rs

EE Core Instruction Set Manual Version 6.0

96 95

A3
127

rt

+

64 63

32 31

A2
96 95

B3

+

A1
64 63

B2

+

0

A0
32 31

B1

+

0

B0

Saturation
127

rd

96 95

A3+B3

64 63

A2+B2

32 31

A1+B1

0

A0+B0

© SCEI
-173-

SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

PADDW : Parallel Add Word
128-bit MMI
To add 4 pairs of 32-bit integers in parallel.
Operation Code
31

26

25

21

20

16

15

11

10

6

5

0

MMI
011100

rs

rt

rd

PADDW
00000

MMI0
001000

6

5

5

5

5

6

Format
PADDW rd, rs, rt
Description
GPR[rd] ← GPR[rs] + GPR[rt]
Splits the 128-bit values in GPR[rs] and GPR[rt] into four 32-bit integers, adds the data in GPR[rs] to the
corresponding data in GPR[rt] and stores them in the corresponding words in GPR[rd].
Exceptions
None
Operation
GPR[rd]31..0
GPR[rd]63..32
GPR[rd]95..64
GPR[rd]127..96
127

rs

96 95

A3
127

rt

+

64 63

A2
96 95

B3

127

rd

← (GPR[rs]31..0 + GPR[rt]31..0)31..0
← (GPR[rs]63..32 + GPR[rt]63..32)31..0
← (GPR[rs]95..64 + GPR[rt]95..64)31..0
← (GPR[rs]127..96 + GPR[rt]127..96)31..0

+

A3+B3

A1
64 63

B2

96 95

32 31

+

A0
32 31

B1

64 63

A2+B2

-174-

+

0

B0

32 31

A1+B1

© SCEI

0

0

A0+B0

SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

PADSBH : Parallel Add/Subtract Halfword
128-bit MMI
To add/subtract 8 pairs of 16-bit integers in parallel.
Operation Code
31

26

25

21

20

16

15

11

10

6

5

0

MMI
011100

rs

rt

rd

PADSBH
00100

MMI1
101000

6

5

5

5

5

6

Format
PADSBH rd, rs, rt
Description
GPR[rd] ← GPR[rs] +/– GPR[rt]
Splits the 128-bit values in GPR[rs] and GPR[rt] into eight 16-bit integers, adds the high-order four pairs and
subtracts the low-order four pairs, and stores them in the corresponding halfwords in GPR[rd].
Exceptions
None. When it overflows or underflows, simply ignored and an exception do not occur.
Operation
GPR[rd]15..0
GPR[rd]31..16
GPR[rd]47..32
GPR[rd]63..48
GPR[rd]79..64
GPR[rd]95..80
GPR[rd]111..96
GPR[rd]127..112
127

rs

← (GPR[rs]15..0 – GPR[rt]15..0)15..0
← (GPR[rs]31..16 – GPR[rt]31..16)15..0
← (GPR[rs]47..32 – GPR[rt]47..32)15..0
← (GPR[rs]63..48 – GPR[rt]63..48)15..0
← (GPR[rs]79..64 + GPR[rt]79..64)15..0
← (GPR[rs]95..80 + GPR[rt]95..80)15..0
← (GPR[rs]111..96 + GPR[rt]111..96)15..0
← (GPR[rs]127..112 + GPR[rt]127..112)15..0

112 111

A7

A6

+
127

rt

rd

A7+B7

A6+B6

A5+B5

A4+B4

A3−B3

−
16 15

B1

32 31

A2−B2

0

A0

−
32 31

B2

48 47

16 15

A1

−
48 47

B3

64 63

32 31

A2

−
64 63

B4

80 79

48 47

A3

+
80 79

B5

96 95

64 63

A4

+
96 95

B6

112 111

80 79

A5

+
112 111

B7

127

96 95

0

B0

16 15

A1−B1

0

A0−B0

© SCEI
-175-

SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

PAND : Parallel And
128-bit MMI
To calculate a bitwise logical AND.
Operation Code
31

26

25

21

20

16

15

11

10

6

5

0

MMI
011100

rs

rt

rd

PAND
10010

MMI2
001001

6

5

5

5

5

6

Format
PAND rd, rs, rt
Description
GPR[rd] ← GPR[rs] AND GPR[rt]
Calculates a bitwise logical AND between the 128-bit values of GPR[rs] and GPR[rt]. The result is stored in
GPR[rd].
The truth table values for AND are as follows:
X
0
0
1
1

Y
0
1
0
1

X AND Y
0
0
0
1

Exceptions
None
Operation
GPR[rd]127..0

← GPR[rs]127..0 AND GPR[rt]127..0

© SCEI
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SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

PCEQB : Parallel Compare for Equal Byte
128-bit MMI
To compare 16 pairs of byte data in parallel.
Operation Code
31

26

25

21

20

16

15

11

10

6

5

0

MMI
011100

rs

rt

rd

PCEQB
01010

MMI1
101000

6

5

5

5

5

6

Format
PCEQB rd, rs, rt
Description
GPR[rd] ← (GPR[rs] = GPR[rt])
Splits the 128-bit values in GPR[rs] and GPR[rt] into sixteen bytes and compares the data in GPR[rs] with
the corresponding data in GPR[rt]. If the results are equal, stores 0xFF and if not equal, stores 0x00 in the
corresponding bytes in GPR[rd].
Exceptions
None
Operation
if (GPR[rs]7..0 = GPR[rt]7..0) then
GPR[rd]7..0 ← 18
else
GPR[rd]7..0 ← 08
endif
if (GPR[rs]15..8 = GPR[rt]15..8) then
GPR[rd]15..8 ← 18
else
GPR[rd]15..8 ← 08
endif
(The same operations follow every 8 bits)
if (GPR[rs]127..120 = GPR[rt]127..120) then
GPR[rd]127..120 ← 18
else
GPR[rd]127..120 ← 08
endif

© SCEI
-177-

SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

127 120119 112 111 104 103 96 95 88 87 80 79 72 71 64 63 56 55 48 47 40 39 32 31 24 23 16 15

rs A15 A14 A13 A12

=

=

=

=

A11 A10

=

=

B11 B10

A8

A7

A6

A5

A4

A3

A2

A1

A0

=

=

=

=

=

=

=

=

=

=

B9

B8

B7

B6

B5

B4

B3

B2

rd

c

c

8

c

8

c

8

c

8

c

8

c

8

c

8

© SCEI
-178-

c

8

c

8

c

8

c

8

c

8

c

8

87

B1

127 120119 112 111 104 103 96 95 88 87 80 79 72 71 64 63 56 55 48 47 40 39 32 31 24 23 16 15
8

0

A9

127 120119 112 111 104 103 96 95 88 87 80 79 72 71 64 63 56 55 48 47 40 39 32 31 24 23 16 15

rt B15 B14 B13 B12

87

B0

87

c

8

0

0

c

8

SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

PCEQH : Parallel Compare for Equal Halfword
128-bit MMI
To compare 8 pairs of halfword data in parallel.
Operation Code
31

26

25

21

20

16

15

11

10

6

5

0

MMI
011100

rs

rt

rd

PCEQH
00110

MMI1
101000

6

5

5

5

5

6

Format
PCEQH rd, rs, rt
Description
GPR[rd] ← (GPR[rs] = GPR[rt])
Splits the 128-bit values in GPR[rs] and GPR[rt] into eight halfwords and compares the data in GPR[rs]
with the corresponding data in GPR[rt]. If the results are equal, stores 0xFFFF and if not equal, stores
0x0000 in the corresponding halfwords in GPR[rd].
Exceptions
None
Operation
if (GPR[rs]15..0 = GPR[rt]15..0) then
GPR[rd]15..0 ← 116
else
GPR[rd]15..0 ← 016
endif
if (GPR[rs]31..16 = GPR[rt]31..16) then
GPR[rd]31..16 ← 116
else
GPR[rd]31..16 ← 016
endif
(The same operations follow every 16 bits)
if (GPR[rs]127..112 = GPR[rt]127..112) then
GPR[rd]127..112 ← 116
else
GPR[rd]127..112 ← 016
endif

© SCEI
-179-

SCE CONFIDENTIAL

127

rs

112 111

A7

=

127

rt

96 95

A6
112 111

B7

127

rd

EE Core Instruction Set Manual Version 6.0

=

c

A5
96 95

B6

112 111
16

80 79

=

c

A4
80 79

B5

96 95
16

64 63

=

c

A3
64 63

B4

80 79
16

48 47

=

64 63

c

A2
48 47

B3

16

-180-

=

16

16 15

A1
32 31

B2

48 47

c

© SCEI

32 31

=

c

A0
16 15

B1

32 31
16

0

=
B0

16 15

c

16

0

0

c

16

SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

PCEQW : Parallel Compare for Equal Word
128-bit MMI
To compare 4 pairs of word data in parallel.
Operation Code
31

26

25

21

20

16

15

11

10

6

5

0

MMI
011100

rs

rt

rd

PCEQW
00010

MMI1
101000

6

5

5

5

5

6

Format
PCEQW rd, rs, rt
Description
GPR[rd] ← (GPR[rs] = GPR[rt])
Splits the 128-bit values in GPR[rs] and GPR[rt] into four words and compares the data in GPR[rs] with the
corresponding data in GPR[rt]. If the results are equal, stores 0xFFFFFFFF and if not equal, stores
0x00000000 in the corresponding words in GPR[rd].
Exceptions
None
Operation
if (GPR[rs]31..0 = GPR[rt]31..0) then
GPR[rd]31..0 ← 132
else
GPR[rd]31..0 ← 032
endif
if (GPR[rs]63..32 = GPR[rt]63..32) then
GPR[rd]63..32 ← 132
else
GPR[rd]63..32 ← 032
endif
if (GPR[rs]95..64 = GPR[rt]95..64) then
GPR[rd]95..64 ← 132
else
GPR[rd]95..64 ← 032
endif
if (GPR[rs]127..96 = GPR[rt]127..96) then
GPR[rd]127..96 ← 132
else
GPR[rd]127..96 ← 032
endif

© SCEI
-181-

SCE CONFIDENTIAL

127

rs

96 95

A3
127

rt

=

64 63

A2
96 95

B3

127

rd

EE Core Instruction Set Manual Version 6.0

=

c 32

A1
64 63

B2

96 95

32 31

=

A0
32 31

B1

64 63

c 32

-182-

=

0

B0

32 31

c 32

© SCEI

0

0

c 32

SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

PCGTB : Parallel Compare for Greater Than Byte
128-bit MMI
To compare 16 pairs of byte data in parallel.
Operation Code
31

26

25

21

20

16

15

11

10

6

5

0

MMI
011100

rs

rt

rd

PCGTB
01010

MMI0
001000

6

5

5

5

5

6

Format
PCGTB rd, rs, rt
Description
GPR[rd] ← (GPR[rs] > GPR[rt])
Splits the 128-bit values in GPR[rs] and GPR[rt] into sixteen 8-bit signed integers and compares the data in
GPR[rs] with the corresponding data in GPR[rt]. If GPR[rs] is greater than GPR[rt], stores 0xFF and
otherwise, stores 0x00 in the corresponding bytes in GPR[rd].
Exceptions
None
Operation
if (GPR[rs]7..0 > GPR[rt]7..0) then
GPR[rd]7..0 ← 18
else
GPR[rd]7..0 ← 08
endif
if (GPR[rs]15..8 > GPR[rt]15..8) then
GPR[rd]15..8 ← 18
else
GPR[rd]15..8 ← 08
endif
(The same operations follow every 8 bits)
if (GPR[rs]127..120 > GPR[rt]127..120) then
GPR[rd]127..120 ← 18
else
GPR[rd]127..120 ← 08
endif

© SCEI
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SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

127 120119 112 111 104 103 96 95 88 87 80 79 72 71 64 63 56 55 48 47 40 39 32 31 24 23

rs A15 A14

>

>

A13 A12

>

A11 A10

>

>

>

B12 B11 B10

A8

A7

A6

A5

A4

A3

A2

A1

>

>

>

>

>

>

>

>

>

B9

B8

B7

B6

B5

B4

B3

B2

16 15

127 120 119 112 111 104 103 96 95 88 87 80 79 72 71 64 63 56 55 48 47 40 39 32 31 24 23

rd

c

8

8

c

c

8

8

c

c

8

8

c

87

A9

127 120 119 112 111 104 103 96 95 88 87 80 79 72 71 64 63 56 55 48 47 40 39 32 31 24 23

rt B15 B14 B13

16 15

8

c

8

c

© SCEI
-184-

8

c

8

c

8

c

8

c

8

c

8

A0
87

B1

16 15

c

0

>

0

B0

87
8

c

0

c

8

SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

PCGTH : Parallel Compare for Greater Than Halfword
128-bit MMI
To compare 8 pairs of halfword data in parallel.
Operation Code
31

26

25

21

20

16

15

11

10

6

5

0

MMI
011100

rs

rt

rd

PCGTH
00110

MMI0
001000

6

5

5

5

5

6

Format
PCGTH rd, rs, rt
Description
GPR[rd] ← (GPR[rs] > GPR[rt])
Splits the 128-bit values in GPR[rs] and GPR[rt] into eight 16-bit signed integers and compares the data in
GPR[rs] with the corresponding data in GPR[rt]. If GPR[rs] is greater than GPR[rt], stores 0xFFFF and
otherwise, stores 0x0000 in the corresponding halfwords in GPR[rd].
Exceptions
None
Operation
if (GPR[rs]15..0 > GPR[rt]15..0) then
GPR[rd]15..0 ← 116
else
GPR[rd]15..0 ← 016
endif
if (GPR[rs]31..16 > GPR[rt]31..16) then
GPR[rd]31..16 ← 116
else
GPR[rd]31..16 ← 016
endif
(The same operations follow every 16 bits)
if (GPR[rs]127..112 > GPR[rt]127..112) then
GPR[rd]127..112 ← 116
else
GPR[rd]127..112 ← 016
endif

© SCEI
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SCE CONFIDENTIAL

127

rs

112 111

A7

>

127

rt

96 95

A6
112 111

B7

127

rd

EE Core Instruction Set Manual Version 6.0

>

c

A5
96 95

B6

112 111
16

80 79

>

c

A4
80 79

B5

96 95
16

64 63

>

c

A3

>

64 63

B4

80 79
16

48 47

A2

64 63

c

© SCEI
-186-

16 15

A1

>

32 31

B2

48 47
16

c

>

48 47

B3

16

32 31

c

A0

>

16 15

B1

32 31
16

0

B0

16 15
16

c

0

0
16

c

SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

PCGTW : Parallel Compare for Greater Than Word
128-bit MMI
To compare 4 pairs of word data in parallel.
Operation Code
31

26

25

21

20

16

15

11

10

6

5

0

MMI
011100

rs

rt

rd

PCGTW
00010

MMI0
001000

6

5

5

5

5

6

Format
PCGTW rd, rs, rt
Description
GPR[rd] ← (GPR[rs] > GPR[rt])
Splits the 128-bit values in GPR[rs] and GPR[rt] into four 32-bit signed integers and compares the data in
GPR[rs] with the corresponding data in GPR[rt]. If GPR[rs] is greater than GPR[rt], stores 0xFFFFFFFF,
and otherwise stores 0x00000000 in the corresponding words in GPR[rd].
Exceptions
None
Operation
if (GPR[rs]31..0 > GPR[rt]31..0) then
GPR[rd]31..0 ← 132
else
GPR[rd]31..0 ← 032
endif
if (GPR[rs]63..32 > GPR[rt]63..32) then
GPR[rd]63..32 ← 132
else
GPR[rd]63..32 ← 032
endif
if (GPR[rs]95..64 > GPR[rt]95..64) then
GPR[rd]95..64 ← 132
else
GPR[rd]95..64 ← 032
endif
if (GPR[rs]127..96 > GPR[rt]127..96) then
GPR[rd]127..96 ← 132
else
GPR[rd]127..96 ← 032
endif

© SCEI
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SCE CONFIDENTIAL

127

rs

96 95

A3
127

rt

>

64 63

A2
96 95

B3

127

rd

EE Core Instruction Set Manual Version 6.0

>

c 32

A1
64 63

B2

96 95

32 31

>

A0
32 31

B1

64 63

c 32

-188-

>

0

B0

32 31

c 32

© SCEI

0

0

c 32

SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

PCPYH : Parallel Copy Halfword
128-bit MMI
To copy halfword data in parallel.
Operation Code
31

26

25

21

20

16

15

11

10

6

5

0

MMI
011100

0
00000

rt

rd

PCPYH
11011

MMI3
101001

6

5

5

5

5

6

Format
PCPYH rd, rt
Description
GPR[rd] ← GPR[rt]
Splits GPR[rt] into the high-order and low-order 64 bits. Copies each of the least-significant halfwords into
each of the halfwords of the two doublewords of GPR[rd].
Exceptions
None
Operation
GPR[rd]15..0
GPR[rd]31..16
GPR[rd]47..32
GPR[rd]63..48
GPR[rd]79..64
GPR[rd]95..80
GPR[rd]111..96
GPR[rd]127..112

← GPR[rt]15..0
← GPR[rt]15..0
← GPR[rt]15..0
← GPR[rt]15..0
← GPR[rt]79..64
← GPR[rt]79..64
← GPR[rt]79..64
← GPR[rt]79..64

127

80 79

rt

16 15

A1

127
rd

64 63

112 111
A1

96 95
A1

80 79
A1

0
A0

64 63
A1

48 47
A0

32 31
A0

16 15
A0

0
A0

© SCEI
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SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

PCPYLD : Parallel Copy Lower Doubleword
128-bit MMI
To combine 2 doublewords.
Operation Code
31

26

25

21

20

16

15

11

10

6

5

0

MMI
011100

rs

rt

rd

PCPYLD
01110

MMI2
001001

6

5

5

5

5

6

Format
PCPYLD rd, rs, rt
Description
GPR[rd] ← copy(GPR[rs], GPR[rt])
To calculate a 128-bit value, in which the high-order and low-order 64 bits correspond to the low-order 64
bits of GPR[rs] and low-order 64 bits in GPR[rt] respectively, and stores it in GPR[rd].
Exceptions
None
Operation
GPR[rd]127..0

← GPR[rs]63..0 || GPR[rt]63..0

127

64 63

rs

0
A0

127
rd

64 63
A0

127

0
B0

64 63

rt

0
B0

© SCEI
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SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

PCPYUD : Parallel Copy Upper Doubleword
128-bit MMI
To combine 2 doublewords.
Operation Code
31

26

25

21

20

16

15

11

10

6

5

0

MMI
011100

rs

rt

rd

PCPYUD
01110

MMI3
101001

6

5

5

5

5

6

Format
PCPYUD rd, rs, rt
Description
GPR[rd] ← copy(GPR[rs], GPR[rt])
To calculate a 128-bit value, in which the low-order and high-order 64 bits correspond to the high-order 64
bits of GPR[rs] and high-order 64 bits of GPR[rt] respectively, and stores it in GPR[rd].
Exceptions
None
Operation
GPR[rd]127..0

← GPR[rt]127..64 || GPR[rs]127..64

127

rs

0

64 63

0

A0
127

rd

B0
127

rt

64 63

A0
64 63

0

B0

© SCEI
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SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

PDIVBW : Parallel Divide Broadcast Word
128-bit MMI
To divide four 32-bit signed integers by a 16-bit signed integer in parallel.
Operation Code
31

26

25

21

20

16

15

11

10

6

5

0

MMI
011100

rs

rt

0
00000

PDIVBW
11101

MMI2
001001

6

5

5

5

5

6

Format
PDIVBW rs, rt
Description
(LO, HI) ← GPR[rs] / GPR[rt]
Splits GPR[rs] into four signed 32-bit integers and divides each of them by the least-significant halfword of
GPR[rt]. The resulting four quotients (32-bit integers) are stored in the words corresponding to GPR[rs] in
the LO register and the four remainders (16-bit integers) are zero-extended and stored in the words
corresponding to GPR[rs] in the HI register.
Restrictions
If the least-significant halfword in GPR[rt] is zero, the arithmetic result is undefined. (An exception does not
occur.)
Exceptions
None. If the divisor is 0, an exception does not occur on overflow.
Operation
q0
r0
LO31..0
HI31..0

← GPR[rs]31..0 DIV GPR[rt]15..0
← GPR[rs]31..0 MOD GPR[rt]15..0
← q031..0
← (r015)16 || r015..0

q1
r1
LO63..32
HI63..32

← GPR[rs]63..32 DIV GPR[rt]15..0
← GPR[rs]63..32 MOD GPR[rt]15..0
← q131..0
← (r115)16 || r115..0

q2
r2
LO95..64
HI95..64

← GPR[rs]95..64 div GPR[rt]15..0
← GPR[rs]95..64 mod GPR[rt]15..0
← q231..0
← (r215)16 || r215..0

q3
r3
LO127..96
HI127..96

← GPR[rs]127..96 div GPR[rt]15..0
← GPR[rs]127..96 mod GPR[rt]15..0
← q331..0
← (r315)16 || r315..0

© SCEI
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SCE CONFIDENTIAL

127

rs

EE Core Instruction Set Manual Version 6.0

96 95

A3

64 63

A2

32 31

A1

0

A0

÷
127

16 15

rt

B0

127

HI

96 95

sign ext(A3 MOD B0)
127

LO

0

64 63

sign ext(A2 MOD B0)

sign ext(A1 MOD B0)

64 63

96 95

A3 DIV B0

32 31

A2 DIV B0

0

sign ext( A0 MOD B0)

32 31

A1 DIV B0

0

A0 DIV B0

Programming Notes
In the EE Core, the integer divide operation proceeds asynchronously. An attempt to read the contents of
the LO or HI register before the divide operation finishes will result in interlock. Other CPU instructions
can execute without delay. Therefore, scheduling the divide operation appropriately can improve
performance.
When 0x80000000(–2147483648), the signed minimum value, is divided by 0xFFFF(–1), the operation will
result in an overflow. However, in this instruction an overflow exception does not occur and the following
results will be returned.
Quotient: 0x80000000(–2147483648), Remainder: 0x00000000(0)
If an overflow or divide-by-zero is required to be detected, then add an instruction that detects these
conditions following the divide instruction. Since the divide instruction is asynchronous, the divide operation
and check can be executed in parallel. If an overflow or divide-by-zero is detected, then the system software
can be informed of the problem by generating an exception using an appropriate code value with a BREAK
instruction.

© SCEI
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SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

PDIVUW : Parallel Divide Unsigned Word
128-bit MMI
To divide 2 pairs of 32-bit unsigned integers in parallel.
Operation Code
31

26

25

21

20

16

15

11

10

6

5

0

MMI
011100

rs

rt

0
00000

PDIVUW
01101

MMI3
101001

6

5

5

5

5

6

Format
PDIVUW rs, rt
Description
(LO, HI) ← GPR[rs] / GPR[rt]
Divides bits 31..0 of GPR[rs] by bits 31..0 of GPR[rt]. Both are treated as 32-bit unsigned integers. The
resulting quotients and remainders are sign-extended and stored in bits 63..0 of the LO and HI registers
respectively. Similarly, divides bits 95..64 of GPR[rs] by bits 95..64 of GPR[rt] and stores the results in bits
127..64 of LO and HI respectively.
Restrictions
If GPR[rt] and GPR[rs] are not sign-extended 32-bit values (bits 127..95 equal and bits 63..31 equal), then the
result is undefined.
If the divisor is 0, an exception does not occur on overflow.
Exceptions
None. Even if the divisor is zero, a divide-by-zero exception does not occur.
Operation
if (NotWordValue(GPR[rs]) or NotWordValue(GPR[rt])) then UndefinedResult() endif
q0
← (0 || GPR[rs]31..0) DIV (0 || GPR[rt]31..0)
r0
← (0 || GPR[rs]31..0) MOD (0 || GPR[rt]31..0)
← (q031)32 || q031..0
LO63..0
← (r031)32 || r031..0
HI63..0
q1
r1
LO127..64
HI127..64

← (0 || GPR[rs]95..64) DIV (0 || GPR[rt]95..64)
← (0 || GPR[rs]95..64) MOD (0 || GPR[rt]95..64)
← (q131)32 || q131..0
← (r131)32 || r131..0

© SCEI
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SCE CONFIDENTIAL

127

EE Core Instruction Set Manual Version 6.0

96 95

rs
127

96 95

rt

32 31

¸

HI

96 95
sign ext

127

64 63

32 31

sign ext

¸

0

B0

64 63

(0 || A1) MOD (0 || B1)
96 95

0
A0

B1

127

LO

64 63
A1

32 31
sign ext

64 63

(0 || A1) DIV (0 || B1)

(0 || A0) MOD (0 || B0)
32 31

sign ext

0
0

(0 || A0) DIV (0 || B0)

Programming Notes
In the EE Core, the integer divide operation proceeds asynchronously. An attempt to read the contents of
the LO or HI register before the divide operation finishes will result in interlock. Other CPU instructions
can execute without delay. Therefore, scheduling the divide operation appropriately can improve
performance.
If divide-by-zero is required to be detected, then add an instruction that detects this condition following the
divide instruction. Since the divide instruction is asynchronous, the divide operation and check can be
executed in parallel. If divide-by-zero is detected, then the system software can be informed of the problem
by generating an exception using an appropriate code value with a BREAK instruction.

© SCEI
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SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

PDIVW : Parallel Divide Word
128-bit MMI
To divide 2 pairs of 32-bit signed integers in parallel.
Operation Code
31

26

25

21

20

16

15

11

10

6

5

0

MMI
011100

rs

rt

0
00000

PDIVW
01101

MMI2
001001

6

5

5

5

5

6

Format
PDIVW rs, rt
Description
(LO, HI) ← GPR[rs] / GPR[rt]
Divides bits 31..0 of GPR[rs] by bits 31..0 of GPR[rt]. Both are treated as 32-bit signed integers. The
resulting quotients and remainders are sign-extended and stored in bits 63..0 of the LO and HI registers
respectively. Similarly, divides bits 95..64 of GPR[rs] by bits 95..64 of GPR[rt] and stores the results in bits
127..64 of LO and HI, respectively.
Restrictions
If GPR[rt] and GPR[rs] are not sign-extended 32-bit values (bits 127..95 equal and bits 63..31 equal), then the
result is undefined.
If the divisor is 0, an exception does not occur on overflow. (An exception does not occur.)
Exceptions
None. If the divisor is zero, an exception does not occur when the arithmetic result overflows.
Operation
if (NotWordValue(GPR[rs]) or NotWordValue(GPR[rt])) then UndefinedResult() endif
q0
← GPR[rs]31..0 DIV GPR[rt]31..0
r0
← GPR[rs]31..0 MOD GPR[rt]31..0
q1
← GPR[rs]95..64 DIV GPR[rt]95..64
r1
← GPR[rs]95..64 MOD GPR[rt]95..64
← (q031)32 || q031..0
LO63..0
← (r031)32 || r031..0
HI63..0
LO127..64 ← (q131)32 || q131..0
← (r131)32 || r131..0
HI127..64
127

96 95

rs

64 63

32 31

A1
127

96 95

rt

÷

64 63

32 31

B1

127

HI
127

LO

A1 MOD B1
96 95

sign ext

÷

0

B0

64 63

96 95

sign ext

0

A0

32 31

sign ext
64 63

A1 DIV B1

32 31

sign ext

© SCEI
-196-

0

A0 MOD B0
0

A0 DIV B0

SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

Programming Notes
In the EE Core, the integer divide operation proceeds asynchronously. An attempt to read the contents of
the LO or HI register before the divide operation finishes will result in interlock. Other CPU instructions
can execute without delay. Therefore, scheduling the divide operation appropriately can improve
performance.
When 0x80000000(–2147483648), the signed minimum value, is divided by 0xFFFFFFFF(–1), the operation
will result in an overflow. However, in this instruction an overflow exception does not occur and the
following results will be returned:
Quotient: 0x80000000(–2147483648), Remainder: 0x00000000(0)
If an overflow or divide-by-zero is required to be detected, then add an instruction that detects these
conditions following the divide instruction. Since the divide instruction is asynchronous, the divide operation
and check can be executed in parallel. If an overflow or divide-by-zero is detected, then the system software
can be informed of the problem by generating an exception using an appropriate code value with a BREAK
instruction.

© SCEI
-197-

SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

PEXCH : Parallel Exchange Center Halfword
128-bit MMI
To exchange the position of halfwords in 128-bit data.
Operation Code
31

26

25

21

20

16

15

11

10

6

5

0

MMI
011100

0
00000

rt

rd

PEXCH
11010

MMI3
101001

6

5

5

5

5

6

Format
PEXCH rd, rt
Description
GPR[rd] ← exchange(GPR[rt])
Splits the 128-bit data in GPR[rt] into eight halfwords, exchanges the central halfwords of each doubleword,
and stores them in GPR[rd]. See "Operation" about the details of the exchange.
Exceptions
None
Operation
GPR[rd]15..0
GPR[rd]31..16
GPR[rd]47..32
GPR[rd]63..48
GPR[rd]79..64
GPR[rd]95..80
GPR[rd]111..96
GPR[rd]127..112
127
rt

112 111
A7

127
rd

← GPR[rt]15..0
← GPR[rt]47..32
← GPR[rt]31..16
← GPR[rt]63..48
← GPR[rt]79..64
← GPR[rt]111..96
← GPR[rt]95..80
← GPR[rt]127..112
96 95
A6

112 111
A7

80 79
A5

96 95
A5

64 63
A4

80 79
A6

48 47
A3

64 63
A4

-198-

A2

48 47
A3

© SCEI

32 31

16 15
A1

32 31
A1

0
A0

16 15
A2

0
A0

SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

PEXCW : Parallel Exchange Center Word
128-bit MMI
To exchange the position of words in 128-bit data.
Operation Code
31

26

25

21

20

16

15

11

10

6

5

0

MMI
011100

0
00000

rt

rd

PEXCW
11110

MMI3
101001

6

5

5

5

5

6

Format
PEXCW rd, rt
Description
GPR[rd] ← exchange(GPR[rt])
Splits a 128-bit value in GPR[rt] into four words, exchanges the two central words, and stores the result in
GPR[rd]. See "Operation" about the details of the exchange.
Exceptions
None
Operation
GPR[rd]31..0
GPR[rd]63..32
GPR[rd]95..64
GPR[rd]127..96
127
rt

96 95
A3

127
rd

← GPR[rt]31..0
← GPR[rt]95..64
← GPR[rt]63..32
← GPR[rt]127..96
64 63
A2

96 95
A3

32 31
A1

64 63
A1

0
A0

32 31
A2

0
A0

© SCEI
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SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

PEXEH : Parallel Exchange Even Halfword
128-bit MMI
To exchange the position of halfwords in 128-bit data.
Operation Code
31

26

25

21

20

16

15

11

10

6

5

0

MMI
011100

0
00000

rt

rd

PEXEH
11010

MMI2
001001

6

5

5

5

5

6

Format
PEXEH rd, rt
Description
GPR[rd] ← exchange(GPR[rt])
Splits a 128-bit value in GPR[rt] into eight halfwords, exchanges the sequence partially and stores the result
in GPR[rd]. See "Operation" about the details of the exchange.
Exceptions
None
Operation
GPR[rd]15..0
GPR[rd]31..16
GPR[rd]47..32
GPR[rd]63..48
GPR[rd]79..64
GPR[rd]95..80
GPR[rd]111..96
GPR[rd]127..112
127
rt

112 111
A7

127
rd

← GPR[rt]47..32
← GPR[rt]31..16
← GPR[rt]15..0
← GPR[rt]63..48
← GPR[rt]111..96
← GPR[rt]95..80
← GPR[rt]79..64
← GPR[rt]127..112
96 95
A6

112 111
A7

80 79
A5

96 95
A4

64 63
A4

80 79
A5

48 47
A3

64 63
A6

-200-

A2

48 47
A3

© SCEI

32 31

16 15
A1

32 31
A0

0
A0

16 15
A1

0
A2

SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

PEXEW : Parallel Exchange Even Word
128-bit MMI
To exchange the position of words in 128-bit data.
Operation Code
31

26

25

21

20

16

15

11

10

6

5

0

MMI
011100

0
00000

rt

rd

PEXEW
11110

MMI2
001001

6

5

5

5

5

6

Format
PEXEW rd, rt
Description
GPR[rd] ← exchange(GPR[rt])
Splits a 128-bit value in GPR[rt] into four words, exchanges the two low-order words of each doubleword,
and stores the result in GPR[rd]. See "Operation" about the details of the exchange.
Exceptions
None
Operation
GPR[rd]31..0
GPR[rd]63..32
GPR[rd]95..64
GPR[rd]127..96
127
rt

96 95
A3

127
rd

← GPR[rt]95..64
← GPR[rt]63..32
← GPR[rt]31..0
← GPR[rt]127..96
64 63
A2

96 95
A3

32 31
A1

64 63
A0

0
A0

32 31
A1

0
A2

© SCEI
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SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

PEXT5 : Parallel Extend from 5 bits
128-bit MMI
To extend 4 bytes in the 1-5-5-5 bit format to the 8-8-8-8 bit format.
Operation Code
31

26

25

21

20

16

15

11

10

6

5

0

MMI
011100

0
00000

rt

rd

PEXT5
11110

MMI0
001000

6

5

5

5

5

6

Format
PEXT5 rd, rt
Description
GPR[rd] ← extend(GPR[rt])
Splits the 128-bit data in GPR[rt] into four words. Each of the low-order 16 bits are considered to be in the
1-5-5-5 bit data format, and they are extended to four words in the to 8-8-8-8 bit data format, as illustrated in
"Operation". The resulting value is stored in GPR[rd].
Exceptions
None
Operation
GPR[rd]31..0

← GPR[rt]15 || 07 || GPR[rt]14..10 || 03 || GPR[rt]9..5 || 03
|| GPR[rt]4..0 || 03
← GPR[rt]47 || 07 || GPR[rt]46..42 || 03 || GPR[rt]41..37 || 03
|| GPR[rt]36..32 || 03
← GPR[rt]79 || 07 || GPR[rt]78..74 || 03 || GPR[rt]73..69 || 03
|| GPR[rt]68..64 || 03
← GPR[rt]111 || 07 || GPR[rt]110..106 || 03 || GPR[rt]105..101 || 03
|| GPR[rt]100..96 || 03

GPR[rd]63..32
GPR[rd]95..64
GPR[rd]127..96
127

112 111

96 95

80 79

64 63

48 47

32 31

16 15

0

rt
127

96 95

64 63

32 31

0

rd

31

16 15 14

rt

A3
1bit
31 30

rd A3

24 23
7

0

8bit

10 9

A2

5bit
19 18

0

11 10

8bit

0
8bit

© SCEI
-202-

A0
5bit

8 7
3

A1

0

A1
5bit

16 15
3

A2

5 4

3 2

0
3

A0

0
8bit

SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

PEXTLB : Parallel Extend Lower from Byte
128-bit MMI
To combine two doublewords interleaving by bytes.
Operation Code
31

26

25

21

20

16

15

11

10

6

5

0

MMI
011100

rs

rt

rd

PEXTLB
11010

MMI0
001000

6

5

5

5

5

6

Format
PEXTLB rd, rs, rt
Description
GPR[rd] ← combine(GPR[rs] , GPR[rt])
Splits the low-order 64 bits of GPR[rs] and GPR[rt] into byte data and stores them in GPR[rd] in an
interleaved manner.
Exceptions
None
Operation
GPR[rd]15..0
GPR[rd]31..16

← GPR[rs]7..0 || GPR[rt]7..0
← GPR[rs]15..8 || GPR[rt]15..8

(The same operations follow every 16 bits)
GPR[rd]127..112

← GPR[rs]63..56 || GPR[rt]63..56

127

64 63 56 55 48 47 40 39 32 31 24 23 16 15

rs

A7

A6

A5

A4

A3

A2

A1

127 120 119 112 111 104 103 96 95 88 87 80 79 72 71 64 63 56 55 48 47 40 39 32 31 24 23 16 15

rd A7
127

rt

B7

A6

B6

A5

B5

A4

B4

A3

B3

A2

B2

A1

B1

A0

64 63 56 55 48 47 40 39 32 31 24 23 16 15

B7

B6

B5

B4

B3

B2

B1

8 7

0

A0

8 7

0

B0
8 7

0

B0

© SCEI
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SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

PEXTLH : Parallel Extend Lower from Halfword
128-bit MMI
To combine two doublewords interleaving by halfwords.
Operation Code
31

26

25

21

20

16

15

11

10

6

5

0

MMI
011100

rs

rt

rd

PEXTLH
10110

MMI0
001000

6

5

5

5

5

6

Format
PEXTLH rd, rs, rt
Description
GPR[rd] ← combine(GPR[rs] , GPR[rt])
Splits the low-order 64 bits of GPR[rs] and GPR[rt] into halfwords and stores them in GPR[rd] in an
interleaved manner.
Exceptions
None
Operation
GPR[rd]31..0
GPR[rd]63..32

← GPR[rs]15.. 0 || GPR[rt]15..0
← GPR[rs]31..16 || GPR[rt]31..16

(The same operations follow every 32 bits)
← GPR[rs]63..48 || GPR[rt]63..48

GPR[rd]127..112
127

64 63

rs

48 47

A3

127

rd

112 111

A3
127

96 95

B3

80 79

A2

64 63

B2

A2

48 47

A1
64 63

rt

-204-

16 15

A1

32 31

B1
48 47

B3

© SCEI

32 31

A0

16 15

A0
32 31

B2

0

0

B0
16 15

B1

0

B0

SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

PEXTLW : Parallel Extend Lower from Word
128-bit MMI
To combine two doublewords interleaving by words.
Operation Code
31

26

25

21

20

16

15

11

10

6

5

0

MMI
011100

rs

rt

rd

PEXTLW
10010

MMI0
001000

6

5

5

5

5

6

Format
PEXTLW rd, rs, rt
Description
GPR[rd] ← combine(GPR[rs] , GPR[rt])
Splits the low-order 64 bits of GPR[rs] and GPR[rt] into words and stores them in GPR[rd] in an interleaved
manner.
Exceptions
None
Operation
GPR[rd]63..0
GPR[rd]127..64

← GPR[rs]31..0 || GPR[rt]31..0
← GPR[rs]63..32 || GPR[rt]63..32

127

64 63

rs

32 31

A1
127

rd

96 95

A1
127

64 63

B1

A0
32 31

A0
64 63

rt

0

0

B0
32 31

B1

0

B0

© SCEI
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SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

PEXTUB : Parallel Extend Upper from Byte
128-bit MMI
To combine two doublewords interleaving by bytes.
Operation Code
31

26

25

21

20

16

15

11

10

6

5

0

MMI
011100

rs

rt

rd

PEXTUB
11010

MMI1
101000

6

5

5

5

5

6

Format
PEXTUB rd, rs, rt
Description
GPR[rd] ← combine(GPR[rs] , GPR[rt])
Splits the high-order 64 bits of GPR[rs] and GPR[rt] into bytes and stores them in GPR[rd] in an interleaved
manner.
Exceptions
None
Operation
GPR[rd]15..0
GPR[rd]31..16

← GPR[rs]71..64 || GPR[rt]71..64
← GPR[rs]79..72 || GPR[rt]79..72

(The same operations follow every 16 bits)
GPR[rd]127..112

← GPR[rs]127..120 || GPR[rt]127..120

127 120 119 112 111 104 103 96 95 88 87 80 79 72 71 64 63

rs

A7

A6

A5

A4

A3

A2

A1

0

A0

127 120 119 112 111 104 103 96 95 88 87 80 79 72 71 64 63 56 55 48 47 40 39 32 31 24 23 16 15

rd A7

B7

A6

B6

A5

B5

A4

B4

A3

127 120 119 112 111 104 103 96 95 88 87 80 79 72 71 64 63

rt

B7

B6

B5

B4

B3

B2

B1

B0

© SCEI
-206-

B3

A2

B2

A1

B1

A0

8 7

0

B0
0

SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

PEXTUH : Parallel Extend Upper from Halfword
128-bit MMI
To combine two doublewords interleaving by halfwords.
Operation Code
31

26

25

21

20

16

15

11

10

6

5

0

MMI
011100

rs

rt

rd

PEXTUH
10110

MMI1
101000

6

5

5

5

5

6

Format
PEXTUH rd, rs, rt
Description
GPR[rd] ← combine(GPR[rs] , GPR[rt])
Splits the high-order 64 bits of GPR[rs] and GPR[rt] into halfwords and stores them in GPR[rd] in an
interleaved manner.
Exceptions
None
Operation
GPR[rd]31..0
GPR[rd]63..32
GPR[rd]95..64
GPR[rd]127..96
127
rs

112 111
A3

127
rd

96 95
A2

112 111
A3

127
rt

← GPR[rs]79.64 || GPR[rt]79..64
← GPR[rs]95..80 || GPR[rt]95..80
← GPR[rs]111..96 || GPR[rt]111..96
← GPR[rs]127..112 || GPR[rt]127..112

A1
96 95

B3
112 111

B3

80 79

A2

64 63
B2

80 79
B1

0

A0
80 79

96 95
B2

64 63

48 47
A1

64 63

32 31
B1

16 15
A0

0
B0
0

B0

© SCEI
-207-

SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

PEXTUW : Parallel Extend Upper from Word
128-bit MMI
To combine two doublewords interleaving by words.
Operation Code
31

26

25

21

20

16

15

11

10

6

5

0

MMI
011100

rs

rt

rd

PEXTUW
10010

MMI1
101000

6

5

5

5

5

6

Format
PEXTUW rd, rs, rt
Description
GPR[rd] ← combine(GPR[rs] , GPR[rt])
Splits the high-order 64 bits of GPR[rs] and GPR[rt] into words and stores them in GPR[rd] in an
interleaved manner.
Exceptions
None
Operation
GPR[rd]63..0
GPR[rd]127..64
127

rs

← GPR[rs]95.64 || GPR[rt]95..64
← GPR[rs]127..96 || GPR[rt]127..96
96 95

A1
127

rd

96 95

127

64 63

B1
96 95

B1

0

A0

A1

rt

64 63

32 31

A0
64 63

B0

© SCEI
-208-

0

B0
0

SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

PHMADH : Parallel Horizontal Multiply-Add Halfword
128-bit MMI
To multiply 8 pairs of 16-bit signed integers and horizontally add.
Operation Code
31

26

25

21

20

16

15

11

10

6

5

0

MMI
011100

rs

rt

rd

PHMADH
10001

MMI2
001001

6

5

5

5

5

6

Format
PHMADH rd, rs, rt
Description
(GPR[rd], HI, LO) ← GPR[rs] × GPR[rt] + GPR[rs] × GPR[rt]
Splits the 128-bit data in GPR[rs] and GPR[rt] into eight 16-bit signed integers. Multiplies the halfwords in
GPR[rs] by the corresponding halfwords in GPR[rt], then adds the result of adjacent multiplications and
stores them in the GPR[rd], HI and LO registers, as described in "Operation".
Exceptions
None. Even when the result of the arithmetic operation overflows, an overflow exception does not occur.
Operation
prod0
LO31..0
GPR[rd]31..0

← GPR[rs]31..16 × GPR[rt]31..16 + GPR[rs]15..0 × GPR[rt]15..0
← prod031..0
← prod031..0

prod1
HI31..0
GPR[rd]63..32

← GPR[rs]63..48 × GPR[rt]63..48 + GPR[rs]47..32 × GPR[rt]47..32
← prod131..0
← prod131..0

prod2
LO95..64
GPR[rd]95..64

← GPR[rs]95..80 × GPR[rt]95..80 + GPR[rs]79..64 × GPR[rt]79..64
← prod231..0
← prod231..0

prod3
HI95..64
GPR[rd]127..96

← GPR[rs]127..112 × GPR[rt]127..112 + GPR[rs]111..96 × GPR[rt]111..96
← prod331..0
← prod331..0

© SCEI
-209-

SCE CONFIDENTIAL

127

rs

EE Core Instruction Set Manual Version 6.0

112 111

A7

96 95

A6

80 79

A5

64 63

48 47

A4

A3

32 31

16 15

A2

A1

0

A0

´
127

rt

112 111

B7

96 95

80 79

B6

B5

+

127

rd

96 95

127

Undefined

B3

32 31

B2

B0

32 31

64 63

0

Α1×Β1 + Α0×Β0

32 31

0

Α3×Β3 + Α2 ×Β2

Υνδεφινεδ
64 63

A5×Β5 + Α4 ×Β4

0

+

Α3 ×Β3 + Α2 ×Β2

A7×Β7 + Α6 ×Β6

16 15

B1

+

Α5 ×Β5 + Α4×Β4

96 95

Undefined

48 47

64 63

96 95

127

LO

B4

+

A7×Β7 + Α6 ×Β6

HI

64 63

32 31

Υνδεφινεδ

0

Α1 ×Β1 + Α0 ×Β0

Programming Notes
In the EE Core, the integer multiply operation proceeds asynchronously. An attempt to read the contents of
the LO/HI/GPR[rd] registers before the multiply operation finishes will result in interlock. Other CPU
instructions can execute without delay. Therefore, scheduling the multiply operation appropriately can
improve performance.
Even when the result of a multiply operation overflows, an overflow exception does not occur. If an
overflow is required to be detected, an explicit check is necessary.

© SCEI
-210-

SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

PHMSBH : Parallel Horizontal Multiply-Subtract Halfword
128-bit MMI
To multiply 8 pairs of 16-bit signed integers and horizontally subtract.
Operation Code
31

26

25

21

20

16

15

11

10

6

5

0

MMI
011100

rs

rt

rd

PHMSBH
10101

MMI2
001001

6

5

5

5

5

6

Format
PHMSBH rd, rs, rt
Description
(GPR[rd], HI, LO) ← GPR[rs] × GPR[rt] – GPR[rs] × GPR[rt]
Splits the 128-bit data in GPR[rs] and GPR[rt] into eight 16-bit signed integers. Multiplies the halfwords in
GPR[rs] by the corresponding halfwords in GPR[rt], then subtracts the results of adjacent multiplications
and stores them in the GPR[rd], HI and LO registers, as described in "Operation".
Exceptions
None
Operation
prod0
LO31..0
GPR[rd]31..0

← GPR[rs]31..16 × GPR[rt]31..16 – GPR[rs]15..0 × GPR[rt]15..0
← prod031..0
← prod031..0

prod1
HI31..0
GPR[rd]63..32

← GPR[rs]63..48 × GPR[rt]63..48 – GPR[rs]47..32 × GPR[rt]47..32
← prod131..0
← prod131..0

prod2
LO95..64
GPR[rd]95..64

← GPR[rs]95..80 × GPR[rt]95..80 – GPR[rs]79..64 × GPR[rt]79..64
← prod231..0
← prod231..0

prod3
HI95..64
GPR[rd]127..96

← GPR[rs]127..112 × GPR[rt]127..112 – GPR[rs]111..96 × GPR[rt]111..96
← prod331..0
← prod331..0

© SCEI
-211-

SCE CONFIDENTIAL

127

rs

112 111

A7
127

rt

EE Core Instruction Set Manual Version 6.0

96 95

A6
112 111

B7

A5
96 95

B6

127

64 63

B4

Undefined

A2
32 31

B2

16 15

0

B0

–

32 31

A3×B3 – A2×B2

64 63

0

A1×B1 – A0×B0

32 31

Undefined

64 63

A5×B5 – A4×B4

0

A0

B1

–

A7×B7 – A6×B6

16 15

A1

48 47

B3

A5×B5 – A4×B4

96 95

Undefined

32 31

64 63

96 95

127

LO

×

80 79

96 95

127

48 47

A3

–

A7×B7 – A6×B6

HI

64 63

A4

B5

–

rd

80 79

0

A3×B3 – A2×B2
32 31

Undefined

0

A1×B1 – A0×B0

Programming Notes
In the EE Core, the integer multiply operation proceeds asynchronously. An attempt to read the contents of
the LO/HI/GPR[rd] registers before the multiply operation finishes will result in interlock. Other CPU
instructions can execute without delay. Therefore, scheduling the multiply operation appropriately can
improve performance.
Even when the result of the multiply operation overflows, an overflow exception does not occur. If an
overflow is required to be detected, an explicit check is necessary.

© SCEI
-212-

SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

PINTEH : Parallel Interleave Even Halfword
128-bit MMI
To combine 2 doublewords in a halfword wide interleaved operation.
Operation Code
31

26

25

21

20

16

15

11

10

6

5

0

MMI
011100

rs

rt

rd

PINTEH
01010

MMI3
101001

6

5

5

5

5

6

Format
PINTEH rd, rs, rt
Description
GPR[rd] ← interleave(GPR[rs] , GPR[rt])
Splits the GPR[rs] and GPR[rt] into words, and stores each of the low-order halfwords in GPR[rd] in an
interleaved manner.
Exceptions
None
Operation
GPR[rd]31..0
GPR[rd]63..32
GPR[rd]95..64
GPR[rd]127..96
127

112 111

rs

96 95

80 79

A3
127

rd

112 111

A3
127

rt

← GPR[rs]15..0 || GPR[rt]15..0
← GPR[rs]47..32 || GPR[rt]47..32
← GPR[rs]79..64 || GPR[rt]79..64
← GPR[rs]111..96 || GPR[rt]111..96

B3

80 79

A2
96 95

B3

48 47

A2
96 95

112 111

64 63

16 15

A1
64 63

B2
80 79

32 31

48 47

A1
64 63

B2

A0
32 31

B1
48 47

16 15

A0
32 31

B1

0

0

B0
16 15

0

B0

© SCEI
-213-

SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

PINTH : Parallel Interleave Halfword
128-bit MMI
To combine 2 doublewords in a halfword wide interleaved operation.
Operation Code
31

26

25

21

20

16

15

11

10

6

5

0

MMI
011100

rs

rt

rd

PINTH
01010

MMI2
001001

6

5

5

5

5

6

Format
PINTH rd, rs, rt
Description
GPR[rd] ← interleave(GPR[rs] , GPR[rt])
Splits the high-order 64 bits of GPR[rs] and the low-order 64 bits of GPR[rt] into halfwords and stores them
in GPR[rd] in an interleaved manner.
Exceptions
None
Operation
GPR[rd]31..0
GPR[rd]63..32
GPR[rd]95..64
GPR[rd]127..96
127

rs

112 111

A3

127

rd

96 95

A2

112 111

A3
127

← GPR[rs]79..64 || GPR[rt]15..0
← GPR[rs]95..80 || GPR[rt]31..16
← GPR[rs]111..96 || GPR[rt]47..32
← GPR[rs]127..112 || GPR[rt]63..48
80 79

A1

96 95

B3

64 63

A0

80 79

A2

0

64 63

B2

48 47

A1
64 63

rt

-214-

B1
48 47

B3

© SCEI

32 31

16 15

A0
32 31

B2

0

B0
16 15

B1

0

B0

SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

PLZCW : Parallel Leading Zero or one Count Word
EE Core
To count leading zeros or ones.
Operation Code
31

26

25

21

20

16

15

11

10

6

5

0

MMI
011100

rs

0
00000

rd

0
00000

PLZCW
000100

6

5

5

5

5

6

Format
PLZCW rd, rs
Description
GPR[rd] ← LZC(GPR[rs]) – 1
Splits the 64-bit value in GPR[rs] into two words and counts the number of leading bits that have the same
value as the highest-order bit (either zero or one) in both words. The result minus 1 is stored in the
corresponding words in GPR[rd].
Exceptions
None
Operation
GPR[rd]31..0
GPR[rd]63..32

← LZC(GPR[rs]31..0) − 1
← LZC(GPR[rs]63..32) − 1

If GPR[1] == 0x000F:FF0F:FF0F:F00F
Then
PLZCW 1, 1
GPR[1] == 0x0000:000B:0000:0007
63

rs

32 31

0

A1

A0
Count Leading 0/1

63

rd

32 31

LZC(A1) − 1

0

LZC(A0) − 1

© SCEI
-215-

SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

PMADDH : Parallel Multiply-Add Halfword
128-bit MMI
To multiply 8 pairs of 16-bit signed integers and accumulate in parallel.
Operation Code
31

26

25

21

20

16

15

11

10

6

5

0

MMI
011100

rs

rt

rd

PMADDH
10000

MMI2
001001

6

5

5

5

5

6

Format
PMADDH rd, rs, rt
Description
(GPR[rd], HI, LO) ← (HI, LO) + GPR[rs] × GPR[rt]
Splits GPR[rs] and GPR[rt] into eight 16-bit signed integers, multiplies each halfword in GPR[rs] by the
corresponding halfword in GPR[rt], and adds the results to the corresponding words in the HI and LO
registers. The result are stored in HI, LO, and GPR[rd].
Exceptions
None. Even when the result of the arithmetic operation overflows, an exception does not occur.
Operation
prod0
LO31..0
GPR[rd]31..0

← LO31..0 + GPR[rs]15..0 × GPR[rt]15..0
← prod031..0
← prod031..0

prod1
LO63..32

← LO63..32 + GPR[rs]31..16 × GPR[rt]31..16
← prod131..0

prod2
HI31..0
GPR[rd]63..32

← HI31..0 + GPR[rs]47..32 × GPR[rt]47..32
← prod231..0
← prod231..0

prod3
HI63..32

← HI63..32 + GPR[rs]63..48 × GPR[rt]63..48
← prod331..0

prod4
LO95..64
GPR[rd]95..64

← LO95..64 + GPR[rs]79..64 × GPR[rt]79..64
← prod431..0
← prod431..0

prod5
LO127..96

← LO127..96 + GPR[rs]95..80 × GPR[rt]95..80
← prod531..0

prod6
HI95..64
GPR[rd]127..96

← HI95..64 + GPR[rs]111..96 × GPR[rt]111..96
← prod631..0
← prod631..0

© SCEI
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SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

← HI127..96 + GPR[rs]127..112 × GPR[rt]127..112
← prod731..0

prod7
HI127..96
127

rs

112 111

A7
127

rt

96 95

A6

112 111

B7

80 79

A5
96 95

B6

64 63

A4

A3

×

80 79

B5

48 47

64 63

B4

32 31

A2
48 47

B3

16 15

A1
32 31

B2

0

A0
16 15

B1

0

B0

+
127

HI

96 95

C7
127

LO

96 95

127

A7×B7 + C7

LO

64 63

127

A3×B3 + C3

A4×B4 + C4

0

A2×B2 + C2
32 31

A1×B1 + C1
64 63

A4×B4 + C4

0

C0

32 31

64 63

96 95

A6×B6 + C6

32 31

64 63

96 95

0

C2

C1

A6×B6 + C6

A5×B5 + C5

32 31

C3

C4

96 95

127

rd

C6

C5

HI

64 63

0

A0×B0 + C0
32 31

A2×B2 + C2

0

A0×B0 + C0

Programming Notes
In the EE Core, the integer multiply operation proceeds asynchronously. An attempt to read the contents of
the LO/HI/GPR[rd] registers before the multiply operation finishes will result in interlock. Other CPU
instructions can execute without delay. Therefore, scheduling the multiply operation appropriately can
improve performance.
Even when the result of the multiply operation overflows, an overflow exception does not occur. If an
overflow is required to be detected, an explicit check is necessary.

© SCEI
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SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

PMADDUW : Parallel Multiply-Add Unsigned Word
128-bit MMI
To multiply 2 pairs of 32-bit unsigned integers and accumulate in parallel.
Operation Code
31

26

25

21

20

16

15

11

10

6

5

0

MMI
011100

rs

rt

rd

PMADDUW
00000

MMI3
101001

6

5

5

5

5

6

Format
PMADDUW rd, rs, rt
Description
(GPR[rd], HI, LO) ← (HI, LO) + GPR[rs] × GPR[rt]
Multiplies bits 95..64 of GPR[rs] by bits 95..64 of GPR[rt] and bits 31..0 of GPR[rs] by bits 31..0 of GPR[rt]
as unsigned 32-bit integers and adds the resulting 64-bit values to the corresponding words in the HI and LO
registers. A part of the result is stored in GPR[rd]. See "Operation" for details.
Restrictions
If the contents of GPR[rt] and GPR[rs] are not sign-extended 32-bit values (bits 127..95 equal and bits 63..31
equal), then the result is undefined.
Exceptions
None. Even when the result of the arithmetic operation overflows, an exception does not occur.
Operation
if (NotWordValue(GPR[rs]) or NotWordValue(GPR[rt])) then UndefinedResult() endif
prod0
LO63..0
HI63..0
GPR[rd]63..0

← (HI31..0 || LO31..0) + (0 || GPR[rs]31..0) × (0 || GPR[rt]31..0)
← (prod031)32 || prod031..0
← (prod063)32 || prod063..32
← prod063..0

prod1
LO127..64
HI127..64
GPR[rd]127..64

← (HI95..64 || LO95..64) + (0 || GPR[rs]95..64) × (0 || GPR[rt]95..64)
← (prod131)32 || prod131..0
← (prod163)32 || prod163..32
← prod163..0

© SCEI
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127

EE Core Instruction Set Manual Version 6.0

96 95

rs

64 63

32 31

127

96 95

rt

´

A0
64 63

32 31

B2

127

96 95

HI

64 63

96 95

LO

32 31

32 31

C4

64 63

127

HI

0

C0

(0 || A2) ´ (0 || B2) + (C6 || C4)

rd

0

C2
64 63

127

0

+

C6
127

´
B0

+

96 95

0

(0 || A0) ´ (0 || B0) + (C2 || C0)
64 63

sign ext
127

LO

0

A2

32 31

0

32 31

0

sign ext
96 95

64 63

sign ext

sign ext

Programming Notes
In the EE Core, the integer multiply operation proceeds asynchronously. An attempt to read the contents of
the LO/HI/GPR[rd] registers before the multiply operation finishes will result in interlock. Other CPU
instructions can execute without delay. Therefore, scheduling the multiply operation appropriately can
improve performance.
Even when the result of the multiply operation overflows, an overflow exception does not occur. If an
overflow is required to be detected, an explicit check is necessary.

© SCEI
-219-

SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

PMADDW : Parallel Multiply-Add Word
128-bit MMI
To multiply 2 pairs of 32-bit signed integers and accumulate in parallel.
Operation Code
31

26

25

21

20

16

15

11

10

6

5

0

MMI
011100

rs

rt

rd

PMADDW
00000

MMI2
001001

6

5

5

5

5

6

Format
PMADDW rd, rs, rt
Description
(GPR[rd], HI, LO) ← (HI, LO) + GPR[rs] × GPR[rt]
Multiplies bits 95..64 of GPR[rs] by bits 95..64 of GPR[rt] and bits 31..0 of GPR[rs] by bits 31..0 of GPR[rt]
as signed 32-bit integers and adds the resulting 64-bit value to the corresponding word positions in the HI
and LO registers. A part of the result is stored in GPR[rd]. See "Operation" for details.
Restrictions
If the contents of GPR[rt] and GPR[rs] are not sign-extended 32-bit values (bits 127..95 equal and bits 63..31
equal), then the result is undefined.
Exceptions
None
Operation
if (NotWordValue(GPR[rs]) or NotWordValue(GPR[rt])) then UndefinedResult() endif
prod0
LO63..0
HI63..0
GPR[rd]63..0

← (HI31..0 || LO31..0) + GPR[rs]31..0 × GPR[rt]31..0
← (prod031)32 || prod031..0
← (prod063)32 || prod063..32
← prod063..0

prod1
LO127..64
HI127..64
GPR[rd]127..64

← (HI95..64 || LO95..64) + GPR[rs]95..64 × GPR[rt]95..64
← (prod131)32 || prod131..0
← (prod163)32 || prod163..32
← prod163..0

© SCEI
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127

EE Core Instruction Set Manual Version 6.0

96 95

rs

64 63

32 31

A2
127

96 95

rt

×

64 63

32 31

B2

96 95

HI
96 95

LO

64 63

32 31

HI

96 95

0

A0 × B0 + (C2 || C0)
64 63

sign ext
127

0

C0

64 63

127

0

C2

A2 × B2 + (C6 || C4)

rd

LO

32 31

C4

127

0

+
64 63

C6
127

×
B0

+
127

0

A0

32 31

0

32 31

0

sign ext
96 95

64 63

sign ext

sign ext

Programming Notes
In the EE Core, the integer multiply operation proceeds asynchronously. An attempt to read the contents of
the LO/HI/GPR[rd] registers before the multiply operation finishes will result in interlock. Other CPU
instructions can execute without delay. Therefore, scheduling the multiply operation appropriately can
improve performance.
Even when the result of the multiply operation overflows, an overflow exception does not occur. If an
overflow is required to be detected, an explicit check is necessary.

© SCEI
-221-

SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

PMAXH : Parallel Maximize Halfword
128-bit MMI
To compare 16-bit signed integers and calculate the maximum value (8 parallel operations).
Operation Code
31

26

25

21

20

16

15

11

10

6

5

0

MMI
011100

rs

rt

rd

PMAXH
00111

MMI0
001000

6

5

5

5

5

6

Format
PMAXH rd, rs, rt
Description
GPR[rd] ← max(GPR[rs], GPR[rt])
Splits the 128-bit value in GPR[rs] and GPR[rt] into eight 16-bit signed integers and compares the data in
GPR[rs] with the corresponding data in GPR[rt] and stores the maximum value in the corresponding
halfwords in GPR[rd].
Exceptions
None
Operation
if ((GPR[rs]15..0 > GPR[rt]15..0) then
← GPR[rs]15..0
GPR[rd]15..0
else
← GPR[rt]15..0
GPR[rd]15..0
endif
if ((GPR[rs]31..16 > GPR[rt]31..16) then
← GPR[rs]31..16
GPR[rd]31..16
else
← GPR[rt]31..16
GPR[rd]31..16
endif
(The same operations follow every 16 bits)
if ((GPR[rs]127..112 > GPR[rt]127..112) then
← GPR[rs]127..112
GPR[rd]127..112
else
← GPR[rt]127..112
GPR[rd]127..112
endif

© SCEI
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SCE CONFIDENTIAL

127

rs

112 111

A7
127

rt

rd

96 95

A6
112 111

B7

127

EE Core Instruction Set Manual Version 6.0

112 111

80 79

A5
96 95

B6

A4
80 79

B5

96 95

64 63

A3
64 63

B4

80 79

48 47

A2
48 47

B3

64 63

32 31

A1
32 31

B2

48 47

16 15

A0
16 15

B1

32 31

0

0

B0

16 15

0

max(A7,B7) max(A6,B6) max(A5,B5) max(A4,B4) max(A3,B3) max(A2,B2) max(A1,B1) max(A0,B0)

© SCEI
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SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

PMAXW : Parallel Maximize Word
128-bit MMI
To compare 32-bit signed integers and calculate the maximum value (4 parallel operations).
Operation Code
31

26

25

21

20

16

15

11

10

6

5

0

MMI
011100

rs

rt

rd

PMAXW
00011

MMI0
001000

6

5

5

5

5

6

Format
PMAXW rd, rs, rt
Description
GPR[rd] ← max(GPR[rs], GPR[rt])
Splits the 128-bit value in GPR[rs] and GPR[rt] into four 32-bit signed integers and compares the data in
GPR[rs] with the corresponding data in GPR[rt] and stores the maximum value in the corresponding words
in GPR[rd].
Exceptions
None
Operation
if ((GPR[rs]31..0 > GPR[rt]31..0) then
← GPR[rs]31..0
GPR[rd]31..0
else
← GPR[rt]31..0
GPR[rd]31..0
endif
if ((GPR[rs]63..32 > GPR[rt]63..32) then
← GPR[rs]63..32
GPR[rd]63..32
else
← GPR[rt]63..32
GPR[rd]63..32
endif
if ((GPR[rs]95..64 > GPR[rt]95..64) then
← GPR[rs]95..64
GPR[rd]95..64
else
← GPR[rt]95..64
GPR[rd]95..64
endif
if ((GPR[rs]127..96 > GPR[rt]127..96) then
← GPR[rs]127..96
GPR[rd]127..96
else
GPR[rd]127..96
← GPR[rt]127..96
endif

© SCEI
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SCE CONFIDENTIAL

127

rs

96 95

A3
127

rt

64 63

A2
96 95

B3
127

rd

EE Core Instruction Set Manual Version 6.0

A1
64 63

B2
96 95

max(A3,B3)

32 31

A0
32 31

B1
64 63

max(A2,B2)

0

0

B0
32 31

max(A1,B1)

0

max(A0,B0)

© SCEI
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SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

PMFHI : Parallel Move From HI Register
128-bit MMI
To copy the 128-bit value in the HI register to a GPR.
Operation Code
31

26

25

16

15

11

10

6

5

0

MMI
011100

0
00 0000 0000

rd

PMFHI
01000

MMI2
001001

6

10

5

5

6

Format
PMFHI rd
Description
GPR[rd] ← HI
Stores the 128-bit value in the HI register into GPR[rd].
Exceptions
None
Operation
GPR[rd]127..0 ← HI127..0

© SCEI
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SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

PMFHL.LH : Parallel Move From HI/LO Register
128-bit MMI
To copy the contents of the HI and LO registers to a GPR in halfword units.
Operation Code
31

26

25

16

15

11

10

6

5

0

MMI
011100

0
00 0000 0000

rd

fmt
00011

PMFHL
110000

6

10

5

5

6

Format
PMFHL.LH rd
Description
GPR[rd] ← HI / LO
Splits the contents of the HI and LO registers into halfwords, rearranges them as shown in "Operation", and
stores them in GPR[rd].
Exceptions
None
Operation
GPR[rd]15..0
GPR[rd]31..16
GPR[rd]47..32
GPR[rd]63..48
GPR[rd]79..64
GPR[rd]95..80
GPR[rd]111..96
GPR[rd]127..112
127

← LO15..0
← LO47..32
← HI15..0
← HI47..32
← LO79..64
← LO111..96
← HI79..64
← HI111..96

112 111

HI

96 95

80 79

A3

127

rd

112 111

A3
127

LO

A2

80 79

B3
96 95

B3

48 47

A2

96 95

112 111

64 63

16 15

A1

64 63

B2
80 79

32 31

48 47

A1
64 63

B2

A0

32 31

A0
48 47

16 15

B1
32 31

B1

0

0

B0
16 15

0

B0

© SCEI
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SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

PMFHL.LW : Parallel Move From HI/LO Register
128-bit MMI
To copy the contents of the HI and LO registers to a GPR in word units.
Operation Code
31

26

25

16

15

11

10

6

5

0

MMI
011100

0
00 0000 0000

rd

fmt
00000

PMFHL
110000

6

10

5

5

6

Format
PMFHL.LW rd
Description
GPR[rd] ← HI / LO
Splits the contents of the HI and LO registers into words, rearranges them as shown in "Operation", and
stores them in GPR[rd].
Exceptions
None
Operation
GPR[rd]31..0
GPR[rd]63..32
GPR[rd]95..64
GPR[rd]127..96
127

← LO31..0
← HI31..0
← LO95..64
← HI95..64
96 95

HI

64 63

32 31

A1
127

rd

96 95

A1
127

LO

A0
64 63

B1
96 95

0

32 31

A0
64 63

B1

0

B0
32 31

0

B0

© SCEI
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SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

PMFHL.SH : Parallel Move From HI/LO Register
128-bit MMI
To saturate the contents of HI/LO register to signed halfwords and copy to a GPR.
Operation Code
31

26

25

16

15

11

10

6

5

0

MMI
011100

0
00 0000 0000

rd

fmt
00100

PMFHL
110000

6

10

5

5

6

Format
PMFHL.SH rd
Description
GPR[rd] ← HI / LO
Splits the contents of HI/LO registers into words, saturates them to 16-bit signed integers, rearranges them
as shown in "Operation", and stores them in GPR[rd].
Exceptions
None
Operation
GPR[rd]15..0
GPR[rd]31..16
GPR[rd]47..32
GPR[rd]63..48
GPR[rd]79..64
GPR[rd]95..80
GPR[rd]111..96
GPR[rd]127..112

← clamp(LO31..0)
← clamp(LO63..32)
← clamp(HI31..0)
← clamp(HI63..32)
← clamp(LO95..64)
← clamp(LO127..96)
← clamp(HI95..64)
← clamp(HI127..96)

clamp(X)
begin
if (X > 0x00007FFF) then
clamp := 0x7FFF
else if (X < 0xFFFF8000) then
clamp := 0x8000
else
clamp := X
endif
end

© SCEI
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SCE CONFIDENTIAL

127

EE Core Instruction Set Manual Version 6.0

96 95

HI

64 63

A3

32 31

A2

0

A1

A0

Saturate to signed Halfword
127

rd

112 111

A3

96 95

A2

80 79

B3

64 63

B2

48 47

A1

32 31

A0

16 15

B1

0

B0

Saturate to signed Halfword
127

LO

96 95

B3

64 63

B2

32 31

B1

© SCEI
-230-

0

B0

SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

PMFHL.SLW : Parallel Move From HI/LO Register
128-bit MMI
To copy the contents of HI/LO register to a GPR in word units.
Operation Code
31

26

25

16

15

11

10

6

5

0

MMI
011100

0
00 0000 0000

rd

fmt
00010

PMFHL
110000

6

10

5

5

6

Format
PMFHL.SLW rd
Description
GPR[rd] ← HI / LO
Splits the contents of the HI and LO registers into word data and combines them. Then saturates to 32-bit
signed integers and stores them in GPR[rd].
Exceptions
None
Operation
if ( (HI31..0 || LO31..0) >= 0x000000007FFFFFFF ) then
← 0x000000007FFFFFFF
GPR[rd]63..0
else if ( (HI31..0 || LO31..0) <= 0xFFFFFFFF80000000 ) then
← 0xFFFFFFFF80000000
GPR[rd]63..0
else
← (LO31)32 || LO31..0
GPR[rd]63..0
endif
if ( (HI95..64 || LO95..64) >= 0x000000007FFFFFFF ) then
← 0x000000007FFFFFFF
GPR[rd]127.. 64
else if ( (HI95..64 || LO95..64) <= 0xFFFFFFFF80000000 ) then
← 0xFFFFFFFF80000000
GPR[rd]127.. 64
else
← (LO95)32 || LO95..64
GPR[rd]127.. 64
endif

© SCEI
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SCE CONFIDENTIAL

127

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96 95

64 63

HI

127

32 31

A1

A0

||

||

96 95

64 63

LO

0

32 31

0

B1

B0
Clamp to Signed Word

127

rd

96 95

sign ext

64 63

clamp(A1 || B1)

32 31

sign ext

0

clamp(A0 || B0)

Saturation
FFFFFFFFFFFFFFFF

7FFFFFFFFFFFFFFF

FFFFFFFF80000000
Values in this area are
clamped to 80000000.

0

000000007FFFFFFF

↓

Values in this area are
clamped to 7FFFFFFF.

80000000 Values in this area do not 7FFFFFFF
change.

© SCEI
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SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

PMFHL.UW : Parallel Move From HI/LO Register
128-bit MMI
To copy the contents of the HI/LO registers to a GPR in word units.
Operation Code
31

26

25

16

15

11

10

6

5

0

MMI
011100

0
00 0000 0000

rd

fmt
00001

PMFHL
110000

6

10

5

5

6

Format
PMFHL.UW rd
Description
GPR[rd] ← HI / LO
Splits the contents of HI/LO registers into word data, rearranges them as shown in "Operation", and stores
them in GPR[rd].
Exceptions
None
Operation
GPR[rd]31..0
GPR[rd]63..32
GPR[rd]95..64
GPR[rd]127..96
127

HI

96 95

64 63

A1
127

rd

32 31

0

32 31

0

A0
96 95

A1
127

LO

← LO63..32
← HI63..32
← LO127..96
← HI127..96

64 63

B1
96 95

A0
64 63

B1

B0
32 31

0

B0

© SCEI
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SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

PMFLO : Parallel Move From LO Register
128-bit MMI
To copy the 128-bit value in the LO register to a GPR.
Operation Code
31

26

25

16

15

11

10

6

5

0

MMI
011100

0
00 0000 0000

rd

PMFLO
01001

MMI2
001001

6

10

5

5

6

Format
PMFLO rd
Description
GPR[rd] ← LO
Stores the 128-bit value in the LO register into GPR[rd].
Exceptions
None
Operation
GPR[rd]127..0 ← LO127..0

© SCEI
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SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

PMINH : Parallel Minimize Halfword
128-bit MMI
To compare 16-bit signed integers and calculate minimum value (8 parallel operations).
Operation Code
31

26

25

21

20

16

15

11

10

6

5

0

MMI
011100

rs

rt

rd

PMINH
00111

MMI1
101000

6

5

5

5

5

6

Format
PMINH rd, rs, rt
Description
GPR[rd] ← min(GPR[rs], GPR[rt])
Splits the 128-bit value in GPR[rs] and GPR[rt] into eight 16-bit signed integers, compares the data in
GPR[rs] with the corresponding data in GPR[rt], and stores the minimum value in the corresponding
halfwords in GPR[rd].
Exceptions
None
Operation
if ((GPR[rs]15..0 > GPR[rt]15..0) then
← GPR[rt]15..0
GPR[rd]15..0
else
← GPR[rs]15..0
GPR[rd]15..0
endif
if ((GPR[rs]31..16 > GPR[rt]31..16) then
← GPR[rt]31..16
GPR[rd]31..16
else
← GPR[rs]31..16
GPR[rd]31..16
endif
(The same operations follow every 16 bits)
if ((GPR[rs]127..112 > GPR[rt]127..112) then
← GPR[rt]127..112
GPR[rd]127..112
else
← GPR[rs]127..112
GPR[rd]127..112
endif

© SCEI
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SCE CONFIDENTIAL

127

rs

112 111

A7
127

rt

96 95

A6
112 111

B7

127

EE Core Instruction Set Manual Version 6.0

112 111

80 79

A5
96 95

B6

A4
80 79

B5

96 95

64 63

A3
64 63

B4

80 79

48 47

A2
48 47

B3

64 63

32 31

A1
32 31

B2

48 47

16 15

A0
16 15

B1

32 31

0

0

B0

16 15

0

rd min(A7,B7) min(A6,B6) min(A5,B5) min(A4,B4) min(A3,B3) min(A2,B2) min(A1,B1) min(A0,B0)

© SCEI
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SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

PMINW : Parallel Minimize Word
128-bit MMI
To compare 32-bit signed integers and calculate minimum value (4 parallel operations).
Operation Code
31

26

25

21

20

16

15

11

10

6

5

0

MMI
011100

rs

rt

rd

PMINW
00011

MMI1
101000

6

5

5

5

5

6

Format
PMINW rd, rs, rt
Description
GPR[rd] ← min(GPR[rs], GPR[rt])
Splits the 128-bit value in GPR[rs] and GPR[rt] into four 32-bit signed integers and compares the data in
GPR[rs] with the corresponding data in GPR[rt] and stores the minimum value in the corresponding words
in GPR[rd].
Exceptions
None
Operation
if ((GPR[rs]31..0 > GPR[rt]31..0) then
← GPR[rt]31..0
GPR[rd]31..0
else
← GPR[rs]31..0
GPR[rd]31..0
endif
if ((GPR[rs]63..32 > GPR[rt]63..32) then
← GPR[rt]63..32
GPR[rd]63..32
else
← GPR[rs]63..32
GPR[rd]63..32
endif
if ((GPR[rs]95..64 > GPR[rt]95..64) then
← GPR[rt]95..64
GPR[rd]95..64
else
← GPR[rs]95..64
GPR[rd]95..64
endif
if ((GPR[rs]127..96 > GPR[rt]127..96) then
← GPR[rt]127..96
GPR[rd]127..96
else
GPR[rd]127..96
← GPR[rs]127..96
endif

© SCEI
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SCE CONFIDENTIAL

127

rs

EE Core Instruction Set Manual Version 6.0

96 95

A3
127

rt

96 95

B3

127

rd

64 63

A2
64 63

B2

96 95

min(A3,B3)

32 31

A1
32 31

B1

64 63

min(A2,B2)

-238-

0

B0

32 31

min(A1,B1)

© SCEI

0

A0

0

min(A0,B0)

SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

PMSUBH : Parallel Multiply-Subtract Halfword
128-bit MMI
To multiply 8 pairs of 16-bit signed integers and subtract in parallel.
Operation Code
31

26

25

21

20

16

15

11

10

6

5

0

MMI
011100

rs

rt

rd

PMSUBH
10100

MMI2
001001

6

5

5

5

5

6

Format
PMSUBH rd, rs, rt
Description
(GPR[rd], HI, LO) ← (HI, LO) – GPR[rs] × GPR[rt]
Splits GPR[rs] and GPR[rt] into eight 16-bit signed integers and multiplies each halfword in GPR[rs] by the
corresponding halfword in GPR[rt] and subtracts the resulting 32-bit value from the corresponding word in
the HI/LO registers. The results of the subtraction are written back to HI/LO registers and a part of them
are stored in GPR[rd].
Exceptions
None. Even when the result of the arithmetic operation overflows, an exception does not occur.
Operation
prod0
LO31..0
GPR[rd]31..0

← LO31..0 – GPR[rs]15..0 × GPR[rt]15..0
← prod031..0
← prod031..0

prod1
LO63..32

← LO63..32 – GPR[rs]31..16 × GPR[rt]31..16
← prod131..0

prod2
HI31..0
GPR[rd]63..32

← HI31..0 – GPR[rs]47..32 × GPR[rt]47..32
← prod231..0
← prod231..0

prod3
HI63..32

← HI63..32 – GPR[rs]63..48 × GPR[rt]63..48
← prod331..0

prod4
LO95..64
GPR[rd]95..64

← LO95..64 – GPR[rs]79..64 × GPR[rt]79..64
← prod431..0
← prod431..0

prod5
LO127..96

← LO127..96 – GPR[rs]95..80 × GPR[rt]95..80
← prod531..0

prod6
HI95..64
GPR[rd]127..96

← HI95..64 – GPR[rs]111..96 × GPR[rt]111..96
← prod631..0
← prod631..0
© SCEI
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SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

← HI127..96 – GPR[rs]127..112 × GPR[rt]127..112
← prod731..0

prod7
HI127..96
127

96 95

HI

64 63

C7

C6

127

C2

64 63

C5

0

C3

96 95

LO

32 31
32 31

C4

0

C1

C0

–
127

rs

112 111

A7

96 95

A6

80 79

A5

64 63

A4

48 47

A3

32 31

A2

16 15

A1

0

A0

×
127

rt

112 111

B7

96 95

B6

127

HI

64 63

B4

96 95

127

32 31

B2

B1

C3–A3×B3

C4–A4×B4

0

B0

0

C2–A2×B2
32 31

C1–A1×B1
64 63

C4–A4×B4

16 15

32 31

64 63

96 95

C6–A6×B6

B3

C6–A6×B6

C5–A5×B5

48 47

64 63

96 95

127

rd

B5

C7–A7×B7

LO

80 79

0

C0–A0×B0
32 31

C2–A2×B2

0

C0–A0×B0

Programming Notes
In the EE Core, the integer multiply operation proceeds asynchronously. An attempt to read the contents of
the LO/HI/GPR[rd] registers before the multiply operation finishes will result in interlock. Other CPU
instructions can execute without delay. Therefore, scheduling the multiply operation appropriately can
improve performance.
Even when the result of the multiply operation overflows, an overflow exception does not occur. If an
overflow is required to be detected, an explicit check is necessary.

© SCEI
-240-

SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

PMSUBW : Parallel Multiply-Subtract Word
128-bit MMI
To multiply 2 pairs of 32-bit signed integers and subtract in parallel.
Operation Code
31

26

25

21

20

16

15

11

10

6

5

0

MMI
011100

rs

rt

rd

PMSUBW
00100

MMI2
001001

6

5

5

5

5

6

Format
PMSUBW rd, rs, rt
Description
(GPR[rd], HI, LO) ← (HI, LO) – GPR[rs] × GPR[rt]
Multiplies bits 95..64 of GPR[rs] by bits 95..64 of GPR[rt] and bits 31..0 of GPR[rs] by bits 31..0 of GPR[rt]
as signed 32-bit integers and subtracts the resulting 64-bit value from the value that combines the
corresponding word data in the HI and LO registers. A part of the result of subtraction is stored in GPR[rd].
See "Operation" for details.
Restrictions
If the contents of GPR[rt] and GPR[rs] are not sign-extended 32-bit values (bits 127..95 equal and bits 63..31
equal), then the result is undefined.
Exceptions
None. Even when the result of the arithmetic operation overflows, an exception does not occur.
Operation
if (NotWordValue(GPR[rs]) or NotWordValue(GPR[rt])) then UndefinedResult() endif
prod0
LO63..0
HI63..0
GPR[rd]63..0

← (HI31..0 || LO31..0) − GPR[rs]31..0 × GPR[rt]31..0
← (prod031)32 || prod031..0
← (prod063)32 || prod063..32
← prod063..0

prod1
LO127..64
HI127..64
GPR[rd]127..64

← (HI95..64 || LO95..64) − GPR[rs]95..64 × GPR[rt]95..64
← (prod131)32 || prod131..0
← (prod163)32 || prod163..32
← prod163..0

© SCEI
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64 63

96 95

HI

32 31

C6
127

96 95

LO

0

C2
64 63

32 31

C4

0

C0

–
127

96 95

rs

64 63

32 31

A2
127

rt

A0

×

96 95

64 63

32 31

B2

127

127

64 63

96 95

127

LO

96 95

0

(C2 || C0) − A0 × B0

64 63

← sign extend

HI

0

B0

(C6 || C4) − A2 × B2

rd

0

32 31

0

32 31

0

← sign extend
64 63

← sign extend

← sign extend

Programming Notes
In the EE Core, the integer multiply operation proceeds asynchronously. An attempt to read the contents of
the LO/HI/GPR[rd] registers before the multiply operation finishes will result in interlock. Other CPU
instructions can execute without delay. Therefore, scheduling the multiply operation appropriately can
improve performance.
Even when the result of the multiply operation overflows, an overflow exception does not occur. If an
overflow is required to be detected, an explicit check is necessary.

© SCEI
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SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

PMTHI : Parallel Move To HI Register
128-bit MMI
To copy the value of a GPR to the HI register.
Operation Code
31

26

25

21

20

11

10

6

5

0

MMI
011100

rs

0
00 0000 0000

PMTHI
01000

MMI3
101001

6

5

10

5

6

Format
PMTHI rs
Description
HI ← GPR[rs]
To store the contents of GPR[rs] in the HI register.
Exceptions
None
Operation
HI127..0 ← GPR[rs]127..0

© SCEI
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SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

PMTHL.LW : Parallel Move To HI/LO Register
128-bit MMI
To copy the value of a GPR to the HI/LO registers in word units.
Operation Code
31

26

25

21

20

11

10

6

5

0

MMI
011100

rs

0
00 0000 0000

fmt
00000

PMTHL
110001

6

5

10

5

6

Format
PMTHL.LW rs
Description
HI / LO ← GPR[rs]
Splits the 128-bit value in GPR[rs] into four words and stores them in the HI and LO registers, as shown in
"Operation".
Exceptions
None
Operation
LO31..0
LO63..32
HI31..0
HI63..32
LO95..64
LO127..96
HI95..64
HI127..96

← GPR[rs]31..0
← LO63..32
← GPR[rs]63..32
← HI63..32
← GPR[rs]95..64
← LO127..96
← GPR[rs]127..96
← HI127..96

127

rs

96 95

A3

127

A2

96 95

HI

( not changed )
127

LO

64 63

( not changed )

32 31

A1

64 63

A3
96 95

A0

32 31

( not changed )
64 63

A2

-244-

0

A1
32 31

( not changed )

© SCEI

0

0

A0

SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

PMTLO : Parallel Move To LO Register
128-bit MMI
To copy the value of a GPR to LO register.
Operation Code
31

26

25

21

20

11

10

6

5

0

MMI
011100

rs

0
00 0000 0000

PMTLO
01001

MMI3
101001

6

5

10

5

6

Format
PMTLO rs
Description
LO ← GPR[rs]
Stores the contents of GPR[rs] in the LO register.
Exceptions
None
Operation
LO127..0 ← GPR[rs]127..0

© SCEI
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SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

PMULTH : Parallel Multiply Halfword
128-bit MMI
To multiply 8 pairs of 16-bit signed integers in parallel.
Operation Code
31

26

25

21

20

16

15

11

10

6

5

0

MMI
011100

rs

rt

rd

PMULTH
11100

MMI2
001001

6

5

5

5

5

6

Format
PMULTH rd, rs, rt
Description
(GPR[rd], LO, HI) ← GPR[rs] × GPR[rt]
Splits the 128-bit value in GPR[rs] and GPR[rt] into eight 16-bit signed integers and multiplies the data in
GPR[rs] by the corresponding data in GPR[rt] and stores the resulting 32-bit signed integers into the HI/LO
registers and GPR[rd], as shown in "Operation".
Exceptions
None
Operation
prod0
LO31..0
GPR[rd]31..0

← GPR[rs]15..0 × GPR[rt]15..0
← prod031..0
← prod031..0

prod1
LO63..32

← GPR[rs]31..16 × GPR[rt]31..16
← prod131..0

prod2
HI31..0
GPR[rd]63..32

← GPR[rs]47..32 × GPR[rt]47..32
← prod231..0
← prod231..0

prod3
HI63..32

← GPR[rs]63..48 × GPR[rt]63..48
← prod331..0

prod4
LO95..64
GPR[rd]95..64

← GPR[rs]79..64 × GPR[rt]79..64
← prod431..0
← prod431..0

prod5
LO127..96

← GPR[rs]95..80 × GPR[rt]95..80
← prod531..0

prod6
HI95..64
GPR[rd]127..96

← GPR[rs]111..96 × GPR[rt]111..96
← prod631..0
← prod631..0

prod7
HI127..96

← GPR[rs]127..112 × GPR[rt]127..112
← prod731..0

© SCEI
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SCE CONFIDENTIAL

127

rs

112 111

A7

EE Core Instruction Set Manual Version 6.0

96 95

A6

80 79

A5

64 63

A4

48 47

A3

32 31

A2

16 15

A1

0

A0

×
127

rt

112 111

B7

B6

127

rd

B5

A6×B6

HI

80 79

32 31

B2

B1

A2×B2

A6×B6

B0

0

32 31

64 63

0

A2×B2
32 31

A1×B1

0

A0×B0

A3×B3

A4×B4

16 15

32 31

64 63

96 95

A5×B5

B3

A4×B4

A7×B7

48 47

64 63

96 95

127

64 63

B4

96 95

127

LO

96 95

0

A0×B0

Programming Notes
In the EE Core, the integer multiply operation proceeds asynchronously. An attempt to read the contents of
the LO/HI/GPR[rd] registers before the multiply operation finishes will result in interlock. Other CPU
instructions can execute without delay. Therefore, scheduling the multiply operation appropriately can
improve performance.

© SCEI
-247-

SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

PMULTUW : Parallel Multiply Unsigned Word
128-bit MMI
To multiply 2 pairs of 32-bit unsigned integers in parallel.
Operation Code
31

26

25

21

20

16

15

11

10

6

5

0

MMI
011100

rs

rt

rd

PMULTUW
01100

MMI3
101001

6

5

5

5

5

6

Format
PMULTUW rd, rs, rt
Description
Multiplies bits 95-64 of GPR[rs] by bits 95-64 of GPR[rt] and bits 31-0 of GPR[rs] by bits 31-0 of GPR[rt] as
unsigned 32-bit integers. The resulting 64-bit value is stored in GPR[rd] and also in the corresponding words
in the HI and LO registers, as shown in "Operation".
Restrictions
If the contents of GPR[rt] and GPR[rs] are not sign-extended 32-bit values (bits 127-95 equal and bits 63-31
equal), then the result is undefined.
Exceptions
None
Operation
if (NotWordValue(GPR[rs]) or NotWordValue(GPR[rt])) then UndefinedResult() endif
prod0
LO63..0
HI63..0
GPR[rd]63..0

← (0 || GPR[rs]31..0) × (0 || GPR[rt]31..0)
← (prod031)32 || prod031..0
← (prod063)32 || prod063..32
← prod063..0

prod1
LO127..64
HI127..64
GPR[rd]127..64

← (0 || GPR[rs]95..64) × (0 || GPR[rt]95..64)
← (prod131)32 || prod131..0
← (prod163)32 || prod163..32
← prod163..0

© SCEI
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SCE CONFIDENTIAL

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EE Core Instruction Set Manual Version 6.0

96 95

rs
127

96 95

rt

32 31

×

64 63

32 31

64 63

127

96 95

127

0

0

(0 || A0) × (0 || B0)
64 63

← sign ext

HI

×
B0

(0 || A2) × (0 || B2)

rd

0

A0

B2

127

LO

64 63

A2

32 31

0

32 31

0

← sign ext
96 95

64 63

← sign ext

← sign ext

Programming Notes
In the EE Core, the integer multiply operation proceeds asynchronously. An attempt to read the contents of
the LO/HI/GPR[rd] registers before the multiply operation finishes will result in interlock. Other CPU
instructions can execute without delay. Therefore, scheduling the multiply operation appropriately can
improve performance.

© SCEI
-249-

SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

PMULTW : Parallel Multiply Word
128-bit MMI
To multiply 2 pairs of 32-bit signed integers in parallel.
Operation Code
31

26

25

21

20

16

15

11

10

6

5

0

MMI
011100

rs

rt

rd

PMULTW
01100

MMI2
001001

6

5

5

5

5

6

Format
PMULTW rd, rs, rt
Description
Multiplies bits 95-.64 of GPR[rs] by bits 95-64 of GPR[rt] and bits 31-0 of GPR[rs] by bits 31-0 of GPR[rt]
as signed 32-bit integers and the resulting 64-bit value is stored into GPR[rd] and the corresponding words in
the HI and LO registers, as shown in "Operation".
Restrictions
If the contents of GPR[rt] and GPR[rs] are not sign-extended 32-bit values (bits 127..95 equal and bits 63..31
equal), then the result is undefined.
Exceptions
None
Operation
if (NotWordValue(GPR[rs]) or NotWordValue(GPR[rt])) then UndefinedResult() endif
prod0
LO63..0
HI63..0
GPR[rd]63..0

← GPR[rs]31..0 × GPR[rt]31..0
← (prod031)32 || prod031..0
← (prod063)32 || prod063..32
← prod063..0

prod1
LO127..64
HI127..64
GPR[rd]127..64

← GPR[rs]95..64 × GPR[rt]95..64
← (prod131)32 || prod131..0
← (prod163)32 || prod163..32
← prod163..0

© SCEI
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SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

127

96 95

rs

64 63

32 31

A2
127

96 95

rt

64 63

32 31

B2

127

64 63

127

96 95

127

0

0

A0 × B0
64 63

← sign ext

HI

×
B0

A2 × B2

rd

LO

×

0

A0

32 31

0

32 31

0

← sign ext
96 95

64 63

← sign ext

← sign ext

Programming Notes
In the EE Core, the integer multiply operation proceeds asynchronously. An attempt to read the contents of
the LO/HI/GPR[rd] registers before the multiply operation finishes will result in interlock. Other CPU
instructions can execute without delay. Therefore, scheduling the multiply operation appropriately can
improve performance.

© SCEI
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SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

PNOR : Parallel Not Or
128-bit MMI
To calculate a bitwise logical NOT OR.
Operation Code
31

26

25

21

20

16

15

11

10

6

5

0

MMI
011100

rs

rt

rd

PNOR
10011

MMI3
101001

6

5

5

5

5

6

Format
PNOR rd, rs, rt
Description
GPR[rd] ← GPR[rs] NOR GPR[rt]
Calculates a bitwise logical NOR between the contents of GPR[rs] and GPR[rt]. The result is stored in
GPR[rd].
The truth table values for NOR are as follows:
X
0
0
1
1

Y
0
1
0
1

X NOR Y
1
0
0
0

Exceptions
None
Operation
GPR[rd]127..0 ← GPR[rs]127..0 NOR GPR[rt]127..0

© SCEI
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SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

POR : Parallel Or
128-bit MMI
To calculate a bitwise logical OR.
Operation Code
31

26

25

21

20

16

15

11

10

6

5

0

MMI
011100

rs

rt

rd

POR
10010

MMI3
101001

6

5

5

5

5

6

Format
POR rd, rs, rt
Description
GPR[rd] ← GPR[rs] OR GPR[rt]
Calculates a bitwise logical OR between the contents of GPR[rs] and GPR[rt]. The result is stored into
GPR[rd].
The truth table values for OR are as follows:
X
0
0
1
1

Y
0
1
0
1

X OR Y
0
1
1
1

Exceptions
None
Operation
GPR[rd]127..0 ← GPR[rs]127..0 OR GPR[rt]127..0

© SCEI
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SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

PPAC5 : Parallel Pack to 5 bits
128-bit MMI
To pack 4 words in the 8-8-8-8 bit format into 4 halfwords in the 1-5-5-5 bit format.
Operation Code
31

26

25

21

20

16

15

11

10

6

5

0

MMI
011100

0
00000

rt

rd

PPAC5
11111

MMI0
001000

6

5

5

5

5

6

Format
PPAC5 rd, rt
Description
GPR[rd] ← pack(GPR[rt])
Splits the 128-bit data in GPR[rt] into four words in the 8-8-8-8 bit format. Each of the low-order bits are
truncated and packed into four halfwords in the 1-5-5-5 bit format. The result is stored in GPR[rd].
Exceptions
None
Operation
GPR[rd]15..0
GPR[rd]31..16

← GPR[rt]31 || GPR[rt]23..19 || GPR[rt]15..11 || GPR[rt]7..3
← 016

GPR[rd]47..32
GPR[rd]63..48

← GPR[rt]63 || GPR[rt]55..51 || GPR[rt]47..43 || GPR[rt]39..35
← 016

GPR[rd]79..64
GPR[rd]95..80

← GPR[rt]95 || GPR[rt]87..83 || GPR[rt]79..75 || GPR[rt]71..67
← 016

GPR[rd]111..96
GPR[rd]127..112

← GPR[rt]127 || GPR[rt]119..115 || GPR[rt]111..107 || GPR[rt]103..99
← 016

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96 95

64 63

32 31

0

rt
127

112 111

96 95

80 79

64 63

48 47

32 31

16 15

0

rd

8bit
31

rt

30

A3

19 18

16 15

A2

31

rd

8bit

8bit
24 23

0

8 7

A1

16 15
16

8bit

11 10

3 2

0

A0

14

10 9

5 4

0

A3

A2

A1

A0

1bit

5bit

5bit

5bit

© SCEI
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SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

PPACB : Parallel Pack to Byte
128-bit MMI
To pack the data in two GPRs into consecutive bytes.
Operation Code
31

26

25

21

20

16

15

11

10

6

5

0

MMI
011100

rs

rt

rd

PPACB
11011

MMI0
001000

6

5

5

5

5

6

Format
PPACB rd, rs, rt
Description
GPR[rd] ← pack(GPR[rs] , GPR[rt])
Splits the 128-bit data in GPR[rs] into eight halfwords, takes the low-order bytes of each of the halfwords
and stores them in the high-order 64 bits of GPR[rd]. Likewise, takes the low-order bytes of each of the
halfwords of GPR[rt] and stores them in the low-order 64 bits of GPR[rd].
Exceptions
None
Operation
GPR[rd]7..0
GPR[rd]15..8

← GPR[rt]7..0
← GPR[rt]23..16

(The same operations follow every 8 bits)
GPR[rd]63..56

← GPR[rt]119..112

GPR[rd]71..64
GPR[rd]79..72

← GPR[rs]7..0
← GPR[rs]23..16

(The same operations follow every 8 bits)
GPR[rd]127..120

← GPR[rs]119..112

127 120 119 112 111 104 103

rs

A7

A6

A5

B7

A5

96 95

A4

127 120 119 112 111 104 103

rt

88 87 80 79 72 71 64 63 56 55

A6

127 120 119 112 111 104 103

rd A7

96 95

96 95

A3

88 87 80 79 72 71 64 63 56 55

A3

B6

A4

A2

A1

A0

B7

B4

© SCEI
-256-

B5

B3

8 7

B1

16 15

B1

0

A0

16 15

B2

32 31 24 23

B2

16 15

A1

32 31 24 23

B4

48 47 40 39

B3

32 31 24 23

A2

48 47 40 39

B6

88 87 80 79 72 71 64 63 56 55

B5

48 47 40 39

8 7

0

B0
8 7

B0

0

SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

PPACH : Parallel Pack to Halfword
128-bit MMI
To pack the data in two GPRs into consecutive halfwords.
Operation Code
31

26

25

21

20

16

15

11

10

6

5

0

MMI
011100

rs

rt

rd

PPACH
10111

MMI0
001000

6

5

5

5

5

6

Format
PPACH rd, rs, rt
Description
GPR[rd] ← pack(GPR[rs] , GPR[rt])
Splits the 128-bit data in GPR[rs] into four words, takes the low-order halfword of each of the words and
stores them in the high-order 64 bits of GPR[rd]. Likewise, takes the low-order halfwords of each of the
words in GPR[rt] and stores them in the low-order 64 bits of GPR[rd].
Exceptions
None
Operation
GPR[rd]15..0
GPR[rd]31..16
GPR[rd]47..32
GPR[rd]63..48
GPR[rd]79..64
GPR[rd]95..80
GPR[rd]111..96
GPR[rd]127..112

← GPR[rs]15..0
← GPR[rs]47..32
← GPR[rs]79..64
← GPR[rs]111..96

127

96 95

112 111

rs

80 79

A3
127

rd

112 111

A3
127

rt

← GPR[rt]15..0
← GPR[rt]47..32
← GPR[rt]79..64
← GPR[rt]111..96

A2

80 79

A1
96 95

B3

48 47

A2
96 95

112 111

64 63

16 15

A1
64 63

A0
80 79

32 31

48 47

B3
64 63

B2

A0
32 31

B2
48 47

16 15

B1
32 31

B1

0

0

B0
16 15

0

B0

© SCEI
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SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

PPACW : Parallel Pack to Word
128-bit MMI
To pack the data in two GPRs into consecutive words.
Operation Code
31

26

25

21

20

16

15

11

10

6

5

0

MMI
011100

rs

rt

rd

PPACW
10011

MMI0
001000

6

5

5

5

5

6

Format
PPACW rd, rs, rt
Description
GPR[rd] ← pack(GPR[rs] , GPR[rt])
Splits the 128-bit data in GPR[rs] into two doublewords, takes the low-order word of each of the
doublewords and stores them in the high-order 64 bits of GPR[rd]. Likewise, takes the low-order word of
each of the doublewords of GPR[rt] and stores them in the low-order 64-bit in GPR[rd].
Exceptions
None
Operation
GPR[rd]31..0
GPR[rd]63..32
GPR[rd]95..64
GPR[rd]127..96
127

← GPR[rt]31..0
← GPR[rt]95..64
← GPR[rs]31..0
← GPR[rs]95..64
96 95

rs

64 63

32 31

A1
127

rd

96 95

A1
127

rt

A0
64 63

A0
96 95

0

32 31

B1
64 63

B1

0

B0
32 31

0

B0

© SCEI
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SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

PREVH : Parallel Reverse Halfword
128-bit MMI
To exchange the position of halfwords.
Operation Code
31

26

25

21

20

16

15

11

10

6

5

0

MMI
011100

0
00000

rt

rd

PREVH
11011

MMI2
001001

6

5

5

5

5

6

Format
PREVH rd, rt
Description
GPR[rd] ← exchange(GPR[rt])
Splits the 128-bit data in GPR[rt] into eight halfwords, exchanges their sequence and stores them in GPR[rd].
See "Operation" about the details of the exchange.
Exceptions
None
Operation
GPR[rd]15..0
GPR[rd]31..16
GPR[rd]47..32
GPR[rd]63..48
GPR[rd]79..64
GPR[rd]95..80
GPR[rd]111..96
GPR[rd]127..112
127

rt

112 111

A7

127

rd

← GPR[rt]63..48
← GPR[rt]47..32
← GPR[rt]31..16
← GPR[rt]15..0
← GPR[rt]127..112
← GPR[rt]111..96
← GPR[rt]95..80
← GPR[rt]79..64
96 95

A6

112 111

A4

80 79

A5

96 95

A5

64 63

A4

80 79

A6

48 47

A3

64 63

A7

32 31

A2

48 47

A0

16 15

A1

32 31

A1

0

A0

16 15

A2

0

A3

© SCEI
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SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

PROT3W : Parallel Rotate 3 Words Left
128-bit MMI
To exchange the sequence of 3 words in 128-bit data.
Operation Code
31

26

25

21

20

16

15

11

10

6

5

0

MMI
011100

0
00000

rt

rd

PROT3W
11111

MMI2
001001

6

5

5

5

5

6

Format
PROT3W rd, rt
Description
GPR[rd] ← rotate(GPR[rt])
Splits the 128-bit data in GPR[rt] into four words, rotates the positions of the low-order three words, and
stores them in GPR[rd].
Exceptions
None
Operation
GPR[rd]31..0
GPR[rd]63..32
GPR[rd]95..64
GPR[rd]127..96
127

rt

← GPR[rt]63..32
← GPR[rt]95..64
← GPR[rt]31..0
← GPR[rt]127..96
96 95

A3

127

rd

64 63

A2

96 95

A3

32 31

A1

64 63

A0

-260-

A0

32 31

A2

© SCEI

0

0

A1

SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

PSLLH : Parallel Shift Left Logical Halfword
128-bit MMI
To logical shift left halfwords in 128-bit data. The shift amount is a fixed value (0-15 bits) specified by sa.
Operation Code
31

26

25

21

20

16

15

11

10

6

5

0

MMI
011100

0
00000

rt

rd

sa

PSLLH
110100

6

5

5

5

5

6

Format
PSLLH rd, rt, sa
Description
GPR[rd] ← GPR[rt] << sa (logical)
Splits the 128-bit data in GPR[rt] into eight halfwords, shifts them left by the number of bits specified by the
low-order 4 bits of sa and inserts zeros in the emptied bits. The resulting value is stored in the corresponding
halfwords in GPR[rd].
Exceptions
None
Operation
s ← sa3..0
GPR[rd]15..0
GPR[rd]31..16
GPR[rd]47..32
GPR[rd]63..48
GPR[rd]79..64
GPR[rd]95..80
GPR[rd]111..96
GPR[rd]127..112
127

rt

112 111

A7
s bit
127

rd A7

← GPR[rt]15-s..0 || 0s
← GPR[rt]31-s..16 || 0s
← GPR[rt]47-s..32 || 0s
← GPR[rt]63-s..48 || 0s
← GPR[rt]79-s..64 || 0s
← GPR[rt]95-s..80 || 0s
← GPR[rt]111-s..96 || 0s
← GPR[rt]127-s..112 || 0s
96 95

A6
s bit

112 111
s

0

s bit

A6

80 79

A5
s bit

64 63

A4
s bit

48 47

A3
s bit

32 31

A2
s bit

16 15

A1
s bit

A0
s bit

96 95

80 79

64 63

48 47

32 31

16 15

s

s

s

s

s

s

0

s bit

A5

0

s bit

A4

0

A3

s bit

0

s bit

A2

0

s bit

A1

0

0

s bit

A0

0
s

0

s bit

© SCEI
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SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

PSLLVW : Parallel Shift Left Logical Variable Word
128-bit MMI
To shift left 2 words in 128-bit data. The shift amount is specified by a GPR.
Operation Code
31

26

25

21

20

16

15

11

10

6

5

0

MMI
011100

rs

rt

rd

PSLLVW
00010

MMI2
001001

6

5

5

5

5

6

Format
PSLLVW rd, rt, rs
Description
GPR[rd] ← GPR[rt] << GPR[rs]
(logical)
Splits the 128-bit data in GPR[rt] into two doublewords and shifts each of the low-order words left. The
shift amount is specified by the low-order 5 bits of the corresponding word in GPR[rs]. Inserts zeros in the
emptied bits. The resulting two 32-bit values are sign-extended and stored in GPR[rd].
Exceptions
None
Operation
s ← GPR[rs]4..0
t ← GPR[rs]68..64
← (GPR[rt]31-s)32 || GPR[rt]31-s..0 || 0s
GPR[rd]63..0
← (GPR[rt]95-t)32 || GPR[rt]95-t..64 || 0t
GPR[rd]127..64
127

68 64 63

rs

4

t
127

96 95

s
64 63

rt

32 31

0

A1

127

rd

96 95

← sign extend

A0

64 63

A1

0

32 31

← sign extend

0
t bit

0

A0

0
s bit

© SCEI
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SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

PSLLW : Parallel Shift Left Logical Word
128-bit MMI
To logically shift left four words in 128-bit data. The shift amount is a fixed value specified by sa.
Operation Code
31

26

25

21

20

16

15

11

10

6

5

0

MMI
011100

0
00000

rt

rd

sa

PSLLW
111100

6

5

5

5

5

6

Format
PSLLW rd, rt, sa
Description
GPR[rd] ← GPR[rt] << sa (logical)
Splits the 128-bit data in GPR[rt] into four words, shifts left by the number of bits specified by sa and inserts
zeros in the emptied bits. The resulting value is stored in the corresponding words in GPR[rd].
Exceptions
None
Operation
GPR[rd]31..0
GPR[rd]63..32
GPR[rd]95..64
GPR[rd]127..96

← GPR[rt]31-sa..0 || 0sa
← GPR[rt]63-sa..32 || 0sa
← GPR[rt]95-sa..64 || 0sa
← GPR[rt]127-sa..96 || 0sa

127

96 95

rt

A3
sa bit

A3

0

sa bit

sa

0

32 31

A1

sa bit

A0
sa bit

64 63

A2

0

A1
sa bit

96 95
sa

32 31

A2
sa bit

127

rd

64 63

sa

0

sa bit

0

A0

sa

0

sa bit

© SCEI
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SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

PSRAH : Parallel Shift Right Arithmetic Halfword
128-bit MMI
To arithmetically shift right 8 halfwords in 128-bit data. The shift amount is a fixed value (0-15 bits) specified by
sa.
Operation Code
31

26

25

21

20

16

15

11

10

6

5

0

MMI
011100

0
00000

rt

rd

sa

PSRAH
110111

6

5

5

5

5

6

Format
PSRAH rd, rt, sa
Description
GPR[rd] ← GPR[rt] >> sa (arithmetic)
Splits the 128-bit data in GPR[rt] into eight halfword data, shifts right by the bit number specified by the
low-order 4 bits of sa and duplicates the sign bits in the emptied bits. The resulting values are stored in the
corresponding halfwords in GPR[rd].
Restrictions
The value of sa must be within the range from 0 to 15. Otherwise, the result is undefined.
Exceptions
None
Operation
s ← sa3..0
GPR[rd]15..0
GPR[rd]31..16
GPR[rd]47..32
GPR[rd]63..48
GPR[rd]79..64
GPR[rd]95..80
GPR[rd]111..96
GPR[rd]127..112
127

rt

112 111

A7

rd sign
s bit

96 95

A6
s bit

127

← (GPR[rt]15)s || GPR[rt]15..s
← (GPR[rt]31)s || GPR[rt]31..16+s
← (GPR[rt]47)s || GPR[rt]47..32+s
← (GPR[rt]63)s || GPR[rt]63..48+s
← (GPR[rt]79)s || GPR[rt]79..64+s
← (GPR[rt]95)s || GPR[rt]95..80+s
← (GPR[rt]111)s || GPR[rt]111..96+s
← (GPR[rt]127)s || GPR[rt]127..112+s

A7

A5
s bit

112 111
sign
s bit

80 79

A6

A4
s bit

96 95

64 63

A3
s bit

80 79

48 47

A2
s bit

64 63

sign A5

sign A4

sign

s bit

s bit

s bit

© SCEI
-264-

32 31

A3

A1
s bit

48 47
sign
s bit

16 15

A2

A0
s bit

32 31
sign
s bit

0

s bit

16 15

A1

sign
s bit

0

A0

SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

PSRAVW : Parallel Shift Right Arithmetic Variable Word
128-bit MMI
To arithmetically shift right 2 words in a 128-bit data. The shift amount is specified by a GPR.
Operation Code
31

26

25

21

20

16

15

11

10

6

5

0

MMI
011100

rs

rt

rd

PSRAVW
00011

MMI3
101001

6

5

5

5

5

6

Format
PSRAVW rd, rt, rs
Description
GPR[rd] ← GPR[rt] >> GPR[rs]
(arithmetic)
Splits the 128-bit data in GPR[rt] into two doublewords and shifts each of the low-order words right. The
shift amount is specified by the low-order 5 bits of the corresponding word in GPR[rs]. Duplicates the sign
bits into the emptied bits. The resulting two 32-bit values are sign-extended and stored in GPR[rd].
Exceptions
None
Operation
s ← GPR[rs]4..0
t ← GPR[rs]68..64
← (GPR[rt]31)32 || (GPR[rt]31)s  GPR[rt]31..s
GPR[rd]63..0
← (GPR[rt]95)32 || (GPR[rt]95)t  GPR[rt]95..64+t
GPR[rd]127..64
127

68 64 63

rs

4

t
127

96 95

rt

s
64 63

32 31

A1

0

A0
t bit

127

rd

96 95

← sign extend

s bit
64 63

← sign

0

32 31

← sign extend

A1

← sign

0

A0

s bit

t bit

© SCEI
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SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

PSRAW : Parallel Shift Right Arithmetic Word
128-bit MMI
To arithmetically shift right 4 words in 128-bit data. The shift amount is a fixed value specified by sa.
Operation Code
31

26

25

21

20

16

15

11

10

6

5

0

MMI
011100

0
00000

rt

rd

sa

PSRAW
111111

6

5

5

5

5

6

Format
PSRAW rd, rt, sa
Description
GPR[rd] ← GPR[rt] >> sa (arithmetic)
Splits the 128-bit data in GPR[rt] into four words, shifts them right by the number of bits specified by sa and
duplicates the sign bits in the emptied bits. The resulting value is stored in the corresponding words of
GPR[rd].
Exceptions
None
Operation
GPR[rd]31..0
GPR[rd]63..32
GPR[rd]95..64
GPR[rd]127..96

← (GPR[rt]31)sa || GPR[rt]31..sa
← (GPR[rt]63)sa || GPR[rt]63..32+sa
← (GPR[rt]95)sa || GPR[rt]95..64+sa
← (GPR[rt]127)sa || GPR[rt]127..96+sa

127

rt

96 95

A3

64 63

A2
sa bit

127

rd

sign ext
sa bit

A1
sa bit

96 95

A3

32 31

sign ext
sa bit

A0
sa bit

64 63

A2

0

sign ext
sa bit

© SCEI
-266-

sa bit
32 31

A1

sign ext
sa bit

0

A0

SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

PSRLH : Parallel Shift Right Logical Halfword
128-bit MMI
To logically shift right 8 halfwords in 128-bit data. The shift amount is a fixed value (0-15 bits) specified by sa.
Operation Code
31

26

25

21

20

16

15

11

10

6

5

0

MMI
011100

0
00000

rt

rd

sa

PSRLH
110110

6

5

5

5

5

6

Format
PSRLH rd, rt, sa
Description
GPR[rd] ← GPR[rt] >> sa (logical)
Splits the 128-bit data in GPR[rt] into eight halfwords, shifts right by the number of bits specified by the
low-order 4 bits of sa and inserts zeros into the emptied bits. The resulting value is stored in the
corresponding halfwords in GPR[rd].
Restrictions
The value of sa must be within the range from 0 to 15. Otherwise, the result is undefined.
Exceptions
None
Operation
s ← sa3..0
GPR[rd]15..0
GPR[rd]31..16
GPR[rd]47..32
GPR[rd]63..48
GPR[rd]79..64
GPR[rd]95..80
GPR[rd]111..96
GPR[rd]127..112
127

← 0s || GPR[rt]15..s
← 0s || GPR[rt]31..16+s
← 0s || GPR[rt]47..32+s
← 0s || GPR[rt]63..48+s
← 0s || GPR[rt]79..64+s
← 0s || GPR[rt]95..80+s
← 0s || GPR[rt]111..96+s
← 0s || GPR[rt]127..112+s

112 111

rt A7

A6
s bit

127

rd

s

0

s bit

96 95

A5
s bit

112 111

A7

80 79

s

0

s bit

A4
s bit

96 95

A6

64 63

0

s bit

A5

A3
s bit

80 79
s

48 47

0

s bit

A4

A2
s bit

64 63
s

32 31

0

s bit

A3

A1
s bit

48 47
s

16 15

0

s bit

A2

A0
s bit

32 31
s

0

s bit

16 15
s

0

s bit

A1

0
s

0

A0

s bit

© SCEI
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SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

PSRLVW : Parallel Shift Right Logical Variable Word
128-bit MMI
To logically shift right 2 words in 128-bit data. The shift amount is specified by a GPR.
Operation Code
31

26

25

21

20

16

15

11

10

6

5

0

MMI
011100

rs

rt

rd

PSRLVW
00011

MMI2
001001

6

5

5

5

5

6

Format
PSRLVW rd, rt, rs
Description
GPR[rd] ← GPR[rt] >> GPR[rs]
(logical)
Splits the 128-bit data in GPR[rt] into two doublewords and shifts each of the low-order words right. The
shift amount is specified by the low-order five bits of the corresponding word in GPR[rs]. Inserts zeros into
the emptied bits. The resulting two 32-bit values are sign-extended and stored in GPR[rd].
Exceptions
None
Operation
s ← GPR[rs]4..0
t ← GPR[rs]68..64
temp0 ← 0s || GPR[rt]31..s
temp1 ← 0t || GPR[rt]95..64+t
GPR[rd]63..0 ← (temp031)32 || temp031..0
GPR[rd]127..64 ← (temp131)32 || temp131..0
127

68 64 63

rs

4

t
127

96 95

rt

64 63

32 31

0

A1

A0
t bit

127

rd

96 95

← sign extend

s bit
64 63

t

0

0

s

32 31

← sign extend

A1

0
s

0

s bit

t bit

© SCEI
-268-

A0

SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

PSRLW : Parallel Shift Right Logical Word
128-bit MMI
To arithmetically shift right 4 words in 128-bit data. The shift amount is a fixed value specified by sa.
Operation Code
31

26

25

21

20

16

15

11

10

6

5

0

MMI
011100

0
00000

rt

rd

sa

PSRLW
111110

6

5

5

5

5

6

Format
PSRLW rd, rt, sa
Description
GPR[rd] ← GPR[rt] >> sa (logical)
Splits the 128-bit data in GPR[rt] into four words, shifts them right by the number of bits specified by sa and
inserts zeros into the emptied bits. The resulting value is stored in the corresponding words in GPR[rd].
Exceptions
None
Operation
GPR[rd]31..0
GPR[rd]63..32
GPR[rd]95..64
GPR[rd]127..96

← 0sa || GPR[rt]31..sa
← 0sa || GPR[rt]63..32+sa
← 0sa || GPR[rt]95..64+sa
← 0sa || GPR[rt]127..96+sa

127

rt

96 95

A3

64 63

A2
sa bit

127

rd

A1
sa bit

96 95
sa

0

sa bit

A3

32 31

A0
sa bit

64 63
sa

0

sa bit

0

sa bit

32 31
sa

A2

0

sa bit

A1

0
sa

0

A0

sa bit

© SCEI
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SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

PSUBB : Parallel Subtract Byte
128-bit MMI
To subtract 16 pairs of 8-bit integers in parallel.
Operation Code
31

26

25

21

20

16

15

11

10

6

5

0

MMI
011100

rs

rt

rd

PSUBB
01001

MMI0
001000

6

5

5

5

5

6

Format
PSUBB rd, rs, rt
Description
GPR[rd] ← GPR[rs] – GPR[rt]
Splits the 128-bit data in GPR[rs] and GPR[rt] into sixteen 8-bit integers, subtracts the data in GPR[rt] from
the corresponding data in GPR[rs] and stores them in the corresponding bytes in GPR[rd]. If an overflow or
underflow occurs, the results are just truncated.
Exceptions
None. Even when the result of the arithmetic operation overflows or underflows, an exception does not
occur.
Operation
GPR[rd]7..0
GPR[rd]15..8

← (GPR[rs]7..0 – GPR[rt]7..0)7..0
← (GPR[rs]15..8 – GPR[rt]15..8)7..0

(The same operations follow every 8 bits)
127 120 119 112 111 104 103 96 95 88 87 80 79 72 71 64 63 56 55 48 47 40 39 32 31 24 23 16 15

rs A15 A14 A13 A12 A11 A10

−

−

−

−

−

−

87

A9

A8

A7

A6

A5

A4

A3

A2

A1

−

−

−

−

−

−

−

−

−

127 120 119 112 111 104 103 96 95 88 87 80 79 72 71 64 63 56 55 48 47 40 39 32 31 24 23 16 15

rt B15 B14 B13 B12

B11 B10

B9

B8

B7

B6

B5

B4

127 120 119 112 111 104 103 96 95 88 87 80 79 72 71 64 63 56 55 48 47 40 39

rd

A15
−
B15

A14
−
B14

A13
−
B13

A12
−
B12

A11
−
B11

A10
−
B10

A9
−
B9

A8
−
B8

A7
−
B7

© SCEI
-270-

A6
−
B6

A5
−
B5

A4
−
B4

B3

B2

A2
−
B2

A0

−
87

B1

32 31 24 23 16 15
A3
−
B3

0

A1
−
B1

0

B0

87

0
A0
−
B0

SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

PSUBH : Parallel Subtract Halfword
128-bit MMI
To subtract 8 pairs of 16-bit integers in parallel.
Operation Code
31

26

25

21

20

16

15

11

10

6

5

0

MMI
011100

rs

rt

rd

PSUBH
00101

MMI0
001000

6

5

5

5

5

6

Format
PSUBH rd, rs, rt
Description
GPR[rd] ← GPR[rs] – GPR[rt]
Splits the 128-bit data in GPR[rs] and GPR[rt] into eight 16-bit integers, subtracts the data in GPR[rt] from
the corresponding data in GPR[rs] and stores them in the corresponding halfwords in GPR[rd]. If an
overflow or underflow occurs, the results are just truncated.
Exceptions
None
Operation
GPR[rd]15..0
GPR[rd]31..16

← (GPR[rs]15..0 – GPR[rt]15..0)15..0
← (GPR[rs]31..16 – GPR[rt]31..16)15..0

(The same operations follow every 16 bits)
← (GPR[rs]127..112 – GPR[rt]127..112)15..0

GPR[rd]127..112
127

rs
127

rt

96 95

80 79

64 63

48 47

32 31

16 15

0

A7

A6

A5

A4

A3

A2

A1

A0

–

–

–

–

–

–

–

–

112 111

B7

127

rd

112 111

B6

112 111

A7–B7

96 95

80 79

B5

96 95

A6–B6

A5–B5

64 63

B4

80 79

A4–B4

48 47

B3

64 63

A3–B3

32 31

B2

48 47

16 15

B1

32 31

A2–B2

0

B0

16 15

A1–B1

0

A0–B0

© SCEI
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SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

PSUBSB : Parallel Subtract with Signed saturation Byte
128-bit MMI
To subtract 16 pairs of 8-bit signed integers with saturation in parallel.
Operation Code
31

26

25

21

20

16

15

11

10

6

5

0

MMI
011100

rs

rt

rd

PSUBSB
11001

MMI0
001000

6

5

5

5

5

6

Format
PSUBSB rd, rs, rt
Description
GPR[rd] ← GPR[rs] – GPR[rt]
Splits GPR[rs] and GPR[rt] into sixteen 8-bit signed integers, subtracts the data in GPR[rt] from the
corresponding data in GPR[rs] with saturation and stores them in the corresponding bytes in GPR[rd].
Exceptions
None
Operation
if ((GPR[rs]7..0 – GPR[rt]7..0) >= 0x7F) then
← 0x7F
GPR[rd]7..0
else if (0x100 <= (GPR[rs]7..0 – GPR[rt]7..0) < 0x180) then
← 0x80
GPR[rd]7..0
else
← (GPR[rs]7..0 – GPR[rt]7..0)7..0
GPR[rd]7..0
endif
if ((GPR[rs]15..8 – GPR[rt]15..8) >= 0x7F) then
← 0x7F
GPR[rd]15..8
else if (0x100 <= (GPR[rs]15..8 – GPR[rt]15..8) < 0x180) then
← 0x80
GPR[rd]15..8
else
← (GPR[rs]15..8 – GPR[rt]15..8)7..0
GPR[rd]15..8
endif
(The same operations follow every 8 bits)
if ((GPR[rs]127..120 – GPR[rt]127..120) >= 0x7F) then
GPR[rd]127..120 ← 0x7F
else if (0x100 <= (GPR[rs]127..120 – GPR[rt]127..120) < 0x180) then
GPR[rd]127..120 ← 0x80
else
GPR[rd]127..120 ← (GPR[rs]127..120 – GPR[rt]127..120)7..0
endif

© SCEI
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SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

127 120 119 112 111 104 103 96 95 88 87 80 79 72 71 64 63 56 55 48 47 40 39

rs A15 A14 A13 A12 A11 A10

A9

A8

A7

A6

A5

32 31 24 23 16 15

A4

A3

A2

A1

8 7

0

A0

–
127 120 119 112 111 104 103 96 95 88 87 80 79 72 71 64 63 56 55 48 47 40 39

rt B15 B14 B13 B12 B11 B10

B9

B8

B7

B6

B5

32 31 24 23 16 15

B4

B3

B2

8 7

B1

0

B0

Clamp to signed byte
127 120 119 112 111 104 103 96 95 88 87 80 79 72 71 64 63 56 55 48 47 40 39

rd

A15
−
B15

A14
−
B14

A13
−
B13

A12
−
B12

A11
−
B11

A10
−
B10

A9
−
B9

A8
−
B8

A7
−
B7

A6
−
B6

A5
−
B5

32 31 24 23 16 15
A4
−
B4

A3
−
B3

A2
−
B2

A1
−
B1

8 7

0
A0
−
B0

© SCEI
-273-

SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

PSUBSH : Parallel Subtract with Signed Saturation Halfword
128-bit MMI
To subtract 8 pairs of 16-bit integers in parallel.
Operation Code
31

26

25

21

20

16

15

11

10

6

5

0

MMI
011100

rs

rt

rd

PSUBSH
10101

MMI0
001000

6

5

5

5

5

6

Format
PSUBSH rd, rs, rt
Description
GPR[rd] ← GPR[rs] – GPR[rt]
Splits the 128-bit data in GPR[rs] and GPR[rt] into eight 16-bit signed integers, subtracts the data in GPR[rt]
from the corresponding data in GPR[rs] and stores them in the corresponding halfwords in GPR[rd]. If an
overflow or underflow occurs, the results are just truncated.
Exceptions
None
Operation
if ((GPR[rs]15..0 – GPR[rt]15..0) >= 0x7FFF) then
← 0x7FFF
GPR[rd]15..0
else if (0x10000 <= (GPR[rs]15..0 – GPR[rt]15..0) < 0x18000) then
← 0x8000
GPR[rd]15..0
else
GPR[rd]15..0
← (GPR[rs]15..0 – GPR[rt]15..0)15..0
endif
if ((GPR[rs]31..16 – GPR[rt]31..16) >= 0x7FFF) then
← 0x7FFF
GPR[rd]31..16
else if (0x10000 <= (GPR[rs]31..16 – GPR[rt]31..16) < 0x18000) then
← 0x8000
GPR[rd]31..16
else
← (GPR[rs]31..16 – GPR[rt]31..16)15..0
GPR[rd]31..16
endif
(The same operations follow every 16 bits)
if ((GPR[rs]127..112 – GPR[rt]127..112) >= 0x7FFF) then
GPR[rd]127..112 ← 0x7FFF
else if (0x10000 <= (GPR[rs]127..112 – GPR[rt]127..112) < 0x18000) then
GPR[rd]127..112 ← 0x8000
else
GPR[rd]127..112 ← (GPR[rs]127..112 – GPR[rt]127..112)15..0
endif

© SCEI
-274-

SCE CONFIDENTIAL

127

rs

112 111

96 95

80 79

64 63

48 47

32 31

16 15

0

A7

A6

A5

A4

A3

A2

A1

A0

–

–

–

–

–

–

–

–

127

rt

EE Core Instruction Set Manual Version 6.0

112 111

B7

96 95

B6

80 79

B5

64 63

B4

48 47

B3

32 31

16 15

B2

B1

0

B0

Clamp to signed halfword
127

rd

112 111

A7–B7

96 95

A6–B6

80 79

A5–B5

64 63

A4–B4

48 47

A3–B3

32 31

A2–B2

16 15

A1–B1

0

A0–B0

© SCEI
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SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

PSUBSW : Parallel Subtract with Signed Saturation Word
128-bit MMI
To subtract 4 pairs of 32-bit signed integers with saturation in parallel.
Operation Code
31

26

25

21

20

16

15

11

10

6

5

0

MMI
011100

rs

rt

rd

PSUBSW
10001

MMI0
001000

6

5

5

5

5

6

Format
PSUBSW rd, rs, rt
Description
GPR[rd] ← GPR[rs] – GPR[rt]
Splits the 128-bit data in GPR[rs] and GPR[rt] into four 32-bit signed integers, subtracts the data in GPR[rt]
from the corresponding data in GPR[rs] with saturation and stores them in the corresponding words in
GPR[rd].
Exceptions
None
Operation
if ((GPR[rs]31..0 – GPR[rt]31..0) >= 0x7FFFFFFF) then
← 0x7FFFFFFF
GPR[rd]31..0
else if (0x100000000 <= (GPR[rs]31..0 – GPR[rt]31..0) < 0x180000000) then
← 0x80000000
GPR[rd]31..0
else
GPR[rd]31..0
← (GPR[rs]31..0 – GPR[rt]31..0)31..0
endif
if ((GPR[rs]63..32 – GPR[rt]63..32) >= 0x7FFFFFFF) then
← 0x7FFFFFFF
GPR[rd]63..32
else if (0x100000000 <= (GPR[rs]63..32 – GPR[rt]63..32) < 0x180000000) then
← 0x80000000
GPR[rd]63..32
else
← (GPR[rs]63..32 – GPR[rt]63..32)31..0
GPR[rd]63..32
endif
if ((GPR[rs]95..64 – GPR[rt]95..64) >= 0x7FFFFFFF) then
← 0x7FFFFFFF
GPR[rd]95..64
else if (0x100000000 <= (GPR[rs]95..64 – GPR[rt]95..64) < 0x180000000) then
← 0x80000000
GPR[rd]95..64
else
GPR[rd]95..64
← (GPR[rs]95..64 – GPR[rt]95..64)31..0
endif
if ((GPR[rs]127..96 – GPR[rt]127..96) >= 0x7FFFFFFF) then
← 0x7FFFFFFF
GPR[rd]127..96
else if (0x100000000 <= (GPR[rs]127..96 – GPR[rt]127..96) < 0x180000000) then
← 0x80000000
GPR[rd]127..96
else
← (GPR[rs]127..96 – GPR[rt]127..96)31..0
GPR[rd]127..96
© SCEI
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SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

endif
127

rs

96 95

A3

64 63

A2

32 31

A1

0

A0

–
127

rt

96 95

B3

64 63

B2

32 31

B1

0

B0

Clamp to signed word
127

rd

96 95

A3–B3

64 63

A2–B2

32 31

A1–B1

0

A0–B0

© SCEI
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SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

PSUBUB : Parallel Subtract with Unsigned Saturation Byte
128-bit MMI
To subtract 16 pairs of 8-bit unsigned integers with saturation in parallel.
Operation Code
31

26

25

21

20

16

15

11

10

6

5

0

MMI
011100

rs

rt

rd

PSUBUB
11001

MMI1
101000

6

5

5

5

5

6

Format
PSUBUB rd, rs, rt
Description
GPR[rd] ← GPR[rs] – GPR[rt]
Splits the 128-bit data in GPR[rs] and GPR[rt] into sixteen unsigned bytes, subtracts the data in GPR[rt]
from the corresponding data in GPR[rs] with saturation and stores them in the corresponding bytes in
GPR[rd].
Exceptions
None
Operation
if ((GPR[rs]7..0 – GPR[rt]7..0) <= 0x00) then
← 0x00
GPR[rd]7..0
else
← (GPR[rs]7..0 – GPR[rt]7..0)7..0
GPR[rd]7..0
endif
if ((GPR[rs]15..8 – GPR[rt]15..8) <= 0x00) then
← 0x00
GPR[rd]15..8
else
← (GPR[rs]15..8 – GPR[rt]15..8)7..0
GPR[rd]15..8
endif
(The same operations follow every 8 bits)
if ((GPR[rs]127..120 – GPR[rt]127..120) <= 0x00) then
GPR[rd]127..120 ← 0x00
else
GPR[rd]127..120 ← (GPR[rs]127..120 – GPR[rt]127..120)7..0
endif

© SCEI
-278-

SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

127 120 119 112 111 104 103

96 95 88 87 80 79 72 71 64 63 56 55 48 47 40 39

rs A15 A14 A13 A12 A11 A10

A9

A8

A7

A6

A5

32 31 24 23 16 15

A4

A3

A2

8 7

A1

0

A0

–
127 120 119 112 111 104 103

rt B15 B14 B13

96 95 88 87 80 79 72 71 64 63 56 55 48 47 40 39

B12 B11 B10

B9

B8

B7

B6

B5

32 31 24 23 16 15

B4

B3

B2

8 7

B1

0

B0

Clamp to unsigned byte
127 120 119 112 111 104 103

rd

A15
−
B15

A14
−
B14

A13
−
B13

A12
−
B12

96 95 88 87 80 79 72 71 64 63 56 55 48 47 40 39 32 31 24 23 16 15
A11
−
B11

A10
−
B10

A9
−
B9

A8
−
B8

A7
−
B7

A6
−
B6

A5
−
B5

A4
−
B4

A3
−
B3

A2
−
B2

8 7
A1
−
B1

0
A0
−
B0

© SCEI
-279-

SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

PSUBUH : Parallel Subtract with Unsigned Saturation Halfword
128-bit MMI
To subtract 8 pairs of 16-bit unsigned integers with saturation in parallel.
Operation Code
31

26

25

21

20

16

15

11

10

6

5

0

MMI
011100

rs

rt

rd

PSUBUH
10101

MMI1
101000

6

5

5

5

5

6

Format
PSUBUH rd, rs, rt
Description
GPR[rd] ← GPR[rs] – GPR[rt]
Splits the 128-bit data in GPR[rs] and GPR[rt] into eight unsigned halfword data, subtracts the data in
GPR[rt] from the corresponding data in GPR[rs] with saturation and stores them in the corresponding
halfwords in GPR[rd].
Exceptions
None
Operation
if ((GPR[rs]15..0 – GPR[rt]15..0) <= 0x0000) then
← 0x0000
GPR[rd]15..0
else
← (GPR[rs]15..0 – GPR[rt]15..0)15..0
GPR[rd]15..0
endif
if ((GPR[rs]31..16 – GPR[rt]31..16) <= 0x0000) then
← 0x0000
GPR[rd]31..16
else
← (GPR[rs]31..16 – GPR[rt]31..16)15..0
GPR[rd]31..16
endif
(The same operations follow every 16 bits)
if ((GPR[rs]127..112 – GPR[rt]127..112) <= 0x0000) then
GPR[rd]127..112 ← 0x0000
else
GPR[rd]127..112 ← (GPR[rs]127..112 – GPR[rt]127..112)15..0
endif

© SCEI
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SCE CONFIDENTIAL

127

rs

112 111

96 95

80 79

64 63

48 47

32 31

16 15

0

A7

A6

A5

A4

A3

A2

A1

A0

–

–

–

–

–

–

–

–

127

rt

EE Core Instruction Set Manual Version 6.0

112 111

B7

96 95

B6

80 79

B5

64 63

B4

48 47

B3

32 31

B2

16 15

B1

0

B0

Clamp to unsigned halfword
127

rd

112 111

A7–B7

96 95

A6–B6

A5–B5

80 79

A4–B4

64 63

A3–B3

48 47

32 31

A2–B2

16 15

A1–B1

0

A0–B0

© SCEI
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SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

PSUBUW : Parallel Subtract with Unsigned Saturation Word
128-bit MMI
To subtract 4 pairs of 32-bit unsigned integers with saturation in parallel.
Operation Code
31

26

25

21

20

16

15

11

10

6

5

0

MMI
011100

rs

rt

rd

PSUBUW
10001

MMI1
101000

6

5

5

5

5

6

Format
PSUBUW rd, rs, rt
Description
GPR[rd] ← GPR[rs] – GPR[rt]
Splits the 128-bit data in GPR[rs] and GPR[rt] into four unsigned words, subtracts the data in GPR[rt] from
the corresponding data in GPR[rs] with saturation and stores them in the corresponding words in GPR[rd].
Exceptions
None
Operation
if ((GPR[rs]31..0 – GPR[rt]31..0) <= 0x00000000) then
← 0x00000000
GPR[rd]31..0
else
← (GPR[rs]31..0 – GPR[rt]31..0)31..0
GPR[rd]31..0
endif
if ((GPR[rs]63..32 – GPR[rt]63..32) <= 0x00000000) then
← 0x00000000
GPR[rd]63..32
else
← (GPR[rs]63..32 – GPR[rt]63..32)31..0
GPR[rd]63..32
endif
if ((GPR[rs]95..64 – GPR[rt]95..64) <= 0x00000000) then
← 0x00000000
GPR[rd]95..64
else
← (GPR[rs]95..64 – GPR[rt]95..64)31..0
GPR[rd]95..64
endif
if ((GPR[rs]127..96 – GPR[rt]127..96) <= 0x00000000) then
← 0x00000000
GPR[rd]127..96
else
← (GPR[rs]127..96 – GPR[rt]127..96)31..0
GPR[rd]127..96
endif

© SCEI
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SCE CONFIDENTIAL

127

rs

EE Core Instruction Set Manual Version 6.0

96 95

A3

64 63

A2

32 31

A1

0

A0

–
127

rt

96 95

B3

64 63

B2

32 31

B1

0

B0

Clamp to unsigned word
127

rd

96 95

A3–B3

64 63

A2–B2

32 31

A1–B1

0

A0–B0

© SCEI
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SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

PSUBW : Parallel Subtract Word
128-bit MMI
To subtract 4 pairs of 32-bit integers in parallel.
Operation Code
31

26

25

21

20

16

15

11

10

6

5

0

MMI
011100

rs

rt

rd

PSUBW
00001

MMI0
001000

6

5

5

5

5

6

Format
PSUBW rd, rs, rt
Description
GPR[rd] ← GPR[rs] – GPR[rt]
Splits the 128-bit data in GPR[rs] and GPR[rt] into four 32-bit signed integers, subtracts the data in GPR[rt]
from the corresponding data in GPR[rs] and stores them in the corresponding words in GPR[rd].
If an overflow or underflow occurs, the results are just truncated.
Exceptions
None
Operation
GPR[rd]31..0
GPR[rd]63..32
GPR[rd]95..64
GPR[rd]127..96
127

rs

← (GPR[rs]31..0 – GPR[rt]31..0)31..0
← (GPR[rs]63..32 – GPR[rt]63..32)31..0
← (GPR[rs]95..64 – GPR[rt]95..64)31..0
← (GPR[rs]127..96 – GPR[rt]127..96)31..0
96 95

A3

64 63

A2

32 31

A1

0

A0

–
127

rt

96 95

B3

127

rd

64 63

B2

96 95

A3–B3

32 31

B1

64 63

A2–B2

-284-

B0

32 31

A1–B1

© SCEI

0

0

A0–B0

SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

PXOR : Parallel Exclusive OR
128-bit MMI
To calculate a bitwise logical EXCLUSIVE OR.
Operation Code
31

26

25

21

20

16

15

11

10

6

5

0

MMI
011100

rs

rt

rd

PXOR
10011

MMI2
001001

6

5

5

5

5

6

Format
PXOR rd, rs, rt
Description
GPR[rd] ← GPR[rs] XOR GPR[rt]
Calculates a 128-bit bitwise logical XOR between GPR[rs] and GPR[rt]. The result is stored in GPR[rd].
The truth table values for XOR are as follows:
X
0
0
1
1

Y
0
1
0
1

X XOR Y
0
1
1
0

Exceptions
None
Operation
GPR[rd]127..0 ← GPR[rs]127..0 XOR GPR[rt]127..0

© SCEI
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SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

QFSRV : Quadword Funnel Shift Right Variable
128-bit MMI
To right shift a 128-bit value. The shift amount is specified by the SA register.
Operation Code
31

26

25

21

20

16

15

11

10

6

5

0

MMI
011100

rs

rt

rd

QFSRV
11011

MMI1
101000

6

5

5

5

5

6

Format
QFSRV rd, rs, rt
Description
GPR[rd] ← (GPR[rs], GPR[rt]) >> SA
Shifts right the 256-bit concatenation of GPR[rs] with GPR[rt] by the number of bits specified by the SA
register, and stores the low-order 128 bits of the result in GPR[rd].
Since the value of the SA register is set using the MTSAB or MTSAH instruction, the shift amount with the
QFSRV instruction must be a multiple of bytes or halfwords.
Exceptions
None
Operation
if ( SA = 0 ) then
GPR[rd]127..0
else
GPR[rd]127..0
endif

← GPR[rt]127..0
← GPR[rs]SA−1..0 || GPR[rt]127..SA

Programming Notes
A left funnel shift is made possible by the value set in the SA register. To left shifts s bytes and s halfwords,
specify 16-s in the MTSAB instruction and 8-s in the MTSAH instruction respectively (0= 0xFF) then //Exp of ACC is in overflow state at instruction entry
if (TEMP.exp >= 0xFF) then
FPR[fd] ← maxmin(TEMP.sign)
else
FPR[fd] ← ACC
endif
FCR31.SO ← 1
FCR31.O ← 1
else
// Exp of ACC is normal or in underflow state at instruction entry
if (TEMP.exp >= 0xFF) then
FPR[fd] ← maxmin(TEMP.sign)
FCR31.SO ← 1
FCR31.O ← 1
else
if (TEMP.exp = 0x00) then
FPR[fd] ← ACC
else
TEMP1 ← ACC + TEMP
if (TEMP1.exp >= 0xFF) then
FPR[fd] ← maxmin(TEMP1.sign)
FCR31.SO ← 1
FCR31.O ← 1
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else

endif
endif
endif

if (TEMP1.exp = 0x00) then
FPR[fd] ← signedzero(TEMP1.sign)
FCR31.SU ← 1
FCR31.U ← 1
else
FPR[fd] ← TEMP1
endif

endif

maxmin(sign)
begin
if (sign = 1)
maxmin ← 0xFFFFFFFF
else
maxmin ← 0x7FFFFFFF
end
signedzero(sign)
begin
if (sign = 1)
signedzero ← 0x80000000
else
signedzero ← 0x00000000
end

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EE Core Instruction Set Manual Version 6.0

MADDA.S : Floating Point Multiply-Add
EE Core
To multiply Single-precision floating-point values and add to the accumulator.
Operation Code
31

26

25

21

20

16

15

11

10

6

5

0

COP1
010001

S
10000

ft

fs

0
00000

MADDA
011110

6

5

5

5

5

6

Format
MADDA.S fs, ft
Description
ACC ← ACC + FPR[fs] × FPR[ft]
Multiplies the value of FPR[fs] by the value of FPR[ft] and adds the result to the Accumulator ACC; that
result is stored in the Accumulator ACC. The results are all single-precision floating-point values. When an
exponent overflow occurs, Flag O and Flag SO are set to 1 with the value of +maximum or -maximum as a
result. When an exponent underflow occurs, Flag U and Flag SU are set to 1 with the value of +0 or -0 as a
result.
Exceptions
Coprocessor unusable. Floating-point exceptions such as invalid operation, inexact, overflow and underflow
are not generated by this instruction.
Operation
TEMP ← fs × ft
if (TEMP.exp = plusminuszero) then // multiply underflow occured
FCR31.SU ← 1
if (ACC.exp >= 0xFF) then //Exp of ACC is in overflow state at instruction entry
if (TEMP.exp >= 0xFF) then
ACC ← maxmin(TEMP.sign)
else
ACC ← ACC
endif
FCR31.SO ← 1
FCR31.O ← 1
else
// Exp of ACC is normal or in underflow state at instruction entry
if (TEMP.exp >= 0xFF) then
ACC ← maxmin(TEMP.sign)
FCR31.SO ← 1
FCR31.O ← 1
else
if (TEMP.exp = 0x00) then
ACC ← ACC
else
TEMP1 ← ACC + TEMP
if (TEMP1.exp >= 0xFF) then
ACC ← maxmin(TEMP1.sign)
FCR31.SO ← 1
FCR31.O ← 1
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else

endif
endif
endif

if (TEMP1.exp = 0x00) then
ACC ← signedzero(TEMP1.sign)
FCR31.SU ← 1
FCR31.U ← 1
else
ACC ← TEMP1
endif

endif

maxmin(sign)
begin
if (sign = 1)
maxmin ← 0xFFFFFFFF
else
maxmin ← 0x7FFFFFFF
end
signedzero(sign)
begin
if (sign = 1)
signedzero ← 0x80000000
else
signedzero ← 0x00000000
end

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MAX.S : Floating Point Maximum
EE Core
To obtain the maximum of two single-precision floating-point values.
Operation Code
31

26

25

21

20

16

15

11

10

6

5

0

COP1
010001

S
10000

ft

fs

fd

MAX
101000

6

5

5

5

5

6

Format
MAX.S fd, fs, ft
Description
FPR[fd] ← max(FPR[fs], FPR[ft])
Compares the values of FPR[fs] and FPR[ft] and stores the greater value in FPR[fd]. Flag O and Flag U are
cleared to zero.
Exceptions
Coprocessor unusable
Operation
if (FPR[fs] >= FPR[ft]) then
FPR[fd] ← FPR[fs]
else
FPR[fd] ← FPR[ft]
endif
Flag O
←0
Flag U
←0

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MFC1 : Move Word from Floating Point
MIPS I
To copy the contents of a floating-point register (FPR) to a general-purpose register (GPR).
Operation Code
31

26

25

21

20

16

15

11

10

0

COP1
010001

MFC1
00000

rt

fs

0
000 0000 0000

6

5

5

5

11

Format
MFC1 rt, fs
Description
GPR[rt] ← FPR[fs]
Sign-extends the FPR[fs] value and stores it in GPR[rt].
Exceptions
Coprocessor unusable
Operation
GPR[rt] ← sign_extend(FPR[fs])

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MIN.S : Floating Point Minimum
EE Core
To obtain the minimum of two single-precision floating-point values.
Operation Code
31

26

25

21

20

16

15

11

10

6

5

0

COP1
010001

S
10000

ft

fs

fd

MIN
101001

6

5

5

5

5

6

Format
MIN.S fd, fs, ft
Description
FPR[fd] ← min(FPR[fs], FPR[ft])
Compares the values of FPR[fs] and FPR[ft] and stores the lesser value in FPR[fd].
Flag O and Flag U are cleared to zero.
Exceptions
Coprocessor unusable
Operation
if (FPR[fs] <= FPR[ft]) then
FPR[fd] ← FPR[fs]
else
FPR[fd] ← FPR[ft]
endif
Flag O
←0
Flag U
←0

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MOV.S : Floating Point Move
MIPS I
To move data between floating-point registers (FPR).
Operation Code
31

26

25

21

20

16

15

11

10

6

5

0

COP1
010001

S
10000

0
00000

fs

fd

MOV
000110

6

5

5

5

5

6

Format
MOV.S fd, fs
Description
FPR[fd] ← FPR[fs]
Stores the value of FPR[fs] in FPR[fd].
Exceptions
Coprocessor unusable
Operation
FPR[fd] ← FPR[fs]

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MSUB.S : Floating Point Multiply and Subtract
MIPS I
To multiply single-precision floating-point values and subtract from Accumulator.
Operation Code
31

26

25

21

20

16

15

11

10

6

5

0

COP1
010001

S
10000

ft

fs

fd

MSUB
011101

6

5

5

5

5

6

Format
MSUB.S fd, fs, ft
Description
FPR[fd] ← ACC – FPR[fs] × FPR[ft]
Multiplies the value of FPR[fs] by the value of FPR[ft] and subtracts the product from the Accumulator
ACC, then stores the result in FPR[fd]. The results are all single-precision floating-point values. When an
exponent overflow occurs, Flag O and Flag SO are set to 1 with the value of +maximum or -maximum as a
result. When an exponent underflow occurs, Flag U and Flag SU are set to 1 with the value of +0 or -0 as a
result.
Exceptions
Coprocessor unusable. Floating-point exceptions such as invalid operation, inexact, overflow and underflow
are not generated by this instruction.
Operation
TEMP ← fs × ft
if (TEMP.exp = plusminuszero) then // multiply underflow occured
FCR31.SU ← 1
if (ACC.exp >= 0xFF) then //Exp of ACC is in overflow state at instruction entry
if (TEMP.exp >= 0xFF) then
FPR[fd] ← maxmin(TEMP.sign)
else
FPR[fd] ← ACC
endif
FCR31.SO ← 1
FCR31.O ← 1
else
// Exp of ACC is normal or in underflow state at instruction entry
if (TEMP.exp >= 0xFF) then
FPR[fd] ← maxmin(TEMP.sign)
FCR31.SO ← 1
FCR31.O ← 1
else
if (TEMP.exp = 0x00) then
FPR[fd] ← ACC
else
TEMP1 ← ACC – TEMP
if (TEMP1.exp >= 0xFF) then
FPR[fd] ← maxmin(TEMP1.sign)
FCR31.SO ← 1
FCR31.O ← 1
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else

endif
endif
endif

if (TEMP1.exp = 0x00) then
FPR[fd] ← signedzero(TEMP1.sign)
FCR31.SU ← 1
FCR31.U ← 1
else
FPR[fd] ← TEMP1
endif

endif

maxmin(sign)
begin
if (sign = 1)
maxmin ← 0xFFFFFFFF
else
maxmin ← 0x7FFFFFFF
end
signedzero(sign)
begin
if (sign = 1)
signedzero ← 0x80000000
else
signedzero ← 0x00000000
end

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MSUBA.S : Floating Point Multiply and Subtract from Accumulator
EE Core
To multiply single-precision floating-point values and subtract from Accumulator.
Operation Code
31

26

25

21

20

16

15

11

10

6

5

0

COP1
010001

S
10000

ft

fs

0
00000

MSUBA
011111

6

5

5

5

5

6

Format
MSUBA.S fs, ft
Description
ACC ← ACC – FPR[fs] × FPR[ft]
Multiplies the value of FPR[fs] by the value of the FPR[ft], subtracts the product from the Accumulator
ACC, then writes the result back to the ACC. The results are all single-precision floating-point values.
When an exponent overflow occurs, Flag O and Flag SO are set to 1 with +maximum or -maximum as a
result. When an exponent underflow occurs, Flag U and Flag SU are set to 1 and the result value is +0 or -0.
Exceptions
Coprocessor unusable. Floating-point exceptions such as invalid operation, inexact, overflow and underflow
are not generated by this instruction.
Operation
TEMP ← fs × ft
if (TEMP.exp = plusminuszero) then // multiply underflow occured
FCR31.SU ← 1
if (ACC.exp >= 0xFF) then //Exp of ACC is in overflow state at instruction entry
if (TEMP.exp >= 0xFF) then
ACC ← maxmin(TEMP.sign)
else
ACC ← ACC
endif
FCR31.SO ← 1
FCR31.O ← 1
else
// Exp of ACC is normal or in underflow state at instruction entry
if (TEMP.exp >= 0xFF) then
ACC ← maxmin(TEMP.sign)
FCR31.SO ← 1
FCR31.O ← 1
else
if (TEMP.exp = 0x00) then
ACC ← ACC
else
TEMP1 ← ACC – TEMP
if (TEMP1.exp >= 0xFF) then
ACC ← maxmin(TEMP1.sign)
FCR31.SO ← 1
FCR31.O ← 1
else
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if (TEMP1.exp = 0x00) then
ACC ← signedzero(TEMP1.sign)
FCR31.SU ← 1
FCR31.U ← 1
else
ACC ← TEMP1
endif
endif

endif

endif
endif
maxmin(sign)
begin
if (sign = 1)
maxmin ← 0xFFFFFFFF
else
maxmin ← 0x7FFFFFFF
end
signedzero(sign)
begin
if (sign = 1)
signedzero ← 0x80000000
else
signedzero ← 0x00000000
end

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EE Core Instruction Set Manual Version 6.0

MTC1 : Move Word to Floating Point
MIPS I
To copy the contents of a general-purpose register (GPR) to a floating-point register (FPR).
Operation Code
31

26

25

21

20

16

15

11

10

0

COP1
010001

MTC1
00100

rt

fs

0
000 0000 0000

6

5

5

5

11

Format
MTC1 rt, fs
Description
FPR[fs] ← GPR[rt]
Stores the lower 32 bits of GPR[rt] in a floating-point register FPR[fs].
Exceptions
Coprocessor unusable
Operation
FPR[fs] ← GPR[rt]31..0

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MUL.S : Floating Point Multiply
MIPS I
To multiply single-precision floating-point values.
Operation Code
31

26

25

21

20

16

15

11

10

6

5

0

COP1
010001

S
10000

ft

fs

fd

MUL
000010

6

5

5

5

5

6

Format
MUL.S fd, fs, ft
Description
FPR[fd] ← FPR[fs] × FPR[ft]
Multiplies the value of FPR[fs] by the value of FPR[ft] and stores the product in FPR[fd]. When an
exponent overflow occurs, Flag O and Flag SO are set to 1 with the value of +maximum or -maximum as a
result. When an exponent underflow occurs, Flag U and Flag SU are set to 1 with the value of +0 or -0 as a
result.
Exceptions
Coprocessor unusable. Floating-point exceptions such as invalid operation, inexact, overflow and underflow
are not generated by this instruction.
Operation
FPR[fd]
Flag O
Flag U
Flag SO
Flag SU

← FPR[fs] × FPR[ft]
← 1 if exponent overflows.
← 1 if exponent underflows.
← 1 if exponent overflows.
← 1 if exponent underflows.

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MULA.S : Floating Point Multiply to Accumulator
EE Core
To multiply single-precision floating-point values and store in Accumulator.
Operation Code
31

26

25

21

20

16

15

11

10

6

5

0

COP1
010001

S
10000

ft

fs

0
00000

MULA
011010

6

5

5

5

5

6

Format
MULA.S fs, ft
Description
ACC ← FPR[fs] × FPR[ft]
Multiplies the value of FPR[fs] by the value of FPR[ft] as single-precision floating-point values and stores the
product in the ACC register. When an exponent overflow occurs, Flag O and Flag SO are set to 1 and
+maximum or -maximum value is stored in the ACC register as the result. When an exponent underflow
occurs, Flag U and Flag SU are set to 1 and the value of +0 or -0 is stored in the ACC register as the result.
Exceptions
Coprocessor unusable. Floating-point exceptions such as invalid operation, inexact, overflow and underflow
are not generated by this instruction.
Operation
ACC
Flag O
Flag U
Flag SO
Flag SU

← FPR[fs] × FPR[ft]
← 1 if exponent overflows.
← 1 if exponent underflows.
← 1 if exponent overflows.
← 1 if exponent underflows.

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NEG.S : Floating Point Negate
MIPS I
To negate a floating-point value.
Operation Code
31

26

25

21

20

16

15

11

10

6

5

0

COP1
010001

S
10000

0
00000

fs

fd

NEG
000111

6

5

5

5

5

6

Format
NEG.S fd, fs
Description
FPR[fd] ← –FPR[fs]
Stores the value that is obtained by reversing the sign bit of FPR[fs] in FPR[fd]. Flag O and Flag U are
cleared to zero.
Exceptions
Coprocessor unusable
Operation
FPR[fd] ← –FPR[fs]
Flag O
←0
Flag U
←0

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RSQRT.S : Floating Point Reciprocal Square Root
MIPS IV
To obtain the reciprocal of the square root of a single-precision floating-point value.
Operation Code
31

26

25

21

20

16

15

11

10

6

5

0

COP1
010001

S
10000

ft

fs

fd

RSQRT
010110

6

5

5

5

5

6

Format
RSQRT.S fd, fs, ft
Description
FPR[fd] ← FPR[fs] / SQRT(FPR[ft])
Divides the value of FPR[fs] by the square root of FPR[ft] and stores the result in FPR[fd]. Values are
handled as single-precision floating-point. When the value of FPR[ft] is 0, Flag D and Flag SD are set to 1
and +maximum or –maximum is stored in FPR[fd] as the result. When the value of FPR[ft] is negative, Flag
I and Flag SI are set to 1 and the value of FPR[fs] divided by SQRT(ABS(FPR[ft])) is stored in FPR[fd] as
the result. When an exponent overflow occurs, the result is +maximum or –maximum. When an exponent
underflow occurs, the result is +0 or –0.
Exceptions
Coprocessor unusable. Floating-point exceptions, such as invalid operation or inexact are not generated.
Operation
FPR[fd] ← FPR[fs] / SQRT(FPR[ft])
Flag I
← 1 if FPR[ft] < 0
Flag D
← 1 if FPR[ft] = 0
Flag SI
← 1 if FPR[ft] < 0
Flag SD ← 1 if FPR[ft] = 0

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SQRT.S : Floating Point Square Root
MIPS II
To obtain the square root of a single-precision floating-point value.
Operation Code
31

26

25

21

20

16

15

11

10

6

5

0

COP1
010001

S
10000

ft

0
00000

fd

SQRT
000100

6

5

5

5

5

6

Format
SQRT.S fd, ft
Description
FPR[fd] ← SQRT(FPR[ft])
Calculates the single-precision floating-point square root value of FPR[ft] and stores the result in FPR[fd]. If
the value of FPR[ft] is –0, the result is –0.
If the value of FPR[ft] is less than 0, Flag I and Flag SI are set to 1 and the value of SQRT(ABS(FPR[ft])) is
stored in FPR[fd] as the result.
Exceptions
Coprocessor unusable. Floating-point exceptions, such as invalid operation or inexact are not generated.
Operation
FPR[fd]
Flag I
Flag D
Flag SI

← SQRT(FPR[ft])
← 1 if (FPR[ft] < 0)
←0
← 1 if (FPR[ft] < 0)

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SUB.S : Floating Point Subtract
MIPS I
To subtract single-precision floating-point values.
Operation Code
31

26

25

21

20

16

15

11

10

6

5

0

COP1
010001

S
10000

ft

fs

fd

SUB
000001

6

5

5

5

5

6

Format
SUB.S fd, fs, ft
Description
FPR[fd] ← FPR[fs] – FPR[ft]
Subtracts the value of FPR[ft] from the value of FPR[fs] and stores the result in FPR[fd]. Values are handled
as single-precision floating-point. When an exponent overflow occurs, Flag O and Flag SO are set to 1 and
+maximum or –maximum is stored in FPR[fd] as the result. When an exponent underflow occurs, Flag U
and Flag SU are set to 1 and +0 or –0 is stored in FPR[fd] as the result.
Exceptions
Coprocessor unusable. Floating-point exceptions such as invalid operation, inexact, overflow and underflow
are not generated by this instruction.
Operation
FPR[fd]
Flag O
Flag U
Flag SO
Flag SU

← FPR[fs] – FPR[ft]
← 1 if exponent overflows.
← 1 if exponent underflows.
← 1 if exponent overflows.
← 1 if exponent underflows.

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SUBA.S : Floating Point Subtract to Accumulator
EE Core
To subtract single-precision floating-point values and store in Accumulator.
Operation Code
31

26

25

21

20

16

15

11

10

6

5

0

COP1
010001

S
10000

ft

fs

0
00000

SUBA
011001

6

5

5

5

5

6

Format
SUBA.S fs, ft I
Description
ACC ← FPR[fs] – FPR[ft]
Subtracts the value of FPR[ft] from the value of FPR[fs] and stores the result in the ACC register. Values are
handled as single-precision floating-point. When an exponent overflow occurs, Flag O and Flag SO are set
to 1 and +maximum or –maximum is stored in the ACC register as the result. When an exponent underflow
occurs, Flag U and Flag SU are set to 1 and +0 or –0 is stored in the ACC register as the result.
Exceptions
Coprocessor unusable. Floating-point exceptions such as invalid operation, inexact, overflow and underflow
are not generated by this instruction.
Operation
ACC ← FPR[fs] – FPR[ft]
Flag O
← 1 if exponent overflows.
Flag U
← 1 if exponent underflows.
Flag SO ← 1 if exponent overflows.
Flag SU ← 1 if exponent underflows.

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SWC1 : Store Word from Floating Point
MIPS I
To store the contents of a floating-point register in memory.
Operation Code
31

26

25

21

20

16

15

0

SWC1
111001

base

ft

offset

6

5

5

16

Format
SWC1 ft, offset(base)
Description
memory[GPR[base]+offset] ← FPR[ft]
Adds the 16-bit signed offset to the value of GPR[base] and stores the contents of FPR[ft] in memory at the
obtained effective address.
Restrictions
The effective address must comply with word alignment. Otherwise, an address error exception occurs if the
lower 2 bits of effective address are not 0.
Exceptions
Coprocessor unusable, TLB Refill, TLB Invalid, Address Error
Operation (128-bit bus)
vAddr
← sign_extend(offset) + GPR[base]
if vAddr1..0 ≠ 02 then
SignalException(AddressError)
endif
(pAddr, uncached) ← AddressTranslation (vAddr, DATA, LOAD)
byte ← vAddr3..0
dataquad ← 096-8*byte || FPR[ft] || 08*byte
StoreMemory(uncached, WORD, dataquad, pAddr, vAddr, DATA)

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6. Appendix Instruction Set List
The instructions of the EE Core, COP0, COP1 (FPU) and COP2 (VU macro instructions) are classified
according to the following functions. The chapter number in this book where each instruction is described is
shown in the table. However, for the VU macro instructions indicated as VPU0, see a supplementary volume
"VU User's Manual".
• Computational Instructions
Integer add/subtraction and Floating point add/subtraction
Integer multiplication/division and Floating point multiplication/division
Integer multiply-add and Floating point multiply-add
Shift operation / Logical operation / Comparison operation
Maximum/Minimum value
Data Format Conversion
Exchange
Random Numbers
Other Operations (e.g. absolute value, square-root)
• Data transfer instructions
Instructions for transferring between registers
Load / Store
Data transfer with special registers
• Program Control Instructions
Conditional Branch / Jump
Subroutine Call
Break / Trap
• Other Instructions

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6.1. Computational Instructions
6.1.1. Integer Addition and Subtraction
Inst.
ADD
ADDI
ADDIU
ADDU
DADD
DADDI
DADDIU
DADDU
DSUB
DSUBU
SUB
SUBU
PADDB
PADDH
PADDSB
PADDSH
PADDSW
PADDUB
PADDUH
PADDUW
PADDW
PADSBH
PSUBB
PSUBH
PSUBSB
PSUBSH
PSUBSW
PSUBUB
PSUBUH
PSUBUW
PSUBW
VIADD
VIADDI
VISUB

Description
Add
Add Immediate
Add Immediate Unsigned
Add Unsigned
Doubleword Add
Doubleword Add Immediate
Doubleword Add Immediate (Unsigned)
Doubleword Add Unsigned
Doubleword Subtract
Doubleword Subtract Unsigned
Subtract
Subtract Unsigned
Parallel Add Byte
Parallel Add Halfword
Parallel Add with Signed Saturation Byte
Parallel Add with Signed Saturation Halfword
Parallel Add with Signed Saturation Word
Parallel Add with Unsigned Saturation Byte
Parallel Add with Unsigned Saturation Halfword
Parallel Add with Unsigned Saturation Word
Parallel Add Word
Parallel Add/Subtract Halfword
Parallel Subtract Byte
Parallel Subtract Halfword
Parallel Subtract with Signed Saturation Byte
Parallel Subtract with Signed Saturation Halfword
Parallel Subtract with Signed Saturation Word
Parallel Subtract with Unsigned Saturation Byte
Parallel Subtract with Unsigned Saturation Halfword
Parallel Subtract with Unsigned Saturation Word
Parallel Subtract Word
Integer Add
Integer Add Immediate
Integer Subtract

Ref.
2
2
2
2
2
2
2
2
2
2
2
2
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
VPU0
VPU0
VPU0

6.1.2. Floating Point Addition and Subtraction
Inst.
ADD.S
ADDA.S
SUB.S
SUBA.S
VADD
VADDA

Description
Single Floating Point Add
Single Floating Point Add to Accumulator
Single Floating Point Subtract
Single Floating Point Subtract to Accumulator
Addition
ADD output to ACC

© SCEI
-382-

Ref.
5
5
5
5
VPU0
VPU0

SCE CONFIDENTIAL

Inst.
VADDAbc
VADDAi
VADDAq
VADDbc
VADDi
VADDq
VSUB
VSUBA
VSUBAbc
VSUBAi
VSUBAq
VSUBbc
VSUBi
VSUBq

EE Core Instruction Set Manual Version 6.0

Description
ADD broadcast bc field
ADD output to ACC broadcast I register
ADD output to ACC broadcast Q register
ADD output to ACC broadcast bc field
ADD broadcast I register
ADD broadcast Q register
Subtraction
SUB output ACC
SUB output to ACC broadcast bc field
SUB output to ACC broadcast I register
SUB output to ACC broadcast Q register
SUB broadcast bc field
SUB broadcast I register
SUB broadcast Q register

Ref.
VPU0
VPU0
VPU0
VPU0
VPU0
VPU0
VPU0
VPU0
VPU0
VPU0
VPU0
VPU0
VPU0
VPU0

6.1.3. Integer Multiplication and Division
Inst.
DIV
DIVU
MULT
MULTU
DIV1
DIVU1
MULT
MULT1
MULTU
MULTU1
PDIVBW
PDIVUW
PDIVW
PMULTH
PMULTUW
PMULTW

Description
Divide
Divide Unsigned
Multiply
Multiply Unsigned
Divide 1
Divide Unsigned 1
Multiply (3-operand)
Multiply 1
Multiply Unsigned (3-operand)
Multiply unsigned 1
Parallel Divide Broadcast Word
Parallel Divide Unsigned Word
Parallel Divide Word
Parallel Multiply Halfword
Parallel Multiply Unsigned Word
Parallel Multiply Word

Ref.
2
2
2
2
3
3
3
3
3
3
3
3
3
3
3
3

6.1.4. Floating Point Multiplication and Division
Inst.
DIV.S
MUL.S
MULA.S
VDIV
VMUL
VMULA
VMULAbc
VMULAi
VMULAq
VMULbc
VMULi
VMULq

Description
Single Floating Point Divide
Single Floating Point Multiply
Single Floating Point Multiply to Accumulator
Floating Divide
Multiply
MUL output to ACC
MUL output to ACC broadcast bc field
MUL output to ACC broadcast I register
MUL output to ACC broadcast Q register
MUL broadcast bc field
MUL broadcast I register
MUL broadcast Q register

Ref.
5
5
5
VPU0
VPU0
VPU0
VPU0
VPU0
VPU0
VPU0
VPU0
VPU0
© SCEI

-383-

SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

6.1.5. Integer Multiply-Add
Inst.
MADD
MADD1
MADDU
MADDU1
PHMADH
PHMSBH
PMADDH
PMADDUW
PMADDW
PMSUBH
PMSUBW

Description
Multiply / Add
Multiply / Add 1
Multiply / Add Unsigned
Multiply / Add Unsigned 1
Parallel Horizontal Multiply / Add Halfword
Parallel Horizontal Multiply / Subtract Halfword
Parallel Multiply / Add Halfword
Parallel Multiply / Add Unsigned Word
Parallel Multiply / Add Word
Parallel Multiply / Subtract Halfword
Parallel Multiply / Subtract Word

Ref.
3
3
3
3
3
3
3
3
3
3
3

6.1.6. Floating Point Multiply-Add
Inst.
MADD.S
MADDA.S
MSUB.S
MSUBA.S
VMADD
VMADDA
VMADDAbc
VMADDAi
VMADDAq
VMADDbc
VMADDi
VMADDq
VMSUB
VMSUBA
VMSUBAbc
VMSUBAi
VMSUBAq
VMSUBbc
VMSUBi
VMSUBq

Description
Single Floating Point Multiply and Add
Single Floating Point Multiply and Add to Accumulator
Single Floating Point Multiply and Subtract
Single Floating Point Multiply and Subtract from Accumulator
MUL and ADD (SUB)
MUL and ADD (SUB) output to ACC
MUL and ADD (SUB) output to ACC broadcast bc field
MUL and ADD (SUB) output to ACC broadcast I register
MUL and ADD (SUB) output to ACC broadcast Q register
MUL and ADD (SUB) broadcast bc field
MUL and ADD (SUB) broadcast I register
MUL and ADD (SUB) broadcast Q register
Multiply and SUB
Multiply and SUB output to ACC
Multiply and SUB output to ACC bc field
Multiply and SUB output to ACC I register
Multiply and SUB output to ACC Q register
Multiply and SUB broadcast bc field
Multiply and SUB broadcast I register
Multiply and SUB broadcast Q register

Ref.
5
5
5
5
VPU0
VPU0
VPU0
VPU0
VPU0
VPU0
VPU0
VPU0
VPU0
VPU0
VPU0
VPU0
VPU0
VPU0
VPU0
VPU0

6.1.7. Shift Operation
Inst.
DSRA
DSLL
DSLL32
DSLLV
DSRA32
DSRAV
DSRL
DSRL32
DSRLV

Description
Doubleword Shift Right Arithmetic
Doubleword Shift Left Logical
Doubleword Shift Left Logical + 32
Doubleword Shift Left Logical Variable
Doubleword Shift Right Arithmetic + 32
Doubleword Shift Right Arithmetic
Doubleword Shift Right Logical
Doubleword Shift Right Logical + 32
Doubleword Shift Right Logical Variable

© SCEI
-384-

Ref.
2
2
2
2
2
2
2
2
2

SCE CONFIDENTIAL

Inst.
SLL
SLLV
SRA
SRAV
SRL
SRLV
PSLLH
PSLLVW
PSLLW
PSRAH
PSRAVW
PSRAW
PSRLH
PSRLVW
PSRLW
QFSRV

EE Core Instruction Set Manual Version 6.0

Description
Shift Left Logical
Shift Left Logical Variable
Shift Right Arithmetic
Shift Right Arithmetic Variable
Shift Right Logical
Shift Right Logical Variable
Parallel Shift Left Logical Halfword
Parallel Shift Left Logical Variable Word
Parallel Shift Left Logical Word
Parallel Shift Right Arithmetic Halfword
Parallel Shift Right Arithmetic Variable Word
Parallel Shift Right Arithmetic Word
Parallel Shift Right Logical Halfword
Parallel Shift Right Logical Variable Word
Parallel Shift Right Logical Word
Quadword Funnel Shift Right Variable

Ref.
2
2
2
2
2
2
3
3
3
3
3
3
3
3
3
3

6.1.8. Logical Operation
Inst.
AND
ANDI
NOR
OR
ORI
XOR
XORI
PAND
PNOR
POR
PXOR
VIAND
VIOR

Description
AND
AND Immediate
NOR
OR
OR Immediate
Exclusive OR
Exclusive OR Immediate
Parallel AND
Parallel NOR
Parallel OR
Parallel XOR
Integer AND
Integer OR

Ref.
2
2
2
2
2
2
2
3
3
3
3
VPU0
VPU0

6.1.9. Comparison Operation
Inst.
SLT
SLTI
SLTIU
SLTU
PCEQB
PCEQH
PCEQW
PCGTB
PCGTH
PCGTW
C.EQ.S
C.F.S
C.LE.S

Description
Set on Less Than
Set on Less Than on Immediate
Set on Less Than on Immediate Unsigned
Set on Less Than Unsigned
Parallel Compare for Equal Byte
Parallel Compare for Equal Halfword
Parallel Compare for Equal Word
Parallel Compare for Greater Than Byte
Parallel Compare for Greater Than Halfword
Parallel Compare for Greater Than Word
Single Floating Point Compare
Single Floating Point Compare
Single Floating Point Compare

Ref.
2
2
2
2
3
3
3
3
3
3
5
5
5
© SCEI

-385-

SCE CONFIDENTIAL

Inst.
C.LT.S
VCLIP

EE Core Instruction Set Manual Version 6.0

Description
Single Floating Point Compare
Clipping

Ref.
5
VPU0

6.1.10. Maximum / Minimum Value
Inst.
PMAXH
PMAXW
PMINH
PMINW
MAX.S
MIN.S
VMAX
VMAXbc
VMAXi
VMINI
VMINIbc
VMINIi

Description
Parallel Maximum Halfword
Parallel Maximum Word
Parallel Minimum Halfword
Parallel Minimum Word
Single Floating Point Maximum
Single Floating Point Minimum
Maximum
Maximum broadcast bc field
Maximum broadcast I register
Minimum
Minimum broadcast bc field
Minimum broadcast I register

Ref.
3
3
3
3
5
5
VPU0
VPU0
VPU0
VPU0
VPU0
VPU0

6.1.11. Data Format Conversion
Inst.
PEXT5
PPAC5
CVT.S.W
CVT.W.S
VFTOI0
VFTOI12
VFTOI15
VFTOI4
VITOF0
VITOF12
VITOF15
VITOF4
VMR32

Description
Parallel Extend from 5 bits
Parallel Pack to 5 bits
32-bit Fixed Point Floating Point Convert to Single Floating Point
Single Floating Point Convert to 32-bit Fixed Point
Float to Integer, fixed point 0 bit
Float to Integer, fixed point 12 bits
Float to Integer, fixed point 15 bits
Float to Integer, fixed point 4 bits
Integer to Float, fixed point 0 bit
Integer to Float, fixed point 12 bits
Integer to Float, fixed point 15 bits
Integer to Float, fixed point 4 bits
Rotate right 32 bits

Ref.
3
3
5
5
VPU0
VPU0
VPU0
VPU0
VPU0
VPU0
VPU0
VPU0
VPU0

6.1.12. Exchange
Inst.
PCPYH
PCPYLD
PCPYUD
PEXCH
PEXCW
PEXEH
PEXEW
PEXTLB
PEXTLH
PEXTLW
PEXTUB
PEXTUH

Description
Parallel Copy Halfword
Parallel Copy Lower Doubleword
Parallel Copy Upper Doubleword
Parallel Exchange Center Halfword
Parallel Exchange Center Word
Parallel Exchange Even Halfword
Parallel Exchange Even Word
Parallel Extend Lower From Byte
Parallel Extend Lower From Halfword
Parallel Extend Lower From Word
Parallel Extend Upper From Byte
Parallel Extend Upper From Halfword

© SCEI
-386-

Ref.
3
3
3
3
3
3
3
3
3
3
3
3

SCE CONFIDENTIAL

Inst.
PEXTUW
PINTEH
PINTH
PPACB
PPACH
PPACW
PREVH
PROT3W

EE Core Instruction Set Manual Version 6.0

Description
Parallel Extend Upper From Word
Parallel Interleave Even Halfword
Parallel Interleave Halfword
Parallel Pack To Byte
Parallel Pack To Halfword
Parallel Pack To Word
Parallel Reverse Halfword
Parallel Rotate 3 Word

Ref.
3
3
3
3
3
3
3
3

6.1.13. Random Number
Inst.
VRGET
VRINIT
VRNEXT
VRXOR

Description
Random-unit get R register
Random-unit init R register
Random-unit next M sequence
Random-unit XOR R register

Ref.
VPU0
VPU0
VPU0
VPU0

6.1.14. Other Operations
Inst.
PABSH
PABSW
PLZCW
ABS.S
NEG.S
RSQRT.S
SQRT.S
VABS
VOPMSUB
VOPMULA
VRSQRT
VSQRT

Description
Parallel Absolute Halfword
Parallel Absolute Word
Parallel Leading Zero Count Word
Single Floating Point Absolute
Single Floating Point Negate
Single Floating Point Reciprocal Square Root
Single Floating Point Square Root
Absolute
Outer product MSUB
Outer product MULA
Floating reciprocal Square-root
Floating reciprocal Square

Ref.
3
3
3
5
5
5
5
VPU0
VPU0
VPU0
VPU0
VPU0

© SCEI
-387-

SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

6.2. Data Transfer Instructions
6.2.1. Instructions for Transferring between Registers
Inst.
MFHI
MFLO
MOVN
MOVZ
MTHI
MTLO
MFHI1
MFLO1
MTHI1
MTLO1
PMFHI
PMFHL
PMFLO
PMTHI
PMTHL
PMTLO
MFC1
MOV.S
MTC1
CFC2
CTC2
LQC2
QMFC2
QMTC2
SQC2
VMFIR
VMOVE
VMTIR

Description
Move From HI
Move From LO
Move on Register Not Equal to Zero
Move on Register Equal to Zero
Move To HI
Move To LO
Move From HI1
Move From LO1
Move To HI1
Move To LO1
Parallel Move From HI
Parallel Move From HI / LO
Parallel Move From LO
Parallel Move To HI
Parallel Move To HI / LO
Parallel Move To LO
Move Word from FPR
Single Floating Point Move
Move Word to FCR
Move Control From COP2
Move Control To COP2
Load Quadword to COP2
Quadword Move From COP2
Quadword Move To COP2
Store Quadword from COP2
Move From integer register
Move Floating register
Move To integer register

Ref.
2
2
2
2
2
2
3
3
3
3
3
3
3
3
3
3
5
5
5
VPU0
VPU0
VPU0
VPU0
VPU0
VPU0
VPU0
VPU0
VPU0

6.2.2. Load
Inst.
LB
LBU
LD
LDL
LDR
LH
LHU
LUI
LW
LWL
LWR
LWU

Description
Load Byte
Load Byte Unsigned
Load Doubleword
Load Doubleword Left
Load Doubleword Right
Load Halfword
Load Halfword Unsigned
Load Upper Immediate
Load Word
Load Word Left
Load Word Right
Load Word Unsigned

Ref.
2
2
2
2
2
2
2
2
2
2
2
2

© SCEI
-388-

SCE CONFIDENTIAL

Inst.
LQ
LWC1
VILWR
VLQD
VLQI

EE Core Instruction Set Manual Version 6.0

Description
Load Quadword
Load Word to FPR
Integer load word register
Load Quadword with pre-decrement
Load Quadword with post-increment

Ref.
3
5
VPU0
VPU0
VPU0

Description
Store Byte
Store Doubleword
Store Doubleword Left
Store Doubleword Right
Store Halfword
Store Word
Store Word Left
Store Word Right
Store Quadword
Store Word from FPR
Integer store word register
Store Quadword with pre-decrement
Store Quadword with post-increment

Ref.
2
2
2
2
2
2
2
2
3
5
VPU0
VPU0
VPU0

6.2.3. Store
Inst.
SB
SD
SDL
SDR
SH
SW
SWL
SWR
SQ
SWC1
VISWR
VSQD
VSQI

6.2.4. Special Data Transfer
Inst.
MFSA
MTSA
MTSAB
MTSAH
MFBPC
MFC0
MFDAB
MFDABM
MFDVB
MFDVBM
MFIAB
MFIABM
MFPC
MFPS
MTBPC
MTC0
MTDAB
MTDABM
MTDVB
MTDVBM
MTIAB
MTIABM
MTPC
MTPS

Description
Move From SA Register
Move To SA Register
Move Byte Count to SA Register
Move Halfword Count to SA Register
Move From Breakpoint Control
Move From COP0
Move From Data Address Breakpoint
Move From Data Address Breakpoint Mask
Move From Data Value Breakpoint
Move From Data Value Breakpoint Mask
Move From Instruction Address Breakpoint
Move From Instruction Address Breakpoint Mask
Move From Performance Counter
Move From Performance Event Specifier
Move To Breakpoint Control
Move To COP0
Move To Data Address Breakpoint
Move To Data Address Breakpoint Mask
Move To Data Value Breakpoint
Move To Data Value Breakpoint Mask
Move To Instruction Address Breakpoint
Move To Instruction Address Breakpoint Mask
Move From Performance Counter
Move From Performance Event Specifier

Ref.
3
3
3
3
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
© SCEI

-389-

SCE CONFIDENTIAL

Inst.
CFC1
CTC1

EE Core Instruction Set Manual Version 6.0

Description
Move Control Word from FCR
Move Control Word to FCR

Ref.
5
5

© SCEI
-390-

SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

6.3. Program Control Instructions
6.3.1. Conditional Branch
Inst.
BEQ
BEQL
BGEZ
BGEZL
BGTZ
BGTZL
BLEZ
BLEZL
BLTZ
BLTZL
BNE
BNEL
BC0F
BC0FL
BC0T
BC0TL
BC1F
BC1FL
BC1T
BC1TL
BC2F
BC2FL
BC2T
BC2TL

Description
Branch on Equal
Branch on Equal Likely
Branch on Greater Than or Equal to Zero
Branch on Greater Than or Equal to Zero And Link
Branch on Greater Than Zero
Branch on Greater Than Zero Likely
Branch on Less Than or Equal to Zero
Branch on Less Than or Equal to Zero Likely
Branch on Less Than Zero
Branch on Less Than Zero Likely
Branch on Not Equal
Branch on Not Equal Likely
Branch on COP0 False
Branch on COP0 False Likely
Branch on COP0 True
Branch on COP0 True Likely
Branch on FPU False
Branch on FPU False Likely
Branch on FPU True
Branch on FPU True Likely
Branch on COP2 False
Branch on COP2 False Likely
Branch on COP2 True
Branch on COP2 True Likely

Ref.
2
2
2
2
2
2
2
2
2
2
2
2
4
4
4
4
5
5
5
5
VPU0
VPU0
VPU0
VPU0

6.3.2. Jump
Inst.
J
JR

Description
Jump
Jump Register

Ref.
2
2

6.3.3. Subroutine Call
Inst.
BGEZAL
BGEZALL
BLTZAL
BLTZALL
JAL
JALR
VCALLMS
VCALLMSR

Description
Branch on Greater Than or Equal to Zero And Link
Branch on Greater Than or Equal to Zero And Link Likely
Branch on Less Than Zero And Link
Branch on Less Than Zero And Link Likely
Jump And Link
Jump And Link Register
Call micro sub-routine
Call micro sub-routine register

Ref.
2
2
2
2
2
2
VPU0
VPU0

© SCEI
-391-

SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

6.3.4. Break / Trap
Inst.
BREAK
SYSCALL
TEQ
TEQI
TGE
TGEI
TGEIU
TGEU
TLT
TLTI
TLTIU
TLTU
TNE
TNEI
ERET

Description
Break
System Call
Trap if Equal
Trap if Equal Immediate
Trap if Greater Than or Equal
Trap if Greater Than or Equal Immediate
Trap if Greater Than or Equal Immediate Unsigned
Trap if Greater Than or Equal Unsigned
Trap if Less Than
Trap if Less Than Immediate
Trap if Less Than Immediate Unsigned
Trap if Less Than Unsigned
Trap if Not Equal
Trap if Not Equal Immediate
Exception Return

© SCEI
-392-

Ref.
2
2
2
2
2
2
2
2
2
2
2
2
2
2
4

SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

6.4. Other Instructions
Inst.
SYNC.stype
VWAITQ
PREF
DI
EI
VNOP

Description
Synchronization
Wait Q register
Prefetch
Disable Interrupt
Enable Interrupt
No operation

Ref.
2
VPU0
2
4
4
VPU0

© SCEI
-393-

SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

(This page is left blank intentionally)

© SCEI
-394-

SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

7. Appendix OpCode Encoding
This section shows the instructions of the EE Core, COP0 and COP1 (FPU) according to the bit pattern of the
instruction codes. The characters shown in a bold italic type are instruction classes and their details are shown in
the attached tables.
Explanation of terms:
reserved
Undefined instruction. When executing, generates undefined instruction exception.
undefined
Undefined instruction. When executing, the operation is undefined.
unsupported
MIPS IV instructions that the EE Core does not support. If executing them, an
undefined instruction exception occurs.
*
EE Core-specific instructions (in the table of the CPU instruction)

© SCEI
-395-

SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

7.1. CPU Instructions
7.1.1. Instructions encoded by OpCode field
31

26

25

21

20

16

10

6

5

0

OpCode
6
Bits
28 - 26

5

5

5

5

6

0

1

2

3

4

5

6

7

000

001

010

011

100

101

110

111

0 000

SPECIAL

REGIMM

J

JAL

BEQ

BNE

BLEZ

BGTZ

1 001

ADDI

ADDIU

SLTI

SLTIU

ANDI

ORI

XORI

LUI

2 010

COP0

COP1

COP2

reserved

BEQL

BNEL

BLEZL

BGTZL

3 011

DADDI

DADDIU

LDL

LDR

MMI *

reserved

LQ *

SQ *

4 100

LB

LH

LWL

LW

LBU

LHU

LWR

LWU

5 101

SB

SH

SWL

SW

SDL

SDR

SWR

CACHE

6 110

unsupported

LWC1

unsupported

PREF

unsupported

unsupported

LQC2 **

LD

7 111

unsupported

SWC1

unsupported

reserved

unsupported

unsupported

SQC2 **

SD

Bits
31 - 29

** LQC2 and SQC2 are COP2 Instructions.

© SCEI
-396-

SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

7.1.2. SPECIAL Instruction Class
Instructions encoded by function field when OpCode = SPECIAL.
31

26

25

21

OpCode =
SPECIAL

16

10

6

5

0

function

6

Bits
2-0

20

5

5

5

5

6

0

1

2

3

4

5

6

7

000

001

010

011

100

101

110

111

0 000

SLL

reserved

SRL

SRA

SLLV

reserved

SRLV

SRAV

1 001

JR

JALR

MOVZ

MOVN

SYSCALL

BREAK

reserved

SYNC

2 010

MFHI

MTHI

MFLO

MTLO

DSLLV

reserved

DSRLV

DSRAV

3 011

MULT

MULTU

DIV

DIVU

unsupported

unsupported

unsupported

unsupported

4 100

ADD

ADDU

SUB

SUBU

AND

OR

XOR

NOR

5 101

MFSA *

MTSA *

SLT

SLTU

DADD

DADDU

DSUB

DSUBU

6 110

TGE

TGEU

TLT

TLTU

TEQ

reserved

TNE

reserved

7 111

DSLL

reserved

DSRL

DSRA

DSLL32

reserved

DSRL32

DSRA32

Bits
5-3

© SCEI
-397-

SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

7.1.3. REGIMM Instruction Class
Instructions encoded by rt field when OpCode = REGIMM.
31

26

25

21

OpCode =
REGIMM

16

10

6

5

0

rt

6

Bits
18 - 16

20

5

5

5

5

6

0

1

2

3

4

5

6

7

000

001

010

011

100

101

110

111

0 00

BLTZ

BGEZ

BLTZL

BGEZL

reserved

reserved

reserved

reserved

0 01

TGEI

TGEIU

TLTI

TLTIU

TEQI

reserved

TNEI

reserved

2 10

BLTZAL

BGEZAL

BLTZALL

BGEZALL

reserved

reserved

reserved

reserved

3 11

MTSAB *

MTSAH *

reserved

reserved

reserved

reserved

reserved

reserved

Bits
20 - 19

© SCEI
-398-

SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

7.2. EE Core-Specific Instructions
7.2.1. MMI Instruction Class
Instructions encoded by function field when OpCode = MMI.
31

26

25

21

OpCode =
MMI

16

10

6

5

0

function

6

Bits
2-0

20

5

5

5

5

6

0

1

2

3

4

5

6

7

000

001

010

011

100

101

110

111

0 000

MADD

MADDU

reserved

reserved

PLZCW

reserved

reserved

reserved

1 001

MMI0

MMI2

reserved

reserved

reserved

reserved

reserved

reserved

2 010

MFHI1

MTHI1

MFLO1

MTLO1

reserved

reserved

reserved

reserved

3 011

MULT1

MULTU1

DIV1

DIVU1

reserved

reserved

reserved

reserved

4 100

MADD1

MADDU1

reserved

reserved

reserved

reserved

reserved

reserved

5 101

MMI1

MMI3

reserved

reserved

reserved

reserved

reserved

reserved

6 110

PMFHL

PMTHL

reserved

reserved

PSLLH

reserved

PSRLH

PSRAH

7 111

reserved

reserved

reserved

reserved

PSLLW

reserved

PSRLW

PSRAW

Bits
5-3

© SCEI
-399-

SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

7.2.2. MMI0 Instruction Class
Instructions encoded by function filed when OpCode = MMI and bits 5..0 = MMI0.
31

26

OpCode =
MMI
6

Bits
7-6

25

21

5

20

16

10

5

5

0

1

2

3

00

01

10

11

0 000

PADDW

PSUBW

PCGTW

PMAXW

1 001

PADDH

PSUBH

PCGTH

PMAXH

2 010

PADDB

PSUBB

PCGTB

reserved

3 011

reserved

reserved

reserved

reserved

4 100

PADDSW

PSUBSW

PEXTLW

PPACW

5 101

PADDSH

PSUBSH

PEXTLH

PPACH

6 110

PADDSB

PSUBSB

PEXTLB

PPACB

7 111

reserved

reserved

PEXT5

PPAC5

Bits
10 - 8

© SCEI
-400-

6

5

function

MMI0

5

6

0

SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

7.2.3. MMI1 Instruction Class
Instructions encoded by function field when OpCode = MMI and bits 5..0 = MMI1.
31

26

OpCode =
MMI
6

Bits
7-6

25

21

5

20

16

10

5

5

0

1

2

3

00

01

10

11

0 000

reserved

PABSW

PCEQW

PMINW

1 001

PADSBH

PABSH

PCEQH

PMINH

2 010

reserved

reserved

PCEQB

reserved

3 011

reserved

reserved

reserved

reserved

4 100

PADDUW

PSUBUW

PEXTUW

reserved

5 101

PADDUH

PSUBUH

PEXTUH

reserved

6 110

PADDUB

PSUBUB

PEXTUB

QFSRV

7 111

reserved

reserved

reserved

reserved

Bits
10 - 8

6

5

function

MMI1

5

6

0

© SCEI
-401-

SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

7.2.4. MMI2 Instruction Class
Instructions encoded by function field when OpCode = MMI and bits 5..0 = MMI2.
31

26

OpCode =
MMI
6

Bits
7-6

25

21

5

20

16

10

5

5

0

1

2

3

00

01

10

11

0 000

PMADDW

reserved

PSLLVW

PSRLVW

1 001

PMSUBW

reserved

reserved

reserved

2 010

PMFHI

PMFLO

PINTH

reserved

3 011

PMULTW

PDIVW

PCPYLD

reserved

4 100

PMADDH

PHMADH

PAND

PXOR

5 101

PMSUBH

PHMSBH

reserved

reserved

6 110

reserved

reserved

PEXEH

PREVH

7 111

PMULTH

PDIVBW

PEXEW

PROT3W

Bits
10 - 8

© SCEI
-402-

6

5

function

MMI2

5

6

0

SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

7.2.5. MMI3 Instruction Class
Instructions encoded by function field when OpCode = MMI and bits 5..0 = MMI3.
31

26

25

OpCode =
MMI
6

Bits
7-6

21

5

20

16

10

5

5

0

1

2

3

00

01

10

11

0 000

PMADDUW

reserved

reserved

PSRAVW

1 001

reserved

reserved

reserved

reserved

2 010

PMTHI

PMTLO

PINTEH

reserved

3 011

PMULTUW

PDIVUW

PCPYUD

reserved

4 100

reserved

reserved

POR

PNOR

5 101

reserved

reserved

reserved

reserved

6 110

reserved

reserved

PEXCH

PCPYH

7 111

reserved

reserved

PEXCW

reserved

Bits
10 - 8

6

5

function

MMI3

5

6

0

© SCEI
-403-

SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

7.3. COP0 Instructions
7.3.1. COP0 Instruction Class
Instructions encoded by rs field when OpCode = COP0.
31

26

25

OpCode =
COP0

21

6

Bits
23 - 21

20

16

10

6

5

0

rs
5

5

5

5

6

0

1

2

3

4

5

6

7

000

001

010

011

100

101

110

111

0 00

MF0

reserved

reserved

reserved

MT0

reserved

reserved

reserved

1 01

BC0

reserved

reserved

reserved

reserved

reserved

reserved

reserved

2 10

C0

reserved

reserved

reserved

reserved

reserved

reserved

reserved

3 11

reserved

reserved

reserved

reserved

reserved

reserved

reserved

reserved

Bits
25 - 24

7.3.2. BC0 Instruction Class
Instructions encoded by rt field when OpCode field = COP0 and rs field = BC0.
31

26

25

21

20

16

10

6

5

0

OpCode =
COP0

rs =
BC0

Bits
18 - 16

0

1

2

3

4

5

6

7

000

001

010

011

100

101

110

111

0 00

BC0F

BC0T

BC0FL

BC0TL

reserved

reserved

reserved

reserved

1 01

reserved

reserved

reserved

reserved

reserved

reserved

reserved

reserved

2 10

reserved

reserved

reserved

reserved

reserved

reserved

reserved

reserved

3 11

reserved

reserved

reserved

reserved

reserved

reserved

reserved

reserved

6

Bits
20 - 19

rt

5

5

5

© SCEI
-404-

5

6

SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

7.3.3. C0 Instruction Class
Instructions encoded by function field when OpCode = COP0 and rs = C0.
31

26

25

21

20

16

10

6

5

0

OpCode =
COP0

rs =
C0

Bits
2-0

0

1

2

3

4

5

6

7

000

001

010

011

100

101

110

111

0 000

undefined

TLBR

TLBWI

undefined

undefined

undefined

TLBWR

undefined

1 001

TLBP

undefined

undefined

undefined

undefined

undefined

undefined

undefined

2 010

undefined

undefined

undefined

undefined

undefined

undefined

undefined

undefined

3 011

ERET

undefined

undefined

undefined

undefined

undefined

undefined

undefined

4 100

undefined

undefined

undefined

undefined

undefined

undefined

undefined

undefined

5 101

undefined

undefined

undefined

undefined

undefined

undefined

undefined

undefined

6 110

undefined

undefined

undefined

undefined

undefined

undefined

undefined

undefined

7 111

EI

DI

undefined

undefined

undefined

undefined

undefined

undefined

6

Bits
5-3

function

5

5

5

5

6

© SCEI
-405-

SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

7.4. COP1 Instructions
7.4.1. COP1 Instruction Class
Instructions encoded by rs field when OpCode = COP1.
31

26

25

OpCode =
COP0

21

6

Bits
23 - 21

20

16

10

6

5

0

rs
5

5

5

5

6

0

1

2

3

4

5

6

7

000

001

010

011

100

101

110

111

0 00

MFC1

reserved

CFC1

reserved

MTC1

reserved

CTC1

reserved

1 01

BC1

reserved

reserved

reserved

reserved

reserved

reserved

reserved

2 10

S

reserved

reserved

reserved

W

reserved

reserved

reserved

3 11

reserved

reserved

reserved

reserved

reserved

reserved

reserved

reserved

Bits
25 - 24

7.4.2. BC1 Instruction Class
Instructions encoded by rt field when OpCode field = COP1 and rs = BC1.
31

26

25

21

20

16

10

6

5

0

OpCode =
COP0

rs =
BC1

Bits
18 - 16

0

1

2

3

4

5

6

7

000

001

010

011

100

101

110

111

0 00

BC1F

BC1T

BC1FL

BC1TL

reserved

reserved

reserved

reserved

1 01

reserved

reserved

reserved

reserved

reserved

reserved

reserved

reserved

2 10

reserved

reserved

reserved

reserved

reserved

reserved

reserved

reserved

3 11

reserved

reserved

reserved

reserved

reserved

reserved

reserved

reserved

6

Bits
20 - 19

rt

5

5

5

© SCEI
-406-

5

6

SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

7.4.3. S Instruction Class
Instructions encoded by function field when OpCode = COP1 and rs = S.
31

26

25

21

20

16

10

6

5

0

OpCode =
COP0

rs =
S

Bits
2-0

0

1

2

3

4

5

6

7

000

001

010

011

100

101

110

111

0 000

ADD

SUB

MUL

DIV

SQRT

ABS

MOV

NEG

1 001

undefined

undefined

undefined

undefined

undefined

undefined

undefined

undefined

2 010

undefined

undefined

undefined

undefined

undefined

undefined

RSQRT

undefined

3 011

ADDA

SUBA

MULA

undefined

MADD

MSUB

MADDA

MSUBA

4 100

undefined

undefined

undefined

undefined

CVTW

undefined

undefined

undefined

5 101

MAX

MIN

undefined

undefined

undefined

undefined

undefined

undefined

6 110

C.F

undefined

C.EQ

undefined

C.LT

undefined

C.LE

undefined

7 111

undefined

undefined

undefined

undefined

undefined

undefined

undefined

undefined

6

Bits
5-3

function

5

5

5

5

6

© SCEI
-407-

SCE CONFIDENTIAL

EE Core Instruction Set Manual Version 6.0

7.4.4. W Instruction Class
Instructions encoded by function field when OpCode = COP1 and rs = W.
31

26

25

21

20

16

10

6

5

0

OpCode =
COP0

rs =
W

Bits
2-0

0

1

2

3

4

5

6

7

000

001

010

011

100

101

110

111

0 000

undefined

undefined

undefined

undefined

undefined

undefined

undefined

undefined

1 001

undefined

undefined

undefined

undefined

undefined

undefined

undefined

undefined

2 010

undefined

undefined

undefined

undefined

undefined

undefined

undefined

undefined

3 011

undefined

undefined

undefined

undefined

undefined

undefined

undefined

undefined

4 100

CVTS

undefined

undefined

undefined

undefined

undefined

undefined

undefined

5 101

undefined

undefined

undefined

undefined

undefined

undefined

undefined

undefined

6 110

undefined

undefined

undefined

undefined

undefined

undefined

undefined

undefined

7 111

undefined

undefined

undefined

undefined

undefined

undefined

undefined

undefined

6

Bits
5-3

function

5

5

5

© SCEI
-408-

5

6



---

Source Exif Data:

File Type                       : PDF
File Type Extension             : pdf
MIME Type                       : application/pdf
PDF Version                     : 1.4
Linearized                      : Yes
Encryption                      : Standard V1.2 (40-bit)
User Access                     : Print, Fill forms, Extract, Assemble, Print high-res
Modify Date                     : 2002:06:10 14:24:25-07:00
Create Date                     : 2002:05:31 17:58:33Z
Page Count                      : 408
Creation Date                   : 2002:05:31 17:58:33Z
Mod Date                        : 2002:06:10 14:24:25-07:00
Producer                        : Acrobat Distiller 5.0.5 (Windows)
Author                          : Sony Computer Entertainment
Metadata Date                   : 2002:06:10 14:24:25-07:00
Creator                         : Sony Computer Entertainment
Title                           : EE Core Instruction Set Manual
Page Mode                       : UseOutlines
Page Layout                     : SinglePage

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