EE Overview Manual

• EE OVERVIEW
  • 6th Edition, April 2002
• About This Manual
• Changes Since Release of 5th Edition
• Architecture Policy
  • Main Points of Architecture Policy
  • Expansion of Bandwidth
  • Geometry Engines in Parallel
  • Data Decompression/Unpack
  • Memory Architecture
• Architecture Overview
  • EE Block Configuration
  • EE Core: CPU
    • EE Core Features
    • Memory Map
    • Instruction Set Overview
  • VPU: Vector Operation Processor
    • VPU Architecture
    • VPU0
    • VPU1
    • VIF: VPU Interface
    • Operation Mode and Programming Model
    • VPU Instruction Set Overview
  • IPU: Image Data Processor
  • GIF: GS Interface
  • SIF: Sub-CPU Interface
• Functional Overview
  • Data Transfer via DMA
    • Sliced Transfer
    • Chain Mode Transfer
    • Interleave Transfer
    • Stall Control
    • MFIFO
  • Data Transfer to VPU
    • VIF Overview
    • VIF Packet
    • VIFcode Structure
    • Data Transfer by UNPACK
    • Double Buffering
  • Data Transfer to GS
    • Data Transfer Route
    • Data Format
    • PACKED Mode
    • REGLIST Mode
    • IMAGE Mode
  • Image Decompression by IPU