AMD64 Architecture Programmer’s Manual, Volume 3: General Purpose And System Instructions EN Programmer's Manual 3

• Contents
• Figures
• Tables
• Revision History
• Preface
  • About This Book
  • Audience
  • Organization
  • Definitions
    • Terms and Notation
    • Registers
    • Endian Order
  • Related Documents
• 1 Instruction Formats
  • 1.1 Instruction Byte Order
  • 1.2 Instruction Prefixes
    • 1.2.1 Summary of Legacy Prefixes
    • 1.2.2 Operand-Size Override Prefix
    • 1.2.3 Address-Size Override Prefix
    • 1.2.4 Segment-Override Prefixes
    • 1.2.5 Lock Prefix
    • 1.2.6 Repeat Prefixes
    • 1.2.7 REX Prefixes
  • 1.3 Opcode
  • 1.4 ModRM and SIB Bytes
  • 1.5 Displacement Bytes
  • 1.6 Immediate Bytes
  • 1.7 RIP-Relative Addressing
    • 1.7.1 Encoding
    • 1.7.2 REX Prefix and RIP-Relative Addressing
    • 1.7.3 Address-Size Prefix and RIP-Relative Addressing
• 2 Instruction Overview
  • 2.1 Instruction Subsets
  • 2.2 Reference-Page Format
  • 2.3 Summary of Registers and Data Types
    • 2.3.1 General-Purpose Instructions
    • 2.3.2 System Instructions
    • 2.3.3 128-Bit Media Instructions
    • 2.3.4 64-Bit Media Instructions
    • 2.3.5 x87 Floating-Point Instructions
  • 2.4 Summary of Exceptions
  • 2.5 Notation
    • 2.5.1 Mnemonic Syntax
    • 2.5.2 Opcode Syntax
    • 2.5.3 Pseudocode Definitions
• 3 General-Purpose Instruction Reference
  • AAA
  • AAD
  • AAM
  • AAS
  • ADC
  • ADD
  • AND
  • BOUND
  • BSF
  • BSR
  • BSWAP
  • BT
  • BTC
  • BTR
  • BTS
  • CALL (Near)
  • CALL (Far)
  • CBW CWDE CDQE
  • CWD CDQ CQO
  • CLC
  • CLD
  • CLFLUSH
  • CMC
  • CMOVcc
  • CMP
  • CMPS CMPSB CMPSW CMPSD CMPSQ
  • CMPXCHG
  • CMPXCHG8B CMPXCHG16B
  • CPUID
    • Testing for the CPUID Instruction
    • Standard Function 0 and Extended Function 8000_0000h
  • DAA
  • DAS
  • DEC
  • DIV
  • ENTER
  • IDIV
  • IMUL
  • IN
  • INC
  • INS INSB INSW INSD
  • INT
  • INTO
  • Jcc
  • JCXZ JECXZ JRCXZ
  • JMP (Near)
  • JMP (Far)
  • LAHF
  • LDS LES LFS LGS LSS
  • LEA
  • LEAVE
  • LFENCE
  • LODS LODSB LODSW LODSD LODSQ
  • LOOP LOOPE LOOPNE LOOPNZ LOOPZ
  • LZCNT
  • MFENCE
  • MOV
  • MOVD
  • MOVMSKPD
  • MOVMSKPS
  • MOVNTI
  • MOVS MOVSB MOVSW MOVSD MOVSQ
  • MOVSX
  • MOVSXD
  • MOVZX
  • MUL
  • NEG
  • NOP
  • NOT
  • OR
  • OUT
  • OUTS OUTSB OUTSW OUTSD
  • PAUSE
  • POP
  • POPA POPAD
  • POPCNT
  • POPF POPFD POPFQ
  • PREFETCH PREFETCHW
  • PREFETCHlevel
  • PUSH
  • PUSHA PUSHAD
  • PUSHF PUSHFD PUSHFQ
  • RCL
  • RCR
  • RET (Near)
  • RET (Far)
  • ROL
  • ROR
  • SAHF
  • SAL SHL
  • SAR
  • SBB
  • SCAS SCASB SCASW SCASD SCASQ
  • SETcc
  • SFENCE
  • SHL
  • SHLD
  • SHR
  • SHRD
  • STC
  • STD
  • STOS STOSB STOSW STOSD STOSQ
  • SUB
  • TEST
  • XADD
  • XCHG
  • XLAT
  • XLATB
  • XOR
• 4 System Instruction Reference
  • ARPL
  • CLGI
  • CLI
  • CLTS
  • HLT
  • INT 3
  • INVD
  • INVLPG
  • INVLPGA
  • IRET IRETD IRETQ
  • LAR
  • LGDT
  • LIDT
  • LLDT
  • LMSW
  • LSL
  • LTR
  • MONITOR
  • MOV (CRn)
  • MOV(DRn)
  • MWAIT
  • RDMSR
  • RDPMC
  • RDTSC
  • RDTSCP
  • RSM
  • SGDT
  • SIDT
  • SKINIT
  • SLDT
  • SMSW
  • STI
  • STGI
  • STR
  • SWAPGS
  • SYSCALL
  • SYSENTER
  • SYSEXIT
  • SYSRET
  • UD2
  • VERR
  • VERW
  • VMLOAD
  • VMMCALL
  • VMRUN
  • VMSAVE
  • WBINVD
  • WRMSR
• Appendix A Opcode and Operand Encodings
  • A.1 Opcode-Syntax Notation
  • A.2 Opcode Encodings
    • A.2.1 One-Byte Opcodes
    • A.2.2 Two-Byte Opcodes
    • A.2.3 rFLAGS Condition Codes for Two-Byte Opcodes
    • A.2.4 ModRM Extensions to One-Byte and Two-Byte Opcodes
    • A.2.5 ModRM Extensions to Opcodes 0F 01 and 0F AE
    • A.2.6 3DNow!™ Opcodes
    • A.2.7 x87 Encodings
    • A.2.8 rFLAGS Condition Codes for x87 Opcodes
  • A.3 Operand Encodings
    • A.3.1 ModRM Operand References
      • 16-Bit Register and Memory References
      • Register and Memory References for 32-Bit and 64-Bit Addressing
    • A.3.2 SIB Operand References
• Appendix B General-Purpose Instructions in 64-Bit Mode
  • B.1 General Rules for 64-Bit Mode
  • B.2 Operation and Operand Size in 64-Bit Mode
  • B.3 Invalid and Reassigned Instructions in 64-Bit Mode
  • B.4 Instructions with 64-Bit Default Operand Size
  • B.5 Single-Byte INC and DEC Instructions in 64-Bit Mode
  • B.6 NOP in 64-Bit Mode
  • B.7 Segment Override Prefixes in 64-Bit Mode
• Appendix C Differences Between Long Mode and Legacy Mode
• Appendix D Instruction Subsets and CPUID Feature Sets
  • D.1 Instruction Subsets
  • D.2 CPUID Feature Sets
  • D.3 Instruction List
• Appendix E Instruction Effects on RFLAGS
• Index