Evaluation Board With STM32L476ZGT6 MCU Eval User Manual
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UM1855
User manual
Evaluation board with STM32L476ZGT6 MCU
Introduction
The STM32L476G-EVAL evaluation board is designed as complete demonstration and
development platform for STMicroelectronics ARM® Cortex®-M4-core-based
STM32L476ZGT6 microcontroller with three I²C buses, three SPI and six USART ports,
CAN port, SWPMI, two SAI ports, 12-bit ADC, 12-bit DAC, LCD driver, internal 128-Kbyte
SRAM and 1-Mbyte Flash memory, Quad-SPI port, touch sensing capability, USB OTG FS
port, LCD controller, flexible memory controller (FMC), JTAG debug port.
STM32L476G-EVAL, shown in Figure 1, is used as reference design for user application
development, although it is not considered as final application.
A full range of hardware features on the board helps users to evaluate all on-board
peripherals such as USB, USART, digital microphones, ADC and DAC, dot-matrix TFT LCD,
LCD glass module, IrDA (supported up to version MB1144 C-01 of the board), LDR, SRAM,
NOR Flash memory device, Quad-SPI Flash memory device, microSD card, sigma-delta
modulators, smartcard with SWP, CAN transceiver, EEPROM, RF-EEPROM. Extension
headers allow connecting daughterboards or wrapping boards.
ST-LINK/V2-1 in-circuit debugger and flashing facility is integrated on the mainboard.
Figure 1. STM32L476G-EVAL evaluation board
1. Picture not contractual.
November 2016
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www.st.com
1
Contents
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Contents
1
2
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.2
Demonstration software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.3
Order code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.4
Unpacking recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Hardware layout and configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.1
2.1.1
Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.1.2
ST-LINK/V2-1 firmware upgrade . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.2
ETM trace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.3
Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.3.1
Supplying the board through ST-LINK/V2-1 USB port . . . . . . . . . . . . . . 15
2.3.2
Using ST-LINK/2-1 along with powering through CN22 power jack . . . 16
2.4
Clock references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.5
Reset sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.6
Boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.7
2.8
2.9
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ST-LINK/V2-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.6.1
Boot options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.6.2
Bootloader limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Audio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.7.1
Digital microphones . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.7.2
Headphones outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.7.3
Limitations in using audio features . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
USB OTG FS port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.8.1
STM32L476G-EVAL used as USB device . . . . . . . . . . . . . . . . . . . . . . . 23
2.8.2
STM32L476G-EVAL used as USB host . . . . . . . . . . . . . . . . . . . . . . . . 24
2.8.3
Configuration elements related with USB OTG FS port . . . . . . . . . . . . 24
2.8.4
Limitations in using USB OTG FS port . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.8.5
Operating voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
RS-232 and IrDA ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.9.1
RS-232 port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2.9.2
IrDA port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2.9.3
Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
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2.9.4
Operating voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2.10
LPUART port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.11
microSD card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.12
2.13
2.11.1
Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.11.2
Operating voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Motor control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2.12.1
Board modifications to enable motor control . . . . . . . . . . . . . . . . . . . . . 30
2.12.2
Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
CAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2.13.1
Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2.13.2
Operating voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2.14
Extension connectors CN6 and CN7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2.15
LCD glass module daughterboard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2.15.1
Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
2.16
TFT LCD panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
2.17
User LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
2.18
Physical input devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
2.18.1
2.19
Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Operational amplifier and comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
2.19.1
Operational amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
2.19.2
Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
2.20
Analog input, output, VREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
2.21
SRAM device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
2.22
2.23
2.21.1
Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
2.21.2
Operating voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
NOR Flash memory device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
2.22.1
Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
2.22.2
Operating voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
2.23.1
Operating voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
2.24
RF-EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
2.25
Quad-SPI Flash memory device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
2.26
2.25.1
Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
2.25.2
Operating voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Touch-sensing button . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
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2.26.1
2.27
Smartcard, SWP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
2.27.1
Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
2.27.2
Operating voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
2.28
Near-field communication (NFC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
2.29
Dual-channel sigma-delta modulators STPMS2L . . . . . . . . . . . . . . . . . . 51
2.30
3
Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
2.29.1
STPMS2L presentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
2.29.2
STPMS2L settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
2.29.3
STPMS2L power metering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
2.29.4
STPMS2L for PT100 measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
2.29.5
Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
STM32L476ZGT6 current consumption measurement . . . . . . . . . . . . . . 54
2.30.1
IDD measurement principle - analog part . . . . . . . . . . . . . . . . . . . . . . . 55
2.30.2
Low-power-mode IDD measurement principle - logic part . . . . . . . . . . . 56
2.30.3
IDD measurement in dynamic run mode . . . . . . . . . . . . . . . . . . . . . . . . 58
2.30.4
Calibration procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
3.1
RS-232 D-sub male connector CN9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
3.2
Power connector CN22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
3.3
LCD daughterboard connectors CN11 and CN14 . . . . . . . . . . . . . . . . . . 61
3.4
Extension connectors CN6 and CN7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
3.5
ST-LINK/V2-1 programming connector CN16 . . . . . . . . . . . . . . . . . . . . . 65
3.6
ST-LINK/V2-1 Standard-B USB connector CN17 . . . . . . . . . . . . . . . . . . . 65
3.7
JTAG connector CN15
3.8
ETM trace debugging connector CN12 . . . . . . . . . . . . . . . . . . . . . . . . . . 67
3.9
microSD card connector CN18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
3.10
ADC/DAC connector CN8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
3.11
RF-EEPROM daughterboard connector CN3 . . . . . . . . . . . . . . . . . . . . . 69
3.12
Motor control connector CN2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
3.13
USB OTG FS Micro-AB connector CN1 . . . . . . . . . . . . . . . . . . . . . . . . . . 70
3.14
CAN D-sub male connector CN5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
3.15
NFC connector CN13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Appendix A Schematic diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
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Appendix B Federal Communications Commission (FCC)
and Industry Canada (IC) Compliance Statements. . . . . . . . . . . . . 99
B.1
B.2
4
FCC Compliance Statement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
B.1.1
Part 15.19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
B.1.2
Part 15.105 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
B.1.3
Part 15.21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
IC Compliance Statement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
B.2.1
Compliance Statement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
B.2.2
Déclaration de conformité. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
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List of tables
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List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
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Setting of configuration elements for trace connector CN12 . . . . . . . . . . . . . . . . . . . . . . . 14
Power-supply-related jumper settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
X1-crystal-related solder bridge settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
X2-crystal-related solder bridge settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Boot selection switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Bootloader-related jumper setting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Digital microphone-related jumper settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Configuration elements related with USB OTG FS port . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Settings of configuration elements for RS-232 and IrDA ports . . . . . . . . . . . . . . . . . . . . . . 26
Hardware settings for LPUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Terminals of CN18 microSD slot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Motor control terminal and function assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
CAN related jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
LCD-daughterboard-related configuration elements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
LCD glass element mapping - segments 0 to 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
LCD glass element mapping - segments 10 to 19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
LCD glass element mapping - segments 20 to 29 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
LCD glass element mapping - segments 30 to 39 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Access to TFT LCD resources with FMC address lines A0 and A1 . . . . . . . . . . . . . . . . . . 39
Assignment of CN19 connector terminals of TFT LCD panel . . . . . . . . . . . . . . . . . . . . . . . 39
Port assignment for control of LED indicators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Port assignment for control of physical input devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Setting of jumpers related with potentiometer and LDR . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
SRAM chip select configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
NOR Flash memory-related configuration elements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Configuration elements related with Quad-SPI device . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Touch-sensing-related configuration elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Assignment of ports for ST8024CDR control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Configuration elements related with smartcard and SWP . . . . . . . . . . . . . . . . . . . . . . . . . 49
CN13 NFC connector terminal assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
JP11 jumper settings during IDD measurement with calibration . . . . . . . . . . . . . . . . . . . . 59
RS-232 D-sub (DE-9M) connector CN9 with HW flow control and ISP support . . . . . . . . . 60
CN11 and CN14 daughterboard connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Daughterboard extension connector CN6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Daughterboard extension connector CN7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
USB Standard-B connector CN17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
JATG debugging connector CN15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Trace debugging connector CN12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
microSD card connector CN18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Analog input-output connector CN8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
RF-EEPROM daughterboard connector CN3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Motor control connector CN2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
USB OTG FS Micro-AB connector CN1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
CAN D-sub (DE-9M) 9-pins male connector CN5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
NFC CN13 terminal assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
DocID027351 Rev 5
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List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Figure 40.
Figure 41.
Figure 42.
Figure 43.
Figure 44.
Figure 45.
Figure 46.
Figure 47.
Figure 48.
STM32L476G-EVAL evaluation board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
STM32L476G-EVAL hardware block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
STM32L476G-EVAL main component layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
USB composite device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
CN22 power jack polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
CN20, CN21 top view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
PCB top-side rework for motor control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
PCB underside rework for motor control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
LCD glass module daughterboard in display position. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
LCD glass module daughterboard in I/O-bridge position . . . . . . . . . . . . . . . . . . . . . . . . . . 34
LCD glass display element mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
NFC board plugged into STM32L476G-EVAL board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Routing of STPMS2L dual-channel sigma-delta modulators . . . . . . . . . . . . . . . . . . . . . . . 52
Power measurement principle schematic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
STPMS2L power metering schematic diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Temperature measurement principle schematic diagram. . . . . . . . . . . . . . . . . . . . . . . . . . 54
Schematic diagram of the analog part of IDD measurement . . . . . . . . . . . . . . . . . . . . . . . 56
Schematic diagram of logic part of low-power-mode IDD measurement . . . . . . . . . . . . . . 57
Low-power-mode IDD measurement timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
RS-232 D-sub (DE-9M) 9-pole connector (front view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Power supply connector CN22 (front view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
USB type B connector CN17 (front view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
JTAG debugging connector CN15 (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Trace debugging connector CN12 (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
microSD card connector CN18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Analog input-output connector CN8 (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
RF-EEPROM daughterboard connector CN3 (front view) . . . . . . . . . . . . . . . . . . . . . . . . . 69
Motor control connector CN2 (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
USB OTG FS Micro-AB connector CN1 (front view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
CAN D-sub (DE-9M) 9-pole male connector CN5 (front view) . . . . . . . . . . . . . . . . . . . . . . 71
NFC female connector CN13 (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
STM32L476G-EVAL top . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
MCU, LCD daughterboard and I/O expander interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . 75
STM32L476G-EVAL MCU part 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
STM32L476G-EVAL MCU part 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
LCD glass module daughterboard connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
I/O expander . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Smartcard, SWP and NFC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
USART and IrDA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
SRAM and NOR Flash memory devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
TFT LCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Extension connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Quad-SPI Flash memory device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
microSD card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Physical control peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
CAN transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Touch-sensing device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
DocID027351 Rev 5
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8
List of figures
Figure 49.
Figure 50.
Figure 51.
Figure 52.
Figure 53.
Figure 54.
Figure 55.
Figure 56.
8/101
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USB_OTG_FS port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
IDD measurement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Audio codec device. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
STPMS2L and PT100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
RF-EEPROM and EEPROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Motor control connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
JTAG and trace debug connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
ST-LINK/V2-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
DocID027351 Rev 5
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Overview
1
Overview
1.1
Features
•
STM32L476ZGT6 microcontroller with 1-Mbyte Flash memory and 128-Kbyte RAM
•
Four power supply options: power jack, ST-LINK/V2-1 USB connector, USB OTG FS
connector, daughterboard
•
Microcontroller supply voltage: 3.3 V or range from 1.71 V to 3.6 V
•
Two MEMS digital microphones
•
Two jack outputs for stereo audio headphone with independent content
•
Slot for microSD card supporting SD, SDHC, SDXC
•
4-Gbyte microSD card bundled
•
16-Mbit (1M x 16 bit) SRAM device
•
128-Mbit (8M x 16 bit) NOR Flash memory device
•
256-Mbit Quad-SPI Flash memory device with double transfer rate (DTR) support
•
RF-EEPROM with I²C bus
•
EEPROM supporting 1 MHz I²C-bus communication speed
•
RS-232 port configurable for communication or MCU flashing
•
IrDA transceiver (only supported up to MB1144 C-01 version of the board, no more
supported from MB1144 C-02 version)
•
USB OTG FS Micro-AB port
•
CAN 2.0A/B-compliant port
•
Joystick with four-way controller and selector
•
Reset and wake-up / tamper buttons
•
Touch-sensing button
•
Light-dependent resistor (LDR)
•
Potentiometer
•
Coin battery cell for power backup
•
LCD glass module daughterboard (MB979) with 40x8-segment LCD driven directly by
STM32L476ZGT6
•
2.8-inch 320x240 dot-matrix color TFT LCD panel with resistive touchscreen
•
Smartcard connector and SWP support
•
NFC transceiver connector
•
Connector for ADC input and DAC output
•
Power-metering demonstration with dual-channel, sigma-delta modulator
•
PT100 thermal sensor with dual-channel, sigma-delta modulator
•
MCU current consumption measurement circuit
•
Access to comparator and operational amplifier of STM32L476ZGT6
•
Extension connector for motor control module
•
JTAG/SWD, ETM trace debug support, user interface through USB virtual COM port,
embedded ST-LINK/V2-1 debug and flashing facility
•
Extension connector for daughterboard
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Overview
1.2
UM1855
Demonstration software
Demonstration software is preloaded in the STM32L476ZGT6 Flash memory, for easy
demonstration of the device peripherals in stand-alone mode. For more information and to
download the latest available version, refer to the STM32L476G-EVAL demonstration
software available on the www.st.com website.
1.3
Order code
To order the evaluation board based on the STM32L476ZGT6 MCU, use the order code
STM32L476G-EVAL.
1.4
Unpacking recommendations
Before the first use, make sure that, no damage occurred to the board during shipment and
no socketed components are loosen in their sockets or fallen into the plastic bag.
In particular, pay attention to the following components:
1.
Quartz crystal (X2 position)
2.
microSD card in its CN18 receptacle
3.
RF-EEPROM board (ANT7-M24LR-A) in its CN3 connector
For product information related with STM32L476ZGT6 microcontroller, visit www.st.com
website.
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2
Hardware layout and configuration
Hardware layout and configuration
The STM32L476G-EVAL evaluation board is designed around STM32L476ZGT6 target
microcontroller in LQFP 144-pin package. Figure 2 illustrates STM32L476ZGT6
connections with peripheral components. Figure 3 shows the location of main components
on the evaluation board.
Figure 2. STM32L476G-EVAL hardware block diagram
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Note:
If the STM32L476G-EVAL board version is greater than or equal to MB1144 C-02, the IrDA
feature is not populated. Any mention of the IrDA feature in this User manual refers to the
previous versions of the board (up to MB1144 C-01). The version of the board is written on
the sticker placed on bottom side of the board.
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Hardware layout and configuration
UM1855
Figure 3. STM32L476G-EVAL main component layout
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2.1
Hardware layout and configuration
ST-LINK/V2-1
ST-LINK/V2-1 facility for debug and flashing of STM32L476ZGT6, is integrated on the
STM32L476G-EVAL evaluation board.
Compared to ST-LINK/V2 stand-alone tool available from STMicroelectronics,
ST-LINK/V2-1 offers new features and drops some others.
New features:
•
USB software re-enumeration
•
Virtual COM port interface on USB
•
Mass storage interface on USB
•
USB power management request for more than 100mA power on USB
Features dropped:
•
SWIM interface
The USB connector CN17 can be used to power STM32L476G-EVAL regardless of
the ST-LINK/V2-1 facility use for debugging or for flashing STM32L476ZGT6. This holds
also when ST-LINK/V2 stand-alone tool is connected to CN12 or CN15 connector and used
for debugging or flashing STM32L476ZGT6. Section 2.3 provides more detail on powering
STM32L476G-EVAL.
For full detail on both versions of the debug and flashing tool, the stand-alone ST-LINK/V2
and the embedded ST-LINK/V2-1, refer to www.st.com.
2.1.1
Drivers
Before connecting STM32L476G-EVAL to a Windows 7, Windows 8 or Windows XP PC via
USB, a driver for ST-LINK/V2-1 must be installed. It can be downloaded from www.st.com.
In case the STM32L476G-EVAL evaluation board is connected to the PC before installing
the driver, the Windows device manager may report some USB devices found on
STM32L476G-EVAL as “Unknown”. To recover from this situation, after installing the
dedicated driver downloaded from www.st.com, the association of “Unknown” USB devices
found on STM32L476G-EVAL to this dedicated driver must be updated in the device
manager manually. It is recommended to proceed using USB Composite Device line, as
shown in Figure 4.
Figure 4. USB composite device
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Hardware layout and configuration
2.1.2
UM1855
ST-LINK/V2-1 firmware upgrade
For its own operation, ST-LINK/V2-1 employs a dedicated MCU with Flash memory. Its
firmware determines ST-LINK/V2-1 functionality and performance. The firmware may evolve
during the life span of STM32L476G-EVAL to include new functionality, fix bugs or support
new target microcontroller families. It is therefore recommended to keep ST-LINK/V2-1
firmware up to date. The latest version is available from www.st.com.
2.2
ETM trace
The connector CN12 can output trace signals used for debug. By default, the evaluation
board is configured such that, STM32L476ZGT6 signals PE2 through PE5 are not
connected to trace outputs Trace_D0, Trace_D1, Trace_D2, Trace_D3 and Trace_CK of
CN12. They are used for other functions.
Table 1 shows the setting of configuration elements to shunt PE2, PE3, PE4 and PE5 MCU
ports to CN12 connector, to use them as debug trace signals.
Table 1. Setting of configuration elements for trace connector CN12
Element
R103
SB26
Setting
R103 in
SB26 open
R103 out
SB26 closed
R104 in
R104
R104 out
R84
SB40
R85
SB38
R86
SB39
R84 in
SB40 open
R84 out
SB40 closed
R85 in
SB38 open
R85 out
SB38 closed
R86 in
SB39 open
R86 out
SB39 closed
Use of PE2, PE3, PE4, PE5 terminals of STM32L476ZGT6
Default setting.
PE2 connected to LCDSEG38 and memory address line A23.
PE2 connected to TRACE_CK on CN12. A23 pulled down.
Default setting.
PE3 connected to LCDSEG39 and memory address line A19.
PE3 connected to TRACE_D0 on CN12. A19 pulled down.
Default setting.
PE4 connected to memory address line A20.
PE4 connected to TRACE_D1 on CN12. A20 pulled down.
Default setting.
PE5 connected to memory address line A21.
PE5 connected to TRACE_D2 on CN12. A21 pulled down.
Default setting.
PE6 is used for address bit A22.
PE6 connected to TRACE_D3 on CN12. A22 pulled down.
Warning: Enabling the CN12 trace outputs through hardware modifications described in
Table 1 results in reducing the memory address bus width to 19 address lines and so the
addressable space to 512 Kwords of 16 bits. As a consequence, the on-board SRAM and
NOR Flash memory usable capacity is reduced to 8 Mbits.
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2.3
Hardware layout and configuration
Power supply
STM32L476G-EVAL evaluation board is designed to be powered from 5 V DC power
source. It incorporates a precise polymer Zener diode (Poly-Zen) protecting the board from
damage due to wrong power supply. One of the following four 5V DC power inputs can be
used, upon an appropriate board configuration:
•
Power jack CN22, marked PSU_E5V on the board. A jumper must be placed in PSU
location of JP17. The positive pole is on the center pin as illustrated in Figure 5.
•
Standard-B USB receptacle CN17 of ST-LINK/V2-1, offering enumeration feature
described in Section 2.3.1.
•
Micro-AB USB receptacle CN1 of USB OTG interface, marked OTG_FS on the board.
Up to 500mA can be supplied to the board in this way.
•
Pin 28 of CN6 extension connector for custom daughterboards, marked D5V on the
board.
No external power supply is provided with the board.
LD7 red LED turns on when the voltage on the power line marked as +5V is present. All
supply lines required for the operation of the components on STM32L476G-EVAL are
derived from that +5V line.
Table 2 describes the settings of all jumpers related with powering STM32L476G-EVAL and
extension board. VDD_MCU is STM32L476ZGT6 digital supply voltage line. It can be
connected to either fixed 3.3 V or to an adjustable voltage regulator controlled with RV1
potentiometer and producing a range of voltages between 1.71 V and 3.6 V.
2.3.1
Supplying the board through ST-LINK/V2-1 USB port
To power STM32L476G-EVAL in this way, the USB host (a PC) gets connected with the
STM32L476G-EVAL board’s Standard-B USB receptacle, via a USB cable. This event starts
the USB enumeration procedure. In its initial phase, the host’s USB port current supply
capability is limited to 100 mA. It is enough because only ST-LINK/V2-1 part of
STM32L476G-EVAL draws power at that time. If the jumper header JP18 is open, the U37
ST890 power switch is set to OFF position, which isolates the remainder of
STM32L476G-EVAL from the power source. In the next phase of the enumeration
procedure, the host PC informs the ST-LINK/V2-1 facility of its capability to supply up to
300 mA of current. If the answer is positive, the ST-LINK/V2-1 sets the U37 ST890 switch to
ON position to supply power to the remainder of the STM32L476G-EVAL board. If the PC
USB port is not capable of supplying up to 300 mA of current, the CN22 power jack can be
used to supply the board.
Should a short-circuit occur on the board, the ST890 power switch protects the USB port of
the host PC against a current demand exceeding 600 mA, In such an event, the LD9 LED
lights on.
The STM32L476G-EVAL board can also be supplied from a USB power source not
supporting enumeration, such as a USB charger. In this particular case, the JP18 header
must be fitted with a jumper as shown in Table 2. ST-LINK/V2-1 turns the ST890 power
switch ON regardless of enumeration procedure result and passes the power
unconditionally to the board.
The LD7 red LED turns on whenever the whole board is powered.
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Using ST-LINK/2-1 along with powering through CN22 power jack
It can happen that the board requires more than 300 mA of supply current. It cannot be
supplied from host PC connected to ST-LINK/2-1 USB port for debugging or flashing
STM32L476ZGT6. In such a case, the board can be supplied through CN22 (marked PSU
_E5V on the board).
To do this, it is important to power the board before connecting it with the host PC, which
requires the following sequence to be respected:
1.
Set the jumper in JP15 header in PSU position
2.
Connect the external 5 V power source to CN22
3.
Check the red LED LD7 is turned on
4.
Connect host PC to USB connector CN17
In case the board demands more than 300 mA and the host PC is connected via USB
before the board is powered from CN22, there is a risk of the following events to occur, in
the order of severity:
1.
The host PC is capable of supplying 300 mA (the enumeration succeeds) but it does
not incorporate any over-current protection on its USB port. It is damaged due to overcurrent.
2.
The host PC is capable of supplying 300 mA (the enumeration succeeds) and it has a
built-in over-current protection on its USB port, limiting or shutting down the power out
of its USB port when the excessive current demand from STM32L476G-EVAL is
detected. This causes an operating failure to STM32L476G-EVAL.
3.
The host PC is not capable of supplying 300 mA (the enumeration fails) so
ST-LINK/V2-1 does not supply the remainder of STM32L476G-EVAL from its USB port
VBUS line.
Figure 5. CN22 power jack polarity
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Hardware layout and configuration
Table 2. Power-supply-related jumper settings
Jumper array
Jumper setting
JP17
3688967/.'9
Configuration
STM32L476G-EVAL is supplied through CN22 power
jack (marked PSU_E5V). CN6 extension connector
does not pass the 5 V of STM32L476G-EVAL to
daughterboard.
JP17
STM32L476G-EVAL is supplied through CN1 Micro-AB
USB connector. CN6 extension connector does not
pass the 5 V of STM32L476G-EVAL to daughterboard.
3688967/.'9
JP17
JP17
Power source
selector
3688967/.'9
Default setting.
STM32L476G-EVAL is supplied through CN17
Standard-B USB connector. CN6 extension connector
does not pass the 5 V of STM32L476G-EVAL to
daughterboard.
Check JP18 setting in Table 2.
JP17
STM32L476G-EVAL is supplied through pin 28 of CN6
extension connector.
3688967/.'9
JP17
3688967/.'9
STM32L476G-EVAL is supplied through CN22 power
jack (marked PSU_E5V). CN6 extension connector
passes the 5 V of STM32L476G-EVAL to
daughterboard. Make sure to disconnect from the
daughterboard any power supply that could generate
conflict with the power supply on CN22 power jack.
JP12
Vbat is connected to battery.
JP12
Vbat connection
JP12
Default setting.
Vbat is connected to VDD.
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Table 2. Power-supply-related jumper settings (continued)
Jumper array
Jumper setting
JP2
JP2
VDD_MCU
connection
JP2
JP10
JP10
VDDA
connection
JP10
JP1
JP1
VDD_USB
connection
JP3
JP18
Powering
through USB of
ST-LINK/V2-1
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VDD_MCU is connected to voltage in the range from
+1.71 V to +3.6 V, adjustable with potentiometer RV1.
Default setting.
VDDA terminal of STM32L476ZGT6 is connected with
VDD_MCU.
VDDA terminal of STM32L476ZGT6 is connected to
+3.3 V.
Default setting.
VDD_USB (VDDUSB terminal of STM32L476ZGT6) is
connected with VDD_MCU.
VDD_USB is connected to +3.3V.
Default setting.
VDD_IO (VDDIO2 terminals of STM32L476ZGT6) is
connected with VDD_MCU
JP3
JP18
Default setting.
VDD_MCU (VDD terminals of STM32L476ZGT6) is
connected to fixed +3.3 V.
JP1
JP3
VDD_IO
connection
Configuration
JP18
VDD_IO is open.
Default setting.
Standard-B USB connector CN17 of ST-LINK/V2-1 can
supply power to the STM32L476G-EVAL board
remainder, depending on host PC USB port’s powering
capability declared in the enumeration.
Standard-B USB connector CN17 of ST-LINK/V2-1
supplies power to the STM32L476G-EVAL board
remainder. Setting for powering the board through
CN17 using USB charger.
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2.4
Hardware layout and configuration
Clock references
Two clock references are available on STM32L476G-EVAL for the STM32L476ZGT6 target
microcontroller:
•
32.768 kHz crystal X1, for embedded RTC
•
8 MHz crystal X2, for main clock generator
The main clock can also be generated using an internal RC oscillator. The X2 crystal is in a
socket. It can be removed when the internal RC oscillator is used.
Table 3. X1-crystal-related solder bridge settings
Solder
bridge
Setting
Description
Open
Default setting.
PC14-OSC32_IN terminal is not routed to extension connector CN7. X1 is
used as clock reference.
Closed
PC14-OSC32_IN is routed to extension connector CN7.
R87 must be removed, for X1 quartz circuit not to disturb clock reference
or source on daughterboard.
SB41
Open
SB33
Closed
Default setting.
PC15-OSC32_OUT terminal is not routed to extension connector CN7.
X1 is used as clock reference.
PC15-OSC32_OUT is routed to extension connector CN7.
R88 must be removed, for X1 quartz circuit not to disturb clock reference
on daughterboard.
Table 4. X2-crystal-related solder bridge settings
Solder
bridge
Setting
Open
Default setting.
PH0-OSC_IN terminal is not routed to extension connector CN7. X2 is
used as clock reference.
Closed
PH0-OSC_IN is routed to extension connector CN7.
X2 and C54 must be removed, in order not to disturb clock reference or
source on daughterboard.
SB24
Open
Default setting.
PH1-OSC_OUT terminal is not routed to extension connector CN7. X2 is
used as clock reference.
Closed
PH1-OSC_OUT is routed to extension connector CN7.
R95 must be removed, in order not to disturb clock reference or source on
daughterboard.
SB23
2.5
Configuration
Reset sources
Reset signal of the STM32L476G-EVAL board is active low.
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Sources of reset are:
•
reset button B1
•
JTAG/SWD connector CN15 and ETM trace connector CN12 (reset from debug tools)
•
through extension connector CN7, pin 32 (reset from daughterboard)
•
ST-LINK/V2-1
•
RS-232 connector CN9, terminal 8 (CTS signal), if JP9 is closed (open by default)
2.6
Boot
2.6.1
Boot options
After reset, the STM32L476ZGT6 MCU can boot from the following embedded memory
locations:
•
main (user, non-protected) Flash memory
•
system (protected) Flash memory
•
RAM, for debugging
The microcontroller is configured to one of the listed boot options by setting the
STM32L476ZGT6 port BOOT0 level by the switch SW1 and by setting nBOOT1 bit of
FLASH_OPTR option bytes register, as shown in Table 5. Depending on JP8, BOOT0 level
can be forced high and, SW1 action overruled, by DSR line of RS-232 connector CN9, as
shown in Table 6. This can be used to force the execution of bootloader and start user Flash
memory flashing process (ISP) from RS-232 interface.
The option bytes of STM32L476ZGT6 and their modification procedure are described in the
reference manual RM0351. The application note AN2606 details the bootloader mechanism
and configurations.
Table 5. Boot selection switch
Switch
Setting
Description
Default setting.
BOOT0 line is tied low. STM32L476ZGT6 boots from user Flash
memory.
SW1
BOOT0 line is tied high. STM32L476ZGT6 boots from system Flash
memory (nBOOT1 bit of FLASH_OPTR register is set high) or from
RAM (nBOOT1 is set low).
Table 6. Bootloader-related jumper setting
Jumper
Setting
JP8
JP8
JP8
20/101
Description
Default setting.
BOOT0 level only depends on SW1 switch position
BOOT0 can be forced high with terminal 6 of CN9 connector (RS-232
DSR line). This configuration is used to allow the device connected via
RS-232 to initiate STM32L476ZGT6 flashing process.
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2.6.2
Hardware layout and configuration
Bootloader limitations
Boot from system Flash memory results in executing bootloader code stored in the system
Flash memory protected against write and erase. This allows in-system programming (ISP),
that is, flashing the MCU user Flash memory. It also allows writing data into RAM. The data
come in via one of the communication interfaces such as USART, SPI, I²C bus, USB or
CAN.
Bootloader version can be identified by reading Bootloader ID at the address 0x1FFF6FFE.
The STM32L476ZGT6 part soldered on the STM32L476G-EVAL main board is marked with
a date code corresponding to its date of manufacture. STM32L476ZGT6 parts with the date
code prior or equal to week 22 of 2015 are fitted with bootloader V 9.0 affected by the
limitations to be worked around, as described hereunder. Parts with the date code starting
week 23 of 2015 contain bootloader V9.2 in which the limitations no longer exist.
To locate the visual date code information on the STM32L476ZGT6 package, refer to its
datasheet (DS10198) available on www.st.com, section Package Information. Date code
related portion of the package marking takes Y WW format, where Y is the last digit of the
year and WW is the week. For example, a part manufactured in week 23 of 2015 bares the
date code 5 23.
Bootloader ID of the bootloader V 9.0 is 0x90.
The following limitations exist in the bootloader V 9.0:
1.
RAM data get corrupted when written via USART/SPI/I2C/USB interface
Description:
Data write operation into RAM space via USART, SPI, I²C bus or USB results in wrong
or no data written.
Workaround:
To correct the issue of wrong write into RAM, download STSW-STM32158 bootloader
V 9.0 patch package from www.st.com and load "Bootloader V9.0 SRAM patch" to the
MCU, following the information in readme.txt file available in the package.
2.
User Flash memory data get corrupted when written via CAN interface
Description:
Data write operation into user Flash memory space via CAN interface results in wrong
or no data written.
Workaround:
To correct the issue of wrong write into Flash memory, download STSW-STM32158
bootloader V 0.9 patch package from www.st.com and load "Bootloader V9.0 CAN
patch" to the MCU, following the information in readme.txt file available in the package.
2.7
Audio
A codec connected to SAI interface of STM32L476ZGT6 supports TDM feature of the SAI
port. TDM feature offers to STM32L476ZGT6 the capability to stream two independent
stereo audio channels to two separate stereo analog audio outputs, simultaneously.
There are two digital microphones on board of STM32L476G-EVAL.
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Digital microphones
U35 and U36 on board of STM32L476G-EVAL are MP34DT01TR MEMS digital omnidirectional microphones providing PDM (pulse density modulation) outputs. To share the
same data line, their outputs are interlaced. The combined data output of the microphones
is directly routed to STM32L476ZGT6 terminals, thanks to the integrated input digital filters.
The microphones are supplied with programmable clock generated directly by
STM32L476ZGT6.
As an option, the microphones can be connected to U29, Wolfson audio codec device,
WM8994. In that configuration, U29 also supplies the PDM clock to the microphones.
Regardless of where the microphones are routed to, STM32L476ZGT6 or WM8994, they
can be power-supplied from either VDD or MICBIAS1 output of the WM8994 codec device.
Table 7 shows settings of all jumpers associated with the digital microphones on the board.
Table 7. Digital microphone-related jumper settings
Jumper
Setting
JP14
JP14
JP16
PDM clock for digital microphones comes from WM8994 codec.
Default setting.
Power supply of digital microphones is VDD.
JP16
2.7.2
Default setting.
PDM clock for digital microphones comes from STM32L476ZGT6
JP14
JP16
Configuration
Power supply of digital microphones is generated by WM8994 codec.
Headphones outputs
The STM32L476G-EVAL evaluation board can drive two sets of stereo headphones.
Identical or different stereo audio content can be played back in each set of headphones.
The STM32L476ZGT6 sends up to two independent stereo audio channels, via its SAI1
TDM port, to the WM8994 codec device. The codec device converts the digital audio stream
to stereo analog signals. It then boosts them for direct drive of headphones connecting to
3.5 mm stereo jack receptacles on the board, CN20 for Audio-output1 and CN21 for
Audio_output2. Figure 6 shows a top view of the CN20 and CN21 headphones jack
receptacles.
The CN21 jack takes its signal from the output of the WM8994 codec device intended for
driving an amplifier for loudspeakers. A hardware adaptation is incorporated on the board to
make it compatible with a direct headphone drive. The adaptation consists of coupling
capacitors blocking the DC component of the signal, attenuator and anti-pop resistors. The
loudspeaker output of the WM8994 codec device must be configured by software in linear
mode called “class AB” and not in switching mode called “class D”.
The I²C-bus address of WM8994 is 0b0011010.
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Hardware layout and configuration
Figure 6. CN20, CN21 top view
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2.7.3
Limitations in using audio features
Due to the share of some terminals of STM32L476ZGT6 by multiple peripherals, the
following limitations apply in using the audio features:
2.8
•
If the SAI1_SDA is used as part of SAI1 port, it cannot be used as FMC_NWAIT signal
for NOR Flash memory device. However, FMC_NWAIT is not necessary for operating
the NOR Flash memory device. More details on FMC_NWAIT are available in
Section 2.22: NOR Flash memory device.
•
If the SAI1 port of STM32L476ZGT6 is used for streaming audio to the WM8994 codec
IC, STM32L476ZGT6 cannot control the motor.
•
If the digital microphones are attached to STM32L476ZGT6, the LCD glass module
cannot be driven.
USB OTG FS port
The STM32L476G-EVAL board supports USB OTG full-speed (FS) communication. The
USB OTG connector CN1 is of Micro-AB type.
2.8.1
STM32L476G-EVAL used as USB device
When a “USB host” connection to the CN1 Micro-AB USB connector of STM32L476G-EVAL
is detected, the STM32L476G-EVAL board starts behaving as “USB device”. Depending on
the powering capability of the USB host, the board can take power from VBUS terminal of
CN1. In the board schematic diagrams, the corresponding power voltage line is called U5V.
Section 2.3 provides information on how to set associated jumpers for this powering option.
The JP19 jumper must be left open to prevent STM32L476G-EVAL from sourcing 5 V to
VBUS terminal, which would cause conflict with the 5 V sourced by the USB host. This may
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happen if the PC6 GPIO is controlled by the software of the STM32L476ZGT6 such that, it
enables the output of U1 power switch.
2.8.2
STM32L476G-EVAL used as USB host
When a “USB device” connection to the CN1 Micro-AB USB connector is detected, the
STM32L476G-EVAL board starts behaving as “USB host”. It sources 5 V on the VBUS
terminal of CN1 Micro-AB USB connector to power the USB device. For this to happen, the
STM32L476ZGT6 MCU sets the U1 power switch STMPS2151STR to ON state. The LD5
green LED marked VBUS indicates that the peripheral is supplied from the board. The LD6
red LED marked FAULT lights up if over-current is detected. The JP19 jumper must be
closed to allow the PC6 GPIO to control the U1 power switch.
In any other STM32L476G-EVAL powering option, the JP19 jumper should be open, to
avoid accidental damage caused to an external USB host.
2.8.3
Configuration elements related with USB OTG FS port
The following STM32L476ZGT6 terminals related with USB OTG FS port control are shared
by other resources of the STM32L476G-EVAL board:
•
PB12, used as USB over-current input (USBOTG_OVRCR signal); it is shared with
SWP, touch sensing, LCD glass module and motor control resources
•
PB13, used as USB power ready input (USBOTG_PRDY signal); it is shared with NFC,
touch sensing and LCD glass module resources
•
PC6, used as USB power switch control (USBOTG_PPWR signal); it is shared with
touch sensing, LCD glass module and motor control
Configuration elements related with the USB OTG FS port, such as jumpers, solder bridges
and zero-ohm resistors, shunt the shared ports toward different resources or determine the
operating mode of the USB OTG FS port. By default, they are set such as to enable the
USB OTG FS port operation where STM32L476G-EVAL plays USB device role and can be
connected to a USB host. Table 8 gives an overview of all configuration elements related
with the USB OTG FS port. The LCD glass module daughterboard should be connected in
I/O position.
USBOTG_OVRCR and USBOTG_PRDY signals, requiring the PB12 and PB13 ports of
STM32L476ZGT6, are only exploited when STM32L476G-EVAL acts as USB host. That is
why, the USB host function of STM32L476G-EVAL is exclusive with alternate functions also
requiring PB12 and PB13 ports of STM32L476ZGT6 - NFC, touch sensing, motor control,
SWP.
The PB12 and PB13 ports of STM32L476ZGT6 are not required for the USB OTG FS port
operating as USB device.
Table 8. Configuration elements related with USB OTG FS port
Element
Setting
Description
Open
USB OTG FS port can be connected with a USB host and get power
from it. If connected with USB device, STM32L476G-EVAL cannot
supply power to it.
JP19
Closed
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Default setting.
USB OTG FS port can be connected with a USB device and supply
power to it. It must not be connected with USB host.
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Hardware layout and configuration
Table 8. Configuration elements related with USB OTG FS port (continued)
Element
Setting
Description
In
Default setting
PC6 is shunted to control the U1 power switch, transiting through the
LCD glass module daughterboard connector.
LCD glass module daughterboard should be in I/O position, with SB2
and SB27 open.
R36
Out
In
R39
Out
In
R38
Out
2.8.4
2.8.5
PC6 is disconnected from the LCD glass module daughterboard
connector. It can be shunted to one of alternate resources, either
touch sensing (SB2 closed) or motor control (SB27 closed).
Default setting.
PB12 receives USBOTG_OVRCR signal from U1 power switch,
transiting through the LCD glass module daughterboard connector.
SB3 should be open, R109 in, no smartcard in CN23 slot.
PB12 is disconnected from the LCD glass module daughterboard
connector. It can be shunted to one of alternate resources, either
touch sensing or motor control (SB3 closed).
Default setting.
PB13 receives USBOTG_PRDY signal from CN1 connector, transiting
through the LCD glass module daughterboard connector.
SB6 should be open and no daughterboard inserted in CN13 NFC
connector.
PB13 s disconnected from the LCD glass module daughterboard
connector. It can be shunted to touch sensing (SB6 closed).
Limitations in using USB OTG FS port
•
The USB OTG FS port operation as USB host is exclusive with NFC, SWP, LCD glass
module, touch sensing, motor control
•
The USB OTG FS port operation as USB device is exclusive with LCD glass module,
touch sensing, motor control
Operating voltage
The USB-related operating supply voltage of STM32L476ZGT6 (VDD_USB line) must be
within the range from 3.0 V to 3.6 V.
2.9
RS-232 and IrDA ports
The STM32L476G-EVAL board offers one RS-232 communication port and one IrDA port.
If the STM32L476G-EVAL board version is greater than or equal to
MB1144 C-02, the IrDA transceiver (TFDU6300) is not populated, but it is possible to solder
manually the TDFU6300 on U11 footprint to support IRDA feature.
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RS-232 port
The RS-232 communication port uses the DE-9M 9-pole connector CN9. RX, TX, RTS and
CTS signals of USART1 port of STM32L476ZGT6 are routed to CN9.
Bootloader_RESET_3V3 and Bootloader_BOOT0_3V3 signals can also be routed to CN9,
for ISP (in-system programming) support. To route Bootloader_RESET_3V3 to CN9, the
R93 resistor must be removed and the JP9 jumper closed (open by default). To route
Bootloader_BOOT0_3V3 to CN9, the JP8 jumper must be closed.
For configuration elements related with the RS-232 port operation, refer to Table 6 and
Table 9.
Section 2.10 brings information on using the LPUART port of STM32L476ZGT6 for RS-232,
instead of its USART1 port.
2.9.2
IrDA port
The IrDA communication port uses an IrDA transceiver (U11). Table 9 shows the
configuration elements related with the IrDA port operation
.
Table 9. Settings of configuration elements for RS-232 and IrDA ports
Element
Setting
Description
JP15
1
3
5
2
4
6
Default setting.
RS-232 selected: PB7 port of STM32L476ZGT6 receives signal
originating from RXD terminal of CN9.
JP15
JP15
1
3
5
2
4
6
IrDA selected: PB7 port of STM32L476ZGT6 is connected with RxD
terminal of the IrDA transceiver U11.
2
4
6
NFC selected: PB7 port of STM32L476ZGT6 receives NFC_IRQOUT
signal from NFC peripheral. Section 2.28 provides more detail on the
NFC peripheral.
JP15
1
3
5
2.9.3
R93, R118,
R116
In
Required for IrDA operation
R158, R119
Out
Required for IrDA operation
Limitations
The operation of RS-232 and IrDA ports is mutually exclusive. The operation of either port is
also mutually exclusive with the NFC peripheral operation.
2.9.4
Operating voltage
The RS-232- and IrDA-related operating supply voltage of STM32L476ZGT6 (VDD line)
must be within the range from 1.71 V to 3.6 V.
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2.10
Hardware layout and configuration
LPUART port
On top of USART1 port for serial communication, the STM32L476ZGT6 offers LPUART, a
low-power UART port.
In the default configuration of STM32L476G-EVAL, the RX and TX terminals of the LPUART
port are routed to the USB virtual COM port of ST-LINK/V2-1 and, the RX and TX terminals
of USART1 port to the RS-232 connector CN9.
For specific purposes, the TX and RX of the LPUART port of STM32L476ZGT6 can be
routed to the RS-232 connector CN9 instead. As RTS and CTS terminals of CN9 keep
routed to USART1 port, they may block the LPUART communication flow. To avoid this, set
the USART1 hardware flow control off.
The default settings of LPUART are: 115200b/s, 8bits, no parity, 1 stop bit, no flow control.
Table 10. Hardware settings for LPUART
2.11
LPUART port use
R188
R189
R158
R119
R118
JP15 1-2
Default setting
USB virtual COM port of ST-LINK/V2-1
In
In
Out
Out
Do not
care
Do not
care
RS-232 (RX and TX)
Out
Out
In
In
Out
Closed
microSD card
The CN18 slot for microSD card is routed to STM32L476ZGT6’s SDIO port, accepting SD
(up to 2 Gbytes), SDHC (up to 32 Gbytes) and SDXC (up to 2 Tbytes) cards. One 4-Gbyte
microSD card is delivered as part of STM32L476G-EVAL. The card insertion switch is
routed to the PA8 GPIO port.
Table 11. Terminals of CN18 microSD slot
Terminal
Terminal name (MCU port)
Terminal
Terminal name (MCU port)
1
SDIO_D2 (PC10)
6
Vss/GND
2
SDIO_D3 (PC11)
7
SDIO_D0 (PC8)
3
SDIO_CMD (PD2)
8
SDIO_D1 (PC9)
4
VDD
9
GND
5
SDIO_CLK (PC12)
10
MicroSDcard_detect (PA8)
For microSD card operation, the LCD glass module daughterboard must be plugged into
CN11 and CN14 in I/O-bridge position, as explained in Section 2.15.
2.11.1
Limitations
Due to the share of SDIO port and PA8 terminals, the following limitations apply:
•
The microSD card cannot be operated simultaneously with LCD glass module or with
motor control.
•
The microSD card insertion cannot be detected when the PA8 is used as
microcontroller clock output (MCO), one of alternate functions of PA8.
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Operating voltage
The supply voltage for STM32L476G-EVAL microSD card operation must be within the
range from 2.7 V to 3.6 V.
2.12
Motor control
The CN2 connector is designed to receive a motor control (MC) module. Table 12 shows the
assignment of CN2 and STM32L476ZGT6 terminals.
Table 12 also lists the modifications to be made on the board versus its by-default
configuration. See Section 2.12.1 for further details.
Table 12. Motor control terminal and function assignment
Motor control
connector CN2
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STM32L476ZGT6 microcontroller
Terminal
Terminal
name
Port name
Function
Alternate
function
Board modifications for
enabling motor control
1
Emergency
Stop
PC9
TIM8_BKIN2
-
Close SB29
Remove MB979 daughterboard
2
GND
-
GND
-
-
3
PWM_1H
PC6
TIM8_CH1
-
Close SB27
Open SB2
Remove MB979 daughterboard
4
GND
-
GND
-
-
5
PWM_1L
PA7
TIM8_CH1N
-
Close SB19
Open SB18
Remove R66
6
GND
-
GND
-
-
7
PWM_2H
PC7
TIM8_CH2
-
Close SB30
Open SB4
Remove R33
8
GND
-
GND
-
-
9
PWM_2L
PB0
TIM8_CH2N
-
Close SB15
Open SB14
Remove R62
10
GND
-
GND
-
-
11
PWM_3H
PC8
TIM8_CH3
-
Close SB28
Remove MB979 daughterboard
12
GND
-
GND
-
-
13
PWM_3L
PB1
TIM8_CH3N
-
Close SB13
Open SB12
14
Bus Voltage
PC5
ADC12_IN
-
Close SB16
Remove MB979 daughterboard
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Hardware layout and configuration
Table 12. Motor control terminal and function assignment (continued)
Motor control
connector CN2
STM32L476ZGT6 microcontroller
Terminal
Terminal
name
Port name
Function
Alternate
function
Board modifications for
enabling motor control
15
PhaseA
current+
PC0
ADC123_IN
-
Close SB34
Remove MB979 daughterboard
16
PhaseA
current-
-
GND
-
-
17
PhaseB
current+
PC1
ADC123_IN
-
Close SB36
18
PhaseB
current-
-
GND
-
-
19
PhaseC
current+
PC2
ADC123_IN
-
Close SB42
Remove MB979 daughterboard
20
PhaseC
current-
-
GND
-
-
21
ICL Shutout
PG6
GPIO
-
Close SB5
Remove R35
22
GND
-
GND
-
-
23
Dissipative
Brake
PB2
GPIO
-
Close SB11
Remove R54
24
PFC ind.
curr.
PC4
ADC12_IN
-
Close SB17
Remove MB979 daughterboard
25
+5V
-
+5V
-
-
26
Heatsink
Temp.
PA3
ADC12_IN
-
Close SB22
Remove MB979 daughterboard
27
PFC Sync
PF9
TIM15_CH1
-
Close SB25
Remove R90
28
+3.3V
-
+3.3V
-
-
29
PFC PWM
PF10
TIM15_CH2
-
Close SB37
Remove R91
30
PFC
Shutdown
PB12
TIM15_BKIN
-
Close SB3
Remove MB979 daughterboard
31
Encoder A
PA0
TIM2_CH1
ADC12_IN
Close SB35
Remove R83
32
PFC Vac
PA6
ADC12_IN
-
Close SB20
Open SB21
Remove MB979 daughterboard
33
Encoder B
PA1
TIM2_CH2
ADC12_IN
Close SB32
Remove MB979 daughterboard
34
Encoder
Index
PA2
TIM2_CH3
ADC12_IN
Close SB31
Remove MB979 daughterboard
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2.12.1
UM1855
Board modifications to enable motor control
Figure 7 (top side) and Figure 8 (bottom side) illustrate the board modifications listed in
Table 12, required for the operation of motor control. Red color denotes a component to be
remove. Green color denotes a component to be fitted.
Figure 7. PCB top-side rework for motor control
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Hardware layout and configuration
Figure 8. PCB underside rework for motor control
2.12.2
Limitations
Motor control operation is exclusive with LCD glass module, Quad-SPI Flash memory
device, audio codec, potentiometer, LDR, smartcard, LED1 drive and the use of sigma-delta
modulators.
2.13
CAN
The STM32L476G-EVAL board supports one CAN2.0A/B channel compliant with CAN
specification. The CN5 9-pole male connector of DE-9M type is available as CAN interface.
A 3.3 V CAN transceiver is fitted between the CN5 connector and the CAN controller port of
STM32L476ZGT6.
The JP4 jumper allows selecting one of high-speed, standby and slope control modes of the
CAN transceiver. The JP6 jumper can fit a CAN termination resistor in.
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Table 13. CAN related jumpers
Jumper
Setting
JP4
JP4
Configuration
Default setting
CAN transceiver operates in high-speed mode
JP4
CAN transceiver is in standby mode
JP6
JP6
JP6
2.13.1
No termination resistor on CAN physical link
Default setting
Termination resistor fitted on CAN physical link
Limitations
CAN operation is exclusive with LCD glass module operation.
2.13.2
Operating voltage
The supply voltage for STM32L476G-EVAL CAN operation must be within the range from
3.0 V to 3.6 V.
2.14
Extension connectors CN6 and CN7
The CN6 and CN7 headers complement the LCD glass module daughterboard connector, to
give access to all GPIOs of the STM32L476ZGT6 microcontroller. In addition to GPIOs, the
following signals and power supply lines are also routed on CN6 or CN7:
•
GND
•
+3V3
•
DSV
•
RESET#
•
VDD
•
Clock terminals PC14-OSC32_IN, PC15-OSC32_OUT, PH0-OSC_IN, PH1-OSC_OUT
Each header has two rows of 20 pins, with 1.27 mm pitch and 2.54 mm row spacing. For
extension modules, SAMTEC RSM-120-02-L-D-xxx and SMS-120-x-x-D can be
recommended as SMD and through-hole receptacles, respectively (x is a wild card).
2.15
LCD glass module daughterboard
The MB979 daughterboard delivered in the STM32L476G-EVAL package bears a
segmented LCD glass module. The daughterboard inserts into CN11 and CN14 extension
headers of the main board, each having two rows of pins. The corresponding female
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Hardware layout and configuration
connectors on the daughterboard have three rows of holes each. One raw is routed to
segments of the LCD. The other two rows are interconnected and form a series of jumpers.
The way of inserting the LCD glass module daughterboard into CN11 and CN14 headers
determines two functions of LCD glass module daughterboard. In its display function,
STM32L476ZGT6 terminals are routed to LCD segments. In its I/O-bridge function, they are
not. Instead, they transit from one row of CN11 pins to the other and from one row of CN14
pins to the other, thanks to interconnections fitted by the LCD glass module daughterboard.
Figure 9 shows how the LCD glass module daughterboard must be positioned for display
function. This position is designated in the document as display position.
Figure 10 shows how the LCD glass module daughterboard must be positioned for I/Obridge function. This position is designated in the document as I/O-bridge position.
The arrow indicates the side of the CN11 and CN14 headers where the extra row of holes of
each female counterpart on the LCD glass module daughterboard has to protrude.
When the LCD glass module daughterboard is not plugged in, CN11 and CN14 give access
to ports of the target microcontroller. Figure 36 shows the related schematic diagram.
Table 14 shows the default settings of board configuration elements linked with CN11 and
CN14 extension connectors and LCD glass module daughterboard.
Figure 9. LCD glass module daughterboard in display position
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Figure 10. LCD glass module daughterboard in I/O-bridge position
Table 14. LCD-daughterboard-related configuration elements
LCD
segment
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG10
34/101
Element
Setting to enable
LCD glass
module
R82
In
SB32
Open
R81
In
SB31
Open
R78
In
SB22
Open
R68
In
SB21
Open
PA6 not routed to Quad-SPI Flash memory device
SB20
Open
PA6 not routed to motor control
R66
In
SB18
Open
PA7 not routed to Quad-SPI Flash memory device
SB19
Open
PA7 not routed to motor control
R62
In
SB14
Open
PB0 not routed to Quad-SPI Flash memory device
SB15
Open
PB0 not routed to motor control
R56
In
SB12
Open
PB1 not routed to Quad-SPI Flash memory device
SB13
Open
PB1 not routed to motor control
R50
In
SB9
Open
Description
PA1 routed to LCDSEG0
PA1 not routed to motor control
PA2 routed to LCDSEG1
PA2 not routed to motor control
PA3 routed to LCDSEG2
PA3 not routed to motor control
PA6 routed to LCDSEG3
PA7 routed to LCDSEG4
PB0 routed to LCDSEG5
PB1 routed to LCDSEG6
PB10 routed to LCDSEG10
PB10 not routed to Quad-SPI Flash memory device
DocID027351 Rev 5
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Hardware layout and configuration
Table 14. LCD-daughterboard-related configuration elements (continued)
Element
Setting to enable
LCD glass
module
R48
In
SB8
Open
R39
In
SB3
Open
R38
In
SB6
Open
R97
In
SB34
Open
R98
In
SB36
Open
R99
In
SB42
Open
R65
In
SB17
Open
R64
In
SB16
Open
R36
In
SB2
Open
PC6 not routed to Touch sensing
SB27
Open
PC6 not routed to for motor control
R33
In
SB4
Open
PC7 not routed to Touch sensing
SB30
Open
PC7 not routed to for motor control
SEG26
SB28
Open
PC8 not routed to motor control
SEG27
SB29
Open
PC9 not routed to motor control
R103
In
SB26
Open
R104
In
LCD
segment
SEG11
SEG12
SEG13
SEG18
SEG19
SEG20
SEG22
SEG23
SEG24
SEG25
SEG38
SEG39
Description
PB11 routed to LCDSEG11
PB11 not routed to Quad-SPI Flash memory device
PB12 routed to LCDSEG12
PB12 not routed to Quad-SPI Flash memory device
PB13 routed to LCDSEG13
PB13 not routed to Touch sensing
PC0 routed to LCDSEG18
PC0 not routed to motor control
PC1 routed to LCDSEG19
PC1 not routed to motor control
PC2 routed to LCDSEG20
PC2 not routed to motor control
PC4 routed to LCDSEG22
PC4 not routed to motor control
PC5 routed to LCDSEG23
PC5 not routed to motor control
PC6 routed to LCDSEG24
PC7 routed to LCDSEG25
PE2 routed to LCDSEG38
PE2 not routed to Trace
PE3 routed to LCDSEG39
The custom LCD glass module used on MB979 daughterboard is XHO5002B. To optimize
the number of driving signals, the display elements are connected to eight common planes
called COMx (LCDCOMx in the schematic diagrams), where “x” can be substituted with
figures from “0” to “7”. The other pole of each display element is called segment, SEGy
(LCDSEGy in the schematic diagrams), where “y” can be substituted with figures from “0” to
“39”. Each combination of COMx and SEGy addresses one display element. Table 15,
Table 16, Table 17 and Table 22 show the LCD element mapping. COMx are ordered in
rows, SEGy in columns. The table cells then display the display element names
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corresponding to each COMx and SEGy combination. Names in quoting marks denote
elements forming textual symbols, for example “µA” or “+”. Figure 11 shows the physical
location and shape of each segment on the LCD glass module.
Table 15. LCD glass element mapping - segments 0 to 9
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
COM0
O1
5D
Q4
O4
6D
Q5
ST
7D
Q6
S5
COM1
O2
5K
5L
O3
6K
6L
“nA”
7K
7L
S6
COM2
13b
12b
11b
16b
15b
14b
19b
18b
17b
1b
COM3
13a
12a
11a
16a
15a
14a
19a
18a
17a
1a
COM4
5I
5A
5G
6I
6A
6G
7I
7A
7G
1I
COM5
5B
5H
5F
6B
6H
6F
7B
7H
7F
1B
COM6
5C
5M
P4
6C
6M
P5
7C
7M
P6
1C
COM7
5J
5N
5E
6J
6N
6E
7J
7N
7E
1J
Table 16. LCD glass element mapping - segments 10 to 19
SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19
COM0
1D
“-”
C1
2D
Q1
C4
3D
Q2
“µA”
4D
COM1
1K
1L
C2
2K
2L
C3
3K
3L
“mA”
4K
COM2
S4
S2
4b
3b
2b
7b
6b
5b
10b
9b
COM3
S3
S1
4a
3a
2a
7a
6a
5a
10a
9a
COM4
1A
1G
2I
2A
2G
3I
3A
3G
4I
4A
COM5
1H
1F
2B
2H
2F
3B
3H
3F
4B
4H
COM6
1M
“+”
2C
2M
P1
3C
3M
P2
4C
4M
COM7
1N
1E
2J
2N
2E
3J
3N
3E
4J
4N
Table 17. LCD glass element mapping - segments 20 to 29
SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29
36/101
COM0
Q3
1e
2e
3e
4e
5e
6e
7e
8e
9e
COM1
4L
1f
2f
3f
4f
5f
6f
7f
8f
9f
COM2
8b
1c
2c
3c
4c
5c
6c
7c
8c
9c
COM3
8a
1d
2d
3d
4d
5d
6d
7d
8d
9d
COM4
4G
1j
2j
3j
4j
5j
6j
7j
8j
9j
COM5
4F
1i
2i
3i
4i
5i
6i
7i
8i
9i
COM6
P3
1h
2h
3h
4h
5h
6h
7h
8h
9h
COM7
4E
1g
2g
3g
4g
5g
6g
7g
8g
9g
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Hardware layout and configuration
Table 18. LCD glass element mapping - segments 30 to 39
SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39
2.15.1
COM0
10e
11e
12e
13e
14e
15e
16e
17e
18e
19e
COM1
10f
11f
12f
13f
14f
15f
16f
17f
18f
19f
COM2
10c
11c
12c
13c
14c
15c
16c
17c
18c
19c
COM3
10d
11d
12d
13d
14d
15d
16d
17d
18d
19d
COM4
10j
11j
12j
13j
14j
15j
16j
17j
18j
19j
COM5
10i
11i
12i
13i
14i
15i
16i
17i
18i
19i
COM6
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
COM7
10g
11g
12g
13g
14g
15g
16g
17g
18g
19g
Limitations
LCD glass module operation is exclusive with all other features of the board.
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DocID027351 Rev 5
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Hardware layout and configuration
38/101
Figure 11. LCD glass display element mapping
K K
L
L
M
M
2
M
M
M
M
M
M
M
M M M M M M M M M M
2
06Y 9
UM1855
UM1855
2.16
Hardware layout and configuration
TFT LCD panel
STM32L476G-EVAL is delivered with MB989P, a daughterboard plugged into the CN19
extension connector. It bears a TFT 2.8-inch color LCD panel with resistive touchscreen and
an on-board controller. Section 2.18 provides further information.
Thanks to level shifters on all signal lines, the TFT LCD panel can operate with the entire
operating voltage range of STM32L476G-EVAL.
The TFT LCD panel is attached to the 16-bit data bus and accessed with FMC. The base
address is 0x6800 0000, corresponding to NOR/SRAM3 bank1. The panel is selected with
LCD_NE3 chip select signal generated by PG10 port of the STM32L476ZGT6. Address
lines A0 and A1 determine the panel resources addressed, as depicted in Table 19.
Table 20 gives the CN19 extension connector terminal assignment.
Table 19. Access to TFT LCD resources with FMC address lines A0 and A1
Address
A1
A0
Usage
0x6800_0000
0
0
Read register
0x6800_0002
0
1
Read Graphic RAM (GRAM)
0x6800_0004
1
0
Write register
0x6800_0006
1
1
Write graphic RAM (GRAM)
Table 20. Assignment of CN19 connector terminals of TFT LCD panel
CN19
terminal
Terminal
name
MCU
port
CN19
terminal
Terminal
name
MCU
port
1
CSN
PG10
2
RS
PF0
3
WRN
PD5
4
RDN
PD4
5
RSTN
RESET#
6
D0
PD14
7
D1
PD15
8
D2
PD0
9
D3
PD1
10
D4
PE7
11
D5
PE8
12
D6
PE9
13
D7
PE10
14
D8
PE11
15
D9
PE12
16
D10
PE13
17
D11
PE14
18
D12
PE15
19
D13
PD8
20
D14
PD9
21
D15
PD10
22
BL_GND
-
23
BL_CONTROL
-
24
+3V3
-
25
+3V3
-
26
26
-
27
GND
-
28
BL_VDD
-
29
SDO
-
30
SDI
-
31
XL
I/O expander_X-
32
XR
I/O expander_X+
33
YD
I/O expander_Y-
34
YU
I/O expander_Y+
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2.17
UM1855
User LEDs
Four general-purpose color LEDs (LD1, LD2, LD3, LD4) are available as light indicators.
Each LED is in light-emitting state with low level of the corresponding control port. They are
controlled either by the STM32L476ZGT6 or by the I/O expander IC U32, named
IOExpander1 in the schematic diagram. Table 21 gives the assignment of control ports to
the LED indicators.
Table 21. Port assignment for control of LED indicators
2.18
User LED
Control port
Control device
LED1 (Green)
PB2
STM32L476ZGT6
LED2 (Orange)
GPIO0
IOExpander1
LED3 (Red)
PC1
STM32L476ZGT6
LED4 (Blue)
GPIO2
IOExpander1
Physical input devices
The STM32L476G-EVAL board provides a number of input devices for physical human
control. These are:
•
four-way joystick controller with select key (B3)
•
wake-up/ tamper button (B2)
•
reset button (B1)
•
resistive touchscreen of the TFT LCD panel
•
10 kΩ potentiometer (RV3)
•
light-dependent resistor, LDR (R52)
Table 22 shows the assignment of ports routed to the physical input devices. They are either
ports of the STM32L476ZGT6 or of one of the two I/O expander ICs on the board, named, in
the schematic diagrams, IOExpander1 and IOExpander2.
Table 22. Port assignment for control of physical input devices
40/101
Input device
Control port
Control device
Joystick SEL
GPIO0
IOExpander2
Joystick DOWN
GPIO1
IOExpander2
Joystick LEFT
GPIO2
IOExpander2
Joystick RIGHT
GPIO3
IOExpander2
Joystick UP
GPIO4
IOExpander2
Wake-up/ tamper B2
PC13
STM32L476ZGT6
Reset B1
NRST
STM32L476ZGT6
Resistive touch screen X+
X+
IOExpander1
Resistive touch screen X-
X-
IOExpander1
Resistive touch screen Y+
Y+
IOExpander1
DocID027351 Rev 5
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Hardware layout and configuration
Table 22. Port assignment for control of physical input devices (continued)
Input device
Control port
Control device
Resistive touch screen Y-
Y-
IOExpander1
Potentiometer
PB4 or PA0
STM32L476ZGT6
LDR
PA0 or PB4
STM32L476ZGT6
The potentiometer and the light-dependent resistor can be routed, mutually exclusively, to
either PB4 or to PA0 port of STM32L476ZGT6. Table 23 depicts the setting of associated
configuration jumpers.
As illustrated in the schematic diagram in Figure 46, the PB4 port is routed, in the
STM32L476ZGT6, to the non-inverting input of comparator Comp2. The PA0 is routed to
non-inverting input of operational amplifier OpAmp1. However, depending on register
settings, it can also be routed to ADC1 or to ADC2.
Table 23. Setting of jumpers related with potentiometer and LDR
Jumper
2.18.1
Setting
JP5
Routing
JP7
JP5
JP7
JP5
JP7
JP5
JP7
JP5
JP7
JP5
JP7
JP5
JP7
JP5
Potentiometer is routed to pin PB4 of STM32L476ZGT6.
Default setting.
Potentiometer is routed to pin PA0 of STM32L476ZGT6.
LDR is routed to pin PB4 of STM32L476ZGT6.
JP7
LDR is routed to pin PA0 of STM32L476ZGT6.
Limitations
The potentiometer and the light-dependent resistor are mutually exclusive.
2.19
Operational amplifier and comparator
2.19.1
Operational amplifier
STM32L476ZGT6 provides two on-board operational amplifiers, one of which, OpAmp1, is
made accessible on STM32L476G-EVAL. OpAmp1 has its inputs and its output routed to
I/O ports PA0, PA1 and PA3, respectively. The non-inverting input PA0 is accessible on the
terminal 1 of the JP7 jumper header. On top of the possibility of routing either of the
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Hardware layout and configuration
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potentiometer or LDR to PA0, en external source can also be connected to it, using the
terminal 1 of JP7.
The PA3 output of the operational amplifier can be accessed on test point TP9. Refer to the
schematic diagram in Figure 46.
The gain of OpAmp1 is determined by the ratio of the variable resistor RV2 and the resistor
R121, as shown in the following equation:
Gain = 1 + ( RV2 ) ÷ ( R121 )
With the RV2 ranging from 0 to 10 kΩ and R121 being 1 kΩ, the gain can vary from 1 to 11.
The R63 resistor in series with PA0 is beneficial for reducing the output offset.
2.19.2
Comparator
STM32L476ZGT6 provides two on-board comparators, one of which, Comp2, is made
accessible on STM32L476G-EVAL. Comp2 has its non-inverting input and its output routed
to I/O ports PB4 and PB5, respectively. The input is accessible on the terminal 3 of the JP7
jumper header. On top of the possibility of routing either the potentiometer or LDR to PB4,
an external source can also be connected to it, using the terminal 3 of JP7.
The PB5 output of the comparator can be accessed on test point TP6. Refer to the
schematic diagram in Figure 46.
2.20
Analog input, output, VREF
STM32L476ZGT6 provides on-board analog-to-digital converter, ADC and, digital-to-analog
converter, DAC. The port PA4 can be configured to operate either as ADC input or as DAC
output. PA4 is routed to the two-way header CN8 allowing to fetch signals to or from PA4 or
to ground it by fitting a jumper into CN8.
Parameters of the ADC input low-pass filter formed with R72 and C47 can be modified by
replacing these components according to application requirements. Similarly, parameters of
the DAC output low-pass filter formed with R73 and C47 can be modified by replacing these
components according to application requirements.
The VREF+ terminal of STM32L476ZGT6 is used as reference voltage for both ADC and
DAC. By default, it is routed to VDDA through a jumper fitted into the two-way header CN10.
The jumper can be removed and an external voltage applied to the terminal 1 of CN10, for
specific purposes.
2.21
SRAM device
IS61WV102416BLL, a 16-Mbit static RAM (SRAM), 1 M x16 bit, is fitted on the
STM32L476G-EVAL main board, in U2 position. The STM32L476G-EVAL main board as
well as the addressing capabilities of FMC allow hosting SRAM devices up to 64 Mbytes.
This is the reason why the schematic diagram in Figure 41 mentions several SRAM
devices.
The SRAM device is attached to the 16-bit data bus and accessed with FMC. The base
address is 0x6000 0000, corresponding to NOR/SRAM1 bank1. The SRAM device is
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selected with FMC_NE1 chip select. FMC_NBL0 and FMC_NBL1 signals allow selecting 8bit and 16-bit data word operating modes.
By removal of R18, a zero-ohm resistor, the SRAM is deselected and the STM32L476ZGT6
ports PD7, PE0 and PE1 corresponding to FMC_NE1, FMC_NBL0 and FMC_NBL1 signals,
respectively, can be used for other application purposes.
Table 24. SRAM chip select configuration
Resistor
Fitting
In
R18
Out
2.21.1
Configuration
Default setting.
SRAM chip select is controlled with FMC_NE1
SRAM is deselected. FMC_NE1 is freed for other application purposes.
Limitations
The SRAM addressable space is limited if some or all of A19, A20, A21, A22 and A23 FMC
address lines are shunted to the CN12 connector for debug trace purposes. In such a case,
the disconnected addressing inputs of the SRAM device are pulled down by resistors.
Section 2.2 provides information on the associated configuration elements.
2.21.2
Operating voltage
The SRAM device operating voltage is in the range from 2.4 V to 3.6 V.
2.22
NOR Flash memory device
M29W128GL70ZA6E, a 128-Mbit NOR Flash memory, 8 M x16 bit, is fitted on the
STM32L476G-EVAL main board, in U5 position. The STM32L476G-EVAL main board as
well as the addressing capabilities of FMC allow hosting M29W256GL70ZA6E, a 256-Mbit
NOR Flash memory device. This is the reason why the schematic diagram in Figure 41
mentions both devices.
The NOR Flash memory device is attached to the 16-bit data bus and accessed with FMC.
The base address is 0x6400 0000, corresponding to NOR/SRAM2 bank1. The NOR Flash
memory device is selected with FMC_NE2 chip select signal. 16-bit data word operation
mode is selected by a pull-up resistor connected to BYTE terminal of NOR Flash memory.
The jumper JP13 is dedicated for write protect configuration.
By default, the FMC_NWAIT signal is not routed to RB port of the NOR Flash memory
device, and, to know its ready status, its status register is polled by the demo software fitted
in STM32L476G-EVAL. This can be modified with configuration elements, as shown in
Table 25.
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Table 25. NOR Flash memory-related configuration elements
Element
Setting
JP13
JP13
2.22.1
2.22.2
Default setting.
NOR Flash memory write is enabled.
JP13
R53
SB10
Configuration
R53 In
SB10 open
NOR Flash memory write is inhibited. Write protect is activated.
Default setting.
PD6 port of STM32L476ZGT6 is used for SAI1_SDA signal and routed
to audio codec.
NOR Flash memory device’s status register can be accessed.
PD6 port of STM32L476ZGT6 is used for FMC_NWAIT signal and
R53 Out
routed to NOR Flash memory device’s RB port.
SB10 closed
NOR Flash memory device’s status register cannot be accessed.
Limitations
•
FMC_NWAIT and SAI1_SDA signals are mutually exclusive.
•
The NOR Flash memory device’s addressable space is limited if some or all of A19,
A20, A21, A22 and A23 FMC address lines are shunted to the CN12 connector for
debug trace purposes. In such a case, the disconnected addressing inputs of the NOR
Flash memory device are pulled down by resistors. Section 2.2 provides information on
the associated configuration elements.
Operating voltage
NOR Flash memory operating voltage must be in the range from 1.65 V to 3.6 V.
2.23
EEPROM
M24128-DFDW6TP, a 128-Kbit I²C-bus EEPROM device, is fitted on the main board of
STM32L476G-EVAL, in U6 position. It is accessed with I²C-bus lines I2C2_SCL and
I2C2_SDA of STM32L476ZGT6. It supports all I²C-bus modes with speeds up to 1 MHz.
The base I²C-bus address is 0xA0. Write-protecting the EEPROM is possible through
opening the SB7 solder bridge. By default, SB7 is closed and writing into the EEPROM
enabled.
2.23.1
Operating voltage
The M24128-DFDW6TP EEPROM device’s operating voltage must be in the range from
1.7 V to 3.6 V
2.24
RF-EEPROM
RF-EEPROM daughterboard, ANT7-M24LR-A, can be connected to CN3 connector of the
STM32L476G-EVAL board. STM32L476ZGT6 can access the RF-EEPROM in two ways,
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wired through I²C bus or wireless using 13.56 MHz RF band reserved for RFID and NFC
equipment. For wireless access, CR95HF reader daughterboard plugged in the CN13
connector can be used, for example.
I²C address of RF-EEPROM device is 0xA6.
2.25
Quad-SPI Flash memory device
N25Q256A13EF840E, a 256-Mbit Quad-SPI Flash memory device, is fitted on the
STM32L476G-EVAL main board, in U9 position. It allows evaluating STM32L476ZGT6
Quad-SPI Flash memory device interface.
N25Q256A13EF840E can operate in single transfer rate (STR) and double transfer rate
(DTR) modes.
By default, the Quad-SPI Flash memory device is not accessible. Table 26 shows the
configuration elements and their settings allowing to access the Quad-SPI Flash memory
device. The LCD glass module daughterboard MB979 takes active part in the configuration.
It must be removed from the main board (denoted as “MB979 out”), to operate the QuadSPI Flash memory device. Section 2.12: Motor control provides additional information.
Table 26. Configuration elements related with Quad-SPI device
Element
SB12
SB13
MB979
SB14
SB15
MB979
SB18
SB19
MB979
Setting
SB12 open
SB13 open
Configuration
Default setting.
QSPI_D0 data line is not available at Quad-SPI Flash memory device:
PB1 port of STM32L476ZGT6 is only routed to CN11 connector for the
MB979 daughterboard.
SB12 closed QSPI_D0 data line is available at Quad-SPI Flash memory device:
SB13 open PB1 port of STM32L476ZGT6 is routed to DQ0 port of Quad-SPI Flash
MB979 out memory device.
SB14 open
SB15 open
Default setting.
QSPI_D1 data line is not available at Quad-SPI Flash memory device:
PB0 port of STM32L476ZGT6 is only routed to CN11 connector for the
MB979 daughterboard.
SB14 closed QSPI_D1 data line is available at Quad-SPI Flash memory device:
SB15 open PB0 port of STM32L476ZGT6 is routed to DQ1 port of Quad-SPI Flash
MB979 out memory device.
SB18 open
SB19 open
Default setting.
QSPI_D2 data line is not available at Quad-SPI Flash memory device:
PA7 port of STM32L476ZGT6 is only routed to CN11 connector for the
MB979 daughterboard.
SB18 closed QSPI_D2 data line is available at Quad-SPI Flash memory device:
SB19 open PA7 port of STM32L476ZGT6 is routed to DQ2 port of Quad-SPI Flash
MB979 out memory device.
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Table 26. Configuration elements related with Quad-SPI device (continued)
Element
SB21
SB20
MB979
Setting
SB21 open
SB20 open
Default setting.
QSPI_D3 data line is not available at Quad-SPI Flash memory device:
PA6 port of STM32L476ZGT6 is only routed to CN11 connector for the
MB979 daughterboard.
SB21 closed QSPI_D3 data line is available at Quad-SPI Flash memory device:
SB20 open PA6 port of STM32L476ZGT6 is routed to DQ3 port of Quad-SPI Flash
MB979 out memory device.
SB9 open
SB9
MB979
SB9 closed
MB979 out
SB8 open
SB8
MB979
SB8 closed
MB979 out
2.25.1
Configuration
Default setting.
QSPI_CLK clock line is not available at Quad-SPI Flash memory device:
PB10 port of STM32L476ZGT6 is only routed to CN11 connector for the
MB979 daughterboard.
QSPI_CLK clock line is available at Quad-SPI Flash memory device:
PB10 port of STM32L476ZGT6 is routed to C port of Quad-SPI Flash
memory device.
Default setting.
QSPI_CS line is not available at Quad-SPI Flash memory device:
PB11 port of STM32L476ZGT6 is only routed to CN11 connector for the
MB979 daughterboard.
QSPI_CS line is available at Quad-SPI Flash memory device:
PB11 port of STM32L476ZGT6 is routed to S# port of Quad-SPI Flash
memory device.
Limitations
Quad-SPI operation is exclusive with LCD glass module and with motor control.
2.25.2
Operating voltage
Voltage of Quad-SPI Flash memory device N25Q256A13EF840E is in the range of 2.7 V to
3.6 V.
2.26
Touch-sensing button
The STM32L476G-EVAL evaluation board supports a touch sensing button based on either
RC charging or on charge-transfer technique. The latter is enabled, by default.
The touch sensing button is connected to PB12 port of STM32L476ZGT6 and the related
charge capacitor is connected to PB13.
An active shield is designed in the layer two of the main PCB, under the button footprint. It
allows reducing disturbances from other circuits to prevent from false touch detections.
The active shield is connected to PC6 port of STM32L476ZGT6 through the resistor
R37.The related charge capacitor is connected to PC7.
Table 27 shows the configuration elements related with the touch sensing function. Some of
them serve to enable or disable its operation. However, most of them serve to optimize the
touch sensing performance, by isolating copper tracks to avoid disturbances due to their
antenna effect.
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Table 27. Touch-sensing-related configuration elements
Element
Setting
Configuration
In
Default setting. PB12 port is routed to CN11 connector for LCD glass
module daughterboard.
This setting is not good for robustness of touch sensing.
R39
Out
PB12 port is cut from CN11.
This setting is good for robustness of touch sensing.
Open
Default setting. PB12 is not routed to motor control.
This setting is good for robustness of touch sensing.
SB3
Closed
In
R38
Out
SB6
PB12 is routed to motor control.
This setting is not good for robustness of touch sensing.
Default setting. PB13 port is routed to CN11 connector for LCD glass
module daughterboard.
This setting is not good for robustness of touch sensing.
PB13 port is cut from CN11.
This setting is good for robustness of touch sensing.
Open
Default setting. PB13 is not routed to sampling capacitor. Touch
sensing cannot operate.
Closed
PB13 is routed to sampling capacitor. Touch sensing can operate.
In
R36
Out
Open
SB2
Closed
Open
SB27
Closed
In
R33
Out
Open
SB4
Closed
Default setting. PC6 port is routed to CN14 connector for LCD glass
module daughterboard.
This setting is not good for robustness of touch sensing.
PC6 port is cut from CN14.
This setting is good for robustness of touch sensing.
Default setting. PC6 is not routed to active shield under the touchsensing button.
This setting is not good for robustness of touch sensing.
PC6 is routed to active shield under the touch-sensing button.
This setting is good for robustness of touch sensing.
Default setting. PC6 port of STM32L476ZGT6 is not routed to motor
control. This setting is good for robustness of touch sensing.
PC6 is routed to motor control.
This setting is not good for robustness of touch sensing.
Default setting. PC7 port is routed to CN14 connector for LCD glass
module daughterboard.
This setting is not good for robustness of touch sensing.
PC7 port is cut from CN14.
This setting is good for robustness of touch sensing.
Default setting. PC7 port of STM32L476ZGT6 is not routed to
sampling capacitor of the active shield under the touch-sensing button.
This setting is not good for robustness of touch sensing.
PC7 is routed to sampling capacitor of the active shield under the
touch-sensing button.
This setting is good for robustness of touch sensing.
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Table 27. Touch-sensing-related configuration elements (continued)
Element
Setting
Configuration
Open
Default setting. PC7 port of STM32L476ZGT6 is not routed to motor
control.
This setting is good for robustness of touch sensing.
Closed
PC7 is routed to motor control. This setting is not good for robustness
of touch sensing.
SB30
2.26.1
Limitations
Touch sensing button is exclusive with LCD glass module, thermal sensor PT100 via sigmadelta conversion, USB OTG FS port operating as USB host, SWP and NFC.
2.27
Smartcard, SWP
ST8024CDR, an interface device for 3 V and 5 V asynchronous smartcards, is fitted on the
STM32L476G-EVAL main board, in U30 position. ST8024CDR performs all supply
protection and control functions of the smartcard.
ST8024CDR is controlled, on its turn, by STM32L476ZGT6, directly through its ports or
indirectly through ports of the U33 I/O expander device (IOExpander2), as shown in
Table 28.
The SWIO port of the smartcard for single-wire protocol (SWP) communication is managed
directly by PB12 port of STM32L476ZGT6.
Table 28. Assignment of ports for ST8024CDR control
ST8024CDR
port
Function
Control port
5V/3V
Smartcard power supply selection pin.
IOexpander2 GPIO7
I/OUC
Data I/O line
STM32L476ZGT6 PC4
XTAL1
Quartz crystal or external clock input
STM32L476ZGT6 PB0
OFF
Card presence detect
IOexpander2 GPIO8
RSTIN
Card reset command input
IOexpander2 GPIO5
CMDVCC
Activation sequence start command input (active low)
IOexpander2 GPIO6
Table 29 provides information on configuration elements related with smartcard operation.
Refer to Table 8, Table 12, Table 26 and Table 27 for complementary information. Bridging
of CN11 and CN14 rows of I/Os can be done by means of the MB979 daughterboard
plugged into CN11 and CN14 in I/O-bridge position, as explained in Section 2.15.
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Table 29. Configuration elements related with smartcard and SWP
Element
Setting
Configuration
Default setting.
R109 in
Smartcard SWP cannot be handled:
R39 in
PB12 is routed to USB OTG FS port as USBOTG_OVRCR line, on
SB3 open
top of being routed to SWIO port of smartcard
CN11 I/O-bridged
Configuration dedicated for USB OTG FS operation.
R39
SB3
R109
CN11
R109 out
R39 in
SB3 open
CN11 I/O-bridged
R39 out
SB3 closed
R39 out
SB3 open
Smartcard SWP can be handled:
PB12 is routed to SWIO port of smartcard. It is disconnected from
any other resource that could affect the SWP operation
Configuration dedicated for smartcard SWP operation
Smartcard SWP cannot be handled:
PB12 is routed to motor control as MC_PFC_Shutdown
Configuration dedicated for motor control operation
Smartcard SWP cannot be handled:
PB12 is only routed to touch-sensing button and it is disconnected
from any other resource.
Configuration dedicated for touch-sensing button operation.
Default setting.
R62 in
Smartcard controller U30 is supplied with clock:
SB14 open
PB0 port is routed to XTAL1 of U30, as SmartCard_CLK line and it
SB15 open
is not routed to other resources.
CN11 I/O-bridged
Configuration dedicated for smartcard operation.
R62
SB14
SB15
R65
SB17
CN14
R62 out
SB14 closed
SB15 open
Smartcard controller U30 is not supplied with clock:
PB0 is routed to Quad-SPI Flash memory device as QSPI_D1 and it
is not routed to other resources.
Configuration dedicated for Quad-SPI Flash memory device
operation.
R62 out
SB14 open
SB15 closed
Smartcard controller U30 is not supplied with clock:
PB0 is routed to motor control as MC_PWM_2L line and it is not
routed to other resources.
Configuration dedicated for motor control operation.
Default setting.
R65 in
Smartcard controller gets SmartCard_IO line:
PC4 port of MCU is routed to IOUC port of U30, as SmartCard_IO
SB17 open
CN14 I/O-bridged line and it is not routed to other resources.
Configuration dedicated for smartcard operation.
R65 out
SB17 closed
Smartcard controller does not get SmartCard_IO line:
PC4 port of MCU is routed to motor control as MC0PFC0IndCur line
and it is not routed to other resources.
Configuration dedicated for motor control operation.
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2.27.1
UM1855
Limitations
The following limitations apply for the smartcard operation:
2.27.2
•
Smartcard operation is mutually exclusive with LCD glass module, Quad-SPI Flash
memory device and motor control operation.
•
SWP operation is mutually exclusive with LCD glass module, touch-sensing button,
motor control and USB OTG FS port operation, if the last operates as USB host. SWP
can operate concurrently with USB OTG FS port acting as USB device.
Operating voltage
Smartcard operating ranging from VDD = 2.7 V to VDD = 3.6 V. However, the SWP only
operates with the supply voltage of 3.3 V.
2.28
Near-field communication (NFC)
The STM32L476G-EVAL board can host an NFC transceiver board plugged in CN13
extension connector.
Figure 12 illustrates the way of attaching an NFC board.
Figure 12. NFC board plugged into STM32L476G-EVAL board
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Table 30 shows the assignment of signals to CN13 connector.
The serial communication with the module plugged in CN13 can either use SPI
communication protocol (default) or UART communication protocol.
Table 30. CN13 NFC connector terminal assignment
CN13
terminal
NFC line name
MCU port
1
NFC_IRQOUTN or
UART_TX
PB7
Interrupt output for NFC device
Connected to STM32L476ZGT6 UART RX
2
NFC_IRQINN or
UART_RX
PB6
Interrupt input for NFC device
Connected to STM32L476ZGT6 UART TX
3
NFC_NSS
PF11
SPI slave select
4
NFC_MISO
PB14
SPI data, slave output
5
NFC_MOSI
PB15
SPI data, slave input
6
NFC_SCK
PB13
SPI serial clock
7
+3V3
-
Main power supply/power supply for RF drivers
8
GND
-
Ground
Function
2.29
Dual-channel sigma-delta modulators STPMS2L
2.29.1
STPMS2L presentation
With its DFSDM interface, the STM32L476ZGT6 microcontroller can directly interact with
sigma-delta modulator devices, such as STPMS2L.
STPMS2L comprises two analog measuring channels based on second-order sigma-delta
modulators. Typically, it can be used in power metering where both voltage and current
need to be known. One channel measures the voltage, the other channel measures the
current.
DAT port outputs converted measurement data on the DFSDM_DATIN1 line, received by
the STM32L476ZGT6 DFSDM controller. The data from STPMS2L are synchronized with
DFSDM_CKOUT clock generated by the STM32L476ZGT6 DFSDM controller and received
on CLK terminal of STPMS2L.
There are two STPMS2L devices on STM32L476G-EVAL, sharing the DFSDM clock. One is
wired such as to support a power-metering demonstrator. The other allows measuring
temperature using the PT100 sensor.
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Figure 13. Routing of STPMS2L dual-channel sigma-delta modulators
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2.29.2
STPMS2L settings
STPMS2L operating parameters are set through its configuration terminals MS0, MS1, MS2
and MS3. On STM32L476G-EVAL, both devices are configured as follows:
2.29.3
•
Voltage channel range: differential voltage +/- 300mV
•
Current channel range: differential voltage +/- 300mV
•
Internal voltage reference is used
•
Input bandwidth: 0 to 1 kHz
•
Temperature compensation: flattest +30ppm/°C
•
DAT output: voltage and current samples multiplexed
•
DATn output: not used
•
HW mode selected for settings
STPMS2L power metering
STPMS2L in U3 position simulates low-voltage AC power metering, with capacitive load
impedance, to give different phase to voltage and current.
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Figure 14. Power measurement principle schematic diagram
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A low-voltage AC generator is to be applied by the user as shown in Figure 14. The shunt
resistor is connected in series with the load to provide current measurement points to one of
STPMS2L input channels. The voltage measurement points for the other input channel are
taken across the load. Figure 15 shows an extract of the corresponding schematic diagram.
Warning:
do not connect AC mains!
Test example:
The output of a low-voltage AC generator is connected to CN4, terminals 1 and 3. The
amplitude is set between 200 mV and 300 mV and the frequency adjustable between 10 Hz
and 100 Hz.
With 34 Hz frequency and the load formed of R27 of 1 kΩ in parallel with C29 of 4.7 µF, the
voltage and current phases are theoretically 45 degrees apart.
Figure 15. STPMS2L power metering schematic diagram
C26
C27
1
5
2
CIP
C22
1uF
GND
DATn
Exposed
pad GND
CIN
VDD
1
2
VDDAC
3
VDDA
6
R26
1K
CN4
4
GND
U3
STPMS2L-PUR
VBG
current
shunt
GND
1uF
100nF
VCC
STPMS2 power metering
DAT
16
15
3
GND
C24
13
12
11
10
9
17
GND
R+jX Load
14
MS2
MS3
MS1
VIN
MS0
CLK
GND
7
VIP
VDDAV
AV
R27
1K
4.7uF
external generator input: pins 1 and 3
voltage of complex load: pins 2 and 3
shunt voltage
: pins 1 and 2
C29
8
GND
GND
GND
1uF
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2.29.4
UM1855
STPMS2L for PT100 measurement
PT100 is a resistor with temperature-dependent resistance.
Usually, one of two methods is used for measuring temperature with a temperaturedependent resistor. In the first method, a known current is driven through the measuring
resistor. The temperature is represented by the voltage measured across the resistor. In the
second method, a known voltage is applied on the resistor and the current flowing through is
measured, representing the temperature. In these methods, either an accurate current
source or an accurate voltage source is required.
With the dual-input measurement with STPMS2L in U4 position, no such accurate current or
voltage sources are required. Instead, a precision shunt resistor is required. One channel of
the STPMS2L measures the voltage across the precise shunt resistor, representing the
current flowing through PT100. The other channel measures the voltage across PT100.
Figure 16. Temperature measurement principle schematic diagram
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With voltage across and current through the PT100 resistor, the STM32L476ZGT6
microcontroller computes resistance PT100.
For temperatures lower than +100°C, the temperature is given by the following equation,
where PT100 is resistance of the PT100 resistor and T is temperature in degrees
centigrade:
T = ( PT100 – 100 ) ⁄ ( 0.385 )
2.29.5
Limitations
Operating voltage must be in the range from 3.2 V to 3.6 V.
2.30
STM32L476ZGT6 current consumption measurement
STM32L476ZGT6 has a built-in circuit allowing to measure its own current consumption
(IDD) in Run and Low-power modes, except for Shutdown mode.
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It is strongly recommended that, the MCU supply voltage (VDD_MCU line) does not exceed
3.3 V. This is because there are components on STM32L476G-EVAL supplied from 3.3 V
that communicate with the MCU through I/O ports. Voltage exceeding 3.3 V on the MCU
output port may inject current into 3.3 V-supplied peripheral I/Os and false the MCU current
consumption measurement.
2.30.1
IDD measurement principle - analog part
The analog part is based on measuring voltage drop across a shunt resistor, amplified with a
differential amplifier. The STM32L476ZGT6 microcontroller supply current is shunted, by
jumper settings, to flow through the measurement 1 Ω resistor R135: JP11 terminals 1 and 2
are to be open, terminals 3 and 4 closed. When the transistor T2 is in conductive state, the
MCU supply current is proportional to the voltage across R135. When T2 is in highimpedance state, the MCU supply current is proportional to the voltage across the series of
R135 and R123. The former state is used for measuring the current consumption in dynamic
run mode, the latter in low-power mode.
The differential amplifier uses three stages U15B, U15C, U15D of quadruple operational
amplifier device U15, TSZ124. The gain is set to 50, so every 1 mA of supply current is
represented by additional 50 mV at the U15C output, terminal 8 of U15.
The resistance formed with the series of R135 and R123, when T2 is in high-impedance
state, is of 1001 Ω. It makes the voltage on terminal 8 of U15 increase by approximately
50 mV for every µA of MCU power consumption. The full-scale range, with VDD at 1.8 V is
about 30 µA.
Even with precision resistors R136, R125, R129, R132 to set the gain of the differential
amplifier, the output voltage may theoretically become negative. To avoid the need of
negative power supply, a positive offset of about 220 mV is created at the output, at zero
current consumption of the MCU. This offset does not need to be precise. Any dispersion is
compensated through a calibration procedure detailed in Section 2.30.4.
For allowing the IDD measurement, the jumper in the JP11 header must be placed such as
to short its terminals 3 and 4.
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Figure 17. Schematic diagram of the analog part of IDD measurement
+5V
decoupling capacitor
close from TSZ124 part
R128
22K
GND
3
4
C75
100nF
VDD from
power
supply
V+
Current
direction
6
R135
1[1%]
S
4
U15B
TSZ124IPT
R136
7
3K6 0.1%
R129
180K 0.1%
U15C
TSZ124IPT
8
shunts
G
D
5
1
2
6
R123
1K[1%]
differential
amplifier
9
R132
FDC606P
12
U15D
TSZ124IPT
R125
14
13
180K 0.1%
3K6 0.1%
current
measurement
path
JP11
1
2
3
4
bypass path
V-
GND
10
Shunt_x1000 3
2
GND
GND
5
T2
R124
1K
11
C144
100nF
VDD
U15A
TSZ124IPT
1
Current
direction
VDD_MCU
to MCU
2.30.2
Low-power-mode IDD measurement principle - logic part
The target microcontroller can only carry out actions for measuring a voltage when in
dynamic run mode. This is the reason why, voltage representing the current consumed by
the microcontroller when in low-power mode needs to be held by a sample-and-hold circuit,
for being exploited by the microcontroller at a later time, when back in dynamic run mode.
The sample-and-hold (S&H) circuit is built with U13 switch, R122 resistor and C73 sampling
capacitor.
The measurement of low-power-mode current consumption is started and end by the
microcontroller in its dynamic run mode. As, between the start and end event, the
microcontroller must transit through one of its low-power modes, an extra logic is required to
time and control events during this state. It consists of U14 counter, U16 inverter and the
transistor T3. Figure 18 shows the corresponding schematic diagram.
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Hardware layout and configuration
Figure 18. Schematic diagram of logic part of low-power-mode IDD measurement
R122
U13
VCC
PA5
2
VDDC74
5
10K
T3
SN74LVC1G66DCKT 100nF
4
3
VDD
3
2
Shunt_x1000
VDD
SN74LVC1G04DCKT
PC5
FDC606P
100nF
C72
100nF
U14
1
2
3
4
5
6
7
8
Q11
Q12
Q13
Q5
Q4
Q6
Q3
GND
IDD_Measurement
VDD
5
1
2
6
U16
C76
5
4
S
O/I
G
I/O
C
GND
D
1
4
3
C73
1uF
U15C
TSZ124IPT
8
VCC
Q9
Q7
Q8
MR
RS
Rtc
Ctc
74LV4060PW
16
15
14
13
12
11
10
9
VDD
IDD_WAKEUP
R137
220K
R127
220K
PF10
C77
1nF
R134
15K
IDD_CNT_EN
R130
30K
Oscillator frequency 30KHz
The measurement process consists of 3 phases:
Phase 1 - start and transiting to low-power mode
While in dynamic run mode, the MCU sets IDD_CNT_EN signal on its PF10 port low,
starting the measurement process. This makes the counters in U14 start counting the clock
pulses generated with an own RC oscillator. At about 150 ms from the start, the Q12 output
of U14 goes high, terminating the phase 1. After starting the measurement process, the
MCU transits to low-power mode. The duration of the phase 1 of about 150ms allows the
MCU enough time for transiting into low-power mode.
Phase 2 - sampling
The MCU is now in low-power mode. The phase 2 starts with the Q12 port of U14 going
high, 150 ms after the MCU, at that time in dynamic run mode, started the low-power-mode
consumption current measurement process. The transistor T2 goes in high-impedance
mode, which results in setting the analog part in high sensitivity state, needed for measuring
very low currents. The Q13 port of U14 keeps the path between ports I/O and O/I of U13
conductive. The sampling capacitor C73 is charged through the resistor R122 to the voltage
at the output of the differential analog amplifier, representing the current consumed by the
MCU in low-power mode. The duration of the phase 2 is about 150 ms. This time is needed
to allow the voltage on the sampling capacitor C73 to stabilize.
Phase 3 - exiting low-power mode, measurement and end
The MCU is in low-power mode. The voltage across C73 capacitor is now stabilized so it
represents the current consumed by the MCU in low-power mode. The phase 3 starts with
setting the U13 path between ports O/I and I/O to non-conductive state, for the voltage
across C73 to hold. The same event causes the IDD_WAKEUP signal for the MCU to
change state, to signal to the MCU that the voltage on C73 is now ready for being
measured. The MCU transits from low-power mode to dynamic run mode. The voltage on
C73 representing the current the MCU consumed when it was in low-power mode, is now
measured by the MCU, using the ADC port PA5, and stored. The Q12 port transits to low
state at the same time as the Q13 goes high. As a consequence, the analog part of the IDD
measurement circuit is back to low-sensitivity mode adapted for measuring the
microcontroller supply current in its dynamic run mode. The phase 3 and the whole
measurement process ends with the microcontroller setting the IDD_CNT_EN signal back
high. Figure 19 illustrates the timing of the low-power-mode current consumption
measurement process.
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Hardware layout and configuration
UM1855
Figure 19. Low-power-mode IDD measurement timing
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2.30.3
IDD measurement in dynamic run mode
In dynamic run mode, the IDD_CNT_EN remains high. The T2 is in conductive state, setting
the shunt resistor to 1 Ω. The U13 path from port 1 to 2 is permanently conductive and the
voltage on the capacitor C73 follows the MCU current consumption. R122 allows filtering
fast changes.
2.30.4
Calibration procedure
For the measurement to be precise, it is mandatory to perform a calibration before the
measurement. The calibration allows subtracting, from the voltage measured across C73,
the offset at the differential amplifier output, described in Section 2.30.1.
The calibration procedure consists in measuring the offset voltage when the current through
the shunt resistor is zero. The current consumption values measured by the microcontroller
are then compensated for offset, by subtracting the now-known offset number from the
measured number. Setting the current through the shunt resistor to zero is reached through
appropriate setting jumpers in the JP11 jumper header.
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Hardware layout and configuration
Calibration procedure and current measurement compensation steps:
•
On JP11, short terminals 1 and 2 and open terminals 3 and 4. The current through the
shunt resistor is now zero.
•
Run low-power-mode IDD measurement as described in Section 2.30.2. The value
Voffset measured corresponds to offset of the differential amplifier.
•
On JP11, add a second jumper, to short terminals 3 and 4, then remove the jumper
from terminals 1 and 2 of JP11. The MCU supply has not been interrupted and the
supply current now passes through the shunt resistor.
•
Run low-power-mode IDD measurement as described in Section 2.30.2. The value
Vmeasured obtained corresponds to the sum of MCU supply current and the differential
amplifier’s offset Voffset.
•
The software computes a Vout number representing the MCU supply current as
Vout = Vmeasured - Voffset
Table 31. JP11 jumper settings during IDD measurement with calibration
Jumper
Setting
JP11
1 2 3 4
Description
Configuration used to measure Voffset.
JP11 in VDD position
STM32L476ZGT6 supply current does not flow through shunt
resistor.
JP11
JP11
1 2 3 4
Configuration to transit from direct to shunted supply to
STM32L476ZGT6, without ever interrupting the MCU supply.
JP11
Default setting.
Configuration used to measure the MCU supply current.
JP11 in IDD position
STM32L476ZGT6 supply current flows through shunt resistor.
1 2 3 4
İ
İ
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3
Connectors
3.1
RS-232 D-sub male connector CN9
Figure 20. RS-232 D-sub (DE-9M) 9-pole connector (front view)
-36
Table 32. RS-232 D-sub (DE-9M) connector CN9 with HW flow control and ISP support
3.2
Terminal
Terminal name
Terminal
Description
1
NC
6
Bootloader_BOOT0
2
RS232_RX (PB7)
7
NC
3
RS232_TX (PG12)
8
Bootloader_RESET
4
NC
9
NC
5
GND
-
-
Power connector CN22
The STM32L476G-EVAL board can be powered from a DC-5V external power supply via
the CN22 jack illustrated in Figure 21. The central pin of CN22 must be positive.
Figure 21. Power supply connector CN22 (front view)
'&9
*1'
-36
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3.3
Connectors
LCD daughterboard connectors CN11 and CN14
Two 48-pin male headers CN11 and CN14 are used to connect to LCD glass module
daughterboard MB979. The type of connectors, their mutual orientation, distance and
terminal assignment are kept for a number of ST MCU evaluation boards. This
standardization allows developing daughterboards that can be used in multiple evaluation
kits. The width between CN11 pin1 and CN14 pin1 is 700 mils (17.78 mm).
STM32L476ZGT6 ports routed to these two connectors can be accessed on odd CN11 and
CN14 pins (the row of pin 1), when no daughterboard is plugged in.
Daughterboards plugging into CN11 and CN14 must keep the even terminals of CN11 and
CN14 open.
Table 33 shows the signal assignment to terminals.
Table 33. CN11 and CN14 daughterboard connectors
CN11
CN14
Odd pin
MCU port
Odd pin
MCU port
1
PA9
1
PD2
3
PA8
3
PC12
5
PA10
5
PC11
7
PB9
7
PC10
9
PB11
9
PB7
11
PB10
11
PC4
13
PB5
13
PC5
15
PB14
15
PC6
17
PB13
17
PC7
19
PB12
19
PC8
21
PA15
21
PC9
23
PB8
23
PD8
25
PB15
25
PD9
27
PC2
27
PD10
29
PC1
29
PD11
31
PC0
31
PD12
33
PA3
33
PD13
35
PA2
35
PD14
37
PB0
37
PD15
39
PA7
39
PE0
41
PA6
41
PE1
43
PB4
43
PE2
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Table 33. CN11 and CN14 daughterboard connectors (continued)
CN11
3.4
CN14
Odd pin
MCU port
Odd pin
MCU port
45
PB3
45
PE3
47
PB1
47
PA1
Extension connectors CN6 and CN7
Table 34. Daughterboard extension connector CN6
62/101
Pin
Description
Alternative
Functions
How to disconnect Alternative functions to
use on the extension connector
1
GND
-
3
PG6
CODEC_INT,
MC_ICL_Shutout
5
PA13
TMS/SWDIO
Do not use Trace connector CN12 and JTAG
connector CN15
7
PA12
USBOTG_DP
Remove R4
9
PG8
LPUART_RX_3V3
11
GND
-
13
PG2
A12
15
PD3
DFSDM_DATIN1
17
PD0
D2
19
PD5
FMC_NWE
Cannot be disconnected from SRAM and Flash
memory, but is an input for SRAM and Flash
memory
21
PG10
LCD_NE3
Cannot be disconnected from TFT LCD level
shifters U21 and U22, but is an input for TFT
LCD.
23
PD7
FMC_NE1
Remove R18
25
PF0
A0
27
PG11
USART1_CTS_3V3
Remove R93
29
PG13
I2C_SDA
Remove R58
31
PG12
USART1_RTS
Remove R116
33
PG14
I2C_SCL
Remove R61
35
PG15
IOExpander_INT
Remove R228
37
PF4
A4
Remove R35, Open SB5
Remove R158, R188
Remove R18 to deselect SRAM U2
Remove R43 to deselect Flash memory U5
Remove R23
Remove R18 to deselect SRAM U2
Remove R43 to deselect Flash memory U5
Remove R18 to deselect SRAM U2
Remove R43 to deselect Flash memory U5
Remove R18 to deselect SRAM U2
Remove R43 to deselect Flash memory U5
DocID027351 Rev 5
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Connectors
Table 34. Daughterboard extension connector CN6 (continued)
Pin
Description
Alternative
Functions
How to disconnect Alternative functions to
use on the extension connector
39
GND
-
-
2
+3V3
-
-
4
PG7
LPUART_TX
Remove R119, R189
6
PA11
USBOTG_DM
Remove R3
8
PA14
TCK/SWCLK
Do not use Trace connector CN12 and JTAG
connector CN15
10
PG5
A15
Remove R18 to deselect SRAM U2
Remove R43 to deselect Flash memory U5
12
PG3
A13
Remove R18 to deselect SRAM U2
Remove R43 to deselect Flash memory U5
14
PG4
A14
Remove R18 to deselect SRAM U2
Remove R43 to deselect Flash memory U5
16
PD1
D3
Remove R18 to deselect SRAM U2
Remove R43 to deselect Flash memory U5
18
PD4
FMC_NOE
Remove R18 to deselect SRAM U2
Remove R43 to deselect Flash memory U5
20
PG9
FMC_NE2
Remove R43
22
GND
-
24
PD6
SAI1_SDA,
FMC_NWAIT
26
PF1
A1
28
D5V
-
30
PC13
Wake-up
32
PF2
A2
Remove R18 to deselect SRAM U2
Remove R43 to deselect Flash memory U5
34
PF3
A3
Remove R18 to deselect SRAM U2
Remove R43 to deselect Flash memory U5
36
GND
-
38
PF5
A5
40
PB6
USART1_TX
Remove R53, open SB10
Remove R18 to deselect SRAM U2
Remove R43 to deselect Flash memory U5
Remove R244
Remove R18 to deselect SRAM U2
Remove R43 to deselect Flash memory U5
Remove R118
Table 35. Daughterboard extension connector CN7
Pin
Description
Alternative
Functions
How to disconnect Alternative functions to
use on the extension connector
1
GND
-
-
3
PE14
D11
-
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Table 35. Daughterboard extension connector CN7 (continued)
64/101
Pin
Description
Alternative
Functions
How to disconnect Alternative functions to
use on the extension connector
5
PE12
D9
-
7
PE10
D7
-
9
PE8
D5
-
11
PG1
A11
-
13
PB2
15
GND
-
-
17
PF12
A6
-
19
PF11
NFC_NSS
21
PE4
A20, TRACE_D1
Remove R84, SB40
23
PE5
A21, TRACE_D2
Remove R85, SB38
25
PC14
OSC32_IN
Remove R87, Close SB41
27
PF6
SAI1_SDB
Remove R105
29
PF9
SAI1_FSB,
MC_PFC_sync
Remove R90, SB25
31
PF10
IDD_CNT_EN,
MC_PFC_PWM
Remove R91, SB37
33
PH1
OSC_OUT
35
PA5
IDD_Measurement
37
PA0
OpAmp1_INP,
MC_EncA
39
GND
-
-
2
PE15
D12
-
4
PE13
D10
-
6
PE11
D8
-
8
PE9
D6
-
10
PE7
D4
-
12
PG0
A10
-
14
PF15
A9
-
16
PF14
A8
-
18
PF13
A7
-
20
BOOT0
BootLoader from
UART
Remove JP8
22
PE6
A21, TRACE_D3
Remove R86, SB39
24
PC15
OSC32_OUT
LED1,
Remove R54, SB11
MC_DissipativeBrake
Do not connect the NFC daughterboard to
connector CN13
Remove R95, close SB23
Remove R69
Remove R83, SB35
Remove R88, close SB33
DocID027351 Rev 5
UM1855
Connectors
Table 35. Daughterboard extension connector CN7 (continued)
3.5
Pin
Description
Alternative
Functions
How to disconnect Alternative functions to
use on the extension connector
26
GND
-
28
PF7
SAI1_MCKB
Remove R106
30
PF8
SAI1_SCKB
Remove R89
32
RESET#
-
34
PH0
OSCIN
Remove crystal X2, C54, close SB24
36
PC3
VLCD
Remove R94
38
PA4
ADC_DAC
Remove R73
40
VDD
-
-
-
-
ST-LINK/V2-1 programming connector CN16
The connector CN16 is used only for embedded ST-LINK/V2-1 programming, during board
manufacture. It is not populated by default and not for use by the end user.
3.6
ST-LINK/V2-1 Standard-B USB connector CN17
The USB connector CN17 is used to connect the on-board ST-LINK/V2-1 facility to PC for
flashing and debugging software.
Figure 22. USB type B connector CN17 (front view)
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Table 36. USB Standard-B connector CN17
Terminal
3.7
Description
1
VBUS(power)
2
3
Terminal
Description
4
GND
DM
5,6
Shield
DP
-
-
JTAG connector CN15
Figure 23. JTAG debugging connector CN15 (top view)
D^ϯϬϳϮϮsϮ
Table 37. JATG debugging connector CN15
66/101
Terminal
Function / MCU port
Terminal
Function / MCU port
1
VDD power
2
VDD power
3
PB4
4
GND
5
PA15
6
GND
7
PA13
8
GND
9
PA14
10
GND
11
RTCK
12
GND
13
PB3
14
GND
15
RESET#
16
GND
17
DBGRQ
18
GND
19
DBGACK
20
GND
DocID027351 Rev 5
UM1855
3.8
Connectors
ETM trace debugging connector CN12
Figure 24. Trace debugging connector CN12 (top view)
D^ϯϬϳϮϮsϮ
Table 38. Trace debugging connector CN12
Terminal
Function / MCU port
Terminal
Function / MCU port
1
VDD power
2
TMS/PA13
3
GND
4
TCK/PA14
5
GND
6
TDO/PB3
7
KEY
8
TDI/PA15
9
GND
10
RESET#
11
GND
12
TraceCLK/PE2
13
GND
14
TraceD0/PE3 or SWO/PB3
15
GND
16
TraceD1/PE4 or nTRST/PB4
17
GND
18
TraceD2/PE5
19
GND
20
TraceD3/PE6
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Connectors
3.9
UM1855
microSD card connector CN18
Figure 25. microSD card connector CN18
(YDOXDWLRQERDUG
PLFUR6'
FDUG
&1
06Y 9
Table 39. microSD card connector CN18
3.10
Terminal
Terminal name (MCU port)
Terminal
Terminal name (MCU port)
1
SDIO_D2 (PC10)
6
Vss/GND
2
SDIO_D3 (PC11)
7
SDIO_D0 (PC8)
3
SDIO_CMD (PD2)
8
SDIO_D1 (PC9)
4
VDD
9
GND
5
SDIO_CLK (PC12)
10
MicroSDcard_detect (PA8)
ADC/DAC connector CN8
Figure 26. Analog input-output connector CN8 (top view)
ϭ
Ϯ
06Y 9
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Connectors
Table 40. Analog input-output connector CN8
3.11
Terminal
Function / MCU port
Terminal
Function / MCU port
1
GND
2
analog input-output PA4
RF-EEPROM daughterboard connector CN3
Figure 27. RF-EEPROM daughterboard connector CN3 (front view)
069
Table 41. RF-EEPROM daughterboard connector CN3
3.12
Terminal
Terminal name (MCU port)
Terminal
Terminal name (MCU port)
1
I2C_SDA (PG13)
5
+3V3
2
NC
6
NC
3
I2C_SCL (PG14)
7
GND
4
EXT_RESET(PC6)
8
+5 V
Motor control connector CN2
Figure 28. Motor control connector CN2 (top view)
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Table 42. Motor control connector CN2
3.13
CN2
terminal
Description
MCU port
CN2
terminal
MCU port
Description
1
Emergency STOP
PC9
2
-
GND
3
PWM_1H
PC6
4
-
GND
5
PWM_1L
PA7
6
-
GND
7
PWM_2H
PC7
8
-
GND
9
PWM_2L
PB0
10
-
GND
11
PWM_3H
PC8
12
-
GND
13
PWM_3L
PB1
14
PC5
BUS VOLTAGE
15
CURRENT A
PC0
16
-
GND
17
CURRENT B
PC1
18
-
GND
19
CURRENT C
PC2
20
-
GND
21
ICL Shutout
PG6
22
-
GND
23
DISSIPATIVE
BRAKE
PB2
24
PC4
PCD Ind Current
25
+5V power
-
26
PA3
Heat sink
temperature
27
PFC SYNC
PF9
28
-
3.3 V power
29
PFC PWM
PF10
30
PB12
PFC Shut Down
31
Encoder A
PA0
32
PA6
PFC Vac
33
Encoder B
PA1
34
PA2
Encoder Index
USB OTG FS Micro-AB connector CN1
Figure 29. USB OTG FS Micro-AB connector CN1 (front view)
06 9
Table 43. USB OTG FS Micro-AB connector CN1
70/101
Terminal
Terminal name (MCU port)
Terminal
Terminal name (MCU port)
1
VBUS (PA9 & PB13)
4
ID (PA10)
2
D- (PA11)
5
GND
3
D+ (PA12)
-
-
DocID027351 Rev 5
UM1855
3.14
Connectors
CAN D-sub male connector CN5
Figure 30. CAN D-sub (DE-9M) 9-pole male connector CN5 (front view)
-36
Table 44. CAN D-sub (DE-9M) 9-pins male connector CN5
3.15
Terminal
Terminal name
Terminal
Terminal name
1,4,8,9
NC
7
CANH
2
CANL
3,5,6
GND
NFC connector CN13
Figure 31. NFC female connector CN13 (top view)
06Y 9
Table 45. NFC CN13 terminal assignment
CN13
terminal
NFC signal
MCU port
1
NFC_IRQOUTN or
UART_TX
PB7
Interrupt output for NFC
Connected to STM32L476ZGT6 UART RX
2
NFC_IRQINN or
UART_RX
PB6
Interrupt input for CR95HF
Connected to STM32L476ZGT6 UART TX
Description
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Table 45. NFC CN13 terminal assignment (continued)
72/101
CN13
terminal
NFC signal
MCU port
3
NFC_NSS
PF11
SPI slave select
4
NFC_MISO
PB14
SPI data, slave output
5
NFC_MOSI
PB15
SPI data, slave input
6
NFC_SCK
PB13
SPI serial clock
7
+3V3
PB6
Main power supply/power supply for RF drivers
8
GND
PB7
Ground
Description
DocID027351 Rev 5
UM1855
Schematic diagrams
Appendix A
Schematic diagrams
This section provides design schematics for the STM32L476G-EVAL key features to help
users to implement these features in application designs.
This section includes:
•
Overall schematics for the board, see Figure 32
•
MCU, LCD daughterboard and I/O expander interfaces, see Figure 33
•
STM32L476G-EVALMCU part 1, see Figure 34
•
STM32L476G-EVAL MCU part 2, see Figure 35
•
LCD glass module daughterboard connectors, see Figure 36
•
I/O expander, see Figure 37
•
Power supply, see Figure 38
•
Smartcard, SWP and NFC, see Figure 39
•
USART and IrDA, see Figure 40
•
SRAM and NOR Flash memory devices, see Figure 41
•
TFT LCD, see Figure 42
•
Extension connector, see Figure 43
•
Quad-SPI Flash memory device, Figure 44
•
microSD card, see Figure 45
•
Physical control peripherals, see Figure 46
•
CAN transceiver, see Figure 47
•
Touch-sensing device, see Figure 48
•
USB_OTG_FS port, see Figure 49
•
IDD measurement, see Figure 50
•
Audio codec device, see Figure 51
•
STPMS2L and PT100, see Figure 52
•
RF-EEPROM and EEPROM, see Figure 53
•
Motor control connector, see Figure 54
•
JTAG and trace debug connectors, Figure 55
•
ST-LINK/V2-1, see Figure 56
DocID027351 Rev 5
73/101
100
U_SWP_SmartCard_NFC
SWP_SmartCard_NFC.SchDoc
U_MCU_LCDGlass_Symbol
MCU_LCDGlass_Symbol.SchDoc
NFC_MOSI
NFC_MISO
NFC_SCK
NFC_NSS
LED1
SWP_IO
LED2
SmartCard_OFF
LED3
SmartCard_IO
LED4
SmartCard_CLK
JOY_SEL
SmartCard_CMDVCC
JOY_DOWN
SmartCard_3/5V
JOY_LEFT
SmartCard_RST
JOY_RIGHT
JOY_UP
Key
Comp2_INP
USART1_TX
Comp2_OUT
USART1/IrDA_RX_3V3
OpAmp1_INP
USART1_RTS
OpAmp1_INM
USART1_CTS_3V3
OpAmp1_OUT
ADC_DAC
NFC_MOSI
NFC_MISO
NFC_SCK
NFC_NSS
SWP_IO
SmartCard_OFF
SmartCard_IO
SmartCard_CLK
SmartCard_CMDVCC
SmartCard_3/5V
SmartCard_RST
NFC_IRQOUTN
NFC_IRQINN
U_USART_IrDA
USART_IrDA.SchDoc
USART1_TX
USART1/IrDA_RX_3V3
USART1_RTS
USART1_CTS_3V3
LPUART_TX
LPUART_RX_3V3
Bootloader_BOOT0_3V3
Bootloader_RESET_3V3
NFC_IRQINN
NFC_IRQOUTN
RESET#
U_JTAG&Trace
JTAG&Trace.SchDoc
TMS/SWDIO
TCK/SWCLK
TDO/SWO
TDI
TRST
TRACE_D0
TRACE_D1
TRACE_D2
TRACE_D3
TRACE_CK
D[0..15]
A[0..23]
FMC_NE1
FMC_NE2
FMC_NWE
FMC_NOE
FMC_NBL0
FMC_NBL1
FMC_NWAIT
FMC_NBL0
FMC_NBL1
FMC_NWAIT
U_LCD_TFT
RESET#
BOOT0
U_Extension connector
Extension connector.SCHDOC
RESET#
PA[0..15]
PB[0..15]
PC[0..15]
PD[0..15]
PE[0..15]
PF[0..15]
PG[0..15]
PH0
PA[0..15]
PB[0..15]
PC[0..15]
PD[0..15]
PE[0..15]
PF[0..15]
PG[0..15]
PH0
PH1
U_QSPI
QSPI.SchDoc
QSPI_D0
QSPI_D1
QSPI_D2
QSPI_D3
QSPI_CLK
QSPI_CS
QSPI_D0
QSPI_D1
QSPI_D2
QSPI_D3
QSPI_CLK
QSPI_CS
U_MicroSD
MicroSD.SchDoc
uSD_D0
uSD_D1
uSD_D2
uSD_D3
uSD_CLK
uSD_CMD
uSD_DETECT
TKEY
TKEY_CS
SHIELD
SHIELD_CS
U_USB_OTG_FS
USB_OTG_FS.SchDoc
USBOTG_DM
USBOTG_DP
USBOTG_ID
USBOTG_VBUS
USBOTG_OVRCR
USBOTG_PRDY
USBOTG_PPWR
IDD_Measurement
IDD_CNT_EN
IDD_WAKEUP
IDD_Measurement
IDD_CNT_EN
IDD_WAKEUP
SAI1_SDA
SAI1_SDB
SAI1_SCKB
SAI1_MCKB
SAI1_FSB
DMIC_DATIN
SAI1_SDA
SAI1_SDB
SAI1_SCKB
SAI1_MCKB
SAI1_FSB
DMIC_DATIN
DFSDM_CKOUT
CODEC_INT
I2C_SDA
I2C_SCL
U_IDD_measurement
IDD_measurement.SchDoc
U_Audio
CODEC_INT
D[0..15]
A[0..23]
LCD_NE3
FMC_NWE
FMC_NOE
BL_Control
IOExpander_X+
IOExpander_XIOExpander_Y+
IOExpander_Y-
uSD_D0
uSD_D1
uSD_D2
uSD_D3
uSD_CLK
uSD_CMD
uSD_DETECT
VREF+
CAN_RX
CAN_TX
FMC_NE1
FMC_NE2
LCD_TFT.SchDoc
D[0..15]
A[0..23]
LCD_NE3
FMC_NWE
FMC_NOE
BL_Control
IOExpander_X+
IOExpander_XIOExpander_Y+
IOExpander_Y-
VREF+
USBOTG_DM
USBOTG_DP
USBOTG_ID
USBOTG_VBUS
USBOTG_OVRCR
USBOTG_PRDY
USBOTG_PPWR
RESET#
U_SRAM&Flash
SRAM&Flash.SchDoc
PH1 BOOT0
DocID027351 Rev 5
RESET#
TKEY
TKEY_CS
SHIELD
SHIELD_CS
i PCB Rule
Power.SchDoc
U_Touch Sensing
Touch Sensing.SchDoc
Clearance Constraint [Clearance = 10mil]
Matched Net Lengths [Tolerance = 100mil]
i
i
TMS/SWDIO
TCK/SWCLK
TDO/SWO
TDI
TRST
TRACE_D0
TRACE_D1
TRACE_D2
TRACE_D3
TRACE_CK
U_Power
CAN.SchDoc
LPUART_TX
LPUART_RX_3V3
i PCB Rule
peripherals.SchDoc
U_CAN
CAN_RX
CAN_TX
LPUART_TX
LPUART_RX_3V3
TMS/SWDIO
TCK/SWCLK
TDO/SWO
TDI
TRST
U_peripherals
LED1
LED2
LED3
LED4
JOY_SEL
JOY_DOWN
JOY_LEFT
JOY_RIGHT
JOY_UP
KEY
Comp2_INP
Comp2_OUT
OpAmp1_INP
OpAmp1_INM
OpAmp1_OUT
ADC_DAC
Bootloader_BOOT0_3V3
Bootloader_RESET_3V3
U_ST_LINK
ST_LINK.SCHDOC
Schematic diagrams
74/101
Figure 32. STM32L476G-EVAL top
DFSDM_CKOUT
DFSDM_DATIN1
PT100_DATIN
I2C_SDA
I2C_SCL
EXT_RESET
I2C2_SDA
I2C2_SCL
MC_EmergencySTOP
MC_PWM_1H
MC_PWM_1L
MC_PWM_2H
MC_PWM_2L
MC_PWM_3H
MC_PWM_3L
MC_CurrentA
MC_CurrentB
MC_CurrentC
MC_ICL_Shutout
MC_DissipativeBrake
MC_PFC_sync
MC_PFC_PWM
MC_EncA
MC_EncB
MC_BusVoltage
MC_PFC_IndCurr
MC_Temperature
MC_PFC_Shutdown
MC_PFC_Vac
MC_EncIndex
Audio.SchDoc
U_STPMS2&PT100
STPMS2&PT100.SchDoc
DFSDM_CKOUT
DFSDM_DATIN1
PT100_DATIN
U_RF_I2C_EEPROM
RF_I2C_EEPROM.SchDoc
I2C_SDA
I2C_SCL
EXT_RESET
I2C2_SDA
I2C2_SCL
U_MotorControl
MotorControl.SchDoc
MC_EmergencySTOP
MC_PWM_1H
MC_PWM_1L
MC_PWM_2H
MC_PWM_2L
MC_PWM_3H
MC_PWM_3L
MC_CurrentA
MC_CurrentB
MC_CurrentC
MC_ICL_Shutout
MC_DissipativeBrake
MC_PFC_sync
MC_PFC_PWM
MC_EncA
MC_EncB
MC_BusVoltage
MC_PFC_IndCurr
MC_Temperature
MC_PFC_Shutdown
MC_PFC_Vac
MC_EncIndex
Note: In all sheets, Italic format is used to differentiate text from schematic Net labels.
Title: Top schematic
Project: STM32L476G-EVAL
Size: A3
Reference: MB1144
Date: 10/7/2016
Revision: C-02
Sheet: 1 of 25
UM1855
U_IO_Expandor
IO_Expandor.SchDoc
U_MCU2
MCU2.SchDoc
Key
Bootloader_BOOT0_3V3
Bootloader_RESET_3V3
Key
Bootloader_BOOT0_3V3
Bootloader_RESET_3V3
SAI1_SDB
SAI1_MCKB
SAI1_SCKB
SAI1_FSB
SAI1_SDB
SAI1_MCKB
SAI1_SCKB
SAI1_FSB
PH0
PH1
SHIELD
SHIELD_CS
PH0
PH1
SHIELD
SHIELD_CS
IDD_CNT_EN
CODEC_INT
BOOT0
RESET#
RESET#
DocID027351 Rev 5
TMS/SWDIO
TCK/SWCLK
TDO/SWO
TDI
TRST
TRACE_D0
TRACE_D1
TRACE_D2
TRACE_D3
TRACE_CK
DFSDM_DATIN1
IDD_Measurement
DFSDM_DATIN1
IDD_Measurement
OpAmp1_INP
ADC_DAC
OpAmp1_INP
ADC_DAC
USBOTG_DP
USBOTG_DM
USBOTG_DP
USBOTG_DM
PA[0..15]
PB[0..15]
PD[0..15]
PE[0..15]
A[0..23]
D[0..15]
PA[0..15]
PB[0..15]
PD[0..15]
PE[0..15]
LCDCOM7
LCDCOM[0..3]
LCDSEG[28..39]
LCDSEG21
LCDSEG[0..17]
A[20..22]
D[0..15]
A[0..23]
D[0..15]
LCDCOM[0..7]
LCDSEG[0..39]
A23
A[16..19]
D[0..15]
LCDCOM7
LCDCOM[0..3]
LCDSEG[28..39]
LCDSEG21
LCDSEG[0..17]
A[20..22]
D[0..15]
LCDCOM[0..7]
LCDSEG[0..39]
A23
A[16..19]
D[0..15]
DFSDM_CKOUT
DMIC_DATIN
PT100_DATIN
SmartCard_CLK
SmartCard_IO
SmartCard_CLK
SmartCard_IO
USBOTG_VBUS
USBOTG_ID
USBOTG_PRDY
USBOTG_OVRCR
USBOTG_PPWR
USBOTG_VBUS
USBOTG_ID
USBOTG_PRDY
USBOTG_OVRCR
USBOTG_PPWR
IDD_WAKEUP
IDD_WAKEUP
OpAmp1_INM
OpAmp1_OUT
Comp2_INP
Comp2_OUT
OpAmp1_INM
OpAmp1_OUT
Comp2_INP
Comp2_OUT
USART1_RTS
USART1_CTS_3V3
LPUART_TX
LPUART_RX_3V3
JOY_SEL
JOY_DOWN
JOY_LEFT
JOY_RIGHT
JOY_UP
JOY_SEL
JOY_DOWN
JOY_LEFT
JOY_RIGHT
JOY_UP
BL_Control
SmartCard_3/5V
SmartCard_CMDVCC
SmartCard_OFF
SmartCard_RST
LED2
LED4
EXT_RESET
MC_EmergencySTOP
MC_PWM_1H
MC_PWM_2H
MC_PWM_3H
MC_BusVoltage
MC_CurrentA
MC_CurrentB
MC_CurrentC
MC_ICL_Shutout
MC_PFC_IndCurr
MC_PFC_sync
MC_PFC_PWM
U_MCU
MCU.SchDoc
SAI1_SDA
SAI1_SDA
TKEY
TKEY_CS
TKEY
TKEY_CS
LED1
MC_PWM_1L
MC_PWM_2L
MC_PWM_3L
MC_PFC_Shutdown
MC_DissipativeBrake
MC_Temperature
MC_PFC_Vac
MC_EncA
MC_EncB
MC_EncIndex
U_LCD_Glass
LCD_Glass.SchDoc
I2C2_SDA
I2C2_SCL
USART1/IrDA_RX_3V3
FMC_NBL0
FMC_NBL1
LED3
NFC_MOSI
NFC_MISO
NFC_SCK
SWP_IO
CAN_RX
CAN_TX
uSD_CMD
uSD_CLK
uSD_D0
uSD_D1
uSD_D2
uSD_D3
uSD_DETECT
LED2
LED4
EXT_RESET
I2C_SCL
I2C_SDA
I2C_SCL
I2C_SDA
QSPI_D0
QSPI_D1
QSPI_D2
QSPI_D3
QSPI_CLK
QSPI_CS
USART1_TX
SmartCard_3/5V
SmartCard_CMDVCC
SmartCard_OFF
SmartCard_RST
MC_EmergencySTOP
MC_PWM_1H
MC_PWM_2H
MC_PWM_3H
MC_BusVoltage
MC_CurrentA
MC_CurrentB
MC_CurrentC
MC_ICL_Shutout
MC_PFC_IndCurr
MC_PFC_sync
MC_PFC_PWM
QSPI_D0
QSPI_D1
QSPI_D2
QSPI_D3
QSPI_CLK
QSPI_CS
FMC_NOE
FMC_NWE
FMC_NE1
FMC_NWAIT
BL_Control
FMC_NOE
FMC_NWE
FMC_NE1
FMC_NWAIT
LED1
USART1_TX
MC_PWM_1L
MC_PWM_2L
MC_PWM_3L
MC_PFC_Shutdown
MC_DissipativeBrake
MC_Temperature
MC_PFC_Vac
MC_EncA
MC_EncB
MC_EncIndex
I2C2_SDA
I2C2_SCL
USART1/IrDA_RX_3V3
FMC_NBL0
FMC_NBL1
LED3
NFC_MOSI
NFC_MISO
NFC_SCK
SWP_IO
CAN_RX
CAN_TX
uSD_CMD
uSD_CLK
uSD_D0
uSD_D1
uSD_D2
uSD_D3
uSD_DETECT
75/101
Title: MCU_LCDGlassl
Project: STM32L476G-EVAL
Size: A3
Reference: MB1144
Date: 10/7/2016
Revision: C-02
Sheet: 2 of 25
Schematic diagrams
DFSDM_CKOUT
DMIC_DATIN
PT100_DATIN
NFC_NSS
IOExpander_X+
IOExpander_XIOExpander_Y+
IOExpander_Y-
IOExpander_INT
LCDCOM[4..6]
LCDSEG[18..20]
LCDSEG[22..27]
A[0..15]
D[0..15]
BOOT0
RESET#
TMS/SWDIO
TCK/SWCLK
TDO/SWO
TDI
TRST
TRACE_D0
TRACE_D1
TRACE_D2
TRACE_D3
TRACE_CK
NFC_NSS
IOExpander_X+
IOExpander_XIOExpander_Y+
IOExpander_Y-
IOExpander_INT
I2C_SCL
I2C_SDA
PC[0..15]
PF[0..15]
PG[0..15]
LCDCOM[4..6]
LCDSEG[18..20]
LCDSEG[22..27]
A[0..15]
D[0..15]
LCD_NE3
FMC_NE2
USART1_RTS
USART1_CTS_3V3
LPUART_TX
LPUART_RX_3V3
IDD_CNT_EN
CODEC_INT
PC[0..15]
PF[0..15]
PG[0..15]
LCD_NE3
FMC_NE2
UM1855
Figure 33. MCU, LCD daughterboard and I/O expander interfaces
OpAmp1_INP
R83
0
SB35
Open by default
MC_EncA
LCDSEG0
PA1
PA2
R81
0
0
SB31
Open by default
MC_EncIndex
LCDSEG2
PA3
MC_Temperature
LCDSEG3
R82
SB32
Open by default
MC_EncB
LCDSEG1
Schematic diagrams
76/101
Figure 34. STM32L476G-EVAL MCU part 1
PA6
R78
0
U7A
SB22
Open by default
PA0
35
R68
0
SB21
Open by default
SB20
Open by default
QSPI_D3
MC_PFC_Vac
34
36
37
ADC_DAC
LCDSEG4
PA7
QSPI_D2
MC_PWM_1L
R66 0
IDD_Measurement
R69
0
PA4
40
PA5
41
SB18
Open by default
SB19
Open by default
42
43
LCDCOM0
PA8
100
LCDCOM1
PA9
101
LCDCOM2
PA10 102
PA11 103
USBOTG_DM
DocID027351 Rev 5
PA12 104
USBOTG_DP
PA13 105
TMS/SWDIO
PA14 109
TCK/SWCLK
LCDSEG17
TDI
PA15 110
PA0-WKUP1
PD0
PA1
PD1
PA2
PD2
PA3
PD3
PA4
PD4
PA5
PD5
PA6
PD6
PA7
PD7
PA8
PD8
PA9
PD9
PA10
PD10
PA11
PD11
PA12
PD12
PA13
PD13
PA14
PD14
PA15
PD15
PB0
PE0
PB1
PE1
PB2
PE2
PB3
PE3
PB4
PE4
PB5
PE5
PB6
PE6
PB7
PE7
PB8
PE8
PB9
PE9
PB10
PE10
PB11
PE11
PB12
PE12
PB13
PE13
PB14
PE14
PB15
PE15
114 PD0
115 PD1
116 PD2
D2
D3
LCDCOM7
117 PD3
DFSDM_DATIN1
118 PD4
FMC_NOE
119 PD5
FMC_NWE
122 PD6
R53
123 PD7
FMC_NE1
77
PD8
LCDSEG28
78
PD9
LCDSEG29
79
PD10
LCDSEG30
80
PD11
LCDSEG31
81
PD12
LCDSEG32
82
PD13
LCDSEG33
85
PD14
LCDSEG34
86
PD15
LCDSEG35
0
SB10
Open by default
SAI1_SDA
FMC_NWAIT
R103
PE2
LCDSEG38
0
SB26
TRACE_CK
Open by default
R104
PE3
LCDSEG39
0
LCDSEG5
LCDSEG6
PB1
QSPI_D0
MC_PWM_3L
PA[0..15]
PB[0..15]
PD[0..15]
PE[0..15]
R56
0
SB12
Open by default
SB13
Open by default
PB0
QSPI_D1
MC_PWM_2L
R62
46
0
SB14
Open by default
SB15
Open by default
47
TDO/SWO
LED1
PA[0..15]
MC_DissipativeBrake
PB[0..15]
R54
0
SB11
Open by default
TRST
LCDSEG7
PE[0..15]
LCDSEG10 PB10
QSPI_CLK
R50
0
48
PB3
133
LCDSEG8
PB4
134
LCDSEG9
PB5
135
PB6
136
PB7
137
USART1_TX
LCDSEG21
PD[0..15]
PB2
LCDSEG16
PB8
139
LCDCOM3
PB9
140
SB9
Open by default
69
70
D[0..15]
A[20..22]
RESET#
D[0..15]
A[20..22]
LCDSEG11 PB11
QSPI_CS
R48
0
RESET#
LCDSEG12 PB12
R39
0
TKEY
MC_PFC_Shutdown
LCDCOM[0..3]
LCDCOM7
LCDSEG[28..39]
LCDSEG21
74
LCDSEG14
PB14
75
LCDSEG15
PB15
76
LCDSEG36
142 PE1
LCDSEG37
TRACE_D0
R84
1
0
A20
R100
2
SB40
3
PE4
4
PE5
5
PE6
58
PE7
TRACE_D1
Open by default
R85
0
SB38
PE8
D5
60
PE9
D6
63
PE10
D7
64
PE11
D8
A21
R101
D4
59
R86
TRACE_D2
PE12
D9
PE13
D10
67
PE14
D11
68
PE15
D12
A22
0
R102
SB39
66
GND
100K
Open by default
65
GND
100K
Open by default
GND
100K
TRACE_D3
STM32L476ZGT6U
SB3
Open by default
LCDCOM[0..3]
LCDCOM7
LCDSEG13 PB13
TKEY_CS
LCDSEG[0..17]
73
SB8
Open by default
141 PE0
R38
0
SB6
Open by default
LCDSEG[0..17]
LCDSEG[28..39]
LCDSEG21
Project: STM32L476G-EVAL
Size: A3
Reference: MB1144
Date: 10/7/2016
Revision: C-02
Sheet: 3 of 25
UM1855
Title: MCU
LCDSEG18 PC0
MC_CurrentA
LCDSEG19 PC1
MC_CurrentB
LCDSEG20 PC2
R97
UM1855
Figure 35. STM32L476G-EVAL MCU part 2
0
SB34
Open by default
R98
0
SB36
Open by default
R99
0
U7C
MC_CurrentC
SB42
Open by default
26
TP7
VLCD
VLCD input
R94
0
27
C58
1uF
28
PC3
LCDSEG22 PC4
MC_PFC_IndCurr
R65
0
29
44
SB17
Open by default
45
96
LCDSEG23 PC5
MC_BusVoltage
R64
97
0
98
SB16
Open by default
DocID027351 Rev 5
99
LCDSEG24 PC6
SHIELD
MC_PWM_1H
R36
0
SB2
Open by default
SB27
Open by default
SHIELD_CS
MC_PWM_2H
R33
PC10 111
LCDCOM5
PC11 112
LCDCOM6
PC12 113
Key
C56
LCDSEG25 PC7
LCDCOM4
R87
0
SB4
Open by default
SB30
Open by default
0
2.7pF
PC13
7
PC14
8
PC15
9
X1
PC0
PF0
PC1
PF1
PC2
PF2
PC3
PF3
PC4
PF4
PC5
PF5
PC6
PF6
PC7
PF7
PC8
PF8
PC9
PF9
PC10
PF10
PC11
PF11
PC12
PF12
PC13-WKUP2
PF13
PC14-OSC32_IN
PF14
PC15-OSC32_OUT
PF15
32.768 kHz crystal
PG0
LCDSEG26 PC8
PG1
C57
MC_PWM_3H
R88
SB28
Open by default
PG2
0
2.7pF
PG3
NDK NX3215SA-32.768KHZ-EXS00A-MU00525
LCDSEG27 PC9
PC[0..15]
PF[0..15]
PG[0..15]
MC_EmergencySTOP
PC[0..15]
PG4
SB29
Open by default
PG5
PG6
PF[0..15]
PG7
PG[0..15]
PH0
C54
20pF
LCDSEG[22..27]
LCDCOM[4..6]
20pF
PG10
PG11
25
BOOT0
138
NRST
PG13
BOOT0
PG14
R67
10K
SW1
C141
100nF
PG9
PG12
LCDSEG[18..20]
LCDCOM[4..6]
PH1
RESET#
B1
RESET
PH1-OSC_OUT
390
PH1
LCDSEG[22..27]
24
PH0-OSC_IN
PG15
PF0
A0
11
PF1
A1
12
PF2
A2
13
PF3
A3
14
PF4
A4
15
PF5
A5
18
PF6
19
PF7
20
PF8
R90
21
PF9
22
PF10
SB25
Open by default
R91
0
49
PF11
50
PF12
A6
53
PF13
A7
54
PF14
A8
55
PF15
A9
56
PG0
A10
57
PG1
A11
87
PG2
A12
88
PG3
A13
89
PG4
A14
90
PG5
A15
91
PG6
92
PG7
93
PG8
R105
0
R106
0
R89
0
SAI1_SDB
SAI1_MCKB
SAI1_SCKB
0
SB37
Open by default
NFC_NSS
R35
0
SB5
Open by default
R34
0
SAI1_FSB
MC_PFC_sync
IDD_CNT_EN
MC_PFC_PWM
CODEC_INT
MC_ICL_Shutout
LPUART_TX
LPUART_RX_3V3
124 PG9
FMC_NE2
125 PG10
LCD_NE3
126 PG11
USART1_CTS_3V3
127 PG12
USART1_RTS
128 PG13
R58
0
129 PG14
R61
0
I2C_SDA
I2C_SCL
132 PG15
IOExpander_INT
JP8
STM32L476ZGT6U
Header 2X1
R57
R60
1K2
1K2
D3
BOOT0
VDD
R59
BAT60JFILM
77/101
JP9
150
Bootloader_BOOT0_3V3
D4
BAT60JFILM
Title: MCU2
Bootloader_RESET_3V3
Header 2X1
VDD
Project: STM32L476G-EVAL
Size: A3
Reference: MB1144
Date: 10/7/2016
Revision: C-02
Sheet: 4 of 25
Schematic diagrams
LCDSEG[18..20]
R96
[N/A]
PH0
R95
109.03290.01
2
3
PH1
C55
3
PH0
RESET#
2
RESET#
VDD
A[0..15]
4
A[0..15]
PG8
23
X2
8MHz (with socket)
D[0..15]
1
D[0..15]
10
LCD Glass Connector
VDD
R265
0
R266
0
LCD Glass Connector
R263
R264
1K2
1K2
DocID027351 Rev 5
PA9
PA8
PA10
PB9
PB11
PB10
PB5
PB14
PB13
PB12
PA15
PB8
PB15
PC2
PC1
PC0
PA3
PA2
PB0
PA7
PA6
PB4
PB3
PB1
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
USBOTG_VBUS
uSD_DETECT
USBOTG_ID
CAN_TX
uSD_CMD
NFC_MISO
USBOTG_PRDY
0
NFC_SCK
Comp2_OUT
R109
0
0
R144
0
R145
0
SmartCard_IO
uSD_D3
I2C2_SCL
R108
R143
uSD_CLK
I2C2_SDA
CN11
LCDCOM1
LCDCOM0
LCDCOM2
LCDCOM3
LCDSEG11
LCDSEG10
LCDSEG9
LCDSEG14
LCDSEG13
LCDSEG12
LCDSEG17
LCDSEG16
LCDSEG15
LCDSEG20
LCDSEG19
LCDSEG18
LCDSEG2
LCDSEG1
LCDSEG5
LCDSEG4
LCDSEG3
LCDSEG8
LCDSEG7
LCDSEG6
Schematic diagrams
78/101
Figure 36. LCD glass module daughterboard connectors
USBOTG_OVRCR
SWP_IO
CAN_RX
NFC_MOSI
DFSDM_CKOUT
LED3
DMIC_DATIN
R111
0
OpAmp1_OUT
Comp2_INP
CN14
LCDCOM7 PD2
LCDCOM6 PC12
LCDCOM5 PC11
LCDCOM4 PC10
LCDSEG21 PB7
LCDSEG22 PC4
LCDSEG23 PC5
LCDSEG24 PC6
LCDSEG25 PC7
LCDSEG26 PC
PC8
LCDSEG27 PC9
LCDSEG28 PD8
LCDSEG29 PD9
LCDSEG30 PD10
LCDSEG31 PD11
LCDSEG32 PD12
LCDSEG33 PD13
LCDSEG34 PD14
LCDSEG35 PD15
LCDSEG36 PE0
LCDSEG37 PE1
LCDSEG38 PE2
LCDSEG39 PE3
LCDSEG0 PA1
uSD_D2
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
R140
0
R141
0
R142
0
IDD_WAKEUP
USBOTG_PPWR
USART1/IrDA_RX_3V3
R146
0
D13
D14
D15
A16
R147
0
A18
D0
D1
R148
0
PT100_DATIN
uSD_D0
uSD_D1
FMC_NBL0
FMC_NBL1
R151
0
R149
0
A17
OpAmp1_INM
Header 24X2
Header 24X2
A23
R138
GND
100K
R107
0
SmartCard_CLK
R150
0
A19
R139
100K
D[0..15]
A[16..19]
A23
GND
D[0..15]
A[16..19]
A23
LCDSEG[0..39]
LCDCOM[0..7]
LCDSEG[0..39]
LCDCOM[0..7]
Project: STM32L476G-EVAL
Size: A3
Reference: MB1144
Date: 10/7/2016
Revision: C-02
Sheet: 5 of 25
UM1855
Title: LCD_Glass
UM1855
Figure 37. I/O expander
IOExpander1
VDD
R229
100K
I2C_SCL
I2C_SDA
IOExpander_INT
PG14
PG13
PG15
R228
C134
100nF
U32
DocID027351 Rev 5
6
14
10
4
5
2
7
3
0
VCC
Vio
GND
SCLK
SDAT
INT
Data in
A0/Data Out
YXY+
X+
IN3
IN2
IN1
IN0
1
16
15
13
12
11
9
8
IOExpander_YIOExpander_XIOExpander_Y+
IOExpander_X+
LED4
LED2
STMPE811QTR
I2C device address:0x82
R239
100K
IOExpander2
U33
1
2
3
4
5
6
7
8
JOY_SEL
JOY_DOWN
JOY_LEFT
JOY_RIGHT
JOY_UP
SmartCard_RST
SmartCard_CMDVCC
SmartCard_3/5V
19
20
VDD
C132
100nF
21
9
25
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
SCL
SDA
VCC
GND
TAB
STMPE1600QTR
INT
A2
A1
A0
10
11
12
13
14
15
16
17
SmartCard_OFF
BL_Control
EXT_RESET
22
R243
R232
R230
24
23
18
10K
10K
10K
R231 R233 R237
[N/A][N/A][N/A]
VDD
Default I2C Address:1000010X
79/101
Project: STM32L476G-EVAL
Size: A3
Reference: MB1144
Date: 10/7/2016
Revision: C-02
Sheet: 6 of 25
Schematic diagrams
Title: IO_Expandor
2
Z1
SMAJ5.0A-TR
2
DC-10B
C124
100nF
SV
CV
SG CG1
CG2
CG3
6
3
1
C100
220uF
4
5
6
C116
4.7uF
BNX002-01
VI
PG
EN
VO
R206
[N/A]
GND
1
GND
3
2
1
U28
ST1L05BPUR
+5V
E5V
L2
1
2
3
ADJ
TP17
+3V3
R202
3
+3V3
[N/A]
4
Power Supply 3.3V
Vout=1.22*(1+R1/R2)
R204
5
20.5K[1%]
7
U31
ZEN056V130A24LS
CN22
Schematic diagrams
80/101
Figure 38. Power supply
C101
100nF
C98
10uF[ESR<0.2ohm]
R203 11.8K[1%]
E5V
JP17
EN
72
108
144
39
17
52
62
84
121
106
VDD VDD_MCU
2
3
TP5
VDD
1
VDD_USB
95
131
2
3
6
JP1
VREF+
VREF-
VDDA
VSSA
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDUSB
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDDIO2
VDDIO2
VSS
VSS
31
R240
[N/A]
C133
100nF
C131
10uF[ESR<0.2ohm]
RV1
2
3386P-503H[5%]
94
130
U27
LD1117S18TR
+3V3
JP12
Vin
Vout
Tab
TP16
1V8
+1V8
2
4
TP12
3V6
U26
LD1117STR
+5V
3
Vin
C107
10uF
+3V6
Vout
Tab
2
4
R207
124[1%]
1
BT1
2
3
VDD_MCU
+
-
Header 2X1
CR1220 holder
Recommendation:
100nF decoupling capacitor for each VDD pin
to use a supercapacitor:
remove the jumper, and connect positive terminal
of the supercapacitor to pin 2 of the jumper.
VDD_MCU
VDD_IO
C51
100nF
C43
100nF
1uF
R209
232[1%]
C114
100nF
C99
10uF
Vout=1.25*(1+232/124)=3.589V
VDD_USB
C46
C32
1uF
20K[1%]
10.2K[1%]
3
VDD_IO
C45
100nF
R236
5
71
107
143
38
16
51
61
83
120
VDD
C42
100nF
[N/A]
4
R235
STM32L476ZGT6U
JP3
VO
ADJ
Power Supply VDD_ADJ [1.7V to 3.61V]
Vout=1.22*(1+R1/R2)
TP13
VDD_ADJ
VDD_ADJ
R234
3
30
VBAT
TP4
VDD_IO
PG
1
33
GND
1
C48
C41
C50
C38
100nF 100nF 100nF 100nF
VI
1
C59
1uF
TP2
VDD_USB
+3V3
C140
4.7uF
U7B
32
JP2
VDD_MCU
1
C60
100nF
GND
+3V3
6
VREF+
connected by shunt of
IDD_measurement circuitry
VDD_ADJ
U34
ST1L05BPUR
+5V
BEAD
JP10
TP3
3
2
TP18
VDDA
L1
3
TP11
2
2
+3V3
1
LD7
Red
1
1K
Header 4X2
TP8
VDDA
VDD_MCU
R165
GND
+5V
1
DocID027351 Rev 5
D5V
TP1
TP10
5V
7
5
3
1
GND
8
6
4
2
7
U5V
U5V_STLINK
C33
C35
100nF
1uF
C36
100nF
Project: STM32L476G-EVAL
Size: A3
Reference: MB1144
Date: 10/7/2016
Revision: C-02
Sheet: 7 of 25
UM1855
Title: Power
UM1855
Figure 39. Smartcard, SWP and NFC
+3V3
+3V3
R211
10K
R212
10K
R216
4K7
IOExpander1
U30
+5V
C136
C138
4.7uF
C135
100nF
C137
1
2
3
4
100nF 5
6
7
100nF 8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
CLKDIV1 AUX2UC
CLKDIV2 AUX1UC
5V/3V
I/OUC
PGND
XTAL2
C1+
XTAL1
Vddp
OFF
C1GND
Vup
Vdd
PRES
RSTIN
PRES
CMDVCC
I/O
PORADJ
AUX2
Vcc
AUX1
RST
CGND
CLK
TP14
TP15
R210
PC4
0
PB0
IOExpander1
C119
100nF
DocID027351 Rev 5
CN23
GND VCC
SWIO RST
I/O
CLK
NC
NC
C112
4.7uF
R241
100K
R213
100K
+3V3
R217
10K
R214
100K
100nF
5
6
7
8
SmartCard_CLK
SmartCard_OFF
+3V3
R218
10K
SmartCard Connector
PB12
SmartCard_IO
VDD
ST8024CDR
C117
SWP_IO
SmartCard_3/5V
AUX2
AUX1
1
2
3
4
R215
100K
IOExpander1
IOExpander1
SmartCard_RST
SmartCard_CMDVCC
Operating range: 2.72
Default setting: Open
JP4
3
R46
10K
100nF
CN5
DB9-male
1
6
2
7
3
8
4
9
5
U8
0
PB8
R76
0
1
2
3
4
D
GND
VCC
R
RS
CANH
CANL
Vref
8
7
6
5
SN65HVD230
JP6
Header 2X1
R55
120
D2
ESDCAN24-2BLY
Optional
2
CAN_RX
R75
1
CAN_TX
PB9
3
DocID027351 Rev 5
R45
2
C49
1
VDD
UM1855
Figure 47. CAN transceiver
R70
[N/A]
R77
0
Operating voltage range: 3.0
Source Exif Data:
File Type : PDF
File Type Extension : pdf
MIME Type : application/pdf
PDF Version : 1.3
Linearized : No
Tagged PDF : Yes
Page Layout : SinglePage
Page Mode : UseNone
Page Count : 101
Producer : Acrobat Distiller 9.0.0 (Windows); modified using iText 2.1.7 by 1T3XT
Keywords : Technical Literature, 027351, Product Development, Specification, User manual, STM32L476G-EVAL
Modify Date : 2016:11:22 21:32:46+01:00
Subject : -
Creator : C2 v4.2.0220 build 670 - c2_rendition_config : Techlit_Active
Revision : 5
Title : Evaluation board with STM32L476ZGT6 MCU
Alternate ID : 027351
Alternate Name : UM1855
Classification : Unclassified
Document Type : User manual
Author : STMICROELECTRONICS
Create Date : 2016:11:21 10:56:31Z
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