GS66508B EVBDB User Guide Rev 20160928 1

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This evaluation kit is designed for engineering evaluation in a controlled
lab environment and should be handled by qualified personnel ONLY.
High voltage will be exposed on the board during the test and even brief
contact during operation may result in severe injury or death.
Never leave the board operating unattended. After it is de-energized,
always wait until all capacitors are discharged before touching the board.

This product contains parts that are susceptible to damage by electrostatic
discharge (ESD). Always follow ESD prevention procedures when
handling the product.

The GS665XXX-EVBDB daughter board style evaluation kit consists of two GaN Systems 650V GaN
Enhancement-mode HEMTs (E-HEMTs) and all necessary circuits including half bridge gate drivers,
isolated power supplies and optional heatsink to form a functional half bridge power stage. It allows
users to easily evaluate the GaN E-HEMT performance in any half bridge-based topology, either with the
universal mother board (P/N: GS665MB-EVB) or users’ own system design.






Serves as a reference design and evaluation tool as well as deployment-ready solution for easy insystem evaluation.
Vertical mount style with height of 35mm, which fits in majority of 1U design and allows
evaluation of GaN E-HEMT in traditional through-hole type power supply board.
Current shunt position for switching characterization testing
Universal form factor and footprint for all products

The daughter board and universal mother board ordering part numbers are below:

Part Number
GS66502B-EVBDB
GS66504B-EVBDB
GS66508B-EVBDB
GS66508T-EVBDB
GS66516T-EVBDB
GS665MB-EVB

GaN E-HEMT P/N:
GS66502B
GS66504B
GS66508B
GS66508T
GS66516T

Description
GaN E-HEMT 650V/7.5A, 200mΩ
GaN E-HEMT 650V/15A, 100mΩ
GaN E-HEMT 650V/30A, 50mΩ
GaN E-HEMT top side cooled 650V/30A, 50mΩ
GaN E-HEMT top side cooled 650V/60A, 25mΩ
Universal 650V Mother Board

The daughter board GS665XXX-EVBDB circuit diagram is shown in Figure 1. The control logic inputs on
2x3 pin header J1 are listed below:

Pin
ENA
VCC
VDRV

PWMH
PWML
0V

Descriptipon
Enable input. It is internally pulled up to VCC, a low logic disables all the PWM gate
drive outputs.
+5V auxillary power supply input for logic circuit and gate driver. On the daughter
board there are 2 isolated 5V to 9V DC/DC power supplies for top and bottom switches.
Optional 9V gate drive power input. This pin allows users to supply separate gate drive
power supply. By default VDRV is connected to VCC on the daughter board via a 0 ohm
jumper FB1. If bootstrap mode is used for high side gate drive, connect VDRV to 9V
High side PWM logic input for top switch Q1. It is compatible wth 3.3V and 5V
Low side PWM logic input for bottom switch Q2. It is compatible wth 3.3V and 5V
Logic inputs and gate drive power supply ground return.

The 3 power pins are:
 VDC+: Input DC Bus voltage
 VSW: Switching node output
 VDC-: Input DC bus voltage ground return. Note that control ground 0V is isolated from VDC-.

VCC
ENABLE

Iso. DC/DC
or Bootstrap

PWMH
PWML

VDC+
Si8271 Iso.
Gate Driver

Iso. DC/DC
Si8271 Iso.
Gate Driver

VSW

JP1

C4-10

VDC-

A.
B.
C.
D.
E.
F.
G.
H.

2x GaN Systems 650V E-HEMT GS66508B, 30A/50mΩ
Decoupling capacitors C4-C11
Isolated gate driver Silab Si8271GB-IS
Optional current shunt position JP1.
Test points for bottom Q2 VGS.
Recommended probing positions for Q2 VDS.
Optional bootstrap circuit D1/R1 (unpopulated).
5V-9V isolated DC/DC gate drive power supply



This daughter board includes two GaN Systems E-HEMT GS66508B (650V/30A, 50mΩ) in a
GaNPx™ B type package. The large S pad serves as source connection and thermal pad. The pin
4 is the kelvin source connection for gate drive return.



Silab Si8271GB-IS isolated gate driver is chosen for this design. This driver is compatible with 6V
gate drive with 4V UVLO and has CMTI dv/dt rating up to 200V/ns. It has separated source and
sink drive outputs which eliminates the need for additional diode.
GaN E-HEMT switching speed and slew rate can be directly controlled by the gate resistor. By
default the turn-on Rgate (R6/R12) is 10Ω and Rg_off (R7/R14) is 1Ω. User can adjust the values
of gate resistors to fine tune the turn-on and off speed.
FB1/FB2 are footprints for optional ferrite bead. By default they are populated with 0Ω jumpers.
If gate oscillation is observed, it is recommended to replace them with ferrite bead with Z=1020Ω@100MHz.



VDDH_+6V
U2
10R
VCC_+5V

PWMH

1
2
3

C13
1uF

ENABLE 4

VDD

VDDI

VO+

GNDI
EN

VOGNDA

C12

8
7
6

1uF

Q1_VO+

1
R6
10R

Q1_VO-

FB2
Q1_GOUT
0R

Q1G 2

GS66508B

R8
3.3K

PWMH_INR5

SI8271GB-IS
0V
GNDH






5V-9V isolated DC/DC converters are used for gate drive. 9V output is then regulated down to
6V for gate driver.
By default gate drive supply input VDRV is tied to VCC +5V via 0Ω jumper (FB1). Remove FB1 if
separate gate drive input voltage is to be used.

The board has option for users to experiment with non-isolated bootstrap circuit with following
circuit changes:
o Remove PS2 and short circuit pin 2 to 5 and pin 1 to 4.
o Populate D1/ R1 (not supplied): D1 is the high voltage bootstrap diode (for example ES1J)
and use 1-2Ω 0805 SMD resistor on R1. Depopulate PS1, LED1 and replace C2 with 1uF
capacitor.
o Remove 0Ω jumper at FB1 and supply +9V at VDRV.

D1
R1
0R
R0805

VIN

+VO

PES1-S5-S9-M
GND

LED1

LED-0603

4
R3
3.3K

C1
4.7uF
C0805

VDDH_+9V

PS1

OUT
LP2985IM5-6.1
ON/OFF
BY P

GND

DNP

VDRV

VDDH_+6V

DNP

C2
4.7uF
C0805

5
4

C3
4.7uF
C0805

600V 1A
DO-214AC

R4
3.3K

GNDH
GNDH
VCC_+5V

FB1

VDDL_+9V
VDRV

PS2

PES1-S5-S9-M
GND

LED2

LED-0603

OUT
LP2985IM5-6.1
ON/OFF
BY P

+VO

VIN

2
C14
4.7uF
C0805

VDDL_+6V

GND

VDRV

4
R9
3.3K

R10
3.3K

C16
4.7uF
C0805

5
4

C15
4.7uF
C0805
GNDL

GNDL






The board provides an optional current shunt position JP1 between the source of Q2 and power
ground return. This allows drain current measurement for switching characterization test such as
Eon/Eoff measurement.
The JP1 footprint is compatible with T&M Research SDN series coaxial current shunt
(recommended P/N: SDN-414-10, 2GHz B/W, 0.1Ω)
If current shunt is not used JP1 must be shorted. JP1 affects the power loop inductance and its
inductance should be kept as low as possible. Use a copper foil or jumper with low inductance.

2.
3.

When measuring VSW with current shunt, ensure all channel probe grounds and current shunt
BNC output case are all referenced to the source end of Q2 before the current shunt. The
recommended setup of probes is shown as below.
The output of coaxial current shunt can be connected to oscilloscope via 50Ω termination
impedance to reduce the ringing.
The measured current is inverted and can be scaled by using: Id=Vid/Rsense.

VSW
VGS

VGL

VDS

BNC case
VSL
ID

To oscilloscope
probe input (use
50Ω termination)

BNC tip

1.
2.

GS66508B has a thermal pad at the bottom side for heat dissipation. The heat is transferred to the
bottom side of PCB using thermal vias and copper plane.
A heatsink (35x35mm size) can be attached to the bottom side of board for optimum cooling.
Thermal Interface Material (TIM) is needed to provide electrical insulation and conformance to

4.
5.
6.

the PCB surface. The daughter board evaluation kit supplies with a sample 35x35mm fin heatsink
(not installed), although other heatsinks can also be used to fit users’ system design.
A thermal tape type TIM (Berguist® Bond-Ply 100) is chosen for its easy assembly. The supplied
heatsink has the thermal tape pre-applied so simply peel off the protective film and attach the
heatsink to the back of board as marked in Figure 3.
Two optional mounting holes as shown in Figure 9 are provided for mounting customized
heatsink using screws.
Using the supplied heatsink and TIM, the overall junction to ambient thermal resistance RthJ-A is
~9°C/W with 500LFM airflow.
Forced air cooling is recommended for power testing.

12V INPUT

(+)

Airflow direction
5V Power Supply

VDCCIN
For Ext.
12VDC Fan

Daughter Board
VDC+

Probing point for VSW
VSW

PWM control & dead
time circuit

VDC-

Optional Cout

VOUT

GaN Systems provides a universal 650V mother board (ordering part number: GS665MB-EVB, sold
separately) that can be used as the basic evaluation platform for all the daughter boards.
The universal 650V mother board evaluation kit includes following items:
1. Mother board GS665MB-EVB
2. 12VDC Fan

The board can be powered by 9-12V on J1. On-board voltage regulator creates to 5V for daughter board
and control logic circuits. J3 is used for external 12VDC fan.

+5V
C9

J7
112538

TP7
R1

D1 PMEG2005EB

U2B
4

6
74VHC132

D2 PMEG2005EB

TP8

49R9
74VHC132

1K00
2K
TR1

SOD523
R6

SOD523
R5

5
4
3
2

DNP

R2
100R
R1206

DNP

1uF

49R9
R4
100R
R1206

U2A

0.1uF
C10

C11
100pF

DNP

1K00
TR2

U2C

DNP

C12
100pF

0V U2D
12

9
8
10

11
13

74VHC132

PWM
OUTPUT

R7
49R9

74VHC132

INVERTED
PWM OUTPUT

The top and bottom switches PWM inputs can be individually controlled by two jumpers J4 and J6. Users
can choose between a pair of complementary on-board internal PWM signals (non-inverted and inverted,
controlled by J7 input) with dead time or external high/low side drive signals from J5 (users’ own control
board).
An on-board dead time generation circuit is included on the mother board. Dead time is controlled by
two RC delay circuits, R6/C12 and R5/C11. The default dead time is set to about 100ns. Additionally two
potentiometers locations are provided (TR1/TR2, not included) to allow fine adjustment of the dead time
if needed.

Test points are designed in groups/pairs to facilitate probing:
Test points
TP1/TP2
TP7/TP8
TP4/TP3/TP13
TP9/TP10
TP11/TP12
TP6/TP5

Name
+5V/0V
PWMIN/0V
PWMH/PWML/0V
VDC+/VDCVOUT/VDCVSW/VDC-

Description
5V bias power
PWM input signal from J7
High/low side gate signals to daughter board
DC bus voltage
Output voltage
Switching node output voltage (for HV oscilloscope
probe)

CON1-CON7 mounting pads are designed to be compatible with following mounting terminals:
 #10-32 Screw mount,
 Banana Jack PCB mount (Keystone P/N: 575-4), or
 PC Mount Screw Terminal (Keystone P/N: 8191)

An external power inductor (not included) can be connected between VSW (CON1) and VOUT (CON4/5)
or VDC+ (CON2/3) for double pulse test. Users can choose their inductor size to meet the test
requirement. Generally it is recommended to use power inductor with low inter-winding capacitance to
obtain best switching performance. For the double pulse testing we use 2x 60uH/40Amp inductor (CWS,
P/N: HF467-600M-40AV) in series. C14 is designed to accommodate a film capacitor as output filter.

VDC+

CON3

CON2

LOUT

PWM +5V
INPUT
(J7)
0V
+6V

IL
400V DC

VDS

VGL

VSW
CON4 CON5

CON1

VGL

0V
VDS
ISW

CON6

CON7

VDC-

IL
TON1

t1 t2 t3

Double pulse test allows easy evaluation of device switching performance at high voltage/current
without the need of actually running at high power. It can also be used for switching loss (Eon/Eoff)
measurement and other switching characterization parameter test.
The circuit configuration and operating principle can be found in Figure 13:
1. The output inductor is connected to the VDC+.
2. At t0 when Q2 is switched on, the inductor current starts to ramp up until t1. The period of first
pulse Ton1 defines the switching current ISW = (VDS*TON1) / L.
3. t1-t2 is the free wheeling period when the inductor current IL forces Q1 to conduct in reverse.
4. t1 (turn-off) and t2 (turn-on) are of interest for this test as they are the hard switching trasients for
the half bridge circuit when Q2 is under high switching stress.
5. The second pulse t2-t3 is kept short to limit the peak inductor current at t3.
The double pulse signal can be generated using programmable signal generaotor or microcontroller/DSP
board. As this test involves high switching stress and high current, it is recommended to set the double
pulse test gate signal as single trigger mode or use long repetition period (for example >50-100ms) to void
excess stress to the switches. Q1 can be kept off during the test or driven synchronously (J4 set to OFF or
INT_INV) and Q2 is set to INT (or EXT position if PWM signal is from J5).

This is standard half bridge configuration that can be used in
following circuits :
 Synchronous Buck DC/DC
 Single phase half bridge inverter
 ZVS half bridge LLC
 Phase leg for full bridge DC/DC or
 Phase leg for a 3-phase motor drive
Jumper setting:
 J4 (Q1): INT
 J6 (Q2): INT_INV

CON3

VDC+
CON2

LOUT

CON5

400V DC

CON4

VSW
CON1
Q2

COUT

RLoad

CON6

VDCCON7

VDC+
CON3

CON2

LIN
Q1

CON5 VIN
CON4

VSW
CON1
Q2

INPUT
CON6

VDC-

CON7

When the output becomes the input and the load is
attached between VDC+ and VDC-, the board is
converted into a boost mode circuit and can be used for:
 Synchronous Boost DC/DC
 Totem pole bridgeless PFC
Jumper setting:
 J4 (Q1): INT_INV
 J6 (Q2): INT

The daughter board allows users to easily evaluate the GaN performance in their own systems. Refer to
the footprint drawing of GS665XXX-EVBDB as shown below:

1 3 5

2 4 6

1. All units are in mm.
2. Pin 1-6: Dia. 1mm
3. Pin 7-9: 1.91mm (75mil) mounting hole for Mill-max Receptacle P/N: 0312-0-15-15-34-27-10-0.

Follow the instructions below to quickly get started with your evaluation of GaN E-HEMT. Equipment
and components you will need:
 Four-channel oscilloscope with 500MHz bandwidth or higher
 high bandwidth (500MHz or higher) passive probe
 high bandwidth (500MHz) high voltage probe (>600V)
 AC/DC current probe for inductor current measurement
 12V DC power supply
 Signal generator capable of creating testing pulses
 High voltage power supply (0-400VDC) with current limit.
 External power inductor (recommend toroid inductor 50-200uH)
1.
2.
3.

Check the JP1 on daughter board GS665XXX-EVBDB. Use a copper foil and solder to short JP1.
Install GS665XXX-EVBDB on the mother board. Press all the way down until you feel a click. Connect
probe between VGL and VSL for gate voltage measurement.
Set up the mother board:
a. Connect 12VDC bias supply to J1.
b. Connect PWM input gate signal (0-5V) to J7. If it is generated from a signal generator ensure
the output mode is high-Z mode.
c. Set J4 to OFF position and J7 to INT.
d. Set High voltage (HV) DC supply voltage to 0V and ensure the output is OFF. Connect HV
supply to CON2 and CON6.
e. Use HV probe between TP6 and TP5 for Vds measurement.
f. Connect external inductor between CON1 and CON3. Use current probe to measure inductor
current IL.
Set up and check PWM gate signal:
a. Turn-on 12VDC power.
b. Check the 2 LEDs on the daughter board. They should be turned on indicating the isolated
9V is present.
c. Set up signal generator to create the waveforms as shown in Figure 13. Use equation ISW =
(VDS*TON1) / L to calculate the pulse width of the first pulse and ensure the Isw_max is ≤30A at
400VDC.
d. Set the operation mode to either single trigger or Burst mode with repetition period of 100ms.
e. Turn on the PWM output and check on the oscilloscope to make sure the VGL waveform is
present and matches the PWM input.
Power-on:
a. Turn on the output of the HV supply. Start with low voltage and slowly ramp the voltage up
until it reaches 400VDC. During the ramping period closely observe the the voltage and
current waveforms on the oscilloscope.
Power-off:
a. After the test is complete, slowly ramp down the HV supply voltage to 0V and turn off the
output. Then turn off the 12V bias supply and signal generator output.

Figure 16 shows the hard switching on waveforms at 400V/30A. A Vds dip can be seen due to the rising
drain current (di/dt in the power loop ΔV=Lpxdi/dt, where Lp is the total power loop inductance). After
the drain current reaches the inductor current, the Vds starts to fall. The Vgs undershoot spike is caused
by the miller feedback via Cgd under negative dv/dt.
Due to the low gate charge and small RG(OFF) , GaN E-HEMT gate has limited control on the turn-off
dv/dt. Instead the Vds rise time is determined by how fast the turn-off current charges switching node
capacitance (Coss).
The low Coss of GaN E-HEMT and low parasitic inductance of GaNPX™ package together with
optimized PCB alyout, enables a fast and clean turn-off Vds waveform with only 50V the turn-off Vds
overshoot at dv/dt > 100V/ns. The measured rise time is 3.9ns at 400V and 30A hard turn-off。

A T&M search coaxial current shunt (SDN-414-10, 0.1Ω) is installed for switching loss measurement as
shown below.

The switching energy can be calculated from the measured switching waveform Psw = Vds*Id. The
integral of the Psw during switching period is the measured switching loss. The channel deskewing is
critical for measurement accurary. It is recommended to manually deskew Id against Vds as shown in
Figure 20. The drain current spike is caused by charging the high side switch Coss (Qoss loss).

The switching loss measurements with drain current from 0 to 30A can be found in Figure 22. The turnon loss dominates the overall hard switching loss. Eon at 0A is the Qoss loss caused by the Coss at high
side switch.
The turn-off loss remain almost constant from 0A up to 20A about 8uJ. the measured Eoff matches well
with the Eoss @400V, which indicates that turn-off energy is dominated by Eoss, the energy required to
charge Coss from 0V to bus voltage. This energy is not part of loss at turn-off, but actually part of turn-on
loss at next hard switching turn-on period. This means that with the fast turn-off speed the GaN E-HEMT
can achieve near zero turn-off switching loss.

The board is converted to a synchronous buck DC/DC converter and demonstrates efficiency 99% at
1.5kW. With forced air cooling, the peak device temperature TJ_MAX was measured at 80°C at 1kW output.

1
3
5

0V
VCC_+5V
VDRV

VDRV

ENABLE
PWMH_IN
PWML_IN

2
4
6

GNDL

GNDH

GNDL

GNDH

TPSMD-1mm-cir
TP8

TP7

TPTH-1MM

TPTH-1MM
TP6

TPTH-1MM
TP4

TPTH-1MM
TP2

TP1

Q2S

TPTH-1MM

TPTH-1MM
TP5

TP3

TPSMD-1mm-cir

TPSMD-1mm-cir
TP10

TPSMD-1mm-cir
VDDL_+6V TP9

VDDH_+6V

Q2G

Q1G

PROBE TEST POINT

1
2
3
4
5
6

R2
3.3K
ENABLE
PWMH_IN
PWML_IN

VCC_+5V

VCC_+5V
C18
1uF

10R

GND

+VO

GNDA

VO-

VO+

GND

VO-

VO+

VDD

GNDA

SI8271GB-IS

GNDI

VDDI

PES1-S5-S9-M

VIN

PS2

VDD

SI8271GB-IS

GNDI

VDDI

VCC_+5V

ENABLE 4

PWML

C14
4.7uF
C0805

FB1

+VO

DNP

0R
R0805

PES1-S5-S9-M

VIN

PS1

ENABLE 4

VDRV

R11

PWMH

VDRV

C13
1uF

10R

PWML_IN

VCC_+5V

PWMH_INR5

C1
4.7uF
C0805

VDRV

DNP

600V 1A
DO-214AC

INPUT CONNECTORS

GNDH

Q2_VO-

C16
4.7uF
C0805

1uF

C17

VDDL_+6V

R10
3.3K

GNDL

Q2_VO+

R9
3.3K

LED-0603

LED2

1uF

C12

VDDH_+6V

R4
3.3K

VDDL_+9V

Q1_VO-

6
5

Q1_VO+

R3
3.3K

3
C2
4.7uF
C0805

LED1
LED-0603

VDDH_+9V

R14

10R

R12
Q2_GOUT

GNDL

FB2

FB3

Q1_GOUT

GNDH

OUT
LP2985IM5-6.1
BY P
ON/OFF

10R

OUT
LP2985IM5-6.1
BY P
ON/OFF

U1
IN
GND

2
GND

R13
3.3K

Q2G 2

GNDL

C15
4.7uF
C0805

VDDL_+6V

R8
3.3K

Q1G 2

GNDH

C3
4.7uF
C0805

VDDH_+6V

JP1
CON-JMP-CSHUNT

Q2S

GS66508B

PGND

VIN+

VIN-

C10

PGND

CON-EDGE-MNT-3260

CON3

VDC-

CON-EDGE-MNT-3260

CON2

VSW

C11
0.1uF 1kV
C1812

CON1

VDC+

Top Layer

Mid Layer 1

Mid Layer 2

Bottom Layer

TMK107B7105KA-T
ES1J

M20-9950345

FAIRCHILD
generic 1% 100ppm 0603

HARWIN INC.

600V 1A
0R

CON-JMP-CSHUNT
CON-HDR-2X3

DIODE ULTRAFAST 600V 1A SMA
0R JUMPER 0603

CURRENT SHUNT JUMPER
CONN 3PIN DUAL ROW, 0.1" PITCH, R/A

1 D1

3 FB1,FB2,FB3

1 JP1

1 J1

1 J2

LP2985IM5-6.1

REG LDO 6V, 100mA, STO23-5

2 U1,U3

2 U2,U4

3-141410UBLAN

BOND PLY 100

Cool Innovation

bergquist

heatsink, 35x35mmx25.4mm, black anodized

Thermal sheet cut to 35x35mm square

Bondply 100 thermal adhesive
tape cut to 35x35mm and apply to
heatsink surface (item #21)

CON-TP-1POS

Probe test point

4 TP7,TP8,TP9,TP10

DO NOT install on the PCB
assembly, supply loose with preapplied Thermal sheet (item #22)

CON-TP-1POS

6 TP1,TP2,TP3,TP4,TP5,TP6Probe test point

SI8271GB-IS

RES, 1R, 1%,1/10W, 0603

2 R7,R14

SILICON LABS

generic 1% 100ppm 0603

10R

RES, 10R, 1%,1/10W, 0603

4 R5,R6,R11,R12

IC ISO GATE DRIVER 2.5KV HIGH CMTI SI8271GB-IS

generic 1% 100ppm 0603

3.3K

7 R2,R3,R4,R8,R9,R10,R13 RES, 3.3K, 1%,1/10W, 0603

Off the board components:

DO NOT INSTALL

generic 1% 100ppm 0603

RES,0 R, 1%, 0805

1 R1

LP2985IM5-6.1/NOPB

GS66508B

GaN Systems

GS66508B

GaN E-HEMT 650V/30A

2 Q1,Q2

TEXAS INSTRUMENTS

DO NOT INSTALL

PES1-S5-S9-M

cui

PES1-S5-S9-M

ISO. DC/DC 5-9V, 1W

2 PS1,PS2

For bootstrap mode, DO NOT
INSTALL

ltst-c191kgkt

liteon

LED-SMD-0603

LED, GREEN, SMD 0603

2 LED1,LED2

DO NOT INSTALL

For current measurement, footprint
compatible with T&M SDN-414-010
current shunt. Use wide copper foil to
short the connection if not used for
better

For bootstrap mode, DO NOT
INSTALL

mating receptacle on mother
board:0312-0-15-15-34-27-10-0

Assembly Note

CON-6POS

C1812C104KDRAC7800

TAIYO YUDEN

1uF

CAP, CER, 1UF, 25V, +/-10%, X7R, 0603

4 C12,C13,C17,C18

TMK212AB7475KG-T

KEMET

TAIYO YUDEN

CAP, CER, 0.1UF,1KV, +/-10%, X7R, 1812
8 C4,C5,C6,C7,C8,C9,C10,C11

3620-2-32-15-00-00-08-0

Part number

0.1uF 1kV

CAP, CER, 4.7UF, 25V, +/-10%, X7R, 0603 4.7uF

6 C1,C2,C3,C14,C15,C16

Manufacturer

CON-EDGE-MNT-3260Mill-Max

CONN PC PIN EDGE MNT

3 CON1,CON2,CON3

Value

PCB bare 4-layer 2oz Cu.

Description

1 PCB

Quantity Reference

GS66508B HALF BRIDGE DAUGHTER CARD 2016-06-10
BOARD NAME: GS66508B-EVBDB
B1
Revision
20160624
Last Update

J7
112538

DNP

R4
100R
R1206

DNP

1
2

TP8

TP7

U2A

TO 12V FAN

49R9
R2
100R
R1206

VAUX_RTN

C1
220uF 25V
CAPAL-PANA-F

+5V

74VHC132

1uF
3

0.1uF
C10

MC7805
IN
OUT

DNP

1K00
TR2

SOD523
R6

+5V

1
3
5
7

2
4
6
8

TP1

C4 +5V VCC
10u
TP2
C0805

+5V

C12
100pF
10

74VHC132

U2C

DNP

1K00
2K
TR1

SOD523
R5

D1 PMEG2005EB

C11
100pF

74VHC132

13
74VHC132

0V U2D
12

U2B

EXTERNAL PWM INPUT
TO DSP/MCU CONTROL BOARD

+12V

D2 PMEG2005EB

C3
10u
C0805

+12V

2. DO NOT INSTALL TR1,TR2,R2,R3 AND C14

1. ALL SMD RESISTORS AND CAPACITORS ARE 0603 SIZE
M2

49R9

KEYSTONE 8839-8834

TP13

TP5

TP3

VSW

TP6

CON2

CON3

VDC-

C13
10uF 700V

CON6

VDC_N

TP-KEY STONE-5010

TP10

TP-KEY STONE-5010

TP9
VDC+

VDC_P

POS 4: OFF

CON4

CON1

DNP

C14
10uF 700V

VOUT

C8
0.1uF 1kV
C1812
VDC+
VSW

VDC-

ENABLE
PWMH_IN
PWNL_IN

1
3
5

2
4
6

+5V

CON5

J10

VDRV

TP12
TP-KEY STONE-5010

TP11
TP-KEY STONE-5010

FOOTPRINT FOR GS665XX-EVBDB

C5 C6 C7

POS 2/3: INTERNAL PWM SIGNAL

POS 1: EXT. PWM SIGNAL

INVERTED
PWM OUTPUT

PWM
OUTPUT

TP4

PWM INPUT SELECTION

0V
PWM_EXT_L
PWM_INT
PWM_INT_INV

PWM_EXT_H
PWM_INT
PWM_INT_INV

PCB STANDOFF 4.75MM MNT HOLE

USE TR1 AND TR2 TO ADJUST DEAD TIME

ON BOARD DEAD TIME GENERATION CIRCUIT

CMC-08

C2
1uF 25V

NOTES - UNLESS OTHERWISE SPECIFIED

VAUX 12V IN

5
4
3
2

VAUX

14
7

3
2

4
1

GND

1
1

CON7

Assembly Top

Assembly Bottom

CONN RECEPT PIN .032-.046" .075"

2 C3,C4

4 C5,C6,C7,C8

1 C9

2 C11,C12

1 C13,C14

2 D1,D2
1 J1
1 J1-PLUG

1 J2

1 J3

2 J4,J6

1 J5
1 J7

3 J8,J9,J10

3 R1,R3,R7

9
10
11

15
16

1 U1

1 U2

generic 1% smd 0603

CONN HEADER 8POS DUAL VERT PCB

CONN RCPT 6POS .100 DBL STR PCB

DIODE SCHOTTKY 20V 500MA SOD523
TERM BLOCK HDR 2POS R/A 5.08MM
TERM BLOCK BLUG 2POS 5.08MM

74VHC132

MC7805

CMC-08

TP-KEYSTONE-5010
2K

100R
1K00

49R9

CON-RCPT-EDGEMNT

CON-HDR-4X2
112538

CON-JMP-4POS

CON-2POS

CON-RCPT-2X3-BOT

PMEG2005EB
CON-TERM-BLK-2POS-RA

FAIRCHILD

ON SEMI

KEYSTONE
RECOM

VISHAY DALE

MILLMAX

AMPHENOL
AMPHENOL

HARWIN

NXP
TE CONNECTIVITY
TE CONNECTIVITY

KEMET

TAIYO YUDEN

KEMET

TAIYO YUDEN

Panasonic

KEYSTONE

Manufacturer

FAN AXIAL 38X20MM 12VDC WIRE
JUMPER SHUNT GENERIC

6 M1,M2,M3,M4,M5,M6

1 FAN

2 JUMPER

TE CONNECTIVITY

SUNON FANS

PCB STANDOFF NYLON STACKABLE 4.75MM
MECH-STDOFF-KEYSTONE-8830
HOLE
KEYSTONE

1 IC GATE NAND 4CH 2-INP 14-SOIC

IC REG LDO 5V 1A DPAK

COMM MODE CHOKE 5.2A T/H

Off the board components:

1 T1

0.1uF

0.1uF 1kV

10uF

1uF

220uF 25V

CON-10-32-SCRWMNT

Value

GENERIC 100PF/25V 5% NP0 SMD 0603
100pF
CAP FILM 10UF/600VDC 5%, 27.5MM LEAD
SPACING
10uF 700V

GENERIC 0.1UF/25V, 10% X7R SMD 0603

GENERIC 0.1uF/1000V, SMD 1812

GENERIC 10UF/25V, 10% SMD 0805

GENERIC 1UF/25V, 10% X7R SMD 0603

2 R2,R4
generic 1% smd 1206
2 R5,R6
generic 1% snd 0603
TP1,TP2,TP3,TP4,TP7,TP8,
11 TP9,TP10,TP11,TP12,TP13 TEST POINT PCB
2 TR1,TR2

21
22

19
20

CONN 8-POS, DUAL ROW 2.54MM
CONN BNC JACK STR 50 OHM PCB

1 C2,C10

CAP ALUM 220UF 20% 25V SMD

1 C1

Description

Reference

1 PCB
PCB bare 2-layer 2oz Cu.
CON1,CON2,CON3,CON4,C
7 ON5,CON6,CON7
TERMINAL SCREW VERTICAL PC MNT

Quantity

GAN SYSTEMS 650V GAN UNIVERSAL MOTHER BOATRD
BOARD P/N:
GS665EVBMB
Revision
B1
6/30/2016
Last Update

DO NOT INSTALL

MATING SOCKET FOR MILLMAX
EDGE MNT PIN

MOUNT FROM BOTTOM SIDE
CONNECTOR FOR 12V FAN, DO NOT
INSTALL

DO NOT INSTALL C14

DO NOT INSTALL

Assembly Note

PCB SPACER, INSTALL FROM
8833 BOTTOM SIDE
SUPPLY LOOSE, DO NOT INSTALL
PMD1238PKB1-A.(2).GN
ON THE ASSEMBLY
INSTALL ON J4 "INT" POSITION AND
J6 "INT_INV" POSITION
382811-8

74VHC132MX

MC7805BDTRKG

5010
CMC-08

CRCW06031K00FKEA

CRCW060349R9FKEA

0312-0-15-15-34-27-10-0

75869-132LF
112538

M20-9980445

M20-7850342

PMEG2005EB,115
796638-2
796634-2

C4AEHBU5100A11J

C0603C101J3GACTU

TMJ107BB7104KAHT

C1812C104KDRAC7800

TMK212BBJ106KG-T

TMK107B7105KA-T

EEE-FK1E221P

8191

Part number

GaN Systems Inc. (GaN Systems) provides the enclosed product(s) under the following AS IS conditions:
This evaluation board/kit being sold or provided by GaN Systems is intended for use for ENGINEERING
DEVELOPMENT, DEMONSTRATION, and OR EVALUATION PURPOSES ONLY and is not considered by GaN
Systems to be a finished end-product fit for general consumer use. As such, the goods being sold or provided are
not intended to be complete in terms of required design-, marketing-, and/or manufacturing-related protective
considerations, including but not limited to product safety and environmental measures typically found in end
products that incorporate such semiconductor components or circuit boards. This evaluation board/kit does not fall
within the scope of the European Union directives regarding electromagnetic compatibility, restricted substances
(RoHS), recycling (WEEE), FCC, CE or UL, and therefore may not meet the technical requirements of these directives,
or other related regulations.
If this evaluation board/kit does not meet the specifications indicated in the User’s Guide, the board/kit may be
returned within 30 days from the date of delivery for a full refund. THE FOREGOING WARRANTY IS THE
EXCLUSIVE WARRANTY MADE BY THE SELLER TO BUYER AND IS IN LIEU OF ALL OTHER WARRANTIES,
EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING ANY WARRANTY OF MERCHANTABILITY OR FITNESS
FOR ANY PARTICULAR PURPOSE. EXCEPT TO THE EXTENT OF THIS INDEMNITY, NEITHER PARTY SHALL
BE LIABLE TO THE OTHER FOR ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES.
The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user
indemnifies GaN Systems from all claims arising from the handling or use of the goods. Due to the open construction
of the product, it is the user’s responsibility to take any and all appropriate precautions with regard to electrostatic
discharge.
No License is granted under any patent right or other intellectual property right of GaN Systems whatsoever. GaN
Systems assumes no liability for applications assistance, customer product design, software performance, or
infringement of patents or any other intellectual property rights of any kind.
GaN Systems currently services a variety of customers for products around the world, and therefore this
transaction is not exclusive.
Please read the User’s Guide and, specifically, the Warnings and Restrictions notice in the User’s Guide prior to
handling the product. Persons handling the product(s) must have electronics training and observe good
engineering practice standards.
This notice contains important safety information about temperatures and voltages. For further safety concerns,
please contact a GaN Systems’ application engineer.

Source Exif Data:

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PDF Version                     : 1.5
Linearized                      : No
Page Count                      : 32
Language                        : en-US
Tagged PDF                      : Yes
Producer                        : Microsoft® Word 2013
Creator                         : Microsoft® Word 2013
Create Date                     : 2016:09:28 14:50:31-04:00
Modify Date                     : 2016:09:28 14:50:31-04:00

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GS66508B EVBDB User Guide Rev 20160928 1

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