STM32F100xx Advanced ARM® Based 32 Bit MCUs Reference Manual STM32F100
!F100%20Reference%20manual
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- 1 Documentation conventions
- 2 Memory and bus architecture
- 3 CRC calculation unit
- 4 Power control (PWR)
- 5 Backup registers (BKP)
- 6 Reset and clock control (RCC)
- 6.1 Reset
- 6.2 Clocks
- Figure 8. STM32F100xx clock tree (low and medium-density devices)
- Figure 9. STM32F100xx clock tree (high-density devices)
- 6.2.1 HSE clock
- 6.2.2 HSI clock
- 6.2.3 PLL
- 6.2.4 LSE clock
- 6.2.5 LSI clock
- 6.2.6 System clock (SYSCLK) selection
- 6.2.7 Clock security system (CSS)
- 6.2.8 RTC clock
- 6.2.9 Watchdog clock
- 6.2.10 Clock-out capability
- 6.3 RCC registers
- 6.3.1 Clock control register (RCC_CR)
- 6.3.2 Clock configuration register (RCC_CFGR)
- 6.3.3 Clock interrupt register (RCC_CIR)
- 6.3.4 APB2 peripheral reset register (RCC_APB2RSTR)
- 6.3.5 APB1 peripheral reset register (RCC_APB1RSTR)
- 6.3.6 AHB peripheral clock enable register (RCC_AHBENR)
- 6.3.7 APB2 peripheral clock enable register (RCC_APB2ENR)
- 6.3.8 APB1 peripheral clock enable register (RCC_APB1ENR)
- 6.3.9 Backup domain control register (RCC_BDCR)
- 6.3.10 Control/status register (RCC_CSR)
- 6.3.11 Clock configuration register2 (RCC_CFGR2)
- 6.3.12 RCC register map
- 7 General-purpose and alternate-function I/Os (GPIOs and AFIOs)
- 7.1 GPIO functional description
- Figure 11. Basic structure of a standard I/O port bit
- Figure 12. Basic structure of a five-volt tolerant I/O port bit
- Table 16. Port bit configuration table
- Table 17. Output MODE bits
- 7.1.1 General-purpose I/O (GPIO)
- 7.1.2 Atomic bit set or reset
- 7.1.3 External interrupt/wakeup lines
- 7.1.4 Alternate functions (AF)
- 7.1.5 Software remapping of I/O alternate functions
- 7.1.6 GPIO locking mechanism
- 7.1.7 Input configuration
- 7.1.8 Output configuration
- 7.1.9 Alternate function configuration
- 7.1.10 Analog configuration
- 7.1.11 GPIO configurations for device peripherals
- 7.2 GPIO registers
- 7.2.1 Port configuration register low (GPIOx_CRL) (x=A..G)
- 7.2.2 Port configuration register high (GPIOx_CRH) (x=A..G)
- 7.2.3 Port input data register (GPIOx_IDR) (x=A..G)
- 7.2.4 Port output data register (GPIOx_ODR) (x=A..G)
- 7.2.5 Port bit set/reset register (GPIOx_BSRR) (x=A..G)
- 7.2.6 Port bit reset register (GPIOx_BRR) (x=A..G)
- 7.2.7 Port configuration lock register (GPIOx_LCKR) (x=A..G)
- 7.3 Alternate function I/O and debug configuration (AFIO)
- 7.3.1 Using OSC32_IN/OSC32_OUT pins as GPIO ports PC14/PC15
- 7.3.2 Using OSC_IN/OSC_OUT pins as GPIO ports PD0/PD1
- 7.3.3 JTAG/SWD alternate function remapping
- 7.3.4 Timer alternate function remapping
- Table 30. TIM5 alternate function remapping
- Table 31. TIM12 remapping
- Table 32. TIM13 remapping
- Table 33. TIM14 remapping
- Table 34. TIM4 alternate function remapping
- Table 35. TIM3 alternate function remapping
- Table 36. TIM2 alternate function remapping
- Table 37. TIM1 alternate function remapping
- Table 38. TIM1 DMA remapping
- Table 39. TIM15 remapping
- Table 40. TIM16 remapping
- Table 41. TIM17 remapping
- 7.3.5 USART alternate function remapping
- 7.3.6 I2C1 alternate function remapping
- 7.3.7 SPI1 alternate function remapping
- 7.3.8 CEC remap
- 7.4 AFIO registers
- 7.4.1 Event control register (AFIO_EVCR)
- 7.4.2 AF remap and debug I/O configuration register (AFIO_MAPR)
- 7.4.3 External interrupt configuration register 1 (AFIO_EXTICR1)
- 7.4.4 External interrupt configuration register 2 (AFIO_EXTICR2)
- 7.4.5 External interrupt configuration register 3 (AFIO_EXTICR3)
- 7.4.6 External interrupt configuration register 4 (AFIO_EXTICR4)
- 7.4.7 AF remap and debug I/O configuration register (AFIO_MAPR2)
- 7.5 GPIO and AFIO register maps
- 7.1 GPIO functional description
- 8 Interrupts and events
- 8.1 Nested vectored interrupt controller (NVIC)
- 8.2 External interrupt/event controller (EXTI)
- 8.3 EXTI registers
- 9 Direct memory access controller (DMA)
- 9.1 DMA introduction
- 9.2 DMA main features
- 9.3 DMA functional description
- 9.4 DMA registers
- 9.4.1 DMA interrupt status register (DMA_ISR)
- 9.4.2 DMA interrupt flag clear register (DMA_IFCR)
- 9.4.3 DMA channel x configuration register (DMA_CCRx) (x = 1..7, where x = channel number)
- 9.4.4 DMA channel x number of data register (DMA_CNDTRx) (x = 1..7, where x = channel number)
- 9.4.5 DMA channel x peripheral address register (DMA_CPARx) (x = 1..7, where x = channel number)
- 9.4.6 DMA channel x memory address register (DMA_CMARx) (x = 1..7, where x = channel number)
- 9.4.7 DMA register map
- 10 Analog-to-digital converter (ADC)
- 10.1 ADC introduction
- 10.2 ADC main features
- 10.3 ADC functional description
- 10.4 Calibration
- 10.5 Data alignment
- 10.6 Channel-by-channel programmable sample time
- 10.7 Conversion on external trigger
- 10.8 DMA request
- 10.9 Temperature sensor
- 10.10 ADC interrupts
- 10.11 ADC registers
- 10.11.1 ADC status register (ADC_SR)
- 10.11.2 ADC control register 1 (ADC_CR1)
- 10.11.3 ADC control register 2 (ADC_CR2)
- 10.11.4 ADC sample time register 1 (ADC_SMPR1)
- 10.11.5 ADC sample time register 2 (ADC_SMPR2)
- 10.11.6 ADC injected channel data offset register x (ADC_JOFRx) (x=1..4)
- 10.11.7 ADC watchdog high threshold register (ADC_HTR)
- 10.11.8 ADC watchdog low threshold register (ADC_LTR)
- 10.11.9 ADC regular sequence register 1 (ADC_SQR1)
- 10.11.10 ADC regular sequence register 2 (ADC_SQR2)
- 10.11.11 ADC regular sequence register 3 (ADC_SQR3)
- 10.11.12 ADC injected sequence register (ADC_JSQR)
- 10.11.13 ADC injected data register x (ADC_JDRx) (x= 1..4)
- 10.11.14 ADC regular data register (ADC_DR)
- 10.11.15 ADC register map
- 11 Digital-to-analog converter (DAC)
- 11.1 DAC introduction
- 11.2 DAC main features
- 11.3 DAC functional description
- 11.4 Dual DAC channel conversion
- 11.4.1 Independent trigger without wave generation
- 11.4.2 Independent trigger with single LFSR generation
- 11.4.3 Independent trigger with different LFSR generation
- 11.4.4 Independent trigger with single triangle generation
- 11.4.5 Independent trigger with different triangle generation
- 11.4.6 Simultaneous software start
- 11.4.7 Simultaneous trigger without wave generation
- 11.4.8 Simultaneous trigger with single LFSR generation
- 11.4.9 Simultaneous trigger with different LFSR generation
- 11.4.10 Simultaneous trigger with single triangle generation
- 11.4.11 Simultaneous trigger with different triangle generation
- 11.5 DAC registers
- 11.5.1 DAC control register (DAC_CR)
- 11.5.2 DAC software trigger register (DAC_SWTRIGR)
- 11.5.3 DAC channel1 12-bit right-aligned data holding register (DAC_DHR12R1)
- 11.5.4 DAC channel1 12-bit left aligned data holding register (DAC_DHR12L1)
- 11.5.5 DAC channel1 8-bit right aligned data holding register (DAC_DHR8R1)
- 11.5.6 DAC channel2 12-bit right aligned data holding register (DAC_DHR12R2)
- 11.5.7 DAC channel2 12-bit left aligned data holding register (DAC_DHR12L2)
- 11.5.8 DAC channel2 8-bit right-aligned data holding register (DAC_DHR8R2)
- 11.5.9 Dual DAC 12-bit right-aligned data holding register (DAC_DHR12RD)
- 11.5.10 DUAL DAC 12-bit left aligned data holding register (DAC_DHR12LD)
- 11.5.11 DUAL DAC 8-bit right aligned data holding register (DAC_DHR8RD)
- 11.5.12 DAC channel1 data output register (DAC_DOR1)
- 11.5.13 DAC channel2 data output register (DAC_DOR2)
- 11.5.14 DAC status register (DAC_SR)
- 11.5.15 DAC register map
- 12 Advanced-control timer (TIM1)
- 12.1 TIM1 introduction
- 12.2 TIM1 main features
- 12.3 TIM1 functional description
- 12.3.1 Time-base unit
- 12.3.2 Counter modes
- Figure 43. Counter timing diagram, internal clock divided by 1
- Figure 44. Counter timing diagram, internal clock divided by 2
- Figure 45. Counter timing diagram, internal clock divided by 4
- Figure 46. Counter timing diagram, internal clock divided by N
- Figure 47. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded)
- Figure 48. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded)
- Figure 49. Counter timing diagram, internal clock divided by 1
- Figure 50. Counter timing diagram, internal clock divided by 2
- Figure 51. Counter timing diagram, internal clock divided by 4
- Figure 52. Counter timing diagram, internal clock divided by N
- Figure 53. Counter timing diagram, update event when repetition counter is not used
- Figure 54. Counter timing diagram, internal clock divided by 1, TIMx_ARR = 0x6
- Figure 55. Counter timing diagram, internal clock divided by 2
- Figure 56. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36
- Figure 57. Counter timing diagram, internal clock divided by N
- Figure 58. Counter timing diagram, update event with ARPE=1 (counter underflow)
- Figure 59. Counter timing diagram, Update event with ARPE=1 (counter overflow)
- 12.3.3 Repetition counter
- 12.3.4 Clock selection
- 12.3.5 Capture/compare channels
- 12.3.6 Input capture mode
- 12.3.7 PWM input mode
- 12.3.8 Forced output mode
- 12.3.9 Output compare mode
- 12.3.10 PWM mode
- 12.3.11 Complementary outputs and dead-time insertion
- 12.3.12 Using the break function
- 12.3.13 Clearing the OCxREF signal on an external event
- 12.3.14 6-step PWM generation
- 12.3.15 One-pulse mode
- 12.3.16 Encoder interface mode
- 12.3.17 Timer input XOR function
- 12.3.18 Interfacing with Hall sensors
- 12.3.19 TIMx and external trigger synchronization
- 12.3.20 Timer synchronization
- 12.3.21 Debug mode
- 12.4 TIM1 registers
- 12.4.1 TIM1 control register 1 (TIMx_CR1)
- 12.4.2 TIM1 control register 2 (TIMx_CR2)
- 12.4.3 TIM1 slave mode control register (TIMx_SMCR)
- 12.4.4 TIM1 DMA/interrupt enable register (TIMx_DIER)
- 12.4.5 TIM1 status register (TIMx_SR)
- 12.4.6 TIM1 event generation register (TIMx_EGR)
- 12.4.7 TIM1 capture/compare mode register 1 (TIMx_CCMR1)
- 12.4.8 TIM1 capture/compare mode register 2 (TIMx_CCMR2)
- 12.4.9 TIM1 capture/compare enable register (TIMx_CCER)
- 12.4.10 TIM1 counter (TIMx_CNT)
- 12.4.11 TIM1 prescaler (TIMx_PSC)
- 12.4.12 TIM1 auto-reload register (TIMx_ARR)
- 12.4.13 TIM1 repetition counter register (TIMx_RCR)
- 12.4.14 TIM1 capture/compare register 1 (TIMx_CCR1)
- 12.4.15 TIM1 capture/compare register 2 (TIMx_CCR2)
- 12.4.16 TIM1 capture/compare register 3 (TIMx_CCR3)
- 12.4.17 TIM1 capture/compare register 4 (TIMx_CCR4)
- 12.4.18 TIM1 break and dead-time register (TIMx_BDTR)
- 12.4.19 TIM1 DMA control register (TIMx_DCR)
- 12.4.20 TIM1 DMA address for full transfer (TIMx_DMAR)
- 12.4.21 TIM1 register map
- 13 General-purpose timers (TIM2 to TIM5)
- 13.1 TIM2 to TIM5 introduction
- 13.2 TIM2 to TIM5 main features
- 13.3 TIM2 to TIM5 functional description
- 13.3.1 Time-base unit
- 13.3.2 Counter modes
- Figure 91. Counter timing diagram, internal clock divided by 1
- Figure 92. Counter timing diagram, internal clock divided by 2
- Figure 93. Counter timing diagram, internal clock divided by 4
- Figure 94. Counter timing diagram, internal clock divided by N
- Figure 95. Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not preloaded)
- Figure 96. Counter timing diagram, Update event when ARPE=1 (TIMx_ARR preloaded)
- Figure 97. Counter timing diagram, internal clock divided by 1
- Figure 98. Counter timing diagram, internal clock divided by 2
- Figure 99. Counter timing diagram, internal clock divided by 4
- Figure 100. Counter timing diagram, internal clock divided by N
- Figure 101. Counter timing diagram, Update event
- Figure 102. Counter timing diagram, internal clock divided by 1, TIMx_ARR=0x6
- Figure 103. Counter timing diagram, internal clock divided by 2
- Figure 104. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36
- Figure 105. Counter timing diagram, internal clock divided by N
- Figure 106. Counter timing diagram, Update event with ARPE=1 (counter underflow)
- Figure 107. Counter timing diagram, Update event with ARPE=1 (counter overflow)
- 13.3.3 Clock selection
- 13.3.4 Capture/compare channels
- 13.3.5 Input capture mode
- 13.3.6 PWM input mode
- 13.3.7 Forced output mode
- 13.3.8 Output compare mode
- 13.3.9 PWM mode
- 13.3.10 One-pulse mode
- 13.3.11 Clearing the OCxREF signal on an external event
- 13.3.12 Encoder interface mode
- 13.3.13 Timer input XOR function
- 13.3.14 Timers and external trigger synchronization
- 13.3.15 Timer synchronization
- 13.3.16 Debug mode
- 13.4 TIMx2 to TIM5 registers
- 13.4.1 TIMx control register 1 (TIMx_CR1)
- 13.4.2 TIMx control register 2 (TIMx_CR2)
- 13.4.3 TIMx slave mode control register (TIMx_SMCR)
- 13.4.4 TIMx DMA/Interrupt enable register (TIMx_DIER)
- 13.4.5 TIMx status register (TIMx_SR)
- 13.4.6 TIMx event generation register (TIMx_EGR)
- 13.4.7 TIMx capture/compare mode register 1 (TIMx_CCMR1)
- 13.4.8 TIMx capture/compare mode register 2 (TIMx_CCMR2)
- 13.4.9 TIMx capture/compare enable register (TIMx_CCER)
- 13.4.10 TIMx counter (TIMx_CNT)
- 13.4.11 TIMx prescaler (TIMx_PSC)
- 13.4.12 TIMx auto-reload register (TIMx_ARR)
- 13.4.13 TIMx capture/compare register 1 (TIMx_CCR1)
- 13.4.14 TIMx capture/compare register 2 (TIMx_CCR2)
- 13.4.15 TIMx capture/compare register 3 (TIMx_CCR3)
- 13.4.16 TIMx capture/compare register 4 (TIMx_CCR4)
- 13.4.17 TIMx DMA control register (TIMx_DCR)
- 13.4.18 TIMx DMA address for full transfer (TIMx_DMAR)
- 13.4.19 TIMx register map
- 14 General-purpose timers (TIM12/13/14)
- 14.1 TIM12/13/14 introduction
- 14.2 TIM12/13/14 main features
- 14.3 TIM12/13/14 functional description
- 14.3.1 Time-base unit
- 14.3.2 Counter modes
- Figure 138. Counter timing diagram, internal clock divided by 1
- Figure 139. Counter timing diagram, internal clock divided by 2
- Figure 140. Counter timing diagram, internal clock divided by 4
- Figure 141. Counter timing diagram, internal clock divided by N
- Figure 142. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded)
- Figure 143. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded)
- 14.3.3 Clock selection
- 14.3.4 Capture/compare channels
- 14.3.5 Input capture mode
- 14.3.6 PWM input mode (only for TIM12)
- 14.3.7 Forced output mode
- 14.3.8 Output compare mode
- 14.3.9 PWM mode
- 14.3.10 One-pulse mode
- 14.3.11 TIM12 external trigger synchronization
- 14.3.12 Timer synchronization (TIM12)
- 14.3.13 Debug mode
- 14.4 TIM12 registers
- 14.4.1 TIM12 control register 1 (TIMx_CR1)
- 14.4.2 TIM12 control register 2 (TIMx_CR2)
- 14.4.3 TIM12 slave mode control register (TIMx_SMCR)
- 14.4.4 TIM12 Interrupt enable register (TIMx_DIER)
- 14.4.5 TIM12 status register (TIMx_SR)
- 14.4.6 TIM event generation register (TIMx_EGR)
- 14.4.7 TIM capture/compare mode register 1 (TIMx_CCMR1)
- 14.4.8 TIM12 capture/compare enable register (TIMx_CCER)
- 14.4.9 TIM12 counter (TIMx_CNT)
- 14.4.10 TIM12 prescaler (TIMx_PSC)
- 14.4.11 TIM12 auto-reload register (TIMx_ARR)
- 14.4.12 TIM12 capture/compare register 1 (TIMx_CCR1)
- 14.4.13 TIM12 capture/compare register 2 (TIMx_CCR2)
- 14.4.14 TIM12 register map
- 14.5 TIM13/14 registers
- 14.5.1 TIM13/14 control register 1 (TIMx_CR1)
- 14.5.2 TIM10/11/13/14 Interrupt enable register (TIMx_DIER)
- 14.5.3 TIM13/14 status register (TIMx_SR)
- 14.5.4 TIM13/14 event generation register (TIMx_EGR)
- 14.5.5 TIM13/14 capture/compare mode register 1 (TIMx_CCMR1)
- 14.5.6 TIM13/14 capture/compare enable register (TIMx_CCER)
- 14.5.7 TIM13/14 counter (TIMx_CNT)
- 14.5.8 TIM13/14 prescaler (TIMx_PSC)
- 14.5.9 TIM13/14 auto-reload register (TIMx_ARR)
- 14.5.10 TIM13/14 capture/compare register 1 (TIMx_CCR1)
- 14.5.11 TIM13/14 register map
- 15 General-purpose timers (TIM15/16/17)
- 15.1 TIM15/16/17 introduction
- 15.2 TIM15 main features
- 15.3 TIM16 and TIM17 main features
- 15.4 TIM15/16/17 functional description
- 15.4.1 Time-base unit
- 15.4.2 Counter modes
- Figure 161. Counter timing diagram, internal clock divided by 1
- Figure 162. Counter timing diagram, internal clock divided by 2
- Figure 163. Counter timing diagram, internal clock divided by 4
- Figure 164. Counter timing diagram, internal clock divided by N
- Figure 165. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded)
- Figure 166. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded)
- 15.4.3 Repetition counter
- 15.4.4 Clock selection
- 15.4.5 Capture/compare channels
- 15.4.6 Input capture mode
- 15.4.7 PWM input mode (only for TIM15)
- 15.4.8 Forced output mode
- 15.4.9 Output compare mode
- 15.4.10 PWM mode
- 15.4.11 Complementary outputs and dead-time insertion
- 15.4.12 Using the break function
- 15.4.13 One-pulse mode
- 15.4.14 TIM15 and external trigger synchronization (only for TIM15)
- 15.4.15 Timer synchronization
- 15.4.16 Debug mode
- 15.5 TIM15 registers
- 15.5.1 TIM15 control register 1 (TIM15_CR1)
- 15.5.2 TIM15 control register 2 (TIM15_CR2)
- 15.5.3 TIM15 slave mode control register (TIM15_SMCR)
- 15.5.4 TIM15 DMA/interrupt enable register (TIM15_DIER)
- 15.5.5 TIM15 status register (TIM15_SR)
- 15.5.6 TIM15 event generation register (TIM15_EGR)
- 15.5.7 TIM15 capture/compare mode register 1 (TIM15_CCMR1)
- 15.5.8 TIM15 capture/compare enable register (TIM15_CCER)
- 15.5.9 TIM15 counter (TIM15_CNT)
- 15.5.10 TIM15 prescaler (TIM15_PSC)
- 15.5.11 TIM15 auto-reload register (TIM15_ARR)
- 15.5.12 TIM15 repetition counter register (TIM15_RCR)
- 15.5.13 TIM15 capture/compare register 1 (TIM15_CCR1)
- 15.5.14 TIM15 capture/compare register 2 (TIM15_CCR2)
- 15.5.15 TIM15 break and dead-time register (TIM15_BDTR)
- 15.5.16 TIM15 DMA control register (TIM15_DCR)
- 15.5.17 TIM15 DMA address for full transfer (TIM15_DMAR)
- 15.5.18 TIM15 register map
- 15.6 TIM16&TIM17 registers
- 15.6.1 TIM16&TIM17 control register 1 (TIMx_CR1)
- 15.6.2 TIM16&TIM17 control register 2 (TIMx_CR2)
- 15.6.3 TIM16&TIM17 DMA/interrupt enable register (TIMx_DIER)
- 15.6.4 TIM16&TIM17 status register (TIMx_SR)
- 15.6.5 TIM16&TIM17 event generation register (TIMx_EGR)
- 15.6.6 TIM16&TIM17 capture/compare mode register 1 (TIMx_CCMR1)
- 15.6.7 TIM16&TIM17 capture/compare enable register (TIMx_CCER)
- 15.6.8 TIM16&TIM17 counter (TIMx_CNT)
- 15.6.9 TIM16&TIM17 prescaler (TIMx_PSC)
- 15.6.10 TIM16&TIM17 auto-reload register (TIMx_ARR)
- 15.6.11 TIM16&TIM17 repetition counter register (TIMx_RCR)
- 15.6.12 TIM16&TIM17 capture/compare register 1 (TIMx_CCR1)
- 15.6.13 TIM16&TIM17 break and dead-time register (TIMx_BDTR)
- 15.6.14 TIM16&TIM17 DMA control register (TIMx_DCR)
- 15.6.15 TIM16&TIM17 DMA address for full transfer (TIMx_DMAR)
- 15.6.16 TIM16&TIM17 register map
- 16 Basic timers (TIM6 and TIM7)
- 16.1 TIM6&TIM7 introduction
- 16.2 TIM6&TIM7 main features
- 16.3 TIM6&TIM7 functional description
- 16.3.1 Time-base unit
- 16.3.2 Counting mode
- Figure 189. Counter timing diagram, internal clock divided by 1
- Figure 190. Counter timing diagram, internal clock divided by 2
- Figure 191. Counter timing diagram, internal clock divided by 4
- Figure 192. Counter timing diagram, internal clock divided by N
- Figure 193. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded)
- Figure 194. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded)
- 16.3.3 Clock source
- 16.3.4 Debug mode
- 16.4 TIM6&TIM7 registers
- 16.4.1 TIM6&TIM7 control register 1 (TIMx_CR1)
- 16.4.2 TIM6&TIM7 control register 2 (TIMx_CR2)
- 16.4.3 TIM6&TIM7 DMA/Interrupt enable register (TIMx_DIER)
- 16.4.4 TIM6&TIM7 status register (TIMx_SR)
- 16.4.5 TIM6&TIM7 event generation register (TIMx_EGR)
- 16.4.6 TIM6&TIM7 counter (TIMx_CNT)
- 16.4.7 TIM6&TIM7 prescaler (TIMx_PSC)
- 16.4.8 TIM6&TIM7 auto-reload register (TIMx_ARR)
- 16.4.9 TIM6&TIM7 register map
- 17 Real-time clock (RTC)
- 17.1 RTC introduction
- 17.2 RTC main features
- 17.3 RTC functional description
- 17.4 RTC registers
- 17.4.1 RTC control register high (RTC_CRH)
- 17.4.2 RTC control register low (RTC_CRL)
- 17.4.3 RTC prescaler load register (RTC_PRLH / RTC_PRLL)
- 17.4.4 RTC prescaler divider register (RTC_DIVH / RTC_DIVL)
- 17.4.5 RTC counter register (RTC_CNTH / RTC_CNTL)
- 17.4.6 RTC alarm register high (RTC_ALRH / RTC_ALRL)
- 17.4.7 RTC register map
- 18 Independent watchdog (IWDG)
- 19 Window watchdog (WWDG)
- 20 Flexible static memory controller (FSMC)
- 20.1 FSMC main features
- 20.2 Block diagram
- 20.3 AHB interface
- 20.4 External device address mapping
- 20.5 NOR Flash/PSRAM controller
- Table 92. Programmable NOR/PSRAM access parameters (continued)
- 20.5.1 External memory interface signals
- 20.5.2 Supported memories and transactions
- 20.5.3 General timing rules
- 20.5.4 NOR Flash/PSRAM controller asynchronous transactions
- Figure 204. Mode1 read accesses
- Figure 205. Mode1 write accesses
- Table 98. FSMC_BCRx bit fields (continued)
- Table 99. FSMC_BTRx bit fields
- Figure 206. ModeA read accesses
- Figure 207. ModeA write accesses
- Table 100. FSMC_BCRx bit fields
- Table 101. FSMC_BTRx bit fields
- Table 102. FSMC_BWTRx bit fields
- Figure 208. Mode2 and mode B read accesses
- Figure 209. Mode2 write accesses
- Figure 210. Mode B write accesses
- Table 103. FSMC_BCRx bit fields
- Table 104. FSMC_BTRx bit fields
- Table 105. FSMC_BWTRx bit fields
- Figure 211. Mode C read accesses
- Figure 212. Mode C write accesses
- Table 106. FSMC_BCRx bit fields (continued)
- Table 107. FSMC_BTRx bit fields
- Table 108. FSMC_BWTRx bit fields
- Figure 213. Mode D read accesses
- Figure 214. Mode D write accesses
- Table 109. FSMC_BCRx bit fields
- Table 110. FSMC_BTRx bit fields
- Table 111. FSMC_BWTRx bit fields
- Figure 215. Multiplexed read accesses
- Figure 216. Multiplexed write accesses
- Table 112. FSMC_BCRx bit fields (continued)
- Table 113. FSMC_BTRx bit fields
- Figure 217. Asynchronous wait during a read access
- Figure 218. Asynchronous wait during a write access
- 20.5.5 Synchronous transactions
- Figure 219. Wait configurations
- Figure 220. Synchronous multiplexed read mode - NOR, PSRAM (CRAM)
- Table 114. FSMC_BCRx bit fields (continued)
- Table 115. FSMC_BTRx bit fields
- Figure 221. Synchronous multiplexed write mode - PSRAM (CRAM)
- Table 116. FSMC_BCRx bit fields (continued)
- Table 117. FSMC_BTRx bit fields
- 20.5.6 NOR/PSRAM control registers
- 20.5.7 FSMC register map
- 21 Serial peripheral interface (SPI)
- 21.1 SPI introduction
- 21.2 SPI main features
- 21.3 SPI functional description
- 21.3.1 General description
- 21.3.2 Configuring the SPI in slave mode
- 21.3.3 Configuring the SPI in master mode
- 21.3.4 Configuring the SPI for half-duplex communication
- 21.3.5 Data transmission and reception procedures
- Figure 225. TXE/RXNE/BSY behavior in Master / full-duplex mode (BIDIMODE=0 and RXONLY=0) in case of continuous transfers
- Figure 226. TXE/RXNE/BSY behavior in Slave / full-duplex mode (BIDIMODE=0, RXONLY=0) in case of continuous transfers
- Figure 227. TXE/BSY behavior in Master transmit-only mode (BIDIMODE=0 and RXONLY=0) in case of continuous transfers
- Figure 228. TXE/BSY in Slave transmit-only mode (BIDIMODE=0 and RXONLY=0) in case of continuous transfers
- Figure 229. RXNE behavior in receive-only mode (BIDIRMODE=0 and RXONLY=1) in case of continuous transfers
- Figure 230. TXE/BSY behavior when transmitting (BIDIRMODE=0 and RXONLY=0) in case of discontinuous transfers
- 21.3.6 CRC calculation
- 21.3.7 Status flags
- 21.3.8 Disabling the SPI
- 21.3.9 SPI communication using DMA (direct memory addressing)
- 21.3.10 Error flags
- 21.3.11 SPI interrupts
- 21.4 SPI registers
- 22 Inter-integrated circuit (I2C) interface
- 22.1 I2C introduction
- 22.2 I2C main features
- 22.3 I2C functional description
- 22.3.1 Mode selection
- 22.3.2 I2C slave mode
- 22.3.3 I2C master mode
- Figure 237. Transfer sequence diagram for master transmitter
- Figure 238. Method 1: transfer sequence diagram for master receiver
- Figure 239. Method 2: transfer sequence diagram for master receiver when N>2
- Figure 240. Method 2: transfer sequence diagram for master receiver when N=2
- Figure 241. Method 2: transfer sequence diagram for master receiver when N=1
- 22.3.4 Error conditions
- 22.3.5 SDA/SCL line control
- 22.3.6 SMBus
- 22.3.7 DMA requests
- 22.3.8 Packet error checking
- 22.4 I2C interrupts
- 22.5 I2C debug mode
- 22.6 I2C registers
- 22.6.1 I2C Control register 1 (I2C_CR1)
- 22.6.2 I2C Control register 2 (I2C_CR2)
- 22.6.3 I2C Own address register 1 (I2C_OAR1)
- 22.6.4 I2C Own address register 2 (I2C_OAR2)
- 22.6.5 I2C Data register (I2C_DR)
- 22.6.6 I2C Status register 1 (I2C_SR1)
- 22.6.7 I2C Status register 2 (I2C_SR2)
- 22.6.8 I2C Clock control register (I2C_CCR)
- 22.6.9 I2C TRISE register (I2C_TRISE)
- 22.6.10 I2C register map
- 23 Universal synchronous asynchronous receiver transmitter (USART)
- 23.1 USART introduction
- 23.2 USART main features
- 23.3 USART functional description
- Figure 243. USART block diagram
- 23.3.1 USART character description
- 23.3.2 Transmitter
- 23.3.3 Receiver
- 23.3.4 Fractional baud rate generation
- Table 125. Error calculation for programmed baud rates at fPCLK = 8 MHz or fPCLK = 12 MHz, oversampling by 16
- Table 126. Error calculation for programmed baud rates at fPCLK = 8 MHz or fPCLK =12 MHz, oversampling by 8
- Table 127. Error calculation for programmed baud rates at fPCLK = 16 MHz or fPCLK = 24 MHz, oversampling by 16 (continued)
- Table 128. Error calculation for programmed baud rates at fPCLK = 16 MHz or fPCLK = 24 MHz, oversampling by 8
- 23.3.5 USART receiver tolerance to clock deviation
- 23.3.6 Multiprocessor communication
- 23.3.7 Parity control
- 23.3.8 LIN (local interconnection network) mode
- 23.3.9 USART synchronous mode
- 23.3.10 Single-wire half-duplex communication
- 23.3.11 Smartcard
- 23.3.12 IrDA SIR ENDEC block
- 23.3.13 Continuous communication using DMA
- 23.3.14 Hardware flow control
- 23.4 USART interrupts
- 23.5 USART mode configuration
- 23.6 USART registers
- 24 High-definition multimedia interface-consumer electronics control controller (HDMI™-CEC)
- 24.1 Introduction
- 24.2 HDMI-CEC main features
- 24.3 HDMI-CEC bus topology
- 24.4 Arbitration
- 24.5 Error handling
- 24.6 Device addressing
- 24.7 HDMI-CEC functional description
- 24.7.1 Block diagram
- 24.7.2 Prescaler
- 24.7.3 Rx digital filter
- 24.7.4 Rx bit timing
- 24.7.5 Tx bit timing
- 24.7.6 CEC arbiter
- 24.7.7 CEC states
- Figure 279. CEC control state machine
- Figure 280. Example of a complete message reception
- Table 140. Software sequence to respect when receiving a message
- Figure 281. Example of a complete message transmission
- Table 141. Software sequence to respect when transmitting a message (continued)
- Figure 282. Example of a message transmission with transmission error
- Table 142. Software sequence to respect when transmitting a message
- 24.7.8 CEC and system Stop mode
- 24.8 HDMI-CEC interrupts
- 24.9 HDMI-CEC registers
- 24.9.1 CEC configuration register (CEC_CFGR)
- 24.9.2 CEC own address register (CEC_OAR)
- 24.9.3 CEC prescaler register (CEC_PRES)
- 24.9.4 CEC error status register (CEC_ESR)
- 24.9.5 CEC control and status register (CEC_CSR)
- 24.9.6 CEC Tx data register (CEC_TXD)
- 24.9.7 CEC Rx data register (CEC_RXD)
- 24.9.8 HDMI-CEC register map
- 25 Debug support (DBG)
- 25.1 Overview
- 25.2 Reference ARM® documentation
- 25.3 SWJ debug port (serial wire and JTAG)
- 25.4 Pinout and debug port pins
- 25.5 STM32F100xx JTAG TAP connection
- 25.6 ID codes and locking mechanism
- 25.7 JTAG debug port
- 25.8 SW debug port
- 25.9 AHB-AP (AHB access port) - valid for both JTAG-DP and SW-DP
- 25.10 Core debug
- 25.11 Capability of the debugger host to connect under system reset
- 25.12 FPB (Flash patch breakpoint)
- 25.13 DWT (data watchpoint trigger)
- 25.14 ITM (instrumentation trace macrocell)
- 25.15 MCU debug component (DBGMCU)
- 25.16 TPIU (trace port interface unit)
- 25.16.1 Introduction
- 25.16.2 TRACE pin assignment
- 25.16.3 TPUI formatter
- 25.16.4 TPUI frame synchronization packets
- 25.16.5 Transmission of the synchronization frame packet
- 25.16.6 Synchronous mode
- 25.16.7 Asynchronous mode
- 25.16.8 TRACECLKIN connection inside the STM32F100xx
- 25.16.9 TPIU registers
- 25.16.10 Example of configuration
- 25.17 DBG register map
- 26 Device electronic signature
- 27 Revision history