STM32F030x4/x6/x8/xC And STM32F070x6/xB Advanced ARM® Based 32 Bit MCUs Reference Manual STM32F070x6x B En.DM00091010
STM32F070CBT6%20Ref%20Manual
stm32f030f4_Reference_Manual
STM32F030F4P6%20-%20Reference%20Manual
en.DM00091010%20-%20STM32F030x%20and%20070x%20Reference%20Manual
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- 1 Documentation conventions
- 2 System and memory overview
- 3 Embedded Flash memory
- 3.1 Flash main features
- 3.2 Flash memory functional description
- 3.3 Memory protection
- 3.4 Flash interrupts
- 3.5 Flash register description
- 3.5.1 Flash access control register (FLASH_ACR)
- 3.5.2 Flash key register (FLASH_KEYR)
- 3.5.3 Flash option key register (FLASH_OPTKEYR)
- 3.5.4 Flash status register (FLASH_SR)
- 3.5.5 Flash control register (FLASH_CR)
- 3.5.6 Flash address register (FLASH_AR)
- 3.5.7 Flash Option byte register (FLASH_OBR)
- 3.5.8 Write protection register (FLASH_WRPR)
- 3.5.9 Flash register map
- 4 Option bytes
- 5 Cyclic redundancy check calculation unit (CRC)
- 6 Power control (PWR)
- 7 Reset and clock control (RCC)
- 7.1 Reset
- 7.2 Clocks
- Figure 10. Clock tree (STM32F030x4, STM32F030x6 and STM32F030x8 devices)
- Figure 11. Clock tree (STM32F070x6, STM32F070xB and STM32F030xC)
- 7.2.1 HSE clock
- 7.2.2 HSI clock
- 7.2.3 PLL
- 7.2.4 LSE clock
- 7.2.5 LSI clock
- 7.2.6 System clock (SYSCLK) selection
- 7.2.7 Clock security system (CSS)
- 7.2.8 ADC clock
- 7.2.9 RTC clock
- 7.2.10 Independent watchdog clock
- 7.2.11 Clock-out capability
- 7.2.12 Internal/external clock measurement with TIM14
- 7.3 Low-power modes
- 7.4 RCC registers
- 7.4.1 Clock control register (RCC_CR)
- 7.4.2 Clock configuration register (RCC_CFGR)
- 7.4.3 Clock interrupt register (RCC_CIR)
- 7.4.4 APB peripheral reset register 2 (RCC_APB2RSTR)
- 7.4.5 APB peripheral reset register 1 (RCC_APB1RSTR)
- 7.4.6 AHB peripheral clock enable register (RCC_AHBENR)
- 7.4.7 APB peripheral clock enable register 2 (RCC_APB2ENR)
- 7.4.8 APB peripheral clock enable register 1 (RCC_APB1ENR)
- 7.4.9 RTC domain control register (RCC_BDCR)
- 7.4.10 Control/status register (RCC_CSR)
- 7.4.11 AHB peripheral reset register (RCC_AHBRSTR)
- 7.4.12 Clock configuration register 2 (RCC_CFGR2)
- 7.4.13 Clock configuration register 3 (RCC_CFGR3)
- 7.4.14 Clock control register 2 (RCC_CR2)
- 7.4.15 RCC register map
- 8 General-purpose I/Os (GPIO)
- 8.1 Introduction
- 8.2 GPIO main features
- 8.3 GPIO functional description
- Figure 14. Basic structure of an I/O port bit
- Table 22. Port bit configuration table (continued)
- 8.3.1 General-purpose I/O (GPIO)
- 8.3.2 I/O pin alternate function multiplexer and mapping
- 8.3.3 I/O port control registers
- 8.3.4 I/O port data registers
- 8.3.5 I/O data bitwise handling
- 8.3.6 GPIO locking mechanism
- 8.3.7 I/O alternate function input/output
- 8.3.8 External interrupt/wakeup lines
- 8.3.9 Input configuration
- 8.3.10 Output configuration
- 8.3.11 Alternate function configuration
- 8.3.12 Analog configuration
- 8.3.13 Using the HSE or LSE oscillator pins as GPIOs
- 8.3.14 Using the GPIO pins in the RTC supply domain
- 8.4 GPIO registers
- 8.4.1 GPIO port mode register (GPIOx_MODER) (x =A..D, F)
- 8.4.2 GPIO port output type register (GPIOx_OTYPER) (x = A..D, F)
- 8.4.3 GPIO port output speed register (GPIOx_OSPEEDR) (x = A..D, F)
- 8.4.4 GPIO port pull-up/pull-down register (GPIOx_PUPDR) (x = A..,D, F)
- 8.4.5 GPIO port input data register (GPIOx_IDR) (x = A..D, F)
- 8.4.6 GPIO port output data register (GPIOx_ODR) (x = A..D, F)
- 8.4.7 GPIO port bit set/reset register (GPIOx_BSRR) (x = A..D, F)
- 8.4.8 GPIO port configuration lock register (GPIOx_LCKR) (x = A..B)
- 8.4.9 GPIO alternate function low register (GPIOx_AFRL) (x = A..D, )
- 8.4.10 GPIO alternate function high register (GPIOx_AFRH) (x = A..D, F)
- 8.4.11 GPIO port bit reset register (GPIOx_BRR) (x =A..D, F)
- 8.4.12 GPIO register map
- 9 System configuration controller (SYSCFG)
- 9.1 SYSCFG registers
- 9.1.1 SYSCFG configuration register 1 (SYSCFG_CFGR1)
- 9.1.2 SYSCFG external interrupt configuration register 1 (SYSCFG_EXTICR1)
- 9.1.3 SYSCFG external interrupt configuration register 2 (SYSCFG_EXTICR2)
- 9.1.4 SYSCFG external interrupt configuration register 3 (SYSCFG_EXTICR3)
- 9.1.5 SYSCFG external interrupt configuration register 4 (SYSCFG_EXTICR4)
- 9.1.6 SYSCFG configuration register 2 (SYSCFG_CFGR2)
- 9.1.7 SYSCFG register maps
- 9.1 SYSCFG registers
- 10 Direct memory access controller (DMA)
- 10.1 Introduction
- 10.2 DMA main features
- 10.3 DMA functional description
- 10.4 DMA registers
- 10.4.1 DMA interrupt status register (DMA_ISR)
- 10.4.2 DMA interrupt flag clear register (DMA_IFCR)
- 10.4.3 DMA channel x configuration register (DMA_CCRx) (x = 1..5, where x = channel number)
- 10.4.4 DMA channel x number of data register (DMA_CNDTRx) (x = 1..5, where x = channel number)
- 10.4.5 DMA channel x peripheral address register (DMA_CPARx) (x = 1..5, where x = channel number)
- 10.4.6 DMA channel x memory address register (DMA_CMARx) (x = 1..5, where x = channel number)
- 10.4.7 DMA channel selection register (DMA_CSELR)
- 10.4.8 DMA register map
- 11 Interrupts and events
- 11.1 Nested vectored interrupt controller (NVIC)
- 11.2 Extended interrupts and events controller (EXTI)
- 11.3 EXTI registers
- 12 Analog-to-digital converter (ADC)
- 12.1 Introduction
- 12.2 ADC main features
- 12.3 ADC pins and internal signals
- 12.4 ADC functional description
- Figure 23. ADC block diagram
- 12.4.1 Calibration (ADCAL)
- 12.4.2 ADC on-off control (ADEN, ADDIS, ADRDY)
- 12.4.3 ADC clock (CKMODE)
- 12.4.4 Configuring the ADC
- 12.4.5 Channel selection (CHSEL, SCANDIR)
- 12.4.6 Programmable sampling time (SMP)
- 12.4.7 Single conversion mode (CONT=0)
- 12.4.8 Continuous conversion mode (CONT=1)
- 12.4.9 Starting conversions (ADSTART)
- 12.4.10 Timings
- 12.4.11 Stopping an ongoing conversion (ADSTP)
- 12.5 Conversion on external trigger and trigger polarity (EXTSEL, EXTEN)
- Table 37. Configuring the trigger polarity
- Table 38. External triggers
- 12.5.1 Discontinuous mode (DISCEN)
- 12.5.2 Programmable resolution (RES) - fast conversion mode
- 12.5.3 End of conversion, end of sampling phase (EOC, EOSMP flags)
- 12.5.4 End of conversion sequence (EOSEQ flag)
- 12.5.5 Example timing diagrams (single/continuous modes hardware/software triggers)
- 12.6 Data management
- 12.7 Low-power features
- 12.8 Analog window watchdog (AWDEN, AWDSGL, AWDCH, AWD_HTR/LTR, AWD)
- 12.9 Temperature sensor and internal reference voltage
- 12.10 ADC interrupts
- 12.11 ADC registers
- 12.11.1 ADC interrupt and status register (ADC_ISR)
- 12.11.2 ADC interrupt enable register (ADC_IER)
- 12.11.3 ADC control register (ADC_CR)
- 12.11.4 ADC configuration register 1 (ADC_CFGR1)
- 12.11.5 ADC configuration register 2 (ADC_CFGR2)
- 12.11.6 ADC sampling time register (ADC_SMPR)
- 12.11.7 ADC watchdog threshold register (ADC_TR)
- 12.11.8 ADC channel selection register (ADC_CHSELR)
- 12.11.9 ADC data register (ADC_DR)
- 12.11.10 ADC common configuration register (ADC_CCR)
- 12.11.11 ADC register map
- 13 Advanced-control timers (TIM1)
- 13.1 TIM1 introduction
- 13.2 TIM1 main features
- 13.3 TIM1 functional description
- 13.3.1 Time-base unit
- 13.3.2 Counter modes
- Figure 43. Counter timing diagram, internal clock divided by 1
- Figure 44. Counter timing diagram, internal clock divided by 2
- Figure 45. Counter timing diagram, internal clock divided by 4
- Figure 46. Counter timing diagram, internal clock divided by N
- Figure 47. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded)
- Figure 48. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded)
- Figure 49. Counter timing diagram, internal clock divided by 1
- Figure 50. Counter timing diagram, internal clock divided by 2
- Figure 51. Counter timing diagram, internal clock divided by 4
- Figure 52. Counter timing diagram, internal clock divided by N
- Figure 53. Counter timing diagram, update event when repetition counter is not used
- Figure 54. Counter timing diagram, internal clock divided by 1, TIMx_ARR = 0x6
- Figure 55. Counter timing diagram, internal clock divided by 2
- Figure 56. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36
- Figure 57. Counter timing diagram, internal clock divided by N
- Figure 58. Counter timing diagram, update event with ARPE=1 (counter underflow)
- Figure 59. Counter timing diagram, Update event with ARPE=1 (counter overflow)
- 13.3.3 Repetition counter
- 13.3.4 Clock sources
- 13.3.5 Capture/compare channels
- 13.3.6 Input capture mode
- 13.3.7 PWM input mode
- 13.3.8 Forced output mode
- 13.3.9 Output compare mode
- 13.3.10 PWM mode
- 13.3.11 Complementary outputs and dead-time insertion
- 13.3.12 Using the break function
- 13.3.13 Clearing the OCxREF signal on an external event
- 13.3.14 6-step PWM generation
- 13.3.15 One-pulse mode
- 13.3.16 Encoder interface mode
- 13.3.17 Timer input XOR function
- 13.3.18 Interfacing with Hall sensors
- 13.3.19 TIMx and external trigger synchronization
- 13.3.20 Timer synchronization
- 13.3.21 Debug mode
- 13.4 TIM1 registers
- 13.4.1 TIM1 control register 1 (TIM1_CR1)
- 13.4.2 TIM1 control register 2 (TIM1_CR2)
- 13.4.3 TIM1 slave mode control register (TIM1_SMCR)
- 13.4.4 TIM1 DMA/interrupt enable register (TIM1_DIER)
- 13.4.5 TIM1 status register (TIM1_SR)
- 13.4.6 TIM1 event generation register (TIM1_EGR)
- 13.4.7 TIM1 capture/compare mode register 1 (TIM1_CCMR1)
- 13.4.8 TIM1 capture/compare mode register 2 (TIM1_CCMR2)
- 13.4.9 TIM1 capture/compare enable register (TIM1_CCER)
- 13.4.10 TIM1 counter (TIM1_CNT)
- 13.4.11 TIM1 prescaler (TIM1_PSC)
- 13.4.12 TIM1 auto-reload register (TIM1_ARR)
- 13.4.13 TIM1 repetition counter register (TIM1_RCR)
- 13.4.14 TIM1 capture/compare register 1 (TIM1_CCR1)
- 13.4.15 TIM1 capture/compare register 2 (TIM1_CCR2)
- 13.4.16 TIM1 capture/compare register 3 (TIM1_CCR3)
- 13.4.17 TIM1 capture/compare register 4 (TIM1_CCR4)
- 13.4.18 TIM1 break and dead-time register (TIM1_BDTR)
- 13.4.19 TIM1 DMA control register (TIM1_DCR)
- 13.4.20 TIM1 DMA address for full transfer (TIM1_DMAR)
- 13.4.21 TIM1 register map
- 14 General-purpose timers (TIM3)
- 14.1 TIM3 introduction
- 14.2 TIM3 main features
- 14.3 TIM3 functional description
- 14.3.1 Time-base unit
- 14.3.2 Counter modes
- Figure 91. Counter timing diagram, internal clock divided by 1
- Figure 92. Counter timing diagram, internal clock divided by 2
- Figure 93. Counter timing diagram, internal clock divided by 4
- Figure 94. Counter timing diagram, internal clock divided by N
- Figure 95. Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not preloaded)
- Figure 96. Counter timing diagram, Update event when ARPE=1 (TIMx_ARR preloaded)
- Figure 97. Counter timing diagram, internal clock divided by 1
- Figure 98. Counter timing diagram, internal clock divided by 2
- Figure 99. Counter timing diagram, internal clock divided by 4
- Figure 100. Counter timing diagram, internal clock divided by N
- Figure 101. Counter timing diagram, Update event when repetition counter is not used
- Figure 102. Counter timing diagram, internal clock divided by 1, TIMx_ARR=0x6
- Figure 103. Counter timing diagram, internal clock divided by 2
- Figure 104. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36
- Figure 105. Counter timing diagram, internal clock divided by N
- Figure 106. Counter timing diagram, Update event with ARPE=1 (counter underflow)
- Figure 107. Counter timing diagram, Update event with ARPE=1 (counter overflow)
- 14.3.3 Clock sources
- 14.3.4 Capture/compare channels
- 14.3.5 Input capture mode
- 14.3.6 PWM input mode
- 14.3.7 Forced output mode
- 14.3.8 Output compare mode
- 14.3.9 PWM mode
- 14.3.10 One-pulse mode
- 14.3.11 Clearing the OCxREF signal on an external event
- 14.3.12 Encoder interface mode
- 14.3.13 Timer input XOR function
- 14.3.14 Timers and external trigger synchronization
- 14.3.15 Timer synchronization
- Figure 128. Master/Slave timer example
- Figure 129. Gating timer 3 with OC1REF of timer 1
- Figure 130. Gating timer 3 with Enable of timer 1
- Figure 131. Triggering timer 3 with update of timer 1
- Figure 132. Triggering timer 3 with Enable of timer 1
- Figure 133. Triggering timer 1 and 3 with timer 1 TI1 input
- 14.3.16 Debug mode
- 14.4 TIM3 registers
- 14.4.1 TIM3 control register 1 (TIM3_CR1)
- 14.4.2 TIM3 control register 2 (TIM3_CR2)
- 14.4.3 TIM3 slave mode control register (TIM3_SMCR)
- 14.4.4 TIM3 DMA/Interrupt enable register (TIM3_DIER)
- 14.4.5 TIM3 status register (TIM3_SR)
- 14.4.6 TIM3 event generation register (TIM3_EGR)
- 14.4.7 TIM3 capture/compare mode register 1 (TIM3_CCMR1)
- 14.4.8 TIM3 capture/compare mode register 2 (TIM3_CCMR2)
- 14.4.9 TIM3 capture/compare enable register (TIM3_CCER)
- 14.4.10 TIM3 counter (TIM3_CNT)
- 14.4.11 TIM3 prescaler (TIM3_PSC)
- 14.4.12 TIM3 auto-reload register (TIM3_ARR)
- 14.4.13 TIM3 capture/compare register 1 (TIM3_CCR1)
- 14.4.14 TIM3 capture/compare register 2 (TIM3_CCR2)
- 14.4.15 TIM3 capture/compare register 3 (TIM3_CCR3)
- 14.4.16 TIM3 capture/compare register 4 (TIM3_CCR4)
- 14.4.17 TIM3 DMA control register (TIM3_DCR)
- 14.4.18 TIM3 DMA address for full transfer (TIM3_DMAR)
- 14.4.19 TIM3 register map
- 15 Basic timer (TIM6/TIM7)
- 15.1 TIM6/TIM7 introduction
- 15.2 TIM6/TIM7 main features
- 15.3 TIM6/TIM7 functional description
- 15.3.1 Time-base unit
- 15.3.2 Counter modes
- Figure 137. Counter timing diagram, internal clock divided by 1
- Figure 138. Counter timing diagram, internal clock divided by 2
- Figure 139. Counter timing diagram, internal clock divided by 4
- Figure 140. Counter timing diagram, internal clock divided by N
- Figure 141. Counter timing diagram, update event when ARPE = 0 (TIMx_ARR not preloaded)
- Figure 142. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded)
- 15.3.3 Clock source
- 15.3.4 Debug mode
- 15.4 TIM6/TIM7 registers
- 15.4.1 TIM6/TIM7 control register 1 (TIMx_CR1)
- 15.4.2 TIM6/TIM7 DMA/Interrupt enable register (TIMx_DIER)
- 15.4.3 TIM6/TIM7 status register (TIMx_SR)
- 15.4.4 TIM6/TIM7 event generation register (TIMx_EGR)
- 15.4.5 TIM6/TIM7 counter (TIMx_CNT)
- 15.4.6 TIM6/TIM7 prescaler (TIMx_PSC)
- 15.4.7 TIM6/TIM7 auto-reload register (TIMx_ARR)
- 15.4.8 TIM6/TIM7 register map
- 16 General-purpose timer (TIM14)
- 16.1 TIM14 introduction
- 16.2 TIM14 main features
- 16.3 TIM14 functional description
- 16.3.1 Time-base unit
- 16.3.2 Counter modes
- Figure 147. Counter timing diagram, internal clock divided by 1
- Figure 148. Counter timing diagram, internal clock divided by 2
- Figure 149. Counter timing diagram, internal clock divided by 4
- Figure 150. Counter timing diagram, internal clock divided by N
- Figure 151. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded)
- Figure 152. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded)
- 16.3.3 Clock source
- 16.3.4 Capture/compare channels
- 16.3.5 Input capture mode
- 16.3.6 Forced output mode
- 16.3.7 Output compare mode
- 16.3.8 PWM mode
- 16.3.9 Debug mode
- 16.4 TIM14 registers
- 16.4.1 TIM14 control register 1 (TIM14_CR1)
- 16.4.2 TIM14 interrupt enable register (TIM14_DIER)
- 16.4.3 TIM14 status register (TIM14_SR)
- 16.4.4 TIM14 event generation register (TIM14_EGR)
- 16.4.5 TIM14 capture/compare mode register 1 (TIM14_CCMR1)
- 16.4.6 TIM14 capture/compare enable register (TIM14_CCER)
- 16.4.7 TIM14 counter (TIM14_CNT)
- 16.4.8 TIM14 prescaler (TIM14_PSC)
- 16.4.9 TIM14 auto-reload register (TIM14_ARR)
- 16.4.10 TIM14 capture/compare register 1 (TIM14_CCR1)
- 16.4.11 TIM14 option register (TIM14_OR)
- 16.4.12 TIM14 register map
- 17 General-purpose timers (TIM15/16/17)
- 17.1 TIM15/16/17 introduction
- 17.2 TIM15 main features
- 17.3 TIM16 and TIM17 main features
- 17.4 TIM15/16/17 functional description
- 17.4.1 Time-base unit
- 17.4.2 Counter modes
- Figure 163. Counter timing diagram, internal clock divided by 1
- Figure 164. Counter timing diagram, internal clock divided by 2
- Figure 165. Counter timing diagram, internal clock divided by 4
- Figure 166. Counter timing diagram, internal clock divided by N
- Figure 167. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded)
- Figure 168. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded)
- 17.4.3 Repetition counter
- 17.4.4 Clock sources
- 17.4.5 Capture/compare channels
- 17.4.6 Input capture mode
- 17.4.7 PWM input mode (only for TIM15)
- 17.4.8 Forced output mode
- 17.4.9 Output compare mode
- 17.4.10 PWM mode
- 17.4.11 Complementary outputs and dead-time insertion
- 17.4.12 Using the break function
- 17.4.13 One-pulse mode
- 17.4.14 TIM15 external trigger synchronization
- 17.4.15 Timer synchronization (TIM15)
- 17.4.16 Debug mode
- 17.5 TIM15 registers
- 17.5.1 TIM15 control register 1 (TIM15_CR1)
- 17.5.2 TIM15 control register 2 (TIM15_CR2)
- 17.5.3 TIM15 slave mode control register (TIM15_SMCR)
- 17.5.4 TIM15 DMA/interrupt enable register (TIM15_DIER)
- 17.5.5 TIM15 status register (TIM15_SR)
- 17.5.6 TIM15 event generation register (TIM15_EGR)
- 17.5.7 TIM15 capture/compare mode register 1 (TIM15_CCMR1)
- 17.5.8 TIM15 capture/compare enable register (TIM15_CCER)
- 17.5.9 TIM15 counter (TIM15_CNT)
- 17.5.10 TIM15 prescaler (TIM15_PSC)
- 17.5.11 TIM15 auto-reload register (TIM15_ARR)
- 17.5.12 TIM15 repetition counter register (TIM15_RCR)
- 17.5.13 TIM15 capture/compare register 1 (TIM15_CCR1)
- 17.5.14 TIM15 capture/compare register 2 (TIM15_CCR2)
- 17.5.15 TIM15 break and dead-time register (TIM15_BDTR)
- 17.5.16 TIM15 DMA control register (TIM15_DCR)
- 17.5.17 TIM15 DMA address for full transfer (TIM15_DMAR)
- 17.5.18 TIM15 register map
- 17.6 TIM16 and TIM17 registers
- 17.6.1 TIM16 and TIM17 control register 1 (TIM16_CR1 and TIM17_CR1)
- 17.6.2 TIM16 and TIM17 control register 2 (TIM16_CR2 and TIM17_CR2)
- 17.6.3 TIM16 and TIM17 DMA/interrupt enable register (TIM16_DIER and TIM17_DIER)
- 17.6.4 TIM16 and TIM17 status register (TIM16_SR and TIM17_SR)
- 17.6.5 TIM16 and TIM17 event generation register (TIM16_EGR and TIM17_EGR)
- 17.6.6 TIM16 and TIM17 capture/compare mode register 1 (TIM16_CCMR1 and TIM17_CCMR1)
- 17.6.7 TIM16 and TIM17 capture/compare enable register (TIM16_CCER and TIM17_CCER)
- 17.6.8 TIM16 and TIM17 counter (TIM16_CNT and TIM17_CNT)
- 17.6.9 TIM16 and TIM17 prescaler (TIM16_PSC and TIM17_PSC)
- 17.6.10 TIM16 and TIM17 auto-reload register (TIM16_ARR and TIM17_ARR)
- 17.6.11 TIM16 and TIM17 repetition counter register (TIM16_RCR and TIM17_RCR)
- 17.6.12 TIM16 and TIM17 capture/compare register 1 (TIM16_CCR1 and TIM17_CCR1)
- 17.6.13 TIM16 and TIM17 break and dead-time register (TIM16_BDTR and TIM17_BDTR)
- 17.6.14 TIM16 and TIM17 DMA control register (TIM16_DCR and TIM17_DCR)
- 17.6.15 TIM16 and TIM17 DMA address for full transfer (TIM16_DMAR and TIM17_DMAR)
- 17.6.16 TIM16 and TIM17 register map
- 18 Infrared interface (IRTIM)
- 19 Independent watchdog (IWDG)
- 20 System window watchdog (WWDG)
- 21 Real-time clock (RTC)
- 21.1 Introduction
- 21.2 RTC main features
- 21.3 RTC implementation
- 21.4 RTC functional description
- 21.4.1 RTC block diagram
- 21.4.2 GPIOs controlled by the RTC
- 21.4.3 Clock and prescalers
- 21.4.4 Real-time clock and calendar
- 21.4.5 Programmable alarm
- 21.4.6 Periodic auto-wakeup
- 21.4.7 RTC initialization and configuration
- 21.4.8 Reading the calendar
- 21.4.9 Resetting the RTC
- 21.4.10 RTC synchronization
- 21.4.11 RTC reference clock detection
- 21.4.12 RTC smooth digital calibration
- 21.4.13 Time-stamp function
- 21.4.14 Tamper detection
- 21.4.15 Calibration clock output
- 21.4.16 Alarm output
- 21.5 RTC low-power modes
- 21.6 RTC interrupts
- 21.7 RTC registers
- 21.7.1 RTC time register (RTC_TR)
- 21.7.2 RTC date register (RTC_DR)
- 21.7.3 RTC control register (RTC_CR)
- 21.7.4 RTC initialization and status register (RTC_ISR)
- 21.7.5 RTC prescaler register (RTC_PRER)
- 21.7.6 RTC wakeup timer register (RTC_WUTR)
- 21.7.7 RTC alarm A register (RTC_ALRMAR)
- 21.7.8 RTC write protection register (RTC_WPR)
- 21.7.9 RTC sub second register (RTC_SSR)
- 21.7.10 RTC shift control register (RTC_SHIFTR)
- 21.7.11 RTC timestamp time register (RTC_TSTR)
- 21.7.12 RTC timestamp date register (RTC_TSDR)
- 21.7.13 RTC time-stamp sub second register (RTC_TSSSR)
- 21.7.14 RTC calibration register (RTC_CALR)
- 21.7.15 RTC tamper and alternate function configuration register (RTC_TAFCR)
- 21.7.16 RTC alarm A sub second register (RTC_ALRMASSR)
- 21.7.17 RTC register map
- 22 Inter-integrated circuit (I2C) interface
- 22.1 Introduction
- 22.2 I2C main features
- 22.3 I2C implementation
- 22.4 I2C functional description
- 22.4.1 I2C block diagram
- 22.4.2 I2C2 block diagram
- 22.4.3 I2C clock requirements
- 22.4.4 Mode selection
- 22.4.5 I2C initialization
- 22.4.6 Software reset
- 22.4.7 Data transfer
- 22.4.8 I2C slave mode
- Figure 201. Slave initialization flowchart
- Figure 202. Transfer sequence flowchart for I2C slave transmitter, NOSTRETCH=0
- Figure 203. Transfer sequence flowchart for I2C slave transmitter, NOSTRETCH=1
- Figure 204. Transfer bus diagrams for I2C slave transmitter
- Figure 205. Transfer sequence flowchart for slave receiver with NOSTRETCH=0
- Figure 206. Transfer sequence flowchart for slave receiver with NOSTRETCH=1
- Figure 207. Transfer bus diagrams for I2C slave receiver
- 22.4.9 I2C master mode
- Figure 208. Master clock generation
- Table 73. I2C-SMBUS specification clock timings
- Figure 209. Master initialization flowchart
- Figure 210. 10-bit address read access with HEAD10R=0
- Figure 211. 10-bit address read access with HEAD10R=1
- Figure 212. Transfer sequence flowchart for I2C master transmitter for N≤255 bytes
- Figure 213. Transfer sequence flowchart for I2C master transmitter for N>255 bytes
- Figure 214. Transfer bus diagrams for I2C master transmitter
- Figure 215. Transfer sequence flowchart for I2C master receiver for N≤255 bytes
- Figure 216. Transfer sequence flowchart for I2C master receiver for N >255 bytes
- Figure 217. Transfer bus diagrams for I2C master receiver
- 22.4.10 I2C_TIMINGR register configuration examples
- 22.4.11 SMBus specific features
- 22.4.12 SMBus initialization
- 22.4.13 SMBus: I2C_TIMEOUTR register configuration examples
- 22.4.14 SMBus slave mode
- Figure 219. Transfer sequence flowchart for SMBus slave transmitter N bytes + PEC
- Figure 220. Transfer bus diagrams for SMBus slave transmitter (SBC=1)
- Figure 221. Transfer sequence flowchart for SMBus slave receiver N Bytes + PEC
- Figure 222. Bus transfer diagrams for SMBus slave receiver (SBC=1)
- Figure 223. Bus transfer diagrams for SMBus master transmitter
- Figure 224. Bus transfer diagrams for SMBus master receiver
- 22.4.15 Error conditions
- 22.4.16 DMA requests
- 22.4.17 Debug mode
- 22.5 I2C low-power modes
- 22.6 I2C interrupts
- 22.7 I2C registers
- 22.7.1 Control register 1 (I2C_CR1)
- 22.7.2 Control register 2 (I2C_CR2)
- 22.7.3 Own address 1 register (I2C_OAR1)
- 22.7.4 Own address 2 register (I2C_OAR2)
- 22.7.5 Timing register (I2C_TIMINGR)
- 22.7.6 Timeout register (I2C_TIMEOUTR)
- 22.7.7 Interrupt and status register (I2C_ISR)
- 22.7.8 Interrupt clear register (I2C_ICR)
- 22.7.9 PEC register (I2C_PECR)
- 22.7.10 Receive data register (I2C_RXDR)
- 22.7.11 Transmit data register (I2C_TXDR)
- 22.7.12 I2C register map
- 23 Universal synchronous asynchronous receiver transmitter (USART)
- 23.1 Introduction
- 23.2 USART main features
- 23.3 USART implementation
- 23.4 USART functional description
- Figure 226. USART block diagram
- 23.4.1 USART character description
- 23.4.2 USART transmitter
- 23.4.3 USART receiver
- 23.4.4 USART baud rate generation
- 23.4.5 Tolerance of the USART receiver to clock deviation
- 23.4.6 USART auto baud rate detection
- 23.4.7 Multiprocessor communication using USART
- 23.4.8 USART parity control
- 23.4.9 A.15.6: USART synchronous mode code exampleUSART synchronous mode
- 23.4.10 USART Single-wire Half-duplex communication
- 23.4.11 USART continuous communication in DMA mode
- 23.4.12 RS232 hardware flow control and RS485 driver enable using USART
- 23.5 USART low-power modes
- 23.6 USART interrupts
- 23.7 USART registers
- 23.7.1 Control register 1 (USART_CR1)
- 23.7.2 Control register 2 (USART_CR2)
- 23.7.3 Control register 3 (USART_CR3)
- 23.7.4 Baud rate register (USART_BRR)
- 23.7.5 Receiver timeout register (USART_RTOR)
- 23.7.6 Request register (USART_RQR)
- 23.7.7 Interrupt and status register (USART_ISR)
- 23.7.8 Interrupt flag clear register (USART_ICR)
- 23.7.9 Receive data register (USART_RDR)
- 23.7.10 Transmit data register (USART_TDR)
- 23.7.11 USART register map
- 24 Serial peripheral interface (SPI)
- 24.1 Introduction
- 24.2 SPI main features
- 24.3 SPI implementation
- 24.4 SPI functional description
- 24.4.1 General description
- 24.4.2 Communications between one master and one slave
- 24.4.3 Standard multi-slave communication
- 24.4.4 Multi-master communication
- 24.4.5 Slave select (NSS) pin management
- 24.4.6 Communication formats
- 24.4.7 Configuration of SPI
- 24.4.8 Procedure for enabling SPI
- 24.4.9 Data transmission and reception procedures
- 24.4.10 SPI status flags
- 24.4.11 SPI error flags
- 24.4.12 NSS pulse mode
- 24.4.13 TI mode
- 24.4.14 CRC calculation
- 24.5 SPI interrupts
- 24.6 SPI registers
- 24.6.1 SPI control register 1 (SPIx_CR1)
- 24.6.2 SPI control register 2 (SPIx_CR2)
- 24.6.3 SPI status register (SPIx_SR)
- 24.6.4 SPI data register (SPIx_DR)
- 24.6.5 SPI CRC polynomial register (SPIx_CRCPR)
- 24.6.6 SPI Rx CRC register (SPIx_RXCRCR)
- 24.6.7 SPI Tx CRC register (SPIx_TXCRCR)
- 24.6.8 SPI register map
- 25 Universal serial bus full-speed device interface (USB)
- 25.1 Introduction
- 25.2 USB main features
- 25.3 USB implementation
- 25.4 USB functional description
- 25.5 Programming considerations
- 25.6 USB registers
- 26 Debug support (DBG)
- 26.1 Overview
- 26.2 Reference ARM documentation
- 26.3 Pinout and debug port pins
- 26.4 ID codes and locking mechanism
- 26.5 SWD port
- 26.6 Core debug
- 26.7 BPU (Break Point Unit)
- 26.8 DWT (Data Watchpoint)
- 26.9 MCU debug component (DBGMCU)
- 27 Device electronic signature
- Appendix A Code examples
- A.1 Introduction
- A.2 Flash operation code example
- A.2.1 Flash memory unlocking sequence code
- A.2.2 Main Flash programming sequence code example
- A.2.3 Page erase sequence code example
- A.2.4 Mass erase sequence code example
- A.2.5 Option byte unlocking sequence code example
- A.2.6 Option byte programming sequence code example
- A.2.7 Option byte erasing sequence code example
- A.3 Clock controller
- A.4 GPIO
- A.5 DMA
- A.6 Interrupts and event
- A.7 ADC
- A.7.1 ADC Calibration code example
- A.7.2 ADC enable sequence code example
- A.7.3 ADC disable sequence code example
- A.7.4 ADC Clock selection code example
- A.7.5 Single conversion sequence code example - Software trigger
- A.7.6 Continuous conversion sequence code example - Software trigger
- A.7.7 Single conversion sequence code example - Hardware trigger
- A.7.8 Continuous conversion sequence code example - Hardware trigger
- A.7.9 DMA one shot mode sequence code example
- A.7.10 DMA circular mode sequence code example
- A.7.11 Wait mode sequence code example
- A.7.12 Auto Off and no wait mode sequence code example
- A.7.13 Auto Off and wait mode sequence code example
- A.7.14 Analog watchdog code example
- A.7.15 Temperature configuration code example
- A.7.16 Temperature computation code example
- A.8 Timers
- A.8.1 Upcounter on TI2 rising edge code example
- A.8.2 Up counter on each 2 ETR rising edges code example
- A.8.3 Input capture configuration code example
- A.8.4 Input capture data management code example
- A.8.5 PWM input configuration code example
- A.8.6 PWM input with DMA configuration code example
- A.8.7 Output compare configuration code example
- A.8.8 Edge-aligned PWM configuration example
- A.8.9 Center-aligned PWM configuration example
- A.8.10 ETR configuration to clear OCxREF code example
- A.8.11 Encoder interface code example
- A.8.12 Reset mode code example
- A.8.13 Gated mode code example
- A.8.14 Trigger mode code example
- A.8.15 External clock mode 2 + trigger mode code example
- A.8.16 One-Pulse mode code example
- A.8.17 Timer prescaling another timer code example
- A.8.18 Timer enabling another timer code example
- A.8.19 Master and slave synchronization code example
- A.8.20 Two timers synchronized by an external trigger code example
- A.8.21 DMA burst feature code example
- A.9 IRTIM code example
- A.10 DBG code example
- A.11 I2C code example
- A.11.1 I2C configured in master mode to receive code example
- A.11.2 I2C configured in master mode to transmit code example
- A.11.3 I2C configured in slave mode code example
- A.11.4 I2C master transmitter code example
- A.11.5 I2C master receiver code example
- A.11.6 I2C slave transmitter code example
- A.11.7 I2C slave receiver code example
- A.11.8 I2C configured in master mode to transmit with DMA code example
- A.11.9 I2C configured in slave mode to receive with DMA code example
- A.12 IWDG code example
- A.13 RTC code example
- A.13.1 RTC calendar configuration code example
- A.13.2 RTC alarm configuration code example
- A.13.3 RTC WUT configuration code example
- A.13.4 RTC read calendar code example
- A.13.5 RTC calibration code example
- A.13.6 RTC tamper and time stamp configuration code example
- A.13.7 RTC tamper and time stamp code example
- A.13.8 RTC clock output code example
- A.14 SPI code example
- A.15 USART code example
- A.15.1 USART transmitter configuration code example
- A.15.2 USART transmit byte code example
- A.15.3 USART transfer complete code example
- A.15.4 USART receiver configuration code example
- A.15.5 USART receive byte code example
- A.15.6 USART synchronous mode code example
- A.15.7 USART DMA code example
- A.15.8 USART hardware flow control code example
- A.16 WWDG code example
- Revision history