STM32F030x4/x6/x8/xC And STM32F070x6/xB Advanced ARM® Based 32 Bit MCUs Reference Manual STM32F070x6x B En.DM00091010

STM32F070CBT6%20Ref%20Manual

stm32f030f4_Reference_Manual

STM32F030F4P6%20-%20Reference%20Manual

en.DM00091010%20-%20STM32F030x%20and%20070x%20Reference%20Manual

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RM0360
Reference manual
STM32F030x4/x6/x8/xC and STM32F070x6/xB
advanced ARM®-based 32-bit MCUs
Introduction
This reference manual targets application developers. It provides complete information on
how to use the STM32F030x4/x6/x8/xC and STM32F070x6/xB microcontroller memory and
peripherals.
It applies to STM32F030x4/x6/x8/xC and STM32F070x6/xB devices.
For the purpose of this manual, STM32F030x4/x6/x8/xC and STM32F070x6/xB
microcontrollers are referred to as STM32F0x0.
The STM32F0x0 is a family of microcontrollers with different memory sizes, packages and
peripherals.
For ordering information, mechanical and electrical device characteristics, please refer to
the corresponding datasheet.
For information on the ARM® Cortex®-M0 core, please refer to the ARM® Cortex®-M0
technical reference manual.

Related documents
 ARM® Cortex®-M0 technical reference manual, available from ARM website at
www.arm.com
 STM32F0xx Cortex-M0 programming manual (PM0215)
 STM32F030x4/x6/x8/xC and STM32F070x6/xB datasheets available from
STMicroelectronics website at www.st.com

April 2017

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Contents

RM0360

Contents
1

2

3

Documentation conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
1.1

List of abbreviations for registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

1.2

Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

1.3

Peripheral availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

System and memory overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
2.1

System architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

2.2

Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

2.2.2

Memory map and register boundary addresses . . . . . . . . . . . . . . . . . . 37

2.3

Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

2.4

Flash memory overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

2.5

Boot configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.1

Flash main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

3.2

Flash memory functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

3.3

2/779

2.2.1

3.2.1

Flash memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

3.2.2

Flash program and erase operations . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Memory protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
3.3.1

Read protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

3.3.2

Write protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

3.3.3

Option byte write protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

3.4

Flash interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

3.5

Flash register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
3.5.1

Flash access control register (FLASH_ACR) . . . . . . . . . . . . . . . . . . . . 58

3.5.2

Flash key register (FLASH_KEYR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

3.5.3

Flash option key register (FLASH_OPTKEYR) . . . . . . . . . . . . . . . . . . . 59

3.5.4

Flash status register (FLASH_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

3.5.5

Flash control register (FLASH_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

3.5.6

Flash address register (FLASH_AR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

3.5.7

Flash Option byte register (FLASH_OBR) . . . . . . . . . . . . . . . . . . . . . . . 62

3.5.8

Write protection register (FLASH_WRPR) . . . . . . . . . . . . . . . . . . . . . . . 63

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3.5.9

4

Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
4.1

5

Option byte description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
4.1.1

User and read protection option byte . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

4.1.2

User data option byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

4.1.3

Write protection option byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

4.1.4

Option byte map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . . 69
5.1

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

5.2

CRC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

5.3

CRC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

5.4

6

Flash register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

5.3.1

CRC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

5.3.2

CRC internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

5.3.3

CRC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

CRC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
5.4.1

Data register (CRC_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

5.4.2

Independent data register (CRC_IDR) . . . . . . . . . . . . . . . . . . . . . . . . . 72

5.4.3

Control register (CRC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

5.4.4

Initial CRC value (CRC_INIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

5.4.5

CRC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Power control (PWR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
6.1

6.2

Power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
6.1.1

Independent A/D converter supply and reference voltage . . . . . . . . . . . 75

6.1.2

Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
6.2.1

6.3

Power on reset (POR) / power down reset (PDR) . . . . . . . . . . . . . . . . . 76

Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
6.3.1

Slowing down system clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

6.3.2

Peripheral clock gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

6.3.3

Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

6.3.4

Stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

6.3.5

Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

6.3.6

RTC wakeup from low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

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6.4

7

6.4.1

Power control register (PWR_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

6.4.2

Power control/status register (PWR_CSR) . . . . . . . . . . . . . . . . . . . . . . 85

6.4.3

PWR register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Reset and clock control (RCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
7.1

7.2

4/779

Power control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
7.1.1

Power reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

7.1.2

System reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

7.1.3

RTC domain reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
7.2.1

HSE clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

7.2.2

HSI clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

7.2.3

PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

7.2.4

LSE clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

7.2.5

LSI clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

7.2.6

System clock (SYSCLK) selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

7.2.7

Clock security system (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

7.2.8

ADC clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

7.2.9

RTC clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

7.2.10

Independent watchdog clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

7.2.11

Clock-out capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

7.2.12

Internal/external clock measurement with TIM14 . . . . . . . . . . . . . . . . . 97

7.3

Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

7.4

RCC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
7.4.1

Clock control register (RCC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

7.4.2

Clock configuration register (RCC_CFGR) . . . . . . . . . . . . . . . . . . . . . 101

7.4.3

Clock interrupt register (RCC_CIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

7.4.4

APB peripheral reset register 2 (RCC_APB2RSTR) . . . . . . . . . . . . . . 106

7.4.5

APB peripheral reset register 1 (RCC_APB1RSTR) . . . . . . . . . . . . . . 108

7.4.6

AHB peripheral clock enable register (RCC_AHBENR) . . . . . . . . . . . 111

7.4.7

APB peripheral clock enable register 2 (RCC_APB2ENR) . . . . . . . . . 112

7.4.8

APB peripheral clock enable register 1 (RCC_APB1ENR) . . . . . . . . . 114

7.4.9

RTC domain control register (RCC_BDCR) . . . . . . . . . . . . . . . . . . . . . 117

7.4.10

Control/status register (RCC_CSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

7.4.11

AHB peripheral reset register (RCC_AHBRSTR) . . . . . . . . . . . . . . . . 120

7.4.12

Clock configuration register 2 (RCC_CFGR2) . . . . . . . . . . . . . . . . . . . 122
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7.4.13

Clock configuration register 3 (RCC_CFGR3) . . . . . . . . . . . . . . . . . . . 123

7.4.14

Clock control register 2 (RCC_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . 123

7.4.15

RCC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

General-purpose I/Os (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
8.1

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

8.2

GPIO main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

8.3

GPIO functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

8.4

8.3.1

General-purpose I/O (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

8.3.2

I/O pin alternate function multiplexer and mapping . . . . . . . . . . . . . . . 129

8.3.3

I/O port control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

8.3.4

I/O port data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

8.3.5

I/O data bitwise handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

8.3.6

GPIO locking mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

8.3.7

I/O alternate function input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

8.3.8

External interrupt/wakeup lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

8.3.9

Input configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

8.3.10

Output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

8.3.11

Alternate function configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

8.3.12

Analog configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

8.3.13

Using the HSE or LSE oscillator pins as GPIOs . . . . . . . . . . . . . . . . . 135

8.3.14

Using the GPIO pins in the RTC supply domain . . . . . . . . . . . . . . . . . 135

GPIO registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
8.4.1

GPIO port mode register (GPIOx_MODER) (x =A..D, F) . . . . . . . . . . . 136

8.4.2

GPIO port output type register (GPIOx_OTYPER) (x = A..D, F) . . . . . 136

8.4.3

GPIO port output speed register (GPIOx_OSPEEDR)
(x = A..D, F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

8.4.4

GPIO port pull-up/pull-down register (GPIOx_PUPDR)
(x = A..,D, F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

8.4.5

GPIO port input data register (GPIOx_IDR) (x = A..D, F) . . . . . . . . . . 138

8.4.6

GPIO port output data register (GPIOx_ODR) (x = A..D, F) . . . . . . . . 138

8.4.7

GPIO port bit set/reset register (GPIOx_BSRR) (x = A..D, F) . . . . . . . 138

8.4.8

GPIO port configuration lock register (GPIOx_LCKR)
(x = A..B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

8.4.9

GPIO alternate function low register (GPIOx_AFRL) 
(x = A..D, ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

8.4.10

GPIO alternate function high register (GPIOx_AFRH)
(x = A..D, F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

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8.4.12

GPIO register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

SYSCFG registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
9.1.1

SYSCFG configuration register 1 (SYSCFG_CFGR1) . . . . . . . . . . . . 144

9.1.2

SYSCFG external interrupt configuration register 1
(SYSCFG_EXTICR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

9.1.3

SYSCFG external interrupt configuration register 2
(SYSCFG_EXTICR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

9.1.4

SYSCFG external interrupt configuration register 3
(SYSCFG_EXTICR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

9.1.5

SYSCFG external interrupt configuration register 4
(SYSCFG_EXTICR4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

9.1.6

SYSCFG configuration register 2 (SYSCFG_CFGR2) . . . . . . . . . . . . 150

9.1.7

SYSCFG register maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

Direct memory access controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . 152
10.1

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

10.2

DMA main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

10.3

DMA functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

10.4

6/779

GPIO port bit reset register (GPIOx_BRR) (x =A..D, F) . . . . . . . . . . . . 141

System configuration controller (SYSCFG) . . . . . . . . . . . . . . . . . . . . 144
9.1

10

8.4.11

10.3.1

DMA transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

10.3.2

Arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

10.3.3

DMA channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

10.3.4

Programmable data width, data alignment and endians . . . . . . . . . . . 156

10.3.5

Error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

10.3.6

DMA interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

DMA registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
10.4.1

DMA interrupt status register (DMA_ISR) . . . . . . . . . . . . . . . . . . . . . . 161

10.4.2

DMA interrupt flag clear register (DMA_IFCR) . . . . . . . . . . . . . . . . . . 162

10.4.3

DMA channel x configuration register (DMA_CCRx)
(x = 1..5, where x = channel number) . . . . . . . . . . . . . . . . . . . . . . . . . 163

10.4.4

DMA channel x number of data register (DMA_CNDTRx) (x = 1..5, where
x = channel number) 165

10.4.5

DMA channel x peripheral address register (DMA_CPARx) (x = 1..5,
where x = channel number) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

10.4.6

DMA channel x memory address register (DMA_CMARx) (x = 1..5,
where x = channel number) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

10.4.7

DMA channel selection register (DMA_CSELR) . . . . . . . . . . . . . . . . . 167

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10.4.8

11

Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
11.1

11.2

11.3

12

DMA register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 170
11.1.1

NVIC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

11.1.2

SysTick calibration value register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

11.1.3

Interrupt and exception vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

Extended interrupts and events controller (EXTI) . . . . . . . . . . . . . . . . . 172
11.2.1

Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

11.2.2

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

11.2.3

Event management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

11.2.4

Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

11.2.5

External and internal interrupt/event line mapping . . . . . . . . . . . . . . . 175

EXTI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
11.3.1

Interrupt mask register (EXTI_IMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

11.3.2

Event mask register (EXTI_EMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

11.3.3

Rising trigger selection register (EXTI_RTSR) . . . . . . . . . . . . . . . . . . 176

11.3.4

Falling trigger selection register (EXTI_FTSR) . . . . . . . . . . . . . . . . . . 177

11.3.5

Software interrupt event register (EXTI_SWIER) . . . . . . . . . . . . . . . . 178

11.3.6

Pending register (EXTI_PR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

11.3.7

EXTI register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

Analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
12.1

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

12.2

ADC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182

12.3

ADC pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

12.4

ADC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
12.4.1

Calibration (ADCAL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184

12.4.2

ADC on-off control (ADEN, ADDIS, ADRDY) . . . . . . . . . . . . . . . . . . . 185

12.4.3

ADC clock (CKMODE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

12.4.4

Configuring the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188

12.4.5

Channel selection (CHSEL, SCANDIR) . . . . . . . . . . . . . . . . . . . . . . . . 189

12.4.6

Programmable sampling time (SMP) . . . . . . . . . . . . . . . . . . . . . . . . . . 189

12.4.7

Single conversion mode (CONT=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . 190

12.4.8

Continuous conversion mode (CONT=1) . . . . . . . . . . . . . . . . . . . . . . . 190

12.4.9

Starting conversions (ADSTART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190

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12.4.10 Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
12.4.11 Stopping an ongoing conversion (ADSTP) . . . . . . . . . . . . . . . . . . . . . 192

12.5

12.6

12.7

Conversion on external trigger and trigger polarity (EXTSEL, EXTEN) . 192
12.5.1

Discontinuous mode (DISCEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193

12.5.2

Programmable resolution (RES) - fast conversion mode . . . . . . . . . . 194

12.5.3

End of conversion, end of sampling phase (EOC, EOSMP flags) . . . . 195

12.5.4

End of conversion sequence (EOSEQ flag) . . . . . . . . . . . . . . . . . . . . 196

12.5.5

Example timing diagrams (single/continuous modes . . . . . . . . . . . . . . . . . 
hardware/software triggers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

Data management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
12.6.1

Data register and data alignment (ADC_DR, ALIGN) . . . . . . . . . . . . . 198

12.6.2

ADC overrun (OVR, OVRMOD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198

12.6.3

Managing a sequence of data converted without using the DMA . . . . 199

12.6.4

Managing converted data without using the DMA without overrun . . . 199

12.6.5

Managing converted data using the DMA . . . . . . . . . . . . . . . . . . . . . . 199

Low-power features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
12.7.1

Wait mode conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201

12.7.2

Auto-off mode (AUTOFF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201

12.8

Analog window watchdog (AWDEN, AWDSGL, AWDCH,
AWD_HTR/LTR, AWD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203

12.9

Temperature sensor and internal reference voltage . . . . . . . . . . . . . . . . 204

12.10 ADC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
12.11 ADC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
12.11.1 ADC interrupt and status register (ADC_ISR) . . . . . . . . . . . . . . . . . . . 207
12.11.2 ADC interrupt enable register (ADC_IER) . . . . . . . . . . . . . . . . . . . . . . 208
12.11.3 ADC control register (ADC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
12.11.4 ADC configuration register 1 (ADC_CFGR1) . . . . . . . . . . . . . . . . . . . 212
12.11.5 ADC configuration register 2 (ADC_CFGR2) . . . . . . . . . . . . . . . . . . . 216
12.11.6 ADC sampling time register (ADC_SMPR) . . . . . . . . . . . . . . . . . . . . . 216
12.11.7 ADC watchdog threshold register (ADC_TR) . . . . . . . . . . . . . . . . . . . 217
12.11.8 ADC channel selection register (ADC_CHSELR) . . . . . . . . . . . . . . . . 218
12.11.9 ADC data register (ADC_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
12.11.10 ADC common configuration register (ADC_CCR) . . . . . . . . . . . . . . . . 219
12.11.11 ADC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220

13

Advanced-control timers (TIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
13.1

8/779

TIM1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
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13.2

TIM1 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221

13.3

TIM1 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
13.3.1

Time-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223

13.3.2

Counter modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225

13.3.3

Repetition counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235

13.3.4

Clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237

13.3.5

Capture/compare channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240

13.3.6

Input capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243

13.3.7

PWM input mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244

13.3.8

Forced output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245

13.3.9

Output compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245

13.3.10 PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
13.3.11 Complementary outputs and dead-time insertion . . . . . . . . . . . . . . . . 250
13.3.12 Using the break function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
13.3.13 Clearing the OCxREF signal on an external event . . . . . . . . . . . . . . . 255
13.3.14 6-step PWM generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
13.3.15 One-pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
13.3.16 Encoder interface mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
13.3.17 Timer input XOR function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
13.3.18 Interfacing with Hall sensors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
13.3.19 TIMx and external trigger synchronization . . . . . . . . . . . . . . . . . . . . . . 264
13.3.20 Timer synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
13.3.21 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267

13.4

TIM1 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
13.4.1

TIM1 control register 1 (TIM1_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . 268

13.4.2

TIM1 control register 2 (TIM1_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . 269

13.4.3

TIM1 slave mode control register (TIM1_SMCR) . . . . . . . . . . . . . . . . 271

13.4.4

TIM1 DMA/interrupt enable register (TIM1_DIER) . . . . . . . . . . . . . . . 274

13.4.5

TIM1 status register (TIM1_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276

13.4.6

TIM1 event generation register (TIM1_EGR) . . . . . . . . . . . . . . . . . . . 277

13.4.7

TIM1 capture/compare mode register 1 (TIM1_CCMR1) . . . . . . . . . . 279

13.4.8

TIM1 capture/compare mode register 2 (TIM1_CCMR2) . . . . . . . . . . 282

13.4.9

TIM1 capture/compare enable register (TIM1_CCER) . . . . . . . . . . . . 284

13.4.10 TIM1 counter (TIM1_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
13.4.11 TIM1 prescaler (TIM1_PSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
13.4.12 TIM1 auto-reload register (TIM1_ARR) . . . . . . . . . . . . . . . . . . . . . . . . 288
13.4.13 TIM1 repetition counter register (TIM1_RCR) . . . . . . . . . . . . . . . . . . . 288

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13.4.14 TIM1 capture/compare register 1 (TIM1_CCR1) . . . . . . . . . . . . . . . . . 288
13.4.15 TIM1 capture/compare register 2 (TIM1_CCR2) . . . . . . . . . . . . . . . . . 289
13.4.16 TIM1 capture/compare register 3 (TIM1_CCR3) . . . . . . . . . . . . . . . . . 289
13.4.17 TIM1 capture/compare register 4 (TIM1_CCR4) . . . . . . . . . . . . . . . . . 290
13.4.18 TIM1 break and dead-time register (TIM1_BDTR) . . . . . . . . . . . . . . . 290
13.4.19 TIM1 DMA control register (TIM1_DCR) . . . . . . . . . . . . . . . . . . . . . . . 292
13.4.20 TIM1 DMA address for full transfer (TIM1_DMAR) . . . . . . . . . . . . . . . 293
13.4.21 TIM1 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294

14

General-purpose timers (TIM3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
14.1

TIM3 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296

14.2

TIM3 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296

14.3

TIM3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
14.3.1

Time-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297

14.3.2

Counter modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299

14.3.3

Clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310

14.3.4

Capture/compare channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313

14.3.5

Input capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315

14.3.6

PWM input mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317

14.3.7

Forced output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318

14.3.8

Output compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318

14.3.9

PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319

14.3.10 One-pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323
14.3.11 Clearing the OCxREF signal on an external event . . . . . . . . . . . . . . . 324
14.3.12 Encoder interface mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325
14.3.13 Timer input XOR function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327
14.3.14 Timers and external trigger synchronization . . . . . . . . . . . . . . . . . . . . 328
14.3.15 Timer synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331
14.3.16 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337

14.4

10/779

TIM3 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338
14.4.1

TIM3 control register 1 (TIM3_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . 338

14.4.2

TIM3 control register 2 (TIM3_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . 340

14.4.3

TIM3 slave mode control register (TIM3_SMCR) . . . . . . . . . . . . . . . . 341

14.4.4

TIM3 DMA/Interrupt enable register (TIM3_DIER) . . . . . . . . . . . . . . . 343

14.4.5

TIM3 status register (TIM3_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344

14.4.6

TIM3 event generation register (TIM3_EGR) . . . . . . . . . . . . . . . . . . . 347

14.4.7

TIM3 capture/compare mode register 1 (TIM3_CCMR1) . . . . . . . . . . 348
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14.4.8

TIM3 capture/compare mode register 2 (TIM3_CCMR2) . . . . . . . . . . 351

14.4.9

TIM3 capture/compare enable register (TIM3_CCER) . . . . . . . . . . . . 352

14.4.10 TIM3 counter (TIM3_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354
14.4.11 TIM3 prescaler (TIM3_PSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354
14.4.12 TIM3 auto-reload register (TIM3_ARR) . . . . . . . . . . . . . . . . . . . . . . . . 354
14.4.13 TIM3 capture/compare register 1 (TIM3_CCR1) . . . . . . . . . . . . . . . . . 354
14.4.14 TIM3 capture/compare register 2 (TIM3_CCR2) . . . . . . . . . . . . . . . . . 355
14.4.15 TIM3 capture/compare register 3 (TIM3_CCR3) . . . . . . . . . . . . . . . . . 355
14.4.16 TIM3 capture/compare register 4 (TIM3_CCR4) . . . . . . . . . . . . . . . . . 356
14.4.17 TIM3 DMA control register (TIM3_DCR) . . . . . . . . . . . . . . . . . . . . . . . 356
14.4.18 TIM3 DMA address for full transfer (TIM3_DMAR) . . . . . . . . . . . . . . . 357
14.4.19 TIM3 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359

15

Basic timer (TIM6/TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361
15.1

TIM6/TIM7 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361

15.2

TIM6/TIM7 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361

15.3

TIM6/TIM7 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362

15.4

16

15.3.1

Time-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362

15.3.2

Counter modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364

15.3.3

Clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368

15.3.4

Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368

TIM6/TIM7 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369
15.4.1

TIM6/TIM7 control register 1 (TIMx_CR1) . . . . . . . . . . . . . . . . . . . . . . 369

15.4.2

TIM6/TIM7 DMA/Interrupt enable register (TIMx_DIER) . . . . . . . . . . . 370

15.4.3

TIM6/TIM7 status register (TIMx_SR) . . . . . . . . . . . . . . . . . . . . . . . . . 371

15.4.4

TIM6/TIM7 event generation register (TIMx_EGR) . . . . . . . . . . . . . . . 371

15.4.5

TIM6/TIM7 counter (TIMx_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371

15.4.6

TIM6/TIM7 prescaler (TIMx_PSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372

15.4.7

TIM6/TIM7 auto-reload register (TIMx_ARR) . . . . . . . . . . . . . . . . . . . 372

15.4.8

TIM6/TIM7 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373

General-purpose timer (TIM14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374
16.1

TIM14 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374

16.2

TIM14 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374

16.3

TIM14 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375
16.3.1

Time-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375

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16.4

16.3.2

Counter modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377

16.3.3

Clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380

16.3.4

Capture/compare channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380

16.3.5

Input capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382

16.3.6

Forced output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383

16.3.7

Output compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383

16.3.8

PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384

16.3.9

Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385

TIM14 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386
16.4.1

TIM14 control register 1 (TIM14_CR1) . . . . . . . . . . . . . . . . . . . . . . . . 386

16.4.2

TIM14 interrupt enable register (TIM14_DIER) . . . . . . . . . . . . . . . . . . 387

16.4.3

TIM14 status register (TIM14_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 387

16.4.4

TIM14 event generation register (TIM14_EGR) . . . . . . . . . . . . . . . . . 388

16.4.5

TIM14 capture/compare mode register 1 (TIM14_CCMR1) . . . . . . . . 389

16.4.6

TIM14 capture/compare enable register (TIM14_CCER) . . . . . . . . . . 392

16.4.7

TIM14 counter (TIM14_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393

16.4.8

TIM14 prescaler (TIM14_PSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393

16.4.9

TIM14 auto-reload register (TIM14_ARR) . . . . . . . . . . . . . . . . . . . . . . 393

16.4.10 TIM14 capture/compare register 1 (TIM14_CCR1) . . . . . . . . . . . . . . . 394
16.4.11 TIM14 option register (TIM14_OR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 394
16.4.12 TIM14 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395

17

General-purpose timers (TIM15/16/17) . . . . . . . . . . . . . . . . . . . . . . . . 397
17.1

TIM15/16/17 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397

17.2

TIM15 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397

17.3

TIM16 and TIM17 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399

17.4

TIM15/16/17 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401
17.4.1

Time-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401

17.4.2

Counter modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403

17.4.3

Repetition counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407

17.4.4

Clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408

17.4.5

Capture/compare channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410

17.4.6

Input capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413

17.4.7

PWM input mode (only for TIM15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414

17.4.8

Forced output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415

17.4.9

Output compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416

17.4.10 PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417
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17.4.11 Complementary outputs and dead-time insertion . . . . . . . . . . . . . . . . 418
17.4.12 Using the break function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421
17.4.13 One-pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424
17.4.14 TIM15 external trigger synchronization . . . . . . . . . . . . . . . . . . . . . . . . 426
17.4.15 Timer synchronization (TIM15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 428
17.4.16 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 428

17.5

TIM15 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 429
17.5.1

TIM15 control register 1 (TIM15_CR1) . . . . . . . . . . . . . . . . . . . . . . . . 429

17.5.2

TIM15 control register 2 (TIM15_CR2) . . . . . . . . . . . . . . . . . . . . . . . . 430

17.5.3

TIM15 slave mode control register (TIM15_SMCR) . . . . . . . . . . . . . . 432

17.5.4

TIM15 DMA/interrupt enable register (TIM15_DIER) . . . . . . . . . . . . . 433

17.5.5

TIM15 status register (TIM15_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 433

17.5.6

TIM15 event generation register (TIM15_EGR) . . . . . . . . . . . . . . . . . 436

17.5.7

TIM15 capture/compare mode register 1 (TIM15_CCMR1) . . . . . . . . 437

17.5.8

TIM15 capture/compare enable register (TIM15_CCER) . . . . . . . . . . 440

17.5.9

TIM15 counter (TIM15_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443

17.5.10 TIM15 prescaler (TIM15_PSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443
17.5.11 TIM15 auto-reload register (TIM15_ARR) . . . . . . . . . . . . . . . . . . . . . . 443
17.5.12 TIM15 repetition counter register (TIM15_RCR) . . . . . . . . . . . . . . . . . 444
17.5.13 TIM15 capture/compare register 1 (TIM15_CCR1) . . . . . . . . . . . . . . . 444
17.5.14 TIM15 capture/compare register 2 (TIM15_CCR2) . . . . . . . . . . . . . . . 445
17.5.15 TIM15 break and dead-time register (TIM15_BDTR) . . . . . . . . . . . . . 445
17.5.16 TIM15 DMA control register (TIM15_DCR) . . . . . . . . . . . . . . . . . . . . . 448
17.5.17 TIM15 DMA address for full transfer (TIM15_DMAR) . . . . . . . . . . . . . 448
17.5.18 TIM15 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 449

17.6

TIM16 and TIM17 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 451
17.6.1

TIM16 and TIM17 control register 1 (TIM16_CR1 and TIM17_CR1) . 451

17.6.2

TIM16 and TIM17 control register 2 (TIM16_CR2 and TIM17_CR2) . 452

17.6.3

TIM16 and TIM17 DMA/interrupt enable register (TIM16_DIER and
TIM17_DIER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453

17.6.4

TIM16 and TIM17 status register (TIM16_SR and TIM17_SR) . . . . . . 454

17.6.5

TIM16 and TIM17 event generation register (TIM16_EGR and
TIM17_EGR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455

17.6.6

TIM16 and TIM17 capture/compare mode register 1 (TIM16_CCMR1
and TIM17_CCMR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456

17.6.7

TIM16 and TIM17 capture/compare enable register (TIM16_CCER
and TIM17_CCER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460

17.6.8

TIM16 and TIM17 counter (TIM16_CNT and TIM17_CNT) . . . . . . . . . 462

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17.6.9

TIM16 and TIM17 prescaler (TIM16_PSC and TIM17_PSC) . . . . . . . 462

17.6.10 TIM16 and TIM17 auto-reload register (TIM16_ARR and 
TIM17_ARR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 462
17.6.11 TIM16 and TIM17 repetition counter register (TIM16_RCR and
TIM17_RCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463
17.6.12 TIM16 and TIM17 capture/compare register 1 (TIM16_CCR1 and
TIM17_CCR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463
17.6.13 TIM16 and TIM17 break and dead-time register (TIM16_BDTR and
TIM17_BDTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 464
17.6.14 TIM16 and TIM17 DMA control register (TIM16_DCR and 
TIM17_DCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 466
17.6.15 TIM16 and TIM17 DMA address for full transfer (TIM16_DMAR and
TIM17_DMAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 466
17.6.16 TIM16 and TIM17 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 468

18

Infrared interface (IRTIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470

19

Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 471
19.1

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 471

19.2

IWDG main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 471

19.3

IWDG functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 471

19.4

20

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19.3.1

IWDG block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 471

19.3.2

Window option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 472

19.3.3

Hardware watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 473

19.3.4

Behavior in Stop and Standby modes . . . . . . . . . . . . . . . . . . . . . . . . . 473

19.3.5

Register access protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 473

19.3.6

Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 473

IWDG registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474
19.4.1

Key register (IWDG_KR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474

19.4.2

Prescaler register (IWDG_PR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 475

19.4.3

Reload register (IWDG_RLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476

19.4.4

Status register (IWDG_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477

19.4.5

Window register (IWDG_WINR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 478

19.4.6

IWDG register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 479

System window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . 480
20.1

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 480

20.2

WWDG main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 480

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20.3

20.4

21

WWDG functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 480
20.3.1

Enabling the watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 481

20.3.2

Controlling the downcounter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 481

20.3.3

Advanced watchdog interrupt feature . . . . . . . . . . . . . . . . . . . . . . . . . 481

20.3.4

How to program the watchdog timeout . . . . . . . . . . . . . . . . . . . . . . . . 482

20.3.5

Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 483

WWDG registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 483
20.4.1

Control register (WWDG_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 483

20.4.2

Configuration register (WWDG_CFR) . . . . . . . . . . . . . . . . . . . . . . . . . 484

20.4.3

Status register (WWDG_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 484

20.4.4

WWDG register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485

Real-time clock (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 486
21.1

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 486

21.2

RTC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 487

21.3

RTC implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 487

21.4

RTC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 488
21.4.1

RTC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 488

21.4.2

GPIOs controlled by the RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 490

21.4.3

Clock and prescalers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491

21.4.4

Real-time clock and calendar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492

21.4.5

Programmable alarm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492

21.4.6

Periodic auto-wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493

21.4.7

RTC initialization and configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 493

21.4.8

Reading the calendar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495

21.4.9

Resetting the RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496

21.4.10 RTC synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496
21.4.11 RTC reference clock detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 497
21.4.12 RTC smooth digital calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 498
21.4.13 Time-stamp function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500
21.4.14 Tamper detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500
21.4.15 Calibration clock output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502
21.4.16 Alarm output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502

21.5

RTC low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503

21.6

RTC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503

21.7

RTC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503

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21.7.1

RTC time register (RTC_TR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503

21.7.2

RTC date register (RTC_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504

21.7.3

RTC control register (RTC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506

21.7.4

RTC initialization and status register (RTC_ISR) . . . . . . . . . . . . . . . . . 509

21.7.5

RTC prescaler register (RTC_PRER) . . . . . . . . . . . . . . . . . . . . . . . . . 511

21.7.6

RTC wakeup timer register (RTC_WUTR) . . . . . . . . . . . . . . . . . . . . . . 512

21.7.7

RTC alarm A register (RTC_ALRMAR) . . . . . . . . . . . . . . . . . . . . . . . . 513

21.7.8

RTC write protection register (RTC_WPR) . . . . . . . . . . . . . . . . . . . . . 514

21.7.9

RTC sub second register (RTC_SSR) . . . . . . . . . . . . . . . . . . . . . . . . . 514

21.7.10 RTC shift control register (RTC_SHIFTR) . . . . . . . . . . . . . . . . . . . . . . 515
21.7.11 RTC timestamp time register (RTC_TSTR) . . . . . . . . . . . . . . . . . . . . . 516
21.7.12 RTC timestamp date register (RTC_TSDR) . . . . . . . . . . . . . . . . . . . . 517
21.7.13 RTC time-stamp sub second register (RTC_TSSSR) . . . . . . . . . . . . . 518
21.7.14 RTC calibration register (RTC_CALR) . . . . . . . . . . . . . . . . . . . . . . . . . 519
21.7.15 RTC tamper and alternate function configuration register
(RTC_TAFCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 520
21.7.16 RTC alarm A sub second register (RTC_ALRMASSR) . . . . . . . . . . . . 523
21.7.17 RTC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 523

22

Inter-integrated circuit (I2C) interface . . . . . . . . . . . . . . . . . . . . . . . . . 526
22.1

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 526

22.2

I2C main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 526

22.3

I2C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 527

22.4

I2C functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 527
22.4.1

I2C block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 528

22.4.2

I2C2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 529

22.4.3

I2C clock requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 529

22.4.4

Mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 530

22.4.5

I2C initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 531

22.4.6

Software reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 535

22.4.7

Data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 536

22.4.8

I2C slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 538

22.4.9

I2C master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 547

22.4.10 I2C_TIMINGR register configuration examples . . . . . . . . . . . . . . . . . . 559
22.4.11 SMBus specific features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 560
22.4.12 SMBus initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 563
22.4.13 SMBus: I2C_TIMEOUTR register configuration examples . . . . . . . . . 565

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22.4.14 SMBus slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 566
22.4.15 Error conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 573
22.4.16 DMA requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 575
22.4.17 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 576

22.5

I2C low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 577

22.6

I2C interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 577

22.7

I2C registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 578
22.7.1

Control register 1 (I2C_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 578

22.7.2

Control register 2 (I2C_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 581

22.7.3

Own address 1 register (I2C_OAR1) . . . . . . . . . . . . . . . . . . . . . . . . . . 584

22.7.4

Own address 2 register (I2C_OAR2) . . . . . . . . . . . . . . . . . . . . . . . . . . 585

22.7.5

Timing register (I2C_TIMINGR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 586

22.7.6

Timeout register (I2C_TIMEOUTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 587

22.7.7

Interrupt and status register (I2C_ISR) . . . . . . . . . . . . . . . . . . . . . . . . 588

22.7.8

Interrupt clear register (I2C_ICR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 590

22.7.9

PEC register (I2C_PECR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 591

22.7.10 Receive data register (I2C_RXDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 592
22.7.11 Transmit data register (I2C_TXDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 592
22.7.12 I2C register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 593

23

Universal synchronous asynchronous receiver
transmitter (USART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 595
23.1

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 595

23.2

USART main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 595

23.3

USART implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 597

23.4

USART functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 598
23.4.1

USART character description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 599

23.4.2

USART transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 600

23.4.3

USART receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 603

23.4.4

USART baud rate generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 609

23.4.5

Tolerance of the USART receiver to clock deviation . . . . . . . . . . . . . . 611

23.4.6

USART auto baud rate detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 612

23.4.7

Multiprocessor communication using USART . . . . . . . . . . . . . . . . . . . 612

23.4.8

USART parity control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 615

23.4.9

A.15.6: USART synchronous mode code exampleUSART synchronous
mode 615

23.4.10 USART Single-wire Half-duplex communication . . . . . . . . . . . . . . . . . 618

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23.4.11 USART continuous communication in DMA mode . . . . . . . . . . . . . . . 618
23.4.12 RS232 hardware flow control and RS485 driver enable
using USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 621

23.5

USART low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 623

23.6

USART interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 624

23.7

USART registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 625
23.7.1

Control register 1 (USART_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 625

23.7.2

Control register 2 (USART_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 628

23.7.3

Control register 3 (USART_CR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 630

23.7.4

Baud rate register (USART_BRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 633

23.7.5

Receiver timeout register (USART_RTOR) . . . . . . . . . . . . . . . . . . . . . 633

23.7.6

Request register (USART_RQR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 634

23.7.7

Interrupt and status register (USART_ISR) . . . . . . . . . . . . . . . . . . . . . 635

23.7.8

Interrupt flag clear register (USART_ICR) . . . . . . . . . . . . . . . . . . . . . . 638

23.7.9

Receive data register (USART_RDR) . . . . . . . . . . . . . . . . . . . . . . . . . 639

23.7.10 Transmit data register (USART_TDR) . . . . . . . . . . . . . . . . . . . . . . . . . 640
23.7.11 USART register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 640

24

Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 642
24.1

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 642

24.2

SPI main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 642

24.3

SPI implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 643

24.4

SPI functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 643
24.4.1

General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 643

24.4.2

Communications between one master and one slave . . . . . . . . . . . . . 644

24.4.3

Standard multi-slave communication . . . . . . . . . . . . . . . . . . . . . . . . . . 646

24.4.4

Multi-master communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 647

24.4.5

Slave select (NSS) pin management . . . . . . . . . . . . . . . . . . . . . . . . . . 648

24.4.6

Communication formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 649

24.4.7

Configuration of SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 651

24.4.8

Procedure for enabling SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 652

24.4.9

Data transmission and reception procedures . . . . . . . . . . . . . . . . . . . 652

24.4.10 SPI status flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 662
24.4.11 SPI error flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 663
24.4.12 NSS pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 664
24.4.13 TI mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 664
24.4.14 CRC calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 665
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24.5

SPI interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 667

24.6

SPI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 668
24.6.1

SPI control register 1 (SPIx_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 668

24.6.2

SPI control register 2 (SPIx_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 670

24.6.3

SPI status register (SPIx_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 673

24.6.4

SPI data register (SPIx_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 674

24.6.5

SPI CRC polynomial register (SPIx_CRCPR) . . . . . . . . . . . . . . . . . . . 674

24.6.6

SPI Rx CRC register (SPIx_RXCRCR) . . . . . . . . . . . . . . . . . . . . . . . . 675

24.6.7

SPI Tx CRC register (SPIx_TXCRCR) . . . . . . . . . . . . . . . . . . . . . . . . 675

24.6.8

SPI register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 676

Universal serial bus full-speed device interface (USB) . . . . . . . . . . . 677
25.1

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 677

25.2

USB main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 677

25.3

USB implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 677

25.4

USB functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 678
25.4.1

25.5

25.6

26

Description of USB blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 679

Programming considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 680
25.5.1

Generic USB device programming . . . . . . . . . . . . . . . . . . . . . . . . . . . 680

25.5.2

System and power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 681

25.5.3

Double-buffered endpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 686

25.5.4

Isochronous transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 688

25.5.5

Suspend/Resume events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 689

USB registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 692
25.6.1

Common registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 692

25.6.2

Buffer descriptor table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 705

25.6.3

USB register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 708

Debug support (DBG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 710
26.1

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 710

26.2

Reference ARM documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .711

26.3

Pinout and debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .711

26.4

26.3.1

SWD port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 712

26.3.2

SW-DP pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 712

26.3.3

Internal pull-up & pull-down on SWD pins . . . . . . . . . . . . . . . . . . . . . . 712

ID codes and locking mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 712

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26.4.1

26.5

SWD port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 714
26.5.1

SWD protocol introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 714

26.5.2

SWD protocol sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 714

26.5.3

SW-DP state machine (reset, idle states, ID code) . . . . . . . . . . . . . . . 715

26.5.4

DP and AP read/write accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 715

26.5.5

SW-DP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 717

26.5.6

SW-AP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 718

26.6

Core debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 718

26.7

BPU (Break Point Unit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 719
26.7.1

26.8

26.9

27

MCU device ID code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 713

BPU functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 719

DWT (Data Watchpoint) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 719
26.8.1

DWT functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 719

26.8.2

DWT Program Counter Sample Register . . . . . . . . . . . . . . . . . . . . . . 719

MCU debug component (DBGMCU) . . . . . . . . . . . . . . . . . . . . . . . . . . . 719
26.9.1

Debug support for low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . 720

26.9.2

Debug support for timers, watchdog and I2C . . . . . . . . . . . . . . . . . . . . 720

26.9.3

Debug MCU configuration register (DBGMCU_CR) . . . . . . . . . . . . . . 721

26.9.4

Debug MCU APB1 freeze register (DBGMCU_APB1_FZ) . . . . . . . . . 722

26.9.5

Debug MCU APB2 freeze register (DBGMCU_APB2_FZ) . . . . . . . . . 724

26.9.6

DBG register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 724

Device electronic signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 726
27.1

Memory size data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 726
27.1.1

Flash size data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 726

Appendix A Code examples. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 727

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A.1

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 727

A.2

Flash operation code example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 727
A.2.1

Flash memory unlocking sequence code . . . . . . . . . . . . . . . . . . . . . . . 727

A.2.2

Main Flash programming sequence code example . . . . . . . . . . . . . . . 727

A.2.3

Page erase sequence code example . . . . . . . . . . . . . . . . . . . . . . . . . . 728

A.2.4

Mass erase sequence code example . . . . . . . . . . . . . . . . . . . . . . . . . . 729

A.2.5

Option byte unlocking sequence code example . . . . . . . . . . . . . . . . . . 729

A.2.6

Option byte programming sequence code example . . . . . . . . . . . . . . . 730

A.2.7

Option byte erasing sequence code example. . . . . . . . . . . . . . . . . . . . 730

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A.3

A.4

A.5

Clock controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 731
A.3.1

HSE start sequence code example . . . . . . . . . . . . . . . . . . . . . . . . . . . 731

A.3.2

PLL configuration modification code example . . . . . . . . . . . . . . . . . . . 732

A.3.3

MCO selection code example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 732

A.3.4

Clock measurement configuration with TIM14 code example . . . . . . . 733

GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 734
A.4.1

Lock sequence code example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 734

A.4.2

Alternate function selection sequence code example. . . . . . . . . . . . . . 734

A.4.3

Analog GPIO configuration code example . . . . . . . . . . . . . . . . . . . . . . 735

DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 735
A.5.1

A.6

A.7

A.8

DMA Channel Configuration sequence code example . . . . . . . . . . . . . 735

Interrupts and event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 736
A.6.1

NVIC initialization example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 736

A.6.2

External interrupt selection code example . . . . . . . . . . . . . . . . . . . . . . 736

ADC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 737
A.7.1

ADC Calibration code example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 737

A.7.2

ADC enable sequence code example . . . . . . . . . . . . . . . . . . . . . . . . . 737

A.7.3

ADC disable sequence code example . . . . . . . . . . . . . . . . . . . . . . . . . 738

A.7.4

ADC Clock selection code example . . . . . . . . . . . . . . . . . . . . . . . . . . . 738

A.7.5

Single conversion sequence code example - Software trigger . . . . . . . 739

A.7.6

Continuous conversion sequence code example - Software trigger. . . 739

A.7.7

Single conversion sequence code example - Hardware trigger . . . . . . 740

A.7.8

Continuous conversion sequence code example - Hardware trigger . . 740

A.7.9

DMA one shot mode sequence code example . . . . . . . . . . . . . . . . . . . 741

A.7.10

DMA circular mode sequence code example . . . . . . . . . . . . . . . . . . . . 741

A.7.11

Wait mode sequence code example. . . . . . . . . . . . . . . . . . . . . . . . . . . 741

A.7.12

Auto Off and no wait mode sequence code example . . . . . . . . . . . . . . 742

A.7.13

Auto Off and wait mode sequence code example . . . . . . . . . . . . . . . . 742

A.7.14

Analog watchdog code example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 742

A.7.15

Temperature configuration code example. . . . . . . . . . . . . . . . . . . . . . . 743

A.7.16

Temperature computation code example . . . . . . . . . . . . . . . . . . . . . . . 743

Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 744
A.8.1

Upcounter on TI2 rising edge code example . . . . . . . . . . . . . . . . . . . . 744

A.8.2

Up counter on each 2 ETR rising edges code example . . . . . . . . . . . . 745

A.8.3

Input capture configuration code example . . . . . . . . . . . . . . . . . . . . . . 745

A.8.4

Input capture data management code example . . . . . . . . . . . . . . . . . . 746

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Contents

RM0360

A.9

A.10

A.11

A.12

22/779

A.8.5

PWM input configuration code example . . . . . . . . . . . . . . . . . . . . . . . . 747

A.8.6

PWM input with DMA configuration code example . . . . . . . . . . . . . . . . 747

A.8.7

Output compare configuration code example . . . . . . . . . . . . . . . . . . . . 748

A.8.8

Edge-aligned PWM configuration example. . . . . . . . . . . . . . . . . . . . . . 748

A.8.9

Center-aligned PWM configuration example . . . . . . . . . . . . . . . . . . . . 749

A.8.10

ETR configuration to clear OCxREF code example . . . . . . . . . . . . . . . 750

A.8.11

Encoder interface code example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 750

A.8.12

Reset mode code example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 751

A.8.13

Gated mode code example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 751

A.8.14

Trigger mode code example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 752

A.8.15

External clock mode 2 + trigger mode code example. . . . . . . . . . . . . . 752

A.8.16

One-Pulse mode code example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 753

A.8.17

Timer prescaling another timer code example . . . . . . . . . . . . . . . . . . . 753

A.8.18

Timer enabling another timer code example. . . . . . . . . . . . . . . . . . . . . 754

A.8.19

Master and slave synchronization code example . . . . . . . . . . . . . . . . . 755

A.8.20

Two timers synchronized by an external trigger code example . . . . . . 756

A.8.21

DMA burst feature code example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 757

IRTIM code example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 758
A.9.1

TIM16 and TIM17 configuration code example . . . . . . . . . . . . . . . . . . 758

A.9.2

IRQHandler for IRTIM code example . . . . . . . . . . . . . . . . . . . . . . . . . . 759

DBG code example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 760
A.10.1

DBG read device ID code example . . . . . . . . . . . . . . . . . . . . . . . . . . . 760

A.10.2

DBG debug in Low-power mode code example . . . . . . . . . . . . . . . . . . 760

I2C code example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 760
A.11.1

I2C configured in master mode to receive code example. . . . . . . . . . . 760

A.11.2

I2C configured in master mode to transmit code example . . . . . . . . . . 760

A.11.3

I2C configured in slave mode code example . . . . . . . . . . . . . . . . . . . . 761

A.11.4

I2C master transmitter code example . . . . . . . . . . . . . . . . . . . . . . . . . . 761

A.11.5

I2C master receiver code example . . . . . . . . . . . . . . . . . . . . . . . . . . . . 761

A.11.6

I2C slave transmitter code example . . . . . . . . . . . . . . . . . . . . . . . . . . . 762

A.11.7

I2C slave receiver code example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 762

A.11.8

I2C configured in master mode to transmit with DMA code example . . 762

A.11.9

I2C configured in slave mode to receive with DMA code example . . . . 763

IWDG code example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 763
A.12.1

IWDG configuration code example . . . . . . . . . . . . . . . . . . . . . . . . . . . . 763

A.12.2

IWDG configuration with window code example. . . . . . . . . . . . . . . . . . 764

DocID025023 Rev 4

RM0360

Contents

A.13

A.14

A.15

A.16

RTC code example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 764
A.13.1

RTC calendar configuration code example. . . . . . . . . . . . . . . . . . . . . . 764

A.13.2

RTC alarm configuration code example . . . . . . . . . . . . . . . . . . . . . . . . 765

A.13.3

RTC WUT configuration code example . . . . . . . . . . . . . . . . . . . . . . . . 765

A.13.4

RTC read calendar code example . . . . . . . . . . . . . . . . . . . . . . . . . . . . 765

A.13.5

RTC calibration code example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 766

A.13.6

RTC tamper and time stamp configuration code example . . . . . . . . . . 766

A.13.7

RTC tamper and time stamp code example . . . . . . . . . . . . . . . . . . . . . 767

A.13.8

RTC clock output code example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 767

SPI code example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 767
A.14.1

SPI master configuration code example . . . . . . . . . . . . . . . . . . . . . . . . 767

A.14.2

SPI slave configuration code example . . . . . . . . . . . . . . . . . . . . . . . . . 768

A.14.3

SPI full duplex communication code example . . . . . . . . . . . . . . . . . . . 768

A.14.4

SPI interrupt code example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 768

A.14.5

SPI master configuration with DMA code example. . . . . . . . . . . . . . . . 768

A.14.6

SPI slave configuration with DMA code example . . . . . . . . . . . . . . . . . 769

USART code example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 769
A.15.1

USART transmitter configuration code example. . . . . . . . . . . . . . . . . . 769

A.15.2

USART transmit byte code example. . . . . . . . . . . . . . . . . . . . . . . . . . . 769

A.15.3

USART transfer complete code example . . . . . . . . . . . . . . . . . . . . . . . 769

A.15.4

USART receiver configuration code example . . . . . . . . . . . . . . . . . . . . 770

A.15.5

USART receive byte code example . . . . . . . . . . . . . . . . . . . . . . . . . . . 770

A.15.6

USART synchronous mode code example . . . . . . . . . . . . . . . . . . . . . . 770

A.15.7

USART DMA code example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 771

A.15.8

USART hardware flow control code example . . . . . . . . . . . . . . . . . . . . 771

WWDG code example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 771
A.16.1

WWDG configuration code example. . . . . . . . . . . . . . . . . . . . . . . . . . . 771

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 772

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23

List of tables

RM0360

List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.

24/779

STM32F0x0 memory boundary addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
STM32F0x0 peripheral register boundary addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Boot modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Flash memory organization (STM32F030x4, STM32F030x6, STM32F070x6 and
STM32F030x8 devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Flash memory organization (STM32F070xB, STM32F030xC devices) . . . . . . . . . . . . . . . 47
Flash memory read protection status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Access status versus protection level and execution modes . . . . . . . . . . . . . . . . . . . . . . . 56
Flash interrupt request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Flash interface - register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Option byte format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Option byte organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Option byte map and ST production values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
CRC internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
CRC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Low-power mode summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Sleep-now . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Sleep-on-exit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Standby mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
PWR register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
RCC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Port bit configuration table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
GPIO register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
SYSCFG register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Programmable data width & endian behavior (when bits PINC = MINC = 1) . . . . . . . . . . 156
DMA interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Summary of the DMA requests for each channel
on STM32F030x4/6, STM32F070x6, STM32F070xB and STM32F030x8 devices . . . . . 159
Summary of the DMA requests for each channel on STM32F030xC devices . . . . . . . . . 160
DMA register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
DMA register map and reset values (registers available on STM32F070xB and
STM32F030xC
devices only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
DMA register map and reset values(register available on STM32F030xC
devices only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Vector table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
External interrupt/event controller register map and reset values. . . . . . . . . . . . . . . . . . . 180
ADC internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
ADC pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Latency between trigger and start of conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Configuring the trigger polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
External triggers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
tSAR timings depending on resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Analog watchdog comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
Analog watchdog channel selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
ADC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
ADC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220

DocID025023 Rev 4

RM0360
Table 44.
Table 45.
Table 46.
Table 47.
Table 48.
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
Table 62.
Table 63.
Table 64.
Table 65.
Table 66.
Table 67.
Table 68.
Table 69.
Table 70.
Table 71.
Table 72.
Table 73.
Table 74.
Table 75.
Table 76.
Table 77.
Table 78.
Table 79.
Table 80.
Table 81.
Table 82.
Table 83.
Table 84.
Table 85.
Table 86.
Table 87.
Table 88.
Table 89.
Table 90.
Table 91.

List of tables
Counting direction versus encoder signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
TIMx Internal trigger connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
Output control bits for complementary OCx and OCxN channels with
break feature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
TIM1 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
Counting direction versus encoder signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326
TIM3 internal trigger connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343
Output control bit for standard OCx channels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353
TIM3 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359
TIM6/TIM7 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373
Output control bit for standard OCx channels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392
TIM14 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395
TIMx Internal trigger connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432
Output control bits for complementary OCx and OCxN channels with break feature . . . . 442
TIM15 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 449
Output control bits for complementary OCx and OCxN channels with break feature . . . . 461
TIM16 and TIM17 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 468
IWDG register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 479
WWDG register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485
STM32F0x0 RTC implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 487
RTC pin PC13 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 490
LSE pin PC14 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491
LSE pin PC15 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491
Effect of low-power modes on RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503
Interrupt control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503
RTC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 523
STM32F0x0 I2C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 527
Comparison of analog vs. digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 531
I2C-SMBUS specification data setup and hold times . . . . . . . . . . . . . . . . . . . . . . . . . . . . 534
I2C configuration table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 538
I2C-SMBUS specification clock timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 549
Examples of timings settings for fI2CCLK = 8 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 559
Examples of timings settings for fI2CCLK = 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . 559
Examples of timings settings for fI2CCLK = 48 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . 560
SMBus timeout specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 562
SMBUS with PEC configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 564
Examples of TIMEOUTA settings for various I2CCLK frequencies
(max tTIMEOUT = 25 ms) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 565
Examples of TIMEOUTB settings for various I2CCLK frequencies . . . . . . . . . . . . . . . . . 565
Examples of TIMEOUTA settings for various I2CCLK frequencies
(max tIDLE = 50 µs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 566
low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 577
I2C Interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 577
I2C register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 593
STM32F0x0 USART implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 597
Noise detection from sampled data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 608
Error calculation for programmed baud rates at fCK = 48 MHz in both cases of
oversampling by 16 or by 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 610
Tolerance of the USART receiver when BRR [3:0] = 0000. . . . . . . . . . . . . . . . . . . . . . . . 611
Tolerance of the USART receiver when BRR [3:0] is different from 0000 . . . . . . . . . . . . 611
Frame formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 615
Effect of low-power modes on the USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 623

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26

List of tables
Table 92.
Table 93.
Table 94.
Table 95.
Table 96.
Table 97.
Table 98.
Table 99.
Table 100.
Table 101.
Table 102.
Table 103.
Table 104.
Table 105.
Table 106.
Table 107.
Table 108.
Table 109.
Table 110.
Table 111.
Table 112.
Table 113.
Table 114.
Table 115.
Table 116.
Table 117.

26/779

RM0360

USART interrupt requests. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 624
USART register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 640
STM32F0x0 SPI implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 643
SPI interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 667
SPI register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 676
STM32F0x0 USB implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 677
Double-buffering buffer flag definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 687
Bulk double-buffering memory buffers usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 687
Isochronous memory buffers usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 689
Resume event detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 691
Reception status encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 703
Endpoint type encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 704
Endpoint kind meaning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 704
Transmission status encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 704
Definition of allocated buffer memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 707
USB register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 708
SW debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 712
DEV_ID and REV_ID field values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 713
Packet request (8-bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 714
ACK response (3 bits). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 715
DATA transfer (33 bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 715
SW-DP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 717
32-bit debug port registers addressed through the shifted value A[3:2] . . . . . . . . . . . . . . 718
Core debug registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 718
DBG register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 725
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 772

DocID025023 Rev 4

RM0360

List of figures

List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Figure 40.
Figure 41.
Figure 42.
Figure 43.
Figure 44.
Figure 45.
Figure 46.
Figure 47.

System architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Programming procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Flash memory Page Erase procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Flash memory Mass Erase procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
CRC calculation unit block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Power supply overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Power on reset/power down reset waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Simplified diagram of the reset circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Clock tree (STM32F030x4, STM32F030x6 and STM32F030x8 devices) . . . . . . . . . . . . . 90
Clock tree (STM32F070x6, STM32F070xB and STM32F030xC). . . . . . . . . . . . . . . . . . . . 91
HSE/ LSE clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Frequency measurement with TIM14 in capture mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Basic structure of an I/O port bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Input floating/pull up/pull down configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Alternate function configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
High impedance-analog configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
DMA block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
DMA request mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Extended interrupts and events controller (EXTI) block diagram . . . . . . . . . . . . . . . . . . . 173
External interrupt/event GPIO mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
ADC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
ADC calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Enabling/disabling the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
ADC clock scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Analog to digital conversion time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
ADC conversion timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
Stopping an ongoing conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
Single conversions of a sequence, software trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Continuous conversion of a sequence, software trigger . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Single conversions of a sequence, hardware trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Continuous conversions of a sequence, hardware trigger . . . . . . . . . . . . . . . . . . . . . . . . 197
Data alignment and resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Example of overrun (OVR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Wait mode conversion (continuous mode, software trigger). . . . . . . . . . . . . . . . . . . . . . . 201
Behavior with WAIT=0, AUTOFF=1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Behavior with WAIT=1, AUTOFF=1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Analog watchdog guarded area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
Advanced-control timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . . 224
Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . . 224
Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
Counter timing diagram, update event when ARPE=0 
(TIMx_ARR not preloaded) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228

DocID025023 Rev 4

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32

List of figures
Figure 48.
Figure 49.
Figure 50.
Figure 51.
Figure 52.
Figure 53.
Figure 54.
Figure 55.
Figure 56.
Figure 57.
Figure 58.
Figure 59.
Figure 60.
Figure 61.
Figure 62.
Figure 63.
Figure 64.
Figure 65.
Figure 66.
Figure 67.
Figure 68.
Figure 69.
Figure 70.
Figure 71.
Figure 72.
Figure 73.
Figure 74.
Figure 75.
Figure 76.
Figure 77.
Figure 78.
Figure 79.
Figure 80.
Figure 81.
Figure 82.
Figure 83.
Figure 84.
Figure 85.
Figure 86.
Figure 87.
Figure 88.
Figure 89.
Figure 90.
Figure 91.
Figure 92.
Figure 93.
Figure 94.
Figure 95.
Figure 96.

28/779

RM0360

Counter timing diagram, update event when ARPE=1 
(TIMx_ARR preloaded) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
Counter timing diagram, update event when repetition counter is not used . . . . . . . . . . . 231
Counter timing diagram, internal clock divided by 1, TIMx_ARR = 0x6 . . . . . . . . . . . . . . 232
Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . . . . . . . . . . . 233
Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
Counter timing diagram, update event with ARPE=1 (counter underflow) . . . . . . . . . . . . 234
Counter timing diagram, Update event with ARPE=1 (counter overflow) . . . . . . . . . . . . . 235
Update rate examples depending on mode and TIMx_RCR register settings . . . . . . . . . 236
Control circuit in normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . 237
TI2 external clock connection example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
Control circuit in external clock mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
External trigger input block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
Control circuit in external clock mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
Capture/compare channel (example: channel 1 input stage) . . . . . . . . . . . . . . . . . . . . . . 241
Capture/compare channel 1 main circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
Output stage of capture/compare channel (channel 1 to 3) . . . . . . . . . . . . . . . . . . . . . . . 242
Output stage of capture/compare channel (channel 4). . . . . . . . . . . . . . . . . . . . . . . . . . . 242
PWM input mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
Output compare mode, toggle on OC1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
Edge-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
Center-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
Complementary output with dead-time insertion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
Dead-time waveforms with delay greater than the negative pulse. . . . . . . . . . . . . . . . . . 251
Dead-time waveforms with delay greater than the positive pulse. . . . . . . . . . . . . . . . . . . 251
Output behavior in response to a break . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
Clearing TIMx OCxREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
6-step generation, COM example (OSSR=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
Example of one pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
Example of counter operation in encoder interface mode. . . . . . . . . . . . . . . . . . . . . . . . . 261
Example of encoder interface mode with TI1FP1 polarity inverted. . . . . . . . . . . . . . . . . . 261
Example of hall sensor interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
Control circuit in reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
Control circuit in gated mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
Control circuit in trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
Control circuit in external clock mode 2 + trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . 267
General-purpose timer block diagram (TIM3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . . 298
Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . . 299
Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300
Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300
Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301
Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301
Counter timing diagram, Update event when ARPE=0 
(TIMx_ARR not preloaded) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302
Counter timing diagram, Update event when ARPE=1 
(TIMx_ARR preloaded) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302

DocID025023 Rev 4

RM0360
Figure 97.
Figure 98.
Figure 99.
Figure 100.
Figure 101.
Figure 102.
Figure 103.
Figure 104.
Figure 105.
Figure 106.
Figure 107.
Figure 108.
Figure 109.
Figure 110.
Figure 111.
Figure 112.
Figure 113.
Figure 114.
Figure 115.
Figure 116.
Figure 117.
Figure 118.
Figure 119.
Figure 120.
Figure 121.
Figure 122.
Figure 123.
Figure 124.
Figure 125.
Figure 126.
Figure 127.
Figure 128.
Figure 129.
Figure 130.
Figure 131.
Figure 132.
Figure 133.
Figure 134.
Figure 135.
Figure 136.
Figure 137.
Figure 138.
Figure 139.
Figure 140.
Figure 141.
Figure 142.
Figure 143.
Figure 144.
Figure 145.
Figure 146.

List of figures
Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304
Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304
Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305
Counter timing diagram, Update event when repetition counter is not used . . . . . . . . . . 305
Counter timing diagram, internal clock divided by 1, TIMx_ARR=0x6 . . . . . . . . . . . . . . . 307
Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307
Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . . . . . . . . . . . 308
Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308
Counter timing diagram, Update event with ARPE=1 (counter underflow). . . . . . . . . . . . 309
Counter timing diagram, Update event with ARPE=1 (counter overflow) . . . . . . . . . . . . . 309
Control circuit in normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . 310
TI2 external clock connection example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311
Control circuit in external clock mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312
External trigger input block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312
Control circuit in external clock mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313
Capture/compare channel (example: channel 1 input stage) . . . . . . . . . . . . . . . . . . . . . . 314
Capture/compare channel 1 main circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314
Output stage of capture/compare channel (channel 1). . . . . . . . . . . . . . . . . . . . . . . . . . . 315
PWM input mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317
Output compare mode, toggle on OC1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319
Edge-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320
Center-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322
Example of one-pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323
Clearing TIMx OCxREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325
Example of counter operation in encoder interface mode . . . . . . . . . . . . . . . . . . . . . . . . 327
Example of encoder interface mode with TI1FP1 polarity inverted . . . . . . . . . . . . . . . . . 327
Control circuit in reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328
Control circuit in gated mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329
Control circuit in trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330
Control circuit in external clock mode 2 + trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . 331
Master/Slave timer example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332
Gating timer 3 with OC1REF of timer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333
Gating timer 3 with Enable of timer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334
Triggering timer 3 with update of timer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335
Triggering timer 3 with Enable of timer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336
Triggering timer 1 and 3 with timer 1 TI1 input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337
Basic timer block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361
Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . . 363
Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . . 363
Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364
Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365
Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365
Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366
Counter timing diagram, update event when ARPE = 0 
(TIMx_ARR not preloaded) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366
Counter timing diagram, update event when ARPE=1 
(TIMx_ARR preloaded) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367
Control circuit in normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . 368
General-purpose timer block diagram (TIM14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375
Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . . 376
Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . . 376

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32

List of figures
Figure 147.
Figure 148.
Figure 149.
Figure 150.
Figure 151.
Figure 152.
Figure 153.
Figure 154.
Figure 155.
Figure 156.
Figure 157.
Figure 158.
Figure 159.
Figure 160.
Figure 161.
Figure 162.
Figure 163.
Figure 164.
Figure 165.
Figure 166.
Figure 167.
Figure 168.
Figure 169.
Figure 170.
Figure 171.
Figure 172.
Figure 173.
Figure 174.
Figure 175.
Figure 176.
Figure 177.
Figure 178.
Figure 179.
Figure 180.
Figure 181.
Figure 182.
Figure 183.
Figure 184.
Figure 185.
Figure 186.
Figure 187.
Figure 188.
Figure 189.
Figure 190.
Figure 191.
Figure 192.
Figure 193.
Figure 194.

30/779

RM0360

Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377
Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378
Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378
Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378
Counter timing diagram, update event when ARPE=0 
(TIMx_ARR not preloaded) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379
Counter timing diagram, update event when ARPE=1 
(TIMx_ARR preloaded) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379
Control circuit in normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . 380
Capture/compare channel (example: channel 1 input stage) . . . . . . . . . . . . . . . . . . . . . . 380
Capture/compare channel 1 main circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381
Output stage of capture/compare channel (channel 1). . . . . . . . . . . . . . . . . . . . . . . . . . . 381
Output compare mode, toggle on OC1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384
Edge-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385
TIM15 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398
TIM16 and TIM17 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400
Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . . 402
Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . . 402
Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404
Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405
Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405
Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406
Counter timing diagram, update event when ARPE=0 
(TIMx_ARR not preloaded) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406
Counter timing diagram, update event when ARPE=1 
(TIMx_ARR preloaded) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407
Update rate examples depending on mode and TIMx_RCR register settings . . . . . . . . . 408
Control circuit in normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . 409
TI2 external clock connection example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409
Control circuit in external clock mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410
Capture/compare channel (example: channel 1 input stage) . . . . . . . . . . . . . . . . . . . . . . 411
Capture/compare channel 1 main circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412
Output stage of capture/compare channel (channel 1). . . . . . . . . . . . . . . . . . . . . . . . . . . 412
Output stage of capture/compare channel (channel 2 for TIM15) . . . . . . . . . . . . . . . . . . 413
PWM input mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415
Output compare mode, toggle on OC1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417
Edge-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418
Complementary output with dead-time insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419
Dead-time waveforms with delay greater than the negative pulse . . . . . . . . . . . . . . . . . . 420
Dead-time waveforms with delay greater than the positive pulse. . . . . . . . . . . . . . . . . . . 420
Output behavior in response to a break . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423
Example of One-pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424
Control circuit in reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426
Control circuit in gated mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 427
Control circuit in trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 428
IR internal hardware connections with TIM16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470
Independent watchdog block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 471
Watchdog block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 481
Window watchdog timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 482
RTC block diagram in STM32F030x4/6, STM32F070x6 and STM32F030x8 devices . 488
RTC block diagram for STM32F070xB and STM32F030xC devices . . . . . . . . . . . . . . . . 489
I2C block diagram
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 528

DocID025023 Rev 4

RM0360
Figure 195.
Figure 196.
Figure 197.
Figure 198.
Figure 199.
Figure 200.
Figure 201.
Figure 202.
Figure 203.
Figure 204.
Figure 205.
Figure 206.
Figure 207.
Figure 208.
Figure 209.
Figure 210.
Figure 211.
Figure 212.
Figure 213.
Figure 214.
Figure 215.
Figure 216.
Figure 217.
Figure 218.
Figure 219.
Figure 220.
Figure 221.
Figure 222.
Figure 223.
Figure 224.
Figure 225.
Figure 226.
Figure 227.
Figure 228.
Figure 229.
Figure 230.
Figure 231.
Figure 232.
Figure 233.
Figure 234.
Figure 235.
Figure 236.
Figure 237.
Figure 238.
Figure 239.
Figure 240.
Figure 241.
Figure 242.
Figure 243.
Figure 244.
Figure 245.
Figure 246.

List of figures
I2C2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 529
I2C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 530
Setup and hold timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 532
I2C initialization flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 535
Data reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 536
Data transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537
Slave initialization flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 541
Transfer sequence flowchart for I2C slave transmitter, NOSTRETCH=0. . . . . . . . . . . . . 542
Transfer sequence flowchart for I2C slave transmitter, NOSTRETCH=1. . . . . . . . . . . . . 543
Transfer bus diagrams for I2C slave transmitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 544
Transfer sequence flowchart for slave receiver with NOSTRETCH=0 . . . . . . . . . . . . . . . 545
Transfer sequence flowchart for slave receiver with NOSTRETCH=1 . . . . . . . . . . . . . . . 546
Transfer bus diagrams for I2C slave receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 546
Master clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 548
Master initialization flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 550
10-bit address read access with HEAD10R=0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 550
10-bit address read access with HEAD10R=1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 551
Transfer sequence flowchart for I2C master transmitter for N≤255 bytes . . . . . . . . . . . . 552
Transfer sequence flowchart for I2C master transmitter for N>255 bytes . . . . . . . . . . . . 553
Transfer bus diagrams for I2C master transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 554
Transfer sequence flowchart for I2C master receiver for N≤255 bytes. . . . . . . . . . . . . . . 556
Transfer sequence flowchart for I2C master receiver for N >255 bytes . . . . . . . . . . . . . . 557
Transfer bus diagrams for I2C master receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 558
Timeout intervals for tLOW:SEXT, tLOW:MEXT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 563
Transfer sequence flowchart for SMBus slave transmitter N bytes + PEC. . . . . . . . . . . . 567
Transfer bus diagrams for SMBus slave transmitter (SBC=1) . . . . . . . . . . . . . . . . . . . . . 567
Transfer sequence flowchart for SMBus slave receiver N Bytes + PEC . . . . . . . . . . . . . 569
Bus transfer diagrams for SMBus slave receiver (SBC=1) . . . . . . . . . . . . . . . . . . . . . . . 570
Bus transfer diagrams for SMBus master transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 571
Bus transfer diagrams for SMBus master receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 573
I2C interrupt mapping diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 578
USART block diagram
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 599
Word length programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 600
Configurable stop bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 601
TC/TXE behavior when transmitting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 603
Start bit detection when oversampling by 16 or 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 604
Data sampling when oversampling by 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 607
Data sampling when oversampling by 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 608
Mute mode using Idle line detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 613
Mute mode using address mark detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 614
USART example of synchronous transmission. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 616
USART data clock timing diagram (M=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 617
USART data clock timing diagram (M=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 617
RX data setup/hold time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 618
Transmission using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 620
Reception using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 621
Hardware flow control between 2 USARTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 621
RS232 RTS flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 622
RS232 CTS flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 623
USART interrupt mapping diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 624
SPI block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 643
Full-duplex single master/ single slave application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 644

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List of figures

RM0360

Figure 247. Half-duplex single master/ single slave application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 645
Figure 248. Simplex single master/single slave application (master in transmit-only/
slave in receive-only mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 646
Figure 249. Master and three independent slaves. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 647
Figure 250. Multi-master application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 648
Figure 251. Hardware/software slave select management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 649
Figure 252. Data clock timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 650
Figure 253. Data alignment when data length is not equal to 8-bit or 16-bit . . . . . . . . . . . . . . . . . . . . 651
Figure 254. Packing data in FIFO for transmission and reception . . . . . . . . . . . . . . . . . . . . . . . . . . . 655
Figure 255. Master full-duplex communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 658
Figure 256. Slave full-duplex communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 659
Figure 257. Master full-duplex communication with CRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 660
Figure 258. Master full-duplex communication in packed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 661
Figure 259. NSSP pulse generation in Motorola SPI master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 664
Figure 260. TI mode transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 665
Figure 261. USB peripheral block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 678
Figure 262. Packet buffer areas with examples of buffer description table locations . . . . . . . . . . . . . 682
Figure 263. Block diagram of STM32F0x0 MCU and ARM® Cortex®-M0-level debug support . . . . . 710

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Documentation conventions

1

Documentation conventions

1.1

List of abbreviations for registers
The following abbreviations are used in register descriptions:

read/write (rw)

Software can read and write to this bit.

read-only (r)

Software can only read this bit.

write-only (w)

Software can only write to this bit. Reading this bit returns the reset value.

read/clear (rc_w1) Software can read as well as clear this bit by writing 1. Writing ‘0’ has no effect on the
bit value.
read/clear (rc_w0) Software can read as well as clear this bit by writing 0. Writing ‘1’ has no effect on the
bit value.
read/clear by read Software can read this bit. Reading this bit automatically clears it to ‘0’. Writing this bit
(rc_r)
has no effect on the bit value.
read/set (rs)

Software can read as well as set this bit. Writing ‘0’ has no effect on the bit value.

Reserved (Res.)

Reserved bit, must be kept at reset value.

1.2

Glossary
This section gives a brief definition of acronyms and abbreviations used in this document:

1.3



Word: data of 32-bit length.



Half-word: data of 16-bit length.



Byte: data of 8-bit length.



SWD-DP (SWD DEBUG PORT): SWD-DP provides a 2-pin (clock and data) interface
based on the Serial Wire Debug (SWD) protocol. Please refer to the ARM® Cortex®-M0
technical reference manual.



IAP (in-application programming): IAP is the ability to re-program the Flash memory
of a microcontroller while the user program is running.



ICP (in-circuit programming): ICP is the ability to program the Flash memory of a
microcontroller using the JTAG protocol, the SWD protocol or the bootloader while the
device is mounted on the user application board.



Option bytes: product configuration bits stored in the Flash memory.



OBL: option byte loader.



AHB: advanced high-performance bus.



APB: advanced peripheral bus.

Peripheral availability
For peripheral availability and number across all sales types, please refer to the particular
device datasheet.

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System and memory overview

RM0360

2

System and memory overview

2.1

System architecture
The main system consists of:




Two masters:
–

ARM® Cortex®-M0 core

–

General-purpose DMA

Four slaves:
–

Internal SRAM

–

Internal Flash memory

–

AHB1 with AHB to APB bridge which connects all the APB peripherals

–

AHB2 dedicated to GPIO ports

These are interconnected using a multilayer AHB bus architecture as shown in Figure 1:
Figure 1. System architecture

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System bus
This bus connects the system bus of the ARM® Cortex®-M0 core (peripherals bus) to a
BusMatrix which manages the arbitration between the core and the DMA.

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System and memory overview

DMA bus
This bus connects the AHB master interface of the DMA to the BusMatrix which manages
the access of CPU and DMA to SRAM, Flash memory and peripherals.

BusMatrix
The BusMatrix manages the access arbitration between the core system bus and the DMA
master bus. The arbitration uses a Round Robin algorithm. The BusMatrix is composed of
two masters (CPU, DMA) and four slaves (FLITF, SRAM, AHB1 with AHB to APB bridge
and AHB2).
AHB peripherals are connected on system bus through a BusMatrix to allow DMA access.

AHB to APB bridge (APB)
The AHB to APB bridge provides full synchronous connections between the AHB and the
APB bus.
Refer to Section 2.2.2: Memory map and register boundary addresses for the address
mapping of the peripherals connected to this bridge.
After each device reset, all peripheral clocks are disabled (except for the SRAM and Flash).
Before using a peripheral you have to enable its clock in the RCC_AHBENR,
RCC_APB2ENR or RCC_APB1ENR register.
Note:

When a 16- or 8-bit access is performed on an APB register, the access is transformed into
a 32-bit access: the bridge duplicates the 16- or 8-bit data to feed the 32-bit vector.

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2.2

Memory organization

2.2.1

Introduction
Program memory, data memory, registers and I/O ports are organized within the same linear
4-Gbyte address space.
The bytes are coded in memory in Little Endian format. The lowest numbered byte in a word
is considered the word’s least significant byte and the highest numbered byte the most
significant.
The addressable memory space is divided into 8 main blocks, of 512 Mbytes each.
Figure 2. Memory map
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All the memory areas that are not allocated to on-chip memories and peripherals are
considered “Reserved”. For the detailed mapping of available memory and register areas,
please refer to Memory map and register boundary addresses and peripheral sections.

2.2.2

Memory map and register boundary addresses
See the datasheet corresponding to your device for a comprehensive diagram of the
memory map.
The following table gives the boundary addresses of the peripherals available in the
devices.
Table 1. STM32F0x0 memory boundary addresses

Device


STM32F030x4,
STM32F030x6


STM32F070x6

Boundary address

Size

Memory Area

0x2000 1000 - 0x3FFF FFFF

~512 MB

Reserved

0x2000 0000 - 0x2000 0FFF

4 KB

SRAM

Register description
Section 2.3 on page 41

0x1FFF FC00 - 0x1FFF FFFF 1 KB

Reserved

0x1FFF F800 - 0x1FFF FBFF 1 KB

Option bytes

0x1FFF EC00 - 0x1FFF F7FF 3 KB

System memory

-

0x0800 8000 - 0x1FFF EBFF

~384 MB

Reserved

-

0x0800 0000 - 0x0800 7FFF

32 KB(1)

Main Flash memory

0x0000 8000 - 0x07FF FFFF

~128 MB

Reserved

-

Main Flash memory,
system memory or SRAM
depending on BOOT
configuration

-

-

(1)

0x0000 0000 - 0x0000 7FFF

32 KB

0x2000 1800 - 0x3FFF FFFF

~512 MB

Reserved

0x2000 0000 - 0x2000 17FF

6 KB

SRAM

Section 4 on page 65

Section 3 on page 45

Section 2.3 on page 41

0x1FFF FC00 - 0x1FFF FFFF 1 KB

Reserved

0x1FFF F800 - 0x1FFF FBFF 1 KB

Option bytes

0x1FFF C400 - 0x1FFF F7FF 13 KB

System memory

-

0x0801 8000- 0x1FFF C7FF

~384 MB

Reserved

-

0x0800 0000 - 0x0801 7FFF

32 KB

Main Flash memory

0x0001 8000 - 0x07FF FFFF

~128 MB

Reserved

-

32 KB

Main Flash memory,
system memory or SRAM
depending on BOOT
configuration

-

0x0000 0000 - 0x0000 7FFF

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Section 3 on page 45

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RM0360
Table 1. STM32F0x0 memory boundary addresses (continued)
Device


STM32F030x8


STM32F070xB


STM32F030xC

Boundary address

Size

Memory Area

0x2000 2000 - 0x3FFF FFFF

~512 MB

Reserved

0x2000 0000 - 0x2000 1FFF

8 KB

SRAM

Section 2.3 on page 41

0x1FFF FC00 - 0x1FFF FFFF 1 KB

Reserved

0x1FFF F800 - 0x1FFF FBFF 1 KB

Option bytes

0x1FFF EC00 - 0x1FFF F7FF 3 KB

System memory

-

0x0801 0000 - 0x1FFF EBFF

~384 MB

Reserved

-

0x0800 0000 - 0x0800 FFFF

64 KB

Main Flash memory

0x0001 0000 - 0x07FF FFFF

~128 MB

Reserved

-

0x0000 0000 - 0x0000 FFFF

64 KB

Main Flash memory,
system memory or SRAM
depending on BOOT
configuration

-

0x2000 4000 - 0x3FFF FFFF

~512 MB

Reserved

-

0x2000 0000 - 0x2000 3FFF

16 KB

SRAM

Section 2.3 on page 41

0x1FFF F800 - 0x1FFF FFFF 2 KB

Option bytes

Section 4 on page 65

0x1FFF C800 - 0x1FFF F7FF 12 KB

System memory

-

0x0802 0000 - 0x1FFF C7FF

~384 MB

Reserved

-

0x0800 0000 - 0x0801 FFFF

128 KB

Main Flash memory

0x0002 0000 - 0x07FF FFFF

~128 MB

Reserved

-

0x0000 0000 - 0x0001 FFFF

128 KB

Main Flash memory,
system memory or SRAM
depending on BOOT
configuration

-

0x2000 8000 - 0x3FFF FFFF

~512 MB

Reserved

-

0x2000 0000 - 0x2000 7FFF

32 KB

SRAM

Section 2.3 on page 41

0x1FFF F800 - 0x1FFF FFFF 2 KB

Option bytes

Section 4 on page 65

0x1FFF D800 - 0x1FFF F7FF 8 KB

System memory

-

0x0804 0000 - 0x1FFF D7FF

~384 MB

Reserved

-

0x0800 0000 - 0x0803 FFFF

256 KB

Main Flash memory

0x0004 0000 - 0x07FF FFFF

~128 MB

Reserved

-

256 KB

Main Flash memory,
system memory or SRAM
depending on BOOT
configuration

-

0x0000 0000 - 0x0003 FFFF

1. Limited to 16 KB on STM32F030x4 devices.

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Register description

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Section 4 on page 65

Section 3 on page 45

Section 3 on page 45

Section 3 on page 45

RM0360
Table 2. STM32F0x0 peripheral register boundary addresses
Bus

Boundary address

-

0xE000 0000 - 0xE00F FFFF

1MB

Cortex®-M0 internal
peripherals

-

-

0x4800 1800 - 0x5FFF FFFF

~384 MB

Reserved

-

0x4800 1400 - 0x4800 17FF

1KB

GPIOF

0x4800 1000 - 0x4800 13FF

1KB

Reserved

0x4800 0C00 - 0x4800 0FFF

1KB

GPIOD

Section 8.4.11 on page 141

0x4800 0800 - 0x4800 0BFF

1KB

GPIOC

Section 8.4.11 on page 141

0x4800 0400 - 0x4800 07FF

1KB

GPIOB

Section 8.4.11 on page 141

0x4800 0000 - 0x4800 03FF

1KB

GPIOA

Section 8.4.11 on page 141

0x4002 4400 - 0x47FF FFFF

~128 MB

Reserved

-

0x4002 3400 - 0x4002 43FF

4 KB

Reserved

-

0x4002 3000 - 0x4002 33FF

1 KB

CRC

0x4002 2400 - 0x4002 2FFF

3 KB

Reserved

0x4002 2000 - 0x4002 23FF

1 KB

FLASH interface

0x4002 1400 - 0x4002 1FFF

3 KB

Reserved

0x4002 1000 - 0x4002 13FF

1 KB

RCC

0x4002 0400 - 0x4002 0FFF

3 KB

Reserved

0x4002 0000 - 0x4002 03FF

1 KB

DMA

0x4001 8000 - 0x4001 FFFF

32 KB

Reserved

AHB2

-

AHB1

-

Size

Peripheral

DocID025023 Rev 4

Peripheral register map

Section 8.4.11 on page 141
-

Section 5.4.5 on page 74
Section 3.5.9 on page 64
Section 7.4.15 on page 125
Section 10.4.8 on page 168
-

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Table 2. STM32F0x0 peripheral register boundary addresses (continued)
Bus

APB

-

40/779

Boundary address

Size

Peripheral

Peripheral register map

0x4001 5C00 - 0x4001 7FFF

9 KB

Reserved

-

0x4001 5800 - 0x4001 5BFF

1 KB

DBGMCU

-

0x4001 4C00 - 0x4001 57FF

3 KB

Reserved

-

0x4001 4800 - 0x4001 4BFF

1 KB

TIM17

Section 17.6.16 on page 468

0x4001 4400 - 0x4001 47FF

1 KB

TIM16

Section 17.6.16 on page 468

0x4001 4000 - 0x4001 43FF

1 KB

TIM15

Section 17.5.18 on page 449

0x4001 3C00 - 0x4001 3FFF

1 KB

Reserved

0x4001 3800 - 0x4001 3BFF

1 KB

USART1

0x4001 3400 - 0x4001 37FF

1 KB

Reserved

0x4001 3000 - 0x4001 33FF

1 KB

SPI1

Section 24.6.8 on page 676

0x4001 2C00 - 0x4001 2FFF

1 KB

TIM1

Section 13.4.21 on page 294

0x4001 2800 - 0x4001 2BFF

1 KB

Reserved

0x4001 2400 - 0x4001 27FF

1 KB

ADC

0x4001 1800 - 0x4001 23FF

4 KB

Reserved

0x4001 1400 - 0x4001 17FF

1 KB

USART6

0x4001 0800 - 0x4001 23FF

7 KB

Reserved

0x4001 0400 - 0x4001 07FF

1 KB

EXTI

Section 11.3.7 on page 180

0x4001 0000 - 0x4001 03FF

1 KB

SYSCFG

Section 9.1.7 on page 151

0x4000 8000 - 0x4000 FFFF

32 KB

Reserved

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Section 23.7.11 on page 640
-

Section 12.11.11 on page 220
Section 23.7.11 on page 640
-

-

RM0360
Table 2. STM32F0x0 peripheral register boundary addresses (continued)
Bus

APB

2.3

Boundary address

Size

Peripheral

Peripheral register map

0x4000 7400 - 0x4000 7FFF

3 KB

Reserved

-

0x4000 7000 - 0x4000 73FF

1 KB

PWR

0x4000 63FF - 0x4000 6FFF

3 KB

Reserved

0x4000 6000 - 0x4000 63FF

1 KB

USB/SRAM

Section 25.6.3 on page 708

0x4000 5C00 - 0x4000 5FFF

1 KB

USB

Section 25.6.3 on page 708

0x4000 5800 - 0x4000 5BFF

1 KB

I2C2

Section 22.7.12 on page 593

0x4000 5400 - 0x4000 57FF

1 KB

I2C1

Section 22.7.12 on page 593

0x4000 5000 - 0x4000 53FF

1 KB

USART5

Section 23.7.11 on page 640

0x4000 4C00 - 0x4000 4FFF

1 KB

USART4

Section 23.7.11 on page 640

0x4000 4800 - 0x4000 4BFF

1 KB

USART3

Section 23.7.11 on page 640

0x4000 4400 - 0x4000 47FF

1 KB

USART2

Section 23.7.11 on page 640

0x4000 3C00 - 0x4000 43FF

2 KB

Reserved

0x4000 3800 - 0x4000 3BFF

1 KB

SPI2

0x4000 3400 - 0x4000 37FF

1 KB

Reserved

0x4000 3000 - 0x4000 33FF

1 KB

IWDG

Section 19.4.6 on page 479

0x4000 2C00 - 0x4000 2FFF

1 KB

WWDG

Section 20.4.4 on page 485

0x4000 2800 - 0x4000 2BFF

1 KB

RTC

Section 21.7.17 on page 523

0x4000 2400 - 0x4000 27FF

1 KB

Reserved

0x4000 2000 - 0x4000 23FF

1 KB

TIM14

0x4000 1800 - 0x4000 1FFF

2 KB

Reserved

0x4000 1400 - 0x4000 17FF

1 KB

TIM7

Section 15.4.8 on page 373

0x4000 1000 - 0x4000 13FF

1 KB

TIM6

Section 15.4.8 on page 373

0x4000 0800 - 0x4000 0FFF

2 KB

Reserved

0x4000 0400 - 0x4000 07FF

1 KB

TIM3

0x4000 0000 - 0x4000 03FF

1 KB

Reserved

Section 6.4.3 on page 86
-

Section 24.6.8 on page 676
-

Section 16.4.12 on page 395
-

Section 14.4.19 on page 359
-

Embedded SRAM
STM32F030x4 and STM32F030x6 devices feature 4 Kbytes of static SRAM. STM32F030x8
devices feature 8 Kbytes of static SRAM. STM32F030xC devices feature 32 Kbytes of static
SRAM. STM32F070x6 devices feature 6 Kbytes of static SRAM. STM32F070xB devices
feature 16 Kbytes of static SRAM.
This RAM can be accessed as bytes, half-words (16 bits) or full words (32 bits). This
memory can be addressed at maximum system clock frequency without wait state and thus
by both CPU and DMA.
Parity check

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The user can enable the parity check using the option bit RAM_PARITY_CHECK in the user
option byte (refer to Section 4: Option bytes).
The data bus width is 36 bits because 4 bits are available for parity check (1 bit per byte) in
order to increase memory robustness, as required for instance by Class B or SIL norms.
The parity bits are computed and stored when writing into the SRAM. Then, they are
automatically checked when reading. If one bit fails, an NMI is generated. The same error
can also be linked to the BRK_IN Break input of TIM1/15/16/17, with the
SRAM_PARITY_LOCK control bit in the SYSCFG configuration register 2
(SYSCFG_CFGR2). The SRAM Parity Error flag (SRAM_PEF) is available in the SYSCFG
configuration register 2 (SYSCFG_CFGR2).
Note:

When enabling the RAM parity check, it is advised to initialize by software the whole RAM
memory at the beginning of the code, to avoid getting parity errors when reading noninitialized locations.

2.4

Flash memory overview
The Flash memory is composed of two distinct physical areas:


The main Flash memory block. It contains the application program and user data if
necessary.



The information block. It is composed of two parts:
–

Option bytes for hardware and memory protection user configuration.

–

System memory which contains the proprietary boot loader code. 
Please, refer to Section 3: Embedded Flash memory for more details.

The Flash interface implements instruction access and data access based on the AHB
protocol. It implements the prefetch buffer that speeds up CPU code execution. It also
implements the logic necessary to carry out the Flash memory operations (Program/Erase)
controlled through the Flash registers.

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2.5

Boot configuration
In the STM32F0x0, three different boot modes can be selected through the BOOT0 pin and
boot configuration bits nBOOT1 in the User option byte, as shown in the following table.
Table 3. Boot modes
Boot mode configuration
Mode
nBOOT1 bit

BOOT0 pin

x

0

Main Flash memory is selected as boot area(1)

1

1

System memory is selected as boot area

0

1

Embedded SRAM is selected as boot area

1. For STM32F070x6 and STM32F030xC devices, see also Empty check description.

The boot mode configuration is latched on the 4th rising edge of SYSCLK after a reset. It is
up to the user to set boot mode configuration related to the required boot mode.
The boot mode configuration is also re-sampled when exiting from Standby mode.
Consequently they must be kept in the required Boot mode configuration in Standby mode.
After this startup delay has elapsed, the CPU fetches the top-of-stack value from address
0x0000 0000, then starts code execution from the boot memory at 0x0000 0004.
Depending on the selected boot mode, main Flash memory, system memory or SRAM is
accessible as follows:


Boot from main Flash memory: the main Flash memory is aliased in the boot memory
space (0x0000 0000), but still accessible from its original memory space
(0x0800 0000). In other words, the Flash memory contents can be accessed starting
from address 0x0000 0000 or 0x0800 0000.



Boot from system memory: the system memory is aliased in the boot memory space
(0x0000 0000), but still accessible from its original memory space (0x1FFF EC00 on
STM32F030x4, STM32F030x6 and STM32F030x8 devices, 0x1FFF C400 on
STM32F070x6 devices, 0x1FFF C800 on STM32F070xB and 0x1FFF D800 on
STM32F030xC devices).



Boot from the embedded SRAM: the SRAM is aliased in the boot memory space
(0x0000 0000), but it is still accessible from its original memory space (0x2000 0000).

Empty check
On STM32F070x6 and STM32F030xC devices only, internal empty check flag is
implemented to allow easy programming of the virgin devices by the boot loader. This flag is
used when BOOT0 pin is defining Main Flash memory as the target boot area. When the
flag is set, the device is considered as empty and System memory (boot loader) is selected
instead of the Main Flash as a boot area to allow user to program the Flash memory.
This flag is updated only during Option bytes loading: it is set when the content of the
address 0x08000 0000 is read as 0xFFFF FFFF, otherwise it is cleared. It means a power
on or setting of OBL_LAUNCH bit in FLASH_CR register is needed to clear this flag after
programming of a virgin device to execute user code after System reset.
Note:

If the device is programmed for a first time but the Option bytes are not reloaded, the device
will still select System memory as a boot area after a System reset. In the STM32F070x6,
the boot loader code is able to detect this situation. It then changes the boot memory
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RM0360
mapping to Main Flash and performs a jump to user code programmed there. In the
STM32F030xC, a POR must be performed or the Option bytes reloaded before applying the
system reset.

Physical remap
Once the boot mode is selected, the application software can modify the memory accessible
in the code area. This modification is performed by programming the MEM_MODE bits in
the SYSCFG configuration register 1 (SYSCFG_CFGR1). Unlike Cortex® M3 and M4, the
M0 CPU does not support the vector table relocation. For application code which is located
in a different address than 0x0800 0000, some additional code must be added in order to be
able to serve the application interrupts. A solution will be to relocate by software the vector
table to the internal SRAM:


Copy the vector table from the Flash (mapped at the base of the application load
address) to the base address of the SRAM at 0x2000 0000.



Remap SRAM at address 0x0000 0000, using SYSCFG configuration register 1.



Then once an interrupt occurs, the Cortex®-M0 processor will fetch the interrupt
handler start address from the relocated vector table in SRAM, then it will jump to
execute the interrupt handler located in the Flash.

This operation should be done at the initialization phase of the application. Please refer to
AN4065 and attached IAP code from www.st.com for more details.

Embedded boot loader
The embedded boot loader is located in the System memory, programmed by ST during
production. It is used to reprogram the Flash memory using one of the following serial
interfaces:


USART on pins PA14/PA15 or PA9/PA10



I2C on pins PB6/PB7 ( STM32F070xx and STM32F030xC devices only)



USB DFU interface (STM32F070xx devices only)

For further details, please refer to AN2606.

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Embedded Flash memory

3

Embedded Flash memory

3.1

Flash main features


Up to 256 Kbyte of Flash memory



Memory organization:
–

Main Flash memory block:
Up to 64 Kword (64 K × 32 bits)

–

Information block:
Up to 3 Kword (3 K × 32 bits) for the system memory

–

Up to 2 x 8 byte for the option byte

Flash memory interface features:


Read interface with prefetch buffer



Option byte Loader



Flash Program / Erase operation



Read / Write protection



Low-power mode

3.2

Flash memory functional description

3.2.1

Flash memory organization
The Flash memory is organized as 32-bit wide memory cells that can be used for storing
both code and data constants.
The memory organization of STM32F030x4, STM32F030x6, STM32F070x6 and
STM32F030x8 devices is based on a main Flash memory block containing up to 64 pages
of 1 Kbyte or up to 16 sectors of 4 Kbytes (4 pages). The sector is the granularity of the write
protection (see Section 3.3: Memory protection on page 55).
The memory organization of STM32F070xB and STM32F030xC devices is based on a main
Flash memory block containing up to 128 pages of 2 Kbytes or up to 64 sectors of 4 Kbytes
(2 pages). The sector is the granularity of the write protection (see Section 3.3: Memory
protection on page 55).
The information block is divided into two parts:
1.

System memory: used to boot the device in System memory boot mode. The area is
reserved for use by STMicroelectronics and contains the boot loader which is used to
reprogram the Flash memory through the selected communication interface. It is
programmed by ST when the device is manufactured, and protected against spurious
write/erase operations. For further details, please refer to AN2606.

2.

Option byte

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Table 4. Flash memory organization (STM32F030x4, STM32F030x6, STM32F070x6 and
STM32F030x8 devices)
Flash area

Main Flash
memory

Information
block

Flash memory addresses

Size (byte)

Name

0x0800 0000 - 0x0800 03FF

1 Kbyte

Page 0

0x0800 0400 - 0x0800 07FF

1 Kbyte

Page 1

0x0800 0800 - 0x0800 0BFF

1 Kbyte

Page 2

0x0800 0C00 - 0x0800 0FFF

1 Kbyte

Page 3

.
.
.

.
.
.

.
.
.

0x0800 7000 - 0x0800 73FF

1 Kbyte

Page 28

0x0800 7400 - 0x0800 77FF

1 Kbyte

Page 29

0x0800 7800 - 0x0800 7BFF

1 Kbyte

Page 30

0x0800 7C00 - 0x0800 7FFF

1 Kbyte

Page 31

.
.
.

.
.
.

.
.
.

0x0800 F000 - 0x0800 F3FF

1 Kbyte

Page 60

0x0800 F400 - 0x0800 F7FF

1 Kbyte

Page 61

0x0800 F800 - 0x0800 FBFF

1 Kbyte

Page 62

0x0800 FC00 - 0x0800 FFFF

1 Kbyte

Page 63

Description(1)

Sector 0

.
.
.

Sector 7 (1)

.
.
.

Sector 15

0x1FFF EC00 - 0x1FFF F7FF

3

Kbyte(2)

-

System memory

0x1FFF C400 -0x1FFF F7FF

13 Kbyte(3)

-

System memory

0x1FFF F800 - 0x1FFF F80F

2 x 8 byte

-

Option byte

1. On STM32F030x4 devices, the main Flash memory space is limited to sector 3. On STM32F030x6 and STM32F070x6
devices, the main Flash memory is limited to sector 7.
2. STM32F030x4, STM32F030x6 and STM32F030x8 devices
3. STM32F070x6 devices

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Embedded Flash memory
Table 5. Flash memory organization (STM32F070xB, STM32F030xC devices)

Flash area

Main Flash
memory

Flash memory addresses

Size (byte)

Name

0x0800 0000 - 0x0800 07FF

2 Kbytes

Page 0

0x0800 0800 - 0x0800 0FFF

2 Kbytes

Page 1

.
.
.

.
.
.

.
.
.

0x0801 F000 - 0x0801 F7FF

2 Kbytes

Page 62

0x0801 F800 - 0x0801 FFFF

2 Kbytes

Page 63

.
.
.

.
.
.

.
.
.

.
.
.

0x0803 F000 - 0x0803 F7FF

2 Kbytes

Page 126

-

0x0803 F800 - 0x0803 FFFF

2 Kbytes

Page 127

-

-

System memory

0x1FFF C800 - 0x1FFF F7FF
Information
block

(2)

12 Kbytes

(3)

Description
Sector 0
.
.
.
Sector 31(1)

0x1FFF D800 - 0x1FFF F7FF

8 Kbytes

-

System memory

0x1FFF F800 - 0x1FFF F80F

2 x 8 byte

-

Option byte

1. The main Flash memory space of STM32F070xB is limited to sector 31.
2. STM32F070xB devices only.
3. STM32F030xC devices only.

Read operations
The embedded Flash module can be addressed directly, as a common memory space. Any
data read operation accesses the content of the Flash module through dedicated read
senses and provides the requested data.
The instruction fetch and the data access are both done through the same AHB bus. Read
accesses can be performed with the following options managed through the Flash access
control register (FLASH_ACR):


Instruction fetch: Prefetch buffer enabled for a faster CPU execution



Latency: number of wait states for a correct read operation (from 0 to 1)

Instruction fetch
The ARM® Cortex®-M0 fetches the instruction over the AHB bus. The prefetch block aims at
increasing the efficiency of instruction fetching.

Prefetch buffer
The prefetch buffer is 3-block wide where each block consists of 4 bytes. The prefetch
blocks are direct-mapped. A block can be completely replaced on a single read to the Flash
memory as the size of the block matches the bandwidth of the Flash memory.
The implementation of this prefetch buffer makes a faster CPU execution possible as the
CPU fetches one word at a time with the next word readily available in the prefetch buffer.
This implies that the acceleration ratio will be of the order of 2 assuming that the code is
aligned at a 32-bit boundary for the jumps.

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However the prefetch buffer has an impact on the performance only when the wait state
number is 1. In the other case (no wait state) the performance remains the same whatever
the prefetch buffer status. There could be some impacts on the power consumption but this
is strongly dependent from the actual application code.

Prefetch controller
The prefetch controller decides to access the Flash memory depending on the available
space in the prefetch buffer. The Controller initiates a read request when there is at least
one block free in the prefetch buffer.
After reset, the state of the prefetch buffer is on.
The prefetch buffer is usually switched on/off during the initialization routine, while the
microcontroller is running on the internal 8 MHz RC (HSI) oscillator.

Access latency
In order to maintain the control signals to read the Flash memory, the ratio of the prefetch
controller clock period to the access time of the Flash memory has to be programmed in the
Flash access control register with the LATENCY[2:0] bits. This value gives the number of
cycles needed to maintain the control signals of the Flash memory and correctly read the
required data. After reset, the value is zero and only one cycle without additional wait states
is required to access the Flash memory.

3.2.2

Flash program and erase operations
The STM32F0x0 embedded Flash memory can be programmed using in-circuit
programming or in-application programming.
The in-circuit programming (ICP) method is used to update the entire contents of the
Flash memory, using the SWD protocol or the boot loader to load the user application into
the microcontroller. ICP offers quick and efficient design iterations and eliminates
unnecessary package handling or socketing of devices.
In contrast to the ICP method, in-application programming (IAP) can use any
communication interface supported by the microcontroller (I/Os, USB, USART, I2C, SPI,
etc.) to download programming data into memory. IAP allows the user to re-program the
Flash memory while the application is running. Nevertheless, part of the application has to
have been previously programmed in the Flash memory using ICP.
The program and erase operations can be performed over the whole product voltage range.
They are managed through the following seven Flash registers:


Key register (FLASH_KEYR)



Option byte key register (FLASH_OPTKEYR)



Flash control register (FLASH_CR)



Flash status register (FLASH_SR)



Flash address register (FLASH_AR)



Option byte register (FLASH_OBR)



Write protection register (FLASH_WRPR)

An ongoing Flash memory operation will not block the CPU as long as the CPU does not
access the Flash memory.

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Embedded Flash memory
On the contrary, during a program/erase operation to the Flash memory, any attempt to read
the Flash memory will stall the bus. The read operation will proceed correctly once the
program/erase operation has completed. This means that code or data fetches cannot be
made while a program/erase operation is ongoing.
For program and erase operations on the Flash memory (write/erase), the internal RC
oscillator (HSI) must be ON.

Unlocking the Flash memory
After reset, the Flash memory is protected against unwanted write or erase operations. The
FLASH_CR register is not accessible in write mode, except for the OBL_LAUNCH bit, used
to reload the option bits. An unlocking sequence should be written to the FLASH_KEYR
register to open the access to the FLASH_CR register. This sequence consists of two write
operations:


Write KEY1 = 0x45670123



Write KEY2 = 0xCDEF89AB

Any wrong sequence locks up the FLASH_CR register until the next reset.
In the case of a wrong key sequence, a bus error is detected and a Hard Fault interrupt is
generated. This is done after the first write cycle if KEY1 does not match, or during the
second write cycle if KEY1 has been correctly written but KEY2 does not match.
The FLASH_CR register can be locked again by user software by writing the LOCK bit in the
FLASH_CR register to 1.
For code example refer to the Appendix section A.2.1: Flash memory unlocking sequence
code.

Main Flash memory programming
The main Flash memory can be programmed 16 bits at a time. The program operation is
started when the CPU writes a half-word into a main Flash memory address with the PG bit
of the FLASH_CR register set. Any attempt to write data that are not half-word long will
result in a bus error generating a Hard Fault interrupt.

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Figure 3. Programming procedure

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1. LSI/LSE is not available on STM32F030x8 devices.

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Reset and clock control (RCC)
Figure 11. Clock tree (STM32F070x6, STM32F070xB and STM32F030xC)
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ARM®

Cortex®-M0’s

FCLK acts as
free-running clock. For more details refer to the ARM
Cortex™-M0 r0p0 technical reference manual (TRM).

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7.2.1

RM0360

HSE clock
The high speed external clock signal (HSE) can be generated from two possible clock
sources:


HSE external crystal/ceramic resonator



HSE user external clock

The resonator and the load capacitors have to be placed as close as possible to the
oscillator pins in order to minimize output distortion and startup stabilization time. The
loading capacitance values must be adjusted according to the selected oscillator.
Figure 12. HSE/ LSE clock sources
Clock source

Hardware configuration

26&B,1

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Reset and clock control (RCC)

External crystal/ceramic resonator (HSE crystal)
The 4 to 32 MHz external oscillator has the advantage of producing a very accurate rate on
the main clock.
The associated hardware configuration is shown in Figure 12. Refer to the electrical
characteristics section of the datasheet for more details.
The HSERDY flag in the Clock control register (RCC_CR) indicates if the HSE oscillator is
stable or not. At startup, the clock is not released until this bit is set by hardware. An
interrupt can be generated if enabled in the Clock interrupt register (RCC_CIR).
The HSE Crystal can be switched on and off using the HSEON bit in the Clock control
register (RCC_CR).
For code example refer to the Appendix section A.3.1: HSE start sequence code example.
Caution:

To switch ON the HSE oscillator, 512 HSE clock pulses need to be seen by an internal
stabilization counter after the HSEON bit is set. Even in the case that no crystal or resonator
is connected to the device, excessive external noise on the OSC_IN pin may still lead the
oscillator to start. Once the oscillator is started, it needs another 6 HSE clock pulses to
complete a switching OFF sequence. If for any reason the oscillations are no more present
on the OSC_IN pin, the oscillator cannot be switched OFF, locking the OSC pins from any
other use and introducing unwanted power consumption. To avoid such situation, it is
strongly recommended to always enable the Clock Security System (CSS) which is able to
switch OFF the oscillator even in this case.

External source (HSE bypass)
In this mode, an external clock source must be provided. It can have a frequency of up to
32 MHz. You select this mode by setting the HSEBYP and HSEON bits in the Clock control
register (RCC_CR). The external clock signal (square, sinus or triangle) with ~40-60% duty
cycle depending on the frequency (refer to the datasheet) has to drive the OSC_IN pin while
the OSC_OUT pin can be used a GPIO. See Figure 12.

7.2.2

HSI clock
The HSI clock signal is generated from an internal 8 MHz RC oscillator and can be used
directly as a system clock or for PLL input
The HSI RC oscillator has the advantage of providing a clock source at low cost (no external
components). It also has a faster startup time than the HSE crystal oscillator however, even
with calibration the frequency is less accurate than an external crystal oscillator or ceramic
resonator.

Calibration
RC oscillator frequencies can vary from one chip to another due to manufacturing process
variations, this is why each device is factory calibrated by ST for 1% accuracy at TA=25°C.
After reset, the factory calibration value is loaded in the HSICAL[7:0] bits in the Clock control
register (RCC_CR).
If the application is subject to voltage or temperature variations this may affect the RC
oscillator speed. You can trim the HSI frequency in the application using the HSITRIM[4:0]
bits in the Clock control register (RCC_CR).

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For more details on how to measure the HSI frequency variation please refer to
Section 7.2.12: Internal/external clock measurement with TIM14 on page 97.
The HSIRDY flag in the Clock control register (RCC_CR) indicates if the HSI RC is stable or
not. At startup, the HSI RC output clock is not released until this bit is set by hardware.
The HSI RC can be switched on and off using the HSION bit in the Clock control register
(RCC_CR).
The HSI signal can also be used as a backup source (Auxiliary clock) if the HSE crystal
oscillator fails. Refer to Section 7.2.7: Clock security system (CSS) on page 95.
Furthermore it is possible to drive the HSI clock to the MCO multiplexer. Then the clock
could be driven to the Timer 14 giving the ability to the user to calibrate the oscillator.

7.2.3

PLL
The internal PLL can be used to multiply the HSI and the HSE output clock frequency. Refer
to Figure 9: Simplified diagram of the reset circuit, Figure 12: HSE/ LSE clock sources and
Clock control register (RCC_CR).
The PLL configuration (selection of the input clock, predivider and multiplication factor) must
be done before enabling the PLL. Once the PLL is enabled, these parameters cannot be
changed.
To modify the PLL configuration, proceed as follows:
1.

Disable the PLL by setting PLLON to 0.

2.

Wait until PLLRDY is cleared. The PLL is now fully stopped.

3.

Change the desired parameter.

4.

Enable the PLL again by setting PLLON to 1.

5.

Wait until PLLRDY is set.

An interrupt can be generated when the PLL is ready, if enabled in the Clock interrupt
register (RCC_CIR).
The PLL output frequency must be set in the range 16-48 MHz.
For code example refer to the Appendix section A.3.2: PLL configuration modification code
example.

7.2.4

LSE clock
The LSE crystal is a 32.768 kHz Low Speed External crystal or ceramic resonator. It has the
advantage of providing a low-power but highly accurate clock source to the real-time clock
peripheral (RTC) for clock/calendar or other timing functions.
The LSE crystal is switched on and off using the LSEON bit in RTC domain control register
(RCC_BDCR). The crystal oscillator driving strength can be changed at runtime using the
LSEDRV[1:0] bits in the RTC domain control register (RCC_BDCR) to obtain the best
compromise between robustness and short start-up time on one side and low-power
consumption on the other.
The LSERDY flag in the RTC domain control register (RCC_BDCR) indicates whether the
LSE crystal is stable or not. At startup, the LSE crystal output clock signal is not released
until this bit is set by hardware. An interrupt can be generated if enabled in the Clock
interrupt register (RCC_CIR).

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Reset and clock control (RCC)

Caution:

To switch ON the LSE oscillator, 4096 LSE clock pulses need to be seen by an internal
stabilization counter after the LSEON bit is set. Even in the case that no crystal or resonator
is connected to the device, excessive external noise on the OSC32_IN pin may still lead the
oscillator to start. Once the oscillator is started, it needs another 6 LSE clock pulses to
complete a switching OFF sequence. If for any reason the oscillations are no more present
on the OSC_IN pin, the oscillator cannot be switched OFF, locking the OSC32 pins from any
other use and introducing unwanted power consumption. The only way to recover such
situation is to perform the RTC domain reset by software.

External source (LSE bypass)
In this mode, an external clock source must be provided. It can have a frequency of up to
1 MHz. You select this mode by setting the LSEBYP and LSEON bits in the RTC domain
control register (RCC_BDCR). The external clock signal (square, sinus or triangle) with
~50% duty cycle has to drive the OSC32_IN pin while the OSC32_OUT pin can be used as
GPIO. See Figure 12.

7.2.5

LSI clock
The LSI RC acts as a low-power clock source that can be kept running in Stop and Standby
mode for the independent watchdog (IWDG) and RTC. The clock frequency is around 40
kHz. For more details, refer to the electrical characteristics section of the datasheets.
The LSI RC can be switched on and off using the LSION bit in the Control/status register
(RCC_CSR).
The LSIRDY flag in the Control/status register (RCC_CSR) indicates if the LSI oscillator is
stable or not. At startup, the clock is not released until this bit is set by hardware. An
interrupt can be generated if enabled in the Clock interrupt register (RCC_CIR).

7.2.6

System clock (SYSCLK) selection
Various clock sources can be used to drive the system clock (SYSCLK):


HSI oscillator



HSE oscillator



PLL

After a system reset, the HSI oscillator is selected as system clock. When a clock source is
used directly or through the PLL as a system clock, it is not possible to stop it.
A switch from one clock source to another occurs only if the target clock source is ready
(clock stable after startup delay or PLL locked). If a clock source which is not yet ready is
selected, the switch will occur when the clock source becomes ready. Status bits in the
Clock control register (RCC_CR) indicate which clock(s) is (are) ready and which clock is
currently used as a system clock.

7.2.7

Clock security system (CSS)
Clock Security System can be activated by software. In this case, the clock detector is
enabled after the HSE oscillator startup delay, and disabled when this oscillator is stopped.
If a failure is detected on the HSE clock, the HSE oscillator is automatically disabled, a clock
failure event is sent to the break input of the advanced-control timers (TIM1) and generalpurpose timers (TIM15, TIM16 and TIM17) and an interrupt is generated to inform the
software about the failure (Clock Security System Interrupt CSSI), allowing the MCU to
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perform rescue operations. The CSSI is linked to the ARM® Cortex®-M0 NMI (NonMaskable Interrupt) exception vector.
Note:

Once the CSS is enabled and if the HSE clock fails, the CSS interrupt occurs and an NMI is
automatically generated. The NMI will be executed indefinitely unless the CSS interrupt
pending bit is cleared. As a consequence, in the NMI ISR user must clear the CSS interrupt
by setting the CSSC bit in the Clock interrupt register (RCC_CIR).
If the HSE oscillator is used directly or indirectly as the system clock (indirectly means: it is
used as PLL input clock, and the PLL clock is used as system clock), a detected failure
causes a switch of the system clock to the HSI oscillator and the disabling of the HSE
oscillator. If the HSE clock (divided or not) is the clock entry of the PLL used as system clock
when the failure occurs, the PLL is disabled too.

7.2.8

ADC clock
The ADC clock selection is done inside the ADC_CFGR2 (refer to Section 12.11.5: ADC
configuration register 2 (ADC_CFGR2) on page 216). It can be either the dedicated 14 MHz
RC oscillator (HSI14) or PCLK divided by 2 or 4. The 14 MHz RC oscillator can be
configured by software either to be turned on/off (“auto-off mode”) by the ADC interface or to
be always enabled. The HSI 14 MHz RC oscillator cannot be turned on by ADC interface
when the APB clock is selected as an ADC kernel clock.

7.2.9

RTC clock
The RTCCLK clock source can be either the HSE/32, LSE or LSI clocks. This is selected by
programming the RTCSEL[1:0] bits in the RTC domain control register (RCC_BDCR). This
selection cannot be modified without resetting the RTC domain. The system must be always
configured in a way that the PCLK frequency is greater then or equal to the RTCCLK
frequency for proper operation of the RTC.

7.2.10

Independent watchdog clock
If the Independent watchdog (IWDG) is started by either hardware option or software
access, the LSI oscillator is forced ON and cannot be disabled. After the LSI oscillator
temporization, the clock is provided to the IWDG.

7.2.11

Clock-out capability
The microcontroller clock output (MCO) capability allows the clock to be output onto the
external MCO pin. The configuration registers of the corresponding GPIO port must be
programmed in alternate function mode. One of the following clock signals can be selected
as the MCO clock:

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

HSI14



SYSCLK



HSI



HSE



PLL clock divided by 2 or direct (direct connection is not available on
STM32F030x8devices)



LSE



LSI

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Reset and clock control (RCC)
The selection is controlled by the MCO[3:0] bits of the Clock configuration register
(RCC_CFGR).
For code example refer to the Appendix section A.3.3: MCO selection code example.
On STM32F030x4, STM32F030x6, STM32F070x6, STM32F070xB and STM32F030xC
devices, the additional bit PLLNODIV of this register controls the divider bypass for a PLL
clock input to MCO. The MCO frequency can be reduced by a configurable binary divider,
controlled by the MCOPRE[2..0] bits of the Clock configuration register (RCC_CFGR).

7.2.12

Internal/external clock measurement with TIM14
It is possible to indirectly measure the frequency of all on-board clock sources by mean of
the TIM14 channel 1 input capture. As represented on Figure 13.
Figure 13. Frequency measurement with TIM14 in capture mode
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069

The input capture channel of the Timer 14 can be a GPIO line or an internal clock of the
MCU. This selection is performed through the TI1_RMP [1:0] bits in the TIM14_OR register.
The possibilities available are the following ones.


TIM14 Channel1 is connected to the GPIO. Refer to the alternate function mapping in
the device datasheets.



TIM14 Channel1 is connected to the RTCCLK.



TIM14 Channel1 is connected to the HSE/32 Clock.



TIM14 Channel1 is connected to the microcontroller clock output (MCO). Refer to
Section 7.2.11: Clock-out capability for MCO clock configuration.

For code example refer to the Appendix section A.3.4: Clock measurement configuration
with TIM14 code example.

Calibration of the HSI
The primary purpose of connecting the LSE, through the MCO multiplexer, to the channel 1
input capture is to be able to precisely measure the HSI system clocks (for this, the HSI
should be used as the system clock source). The number of HSI clock counts between
consecutive edges of the LSE signal provides a measure of the internal clock period. Taking
advantage of the high precision of LSE crystals (typically a few tens of ppm), it is possible to
determine the internal clock frequency with the same resolution, and trim the source to
compensate for manufacturing-process- and/or temperature- and voltage-related frequency
deviations.
The HSI oscillator has dedicated user-accessible calibration bits for this purpose.

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The basic concept consists in providing a relative measurement (e.g. the HSI/LSE ratio): the
precision is therefore closely related to the ratio between the two clock sources. The higher
the ratio is, the better the measurement will be.
If LSE is not available, HSE/32 will be the better option in order to reach the most precise
calibration possible.

Calibration of the LSI
The calibration of the LSI will follow the same pattern that for the HSI, but changing the
reference clock. It will be necessary to connect LSI clock to the channel 1 input capture of
the TIM14. Then define the HSE as system clock source, the number of its clock counts
between consecutive edges of the LSI signal provides a measure of the internal low speed
clock period.
The basic concept consists in providing a relative measurement (e.g. the HSE/LSI ratio): the
precision is therefore closely related to the ratio between the two clock sources. The higher
the ratio is, the better the measurement will be.

Calibration of the HSI14
For the HSI14, because of its high frequency, it is not possible to have a precise resolution.
However a solution could be to clock Timer 14 with HSE through PLL to reach 48 MHz, and
to use the input capture line with the HSI14 and the capture prescaler defined to the higher
value. In that configuration, we got a ratio of 27 events. It is still a bit low to have an accurate
calibration. In order to increase the measure accuracy, it is advised to count the HSI periods
after multiple cycles of Timer 14. Using polling to treat the capture event will be necessary in
this case.

7.3

Low-power modes
APB peripheral clocks and DMA clock can be disabled by software.
Sleep mode stops the CPU clock. The memory interface clocks (Flash and RAM interfaces)
can be stopped by software during sleep mode. The AHB to APB bridge clocks are disabled
by hardware during Sleep mode when all the clocks of the peripherals connected to them
are disabled.
Stop mode stops all the clocks in the core supply domain and disables the PLL and the HSI,
HSI14 and HSE oscillators.
Standby mode stops all the clocks in the core supply domain and disables the PLL and the
HSI, HSI14 and HSE oscillators.
The CPU’s deepsleep mode can be overridden for debugging by setting the DBG_STOP or
DBG_STANDBY bits in the DBGMCU_CR register.
When waking up from deepsleep after an interrupt (Stop mode) or reset (Standby mode),
the HSI oscillator is selected as system clock.
If a Flash programming operation is on going, deepsleep mode entry is delayed until the
Flash interface access is finished. If an access to the APB domain is ongoing, deepsleep
mode entry is delayed until the APB access is finished.

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Reset and clock control (RCC)

7.4

RCC registers
Refer to Section 1.1 on page 33 for a list of abbreviations used in register descriptions.

7.4.1

Clock control register (RCC_CR)
Address offset: 0x00
Reset value: 0x0000 XX83 where X is undefined.
Access: no wait state, word, half-word and byte access

31
Res.

15

30
Res.

14

29
Res.

13

28
Res.

12

27
Res.

11

26

25

Res.

PLL
RDY

PLLON

r

rw

9

8

10

24

23
Res.

22
Res.

7

r

r

r

r

Res.

6

HSICAL[7:0]
r

21

5

20

19

18

17

16

Res.

CSS
ON

HSE
BYP

HSE
RDY

HSE
ON

rw

rw

r

rw

3

2

1

0

Res.

HSI
RDY

HSION

r

rw

4

HSITRIM[4:0]
r

r

r

rw

rw

rw

rw

rw

Bits 31:26 Reserved, must be kept at reset value.
Bit 25 PLLRDY: PLL clock ready flag
Set by hardware to indicate that the PLL is locked.
0: PLL unlocked
1: PLL locked
Bit 24 PLLON: PLL enable
Set and cleared by software to enable PLL.
Cleared by hardware when entering Stop or Standby mode. This bit can not be reset if the PLL
clock is used as system clock or is selected to become the system clock.
0: PLL OFF
1: PLL ON
Bits 23:20 Reserved, must be kept at reset value.
Bit 19 CSSON: Clock security system enable
Set and cleared by software to enable the clock security system. When CSSON is set, the
clock detector is enabled by hardware when the HSE oscillator is ready, and disabled by
hardware if a HSE clock failure is detected.
0: Clock security system disabled (clock detector OFF).
1: Clock security system enabled (clock detector ON if the HSE is ready, OFF if not).
Bit 18 HSEBYP: HSE crystal oscillator bypass
Set and cleared by software to bypass the oscillator with an external clock. The external clock
must be enabled with the HSEON bit set, to be used by the device. The HSEBYP bit can be
written only if the HSE oscillator is disabled.
0: HSE crystal oscillator not bypassed
1: HSE crystal oscillator bypassed with external clock

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Bit 17 HSERDY: HSE clock ready flag
Set by hardware to indicate that the HSE oscillator is stable. This bit needs 6 cycles of the HSE
oscillator clock to fall down after HSEON reset.
0: HSE oscillator not ready
1: HSE oscillator ready
Bit 16 HSEON: HSE clock enable
Set and cleared by software.
Cleared by hardware to stop the HSE oscillator when entering Stop or Standby mode. This bit
cannot be reset if the HSE oscillator is used directly or indirectly as the system clock.
0: HSE oscillator OFF
1: HSE oscillator ON
Bits 15:8 HSICAL[7:0]: HSI clock calibration
These bits are initialized automatically at startup. They are adjusted by SW through the
HSITRIM setting.
Bits 7:3 HSITRIM[4:0]: HSI clock trimming
These bits provide an additional user-programmable trimming value that is added to the
HSICAL[7:0] bits. It can be programmed to adjust to variations in voltage and temperature that
influence the frequency of the HSI.
The default value is 16, which, when added to the HSICAL value, should trim the HSI to 8 MHz
± 1%. The trimming step is around 40 kHz between two consecutive HSICAL steps.
Note: Increased value in the register results to higher clock frequency.
Bit 2 Reserved, must be kept at reset value.
Bit 1 HSIRDY: HSI clock ready flag
Set by hardware to indicate that HSI oscillator is stable. After the HSION bit is cleared,
HSIRDY goes low after 6 HSI oscillator clock cycles.
0: HSI oscillator not ready
1: HSI oscillator ready
Bit 0 HSION: HSI clock enable
Set and cleared by software.
Set by hardware to force the HSI oscillator ON when leaving Stop or Standby mode or in case
of failure of the HSE crystal oscillator used directly or indirectly as system clock. This bit
cannot be reset if the HSI is used directly or indirectly as system clock or is selected to become
the system clock.
0: HSI oscillator OFF
1: HSI oscillator ON

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Reset and clock control (RCC)

7.4.2

Clock configuration register (RCC_CFGR)
Address offset: 0x04
Reset value: 0x0000 0000
Access: 0 ≤ wait state ≤ 2, word, half-word and byte access
1 or 2 wait states inserted only if the access occurs during clock source switch.

31

30

PLL
NODIV

29

28

27

MCOPRE[2:0]

26

25

24

MCO[3:0]

rw

rw

rw

rw

rw

rw

rw

rw

15

14

13

12

11

10

9

8

Res.

ADC
PRE

Res.

Res.

Res.

rw

23

22

Res.

Res.

7

PPRE[2:0]
rw

rw

6

21

20

rw

rw

18

PLLMUL[3:0]

17

16

PLL
XTPRE

PLL
SRC

rw

rw

rw

rw

rw

rw

5

4

3

2

1

0

HPRE[3:0]
rw

19

rw

SWS[1:0]
rw

r

r

SW[1:0]
rw

rw

Bit 31 PLLNODIV: PLL clock not divided for MCO (not available on STM32F030x8 devices)
This bit is set and cleared by software. It switches off divider by 2 for PLL connection to MCO.
0: PLL is divided by 2 for MCO
1: PLL is not divided for MCO
Bits 30:28 MCOPRE[2:0]: Microcontroller Clock Output Prescaler (not available on STM32F030x8
devices)
These bits are set and cleared by software to select the MCO prescaler division factor. To
avoid glitches, it is highly recommended to change this prescaler only when the MCO output is
disabled.
000: MCO is divided by 1
001: MCO is divided by 2
010: MCO is divided by 4
.....
111: MCO is divided by 128
Bits 27:24 MCO[3:0]: Microcontroller clock output
Set and cleared by software.
0000: MCO output disabled, no clock on MCO
0001: Internal RC 14 MHz (HSI14) oscillator clock selected
0010: Internal low speed (LSI) oscillator clock selected
0011: External low speed (LSE) oscillator clock selected
0100: System clock selected
0101: Internal RC 8 MHz (HSI) oscillator clock selected
0110: External 4-32 MHz (HSE) oscillator clock selected
0111: PLL clock selected (divided by 1 or 2, depending on PLLNODIV)
1xxx: Reserved, must be kept at reset value.
Note: This clock output may have some truncated cycles at startup or during MCO clock
source switching.
Bits 23:22 Reserved, must be kept at reset value.

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Bits 21:18 PLLMUL[3:0]: PLL multiplication factor
These bits are written by software to define the PLL multiplication factor. These bits can be
written only when PLL is disabled.
Caution: The PLL output frequency must not exceed 48 MHz.
0000: PLL input clock x 2
0001: PLL input clock x 3
0010: PLL input clock x 4
0011: PLL input clock x 5
0100: PLL input clock x 6
0101: PLL input clock x 7
0110: PLL input clock x 8
0111: PLL input clock x 9
1000: PLL input clock x 10
1001: PLL input clock x 11
1010: PLL input clock x 12
1011: PLL input clock x 13
1100: PLL input clock x 14
1101: PLL input clock x 15
1110: PLL input clock x 16
1111: PLL input clock x 16
Bit 17 PLLXTPRE: HSE divider for PLL input clock
This bit is the same bit as bit PREDIV[0] from RCC_CFGR2. Refer to RCC_CFGR2 PREDIV
bits description for its meaning.
Bit 16 PLLSRC: PLL entry clock source
Set and cleared by software to select PLL clock source. This bit can be written only when PLL
is disabled.
0: HSI/2 selected as PLL input clock
1: HSE/PREDIV selected as PLL input clock (refer to Section 7.4.12: Clock configuration
register 2 (RCC_CFGR2) on page 122)
Bit 15 Reserved, must be kept at reset value.
Bit 14 ADCPRE: ADC prescaler
Obsolete setting. Proper ADC clock selection is done inside the ADC_CFGR2 (refer to
Section 12.11.5: ADC configuration register 2 (ADC_CFGR2) on page 216).
Bits 13:11 Reserved, must be kept at reset value.
Bits 10:8 PPRE[2:0]: PCLK prescaler
Set and cleared by software to control the division factor of the APB clock (PCLK).
0xx: HCLK not divided
100: HCLK divided by 2
101: HCLK divided by 4
110: HCLK divided by 8
111: HCLK divided by 16

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Bits 7:4 HPRE[3:0]: HCLK prescaler
Set and cleared by software to control the division factor of the AHB clock.
0xxx: SYSCLK not divided
1000: SYSCLK divided by 2
1001: SYSCLK divided by 4
1010: SYSCLK divided by 8
1011: SYSCLK divided by 16
1100: SYSCLK divided by 64
1101: SYSCLK divided by 128
1110: SYSCLK divided by 256
1111: SYSCLK divided by 512
Bits 3:2 SWS[1:0]: System clock switch status
Set and cleared by hardware to indicate which clock source is used as system clock.
00: HSI oscillator used as system clock
01: HSE oscillator used as system clock
10: PLL used as system clock
11: Reserved, must be kept at reset value.
Bits 1:0 SW[1:0]: System clock switch
Set and cleared by software to select SYSCLK source.
Cleared by hardware to force HSI selection when leaving Stop and Standby mode or in case
of failure of the HSE oscillator used directly or indirectly as system clock (if the Clock Security
System is enabled).
00: HSI selected as system clock
01: HSE selected as system clock
10: PLL selected as system clock
11: Reserved, must be kept at reset value.

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7.4.3

RM0360

Clock interrupt register (RCC_CIR)
Address offset: 0x08
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

CSSC

Res.

HSI14
RDYC

PLL
RDYC

HSE
RDYC

HSI
RDYC

LSE
RDYC

LSI
RDYC

w

w

w

w

w

w

w
15
Res.

14

13

12

11

10

9

8

Res.

HSI14
RDYIE

PLL
RDYIE

HSE
RDYIE

HSI
RDYIE

LSE
RDYIE

LSI
RDYIE

7
CSSF

rw

rw

rw

rw

rw

rw

r

6

5

4

3

2

1

0

Res.

HSI14
RDYF

PLL
RDYF

HSE
RDYF

HSI
RDYF

LSE
RDYF

LSI
RDYF

r

r

r

r

r

r

Bits 31:24 Reserved, must be kept at reset value.
Bit 23 CSSC: Clock security system interrupt clear
This bit is set by software to clear the CSSF flag.
0: No effect
1: Clear CSSF flag
Bit 22
Reserved, must be kept at reset value.
Bit 21 HSI14RDYC: HSI14 ready interrupt clear
This bit is set by software to clear the HSI14RDYF flag.
0: No effect
1: Clear HSI14RDYF flag
Bit 20 PLLRDYC: PLL ready interrupt clear
This bit is set by software to clear the PLLRDYF flag.
0: No effect
1: Clear PLLRDYF flag
Bit 19 HSERDYC: HSE ready interrupt clear
This bit is set by software to clear the HSERDYF flag.
0: No effect
1: Clear HSERDYF flag
Bit 18 HSIRDYC: HSI ready interrupt clear
This bit is set software to clear the HSIRDYF flag.
0: No effect
1: Clear HSIRDYF flag
Bit 17 LSERDYC: LSE ready interrupt clear
This bit is set by software to clear the LSERDYF flag.
0: No effect
1: LSERDYF cleared

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Reset and clock control (RCC)

Bit 16 LSIRDYC: LSI ready interrupt clear
This bit is set by software to clear the LSIRDYF flag.
0: No effect
1: LSIRDYF cleared
Bits 15:14 Reserved, must be kept at reset value.
Bit 13 HSI14RDYIE: HSI14 ready interrupt enable
Set and cleared by software to enable/disable interrupt caused by the HSI14 oscillator
stabilization.
0: HSI14 ready interrupt disabled
1: HSI14 ready interrupt enabled
Bit 12 PLLRDYIE: PLL ready interrupt enable
Set and cleared by software to enable/disable interrupt caused by PLL lock.
0: PLL lock interrupt disabled
1: PLL lock interrupt enabled
Bit 11 HSERDYIE: HSE ready interrupt enable
Set and cleared by software to enable/disable interrupt caused by the HSE oscillator
stabilization.
0: HSE ready interrupt disabled
1: HSE ready interrupt enabled
Bit 10 HSIRDYIE: HSI ready interrupt enable
Set and cleared by software to enable/disable interrupt caused by the HSI oscillator
stabilization.
0: HSI ready interrupt disabled
1: HSI ready interrupt enabled
Bit 9 LSERDYIE: LSE ready interrupt enable
Set and cleared by software to enable/disable interrupt caused by the LSE oscillator
stabilization.
0: LSE ready interrupt disabled
1: LSE ready interrupt enabled
Bit 8 LSIRDYIE: LSI ready interrupt enable
Set and cleared by software to enable/disable interrupt caused by the LSI oscillator
stabilization.
0: LSI ready interrupt disabled
1: LSI ready interrupt enabled
Bit 7 CSSF: Clock security system interrupt flag
Set by hardware when a failure is detected in the HSE oscillator.
Cleared by software setting the CSSC bit.
0: No clock security interrupt caused by HSE clock failure
1: Clock security interrupt caused by HSE clock failure
Bit 6 Reserved, must be kept at reset value.

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Bit 5 HSI14RDYF: HSI14 ready interrupt flag
Set by hardware when the HSI14 becomes stable and HSI14RDYDIE is set in a response to
setting the HSI14ON bit in Clock control register 2 (RCC_CR2). When HSI14ON is not set
but the HSI14 oscillator is enabled by the peripheral through a clock request, this bit is not set
and no interrupt is generated.
Cleared by software setting the HSI14RDYC bit.
0: No clock ready interrupt caused by the HSI14 oscillator
1: Clock ready interrupt caused by the HSI14 oscillator
Bit 4 PLLRDYF: PLL ready interrupt flag
Set by hardware when the PLL locks and PLLRDYDIE is set.
Cleared by software setting the PLLRDYC bit.
0: No clock ready interrupt caused by PLL lock
1: Clock ready interrupt caused by PLL lock
Bit 3 HSERDYF: HSE ready interrupt flag
Set by hardware when the HSE clock becomes stable and HSERDYDIE is set.
Cleared by software setting the HSERDYC bit.
0: No clock ready interrupt caused by the HSE oscillator
1: Clock ready interrupt caused by the HSE oscillator
Bit 2 HSIRDYF: HSI ready interrupt flag
Set by hardware when the HSI clock becomes stable and HSIRDYDIE is set in a response to
setting the HSION (refer to Clock control register (RCC_CR)). When HSION is not set but the
HSI oscillator is enabled by the peripheral through a clock request, this bit is not set and no
interrupt is generated.
Cleared by software setting the HSIRDYC bit.
0: No clock ready interrupt caused by the HSI oscillator
1: Clock ready interrupt caused by the HSI oscillator
Bit 1 LSERDYF: LSE ready interrupt flag
Set by hardware when the LSE clock becomes stable and LSERDYDIE is set.
Cleared by software setting the LSERDYC bit.
0: No clock ready interrupt caused by the LSE oscillator
1: Clock ready interrupt caused by the LSE oscillator
Bit 0 LSIRDYF: LSI ready interrupt flag
Set by hardware when the LSI clock becomes stable and LSIRDYDIE is set.
Cleared by software setting the LSIRDYC bit.
0: No clock ready interrupt caused by the LSI oscillator
1: Clock ready interrupt caused by the LSI oscillator

7.4.4

APB peripheral reset register 2 (RCC_APB2RSTR)
Address offset: 0x0C
Reset value: 0x00000 0000
Access: no wait state, word, half-word and byte access

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

DBGMCU
RST

Res.

Res.

Res.

TIM17
RST

TIM16
RST

TIM15
RST

rw

rw

rw

rw

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Reset and clock control (RCC)

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Res.

USART1
RST

Res.

SPI1
RST

TIM1
RST

Res.

ADC
RST

Res.

Res.

Res.

USART6
RST

Res.

Res.

Res.

Res.

SYSCFG
RST

rw

rw

rw

rw

rw

rw

Bits 31:23 Reserved, must be kept at reset value.
Bits 22 DBGMCURST: Debug MCU reset
Set and cleared by software.
0: No effect
1: Reset Debug MCU
Bits 21:19 Reserved, must be kept at reset value.
Bit 18 TIM17RST: TIM17 timer reset
Set and cleared by software.
0: No effect
1: Reset TIM17 timer
Bit 17 TIM16RST: TIM16 timer reset
Set and cleared by software.
0: No effect
1: Reset TIM16 timer
Bit 16 TIM15RST: TIM15 timer reset
Set and cleared by software.
0: No effect
1: Reset TIM15 timer
Bit 15 Reserved, must be kept at reset value.
Bit 14 USART1RST: USART1 reset
Set and cleared by software.
0: No effect
1: Reset USART1
Bit 13 Reserved, must be kept at reset value.
Bit 12 SPI1RST: SPI1 reset
Set and cleared by software.
0: No effect
1: Reset SPI1
Bit 11 TIM1RST: TIM1 timer reset
Set and cleared by software.
0: No effect
1: Reset TIM1 timer
Bit 10 Reserved, must be kept at reset value.
Bit 9 ADCRST: ADC interface reset
Set and cleared by software.
0: No effect
1: Reset ADC interface
Bits 8:6 Reserved, must be kept at reset value.

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RM0360

Bit 5 USART6RST: USART6 reset
Set and cleared by software
0: No effect
1: Reset USART6
Bits 4:1 Reserved, must be kept at reset value.
Bit 0 SYSCFGRST: SYSCFG reset
Set and cleared by software.
0: No effect
1: Reset SYSCFG

7.4.5

APB peripheral reset register 1 (RCC_APB1RSTR)
Address offset: 0x10
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access

31
Res.

30
Res.

29

28

Res.

PWR
RST

27

26

Res.

Res
.

25
Res.

24

23

22

21

Res.

USB
RST

I2C2
RST

I2C1
RST

rw

rw

rw

rw

rw

rw

rw

rw

20

19

18

17

USART5 USART4 USART3 USART2
RST
RST
RST
RST

16
Res.

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Res.

SPI2
RST

Res.

Res.

WWDG
RST

Res
.

Res.

TIM14
RST

Res.

Res.

TIM7
RST

TIM6
RST

Res.

Res.

TIM3
RST

Res.

rw

rw

rw

rw

rw

Bit 31:29 Reserved, must be kept at reset value.
Bit 28 PWRRST: Power interface reset
Set and cleared by software.
0: No effect
1: Reset power interface
Bit 27:24 Reserved, must be kept at reset value.
Bit 23 USBRST: USB interface reset
Set and cleared by software.
0: No effect
1: Reset USB interface
Bit 22 I2C2RST: I2C2 reset
Set and cleared by software.
0: No effect
1: Reset I2C2
Bit 21 I2C1RST: I2C1 reset
Set and cleared by software.
0: No effect
1: Reset I2C1

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RM0360

Reset and clock control (RCC)

Bit 20 USART5RST: USART5 reset
Set and cleared by software.
0: No effect
1: Reset USART4
Bit 19 USART4RST: USART4 reset
Set and cleared by software.
0: No effect
1: Reset USART4
Bit 18 USART3RST: USART3 reset
Set and cleared by software.
0: No effect
1: Reset USART3
Bit 17 USART2RST: USART2 reset
Set and cleared by software.
0: No effect
1: Reset USART2
Bits 16:15 Reserved, must be kept at reset value.
Bit 14 SPI2RST: SPI2 reset
Set and cleared by software.
0: No effect
1: Reset SPI2
Bits 13:12 Reserved, must be kept at reset value.
Bit 11 WWDGRST: Window watchdog reset
Set and cleared by software.
0: No effect
1: Reset window watchdog
Bits 10:9 Reserved, must be kept at reset value.
Bit 8 TIM14RST: TIM14 timer reset
Set and cleared by software.
0: No effect
1: Reset TIM14
Bits 7:6 Reserved, must be kept at reset value.
Bit 5 TIM7RST: TIM7 timer reset
Set and cleared by software.
0: No effect
1: Reset TIM7
Bit 4 TIM6RST: TIM6 timer reset
Set and cleared by software.
0: No effect
1: Reset TIM6

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Bit 3:2 Reserved, must be kept at reset value.
Bit 1 TIM3RST: TIM3 timer reset
Set and cleared by software.
0: No effect
1: Reset TIM3
Bit 0

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Reset and clock control (RCC)

7.4.6

AHB peripheral clock enable register (RCC_AHBENR)
Address offset: 0x14
Reset value: 0x0000 0014
Access: no wait state, word, half-word and byte access

Note:

When the peripheral clock is not active, the peripheral register values may not be readable
by software and the returned value is always 0x0.

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

IOPF
EN

Res.

IOPD
EN

IOPC
EN

IOPB
EN

IOPA
EN

Res.

rw

rw

rw

rw

rw
15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

CRC
EN

Res.

FLITF
EN

Res.

SRAM
EN

Res.

DMA
EN

rw

rw

rw

rw

Bits 31:23 Reserved, must be kept at reset value.
Bit 22 IOPFEN: I/O port F clock enable
Set and cleared by software.
0: I/O port F clock disabled
1: I/O port F clock enabled
Bit 21

Reserved, must be kept at reset value.

Bit 20 IOPDEN: I/O port D clock enable
Set and cleared by software.
0: I/O port D clock disabled
1: I/O port D clock enabled
Bit 19 IOPCEN: I/O port C clock enable
Set and cleared by software.
0: I/O port C clock disabled
1: I/O port C clock enabled
Bit 18 IOPBEN: I/O port B clock enable
Set and cleared by software.
0: I/O port B clock disabled
1: I/O port B clock enabled
Bit 17 IOPAEN: I/O port A clock enable
Set and cleared by software.
0: I/O port A clock disabled
1: I/O port A clock enabled
Bits 16:7 Reserved, must be kept at reset value.
Bit 6 CRCEN: CRC clock enable
Set and cleared by software.
0: CRC clock disabled
1: CRC clock enabled

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RM0360

Bit 5 Reserved, must be kept at reset value.
Bit 4 FLITFEN: FLITF clock enable
Set and cleared by software to disable/enable FLITF clock during Sleep mode.
0: FLITF clock disabled during Sleep mode
1: FLITF clock enabled during Sleep mode
Bit 3 Reserved, must be kept at reset value.
Bit 2 SRAMEN: SRAM interface clock enable
Set and cleared by software to disable/enable SRAM interface clock during Sleep mode.
0: SRAM interface clock disabled during Sleep mode.
1: SRAM interface clock enabled during Sleep mode
Bit 1 Reserved, must be kept at reset value.
Bit 0 DMAEN: DMA clock enable
Set and cleared by software.
0: DMA clock disabled
1: DMA clock enabled

7.4.7

APB peripheral clock enable register 2 (RCC_APB2ENR)
Address: 0x18
Reset value: 0x0000 0000
Access: word, half-word and byte access
No wait states, except if the access occurs while an access to a peripheral in the APB
domain is on going. In this case, wait states are inserted until the access to APB peripheral
is finished.

Note:

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When the peripheral clock is not active, the peripheral register values may not be readable
by software and the returned value is always 0x0.

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RM0360

31
Res.

Reset and clock control (RCC)

30
Res.

29
Res.

28
Res.

27
Res.

26
Res.

25

24

Res.

Res.

23

22

Res.

DBG
MCUEN

21
Res.

20
Res.

19

18

17

16

Res.

TIM17
EN

TIM16
EN

TIM15EN

rw

rw

rw

rw
15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Res.

USART1
EN

Res.

SPI1EN

TIM1EN

Res.

ADCEN

Res.

Res.

Res.

USART6
EN

Res.

Res.

Res.

Res.

SYSCFG
COMPEN

rw

rw

rw

rw

rw

rw

Bits 31:23 Reserved, must be kept at reset value.
Bit 22 DBGMCUEN MCU debug module clock enable
Set and reset by software.
0: MCU debug module clock disabled
1: MCU debug module enabled
Bits 21:19 Reserved, must be kept at reset value.
Bit 18 TIM17EN: TIM17 timer clock enable
Set and cleared by software.
0: TIM17 timer clock disabled
1: TIM17 timer clock enabled
Bit 17 TIM16EN: TIM16 timer clock enable
Set and cleared by software.
0: TIM16 timer clock disabled
1: TIM16 timer clock enabled
Bit 16 TIM15EN: TIM15 timer clock enable
Set and cleared by software.
0: TIM15 timer clock disabled
1: TIM15 timer clock enabled
Bit 15 Reserved, must be kept at reset value.
Bit 14 USART1EN: USART1 clock enable
Set and cleared by software.
0: USART1clock disabled
1: USART1clock enabled
Bit 13 Reserved, must be kept at reset value.
Bit 12 SPI1EN: SPI1 clock enable
Set and cleared by software.
0: SPI1 clock disabled
1: SPI1 clock enabled
Bit 11 TIM1EN: TIM1 timer clock enable
Set and cleared by software.
0: TIM1 timer clock disabled
1: TIM1P timer clock enabled
Bit 10 Reserved, must be kept at reset value.

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RM0360

Bit 9 ADCEN: ADC interface clock enable
Set and cleared by software.
0: ADC interface disabled
1: ADC interface clock enabled
Bits 8:6 Reserved, must be kept at reset value.
Bit 5 USART6EN: USART6 clock enable
Set and cleared by software.
0: USART6clock disabled
1: USART6clock enabled
Bits 4:1 Reserved, must be kept at reset value.
Bit 0 SYSCFGEN: SYSCFG clock enable
Set and cleared by software.
0: SYSCFG clock disabled
1: SYSCFG clock enabled

7.4.8

APB peripheral clock enable register 1 (RCC_APB1ENR)
Address: 0x1C
Reset value: 0x0000 0000
Access: word, half-word and byte access
No wait state, except if the access occurs while an access to a peripheral on APB domain is
on going. In this case, wait states are inserted until this access to APB peripheral is finished.

Note:

31
Res.

When the peripheral clock is not active, the peripheral register values may not be readable
by software and the returned value is always 0x0.
30
Res.

29

28

Res.

PWR
EN

27
Res.

26
Res.

25
Res.

24

23

22

21

Res.

USB
EN

I2C2
EN

I2C1
EN

rw

rw

rw

rw

rw

rw

rw

rw

20

19

18

USART5 USART4 USART3
EN
EN
EN

17

16

USART2
EN

Res.

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Res.

SPI2
EN

Res.

Res.

WWDG
EN

Res.

Res.

TIM14
EN

Res.

Res.

TIM7
EN

TIM6
EN

Res.

Res.

TIM3
EN

Res.

rw

rw

rw

rw

rw

Bit 31:29 Reserved, must be kept at reset value.
Bit 28 PWREN: Power interface clock enable
Set and cleared by software.
0: Power interface clock disabled
1: Power interface clock enabled
Bit 27:24 Reserved, must be kept at reset value.
Bit 23 USBEN: USB interface clock enable
Set and cleared by software.
0: USB interface clock disabled
1: USB interface clock enabled

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RM0360

Reset and clock control (RCC)

Bit 22 I2C2EN: I2C2 clock enable
Set and cleared by software.
0: I2C2 clock disabled
1: I2C2 clock enabled
Bit 21 I2C1EN: I2C1 clock enable
Set and cleared by software.
0: I2C1 clock disabled
1: I2C1 clock enabled
Bit 20 USART5EN: USART5 clock enable
Set and cleared by software.
0: USART5 clock disabled
1: USART5 clock enabled
Bit 19 USART4EN: USART4 clock enable
Set and cleared by software.
0: USART4 clock disabled
1: USART4 clock enabled
Bit 18 USART3EN: USART3 clock enable
Set and cleared by software.
0: USART3 clock disabled
1: USART3 clock enabled
Bit 17 USART2EN: USART2 clock enable
Set and cleared by software.
0: USART2 clock disabled
1: USART2 clock enabled
Bits 16:15 Reserved, must be kept at reset value.
Bit 14 SPI2EN: SPI2 clock enable
Set and cleared by software.
0: SPI2 clock disabled
1: SPI2 clock enabled
Bits 13:12 Reserved, must be kept at reset value.
Bit 11 WWDGEN: Window watchdog clock enable
Set and cleared by software.
0: Window watchdog clock disabled
1: Window watchdog clock enabled
Bits 10:9 Reserved, must be kept at reset value.
Bit 8 TIM14EN: TIM14 timer clock enable
Set and cleared by software.
0: TIM14 clock disabled
1: TIM14 clock enabled
Bits 7:6 Reserved, must be kept at reset value.
Bit 5 TIM7EN: TIM7 timer clock enable (not available on STM32F070x6, nor STM32F030x4/6/8/C
devices.)
Set and cleared by software.
0: TIM7 clock disabled
1: TIM7 clock enabled

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RM0360

Bit 4 TIM6EN: TIM6 timer clock enable
Set and cleared by software.
0: TIM6 clock disabled
1: TIM6 clock enabled
Bits 3:2 Reserved, must be kept at reset value.
Bit 1 TIM3EN: TIM3 timer clock enable
Set and cleared by software.
0: TIM3 clock disabled
1: TIM3 clock enabled
Bit 0 Reserved, must be kept at reset value.

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RM0360

Reset and clock control (RCC)

7.4.9

RTC domain control register (RCC_BDCR)
Address offset: 0x20
Reset value: 0x0000 0018, reset by RTC domain reset.
Access: 0 ≤ wait state ≤ 3, word, half-word and byte access
Wait states are inserted in case of successive accesses to this register.

Note:

The LSEON, LSEBYP, RTCSEL and RTCEN bits of the RTC domain control register
(RCC_BDCR) are in the RTC domain. As a result, after Reset, these bits are write-protected
and the DBP bit in the Power control register (PWR_CR) has to be set before these can be
modified. Refer to Section 6.1.2: Voltage regulator for further information. These bits are
only reset after a RTC domain reset (see Section 7.1.3: RTC domain reset). Any internal or
external Reset will not have any effect on these bits.

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

BDRST
rw

15
RTC
EN
rw

14
Res.

13
Res.

12
Res.

11
Res.

10
Res.

9

8

RTCSEL[1:0]
rw

7
Res.

6
Res.

rw

5
Res.

4

3

LSEDRV[1:0]
rw

rw

2

1

0

LSE
BYP

LSE
RDY

LSEON

rw

r

rw

Bits 31:17 Reserved, must be kept at reset value.
Bit 16 BDRST: RTC domain software reset
Set and cleared by software.
0: Reset not activated
1: Resets the entire RTC domain
Bit 15 RTCEN: RTC clock enable
Set and cleared by software.
0: RTC clock disabled
1: RTC clock enabled
Bits 14:10 Reserved, must be kept at reset value.
Bits 9:8 RTCSEL[1:0]: RTC clock source selection
Set by software to select the clock source for the RTC. Once the RTC clock source has been
selected, it cannot be changed anymore unless the RTC domain is reset. The BDRST bit can
be used to reset them.
00: No clock
01: LSE oscillator clock used as RTC clock
10: LSI oscillator clock used as RTC clock
11: HSE oscillator clock divided by 32 used as RTC clock
Bits 7:5 Reserved, must be kept at reset value.

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Reset and clock control (RCC)

RM0360

Bits 4:3 LSEDRV LSE oscillator drive capability
Set and reset by software to modulate the LSE oscillator’s drive capability. A reset of the RTC
domain restores the default value.
00: ‘Xtal mode’ lower driving capability
01: ‘Xtal mode’ medium high driving capability
10: ‘Xtal mode’ medium low driving capability
11: ‘Xtal mode’ higher driving capability (reset value)
Note: The oscillator is in Xtal mode when it is not in bypass mode.
Bit 2 LSEBYP: LSE oscillator bypass
Set and cleared by software to bypass oscillator in debug mode. This bit can be written only
when the external 32 kHz oscillator is disabled.
0: LSE oscillator not bypassed
1: LSE oscillator bypassed
Bit 1 LSERDY: LSE oscillator ready
Set and cleared by hardware to indicate when the external 32 kHz oscillator is stable. After the
LSEON bit is cleared, LSERDY goes low after 6 external low-speed oscillator clock cycles.
0: LSE oscillator not ready
1: LSE oscillator ready
Bit 0 LSEON: LSE oscillator enable
Set and cleared by software.
0: LSE oscillator OFF
1: LSE oscillator ON

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RM0360

Reset and clock control (RCC)

7.4.10

Control/status register (RCC_CSR)
Address: 0x24
Reset value: 0xXXX0 0000, reset by system Reset, except reset flags by power Reset only.
Access: 0 ≤ wait state ≤ 3, word, half-word and byte access
Wait states are inserted in case of successive accesses to this register.

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

LPWR
RSTF

WWDG
RSTF

IWDG
RSTF

SFT
RSTF

POR
RSTF

PIN
RSTF

OB
LRSTF

RMVF

V18PWR
RSTF

Res.

Res.

Res.

Res.

Res.

Res.

Res.

r

r

r

r

r

r

r

rt_w

r

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

LSI
RDY

LSION

r

rw

Bit 31 LPWRRSTF: Low-power reset flag
Set by hardware when a Low-power management reset occurs.
Cleared by writing to the RMVF bit.
0: No Low-power management reset occurred
1: Low-power management reset occurred
For further information on Low-power management reset, refer to Low-power management
reset.
Bit 30 WWDGRSTF: Window watchdog reset flag
Set by hardware when a window watchdog reset occurs.
Cleared by writing to the RMVF bit.
0: No window watchdog reset occurred
1: Window watchdog reset occurred
Bit 29 IWDGRSTF: Independent watchdog reset flag
Set by hardware when an independent watchdog reset from VDD domain occurs.
Cleared by writing to the RMVF bit.
0: No watchdog reset occurred
1: Watchdog reset occurred
Bit 28 SFTRSTF: Software reset flag
Set by hardware when a software reset occurs.
Cleared by writing to the RMVF bit.
0: No software reset occurred
1: Software reset occurred
Bit 27 PORRSTF: POR/PDR reset flag
Set by hardware when a POR/PDR reset occurs.
Cleared by writing to the RMVF bit.
0: No POR/PDR reset occurred
1: POR/PDR reset occurred

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Reset and clock control (RCC)

RM0360

Bit 26 PINRSTF: PIN reset flag
Set by hardware when a reset from the NRST pin occurs.
Cleared by writing to the RMVF bit.
0: No reset from NRST pin occurred
1: Reset from NRST pin occurred
Bit 25 OBLRSTF: Option byte loader reset flag
Set by hardware when a reset from the OBL occurs.
Cleared by writing to the RMVF bit.
0: No reset from OBL occurred
1: Reset from OBL occurred
Bit 24 RMVF: Remove reset flag
Set by software to clear the reset flags including RMVF.
0: No effect
1: Clear the reset flags
Bit 23 V18PWRRSTF: Reset flag of the 1.8 V domain.
Set by hardware when a POR/PDR of the 1.8 V domain occurred.
Cleared by writing to the RMVF bit.
0: No POR/PDR reset of the 1.8 V domain occurred
1: POR/PDR reset of the 1.8 V domain occurred
Bits 22:2 Reserved, must be kept at reset value.
Bit 1 LSIRDY: LSI oscillator ready
Set and cleared by hardware to indicate when the LSI oscillator is stable. After the LSION bit is
cleared, LSIRDY goes low after 3 LSI oscillator clock cycles.
0: LSI oscillator not ready
1: LSI oscillator ready
Bit 0 LSION: LSI oscillator enable
Set and cleared by software.
0: LSI oscillator OFF
1: LSI oscillator ON

7.4.11

AHB peripheral reset register (RCC_AHBRSTR)
Address: 0x28
Reset value: 0x0000 0000
Access: no wait states, word, half-word and byte access

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

IOPF
RST

Res.

IOPD
RST

IOPC
RST

IOPB
RST

IOPA
RST

Res.

rw

rw

rw

rw

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

rw

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RM0360

Reset and clock control (RCC)

Bits 31:23 Reserved, must be kept at reset value.
Bit 22 IOPFRST: I/O port F reset
Set and cleared by software.
0: No effect
1: Reset I/O port F
Bit 21 Reserved, must be kept at reset value.
Bit 20 IOPDRST: I/O port D reset
Set and cleared by software.
0: No effect
1: Reset I/O port D
Bit 19 IOPCRST: I/O port C reset
Set and cleared by software.
0: No effect
1: Reset I/O port C
Bit 18 IOPBRST: I/O port B reset
Set and cleared by software.
0: No effect
1: Reset I/O port B
Bit 17 IOPARST: I/O port A reset
Set and cleared by software.
0: No effect
1: Reset I/O port A
Bits 16:0 Reserved, must be kept at reset value.

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Reset and clock control (RCC)

7.4.12

RM0360

Clock configuration register 2 (RCC_CFGR2)
Address: 0x2C
Reset value: 0x0000 0000
Access: no wait states, word, half-word and byte access

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

3

2

1

0

15

14

13

12

11

10

9

8

7

6

5

4

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

PREDIV[3:0]
rw

rw

rw

rw

Bits 31:4 Reserved, must be kept at reset value.
Bits 3:0 PREDIV[3:0] PREDIV division factor
These bits are set and cleared by software to select PREDIV division factor. They can be
written only when the PLL is disabled.
Note: Bit 0 is the same bit as bit 17 in Clock configuration register (RCC_CFGR), so
modifying bit 17 Clock configuration register (RCC_CFGR) also modifies bit 0 in Clock
configuration register 2 (RCC_CFGR2) (for compatibility with other STM32 products)
0000: PREDIV input clock not divided
0001: PREDIV input clock divided by 2
0010: PREDIV input clock divided by 3
0011: PREDIV input clock divided by 4
0100: PREDIV input clock divided by 5
0101: PREDIV input clock divided by 6
0110: PREDIV input clock divided by 7
0111: PREDIV input clock divided by 8
1000: PREDIV input clock divided by 9
1001: PREDIV input clock divided by 10
1010: PREDIV input clock divided by 11
1011: PREDIV input clock divided by 12
1100: PREDIV input clock divided by 13
1101: PREDIV input clock divided by 14
1110: PREDIV input clock divided by 15
1111: PREDIV input clock divided by 16

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RM0360

Reset and clock control (RCC)

7.4.13

Clock configuration register 3 (RCC_CFGR3)
Address: 0x30
Reset value: 0x0000 0000
Access: no wait states, word, half-word and byte access

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Res.

ADC
SW

USB
SW

Res.

I2C1
SW

Res.

Res.

rw

rw

Res.

Res.

Res.

Res.

Res.

Res.

Res.

rw

USART1SW[1:0]
rw

rw

Bits 31:9 Reserved, must be kept at reset value.
Bit 8 ADCSW: ADC clock source selection
Obsolete setting. To be kept at reset value, connecting the HSI14 clock to the ADC
asynchronous clock input. Proper ADC clock selection is done inside the ADC_CFGR2 (refer
to Section 12.11.5: ADC configuration register 2 (ADC_CFGR2) on page 216).
Bit 7 USBSW: USB clock source selection
This bit is set and cleared by software to select the USB clock source.
0: USB clock disabled (default)
1: PLL clock (PLLCLK) selected as USB clock
Bit 6:5 Reserved, must be kept at reset value.
Bit 4 I2C1SW: I2C1 clock source selection
This bit is set and cleared by software to select the I2C1 clock source.
0: HSI clock selected as I2C1 clock source (default)
1: System clock (SYSCLK) selected as I2C1 clock
Bits 3:2 Reserved, must be kept at reset value.
Bits 1:0 USART1SW[1:0]: USART1 clock source selection
This bit is set and cleared by software to select the USART1 clock source.
00: PCLK selected as USART1 clock source (default)
01: System clock (SYSCLK) selected as USART1 clock
10: LSE clock selected as USART1 clock
11: HSI clock selected as USART1 clock

7.4.14

Clock control register 2 (RCC_CR2)
Address: 0x34
Reset value: 0xXX00 XX80, where X is undefined.
Access: no wait states, word, half-word and byte access

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

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Reset and clock control (RCC)

15

14

13

12

11

RM0360

10

9

8

7

6

HSI14CAL[7:0]
r

r

r

r

r

5

4

3

HSI14TRIM[4:0]
r

r

r

rw

rw

rw

rw

rw

2

1

0

HSI14
DIS

HSI14
RDY

HSI14
ON

rw

r

rw

Bits 31:16 Reserved, must be kept at reset value.
Bits 15:8 HSI14CAL[7:0]: HSI14 clock calibration
These bits are initialized automatically at startup.
Bits 7:3 HSI14TRIM[4:0]: HSI14 clock trimming
These bits provide an additional user-programmable trimming value that is added to the
HSI14CAL[7:0] bits. It can be programmed to adjust to variations in voltage and temperature
that influence the frequency of the HSI14.
The default value is 16, which, when added to the HSI14CAL value, should trim the HSI14 to
14 MHz ± 1%. The trimming step is around 50 kHz between two consecutive HSI14CAL steps.
Bit 2 HSI14DIS HSI14 clock request from ADC disable
Set and cleared by software.
When set this bit prevents the ADC interface from enabling the HSI14 oscillator.
0: ADC interface can turn on the HSI14 oscillator
1: ADC interface can not turn on the HSI14 oscillator
Bit 1 HSI14RDY: HSI14 clock ready flag
Set by hardware to indicate that HSI14 oscillator is stable. After the HSI14ON bit is cleared,
HSI14RDY goes low after 6 HSI14 oscillator clock cycles.
0: HSI14 oscillator not ready
1: HSI14 oscillator ready
Bit 0 HSI14ON: HSI14 clock enable
Set and cleared by software.
0: HSI14 oscillator OFF
1: HSI14 oscillator ON

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0x24

RCC_CSR

Reset value

X

X X X

X X

Reset value

DocID025023 Rev 4

0

0

0

0

0

LSEON

0

0

0

0

LSION

LSE
DRV
[1:0]
Res.

0
1

0
SYSCFGEN

DMAEN

Res.

SRAMEN

Res.
Res.

TIM3RST

0

Res.

Res.

Res.

0

TIM3EN

1

LSEBYP

TM6RST
Res.

PLLRDYF
HSERDYF
HSIRDYF
LSERDYF
LSIRDYF

0
0
0
0
0

Res.
Res.
Res.
Res.
SYSCFGRST

HSION

0
1
1

SWS
[1:0]
SW
[1:0]

Res.
HSIRDY

HPRE[3:0]

LSERDY

FLITFEN
Res.

0

0
0
0
0
0
0
0

Res.
HSI14 RDYF

0

Res.

TM7RST

HSITRIM[4:0]

Res.

0
TIM6EN
Res.

0

Res.

0

USART6EN
Res.

CSSF
0
USART6RST
Res.

Res.

0

Res.

0

TIM7EN

0

Res.

Res.

0

CRCEN
Res.

0

Res.

0

Res.

0

Res.

LSIRDYIE

0

Res.

0

Res.

LSERDYIE

0
ADCRST

0

0

Res.

0

RTC
SEL
[1:0]

1

Res.

0
Res.

Res.
TIM14RST
Res.

HSIRDYIE

PPRE
[2:0]

Res.

Res.

Res.

HSERDYIE
0

TIM1RST
Res.

0

Res.

ADCEN
Res.

WWDGRST
Res.

Res.
Res.

ADC PRE

0

Res.

0

Res.

0

TIM14EN
Res.

Res.

Res.

0

Res.

0

0

Res.

0
TIM1EN
Res.

0

WWDGEN
Res.

PLLRDYIE

SPI1RST

0

Res.

Res.

0

Res.

Res.

0

0

Res.

SPI1EN

Res.
HSI14 RDYIE
0

USART1RST
Res.

0

Res.

0
SPI2RST
Res.

HSEON

HSICAL[7:0]

LSIRDY

X X
0

Res.

0
0

Res.

0

0

Res.

0
Res.

0

Res.

0

USART1EN
Res.

0

SPI2EN
Res.

0

0

Res.

PLLSRC
0
Res.

0

0

Res.

LSIRDYC

0

Res.

0

TIM15RST

0

Res.

0

Res.

HSEBYP
HSERDY
PLLXTPRE

0

Res.

0

TIM15 EN

0

TIM16RST

PLLMUL[3:0]

Res.

0

Res.

HSIRDYC
LSERDYC

0

TIM17RST

Res.

Res.

CSSON

Res.

PLL ON
Res.

0

Res.

0
USART2RST
Res.

0

Res.

Res.

PLL RDY

Res.

Res.

Res.

Res.

Res.

Res.

0

Res.

0

BDRST

0

TIM16 EN

USART3RST

0
IOPAEN
Res.

IOPBEN

0

TIM17 EN

Res.

HSERDYC

Res.

0

Res.

Res.

PLLRDYC

Res.

0

Res.

Res.

HSI14 RDYC

Res.

0

DBGMCURST
Res.

Res.

0

RTCEN
Res.

0

Res.

0

Res.

0
USART2EN
Res.

USART3EN

0

Res.

Res.

0

Res.

USART4RST

0

IOPCEN
0

Res.

0

Res.
0

Res.

USART4EN

Reset value

Res.

USART5RST

0

USART4RST

I2C1RST

0

Res.

I2C2RST

0

IOPEEN

Res.

0

Res.

USART5EN

Reset value

Res.

DBGMCUEN
Res.

Reset value

Res.

I2C1EN

0
I2C2EN

Reset value

Res.

0

Res.

0

Res.

0

CSSC

0

Res.

Res.

0

Res.

Res.
Res.

0

USBRST

Res.
Res.

0

Res.

Res.

Res.

Res.

Res.

0

USBEN

Res.
Res.

CRSRST
Res.

Res.

Res.

PLL NODIV

Reset value
MCO [3:0]

Res.

Res.

Res.

Res.

Res.

Res.
PWRRST

Res.

Res.

0

RMVF
Res.

OBLRSTF

Res.

Res.

Res.
0

Res.

Res.

Res.

Res.

Reset value

Res.

CRSEN
Res.

Res.

Res.
0

Res.

0

Res.

Res.
PWREN

Res.

RCC_CFGR
MCOPRE
[2:0]

PINRSTF

RCC_BDCR

Res.

Reset value

PORRSTF

0x20
RCC_APB1ENR

Res.

0x1C
RCC_APB2ENR
Res.

Reset value

SFTRSTF

0x18
RCC_AHBENR

IWDGRSTF

0x14
RCC_APB1RSTR

Res.

0x010
RCC_APB2RSTR

Res.

0x0C
RCC_CIR

Res.

0x08

Res.

0x04
RCC_CR

Res.

0x00

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0

Register

Res.

Offset

LPWRSTF

7.4.15

WWDGRSTF

RM0360
Reset and clock control (RCC)

RCC register map
The following table gives the RCC register map and the reset values.
Table 21. RCC register map and reset values

0

0

0

0

0

0

0

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126

0x34

126/779
RCC_CR2

Reset value

DocID025023 Rev 4
X X X
X X X

Reset value
0

HSI14CAL[7:0]
X X

Refer to Section 2.2.2 on page 37 for the register boundary addresses.
1
0

0

0
0
0

0

HSI14ON

HSI14TRIM[14:0]

0

HSI14RDY

0
HSI14DIS

0
USART1SW[1:0]

0

Res.

Reset value

I2C1SW
Res.

Res.

USBSW
Res.

ADCSW

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

IOPA RST

Res.

Res.

IOPB RST
0
Res.

IOPC RST
0

Res.

Res.

Res.

Res.

Res.
IOPD RST
0

Res.

Res.

IOPF RST

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

0

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

0

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Reset value

Res.

Res.

Res.

Res.

Res.

Res.

Res.

RCC_CFGR3

Res.

0x30
RCC_CFGR2

Res.

0x2C
RCC_AHBRSTR

Res.

0x28

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0

Register

Res.

Offset

Res.

Reset and clock control (RCC)
RM0360

Table 21. RCC register map and reset values (continued)

PREDIV[3:0]
0
0

0
0
0

RM0360

General-purpose I/Os (GPIO)

8

General-purpose I/Os (GPIO)

8.1

Introduction
Each general-purpose I/O port has four 32-bit configuration registers (GPIOx_MODER,
GPIOx_OTYPER, GPIOx_OSPEEDR and GPIOx_PUPDR), two 32-bit data registers
(GPIOx_IDR and GPIOx_ODR) and a 32-bit set/reset register (GPIOx_BSRR). Ports A and
B also have a 32-bit locking register (GPIOx_LCKR) and two 32-bit alternate function
selection registers (GPIOx_AFRH and GPIOx_AFRL).
On STM32F030xB and STM32F030xC devices, also ports C and D have two 32-bit
alternate function selection registers (GPIOx_AFRH and GPIOx_AFRL).

8.2

8.3

GPIO main features


Output states: push-pull or open drain + pull-up/down



Output data from output data register (GPIOx_ODR) or peripheral (alternate function
output)



Speed selection for each I/O



Input states: floating, pull-up/down, analog



Input data to input data register (GPIOx_IDR) or peripheral (alternate function input)



Bit set and reset register (GPIOx_ BSRR) for bitwise write access to GPIOx_ODR



Locking mechanism (GPIOx_LCKR) provided to freeze the port A or B I/O port
configuration.



Analog function



Alternate function selection registers(at most 16 AFs possible per I/O)



Fast toggle capable of changing every two clock cycles



Highly flexible pin multiplexing allows the use of I/O pins as GPIOs or as one of several
peripheral functions

GPIO functional description
Subject to the specific hardware characteristics of each I/O port listed in the datasheet, each
port bit of the general-purpose I/O (GPIO) ports can be individually configured by software in
several modes:


Input floating



Input pull-up



Input-pull-down



Analog



Output open-drain with pull-up or pull-down capability



Output push-pull with pull-up or pull-down capability



Alternate function push-pull with pull-up or pull-down capability



Alternate function open-drain with pull-up or pull-down capability

Each I/O port bit is freely programmable, however the I/O port registers have to be
accessed as 32-bit words, half-words or bytes. The purpose of the GPIOx_BSRR and
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RM0360

GPIOx_BRR registers is to allow atomic read/modify accesses to any of the GPIOx_ODR
registers. In this way, there is no risk of an IRQ occurring between the read and the modify
access.
Figure 14 shows the basic structures of a standard I/O port bit. Table 22 gives the possible
port bit configurations.
Figure 14. Basic structure of an I/O port bit
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Table 22. Port bit configuration table(1)
MODER(i)
[1:0]

01

128/779

OTYPER(i)

OSPEEDR(i)
[1:0]

PUPDR(i)
[1:0]

I/O configuration

0

0

0

GP output

PP

0

0

1

GP output

PP + PU

0

1

0

GP output

PP + PD

1

1

Reserved

0

0

GP output

OD

1

0

1

GP output

OD + PU

1

1

0

GP output

OD + PD

1

1

1

Reserved (GP output OD)

0
1

SPEED
[1:0]

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RM0360

General-purpose I/Os (GPIO)
Table 22. Port bit configuration table(1) (continued)
MODER(i)
[1:0]

10

00

11

OTYPER(i)

OSPEEDR(i)
[1:0]

PUPDR(i)
[1:0]

I/O configuration

0

0

0

AF

PP

0

0

1

AF

PP + PU

0

1

0

AF

PP + PD

1

1

Reserved

0

0

AF

OD

1

0

1

AF

OD + PU

1

1

0

AF

OD + PD

1

1

1

Reserved

0

SPEED
[1:0]

1

x

x

x

0

0

Input

Floating

x

x

x

0

1

Input

PU

x

x

x

1

0

Input

PD

x

x

x

1

1

Reserved (input floating)

x

x

x

0

0

Input/output

x

x

x

0

1

x

x

x

1

0

x

x

x

1

1

Analog

Reserved

1. GP = general-purpose, PP = push-pull, PU = pull-up, PD = pull-down, OD = open-drain, AF = alternate
function.

8.3.1

General-purpose I/O (GPIO)
During and just after reset, the alternate functions are not active and most of the I/O ports
are configured in input floating mode.
The debug pins are in AF pull-up/pull-down after reset:


PA14: SWCLK in pull-down



PA13: SWDIO in pull-up

When the pin is configured as output, the value written to the output data register
(GPIOx_ODR) is output on the I/O pin. It is possible to use the output driver in push-pull
mode or open-drain mode (only the low level is driven, high level is HI-Z).
The input data register (GPIOx_IDR) captures the data present on the I/O pin at every AHB
clock cycle.
All GPIO pins have weak internal pull-up and pull-down resistors, which can be activated or
not depending on the value in the GPIOx_PUPDR register.

8.3.2

I/O pin alternate function multiplexer and mapping
The device I/O pins are connected to on-board peripherals/modules through a multiplexer
that allows only one peripheral alternate function (AF) connected to an I/O pin at a time. In
this way, there can be no conflict between peripherals available on the same I/O pin.

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Each I/O pin has a multiplexer with up to sixteen alternate function inputs (AF0 to AF15) that
can be configured through the GPIOx_AFRL (for pin 0 to 7) and GPIOx_AFRH (for pin 8 to
15) registers:


After reset the multiplexer selection is alternate function 0 (AF0). The I/Os are
configured in alternate function mode through GPIOx_MODER register.



The specific alternate function assignments for each pin are detailed in the device
datasheet.

In addition to this flexible I/O multiplexing architecture, each peripheral has alternate
functions mapped onto different I/O pins to optimize the number of peripherals available in
smaller packages.
To use an I/O in a given configuration, the user has to proceed as follows:


Debug function: after each device reset these pins are assigned as alternate function
pins immediately usable by the debugger host



GPIO: configure the desired I/O as output, input or analog in the GPIOx_MODER
register.



Peripheral alternate function:



–

Connect the I/O to the desired AFx in one of the GPIOx_AFRL or GPIOx_AFRH
register.

–

Select the type, pull-up/pull-down and output speed via the GPIOx_OTYPER,
GPIOx_PUPDR and GPIOx_OSPEEDER registers, respectively.

–

Configure the desired I/O as an alternate function in the GPIOx_MODER register.

Additional functions:
–

For the ADC, configure the desired I/O in analog mode in the GPIOx_MODER
register and configure the required function in the ADC registers.

–

For the additional functions like RTC, WKUPx and oscillators, configure the
required function in the related RTC, PWR and RCC registers. These functions
have priority over the configuration in the standard GPIO registers.

Please refer to the “Alternate function mapping” table in the device datasheet for the
detailed mapping of the alternate function I/O pins.

8.3.3

I/O port control registers
Each of the GPIO ports has four 32-bit memory-mapped control registers (GPIOx_MODER,
GPIOx_OTYPER, GPIOx_OSPEEDR, GPIOx_PUPDR) to configure up to 16 I/Os. The
GPIOx_MODER register is used to select the I/O mode (input, output, AF, analog). The
GPIOx_OTYPER and GPIOx_OSPEEDR registers are used to select the output type (pushpull or open-drain) and speed. The GPIOx_PUPDR register is used to select the pullup/pull-down whatever the I/O direction.

8.3.4

I/O port data registers
Each GPIO has two 16-bit memory-mapped data registers: input and output data registers
(GPIOx_IDR and GPIOx_ODR). GPIOx_ODR stores the data to be output, it is read/write
accessible. The data input through the I/O are stored into the input data register
(GPIOx_IDR), a read-only register.
See Section 8.4.5: GPIO port input data register (GPIOx_IDR) (x = A..D, F) and
Section 8.4.6: GPIO port output data register (GPIOx_ODR) (x = A..D, F) for the register
descriptions.

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RM0360

8.3.5

General-purpose I/Os (GPIO)

I/O data bitwise handling
The bit set reset register (GPIOx_BSRR) is a 32-bit register which allows the application to
set and reset each individual bit in the output data register (GPIOx_ODR). The bit set reset
register has twice the size of GPIOx_ODR.
To each bit in GPIOx_ODR, correspond two control bits in GPIOx_BSRR: BS(i) and BR(i).
When written to 1, bit BS(i) sets the corresponding ODR(i) bit. When written to 1, bit BR(i)
resets the ODR(i) corresponding bit.
Writing any bit to 0 in GPIOx_BSRR does not have any effect on the corresponding bit in
GPIOx_ODR. If there is an attempt to both set and reset a bit in GPIOx_BSRR, the set
action takes priority.
Using the GPIOx_BSRR register to change the values of individual bits in GPIOx_ODR is a
“one-shot” effect that does not lock the GPIOx_ODR bits. The GPIOx_ODR bits can always
be accessed directly. The GPIOx_BSRR register provides a way of performing atomic
bitwise handling.
There is no need for the software to disable interrupts when programming the GPIOx_ODR
at bit level: it is possible to modify one or more bits in a single atomic AHB write access.

8.3.6

GPIO locking mechanism
It is possible to freeze the port A and B GPIO control registers by applying a specific write
sequence to the GPIOx_LCKR register. The frozen registers are GPIOx_MODER,
GPIOx_OTYPER, GPIOx_OSPEEDR, GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
To write the GPIOx_LCKR register, a specific write / read sequence has to be applied. When
the right LOCK sequence is applied to bit 16 in this register, the value of LCKR[15:0] is used
to lock the configuration of the I/Os (during the write sequence the LCKR[15:0] value must
be the same). When the LOCK sequence has been applied to a port bit, the value of the port
bit can no longer be modified until the next MCU reset or peripheral reset. Each
GPIOx_LCKR bit freezes the corresponding bit in the control registers (GPIOx_MODER,
GPIOx_OTYPER, GPIOx_OSPEEDR, GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
The LOCK sequence (refer to Section 8.4.8: GPIO port configuration lock register
(GPIOx_LCKR) (x = A..B)) can only be performed using a word (32-bit long) access to the
GPIOx_LCKR register due to the fact that GPIOx_LCKR bit 16 has to be set at the same
time as the [15:0] bits.
For more details please refer to LCKR register description in Section 8.4.8: GPIO port
configuration lock register (GPIOx_LCKR) (x = A..B).

8.3.7

I/O alternate function input/output
Two registers are provided to select one of the alternate function inputs/outputs available for
each I/O. With these registers, the user can connect an alternate function to some other pin
as required by the application.
This means that a number of possible peripheral functions are multiplexed on each GPIO
using the GPIOx_AFRL and GPIOx_AFRH alternate function registers. The application can
thus select any one of the possible functions for each I/O. The AF selection signal being
common to the alternate function input and alternate function output, a single channel is
selected for the alternate function input/output of a given I/O.

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For code example refer to the Appendix section A.4.2: Alternate function selection
sequence code example.
To know which functions are multiplexed on each GPIO pin, refer to the device datasheet.

8.3.8

External interrupt/wakeup lines
All ports have external interrupt capability. To use external interrupt lines, the given pin must
not be configured in analog mode or being used as oscillator pin, so the input trigger is kept
enabled. Refer to Section 11.2: Extended interrupts and events controller (EXTI) and to
Section 11.2.3: Event management.

8.3.9

Input configuration
When the I/O port is programmed as input:


The output buffer is disabled



The Schmitt trigger input is activated



The pull-up and pull-down resistors are activated depending on the value in the
GPIOx_PUPDR register



The data present on the I/O pin are sampled into the input data register every AHB
clock cycle



A read access to the input data register provides the I/O state

Figure 15 shows the input configuration of the I/O port bit.

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RM0360

8.3.10

General-purpose I/Os (GPIO)

Output configuration
When the I/O port is programmed as output:


The output buffer is enabled:
–

Open drain mode: A “0” in the Output register activates the N-MOS whereas a “1”
in the Output register leaves the port in Hi-Z (the P-MOS is never activated)

–

Push-pull mode: A “0” in the Output register activates the N-MOS whereas a “1” in
the Output register activates the P-MOS



The Schmitt trigger input is activated



The pull-up and pull-down resistors are activated depending on the value in the
GPIOx_PUPDR register



The data present on the I/O pin are sampled into the input data register every AHB
clock cycle



A read access to the input data register gets the I/O state



A read access to the output data register gets the last written value

Figure 16 shows the output configuration of the I/O port bit.

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8.3.11

Alternate function configuration
When the I/O port is programmed as alternate function:


The output buffer can be configured in open-drain or push-pull mode



The output buffer is driven by the signals coming from the peripheral (transmitter
enable and data)



The Schmitt trigger input is activated



The weak pull-up and pull-down resistors are activated or not depending on the value
in the GPIOx_PUPDR register



The data present on the I/O pin are sampled into the input data register every AHB
clock cycle



A read access to the input data register gets the I/O state

Figure 17 shows the Alternate function configuration of the I/O port bit.

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RM0360
Figure 17. Alternate function configuration

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8.3.12

Analog configuration
When the I/O port is programmed as analog configuration:


The output buffer is disabled



The Schmitt trigger input is deactivated, providing zero consumption for every analog
value of the I/O pin. The output of the Schmitt trigger is forced to a constant value (0).



The weak pull-up and pull-down resistors are disabled by hardware



Read access to the input data register gets the value “0”

For code example refer to the Appendix section A.4.3: Analog GPIO configuration code
example.
Figure 18 shows the high-impedance, analog-input configuration of the I/O port bit.

134/779

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General-purpose I/Os (GPIO)
Figure 18. High impedance-analog configuration

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Using the HSE or LSE oscillator pins as GPIOs
When the HSE or LSE oscillator is switched OFF (default state after reset), the related
oscillator pins can be used as normal GPIOs.
When the HSE or LSE oscillator is switched ON (by setting the HSEON or LSEON bit in the
RCC_CSR register) the oscillator takes control of its associated pins and the GPIO
configuration of these pins has no effect.
When the oscillator is configured in a user external clock mode, only the pin is reserved for
clock input and the OSC_OUT or OSC32_OUT pin can still be used as normal GPIO.

8.3.14

Using the GPIO pins in the RTC supply domain
The PC13/PC14/PC15 GPIO functionality is lost when the core supply domain is powered
off (when the device enters Standby mode). In this case, if their GPIO configuration is not
bypassed by the RTC configuration, these pins are set in an analog input mode.
For details about I/O control by the RTC, refer to Section 21.4: RTC functional description
on page 488.

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8.4

RM0360

GPIO registers
This section gives a detailed description of the GPIO registers.
For a summary of register bits, register address offsets and reset values, refer to Table 23.
The peripheral registers can be written in word, half word or byte mode.

8.4.1

GPIO port mode register (GPIOx_MODER) (x =A..D, F)
Address offset:0x00
Reset values:

31

30



0x2800 0000 for port A



0x0000 0000 for other ports
29

MODER15[1:0]

28

MODER14[1:0]

27

26

MODER13[1:0]

25

24

MODER12[1:0]

23

22

MODER11[1:0]

21

20

MODER10[1:0]

19

18

MODER9[1:0]

17

16

MODER8[1:0]

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MODER7[1:0]
rw

rw

MODER6[1:0]
rw

rw

MODER5[1:0]
rw

rw

MODER4[1:0]
rw

rw

MODER3[1:0]
rw

rw

MODER2[1:0]
rw

rw

MODER1[1:0]
rw

rw

MODER0[1:0]
rw

rw

Bits 2y+1:2y MODERy[1:0]: Port x configuration bits (y = 0..15)
These bits are written by software to configure the I/O mode.
00: Input mode (reset state)
01: General purpose output mode
10: Alternate function mode
11: Analog mode

8.4.2

GPIO port output type register (GPIOx_OTYPER) (x = A..D, F)
Address offset: 0x04
Reset value: 0x0000 0000

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

OT15

OT14

OT13

OT12

OT11

OT10

OT9

OT8

OT7

OT6

OT5

OT4

OT3

OT2

OT1

OT0

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 OTy: Port x configuration bits (y = 0..15)
These bits are written by software to configure the I/O output type.
0: Output push-pull (reset state)
1: Output open-drain

136/779

DocID025023 Rev 4

RM0360

General-purpose I/Os (GPIO)

8.4.3

GPIO port output speed register (GPIOx_OSPEEDR)
(x = A..D, F)
Address offset: 0x08
Reset value:

31



0x0C00 0000 for port A



0x0000 0000 for other ports

30

29

OSPEEDR15
[1:0]

28

27

OSPEEDR14
[1:0]

26

25

OSPEEDR13
[1:0]

24

OSPEEDR12
[1:0]

23

22

OSPEEDR11
[1:0]

21

20

OSPEEDR10
[1:0]

19

18

17

16

OSPEEDR9
[1:0]

OSPEEDR8
[1:0]

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

OSPEEDR7
[1:0]

OSPEEDR6
[1:0]

OSPEEDR5
[1:0]

OSPEEDR4
[1:0]

OSPEEDR3
[1:0]

OSPEEDR2
[1:0]

OSPEEDR1
[1:0]

OSPEEDR0
[1:0]

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

Bits 2y+1:2y OSPEEDRy[1:0]: Port x configuration bits (y = 0..15)
These bits are written by software to configure the I/O output speed.
x0: Low speed
01: Medium speed
11: High speed
Note: Refer to the device datasheet for the frequency specifications and the power supply
and load conditions for each speed.

8.4.4

GPIO port pull-up/pull-down register (GPIOx_PUPDR)
(x = A..,D, F)
Address offset: 0x0C
Reset values:

31

30

PUPDR15[1:0]



0x2400 0000 for port A



0x0000 0000 for other ports
29

28

PUPDR14[1:0]

27

26

PUPDR13[1:0]

25

24

PUPDR12[1:0]

23

22

PUPDR11[1:0]

21

20

PUPDR10[1:0]

19

18

PUPDR9[1:0]

17

16

PUPDR8[1:0]

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

PUPDR7[1:0]
rw

rw

PUPDR6[1:0]
rw

rw

PUPDR5[1:0]
rw

rw

PUPDR4[1:0]
rw

rw

PUPDR3[1:0]
rw

rw

PUPDR2[1:0]
rw

rw

PUPDR1[1:0]
rw

rw

PUPDR0[1:0]
rw

rw

Bits 2y+1:2y PUPDRy[1:0]: Port x configuration bits (y = 0..15)
These bits are written by software to configure the I/O pull-up or pull-down
00: No pull-up, pull-down
01: Pull-up
10: Pull-down
11: Reserved

DocID025023 Rev 4

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143

General-purpose I/Os (GPIO)

8.4.5

RM0360

GPIO port input data register (GPIOx_IDR) (x = A..D, F)
Address offset: 0x10
Reset value: 0x0000 XXXX (where X means undefined)

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

IDR15

IDR14

IDR13

IDR12

IDR11

IDR10

IDR9

IDR8

IDR7

IDR6

IDR5

IDR4

IDR3

IDR2

IDR1

IDR0

r

r

r

r

r

r

r

r

r

r

r

r

r

r

r

r

Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 IDRy: Port input data bit (y = 0..15)
These bits are read-only. They contain the input value of the corresponding I/O port.

8.4.6

GPIO port output data register (GPIOx_ODR) (x = A..D, F)
Address offset: 0x14
Reset value: 0x0000 0000

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

15

14

13

12

11

10

ODR15 ODR14 ODR13 ODR12 ODR11 ODR10
rw

rw

rw

rw

rw

rw

9

8

7

6

5

4

3

2

1

0

ODR9

ODR8

ODR7

ODR6

ODR5

ODR4

ODR3

ODR2

ODR1

ODR0

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 ODRy: Port output data bit (y = 0..15)
These bits can be read and written by software.
Note: For atomic bit set/reset, the ODR bits can be individually set and/or reset by writing to
the GPIOx_BSRR or GPIOx_BRR registers (x = A..D, F).

8.4.7

GPIO port bit set/reset register (GPIOx_BSRR) (x = A..D, F)
Address offset: 0x18
Reset value: 0x0000 0000

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

BR15

BR14

BR13

BR12

BR11

BR10

BR9

BR8

BR7

BR6

BR5

BR4

BR3

BR2

BR1

BR0

w

w

w

w

w

w

w

w

w

w

w

w

w

w

w

w

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

BS15

BS14

BS13

BS12

BS11

BS10

BS9

BS8

BS7

BS6

BS5

BS4

BS3

BS2

BS1

BS0

w

w

w

w

w

w

w

w

w

w

w

w

w

w

w

w

138/779

DocID025023 Rev 4

RM0360

General-purpose I/Os (GPIO)

Bits 31:16 BRy: Port x reset bit y (y = 0..15)
These bits are write-only. A read to these bits returns the value 0x0000.
0: No action on the corresponding ODRx bit
1: Resets the corresponding ODRx bit
Note: If both BSx and BRx are set, BSx has priority.
Bits 15:0 BSy: Port x set bit y (y= 0..15)
These bits are write-only. A read to these bits returns the value 0x0000.
0: No action on the corresponding ODRx bit
1: Sets the corresponding ODRx bit

8.4.8

GPIO port configuration lock register (GPIOx_LCKR)
(x = A..B)
This register is used to lock the configuration of the port bits when a correct write sequence
is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the
GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the
LOCK sequence has been applied on a port bit, the value of this port bit can no longer be
modified until the next MCU reset or peripheral reset.

Note:

A specific write sequence is used to write to the GPIOx_LCKR register. Only word access
(32-bit long) is allowed during this locking sequence.
Each lock bit freezes a specific configuration register (control and alternate function
registers).
Address offset: 0x1C
Reset value: 0x0000 0000

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

LCKK
rw

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

LCK15

LCK14

LCK13

LCK12

LCK11

LCK10

LCK9

LCK8

LCK7

LCK6

LCK5

LCK4

LCK3

LCK2

LCK1

LCK0

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

DocID025023 Rev 4

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143

General-purpose I/Os (GPIO)

RM0360

Bits 31:17 Reserved, must be kept at reset value.
Bit 16 LCKK: Lock key
This bit can be read any time. It can only be modified using the lock key write sequence.
0: Port configuration lock key not active
1: Port configuration lock key active. The GPIOx_LCKR register is locked until the next MCU
reset or peripheral reset.
LOCK key write sequence:
WR LCKR[16] = ‘1’ + LCKR[15:0]
WR LCKR[16] = ‘0’ + LCKR[15:0]
WR LCKR[16] = ‘1’ + LCKR[15:0]
RD LCKR
RD LCKR[16] = ‘1’ (this read operation is optional but it confirms that the lock is active)
Note: During the LOCK key write sequence, the value of LCK[15:0] must not change.
Any error in the lock sequence aborts the lock.
After the first lock sequence on any bit of the port, any read access on the LCKK bit will
return ‘1’ until the next MCU reset or peripheral reset.
For code example refer to the Appendix section A.4.1: Lock sequence code example.
Bits 15:0 LCKy: Port x lock bit y (y= 0..15)
These bits are read/write but can only be written when the LCKK bit is ‘0.
0: Port configuration not locked
1: Port configuration locked

GPIO alternate function low register (GPIOx_AFRL) 
(x = A..D, )

8.4.9

Address offset: 0x20
Reset value: 0x0000 0000
31

30

29

28

27

AFSEL7[3:0]
rw
15

rw

rw

rw

rw

14

13

12

11

AFSEL3[3:0]
rw

rw

rw

26

25

24

23

AFSEL6[3:0]
rw

rw

rw

rw

10

9

8

7

AFSEL2[3:0]
rw

rw

rw

rw

22

21

20

19

AFSEL5[3:0]
rw

rw

rw

rw

6

5

4

3

AFSEL1[3:0]
rw

rw

rw

rw

140/779

1000: Reserved
1001: Reserved
1010: Reserved
1011: Reserved
1100: Reserved
1101: Reserved
1110: Reserved
1111: Reserved

DocID025023 Rev 4

17

16

rw

rw

rw

2

1

0

AFSEL0[3:0]
rw

rw

Bits 31:0 AFSELy[3:0]: Alternate function selection for port x pin y (y = 0..7)
These bits are written by software to configure alternate function I/Os
AFSELy selection:
0000: AF0
0001: AF1
0010: AF2
0011: AF3
0100: AF4
0101: AF5
0110: AF6
0111: AF7

18

AFSEL4[3:0]

rw

rw

rw

RM0360

General-purpose I/Os (GPIO)

8.4.10

GPIO alternate function high register (GPIOx_AFRH)
(x = A..D, F)
Address offset: 0x24
Reset value: 0x0000 0000

31

30

29

28

27

AFSEL15[3:0]

26

25

24

23

AFSEL14[3:0]

22

21

20

19

AFSEL13[3:0]

18

17

16

AFSEL12[3:0]

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

AFSEL11[3:0]
rw

rw

rw

AFSEL10[3:0]
rw

rw

rw

rw

AFSEL9[3:0]
rw

rw

rw

rw

AFSEL8[3:0]
rw

rw

rw

rw

rw

Bits 31:0 AFSELy[3:0]: Alternate function selection for port x pin y (y = 8..15)
These bits are written by software to configure alternate function I/Os
AFSELy selection:
0000: AF0
0001: AF1
0010: AF2
0011: AF3
0100: AF4
0101: AF5
0110: AF6
0111: AF7

8.4.11

1000: Reserved
1001: Reserved
1010: Reserved
1011: Reserved
1100: Reserved
1101: Reserved
1110: Reserved
1111: Reserved

GPIO port bit reset register (GPIOx_BRR) (x =A..D, F)
Address offset: 0x28
Reset value: 0x0000 0000

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

BR15

BR14

BR13

BR12

BR11

BR10

BR9

BR8

BR7

BR6

BR5

BR4

BR3

BR2

BR1

BR0

w

w

w

w

w

w

w

w

w

w

w

w

w

w

w

w

Bits 31:16 Reserved
Bits 15:0 BRy: Port x Reset bit y (y= 0..15)
These bits are write-only. A read to these bits returns the value 0x0000
0: No action on the corresponding ODx bit
1: Reset the corresponding ODx bit

DocID025023 Rev 4

141/779
143

0x20

142/779

Reset value

GPIOx_AFRL
(where x = A.., B)

0

0

0

AFSEL7
[3:0]

0

0

0

0

AFSEL6
[3:0]

0

0

0

0

AFSEL5
[3:0]

0

0

BS11

BS9

BS8

BS7

BS6

BS5

BS4

BS3

BS2

BS1

BS0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

LCK9

LCK8

LCK7

LCK6

LCK5

LCK4

LCK3

LCK2

LCK1

LCK0

Reset value

BS10

GPIOx_LCKR
(where x = A..B)

0

LCK11

0

LCK10

0

0

0

0

DocID025023 Rev 4
ODR12
ODR11
ODR10
ODR9
ODR8
ODR7
ODR6
ODR5
ODR4
ODR3
ODR2
ODR1
ODR0

IDR0

0x10
IDR1
0

IDR2
0

IDR3
0

IDR4
0

IDR5
0

IDR6
0

IDR7
0

IDR8
0

IDR9
0

IDR11

0

IDR10
0

IDR12
0

IDR13

Reset value

ODR13

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

GPIOx_OTYPER
(where x = A..F)

0
0

Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

0
0

AFSEL4
[3:0]

0

0
0
0

0
0

0

0

0

0
0

0
0

AFSEL3
[3:0]

0

0

0
0

0
0

0
0

0

0

0
0

0
0

0
0

AFSEL2
[3:0]

0

0

0
0

0
0

0
0

0

0

OT1
OT0

AFSEL1
[3:0]

0

MODER0[1:0]

MODER1[1:0]

0

0
0
0
0

0
0

0
0

OSPEEDR0[1:0]

OT2

0

PUPDR0[1:0]

OT3

MODER2[1:0]

0

OSPEEDR1[1:0]

OT4

0

PUPDR1[1:0]

OT5

MODER3[1:0]

0

OSPEEDR2[1:0]

OT6

MODER4[1:0]

0

PUPDR2[1:0]

OT7
OSPEEDR3[1:0]

OT8

MODER5[1:0]

MODER6[1:0]

MODER7[1:0]

MODER8[1:0]

MODER9[1:0]

MODER10[1:0]

MODER11[1:0]

MODER12[1:0]

MODER13[1:0]

MODER14[1:0]

MODER15[1:0]

0

PUPDR3[1:0]

OT9
OSPEEDR4[1:0]

0

PUPDR4[1:0]

OT11
OT10

OSPEEDR5[1:0]

OT12
0

PUPDR5[1:0]

OT13

OSPEEDR6[1:0]

0

PUPDR6[1:0]

0

0

0

PUPDR0[1:0]

0

0

0

PUPDR1[1:0]

0

0

0

PUPDR2[1:0]

0

0

PUPDR3[1:0]

0

0

PUPDR4[1:0]

0

Res.

0

PUPDR5[1:0]

0

OT14

0

OT15

OSPEEDR7[1:0]

OSPEEDR8[1:0]

Reset value

Res.

0

PUPDR6[1:0]

0
PUPDR7[1:0]

0
PUPDR7[1:0]

PUPDR8[1:0]

0

IDR14

0

PUPDR8[1:0]

0

IDR15

0

Res.

OSPEEDR9[1:0]

OSPEEDR10[1:0]

OSPEEDR11[1:0]

OSPEEDR12[1:0]

OSPEEDR13[1:0]

OSPEEDR14[1:0]

Reset value

ODR14
0

Res.

PUPDR9[1:0]

0

0

ODR15
0

PUPDR9[1:0]

0

0

Res.
0

Res.

0

Res.
0

Res.

0

Res.

PUPDR10[1:0]

0

Res.
0

PUPDR10[1:0]

0

0

BS12

0

Res.

0

Res.

0

0

BS13

0

Res.

0

Res.

0

Res.

PUPDR11[1:0]

0

Res.
0

PUPDR11[1:0]

0

0

LCK12

BR3

0

Res.

0

Res.

0

0

LCK13

BR4

0

Res.

0

Res.

0

Res.

PUPDR12[1:0]

0

Res.

0

PUPDR12[1:0]

1
0

BS14

BR5

0

Res.

0

Res.

0

0

BS15

BR6

0

Res.

0

Res.

0
0

Res.

PUPDR13[1:0]

0

Res.

0
PUPDR13[1:0]

0
0

LCK14

BR7

0

Res.

0

Res.

1
0
0

LCK15

BR8

0

Res.

0

Res.

0
1

Res.

PUPDR14[1:0]

0

Res.

0
PUPDR14[1:0]

0
0
0

BR0

BR9

0

Res.

0

Res.

Reset value
1

BR1

BR11

BR10

0

Res.

Reset value

GPIOx_IDR
(where x = A..F)
Res.

GPIOA_PUPDR
0
0

Res.

Reset value

Res.

0x0C
GPIOx_OSPEEDR
(where x = B..F)
0

Res.

BR12

0

Res.

0x08
OSPEEDR15[1:0]

0x04
GPIOx_MODER
(where x = B..F)

PUPDR15[1:0]

Reset value

LCKK

BR13

Reset value

Res.

GPIOx_PUPDR
(where x = B..D,F)

Res.

0x00
MODER0[1:0]

MODER1[1:0]

MODER2[1:0]

MODER3[1:0]

MODER4[1:0]

MODER5[1:0]

MODER6[1:0]

MODER7[1:0]

MODER8[1:0]

MODER9[1:0]

MODER10[1:0]

MODER11[1:0]

MODER12[1:0]

MODER13[1:0]

MODER14[1:0]

MODER15[1:0]

GPIOA_MODER

PUPDR15[1:0]

0x0C

Res.

0x00

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0

Register

Res.

Offset

BR2

BR14

8.4.12

Res.

0x18

GPIOx_BSRR
(where x = A..F)

BR15

0x1C
GPIOx_ODR
(where x = A..F)

Res.

Reset value

0x14

Res.

General-purpose I/Os (GPIO)
RM0360

GPIO register map
The following table gives the GPIO register map and reset values.
Table 23. GPIO register map and reset values

0
0

0

0

0

0

0

x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

AFSEL0
[3:0]

0

RM0360

General-purpose I/Os (GPIO)

Register

0x24

GPIOx_AFRH
(where x = A..B)
Reset value

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0x28

GPIOx_BRR
(where x = A..F)

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0

Offset

Res.

Table 23. GPIO register map and reset values (continued)

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

BR9

BR8

BR7

BR6

BR5

BR4

BR3

BR2

BR1

BR0

AFSEL8
[3:0]

BR11

AFSEL9
[3:0]

BR10

AFSEL10
[3:0]

BR12

AFSEL11
[3:0]
BR13

AFSEL12
[3:0]

BR14

AFSEL13
[3:0]

Res.

AFSEL14
[3:0]

BR15

AFSEL15
[3:0]

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Reset value

Refer to Section 2.2.2 on page 37 for the register boundary addresses.

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System configuration controller (SYSCFG)

9

RM0360

System configuration controller (SYSCFG)
The devices feature a set of configuration registers. The main purposes of the system
configuration controller are the following:


Enabling/disabling I2C Fast Mode Plus on some IO ports



Remapping some DMA trigger sources to different DMA channels



Remapping the memory located at the beginning of the code area



Managing the external interrupt line connection to the GPIOs



Managing robustness feature

9.1

SYSCFG registers

9.1.1

SYSCFG configuration register 1 (SYSCFG_CFGR1)
This register is used for specific configurations of memory and DMA requests remap and to
control special I/O features.
Two bits are used to configure the type of memory accessible at address 0x0000 0000.
These bits are used to select the physical remap by software and so, bypass the hardware
BOOT selection.
After reset these bits take the value selected by the actual boot mode configuration.
Address offset: 0x00
Reset value: 0x0000 000X (X is the memory mode selected by the actual boot mode
configuration

Note:

For STM32F030xC devices, DMA remapping bits are replaced by more flexible mapping
configured through DMA_CSELR register. Refer to Section 10.4.7: DMA channel selection
register (DMA_CSELR) for more details.

31
Res.

30
Res.

29
Res.

28
Res.

27

26

Res.

USART3
_DMA_
RMP

25
Res.

24

23

22

Res.

I2C_
PA10_
FMP

I2C_
PA9_
FMP

rw

rw

7

6

rw
15
Res.

14
Res

13
Res

12

10

9

8

USART1 USART1
TIM17_ TIM16_
_RX_
_TX_
DMA_ DMA_
DMA_
DMA_
RMP
RMP
RMP
RMP
rw

144/779

11

rw

rw

rw

ADC_
DMA_
RMP

Res.

rw

DocID025023 Rev 4

21

20

19

18

17

16

I2C1_
FMP

I2C_
PB9_
FMP

I2C_
PB8_
FMP

I2C_
PB7_
FMP

I2C_
PB6_
FMP

rw

rw

rw

rw

rw

5

4

3

2

1

0

Res.

PA11_
PA12_
RMP

Res.

Res.

Res.

rw

MEM_MODE
[1:0]
rw

rw

RM0360

System configuration controller (SYSCFG)

Bits 31:27 Reserved, must be kept at reset value.
Bit 26 USART3_DMA_RMP: USART3 DMA request remapping bit. Available on STM32F070xB
devices only.
This bit is set and cleared by software. It controls the remapping of USART3 DMA requests.
0: Disabled, need to enable remap before use.
1: Remap (USART3_RX and USART3_TX DMA requests mapped on DMA channel 3 and 2
respectively)
Bits 25:24 Reserved, must be kept at reset value.
Bits 23:22 I2C_PAx_FMP: Fast Mode Plus (FM+) driving capability activation bits. Available on
STM32F030x4, STM32F030x6, STM32F070x6 and STM32F030xC devices only.
These bits are set and cleared by software. Each bit enables I2C FM+ mode for PA10 and PA9
I/Os.
0: PAx pin operates in standard mode.
1: I2C FM+ mode enabled on PAx pin and the Speed control is bypassed.
Bit 21

Reserved, must be kept at reset value.

Bit 20 I2C1_FMP: FM+ driving capability activation for I2C1. Not available on STM32F030x8 devices.
This bit is set and cleared by software. This bit is OR-ed with I2C_Pxx_FM+ bits.
0: FM+ mode is controlled by I2C_Pxx_FM+ bits only.
1: FM+ mode is enabled on all I2C1 pins selected through selection bits in GPIOx_AFR
registers. This is the only way to enable the FM+ mode for pads without a dedicated
I2C_Pxx_FM+ control bit.
Bits 19:16 I2C_PBx_FMP: Fast Mode Plus (FM+) driving capability activation bits.
These bits are set and cleared by software. Each bit enables I2C FM+ mode for PB6, PB7,
PB8, and PB9 I/Os.
0: PBx pin operates in standard mode.
1: I2C FM+ mode enabled on PBx pin and the Speed control is bypassed.
Bits 15:13 Reserved, must be kept at reset value.
Bit 12 TIM17_DMA_RMP: TIM17 DMA request remapping bit. Available on STM32F030x4,
STM32F030x6, STM32F070x6, STM32F030x8 and STM32F070xB devices only.
This bit is set and cleared by software. It controls the remapping of TIM17 DMA requests.
0: No remap (TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 1)
1: Remap (TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 2)
Bit 11 TIM16_DMA_RMP: TIM16 DMA request remapping bit. Available on STM32F030x4,
STM32F030x6, STM32F070x6, STM32F030x8 and STM32F070xB devices only.
This bit is set and cleared by software. It controls the remapping of TIM16 DMA requests.
0: No remap (TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 3)
1: Remap (TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 4)
Bit 10 USART1_RX_DMA_RMP: USART1_RX DMA request remapping bit. Available on
STM32F030x4, STM32F030x6, STM32F070x6, STM32F030x8 and STM32F070xB devices
only.
This bit is set and cleared by software. It controls the remapping of USART1_RX DMA
requests.
0: No remap (USART1_RX DMA request mapped on DMA channel 3)
1: Remap (USART1_RX DMA request mapped on DMA channel 5)

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System configuration controller (SYSCFG)

RM0360

Bit 9 USART1_TX_DMA_RMP: USART1_TX DMA request remapping bit. . Available on
STM32F030x4,STM32F030x6, STM32F070x6, STM32F030x8 and STM32F070xB devices
only.
This bit is set and cleared by software. It bit controls the remapping of USART1_TX DMA
requests.
0: No remap (USART1_TX DMA request mapped on DMA channel 2)
1: Remap (USART1_TX DMA request mapped on DMA channel 4)
Bit 8 ADC_DMA_RMP: ADC DMA request remapping bit. Available on
STM32F030x4,STM32F030x6, STM32F070x6, STM32F030x8 and STM32F070xB devices
only.
This bit is set and cleared by software. It controls the remapping of ADC DMA requests.
0: No remap (ADC DMA request mapped on DMA channel 1)
1: Remap (ADC DMA request mapped on DMA channel 2)
Bits 7:5 Reserved, must be kept at reset value.
Bit 4 PA11_PA12_RMP: PA11 and PA12 remapping bit for small packages (28 and 20 pins).
Available on STM32F070x6 devices only.
This bit is set and cleared by software. It controls the mapping of either PA9/10 or PA11/12 pin
pair on small pin-count packages.
0: No remap (pin pair PA9/10 mapped on the pins)
1: Remap (pin pair PA11/12 mapped instead of PA9/10)
Bits 3:2 Reserved, must be kept at reset value.
Bits 1:0 MEM_MODE[1:0]: Memory mapping selection bits
These bits are set and cleared by software. They control the memory internal mapping at
address 0x0000 0000. After reset these bits take on the value selected by the actual boot
mode configuration. Refer to Chapter 2.5: Boot configuration for more details.
x0: Main Flash memory mapped at 0x0000 0000
01: System Flash memory mapped at 0x0000 0000
11: Embedded SRAM mapped at 0x0000 0000

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RM0360

System configuration controller (SYSCFG)

9.1.2

SYSCFG external interrupt configuration register 1
(SYSCFG_EXTICR1)
Address offset: 0x08
Reset value: 0x0000

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

EXTI3[3:0]
rw

rw

rw

EXTI2[3:0]
rw

rw

rw

EXTI1[3:0]

rw

rw

rw

rw

rw

EXTI0[3:0]
rw

rw

rw

rw

rw

Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 EXTIx[3:0]: EXTI x configuration bits (x = 0 to 3)
These bits are written by software to select the source input for the EXTIx external interrupt.
x000: PA[x] pin
x001: PB[x] pin
x010: PC[x] pin
x011: PD[x] pin
x100: Reserved
x101: PF[x] pin
other configurations: reserved

Note:

Some of the I/O pins mentioned in the above register may not be available on small
packages.

9.1.3

SYSCFG external interrupt configuration register 2
(SYSCFG_EXTICR2)
Address offset: 0x0C
Reset value: 0x0000

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

EXTI7[3:0]
rw

rw

rw

EXTI6[3:0]
rw

rw

rw

EXTI5[3:0]

rw

rw

rw

rw

DocID025023 Rev 4

rw

EXTI4[3:0]
rw

rw

rw

rw

rw

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System configuration controller (SYSCFG)

RM0360

Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 EXTIx[3:0]: EXTI x configuration bits (x = 4 to 7)
These bits are written by software to select the source input for the EXTIx external interrupt.
x000: PA[x] pin
x001: PB[x] pin
x010: PC[x] pin
x011: PD[x] pin
x100: Reserved
x101: PF[x] pin
other configurations: reserved

Note:

Some of the I/O pins mentioned in the above register may not be available on small
packages.

9.1.4

SYSCFG external interrupt configuration register 3
(SYSCFG_EXTICR3)
Address offset: 0x10
Reset value: 0x0000

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

EXTI11[3:0]
rw

rw

rw

EXTI10[3:0]
rw

rw

rw

rw

EXTI9[3:0]
rw

rw

rw

rw

EXTI8[3:0]
rw

rw

rw

rw

rw

Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 EXTIx[3:0]: EXTI x configuration bits (x = 8 to 11)
These bits are written by software to select the source input for the EXTIx external interrupt.
x000: PA[x] pin
x001: PB[x] pin
x010: PC[x] pin
x011: PD[x] pin
x100: Reserved
x101: PF[x] pin
other configurations: reserved

Note:

148/779

Some of the I/O pins mentioned in the above register may not be available on small
packages.

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RM0360

System configuration controller (SYSCFG)

9.1.5

SYSCFG external interrupt configuration register 4
(SYSCFG_EXTICR4)
Address offset: 0x14
Reset value: 0x0000

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

15

EXTI15[3:0]
rw

rw

rw

EXTI14[3:0]
rw

rw

rw

rw

EXTI13[3:0]
rw

rw

rw

rw

EXTI12[3:0]
rw

rw

rw

rw

rw

Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 EXTIx[3:0]: EXTI x configuration bits (x = 12 to 15)
These bits are written by software to select the source input for the EXTIx external interrupt.
x000: PA[x] pin
x001: PB[x] pin
x010: PC[x] pin
x011: PD[x] pin
x100: Reserved
x101: PF[x] pin
other configurations: reserved

Note:

Some of the I/O pins mentioned in the above register may not be available on small
packages.

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151

System configuration controller (SYSCFG)

9.1.6

RM0360

SYSCFG configuration register 2 (SYSCFG_CFGR2)
Address offset: 0x18
System reset value: 0x0000

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Res.

Res.

Res.

Res.

Res.

Res.

Res.

SRAM_
PEF

Res.

Res.

Res.

Res.

Res.

Res.

rc_w1

SRAM_
LOCKUP
PARITY
_LOCK
_LOCK
rw

rw

Bits 31:9 Reserved, must be kept at reset value
Bit 8 SRAM_PEF: SRAM parity error flag
This bit is set by hardware when an SRAM parity error is detected. It is cleared by software by
writing ‘1’.
0: No SRAM parity error detected
1: SRAM parity error detected
Bits 7:2 Reserved, must be kept at reset value
Bit 1 SRAM_PARITY_LOCK: SRAM parity lock bit
This bit is set by software and cleared by a system reset. It can be used to enable and lock the
SRAM parity error signal connection to TIM1/15/16/17 Break input.
0: SRAM parity error disconnected from TIM1/15/16/17 Break input
1: SRAM parity error connected to TIM1/15/16/17 Break input
Bit 0 LOCKUP_LOCK: Cortex-M0 LOCKUP bit enable bit
This bit is set by software and cleared by a system reset. It can be use to enable and lock the
connection of Cortex-M0 LOCKUP (Hardfault) output to TIM1/15/16/17 Break input.
0: Cortex-M0 LOCKUP output disconnected from TIM1/15/16/17 Break input
1: Cortex-M0 LOCKUP output connected to TIM1/15/16/17 Break input

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RM0360

9.1.7

System configuration controller (SYSCFG)

SYSCFG register maps
The following table gives the SYSCFG register map and the reset values.

0

0

EXTI6[3:0]
0

0

0

0

EXTI11[3:0]

EXTI10[3:0]

0

0

0

0

EXTI9[3:0]
0

0

0

0

MEM_MODE[1:0]

Res.

Res.
0

0

0

EXTI4[3:0]
0

0

0

0

EXTI8[3:0]
0

0

0

0

EXTI13[3:0]

EXTI12[3:0]

0

0

0

0

0

0

0

Res.

0

0

0

Res.

0

EXTI5[3:0]
0

0

Res.

0

0

Res.

EXTI14[3:0]

0

0

Res.

EXTI15[3:0]
0

0

Res.

0

0

X X
EXTI0[3:0]

SRAM_PEF

0

Res.

0

Res.

0

Res.

0

Res.

0

0
EXTI1[3:0]

0

0

0

0
LOCUP_LOCK

0

PA11_PA12_RMP
Res.

ADC_DMA_RMP

0

Res.

USART1_TX_DMA_RMP

0

Res.

0

0

SRAM_PARITY_LOCK

Reset value

0

0

EXTI2[3:0]

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

SYSCFG_CFGR2

Res.

0x18

Res.

Reset value

0

0

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

SYSCFG_EXTICR4

Res.

0x14

Res.

Reset value

0

TIM16_DMA_RMP

Res.
Res.
Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

SYSCFG_EXTICR3

Res.

0x10

0

EXTI7[3:0]
0

Res.

Reset value

0

USART1_RX_DMA_RMP

Res.
Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

SYSCFG_EXTICR2

Res.

0x0C

0
EXTI3[3:0]
0

Res.

Reset value

Res.

0

TIM17_DMA_RMP

I2C_PB7_FMP
0

Res.

I2C_PB8_FMP
0
Res.

I2C_PB6_FMP
Res.

I2C_PB9_FMP
0
Res.

Res.

I2C1_FMP
0
Res.

I2C_PA9_FMP

Res.

0
Res.

Res.

I2C_PA10_FMP

Res.

Res.

0
Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

0x08

0
Res.

Reset value
SYSCFG_EXTICR1

USART3_DMA_RMP

Res.

Res.

SYSCFG_CFGR1

Res.

0x00

Register

Res.

Offset

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0

Table 24. SYSCFG register map and reset values

0

0

Refer to Section 2.2.2 on page 37 for the register boundary addresses.

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Direct memory access controller (DMA)

RM0360

10

Direct memory access controller (DMA)

10.1

Introduction
Direct memory access (DMA) is used in order to provide high-speed data transfer between
peripherals and memory as well as memory to memory. Data can be quickly moved by DMA
without any CPU actions. This keeps CPU resources free for other operations.
The DMA controller has 5 channels, each dedicated to managing memory access requests
from one or more peripherals. It has an arbiter for handling the priority between DMA
requests.

10.2

152/779

DMA main features


5 independently configurable channels (requests) on DMA



Each channel is connected to dedicated hardware DMA requests, software trigger is
also supported on each channel. This configuration is done by software.



Priorities between requests from the DMA channels are software programmable (4
levels consisting of very high, high, medium, low) or hardware in case of equality
(request 1 has priority over request 2, etc.)



Independent source and destination transfer size (byte, half word, word), emulating
packing and unpacking. Source/destination addresses must be aligned on the data
size.



Support for circular buffer management



3 event flags (DMA Half Transfer, DMA Transfer complete and DMA Transfer Error)
logically ORed together in a single interrupt request for each channel



Memory-to-memory transfer



Peripheral-to-memory and memory-to-peripheral, and peripheral-to-peripheral
transfers



Access to peripherals as source and destination



Programmable number of data to be transferred: up to 65535

DocID025023 Rev 4

RM0360

10.3

Direct memory access controller (DMA)

DMA functional description
Figure 19. DMA block diagram
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The DMA controller performs direct memory transfer by sharing the system bus with the
ARM® Cortex®-M0 core. The DMA request may stop the CPU access to the system bus for
some bus cycles, when the CPU and DMA are targeting the same destination (memory or
peripheral). The bus matrix implements round-robin scheduling, thus ensuring at least half
of the system bus bandwidth (both to memory and peripheral) for the CPU.

10.3.1

DMA transactions
After an event, the peripheral sends a request signal to the DMA Controller. The DMA
controller serves the request depending on the channel priorities. As soon as the DMA
Controller accesses the peripheral, an Acknowledge is sent to the peripheral by the DMA
Controller. The peripheral releases its request as soon as it gets the Acknowledge from the
DMA Controller. Once the request is de-asserted by the peripheral, the DMA Controller
release the Acknowledge. If there are more requests, the peripheral can initiate the next
transaction.
In summary, each DMA transfer consists of three operations:


The loading of data from the peripheral data register or a location in memory addressed
through an internal current peripheral/memory address register. The start address used
for the first transfer is the base peripheral/memory address programmed in the
DMA_CPARx or DMA_CMARx register.

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Direct memory access controller (DMA)

10.3.2

RM0360



The storage of the data loaded to the peripheral data register or a location in memory
addressed through an internal current peripheral/memory address register. The start
address used for the first transfer is the base peripheral/memory address programmed
in the DMA_CPARx or DMA_CMARx register.



The post-decrementing of the DMA_CNDTRx register, which contains the number of
transactions that have still to be performed.

Arbiter
The arbiter manages the channel requests based on their priority and launches the
peripheral/memory access sequences.
The priorities are managed in two stages:


Software: each channel priority can be configured in the DMA_CCRx register. There
are four levels:
–



10.3.3

Very high priority

–

High priority

–

Medium priority

–

Low priority

Hardware: if 2 requests have the same software priority level, the channel with the
lowest number will get priority versus the channel with the highest number. For
example, channel 2 gets priority over channel 4.

DMA channels
Each channel can handle DMA transfer between a peripheral register located at a fixed
address and a memory address. The amount of data to be transferred (up to 65535) is
programmable. The register which contains the amount of data items to be transferred is
decremented after each transaction.

Programmable data sizes
Transfer data sizes of the peripheral and memory are fully programmable through the
PSIZE and MSIZE bits in the DMA_CCRx register.

Pointer incrementation
Peripheral and memory pointers can optionally be automatically post-incremented after
each transaction depending on the PINC and MINC bits in the DMA_CCRx register. If
incremented mode is enabled, the address of the next transfer will be the address of the
previous one incremented by 1, 2 or 4 depending on the chosen data size. The first transfer
address is the one programmed in the DMA_CPARx/DMA_CMARx registers. During
transfer operations, these registers keep the initially programmed value. The current
transfer addresses (in the current internal peripheral/memory address register) are not
accessible by software.
If the channel is configured in non-circular mode, no DMA request is served after the last
transfer (that is once the number of data items to be transferred has reached zero). In order
to reload a new number of data items to be transferred into the DMA_CNDTRx register, the
DMA channel must be disabled.

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Note:

Direct memory access controller (DMA)
If a DMA channel is disabled, the DMA registers are not reset. The DMA channel registers
(DMA_CCRx, DMA_CPARx and DMA_CMARx) retain the initial values programmed during
the channel configuration phase.
In circular mode, after the last transfer, the DMA_CNDTRx register is automatically reloaded
with the initially programmed value. The current internal address registers are reloaded with
the base address values from the DMA_CPARx/DMA_CMARx registers.

Channel configuration procedure
The following sequence should be followed to configure a DMA channel x (where x is the
channel number).
1.

Set the peripheral register address in the DMA_CPARx register. The data will be
moved from/ to this address to/ from the memory after the peripheral event.

2.

Set the memory address in the DMA_CMARx register. The data will be written to or
read from this memory after the peripheral event.

3.

Configure the total number of data to be transferred in the DMA_CNDTRx register.
After each peripheral event, this value will be decremented.

4.

Configure the channel priority using the PL[1:0] bits in the DMA_CCRx register

5.

Configure data transfer direction, circular mode, peripheral & memory incremented
mode, peripheral & memory data size, and interrupt after half and/or full transfer in the
DMA_CCRx register

6.

Activate the channel by setting the ENABLE bit in the DMA_CCRx register.

For code example refer to the Appendix section A.5.1: DMA Channel Configuration
sequence code example.
As soon as the channel is enabled, it can serve any DMA request from the peripheral
connected on the channel.
Once half of the bytes are transferred, the half-transfer flag (HTIF) is set and an interrupt is
generated if the Half-Transfer Interrupt Enable bit (HTIE) is set. At the end of the transfer,
the Transfer Complete Flag (TCIF) is set and an interrupt is generated if the Transfer
Complete Interrupt Enable bit (TCIE) is set.

Circular mode
Circular mode is available to handle circular buffers and continuous data flows (e.g. ADC
scan mode). This feature can be enabled using the CIRC bit in the DMA_CCRx register.
When circular mode is activated, the number of data to be transferred is automatically
reloaded with the initial value programmed during the channel configuration phase, and the
DMA requests continue to be served.

Memory-to-memory mode
The DMA channels can also work without being triggered by a request from a peripheral.
This mode is called Memory to Memory mode.
If the MEM2MEM bit in the DMA_CCRx register is set, then the channel initiates transfers
as soon as it is enabled by software by setting the Enable bit (EN) in the DMA_CCRx
register. The transfer stops once the DMA_CNDTRx register reaches zero. Memory to
Memory mode may not be used at the same time as Circular mode.

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10.3.4

RM0360

Programmable data width, data alignment and endians
When PSIZE and MSIZE are not equal, the DMA performs some data alignments as
described in Table 25: Programmable data width & endian behavior (when bits PINC =
MINC = 1).

Table 25. Programmable data width & endian behavior (when bits PINC = MINC = 1)
Number
Source
of data
Destination
port
items to
port width
width
transfer
(NDT)

Source content:
address / data

Transfer operations

Destination
content:
address / data

8

8

4

@0x0 / B0
@0x1 / B1
@0x2 / B2
@0x3 / B3

1: READ B0[7:0] @0x0 then WRITE B0[7:0] @0x0
2: READ B1[7:0] @0x1 then WRITE B1[7:0] @0x1
3: READ B2[7:0] @0x2 then WRITE B2[7:0] @0x2
4: READ B3[7:0] @0x3 then WRITE B3[7:0] @0x3

@0x0 / B0
@0x1 / B1
@0x2 / B2
@0x3 / B3

8

16

4

@0x0 / B0
@0x1 / B1
@0x2 / B2
@0x3 / B3

1: READ B0[7:0] @0x0 then WRITE 00B0[15:0] @0x0
2: READ B1[7:0] @0x1 then WRITE 00B1[15:0] @0x2
3: READ B2[7:0] @0x2 then WRITE 00B2[15:0] @0x4
4: READ B3[7:0] @0x3 then WRITE 00B3[15:0] @0x6

@0x0 / 00B0
@0x2 / 00B1
@0x4 / 00B2
@0x6 / 00B3

8

32

4

@0x0 / B0
@0x1 / B1
@0x2 / B2
@0x3 / B3

1: READ B0[7:0] @0x0 then WRITE 000000B0[31:0] @0x0
2: READ B1[7:0] @0x1 then WRITE 000000B1[31:0] @0x4
3: READ B2[7:0] @0x2 then WRITE 000000B2[31:0] @0x8
4: READ B3[7:0] @0x3 then WRITE 000000B3[31:0] @0xC

@0x0 / 000000B0
@0x4 / 000000B1
@0x8 / 000000B2
@0xC / 000000B3

16

8

4

@0x0 / B1B0
@0x2 / B3B2
@0x4 / B5B4
@0x6 / B7B6

1: READ B1B0[15:0] @0x0 then WRITE B0[7:0] @0x0
2: READ B3B2[15:0] @0x2 then WRITE B2[7:0] @0x1
3: READ B5B4[15:0] @0x4 then WRITE B4[7:0] @0x2
4: READ B7B6[15:0] @0x6 then WRITE B6[7:0] @0x3

@0x0 / B0
@0x1 / B2
@0x2 / B4
@0x3 / B6

16

16

4

@0x0 / B1B0
@0x2 / B3B2
@0x4 / B5B4
@0x6 / B7B6

1: READ B1B0[15:0] @0x0 then WRITE B1B0[15:0] @0x0
2: READ B3B2[15:0] @0x2 then WRITE B3B2[15:0] @0x2
3: READ B5B4[15:0] @0x4 then WRITE B5B4[15:0] @0x4
4: READ B7B6[15:0] @0x6 then WRITE B7B6[15:0] @0x6

@0x0 / B1B0
@0x2 / B3B2
@0x4 / B5B4
@0x6 / B7B6

16

32

4

@0x0 / B1B0
@0x2 / B3B2
@0x4 / B5B4
@0x6 / B7B6

1: READ B1B0[15:0] @0x0 then WRITE 0000B1B0[31:0] @0x0
2: READ B3B2[15:0] @0x2 then WRITE 0000B3B2[31:0] @0x4
3: READ B5B4[15:0] @0x4 then WRITE 0000B5B4[31:0] @0x8
4: READ B7B6[15:0] @0x6 then WRITE 0000B7B6[31:0] @0xC

@0x0 / 0000B1B0
@0x4 / 0000B3B2
@0x8 / 0000B5B4
@0xC / 0000B7B6

32

8

4

@0x0 / B3B2B1B0
@0x4 / B7B6B5B4
@0x8 / BBBAB9B8
@0xC / BFBEBDBC

1: READ B3B2B1B0[31:0] @0x0 then WRITE B0[7:0] @0x0
2: READ B7B6B5B4[31:0] @0x4 then WRITE B4[7:0] @0x1
3: READ BBBAB9B8[31:0] @0x8 then WRITE B8[7:0] @0x2
4: READ BFBEBDBC[31:0] @0xC then WRITE BC[7:0] @0x3

@0x0 / B0
@0x1 / B4
@0x2 / B8
@0x3 / BC

32

16

4

@0x0 / B3B2B1B0
@0x4 / B7B6B5B4
@0x8 / BBBAB9B8
@0xC / BFBEBDBC

1: READ B3B2B1B0[31:0] @0x0 then WRITE B1B0[15:0] @0x0
2: READ B7B6B5B4[31:0] @0x4 then WRITE B5B4[15:0] @0x2
3: READ BBBAB9B8[31:0] @0x8 then WRITE B9B8[15:0] @0x4
4: READ BFBEBDBC[31:0] @0xC then WRITE BDBC[15:0] @0x6

@0x0 / B1B0
@0x2 / B5B4
@0x4 / B9B8
@0x6 / BDBC

32

32

4

@0x0 / B3B2B1B0
@0x4 / B7B6B5B4
@0x8 / BBBAB9B8
@0xC / BFBEBDBC

1: READ B3B2B1B0[31:0] @0x0 then WRITE B3B2B1B0[31:0] @0x0  @0x0 / B3B2B1B0
2: READ B7B6B5B4[31:0] @0x4 then WRITE B7B6B5B4[31:0] @0x4 @0x4 / B7B6B5B4
3: READ BBBAB9B8[31:0] @0x8 then WRITE BBBAB9B8[31:0] @0x8 @0x8 / BBBAB9B8
4: READ BFBEBDBC[31:0] @0xC then WRITE BFBEBDBC[31:0] @0xC @0xC / BFBEBDBC

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Direct memory access controller (DMA)

Addressing an AHB peripheral that does not support byte or halfword 
write operations
When the DMA initiates an AHB byte or halfword write operation, the data are duplicated on
the unused lanes of the HWDATA[31:0] bus. So when the used AHB slave peripheral does
not support byte or halfword write operations (when HSIZE is not used by the peripheral)
and does not generate any error, the DMA writes the 32 HWDATA bits as shown in the two
examples below:


To write the halfword “0xABCD”, the DMA sets the HWDATA bus to “0xABCDABCD”
with HSIZE = HalfWord



To write the byte “0xAB”, the DMA sets the HWDATA bus to “0xABABABAB” with
HSIZE = Byte

Assuming that the AHB/APB bridge is an AHB 32-bit slave peripheral that does not take the
HSIZE data into account, it will transform any AHB byte or halfword operation into a 32-bit
APB operation in the following manner:


An AHB byte write operation of the data “0xB0” to 0x0 (or to 0x1, 0x2 or 0x3) will be
converted to an APB word write operation of the data “0xB0B0B0B0” to 0x0



An AHB halfword write operation of the data “0xB1B0” to 0x0 (or to 0x2) will be
converted to an APB word write operation of the data “0xB1B0B1B0” to 0x0

For instance, to write the APB backup registers (16-bit registers aligned to a 32-bit address
boundary), the software must configure the memory source size (MSIZE) to “16-bit” and the
peripheral destination size (PSIZE) to “32-bit”.

10.3.5

Error management
A DMA transfer error can be generated by reading from or writing to a reserved address
space. When a DMA transfer error occurs during a DMA read or a write access, the faulty
channel is automatically disabled through a hardware clear of its EN bit in the corresponding
Channel configuration register (DMA_CCRx). The channel's transfer error interrupt flag
(TEIF) in the DMA_IFR register is set and an interrupt is generated if the transfer error
interrupt enable bit (TEIE) in the DMA_CCRx register is set.

10.3.6

DMA interrupts
An interrupt can be produced on a Half-transfer, Transfer complete or Transfer error for
each DMA channel. Separate interrupt enable bits are available for flexibility.
Table 26. DMA interrupt requests
Interrupt event

Event flag

Enable control bit

Half-transfer

HTIF

HTIE

Transfer complete

TCIF

TCIE

Transfer error

TEIF

TEIE

DMA controller
The hardware requests from the peripherals (TIMx, ADC, SPI, I2C, and USARTx) are simply
logically ORed before entering the DMA. This means that on one channel, only one request
must be enabled at a time.

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RM0360

The peripheral DMA requests can be independently activated/de-activated by programming
the DMA control bit in the registers of the corresponding peripheral.
Figure 20. DMA request mapping

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1. DMA request mapped on this DMA channel only if the corresponding remapping bit is cleared in the
SYSCFG_CFGR1 register. For more details, please refer to Section 9.1.1: SYSCFG configuration register
1 (SYSCFG_CFGR1) on page 144.
2. DMA request mapped on this DMA channel only if the corresponding remapping bit is set in the
SYSCFG_CFGR1 register. For more details, please refer to Section 9.1.1: SYSCFG configuration register
1 (SYSCFG_CFGR1) on page 144.

Table 27 lists the DMA requests for each channel.

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Direct memory access controller (DMA)
Table 27. Summary of the DMA requests for each channel
on STM32F030x4/6, STM32F070x6, STM32F070xB and STM32F030x8 devices

Peripherals

Channel 1

Channel 2

Channel 3

Channel 4

Channel 5

ADC

ADC(1)

ADC(2)

-

-

-

SPI

-

SPI1_RX

SPI1_TX

SPI2_RX

SPI2_TX

USART

-

USART1_TX(1)
USART3_TX(2)

USART1_RX(1)
USART3_RX(2)

USART1_TX(2)
USART2_TX

USART1_RX(2)
USART2_RX

I2C

-

I2C1_TX

I2C1_RX

I2C2_TX

I2C2_RX
TIM1_CH3
TIM1_UP

TIM1

-

TIM1_CH1

TIM1_CH2

TIM1_CH4
TIM1_TRIG
TIM1_COM

TIM3

-

TIM3_CH3

TIM3_CH4
TIM3_UP

TIM3_CH1
TIM3_TRIG

-

TIM6

-

-

TIM6_UP

-

-

TIM7

-

-

-

TIM7_UP

-

TIM15

-

-

-

-

TIM15_CH1
TIM15_UP
TIM15_TRIG
TIM15_COM

TIM16

-

-

TIM16_CH1(1)
TIM16_UP(1)

TIM16_CH1(2)
TIM16_UP(2)

-

TIM17

TIM17_CH1(1)
TIM17_UP(1)

TIM17_CH1(2)
TIM17_UP(2)

-

-

-

1. DMA request mapped on this DMA channel only if the corresponding remapping bit is cleared in the SYSCFG_CFGR1
register. For more details, please refer to Section 9.1.1: SYSCFG configuration register 1 (SYSCFG_CFGR1) on page 144.
2. DMA request mapped on this DMA channel only if the corresponding remapping bit is set in the SYSCFG_CFGR1 register.
For more details, please refer to Section 9.1.1: SYSCFG configuration register 1 (SYSCFG_CFGR1) on page 144.

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Table 28. Summary of the DMA requests for each channel on STM32F030xC devices
CxS
[3:0]

Channel 2

Channel 3

Channel 4

Channel 5

-

TIM3_CH3

TIM3_CH4
TIM3_UP

TIM1_CH4
TIM1_TRIG
TIM1_COM

TIM1_UP
TIM15_CH1
TIM15_UP
TIM15_TRIG
TIM15_COM

-

-

-

ADC

-

TIM6_UP

TIM7_UP

-

USART1_TX

USART1_RX

USART2_TX

USART2_ RX

-

-

-

-

-

-

SPI1_RX

SPI1_TX

SPI2_RX

SPI2_TX

-

I2C1_TX

I2C1_RX

I2C2_TX

I2C2_RX

-

TIM1_CH1

TIM1_CH2

-

TIM1_CH3

TIM17_CH1
TIM17_UP

-

TIM16_CH1
TIM16_UP

TIM3_CH1
TIM3_TRIG

-

0001

ADC

ADC

TIM6_UP

TIM7_UP

-

0010

-

I2C1_TX

I2C1_RX

I2C2_TX

I2C2_RX

0011

-

SPI1_RX

SPI1_TX

SPI2_RX

SPI2_TX

0100

-

TIM1_CH1

TIM1_CH2

-

TIM1_CH3

0101

-

-

-

-

-

0110

-

-

-

TIM3_CH1
TIM3_TRIG

-

0111

TIM17_CH1
TIM17_UP

TIM17_CH1
TIM17_UP

TIM16_CH1
TIM16_UP

TIM16_CH1
TIM16_UP

-

1000

USART1_ RX

USART1_TX

USART1_RX

USART1_TX

USART1_ RX

1001

USART2_ RX

USART2_TX

USART2_ RX

USART2_TX

USART2_ RX

1010

USART3_ RX

USART3_TX

USART3_ RX

USART3_TX

USART3_ RX

1011

USART4_ RX

USART4_TX

USART4_ RX

USART4_TX

USART4_ RX

1100

USART5_ RX

USART5_TX

USART5_ RX

USART5_TX

USART5_ RX

1101

USART6_ RX

USART6_TX

USART6_ RX

USART6_TX

USART6_ RX

0000

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Direct memory access controller (DMA)

10.4

DMA registers
Refer to Section 1.1 on page 33 for a list of abbreviations used in register descriptions.
The peripheral registers can be accessed by bytes (8-bit), half-words (16-bit) or words (32bit).

10.4.1

DMA interrupt status register (DMA_ISR)
Address offset: 0x00
Reset value: 0x0000 0000

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

TEIF5

HTIF5

TCIF5

GIF5

r

r

r

r

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

TEIF4

HTIF4

TCIF4

GIF4

TEIF3

HTIF3

TCIF3

GIF3

TEIF2

HTIF2

TCIF2

GIF2

TEIF1

HTIF1

TCIF1

GIF1

r

r

r

r

r

r

r

r

r

r

r

r

r

r

r

r

Bits 19, 15, 11, 7, 3 TEIFx: Channel x transfer error flag (x = 1..5)
This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the
DMA_IFCR register.
0: No transfer error (TE) on channel x
1: A transfer error (TE) occurred on channel x
Bits 18, 14, 10, 6, 2 HTIFx: Channel x half transfer flag (x = 1..5)
This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the
DMA_IFCR register.
0: No half transfer (HT) event on channel x
1: A half transfer (HT) event occurred on channel x
Bits 17, 13, 9, 5, 1 TCIFx: Channel x transfer complete flag (x = 1..5)
This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the
DMA_IFCR register.
0: No transfer complete (TC) event on channel x
1: A transfer complete (TC) event occurred on channel x
Bits 16, 12, 8, 4, 0 GIFx: Channel x global interrupt flag (x = 1..5)
This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the
DMA_IFCR register.
0: No TE, HT or TC event on channel x
1: A TE, HT or TC event occurred on channel x

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RM0360

DMA interrupt flag clear register (DMA_IFCR)
Address offset: 0x04
Reset value: 0x0000 0000

31

15

30

14

29

13

28

12

27

26

25

24

23

22

21

20

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

11

10

9

8

7

6

5

4

19

18

17

16

CTEIF5 CHTIF5 CTCIF5 CGIF5
w

w

w

w

3

2

1

0

CTEIF4 CHTIF4 CTCIF4 CGIF4 CTEIF3 CHTIF3 CTCIF3 CGIF3 CTEIF2 CHTIF2 CTCIF2 CGIF2 CTEIF1 CHTIF1 CTCIF1 CGIF1
w

w

w

w

w

w

w

w

w

w

w

w

w

Bits 19, 15, 11, 7, 3 CTEIFx: Channel x transfer error clear (x = 1..5)
This bit is set by software.
0: No effect
1: Clears the corresponding TEIF flag in the DMA_ISR register
Bits 18, 14, 10, 6, 2 CHTIFx: Channel x half transfer clear (x = 1..5)
This bit is set by software.
0: No effect
1: Clears the corresponding HTIF flag in the DMA_ISR register
Bits 17, 13, 9, 5, 1 CTCIFx: Channel x transfer complete clear (x = 1..5)
This bit is set by software.
0: No effect
1: Clears the corresponding TCIF flag in the DMA_ISR register
Bits 16, 12, 8, 4, 0 CGIFx: Channel x global interrupt clear (x = 1..5)
This bit is set by software.
0: No effect
1: Clears the GIF, TEIF, HTIF and TCIF flags in the DMA_ISR register

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Direct memory access controller (DMA)

10.4.3

DMA channel x configuration register (DMA_CCRx)
(x = 1..5, where x = channel number)
Address offset: 0x08 + 0d20 × (channel number – 1)
Reset value: 0x0000 0000

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MINC

PINC

CIRC

DIR

TEIE

HTIE

TCIE

EN

rw

rw

rw

rw

rw

rw

rw

rw

15

MEM2
MEM
rw

PL[1:0]
rw

rw

MSIZE[1:0]

PSIZE[1:0]

rw

rw

rw

rw

16

Bits 31:1 Reserved, must be kept at reset value.
Bit 14 MEM2MEM: Memory to memory mode
This bit is set and cleared by software.
0: Memory to memory mode disabled
1: Memory to memory mode enabled
Bits 13:12 PL[1:0]: Channel priority level
These bits are set and cleared by software.
00: Low
01: Medium
10: High
11: Very high
Bits 11:10 MSIZE[1:0]: Memory size
These bits are set and cleared by software.
00: 8-bits
01: 16-bits
10: 32-bits
11: Reserved
Bits 9:8 PSIZE[1:0]: Peripheral size
These bits are set and cleared by software.
00: 8-bits
01: 16-bits
10: 32-bits
11: Reserved
Bit 7 MINC: Memory increment mode
This bit is set and cleared by software.
0: Memory increment mode disabled
1: Memory increment mode enabled
Bit 6 PINC: Peripheral increment mode
This bit is set and cleared by software.
0: Peripheral increment mode disabled
1: Peripheral increment mode enabled

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Direct memory access controller (DMA)

RM0360

Bit 5 CIRC: Circular mode
This bit is set and cleared by software.
0: Circular mode disabled
1: Circular mode enabled
Bit 4 DIR: Data transfer direction
This bit is set and cleared by software.
0: Read from peripheral
1: Read from memory
Bit 3 TEIE: Transfer error interrupt enable
This bit is set and cleared by software.
0: TE interrupt disabled
1: TE interrupt enabled
Bit 2 HTIE: Half transfer interrupt enable
This bit is set and cleared by software.
0: HT interrupt disabled
1: HT interrupt enabled
Bit 1 TCIE: Transfer complete interrupt enable
This bit is set and cleared by software.
0: TC interrupt disabled
1: TC interrupt enabled
Bit 0 EN: Channel enable
This bit is set and cleared by software.
0: Channel disabled
1: Channel enabled

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RM0360

Direct memory access controller (DMA)

10.4.4

DMA channel x number of data register (DMA_CNDTRx) (x = 1..5, where
x = channel number)
Address offset: 0x0C + 0d20 × (channel number – 1)
Reset value: 0x0000 0000

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

rw

rw

rw

rw

rw

rw

rw

NDT[15:0]
rw

rw

rw

rw

rw

rw

rw

rw

rw

Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 NDT[15:0]: Number of data to transfer
Number of data to be transferred (0 up to 65535). This register can only be written when the
channel is disabled. Once the channel is enabled, this register is read-only, indicating the
remaining bytes to be transmitted. This register decrements after each DMA transfer.
Once the transfer is completed, this register can either stay at zero or be reloaded
automatically by the value previously programmed if the channel is configured in circular
mode.
If this register is zero, no transaction can be served whether the channel is enabled or not.

10.4.5

DMA channel x peripheral address register (DMA_CPARx) (x = 1..5,
where x = channel number)
Address offset: 0x10 + 0d20 × (channel number – 1)
Reset value: 0x0000 0000
This register must not be written when the channel is enabled.

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

PA [31:16]
rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

PA [15:0]
rw

Bits 31:0 PA[31:0]: Peripheral address
Base address of the peripheral data register from/to which the data will be read/written.
When PSIZE is 01 (16-bit), the PA[0] bit is ignored. Access is automatically aligned to a halfword address.
When PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is automatically aligned to a word
address.

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Direct memory access controller (DMA)

10.4.6

RM0360

DMA channel x memory address register (DMA_CMARx) (x = 1..5,
where x = channel number)
Address offset: 0x14 + 0d20 × (channel number – 1)
Reset value: 0x0000 0000
This register must not be written when the channel is enabled.

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

MA [31:16]
rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

MA [15:0]
rw

Bits 31:0 MA[31:0]: Memory address
Base address of the memory area from/to which the data will be read/written.
When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a halfword address.
When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word
address.

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RM0360

Direct memory access controller (DMA)

10.4.7

DMA channel selection register (DMA_CSELR)
This register is present only on STM32F030xC devices.
Address offset: 0xA8
Reset value: 0x0000 0000
This register is used to manage the remapping of DMA channels.

31

30

29

28

27

26

25

24

23

22

21

20

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.
rw

rw

rw

rw

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

C4S [3:0]
rw

C3S [3:0]

19

rw

17

16

C5S [3:0]

C2S [3:0]

rw

18

C1S [3:0]
rw

rw

Bits 31:20 Reserved, must be kept at reset value.
Bits 19:16 C5S[3:0]: DMA channel 5 selection
DMA request mapping for channel 5 (1)
Bits 15:12 C4S[3:0]: DMA channel 4 selection
DMA request mapping for channel 4 (1)
Bits 11:8 C3S[3:0]: DMA channel 3 selection
DMA request mapping for channel 3 (1)
Bits 7:4 C2S[3:0]: DMA channel 2 selection
DMA request mapping for channel 2 (1)
Bits 3:0 C1S[3:0]: DMA channel 1 selection
DMA request mapping for channel 1 (1)
1. For concrete DMA requests mapping, refer to Table 28: Summary of the DMA requests for each channel on

STM32F030xC devices.

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Direct memory access controller (DMA)

10.4.8

RM0360

DMA register map
The following table gives the DMA register map and the reset values.

TCIF1

GIF1

0

0

0

0

0

CHTIF5

CTCIF5

CGIF5

CTEIF4

CHTIF4

CTCIF4

CGIF4

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0x3C

168/779

PINC

CIRC

DIR

TEIE

HTIE

TCIE

EN

PSIZE [1:0]

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

EN

0

TCIE

0

HTIE

0

TEIE

PL
[1:0]

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

TCIE

EN

0

HTIE

0

TEIE

0

DIR

0

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

0

PL
[1:0]

PINC

0

CIRC

0

PSIZE [1:0]

0

MSIZE [1:0]

0

MEM2MEM

0

0

0

0

0

0

0

0

NDT[15:0]
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

PA[31:0]
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

DMA_CMAR3
Reset value

0

NDT[15:0]

Res.

0

Res.

0

Res.

0

Res.

0

Res.

0

Res.

0

Res.

0

Res.

0

Res.

0

Res.

0

Res.

0

Res.

0

DMA_CPAR3
Reset value

0

0

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.
0

Reset value
0x38

0

MA[31:0]

Res.

DMA_CNDTR3

0

DIR

0

Reset value
0x34

0

MINC

0

Res.

DMA_CCR3

0

PINC

0

0

Res.

0x30

0

0

CIRC

0

DMA_CMAR2
Reset value

0

PA[31:0]

Res.

0x28

0

PSIZE [1:0]

0

DMA_CPAR2
Reset value

0

0

MSIZE [1:0]

0

Reset value
0x24

0

0

0
Res.

DMA_CNDTR2

0

0

MEM2MEM

0

Res.

0

Res.

0

Res.

0

Res.

0

Res.

0

Res.

0

Res.

0

Res.

0

Res.

0

Res.

0

Res.

0

Reset value
0x20

0

MA[31:0]

Res.

DMA_CCR2

0

MINC

0

Res.

0x1C

0

DMA_CMAR1
Reset value

0

0

NDT[15:0]
0

Res.

0x14

Reset value

0

0

0

PA[31:0]

Res.

0x10

0

0

Res.

Reset value
DMA_CPAR1

0

0

MSIZE [1:0]

Res.
Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

DMA_CNDTR1

Res.

0x0C

0
Res.

Reset value

PL
[1:0]

0

CGIF1

HTIF1

0

CTCIF1

0

CHTIF1

GIF2

TEIF1

0

CTEIF1

TCIF2

0

CGIF2

HTIF2

0

CTCIF2

GIF3

TEIF2

0

CHTIF2

TCIF3

0

CTEIF2

HTIF3

0

MINC

GIF4

TEIF3

0

CGIF3

TCIF4

0

CTCIF3

HTIF4

0

CHTIF3

GIF5

TEIF4

0

CTEIF3

TCIF5
0

MEM2MEM

HTIF5
0

Res.

TEIF5

Res.
Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

DMA_CCR1

Res.

0x08

Res.

Reset value

0
CTEIF5

Res.

Res.

Res.

Res.

Res.

Res.

DMA_IFCR

Res.

0x04

Res.

Reset value

Res.

Res.

Res.

Res.

Res.

Res.

DMA_ISR

Res.

0x00

Register

Res.

Offset

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0

Table 29. DMA register map and reset values

0

0

MA[31:0]
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

DocID025023 Rev 4

0

RM0360

Direct memory access controller (DMA)

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0x64

DIR

HTIE

TCIE

EN

PINC

CIRC

TEIE

MINC

PSIZE [1:0]

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

EN

0

TCIE

0

HTIE

0

DIR

0

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

PL
[1:0]

TEIE

0

CIRC

0

0

0

0

0

0

0

0

NDT[15:0]
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

PA[31:0]
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

DMA_CMAR5
Reset value

0

PINC

0

DMA_CPAR5
Reset value

0

0

PSIZE [1:0]

0

Reset value
0x60

0

0

0
Res.

DMA_CNDTR5

0

0

MSIZE [1:0]

0

Reset value
0x5C

0

0

0

MEM2MEM

0

Res.

0

Res.

0

Res.

0

Res.

0

Res.

0

Res.

0

Res.

0

Res.

0

Res.

0

Res.

0

Res.

0

Res.

DMA_CCR5

0

MA[31:0]

Res.

0x58

0

DMA_CMAR4
Reset value

0

NDT[15:0]
0

Res.

0x50

Reset value

0

PA[31:0]

Res.

0x4C

0

MINC

Reset value
DMA_CPAR4

0

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

DMA_CNDTR4

Res.

0x48

0
Res.

Reset value

PL
[1:0]

MSIZE [1:0]

MEM2MEM

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

DMA_CCR4

Res.

0x44

Register

Res.

Offset

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0

Table 29. DMA register map and reset values (continued)

0

0

MA[31:0]
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Reset value

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

DMA_CSELR

Res.

0xA8

Register

Res.

Offset

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0

Table 31. DMA register map and reset values(register available on STM32F030xC
devices only)

C5S[3:0]
0

0

0

C4S[3:0]
0

0

0

0

C3S[3:0]
0

0

0

0

C2S[3:0]
0

0

0

0

C1S[3:0]
0

0

0

0

0

Refer to Section 2.2.2 on page 37 for the register boundary addresses.

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Interrupts and events

RM0360

11

Interrupts and events

11.1

Nested vectored interrupt controller (NVIC)

11.1.1

NVIC main features


32 maskable interrupt channels (not including the sixteen ARM® Cortex®-M0 interrupt
lines)



4 programmable priority levels (2 bits of interrupt priority are used)



Low-latency exception and interrupt handling



Power management control



Implementation of System Control Registers

The NVIC and the processor core interface are closely coupled, which enables low latency
interrupt processing and efficient processing of late arriving interrupts.
All interrupts including the core exceptions are managed by the NVIC. For more information
on exceptions and NVIC programming, refer to the PM0215 programming manual.
For code example refer to the Appendix section A.6.1: NVIC initialization example.

11.1.2

SysTick calibration value register
The SysTick calibration value is set to 6000, which gives a reference time base of 1 ms with
the SysTick clock set to 6 MHz (max fHCLK/8).

11.1.3

Interrupt and exception vectors
Table 32 is the vector table for STM32F0x0 devices. Please consider peripheral availability
on given device.

Position

Priority

Table 32. Vector table
Type of
priority

-

-

-

-

-3

-

Acronym

Description

Address

-

Reserved

0x0000 0000

fixed

Reset

Reset

0x0000 0004

-2

fixed

NMI

Non maskable interrupt. The RCC Clock Security
System (CSS) is linked to the NMI vector.

0x0000 0008

-

-1

fixed

HardFault

All class of fault

0x0000 000C

-

3

settable

SVCall

System service call via SWI instruction

0x0000 002C

-

5

settable

PendSV

Pendable request for system service

0x0000 0038

-

6

settable

SysTick

System tick timer

0x0000 003C

0

7

settable

WWDG

Window watchdog interrupt

0x0000 0040

1
2

170/779

Reserved
9

settable

RTC

0x0000 0044
RTC interrupts (combined EXTI lines 17, 19 and
20)

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0x0000 0048

RM0360

Interrupts and events

Position

Priority

Table 32. Vector table (continued)
Type of
priority

3

10

settable

FLASH

Flash global interrupt

0x0000 004C

4

11

settable

RCC

RCC global interrupts

0x0000 0050

5

12

settable

EXTI0_1

EXTI Line[1:0] interrupts

0x0000 0054

6

13

settable

EXTI2_3

EXTI Line[3:2] interrupts

0x0000 0058

7

14

settable

EXTI4_15

EXTI Line[15:4] interrupts

0x0000 005C

8

Acronym

Description

Reserved

Address

0x0000 0060

9

16

settable

DMA_CH1

DMA channel 1 interrupt

0x0000 0064

10

17

settable

DMA_CH2_3

DMA channel 2 and 3 interrupts

0x0000 0068

11

18

settable

DMA_CH4_5

DMA channel 4 and 5 interrupts

0x0000 006C

12

19

settable

ADC

ADC interrupts

0x0000 0070

13

20

settable

TIM1_BRK_UP_
TRG_COM

TIM1 break, update, trigger and commutation
interrupt

0x0000 0074

14

21

settable

TIM1_CC

TIM1 capture compare interrupt

0x0000 0078

15

Reserved

0x0000 007C

16

23

settable

TIM3

TIM3 global interrupt

0x0000 0080

17

24

settable

TIM6

TIM6 global interrupt

0x0000 0084

18

Reserved

0x0000 0084

19

Reserved

0x0000 0088

19

26

settable

TIM14

TIM14 global interrupt

0x0000 008C

20

27

settable

TIM15

TIM15 global interrupt

0x0000 0090

21

28

settable

TIM16

TIM16 global interrupt

0x0000 0094

22

29

settable

TIM17

TIM17 global interrupt

0x0000 0098

23

30

settable

I2C1

I2C1 global interrupt

0x0000 009C

2C2

24

31

settable

I2C2

I

global interrupt

0x0000 00A0

25

32

settable

SPI1

SPI1 global interrupt

0x0000 00A4

26

33

settable

SPI2

SPI2 global interrupt

0x0000 00A8

27

34

settable

USART1

USART1 global interrupt

0x0000 00AC

28

35

settable

USART2

USART2 global interrupt

0x0000 00B0

29

36

settable

USART3_4_5_6

USART3, USART4, USART5, USART6 global
interrupts

0x0000 00B4

30
31

Reserved
38

settable

USB

0x0000 00B8
USB global interrupt (combined with EXTI line 18)

DocID025023 Rev 4

0x0000 00BC

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180

Interrupts and events

11.2

RM0360

Extended interrupts and events controller (EXTI)
The extended interrupts and events controller (EXTI) manages the external and internal
asynchronous events/interrupts and generates the event request to the CPU/Interrupt
Controller and a wake-up request to the Power Manager.
The EXTI allows the management of up to 28 external/internal event line (21 external event
lines and 7 internal event lines).
The active edge of each external interrupt line can be chosen independently, whilst for
internal interrupt the active edge is always the rising one. An interrupt could be left pending:
in case of an external one, a status register is instantiated and indicates the source of the
interrupt; an event is always a simple pulse and it’s used for triggering the core Wake-up
(e.g. Cortex-M0 RXEV pin). For internal interrupts, the pending status is assured by the
generating IP, so no need for a specific flag. Each input line can be masked independently
for interrupt or event generation, in addition the internal lines are sampled only in STOP
mode. This controller allows also to emulate the (only) external events by software,
multiplexed with the corresponding hardware event line, by writing to a dedicated register.

11.2.1

Main features
The EXTI main features are the following:

172/779



Supports generation of up to 32 event/interrupt requests



Independent mask on each event/interrupt line



Automatic disable of internal lines when system is not in STOP mode



Independent trigger for external event/interrupt line



Dedicated status bit for external interrupt line



Emulation for all the external event requests

DocID025023 Rev 4

RM0360

11.2.2

Interrupts and events

Block diagram
The extended interrupt/event block diagram is shown in Figure 21.
Figure 21. Extended interrupts and events controller (EXTI) block diagram
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11.2.3

Event management
The STM32F0x0 is able to handle external or internal events in order to wake up the core
(WFE). The wakeup event can be generated either by:

11.2.4



enabling an interrupt in the peripheral control register but not in the NVIC, and enabling
the SEVONPEND bit in the Cortex-M0 System Control register. When the MCU
resumes from WFE, the EXTI peripheral interrupt pending bit and the peripheral NVIC
IRQ channel pending bit (in the NVIC interrupt clear pending register) have to be
cleared.



or by configuring an external or internal EXTI line in event mode. When the CPU
resumes from WFE, it is not necessary to clear the peripheral interrupt pending bit or
the NVIC IRQ channel pending bit as the pending bit corresponding to the event line is
not set.

Functional description
For the external interrupt lines, to generate the interrupt, the interrupt line should be
configured and enabled. This is done by programming the two trigger registers with the
desired edge detection and by enabling the interrupt request by writing a ‘1’ to the
corresponding bit in the interrupt mask register. When the selected edge occurs on the
external interrupt line, an interrupt request is generated. The pending bit corresponding to
the interrupt line is also set. This request is reset by writing a ‘1’ in the pending register.

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180

Interrupts and events

RM0360

For the internal interrupt lines, the active edge is always the rising edge, the interrupt is
enabled by default in the interrupt mask register and there is no corresponding pending bit
in the pending register.
To generate the event, the event line should be configured and enabled. This is done by
programming the two trigger registers with the desired edge detection and by enabling the
event request by writing a ‘1’ to the corresponding bit in the event mask register. When the
selected edge occurs on the event line, an event pulse is generated. The pending bit
corresponding to the event line is not set.
For the external lines, an interrupt/event request can also be generated by software by
writing a ‘1’ in the software interrupt/event register.
Note:

The interrupts or events associated to the internal lines can be triggered only when the
system is in STOP mode. If the system is still running, no interrupt/event is generated.
For code example refer to the Appendix section A.6.2: External interrupt selection code
example.

Hardware interrupt selection
To configure a line as interrupt source, use the following procedure:


Configure the corresponding mask bit in the EXTI_IMR register.



Configure the Trigger Selection bits of the Interrupt line (EXTI_RTSR and EXTI_FTSR)



Configure the enable and mask bits that control the NVIC IRQ channel mapped to the
EXTI so that an interrupt coming from one of the EXTI line can be correctly
acknowledged.

Hardware event selection
To configure a line as event source, use the following procedure:


Configure the corresponding mask bit in the EXTI_EMR register.



Configure the Trigger Selection bits of the Event line (EXTI_RTSR and EXTI_FTSR)

Software interrupt/event selection
Any of the external lines can be configured as software interrupt/event lines. The following is
the procedure to generate a software interrupt.

174/779



Configure the corresponding mask bit (EXTI_IMR, EXTI_EMR)



Set the required bit of the software interrupt register (EXTI_SWIER)

DocID025023 Rev 4

RM0360

11.2.5

Interrupts and events

External and internal interrupt/event line mapping
The GPIOs are connected to the 16 external interrupt/event lines in the following manner:
Figure 22. External interrupt/event GPIO mapping
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The remaining lines are connected as follow:

Note:



EXTI line 16 is reserved (internally held low)



EXTI line 17 is connected to the RTC Alarm event



EXTI line 18 is connected to the internal USB wakeup event



EXTI line 19 is connected to the RTC Tamper and TimeStamp events



EXTI line 20 is connected to the RTC Wakeup event (available only on STM32F070xB
and STM32F030xC devices)



EXTI line 21 is reserved (internally held low)



EXTI line 22 is reserved (internally held low)



EXTI line 23 is reserved (internally held low)



EXTI line 24 is reserved (internally held low)



EXTI line 25 is reserved (internally held low)



EXTI line 26 is reserved (internally held low)



EXTI line 27 is reserved (internally held low)



EXTI line 28 is reserved (internally held low)



EXTI line 29 is reserved (internally held low)



EXTI line 30 is reserved (internally held low)



EXTI line 31 is reserved (internally held low)

EXTI lines which are reserved or not used on some devices are considered as internal.

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180

Interrupts and events

11.3

RM0360

EXTI registers
Refer to Section 1.1 on page 33 for a list of abbreviations used in register descriptions.
The peripheral registers have to be accessed by words (32-bit).

11.3.1

Interrupt mask register (EXTI_IMR)
Address offset: 0x00
Reset value: 0x0FF4 0000 (STM32F030x4, STM32F030x6 devices)
0x7FF4 0000 (STM32F070x6 devices)
0x0F94 0000 (STM32F030x8 devices)
0x7F84 0000 (STM32F070xB and STM32F030xC devices)

Note:

The reset value for the internal lines is set to ‘1’ in order to enable the interrupt by default.

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

IM31

IM30

IM29

IM28

IM27

IM26

IM25

IM24

IM23

IM22

IM21

IM20

IM19

IM18

IM17

IM16

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

IM15

IM14

IM13

IM12

IM11

IM10

IM9

IM8

IM7

IM6

IM5

IM4

IM3

IM2

IM1

IM0

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

Bits 31:0 IMx: Interrupt Mask on line x (x = 31 to 0)
0: Interrupt request from Line x is masked
1: Interrupt request from Line x is not masked

11.3.2

Event mask register (EXTI_EMR)
Address offset: 0x04
Reset value: 0x0000 0000

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

EM31

EM30

EM29

EM28

EM27

EM26

EM25

EM24

EM23

EM22

EM21

EM20

EM19

EM18

EM17

EM16

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

EM15

EM14

EM13

EM12

EM11

EM10

EM9

EM8

EM7

EM6

EM5

EM4

EM3

EM2

EM1

EM0

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

Bits 31:0 EMx: Event mask on line x (x = 31 to 0)
0: Event request from Line x is masked
1: Event request from Line x is not masked

11.3.3

Rising trigger selection register (EXTI_RTSR)
Address offset: 0x08
Reset value: 0x0000 0000

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

RT31

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

RT22

RT21

RT20

RT19

Res.

RT17

RT16

rw

rw

rw

rw

rw

rw

rw

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RM0360

Interrupts and events

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

RT15

RT14

RT13

RT12

RT11

RT10

RT9

RT8

RT7

RT6

RT5

RT4

RT3

RT2

RT1

RT0

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

Bit 31 RT31: Rising trigger event configuration bit of line 31
0: Rising trigger disabled (for Event and Interrupt) for input line
1: Rising trigger enabled (for Event and Interrupt) for input line.
Bits 30:23 Reserved, must be kept at reset value.
Bits 22:19 RTx: Rising trigger event configuration bit of line x (x = 22 to 19)
0: Rising trigger disabled (for Event and Interrupt) for input line
1: Rising trigger enabled (for Event and Interrupt) for input line.
Bits 18 Reserved, must be kept at reset value.
Bits 17:0 RTx: Rising trigger event configuration bit of line x (x = 17 to 0)
0: Rising trigger disabled (for Event and Interrupt) for input line
1: Rising trigger enabled (for Event and Interrupt) for input line.

Note:

The external wakeup lines are edge triggered. No glitches must be generated on these
lines. If a rising edge on an external interrupt line occurs during a write operation to the
EXTI_RTSR register, the pending bit is not set.
Rising and falling edge triggers can be set for the same interrupt line. In this case, both
generate a trigger condition.

11.3.4

Falling trigger selection register (EXTI_FTSR)
Address offset: 0x0C
Reset value: 0x0000 0000

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

FT31

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

FT22

FT21

FT20

FT19

Res.

FT17

FT16

rw

rw

rw

rw

rw

rw

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

FT15

FT14

FT13

FT12

FT11

FT10

FT9

FT8

FT7

FT6

FT5

FT4

FT3

FT2

FT1

FT1

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

Bit 31 FT31: Falling trigger event configuration bit of line 31
0: Falling trigger disabled (for Event and Interrupt) for input line
1: Falling trigger enabled (for Event and Interrupt) for input line.
Bits 30:23 Reserved, must be kept at reset value.
Bits 22:19 FTx: Falling trigger event configuration bit of line x (x = 22 to 19)
0: Falling trigger disabled (for Event and Interrupt) for input line.
1: Falling trigger enabled (for Event and Interrupt) for input line.
Bits 18 Reserved, must be kept at reset value.
Bits 17:0 FTx: Falling trigger event configuration bit of line x (x = 17 to 0)
0: Falling trigger disabled (for Event and Interrupt) for input line.
1: Falling trigger enabled (for Event and Interrupt) for input line.

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Interrupts and events
Note:

RM0360

The external wakeup lines are edge triggered. No glitches must be generated on these
lines. If a falling edge on an external interrupt line occurs during a write operation to the
EXTI_FTSR register, the pending bit is not set.
Rising and falling edge triggers can be set for the same interrupt line. In this case, both
generate a trigger condition.

11.3.5

Software interrupt event register (EXTI_SWIER)
Address offset: 0x10
Reset value: 0x0000 0000

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

SWI31

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

SWI22

SWI21

SWI20

SWI19

Res.

SWI17

SWI16

rw

rw

rw

rw

rw

rw

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

SWI15

SWI14

SWI13

SWI12

SWI11

SWI10

SWI9

SWI8

SWI7

SWI6

SWI5

SWI4

SWI3

SWI2

SWI1

SWI0

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

Bit 31 SWI31: Software interrupt on line 31
If the interrupt is enabled on this line in the EXTI_IMR, writing a ‘1’ to this bit when it is at ‘0’
sets the corresponding pending bit in EXTI_PR resulting in an interrupt request generation.
This bit is cleared by clearing the corresponding bit of EXTI_PR (by writing a ‘1’ to the bit)
Bits 30:23 Reserved, must be kept at reset value.
Bits 22:19 SWIx: Software interrupt on line x (x = 22 to 19)
If the interrupt is enabled on this line in the EXTI_IMR, writing a ‘1’ to this bit when it is at ‘0’
sets the corresponding pending bit in EXTI_PR resulting in an interrupt request generation.
This bit is cleared by clearing the corresponding bit of EXTI_PR (by writing a ‘1’ to the bit)
Bits 18 Reserved, must be kept at reset value.
Bits 17:0 SWIx: Software interrupt on line x (x = 17 to 0)
If the interrupt is enabled on this line in the EXTI_IMR, writing a ‘1’ to this bit when it is at ‘0’
sets the corresponding pending bit in EXTI_PR resulting in an interrupt request generation.
This bit is cleared by clearing the corresponding bit of EXTI_PR (by writing a ‘1’ to the bit).

11.3.6

Pending register (EXTI_PR)
Address offset: 0x14
Reset value: undefined

31

30

29

28

27

26

25

24

23

22

21

20

PIF31

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

PIF22

PIF21

rc_w1

rc_w1

rc_w1

19

18

PIF20

PIF19

Res.

rc_w1

rc_w1

17

16

PIF17

PIF16

rc_w1

rc_w1

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

PIF15

PIF14

PIF13

PIF12

PIF11

PIF10

PIF9

PIF8

PIF7

PIF6

PIF5

PIF4

PIF3

PIF2

PIF1

PIF0

rc_w1

rc_w1

rc_w1

rc_w1

rc_w1

rc_w1

rc_w1

rc_w1

rc_w1

rc_w1

rc_w1

rc_w1

rc_w1

rc_w1

rc_w1

rc_w1

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RM0360

Interrupts and events

Bit 31 PIF31: Pending bit on line 31
0: no trigger request occurred
1: selected trigger request occurred
This bit is set when the selected edge event arrives on the external interrupt line. This bit is
cleared by writing a 1 to the bit.
Bits 30:23 Reserved, must be kept at reset value.
Bits 22:19 PIFx: Pending bit on line x (x = 22 to 19)
0: no trigger request occurred
1: selected trigger request occurred
This bit is set when the selected edge event arrives on the external interrupt line. This bit is
cleared by writing a 1 to the bit.
Bits 18 Reserved, must be kept at reset value.
Bits 17:0 PIFx: Pending bit on line x (x = 17 to 0)
0: no trigger request occurred
1: selected trigger request occurred
This bit is set when the selected edge event arrives on the external interrupt line. This bit is
cleared by writing a 1 to the bit.

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Interrupts and events

11.3.7

RM0360

EXTI register map
The following table gives the EXTI register map and the reset values.

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Res.

0

0

0

0

0

0

0

0

0

0

RT[17:0]
0

0

0

0

0

0

0

0

Res.

RT19

0

0

0

0

FT[17:0]
0

0

0

0

0

0

0

0

Res.

0

0

0

0

SWI[17:0]
0

0

0

0

0

0

0

0

Res.

RT20
0

SWI19

0

PIF19

FT19

RT21

0

SWI20

FT20

RT22

0

PIF20

Res.
Res.

Res.
Res.

Res.
Res.

Res.

Res.
Res.

Res.

FT21

0

0

FT22

Reset value

0

SWI21

EXTI_PR

0

SWI22

0

0

PIF21

Reset value

0

PIF22

EXTI_SWIER

0

Res.

0

0

RT23

Reset value

0

FT23

Res.

EXTI_FTSR

0

SWI23

Res.

0

0

PIF23

Res.

Reset value

0

Res.

EXTI_RTSR

0

Res.

0

Res.

0

Res.

0

Res.

0

Res.

0

Res.

0

Res.

0

Res.

Reset value

Res.

EM[31:0]

Res.

EXTI_EMR

Res.

0x14

0

RT31

0x10

0

FT31

0x0C

0

Res.

0x08

IM[31:0]
0

SWI31

0x04

EXTI_IMR
Reset value

Res.

0x00

Register

PIF31

Offset

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0

Table 33. External interrupt/event controller register map and reset values

0

0

PIF[17:0]
0

0

0

0

0

0

0

0

0

0

Refer to Section 2.2.2 on page 37 for the register boundary addresses.

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RM0360

Analog-to-digital converter (ADC)

12

Analog-to-digital converter (ADC)

12.1

Introduction
The 12-bit ADC is a successive approximation analog-to-digital converter. It has up to 19
multiplexed channels allowing it to measure signals from 16 external and 2 internal sources.
A/D conversion of the various channels can be performed in single, continuous, scan or
discontinuous mode. The result of the ADC is stored in a left-aligned or right-aligned 16-bit
data register.
The analog watchdog feature allows the application to detect if the input voltage goes
outside the user-defined higher or lower thresholds.
An efficient low-power mode is implemented to allow very low consumption at low
frequency.

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Analog-to-digital converter (ADC)

12.2

RM0360

ADC main features










High performance
–

12-bit, 10-bit, 8-bit or 6-bit configurable resolution

–

ADC conversion time: 1.0 µs for 12-bit resolution (1 MHz), 0.93 µs conversion
time for 10-bit resolution, faster conversion times can be obtained by lowering
resolution.

–

Self-calibration

–

Programmable sampling time

–

Data alignment with built-in data coherency

–

DMA support

Low-power
–

Application can reduce PCLK frequency for low-power operation while still
keeping optimum ADC performance. For example, 1.0 µs conversion time is kept,
whatever the frequency of PCLK)

–

Wait mode: prevents ADC overrun in applications with low frequency PCLK

–

Auto off mode: ADC is automatically powered off except during the active
conversion phase. This dramatically reduces the power consumption of the ADC.

Analog input channels
–

16 external analog inputs

–

1 channel for internal temperature sensor (VSENSE)

–

1 channel for internal reference voltage (VREFINT)

Start-of-conversion can be initiated:
–

By software

–

By hardware triggers with configurable polarity (internal timer events from TIM1,
TIM3 and TIM15)

Conversion modes
–

Can convert a single channel or can scan a sequence of channels.

–

Single mode converts selected inputs once per trigger

–

Continuous mode converts selected inputs continuously

–

Discontinuous mode



Interrupt generation at the end of sampling, end of conversion, end of sequence
conversion, and in case of analog watchdog or overrun events



Analog watchdog



ADC supply requirements: 2.4 V to 3.6 V



ADC input range: VSSA ≤ VIN ≤ VDDA

Figure 23 shows the block diagram of the ADC.

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RM0360

12.3

Analog-to-digital converter (ADC)

ADC pins and internal signals
Table 34. ADC internal signals
Internal signal
name

Signal type

TRGx

Input

ADC conversion triggers

VSENSE

Input

Internal temperature sensor output voltage

VREFINT

Input

Internal voltage reference output voltage

Description

Table 35. ADC pins
Name

Signal type

Remarks

VDDA

Input, analog power
supply

Analog power supply and positive reference voltage
for the ADC, VDDA ≥ VDD

VSSA

Input, analog supply
ground

Ground for analog power supply. Must be at VSS
potential

ADC_IN[15:0]

Analog input signals

16 analog input channels

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Analog-to-digital converter (ADC)

12.4

RM0360

ADC functional description
Figure 23 shows the ADC block diagram and Table 35 gives the ADC pin description.
Figure 23. ADC block diagram
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12.4.1

Calibration (ADCAL)
The ADC has a calibration feature. During the procedure, the ADC calculates a calibration
factor which is internally applied to the ADC until the next ADC power-off. The application
must not use the ADC during calibration and must wait until it is complete.
Calibration should be performed before starting A/D conversion. It removes the offset error
which may vary from chip to chip due to process variation.
The calibration is initiated by software by setting bit ADCAL=1. Calibration can only be
initiated when the ADC is disabled (when ADEN=0). ADCAL bit stays at 1 during all the
calibration sequence. It is then cleared by hardware as soon the calibration completes. After
this, the calibration factor can be read from the ADC_DR register (from bits 6 to 0).
The internal analog calibration is kept if the ADC is disabled (ADEN=0). When the ADC
operating conditions change (VDDA changes are the main contributor to ADC offset
variations and temperature change to a lesser extend), it is recommended to re-run a
calibration cycle.

184/779

DocID025023 Rev 4

RM0360

Analog-to-digital converter (ADC)
The calibration factor is lost each time power is removed from the ADC (for example when
the product enters STANDBY mode).
Calibration software procedure
1.

Ensure that ADEN=0 and DMAEN=0

2.

Set ADCAL=1

3.

Wait until ADCAL=0

4.

The calibration factor can be read from bits 6:0 of ADC_DR.

For code example refer to the Appendix section A.7.1: ADC Calibration code example.
Figure 24. ADC calibration
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12.4.2

ADC on-off control (ADEN, ADDIS, ADRDY)
At MCU power-up, the ADC is disabled and put in power-down mode (ADEN=0).
As shown in Figure 25, the ADC needs a stabilization time of tSTAB before it starts
converting accurately.
Two control bits are used to enable or disable the ADC:


Set ADEN=1 to enable the ADC. The ADRDY flag is set as soon as the ADC is ready
for operation.



Set ADDIS=1 to disable the ADC and put the ADC in power down mode. The ADEN
and ADDIS bits are then automatically cleared by hardware as soon as the ADC is fully
disabled.

Conversion can then start either by setting ADSTART=1 (refer to Section 12.5: Conversion
on external trigger and trigger polarity (EXTSEL, EXTEN) on page 192) or when an external
trigger event occurs if triggers are enabled.
Follow this procedure to enable the ADC:
1.

Clear the ADRDY bit in ADC_ISR register by programming this bit to 1.

2.

Set ADEN=1 in the ADC_CR register.

3.

Wait until ADRDY=1 in the ADC_ISR register and continue to write ADEN=1 (ADRDY
is set after the ADC startup time). This can be handled by interrupt if the interrupt is
enabled by setting the ADRDYIE bit in the ADC_IER register.

For code example refer to the Appendix section A.7.2: ADC enable sequence code
example.

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220

Analog-to-digital converter (ADC)

RM0360

Follow this procedure to disable the ADC:
1.

Check that ADSTART=0 in the ADC_CR register to ensure that no conversion is
ongoing. If required, stop any ongoing conversion by writing 1 to the ADSTP bit in the
ADC_CR register and waiting until this bit is read at 0.

2.

Set ADDIS=1 in the ADC_CR register.

3.

If required by the application, wait until ADEN=0 in the ADC_CR register, indicating that
the ADC is fully disabled (ADDIS is automatically reset once ADEN=0).

4.

Clear the ADRDY bit in ADC_ISR register by programming this bit to 1 (optional).

For code example refer to the Appendix section A.7.3: ADC disable sequence code
example.
Caution:

ADEN bit cannot be set when ADCAL=1 and during four ADC clock cycles after the ADCAL
bit is cleared by hardware (end of calibration).
Figure 25. Enabling/disabling the ADC
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In auto-off mode (AUTOFF=1) the power-on/off phases are performed automatically, by
hardware and the ADRDY flag is not set.

DocID025023 Rev 4

RM0360

12.4.3

Analog-to-digital converter (ADC)

ADC clock (CKMODE)
The ADC has a dual clock-domain architecture, so that the ADC can be fed with a clock
(ADC asynchronous clock) independent from the APB clock (PCLK).
Figure 26. ADC clock scheme
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1. Refer to Section 7: Reset and clock control (RCC) on page 87 to see how PCLK and ADC asynchronous
clock are enabled.

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Analog-to-digital converter (ADC)

RM0360

The input clock of the analog ADC can be selected between two different clock sources (see
Figure 26: ADC clock scheme to see how PCLK and the ADC asynchronous clock are
enabled):
a)

The ADC clock can be a specific clock source, named “ADC asynchronous clock
“which is independent and asynchronous with the APB clock.
Refer to RCC Section for more information on generating this clock source.
To select this scheme, bits CKMODE[1:0] of the ADC_CFGR2 register must be
reset.
For code example refer to the Appendix section A.7.4: ADC Clock selection code
example.

b)

The ADC clock can be derived from the APB clock of the ADC bus interface,
divided by a programmable factor (2 or 4) according to bits CKMODE[1:0].
To select this scheme, bits CKMODE[1:0] of the ADC_CFGR2 register must be
different from “00”.

Option a) has the advantage of reaching the maximum ADC clock frequency whatever the
APB clock scheme selected.
Option b) has the advantage of bypassing the clock domain resynchronizations. This can be
useful when the ADC is triggered by a timer and if the application requires that the ADC is
precisely triggered without any uncertainty (otherwise, an uncertainty of the trigger instant is
added by the resynchronizations between the two clock domains).
Table 36. Latency between trigger and start of conversion
ADC clock source

12.4.4

CKMODE[1:0]

Latency between the trigger event
and the start of conversion

Dedicated 14MHz clock

00

Latency is not deterministic (jitter)

PCLK divided by 2

01

Latency is deterministic (no jitter) and equal to
2.75 ADC clock cycles

PCLK divided by 4

10

Latency is deterministic (no jitter) and equal to
2.625 ADC clock cycles

Configuring the ADC
Software must write to the ADCAL and ADEN bits in the ADC_CR register if the ADC is
disabled (ADEN must be 0).
Software must only write to the ADSTART and ADDIS bits in the ADC_CR register only if
the ADC is enabled and there is no pending request to disable the ADC (ADEN = 1 and
ADDIS = 0).
For all the other control bits in the ADC_IER, ADC_CFGRi, ADC_SMPR, ADC_TR,
ADC_CHSELR and ADC_CCR registers, software must only write to the configuration
control bits if the ADC is enabled (ADEN = 1) and if there is no conversion ongoing
(ADSTART = 0).
Software must only write to the ADSTP bit in the ADC_CR register if the ADC is enabled
(and possibly converting) and there is no pending request to disable the ADC (ADSTART =
1 and ADDIS = 0)

Note:

188/779

There is no hardware protection preventing software from making write operations forbidden
by the above rules. If such a forbidden write access occurs, the ADC may enter an

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RM0360

Analog-to-digital converter (ADC)
undefined state. To recover correct operation in this case, the ADC must be disabled (clear
ADEN=0 and all the bits in the ADC_CR register).

12.4.5

Channel selection (CHSEL, SCANDIR)
There are up to 18 multiplexed channels:


16 analog inputs from GPIO pins (ADC_IN0...ADC_IN15)



2 internal analog inputs (Temperature Sensor, Internal Reference Voltage )

It is possible to convert a single channel or to automatically scan a sequence of channels.
The sequence of the channels to be converted must be programmed in the ADC_CHSELR
channel selection register: each analog input channel has a dedicated selection bit
(CHSEL0...CHSEL18).
The order in which the channels will be scanned can be configured by programming the bit
SCANDIR bit in the ADC_CFGR1 register:


SCANDIR=0: forward scan Channel 0 to Channel 18



SCANDIR=1: backward scan Channel 18 to Channel 0

Temperature sensor, VREFINT internal channels
The temperature sensor is connected to channel ADC_IN16. The internal voltage reference
VREFINT is connected to channel ADC_IN17.

12.4.6

Programmable sampling time (SMP)
Before starting a conversion, the ADC needs to establish a direct connection between the
voltage source to be measured and the embedded sampling capacitor of the ADC. This
sampling time must be enough for the input voltage source to charge the sample and hold
capacitor to the input voltage level.
Having a programmable sampling time allows to trim the conversion speed according to the
input resistance of the input voltage source.
The ADC samples the input voltage for a number of ADC clock cycles that can be modified
using the SMP[2:0] bits in the ADC_SMPR register.
This programmable sampling time is common to all channels. If required by the application,
the software can change and adapt this sampling time between each conversions.
The total conversion time is calculated as follows:
tCONV = Sampling time + 12.5 x ADC clock cycles
Example:
With ADC_CLK = 14 MHz and a sampling time of 1.5 ADC clock cycles:
tCONV = 1.5 + 12.5 = 14 ADC clock cycles = 1 µs
The ADC indicates the end of the sampling phase by setting the EOSMP flag.

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Analog-to-digital converter (ADC)

12.4.7

RM0360

Single conversion mode (CONT=0)
In Single conversion mode, the ADC performs a single sequence of conversions, converting
all the channels once. This mode is selected when CONT=0 in the ADC_CFGR1 register.
Conversion is started by either:


Setting the ADSTART bit in the ADC_CR register



Hardware trigger event

Inside the sequence, after each conversion is complete:


The converted data are stored in the 16-bit ADC_DR register



The EOC (end of conversion) flag is set



An interrupt is generated if the EOCIE bit is set

After the sequence of conversions is complete:


The EOSEQ (end of sequence) flag is set



An interrupt is generated if the EOSEQIE bit is set

Then the ADC stops until a new external trigger event occurs or the ADSTART bit is set
again.
Note:

To convert a single channel, program a sequence with a length of 1.

12.4.8

Continuous conversion mode (CONT=1)
In continuous conversion mode, when a software or hardware trigger event occurs, the ADC
performs a sequence of conversions, converting all the channels once and then
automatically re-starts and continuously performs the same sequence of conversions. This
mode is selected when CONT=1 in the ADC_CFGR1 register. Conversion is started by
either:


Setting the ADSTART bit in the ADC_CR register



Hardware trigger event

Inside the sequence, after each conversion is complete:


The converted data are stored in the 16-bit ADC_DR register



The EOC (end of conversion) flag is set



An interrupt is generated if the EOCIE bit is set

After the sequence of conversions is complete:


The EOSEQ (end of sequence) flag is set



An interrupt is generated if the EOSEQIE bit is set

Then, a new sequence restarts immediately and the ADC continuously repeats the
conversion sequence.
Note:

To convert a single channel, program a sequence with a length of 1.
It is not possible to have both discontinuous mode and continuous mode enabled: it is
forbidden to set both bits DISCEN=1 and CONT=1.

12.4.9

Starting conversions (ADSTART)
Software starts ADC conversions by setting ADSTART=1.

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RM0360

Analog-to-digital converter (ADC)
When ADSTART is set, the conversion:


Starts immediately if EXTEN = 00 (software trigger)



At the next active edge of the selected hardware trigger if EXTEN ≠ 00

The ADSTART bit is also used to indicate whether an ADC operation is currently ongoing. It
is possible to re-configure the ADC while ADSTART=0, indicating that the ADC is idle.
The ADSTART bit is cleared by hardware:


In single mode with software trigger (CONT=0, EXTEN=00)
–



At any end of conversion sequence (EOSEQ=1)

In discontinuous mode with software trigger (CONT=0, DISCEN=1, EXTEN=00)
–



At end of conversion (EOC=1)

In all cases (CONT=x, EXTEN=XX)
–

Note:

After execution of the ADSTP procedure invoked by software (see
Section 12.4.11: Stopping an ongoing conversion (ADSTP) on page 192)

In continuous mode (CONT=1), the ADSTART bit is not cleared by hardware when the
EOSEQ flag is set because the sequence is automatically relaunched.
When hardware trigger is selected in single mode (CONT=0 and EXTEN = 01), ADSTART is
not cleared by hardware when the EOSEQ flag is set. This avoids the need for software
having to set the ADSTART bit again and ensures the next trigger event is not missed.

12.4.10

Timings
The elapsed time between the start of a conversion and the end of conversion is the sum of
the configured sampling time plus the successive approximation time depending on data
resolution:
tADC = tSMPL + tSAR = [1.5 |min + 12.5 |12bit] x tADC_CLK
tADC = tSMPL + tSAR = 107.1 ns |min + 892.8 ns |12bit = 1 µs |min (for fADC_CLK = 14 MHz)

Figure 27. Analog to digital conversion time
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220

Analog-to-digital converter (ADC)

RM0360
Figure 28. ADC conversion timings

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2. Trigger latency (refer to datasheet for more details)
3. ADC_DR register write latency (refer to datasheet for more details)

12.4.11

Stopping an ongoing conversion (ADSTP)
The software can decide to stop any ongoing conversions by setting ADSTP=1 in the
ADC_CR register.
This will reset the ADC operation and the ADC will be idle, ready for a new operation.
When the ADSTP bit is set by software, any ongoing conversion is aborted and the result is
discarded (ADC_DR register is not updated with the current conversion).
The scan sequence is also aborted and reset (meaning that restarting the ADC would restart a new sequence).
Once this procedure is complete, the ADSTP and ADSTART bits are both cleared by
hardware and the software must wait until ADSTART=0 before starting new conversions.
Figure 29. Stopping an ongoing conversion
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12.5

Conversion on external trigger and trigger polarity (EXTSEL,
EXTEN)
A conversion or a sequence of conversion can be triggered either by software or by an
external event (for example timer capture). If the EXTEN[1:0] control bits are not equal to
“0b00”, then external events are able to trigger a conversion with the selected polarity. The
trigger selection is effective once software has set bit ADSTART=1.
Any hardware triggers which occur while a conversion is ongoing are ignored.

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RM0360

Analog-to-digital converter (ADC)
If bit ADSTART=0, any hardware triggers which occur are ignored.
Table 37 provides the correspondence between the EXTEN[1:0] values and the trigger
polarity.
Table 37. Configuring the trigger polarity
Source

Note:

EXTEN[1:0]

Trigger detection disabled

00

Detection on rising edge

01

Detection on falling edge

10

Detection on both rising and falling edges

11

The polarity of the external trigger can be changed only when the ADC is not converting
(ADSTART= 0).
The EXTSEL[2:0] control bits are used to select which of 8 possible events can trigger
conversions.
Table 38 gives the possible external trigger for regular conversion.
Software source trigger events can be generated by setting the ADSTART bit in the
ADC_CR register.
Table 38. External triggers
Name

Source

EXTSEL[2:0]

TRG0

TIM1_TRGO

000

TRG1

TIM1_CC4

001

TRG2

Reserved

010

TRG3

TIM3_TRGO

011

TRG4

TIM15_TRGO

100

TRG5

Reserved

101

TRG6

Reserved

110

TRG7

Reserved

111

Note:

The trigger selection can be changed only when the ADC is not converting (ADSTART= 0).

12.5.1

Discontinuous mode (DISCEN)
This mode is enabled by setting the DISCEN bit in the ADC_CFGR1 register.
In this mode (DISCEN=1), a hardware or software trigger event is required to start each
conversion defined in the sequence. On the contrary, if DISCEN=0, a single hardware or
software trigger event successively starts all the conversions defined in the sequence.

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Analog-to-digital converter (ADC)

RM0360

Example:




DISCEN=1, channels to be converted = 0, 3, 7, 10
–

1st trigger: channel 0 is converted and an EOC event is generated

–

2nd trigger: channel 3 is converted and an EOC event is generated

–

3rd trigger: channel 7 is converted and an EOC event is generated

–

4th trigger: channel 10 is converted and both EOC and EOSEQ events are
generated.

–

5th trigger: channel 0 is converted an EOC event is generated

–

6th trigger: channel 3 is converted and an EOC event is generated

–

...

DISCEN=0, channels to be converted = 0, 3, 7, 10
–

1st trigger: the complete sequence is converted: channel 0, then 3, 7 and 10. Each
conversion generates an EOC event and the last one also generates an EOSEQ
event.

–

Any subsequent trigger events will restart the complete sequence.

Note:

It is not possible to have both discontinuous mode and continuous mode enabled: it is
forbidden to set both bits DISCEN=1 and CONT=1.

12.5.2

Programmable resolution (RES) - fast conversion mode
It is possible to obtain faster conversion times (tSAR) by reducing the ADC resolution.
The resolution can be configured to be either 12, 10, 8, or 6 bits by programming the
RES[1:0] bits in the ADC_CFGR1 register. Lower resolution allows faster conversion times
for applications where high data precision is not required.

Note:

The RES[1:0] bit must only be changed when the ADEN bit is reset.
The result of the conversion is always 12 bits wide and any unused LSB bits are read as
zeros.
Lower resolution reduces the conversion time needed for the successive approximation
steps as shown in Table 39.
Table 39. tSAR timings depending on resolution
RES[1:0]
bits

194/779

tSAR
(ADC clock
cycles)

tSAR (ns) at
fADC = 14 MHz

tSMPL (min)

tCONV

(ADC clock
cycles)

(ADC clock cycles)
(with min. tSMPL)

tCONV at fADC =
14 MHz

12

12.5

893 ns

1.5

14

1000 ns

10

11.5

821 ns

1.5

13

928 ns

8

9.5

678 ns

1.5

11

785 ns

6

7.5

535 ns

1.5

9

643 ns

DocID025023 Rev 4

RM0360

12.5.3

Analog-to-digital converter (ADC)

End of conversion, end of sampling phase (EOC, EOSMP flags)
The ADC indicates each end of conversion (EOC) event.
The ADC sets the EOC flag in the ADC_ISR register as soon as a new conversion data
result is available in the ADC_DR register. An interrupt can be generated if the EOCIE bit is
set in the ADC_IER register. The EOC flag is cleared by software either by writing 1 to it, or
by reading the ADC_DR register.
The ADC also indicates the end of sampling phase by setting the EOSMP flag in the
ADC_ISR register. The EOSMP flag is cleared by software by writing1 to it. An interrupt can
be generated if the EOSMPIE bit is set in the ADC_IER register.
The aim of this interrupt is to allow the processing to be synchronized with the conversions.
Typically, an analog multiplexer can be accessed in hidden time during the conversion
phase, so that the multiplexer is positioned when the next sampling starts.

Note:

As there is only a very short time left between the end of the sampling and the end of the
conversion, it is recommenced to use polling or a WFE instruction rather than an interrupt
and a WFI instruction.

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220

Analog-to-digital converter (ADC)

12.5.4

RM0360

End of conversion sequence (EOSEQ flag)
The ADC notifies the application of each end of sequence (EOSEQ) event.
The ADC sets the EOSEQ flag in the ADC_ISR register as soon as the last data result of a
conversion sequence is available in the ADC_DR register. An interrupt can be generated if
the EOSEQIE bit is set in the ADC_IER register. The EOSEQ flag is cleared by software by
writing 1 to it.

12.5.5

Example timing diagrams (single/continuous modes
hardware/software triggers)
Figure 30. Single conversions of a sequence, software trigger


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2. CHSEL=0x20601, WAIT=0, AUTOFF=0

For code example refer to the Appendix section A.7.5: Single conversion sequence code
example - Software trigger.
Figure 31. Continuous conversion of a sequence, software trigger
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2. CHSEL=0x20601, WAIT=0, AUTOFF=0

For code example refer to the Appendix section A.7.6: Continuous conversion sequence
code example - Software trigger.

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RM0360

Analog-to-digital converter (ADC)
Figure 32. Single conversions of a sequence, hardware trigger

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1. EXTSEL=TRGx (over-frequency), EXTEN=01 (rising edge), CONT=0
2. CHSEL=0xF, SCANDIR=0, WAIT=0, AUTOFF=0

For code example refer to the Appendix section A.7.7: Single conversion sequence code
example - Hardware trigger.
Figure 33. Continuous conversions of a sequence, hardware trigger
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2. CHSEL=0xF, SCANDIR=0, WAIT=0, AUTOFF=0

For code example refer to the Appendix section A.7.8: Continuous conversion sequence
code example - Hardware trigger.

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Analog-to-digital converter (ADC)

RM0360

12.6

Data management

12.6.1

Data register and data alignment (ADC_DR, ALIGN)
At the end of each conversion (when an EOC event occurs), the result of the converted data
is stored in the ADC_DR data register which is 16-bit wide.
The format of the ADC_DR depends on the configured data alignment and resolution.
The ALIGN bit in the ADC_CFGR1 register selects the alignment of the data stored after
conversion. Data can be right-aligned (ALIGN=0) or left-aligned (ALIGN=1) as shown in
Figure 34.
Figure 34. Data alignment and resolution


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12.6.2

ADC overrun (OVR, OVRMOD)
The overrun flag (OVR) indicates a data overrun event, when the converted data was not
read in time by the CPU or the DMA, before the data from a new conversion is available.
The OVR flag is set in the ADC_ISR register if the EOC flag is still at ‘1’ at the time when a
new conversion completes. An interrupt can be generated if the OVRIE bit is set in the
ADC_IER register.
When an overrun condition occurs, the ADC keeps operating and can continue to convert
unless the software decides to stop and reset the sequence by setting the ADSTP bit in the
ADC_CR register.
The OVR flag is cleared by software by writing 1 to it.
It is possible to configure if the data is preserved or overwritten when an overrun event
occurs by programming the OVRMOD bit in the ADC_CFGR1 register:


OVRMOD=0
–



OVRMOD=1
–

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An overrun event preserves the data register from being overwritten: the old data
is maintained and the new conversion is discarded. If OVR remains at 1, further
conversions can be performed but the resulting data is discarded.
The data register is overwritten with the last conversion result and the previous
unread data is lost. If OVR remains at 1, further conversions can be performed
and the ADC_DR register always contains the data from the latest conversion.

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Analog-to-digital converter (ADC)
Figure 35. Example of overrun (OVR)

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12.6.3

Managing a sequence of data converted without using the DMA
If the conversions are slow enough, the conversion sequence can be handled by software.
In this case the software must use the EOC flag and its associated interrupt to handle each
data result. Each time a conversion is complete, the EOC bit is set in the ADC_ISR register
and the ADC_DR register can be read. The OVRMOD bit in the ADC_CFGR1 register
should be configured to 0 to manage overrun events as an error.

12.6.4

Managing converted data without using the DMA without overrun
It may be useful to let the ADC convert one or more channels without reading the data after
each conversion. In this case, the OVRMOD bit must be configured at 1 and the OVR flag
should be ignored by the software. When OVRMOD=1, an overrun event does not prevent
the ADC from continuing to convert and the ADC_DR register always contains the latest
conversion data.

12.6.5

Managing converted data using the DMA
Since all converted channel values are stored in a single data register, it is efficient to use
DMA when converting more than one channel. This avoids losing the conversion data
results stored in the ADC_DR register.
When DMA mode is enabled (DMAEN bit set to 1 in the ADC_CFGR1 register), a DMA
request is generated after the conversion of each channel. This allows the transfer of the
converted data from the ADC_DR register to the destination location selected by the
software.

Note:

The DMAEN bit in the ADC_CFGR1 register must be set after the ADC calibration phase.

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Despite this, if an overrun occurs (OVR=1) because the DMA could not serve the DMA
transfer request in time, the ADC stops generating DMA requests and the data
corresponding to the new conversion is not transferred by the DMA. Which means that all
the data transferred to the RAM can be considered as valid.
Depending on the configuration of OVRMOD bit, the data is either preserved or overwritten
(refer to Section 12.6.2: ADC overrun (OVR, OVRMOD) on page 198).
The DMA transfer requests are blocked until the software clears the OVR bit.
Two different DMA modes are proposed depending on the application use and are
configured with bit DMACFG in the ADC_CFGR1 register:


DMA one shot mode (DMACFG=0). 
This mode should be selected when the DMA is programmed to transfer a fixed
number of data words.



DMA circular mode (DMACFG=1)
This mode should be selected when programming the DMA in circular mode or double
buffer mode.

DMA one shot mode (DMACFG=0)
In this mode, the ADC generates a DMA transfer request each time a new conversion data
word is available and stops generating DMA requests once the DMA has reached the last
DMA transfer (when a DMA_EOT interrupt occurs, see Section 10: Direct memory access
controller (DMA) on page 152) even if a conversion has been started again.
For code example refer to the Appendix section A.7.9: DMA one shot mode sequence code
example.
When the DMA transfer is complete (all the transfers configured in the DMA controller have
been done):


The content of the ADC data register is frozen.



Any ongoing conversion is aborted and its partial result discarded



No new DMA request is issued to the DMA controller. This avoids generating an
overrun error if there are still conversions which are started.



The scan sequence is stopped and reset



The DMA is stopped

DMA circular mode (DMACFG=1)
In this mode, the ADC generates a DMA transfer request each time a new conversion data
word is available in the data register, even if the DMA has reached the last DMA transfer.
This allows the DMA to be configured in circular mode to handle a continuous analog input
data stream.
For code example refer to the Appendix section A.7.10: DMA circular mode sequence code
example.

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12.7

Low-power features

12.7.1

Wait mode conversion
Wait mode conversion can be used to simplify the software as well as optimizing the
performance of applications clocked at low frequency where there might be a risk of ADC
overrun occurring.
When the WAIT bit is set to 1 in the ADC_CFGR1 register, a new conversion can start only
if the previous data has been treated, once the ADC_DR register has been read or if the
EOC bit has been cleared.
This is a way to automatically adapt the speed of the ADC to the speed of the system that
reads the data.

Note:

Any hardware triggers which occur while a conversion is ongoing or during the wait time
preceding the read access are ignored.
Figure 36. Wait mode conversion (continuous mode, software trigger)
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1. EXTEN=00, CONT=1
2. CHSEL=0x3, SCANDIR=0, WAIT=1, AUTOFF=0

For code example refer to the Appendix section A.7.11: Wait mode sequence code
example.

12.7.2

Auto-off mode (AUTOFF)
The ADC has an automatic power management feature which is called auto-off mode, and
is enabled by setting AUTOFF=1 in the ADC_CFGR1 register.
When AUTOFF=1, the ADC is always powered off when not converting and automatically
wakes-up when a conversion is started (by software or hardware trigger). A startup-time is
automatically inserted between the trigger event which starts the conversion and the
sampling time of the ADC. The ADC is then automatically disabled once the sequence of
conversions is complete.
Auto-off mode can cause a dramatic reduction in the power consumption of applications
which need relatively few conversions or when conversion requests are timed far enough
apart (for example with a low frequency hardware trigger) to justify the extra power and
extra time used for switching the ADC on and off.

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Auto-off mode can be combined with the wait mode conversion (WAIT=1) for applications
clocked at low frequency. This combination can provide significant power savings if the ADC
is automatically powered-off during the wait phase and restarted as soon as the ADC_DR
register is read by the application (see Figure 38: Behavior with WAIT=1, AUTOFF=1).
Note:

Please refer to the Section 7: Reset and clock control (RCC) on page 87 for the description
of how to manage the dedicated 14 MHz internal oscillator. The ADC interface can
automatically switch ON/OFF the 14 MHz internal oscillator to save power.
Figure 37. Behavior with WAIT=0, AUTOFF=1

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1. EXTSEL=TRGx, EXTEN=01 (rising edge), CONT=x, ADSTART=1, CHSEL=0xF, SCANDIR=0, WAIT=1, AUTOFF=1

For code example refer to the Appendix section A.7.12: Auto Off and no wait mode
sequence code example.
Figure 38. Behavior with WAIT=1, AUTOFF=1
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1. EXTSEL=TRGx, EXTEN=01 (rising edge), CONT=x, ADSTART=1, CHSEL=0xF, SCANDIR=0, WAIT=1, AUTOFF=1

For code example refer to the Appendix section A.7.13: Auto Off and wait mode sequence
code example.

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12.8

Analog-to-digital converter (ADC)

Analog window watchdog (AWDEN, AWDSGL, AWDCH,
AWD_HTR/LTR, AWD)
The AWD analog watchdog feature is enabled by setting the AWDEN bit in the
ADC_CFGR1 register. It is used to monitor that either one selected channel or all enabled
channels (see Table 41: Analog watchdog channel selection) remain within a configured
voltage range (window) as shown in Figure 39.
The AWD analog watchdog status bit is set if the analog voltage converted by the ADC is
below a lower threshold or above a higher threshold. These thresholds are programmed in
the 12 least significant bits of the ADC_HTR and ADC_LTR 16-bit registers. An interrupt can
be enabled by setting the AWDIE bit in the ADC_IER register.
The AWD flag is cleared by software by writing 1 to it.
When converting a data with a resolution of less than 12-bit (according to bits DRES[1:0]),
the LSB of the programmed thresholds must be kept cleared because the internal
comparison is always performed on the full 12-bit raw converted data (left aligned).
For code example refer to the Appendix section A.7.14: Analog watchdog code example.
Table 40 describes how the comparison is performed for all the possible resolutions.
Table 40. Analog watchdog comparison

Resolution
bits
RES[1:0]

Analog Watchdog comparison between:
Comments

Raw converted
data, left aligned(1)

Thresholds

00: 12-bit

DATA[11:0]

LT[11:0] and HT[11:0]

-

01: 10-bit

DATA[11:2],00

LT[11:0] and HT[11:0]

The user must configure LT1[1:0] and HT1[1:0] to “00”

10: 8-bit

DATA[11:4],0000

LT[11:0] and HT[11:0]

The user must configure LT1[3:0] and HT1[3:0] to
“0000”

11: 6-bit

DATA[11:6],000000

LT[11:0] and HT[11:0]

The user must configure LT1[5:0] and HT1[5:0] to
“000000”

1. The watchdog comparison is performed on the raw converted data before any alignment calculation.

Table 41 shows how to configure the AWDSGL and AWDEN bits in the ADC_CFGR1
register to enable the analog watchdog on one or more channels.
Figure 39. Analog watchdog guarded area

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Table 41. Analog watchdog channel selection

Channels guarded by the analog watchdog
None
All channels
(1)

Single

channel

AWDSGL bit

AWDEN bit

x

0

0

1

1

1

1. Selected by the AWDCH[4:0] bits

12.9

Temperature sensor and internal reference voltage
The temperature sensor can be used to measure the junction temperature (TJ) of the
device. The temperature sensor is internally connected to the ADC_IN16 input channel
which is used to convert the sensor’s output voltage to a digital value. The sampling time for
the temperature sensor analog pin must be greater than the minimum TS_temp value
specified in the datasheet. When not in use, the sensor can be put in power down mode.
The temperature sensor output voltage changes linearly with temperature, however its
characteristics may vary significantly from chip to chip due to the process variations. To
improve the accuracy of the temperature sensor (especially for absolute temperature
measurement), calibration values are individually measured for each part by ST during
production test and stored in the system memory area. Refer to the specific device
datasheet for additional information.
The internal voltage reference (VREFINT) provides a stable (bandgap) voltage output for the
ADC and Comparators. VREFINT is internally connected to the ADC_IN17 input channel. The
precise voltage of VREFINT is individually measured for each part by ST during production
test and stored in the system memory area. It is accessible in read-only mode.
Figure shows the block diagram of connections between the temperature sensor, the
internal voltage reference and the ADC.
The TSEN bit must be set to enable the conversion of ADC_IN16 (temperature sensor) and
the VREFEN bit must be set to enable the conversion of ADC_IN17 (VREFINT).

Main features


Supported temperature range: –40 to 105 °C



Linearity: ±2 °C max., precision depending on calibration

Reading the temperature
1.

Select the ADC_IN16 input channel

2.

Select an appropriate sampling time specified in the device datasheet (TS_temp).

3.

Set the TSEN bit in the ADC_CCR register to wake up the temperature sensor from
power down mode and wait for its stabilization time (tSTART)
For code example refer to the Appendix section A.7.15: Temperature configuration
code example.

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Analog-to-digital converter (ADC)
4.

Start the ADC conversion by setting the ADSTART bit in the ADC_CR register (or by
external trigger)

5.

Read the resulting data in the ADC_DR register

6.

Calculate the actual temperature using the following formula:
V 30 – V SENSE
Temperature  in °C  = ---------------------------------- + 30 °C
Avg_Slope
TS_DATA
V SENSE = ---------------------------  V DD
4095

For code example refer to the A.7.16: Temperature computation code example.
Note:

The sensor has a startup time after waking from power down mode before it can output
VSENSE at the correct level. The ADC also has a startup time after power-on, so to minimize
the delay, the ADEN and TSEN bits should be set at the same time.

Calculating the actual VDDA voltage using the internal reference voltage
The VDDA power supply voltage applied to the microcontroller may be subject to variation or
not precisely known. The embedded internal voltage reference (VREFINT) and its
calibration data acquired by the ADC during the manufacturing process at VDDA = 3.3 V can
be used to evaluate the actual VDDA voltage level.
The following formula gives the actual VDDA voltage supplying the device:
VDDA = .3 V x VREFINT_CAL / VREFINT_DATA
Where:


VREFINT_CAL is the VREFINT calibration value



VREFINT_DATA is the actual VREFINT output value converted by ADC

Converting a supply-relative ADC measurement to an absolute voltage value
The ADC is designed to deliver a digital value corresponding to the ratio between the analog
power supply and the voltage applied on the converted channel. For most application use
cases, it is necessary to convert this ratio into a voltage independent of VDDA. For
applications where VDDA is known and ADC converted values are right-aligned you can use
the following formula to get this absolute value:
V DDA
V CHANNELx = -------------------------------------  ADC_DATA x
FULL_SCALE

For applications where VDDA value is not known, you must use the internal voltage
reference and VDDA can be replaced by the expression provided in the section Calculating
the actual VDDA voltage using the internal reference voltage, resulting in the following
formula:
3.3 V  VREFINT_CAL  ADC_DATA x
V CHANNELx = ----------------------------------------------------------------------------------------------------VREFINT_DATA  FULL_SCALE

Where:


VREFINT_CAL is the VREFINT calibration value



ADC_DATAx is the value measured by the ADC on channel x (right-aligned)



VREFINT_DATA is the actual VREFINT output value converted by the ADC



full_SCALE is the maximum digital value of the ADC output. For example with 12-bit
resolution, it will be 212 - 1 = 4095 or with 8-bit resolution, 28 - 1 = 255.

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Note:

If ADC measurements are done using an output format other than 12 bit right-aligned, all the
parameters must first be converted to a compatible format before the calculation is done.

12.10

ADC interrupts
An interrupt can be generated by any of the following events:


ADC power-up, when the ADC is ready (ADRDY flag)



End of any conversion (EOC flag)



End of a sequence of conversions (EOSEQ flag)



When an analog watchdog detection occurs (AWD flag)



When the end of sampling phase occurs (EOSMP flag)



when a data overrun occurs (OVR flag)

Separate interrupt enable bits are available for flexibility.
Table 42. ADC interrupts
Interrupt event

Event flag

Enable control bit

ADRDY

ADRDYIE

EOC

EOCIE

End of sequence of conversions

EOSEQ

EOSEQIE

Analog watchdog status bit is set

AWD

AWDIE

EOSMP

EOSMPIE

OVR

OVRIE

ADC ready
End of conversion

End of sampling phase
Overrun

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12.11

ADC registers
Refer to Section 1.1 on page 33 for a list of abbreviations used in register descriptions.

12.11.1

ADC interrupt and status register (ADC_ISR)
Address offset: 0x00
Reset value: 0x0000 0000

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

AWD

Res.

Res.

OVR

EOSEQ

EOC

rc_w1

rc_w1

rc_w1

rc_w1

EOSMP ADRDY
rc_w1

rc_w1

Bits 31:8 Reserved, must be kept at reset value.
Bit 7 AWD: Analog watchdog flag
This bit is set by hardware when the converted voltage crosses the values programmed in the
ADC_LTR and ADC_HTR registers. It is cleared by software writing 1 to it.
0: No analog watchdog event occurred (or the flag event was already acknowledged and cleared by
software)
1: Analog watchdog event occurred
Bit 6:5 Reserved, must be kept at reset value.
Bit 4 OVR: ADC overrun
This bit is set by hardware when an overrun occurs, meaning that a new conversion has complete
while the EOC flag was already set. It is cleared by software writing 1 to it.
0: No overrun occurred (or the flag event was already acknowledged and cleared by software)
1: Overrun has occurred
Bit 3 EOSEQ: End of sequence flag
This bit is set by hardware at the end of the conversion of a sequence of channels selected by the
CHSEL bits. It is cleared by software writing 1 to it.
0: Conversion sequence not complete (or the flag event was already acknowledged and cleared by
software)
1: Conversion sequence complete

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Bit 2 EOC: End of conversion flag
This bit is set by hardware at the end of each conversion of a channel when a new data result is
available in the ADC_DR register. It is cleared by software writing 1 to it or by reading the ADC_DR
register.
0: Channel conversion not complete (or the flag event was already acknowledged and cleared by
software)
1: Channel conversion complete
Bit 1 EOSMP: End of sampling flag
This bit is set by hardware during the conversion, at the end of the sampling phase.It is cleared by
software by programming it to ‘1’.
0: Not at the end of the sampling phase (or the flag event was already acknowledged and cleared by
software)
1: End of sampling phase reached
Bit 0 ADRDY: ADC ready
This bit is set by hardware after the ADC has been enabled (bit ADEN=1) and when the ADC reaches
a state where it is ready to accept conversion requests.
It is cleared by software writing 1 to it.
0: ADC not yet ready to start conversion (or the flag event was already acknowledged and cleared
by software)
1: ADC is ready to start conversion

Note:

In auto-off mode (AUTOFF=1) the power-on/off phases are performed automatically, by
hardware and the ADRDY flag is not set.

12.11.2

ADC interrupt enable register (ADC_IER)
Address offset: 0x04
Reset value: 0x0000 0000

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Res.

AWD
IE

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

rw

Res.

EOSEQ
EOSMP ADRDY
OVRIE
EOCIE
IE
IE
IE
rw

rw

rw

rw

rw

Bits 31:8 Reserved, must be kept at reset value.
Bit 7 AWDIE: Analog watchdog interrupt enable
This bit is set and cleared by software to enable/disable the analog watchdog interrupt.
0: Analog watchdog interrupt disabled
1: Analog watchdog interrupt enabled
Note: Software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion
is ongoing).
Bit 6:5 Reserved, must be kept at reset value.

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Bit 4 OVRIE: Overrun interrupt enable
This bit is set and cleared by software to enable/disable the overrun interrupt.
0: Overrun interrupt disabled
1: Overrun interrupt enabled. An interrupt is generated when the OVR bit is set.
Note: Software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion
is ongoing).
Bit 3 EOSEQIE: End of conversion sequence interrupt enable
This bit is set and cleared by software to enable/disable the end of sequence of conversions interrupt.
0: EOSEQ interrupt disabled
1: EOSEQ interrupt enabled. An interrupt is generated when the EOSEQ bit is set.
Note: Software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion
is ongoing).
Bit 2 EOCIE: End of conversion interrupt enable
This bit is set and cleared by software to enable/disable the end of conversion interrupt.
0: EOC interrupt disabled
1: EOC interrupt enabled. An interrupt is generated when the EOC bit is set.
Note: Software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion
is ongoing).
Bit 1 EOSMPIE: End of sampling flag interrupt enable
This bit is set and cleared by software to enable/disable the end of the sampling phase interrupt.
0: EOSMP interrupt disabled.
1: EOSMP interrupt enabled. An interrupt is generated when the EOSMP bit is set.
Note: Software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion
is ongoing).
Bits 0 ADRDYIE: ADC ready interrupt enable
This bit is set and cleared by software to enable/disable the ADC Ready interrupt.
0: ADRDY interrupt disabled.
1: ADRDY interrupt enabled. An interrupt is generated when the ADRDY bit is set.
Note: Software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion
is ongoing).

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12.11.3

RM0360

ADC control register (ADC_CR)
Address offset: 0x08
Reset value: 0x0000 0000

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

AD
CAL

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Res.

ADSTA
RT

ADDIS

ADEN

rs

rs

rs

rs
15
Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

ADSTP
rs

Bit 31 ADCAL: ADC calibration
This bit is set by software to start the calibration of the ADC.
It is cleared by hardware after calibration is complete.
0: Calibration complete
1: Write 1 to calibrate the ADC. Read at 1 means that a calibration is in progress.
Note: Software is allowed to set ADCAL only when the ADC is disabled (ADCAL=0, ADSTART=0,
ADSTP=0, ADDIS=0 and ADEN=0).
Bits 30:5

Reserved, must be kept at reset value.

Bit 4 ADSTP: ADC stop conversion command
This bit is set by software to stop and discard an ongoing conversion (ADSTP Command).
It is cleared by hardware when the conversion is effectively discarded and the ADC is ready to accept
a new start conversion command.
0: No ADC stop conversion command ongoing
1: Write 1 to stop the ADC. Read 1 means that an ADSTP command is in progress.
Note: Setting ADSTP to ‘1’ is only effective when ADSTART=1 and ADDIS=0 (ADC is enabled and
may be converting and there is no pending request to disable the ADC)
Bit 3

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Analog-to-digital converter (ADC)

Bit 2 ADSTART: ADC start conversion command
This bit is set by software to start ADC conversion. Depending on the EXTEN [1:0] configuration bits, a
conversion either starts immediately (software trigger configuration) or once a hardware trigger event
occurs (hardware trigger configuration).
It is cleared by hardware:
– In single conversion mode (CONT=0, DISCEN=0), when software trigger is selected (EXTEN=00):
at the assertion of the end of Conversion Sequence (EOSEQ) flag.
– In discontinuous conversion mode(CONT=0, DISCEN=1), when the software trigger is selected
(EXTEN=00): at the assertion of the end of Conversion (EOC) flag.
– In all other cases: after the execution of the ADSTP command, at the same time as the ADSTP bit is
cleared by hardware.
0: No ADC conversion is ongoing.
1: Write 1 to start the ADC. Read 1 means that the ADC is operating and may be converting.
Note: Software is allowed to set ADSTART only when ADEN=1 and ADDIS=0 (ADC is enabled and
there is no pending request to disable the ADC)
Bit 1 ADDIS: ADC disable command
This bit is set by software to disable the ADC (ADDIS command) and put it into power-down state
(OFF state).
It is cleared by hardware once the ADC is effectively disabled (ADEN is also cleared by hardware at
this time).
0: No ADDIS command ongoing
1: Write 1 to disable the ADC. Read 1 means that an ADDIS command is in progress.
Note: Setting ADDIS to ‘1’ is only effective when ADEN=1 and ADSTART=0 (which ensures that no
conversion is ongoing)
Bit 0 ADEN: ADC enable command
This bit is set by software to enable the ADC. The ADC will be effectively ready to operate once the
ADRDY flag has been set.
It is cleared by hardware when the ADC is disabled, after the execution of the ADDIS command.
0: ADC is disabled (OFF state)
1: Write 1 to enable the ADC.
Note: Software is allowed to set ADEN only when all bits of ADC_CR registers are 0 (ADCAL=0,
ADSTP=0, ADSTART=0, ADDIS=0 and ADEN=0)

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12.11.4

RM0360

ADC configuration register 1 (ADC_CFGR1)
Address offset: 0x0C
Reset value: 0x0000 0000

31

30

29

Res.

15

28

26

AWDCH[4:0]
rw

rw

rw

rw

rw

14

13

12

11

10

AUTOFF WAIT CONT OVRMOD
rw

27

rw

rw

rw

EXTEN[1:0]

25

24

Res.

Res.

9

8

Res.

23

22

AWDEN AWDSGL
rw

rw

7

6

21

20

19

18

17

16

Res.

Res.

Res.

Res.

Res.

DISCEN

5

4

3

2

1

rw

EXTSEL[2:0]

ALIGN

RES[1:0]

rw

rw

rw

rw

SCAND DMAC
IR
FG
rw

rw

0
DMAEN
rw

Bit 31 Reserved, must be kept at reset value.
Bits 30:26 AWDCH[4:0]: Analog watchdog channel selection
These bits are set and cleared by software. They select the input channel to be guarded by the
analog watchdog.
00000: ADC analog input Channel 0 monitored by AWD
00001: ADC analog input Channel 1 monitored by AWD
.....
10010: ADC analog input Channel 18 monitored by AWD
other values: Reserved, must not be used
Note: The channel selected by the AWDCH[4:0] bits must be also set into the CHSELR
register
Note: Software is allowed to write these bits only when ADSTART=0 (which ensures that no
conversion is ongoing).
Bits 25:24

Reserved, must be kept at reset value.

Bit 23 AWDEN: Analog watchdog enable
This bit is set and cleared by software.
0: Analog watchdog disabled
1: Analog watchdog enabled
Note: Software is allowed to write this bit only when ADSTART=0 (which ensures that no
conversion is ongoing).
Bit 22 AWDSGL: Enable the watchdog on a single channel or on all channels
This bit is set and cleared by software to enable the analog watchdog on the channel identified
by the AWDCH[4:0] bits or on all the channels
0: Analog watchdog enabled on all channels
1: Analog watchdog enabled on a single channel
Note: Software is allowed to write this bit only when ADSTART=0 (which ensures that no
conversion is ongoing).
Bits 21:17 Reserved, must be kept at reset value.

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Analog-to-digital converter (ADC)

Bit 16 DISCEN: Discontinuous mode
This bit is set and cleared by software to enable/disable discontinuous mode.
0: Discontinuous mode disabled
1: Discontinuous mode enabled
Note: It is not possible to have both discontinuous mode and continuous mode enabled: it is
forbidden to set both bits DISCEN=1 and CONT=1.
Note: Software is allowed to write this bit only when ADSTART=0 (which ensures that no
conversion is ongoing).
Bit 15 AUTOFF: Auto-off mode
This bit is set and cleared by software to enable/disable auto-off mode..
0: Auto-off mode disabled
1: Auto-off mode enabled
Note: Software is allowed to write this bit only when ADSTART=0 (which ensures that no
conversion is ongoing).
Bit 14 WAIT: Wait conversion mode
This bit is set and cleared by software to enable/disable wait conversion mode..
0: Wait conversion mode off
1: Wait conversion mode on
Note: Software is allowed to write this bit only when ADSTART=0 (which ensures that no
conversion is ongoing).
Bit 13 CONT: Single / continuous conversion mode
This bit is set and cleared by software. If it is set, conversion takes place continuously until it is
cleared.
0: Single conversion mode
1: Continuous conversion mode
Note: It is not possible to have both discontinuous mode and continuous mode enabled: it is
forbidden to set both bits DISCEN=1 and CONT=1.
Note: Software is allowed to write this bit only when ADSTART=0 (which ensures that no
conversion is ongoing).
Bit 12 OVRMOD: Overrun management mode
This bit is set and cleared by software and configure the way data overruns are managed.
0: ADC_DR register is preserved with the old data when an overrun is detected.
1: ADC_DR register is overwritten with the last conversion result when an overrun is
detected.
Note: Software is allowed to write this bit only when ADSTART=0 (which ensures that no
conversion is ongoing).
Bits 11:10 EXTEN[1:0]: External trigger enable and polarity selection
These bits are set and cleared by software to select the external trigger polarity and enable the
trigger.
00: Hardware trigger detection disabled (conversions can be started by software)
01: Hardware trigger detection on the rising edge
10: Hardware trigger detection on the falling edge
11: Hardware trigger detection on both the rising and falling edges
Note: Software is allowed to write these bits only when ADSTART=0 (which ensures that no
conversion is ongoing).
Bit 9 Reserved, must be kept at reset value.

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RM0360

Bits 8:6 EXTSEL[2:0]: External trigger selection
These bits select the external event used to trigger the start of conversion (refer to Table 38:
External triggers for details):
000: TRG0
001: TRG1
010: TRG2
011: TRG3
100: TRG4
101: TRG5
110: TRG6
111: TRG7
Note: Software is allowed to write these bits only when ADSTART=0 (which ensures that no
conversion is ongoing).
Bit 5 ALIGN: Data alignment
This bit is set and cleared by software to select right or left alignment. Refer to Figure 34: Data
alignment and resolution on page 198
0: Right alignment
1: Left alignment
Note: Software is allowed to write this bit only when ADSTART=0 (which ensures that no
conversion is ongoing).
Bit 4:3 RES[1:0]: Data resolution
These bits are written by software to select the resolution of the conversion.
00: 12 bits
01: 10 bits
10: 8 bits
11: 6 bits
Note: Software is allowed to write these bits only when ADEN=0.

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Analog-to-digital converter (ADC)

Bit 2 SCANDIR: Scan sequence direction
This bit is set and cleared by software to select the direction in which the channels will be
scanned in the sequence.
0: Upward scan (from CHSEL0 to CHSEL17)
1: Backward scan (from CHSEL17 to CHSEL0)
Note: Software is allowed to write this bit only when ADSTART=0 (which ensures that no
conversion is ongoing).
Bit 1 DMACFG: Direct memory access configuration
This bit is set and cleared by software to select between two DMA modes of operation and is
effective only when DMAEN=1.
0: DMA one shot mode selected
1: DMA circular mode selected
For more details, refer to Section 12.6.5: Managing converted data using the DMA on
page 199
Note: Software is allowed to write this bit only when ADSTART=0 (which ensures that no
conversion is ongoing).
Bit 0 DMAEN: Direct memory access enable
This bit is set and cleared by software to enable the generation of DMA requests. This allows to
use the DMA controller to manage automatically the converted data. For more details, refer to
Section 12.6.5: Managing converted data using the DMA on page 199.
0: DMA disabled
1: DMA enabled
Note: Software is allowed to write this bit only when ADSTART=0 (which ensures that no
conversion is ongoing).

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12.11.5

RM0360

ADC configuration register 2 (ADC_CFGR2)
Address offset: 0x10
Reset value: 0x0000 0000

31

30

CKMODE[1:0]

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

rw

rw

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Bits 31:30 CKMODE[1:0]: ADC clock mode
These bits are set and cleared by software to define how the analog ADC is clocked:
00: ADCCLK (Asynchronous clock mode), generated at product level (refer to RCC section)
01: PCLK/2 (Synchronous clock mode)
10: PCLK/4 (Synchronous clock mode)
11: Reserved
In all synchronous clock modes, there is no jitter in the delay from a timer trigger to the start of a
conversion.
Note: Software is allowed to write these bits only when the ADC is disabled (ADCAL=0, ADSTART=0,
ADSTP=0, ADDIS=0 and ADEN=0).
Bits 29:0

12.11.6

Reserved, must be kept at reset value.

ADC sampling time register (ADC_SMPR)
Address offset: 0x14
Reset value: 0x0000 0000

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

SMP[2:0]
rw

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RM0360

Analog-to-digital converter (ADC)

Bits 31:3 Reserved, must be kept at reset value.
Bits 2:0 SMP[2:0]: Sampling time selection
These bits are written by software to select the sampling time that applies to all channels.
000: 1.5 ADC clock cycles
001: 7.5 ADC clock cycles
010: 13.5 ADC clock cycles
011: 28.5 ADC clock cycles
100: 41.5 ADC clock cycles
101: 55.5 ADC clock cycles
110: 71.5 ADC clock cycles
111: 239.5 ADC clock cycles
Note: Software is allowed to write these bits only when ADSTART=0 (which ensures that no
conversion is ongoing).

12.11.7

ADC watchdog threshold register (ADC_TR)
Address offset: 0x20
Reset value: 0x0FFF 0000

31

30

29

28

Res.

Res.

Res.

Res.

15

14

13

12

Res.

Res.

Res.

Res.

27

25

24

23

22

21

20

19

18

17

16

HT[11:0]
rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

11

10

9

8

7

6

5

4

3

2

1

0

rw

rw

rw

rw

rw

rw

LT[11:0]
rw

Bits 31:28

26

rw

rw

rw

rw

rw

Reserved, must be kept at reset value.

Bit 27:16 HT[11:0]: Analog watchdog higher threshold
These bits are written by software to define the higher threshold for the analog watchdog. Refer to
Section 12.8: Analog window watchdog (AWDEN, AWDSGL, AWDCH, AWD_HTR/LTR, AWD) on
page 203
Note: Software is allowed to write these bits only when ADSTART=0 (which ensures that no
conversion is ongoing).
Bits 15:12

Reserved, must be kept at reset value.

Bit 11:0 LT[11:0]: Analog watchdog lower threshold
These bits are written by software to define the lower threshold for the analog watchdog.
Refer to Section 12.8: Analog window watchdog (AWDEN, AWDSGL, AWDCH, AWD_HTR/LTR,
AWD) on page 203
Note: Software is allowed to write these bits only when ADSTART=0 (which ensures that no
conversion is ongoing).

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Analog-to-digital converter (ADC)

12.11.8

RM0360

ADC channel selection register (ADC_CHSELR)
Address offset: 0x28
Reset value: 0x0000 0000

31

30

29

28

27

26

25

24

23

22

21

20

19

18

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

15

14

13

12

11

10

9

8

7

6

5

4

3

2

17

16

CHSEL CHSEL
17
16
rw

rw

1

0

CHSEL CHSEL CHSEL CHSEL CHSEL CHSEL CHSEL CHSEL CHSEL CHSEL CHSEL CHSEL CHSEL CHSEL CHSEL CHSEL
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

Bits 31:18 Reserved, must be kept at reset value.
Bits 17:0 CHSELx: Channel-x selection
These bits are written by software and define which channels are part of the sequence of channels to
be converted.
0: Input Channel-x is not selected for conversion
1: Input Channel-x is selected for conversion
Note: Software is allowed to write these bits only when ADSTART=0 (which ensures that no
conversion is ongoing).

12.11.9

ADC data register (ADC_DR)
Address offset: 0x40
Reset value: 0x0000 0000

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

r

r

r

r

r

r

r

DATA[15:0]
r

r

r

r

r

r

r

r

r

Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 DATA[15:0]: Converted data
These bits are read-only. They contain the conversion result from the last converted channel. The data
are left- or right-aligned as shown in Figure 34: Data alignment and resolution on page 198.
Just after a calibration is complete, DATA[6:0] contains the calibration factor.

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Analog-to-digital converter (ADC)

12.11.10 ADC common configuration register (ADC_CCR)
Address offset: 0x308
Reset value: 0x0000 0000
31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

TS
EN

VREF
EN

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

rw

rw

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Bits 31:24 Reserved, must be kept at reset value.
Bit 23 TSEN: Temperature sensor enable
This bit is set and cleared by software to enable/disable the temperature sensor.
0: Temperature sensor disabled
1: Temperature sensor enabled
Note: Software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion
is ongoing).
Bit 22 VREFEN: VREFINT enable
This bit is set and cleared by software to enable/disable the VREFINT.
0: VREFINT disabled
1: VREFINT enabled
Note: Software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion
is ongoing).
Bits 21:0 Reserved, must be kept at reset value.

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ADC_CCR

0

0

DocID025023 Rev 4

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Reset value

Res.

1
1
1
1

Res.
Res.
Res.
CHSEL17
CHSEL16
CHSEL15
CHSEL14
CHSEL13

0
0
0
0
0
0
0
0
0
0

0
0
0
0
0
0

Refer to Section 2.2.2 on page 37 for the register boundary addresses.
CHSEL0

0

CHSEL1

0

CHSEL2

0

CHSEL7

Res.
Res.
Res.
Res.
Res.

Res.

SCANDIR
DMACFG
DMAEN

0
0
0
0
0
0
0
0

Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

ALIGN

0

Res.

ADRDYIE

0
0

0
RES
[1:0]

ADEN

EOSMPIE

0
ADDIS

EOCIE

0
ADSTART

EOSEQIE

Res.

Res.

AWDIE

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

0
Res.

0

OVRIE

ADSTP

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

EOSEQ
EOC
EOSMP
ADRDY

Res.

Res.

AWD

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

OVR

0

Res.

Res.

Res.

EXTSEL
[2:0]

Res.

Res.

Res.

0

Res.

0

CHSEL3

0

CHSEL8

OVRMOD
0

Res.

CONT
0

Res.

WAIT
0

EXTEN[1:0]

AUTOFF

0

CHSEL4

0

CHSEL9

Res.

DISCEN

Res.

Res.

Res.

Res.

0

Res.

Res.

Res.

Res.

Res.

Res.

AWDSGL

Res.
Res.

AWDEN

Res.

Res.

Res.

Res.

Res.

Reset value

CHSEL5

0

CHSEL10

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Reset value

CHSEL6

0

CHSEL11

1
Reserved

CHSEL12

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Reserved
Reserved

Res.

Res.

Res.

HT[11:0]

Res.

Reserved

Res.

Res.

Res.

Res.

Res.

1

Res.

Reset value
Reserved
Reserved

Res.

Res.

Res.

Res.

Res.

1

Res.

Res.

Res.

0

Res.

Res.

1

Res.

Res.

Res.

Res.

Res.

Res.

ADCAL

Res.

0

Res.

VREFEN

Res.

1

Res.

Res.

0

Res.

1

Res.

Res.

Res.

Res.

Res.

0

Res.

1

Res.

Res.

Res.
0

Res.

Res.

Reset value
1

Res.

Res.

Res.

CKMODE[1:0]
0

TSEN

Reset value
AWDCH[4:0]

Res.

ADC_DR

Res.

ADC_CHSELR

Res.

0x40
Reset value
Reserved

Res.

0x2C
0x30
0x34
0x38
0x3C
ADC_TR
0

Res.

Reset value
0

Res.

0x28
ADC_SMPR
Res.

Reset value

Res.

0x24
ADC_CFGR1

Res.

0x20
0

Res.

0x18
0x1C
Reset value

Res.

0x14
ADC_CFGR2

Res.

0x10
ADC_CR

Res.

0x0C

Res.

0x08
ADC_IER

Res.

0x04
ADC_ISR

Res.

0x00

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0

Register

Res.

Offset

Res.

Analog-to-digital converter (ADC)
RM0360

12.11.11 ADC register map
The following table summarizes the ADC registers.
Table 43. ADC register map and reset values

0
0
0
0
0

0
0
0

0

SMP
[2:0]
0 0 0

LT[11:0]

0
0
0
0
0
0
0

Reserved

DATA[15:0]

RM0360

Advanced-control timers (TIM1)

13

Advanced-control timers (TIM1)

13.1

TIM1 introduction
The advanced-control timers (TIM1) consist of a 16-bit auto-reload counter driven by a
programmable prescaler.
It may be used for a variety of purposes, including measuring the pulse lengths of input
signals (input capture) or generating output waveforms (output compare, PWM,
complementary PWM with dead-time insertion).
Pulse lengths and waveform periods can be modulated from a few microseconds to several
milliseconds using the timer prescaler and the RCC clock controller prescalers.
The advanced-control (TIM1) and general-purpose (TIMx) timers are completely
independent, and do not share any resources. They can be synchronized together as
described in Section 13.3.20.

13.2

TIM1 main features
TIM1 timer features include:


16-bit up, down, up/down auto-reload counter.



16-bit programmable prescaler allowing dividing (also “on the fly”) the counter clock
frequency either by any factor between 1 and 65535.



Up to 4 independent channels for:
–

Input Capture

–

Output Compare

–

PWM generation (Edge- and Center-aligned modes)

–

One-pulse mode output



Complementary outputs with programmable dead-time



Synchronization circuit to control the timer with external signals and to interconnect
several timers together.



Repetition counter to update the timer registers only after a given number of cycles of
the counter.



Break input to put the timer’s output signals in reset state or in a known state.



Interrupt/DMA generation on the following events:
–

Update: counter overflow/underflow, counter initialization (by software or
internal/external trigger)

–

Trigger event (counter start, stop, initialization or count by internal/external trigger)

–

Input capture

–

Output compare

–

Break input



Supports incremental (quadrature) encoder and hall-sensor circuitry for positioning
purposes



Trigger input for external clock or cycle-by-cycle current management

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RM0360

Figure 40. Advanced-control timer block diagram
Internal Clock (CK_INT)

CK_TIM18 from RCC

ETRF

Trigger
Controller

ETRP
ETR

TIMx_ETR

Polarity Selection & Edge
Detector & Prescaler

TRGO

Input Filter

ITR0

to other timers
to ADC

TGI

ITR

ITR1

ITR2

TRC

TRGI

ITR3

Slave
Mode
Controller

Reset, Enable, Up/Down, Count

TI1F_ED

TI1FP1

Encoder
Interface

TI2FP2

REP Register
U

UI

AutoReload Register
Repetition
counter

Stop, Clear or Up/Down

CK_PSC

CK_CNT

PSC

Prescaler

XOR

TI1

Input Filter &
Edge detector

TI2

Input Filter &
Edge detector

TI2FP1
TI2FP2

COUNTER
CC1I

CC1I

IC1
Prescaler

IC1PS U

TRC

TIMx_CH1

TIMx_CH2

TI1FP1
TI1FP2

+/-

Capture/Compare 1 Register

Prescaler

IC2PS U

DTG registers

OC1REF

TIMx_CH1
DTG

Capture/Compare 2 Register

OC2REF

Input Filter &
Edge detector

TI3FP3
TI3FP4

IC3

Prescaler

IC3PS

TRC

TIMx_CH4

TI4

Input Filter &
Edge detector

TI4FP3
TI4FP4

Capture/Compare 3 Register

IC4
Prescaler

IC4PS

Polarity Selection

U
Capture/Compare 4 Register

BI

Clock failure event from clock controller
CSS (Clock Security system

Notes:
Reg

Preload registers transferred
to active registers on U event
according to control bit
event
interrupt & DMA output

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OC3REF

DocID025023 Rev 4

OC4REF

TIMx_CH2N
TIMx_CH3

DTG

output OC3
control

CC4I

ETRF

BRK

control

OC3N

CC4I

TRC

TIMx_BKIN

output OC2

CC3I

U

TIMx_CH1N
TIMx_CH2

DTG

OC2N
CC3I

TI3

control

CC2I

TRC

TIMx_CH3

output OC1
OC1N

CC2I

IC2

U

CNT

TIMx_CH3N

TIMx_CH4
output

control OC4

RM0360

Advanced-control timers (TIM1)

13.3

TIM1 functional description

13.3.1

Time-base unit
The main block of the programmable advanced-control timer is a 16-bit counter with its
related auto-reload register. The counter can count up, down or both up and down. The
counter clock can be divided by a prescaler.
The counter, the auto-reload register and the prescaler register can be written or read by
software. This is true even when the counter is running.
The time-base unit includes:


Counter register (TIMx_CNT)



Prescaler register (TIMx_PSC)



Auto-reload register (TIMx_ARR)



Repetition counter register (TIMx_RCR)

The auto-reload register is preloaded. Writing to or reading from the auto-reload register
accesses the preload register. The content of the preload register are transferred into the
shadow register permanently or at each update event (UEV), depending on the auto-reload
preload enable bit (ARPE) in TIMx_CR1 register. The update event is sent when the counter
reaches the overflow (or underflow when downcounting) and if the UDIS bit equals 0 in the
TIMx_CR1 register. It can also be generated by software. The generation of the update
event is described in detailed for each configuration.
The counter is clocked by the prescaler output CK_CNT, which is enabled only when the
counter enable bit (CEN) in TIMx_CR1 register is set (refer also to the slave mode controller
description to get more details on counter enabling).
Note that the counter starts counting 1 clock cycle after setting the CEN bit in the TIMx_CR1
register.

Prescaler description
The prescaler can divide the counter clock frequency by any factor between 1 and 65536. It
is based on a 16-bit counter controlled through a 16-bit register (in the TIMx_PSC register).
It can be changed on the fly as this control register is buffered. The new prescaler ratio is
taken into account at the next update event.
Figure 42 and Figure 43 give some examples of the counter behavior when the prescaler
ratio is changed on the fly:

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Figure 41. Counter timing diagram with prescaler division change from 1 to 2

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Figure 42. Counter timing diagram with prescaler division change from 1 to 4

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RM0360

13.3.2

Advanced-control timers (TIM1)

Counter modes
Upcounting mode
In upcounting mode, the counter counts from 0 to the auto-reload value (content of the
TIMx_ARR register), then restarts from 0 and generates a counter overflow event.
If the repetition counter is used, the update event (UEV) is generated after upcounting is
repeated for the number of times programmed in the repetition counter register
(TIMx_RCR). Else the update event is generated at each counter overflow.
Setting the UG bit in the TIMx_EGR register (by software or by using the slave mode
controller) also generates an update event.
The UEV event can be disabled by software by setting the UDIS bit in the TIMx_CR1
register. This is to avoid updating the shadow registers while writing new values in the
preload registers. Then no update event occurs until the UDIS bit has been written to 0.
However, the counter restarts from 0, as well as the counter of the prescaler (but the
prescale rate does not change). In addition, if the URS bit (update request selection) in
TIMx_CR1 register is set, setting the UG bit generates an update event UEV but without
setting the UIF flag (thus no interrupt or DMA request is sent). This is to avoid generating
both update and capture interrupts when clearing the counter on the capture event.
When an update event occurs, all the registers are updated and the update flag (UIF bit in
TIMx_SR register) is set (depending on the URS bit):


The repetition counter is reloaded with the content of TIMx_RCR register,



The auto-reload shadow register is updated with the preload value (TIMx_ARR),



The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC
register).

The following figures show some examples of the counter behavior for different clock
frequencies when TIMx_ARR=0x36.

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Figure 43. Counter timing diagram, internal clock divided by 1

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Figure 44. Counter timing diagram, internal clock divided by 2

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Advanced-control timers (TIM1)
Figure 45. Counter timing diagram, internal clock divided by 4

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Figure 46. Counter timing diagram, internal clock divided by N

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Figure 47. Counter timing diagram, update event when ARPE=0
(TIMx_ARR not preloaded)
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Figure 48. Counter timing diagram, update event when ARPE=1
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RM0360

Advanced-control timers (TIM1)

Downcounting mode
In downcounting mode, the counter counts from the auto-reload value (content of the
TIMx_ARR register) down to 0, then restarts from the auto-reload value and generates a
counter underflow event.
If the repetition counter is used, the update event (UEV) is generated after downcounting is
repeated for the number of times programmed in the repetition counter register
(TIMx_RCR). Else the update event is generated at each counter underflow.
Setting the UG bit in the TIMx_EGR register (by software or by using the slave mode
controller) also generates an update event.
The UEV update event can be disabled by software by setting the UDIS bit in TIMx_CR1
register. This is to avoid updating the shadow registers while writing new values in the
preload registers. Then no update event occurs until UDIS bit has been written to 0.
However, the counter restarts from the current auto-reload value, whereas the counter of the
prescaler restarts from 0 (but the prescale rate doesn’t change).
In addition, if the URS bit (update request selection) in TIMx_CR1 register is set, setting the
UG bit generates an update event UEV but without setting the UIF flag (thus no interrupt or
DMA request is sent). This is to avoid generating both update and capture interrupts when
clearing the counter on the capture event.
When an update event occurs, all the registers are updated and the update flag (UIF bit in
TIMx_SR register) is set (depending on the URS bit):


The repetition counter is reloaded with the content of TIMx_RCR register



The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC
register)



The auto-reload active register is updated with the preload value (content of the
TIMx_ARR register). Note that the auto-reload is updated before the counter is
reloaded, so that the next period is the expected one

The following figures show some examples of the counter behavior for different clock
frequencies when TIMx_ARR=0x36.
Figure 49. Counter timing diagram, internal clock divided by 1
CK_PSC
CNT_EN
Timer clock = CK_CNT
Counter register

05

04 03 02 01 00 36 35 34 33 32 31 30 2F

Counter underflow (cnt_udf)
Update event (UEV)
Update interrupt flag (UIF)

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Advanced-control timers (TIM1)

RM0360

Figure 50. Counter timing diagram, internal clock divided by 2
CK_PSC
CNT_EN
Timer clock = CK_CNT
Counter register

0002

0001 0000

0036

0035

0034

0033

Counter underflow
Update event (UEV)
Update interrupt flag (UIF)

Figure 51. Counter timing diagram, internal clock divided by 4
CK_PSC
CNT_EN
Timer clock = CK_CNT
Counter register

0001

0000

0036

0035

Counter underflow
Update event (UEV)
Update interrupt flag (UIF)

Figure 52. Counter timing diagram, internal clock divided by N
CK_PSC
Timer clock = CK_CNT
Counter register

20

Counter underflow
Update event (UEV)
Update interrupt flag (UIF)

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00

36

RM0360

Advanced-control timers (TIM1)
Figure 53. Counter timing diagram, update event when repetition counter is not used
CK_PSC
CEN
Timer clock = CK_CNT
Counter register

05

04 03 02 01 00 36 35 34 33 32 31 30 2F

Counter underflow
Update event (UEV)
Update interrupt flag (UIF)
Auto-reload register

FF

36

Write a new value in TIMx_ARR

Center-aligned mode (up/down counting)
In center-aligned mode, the counter counts from 0 to the auto-reload value (content of the
TIMx_ARR register) – 1, generates a counter overflow event, then counts from the autoreload value down to 1 and generates a counter underflow event. Then it restarts counting
from 0.
Center-aligned mode is active when the CMS bits in TIMx_CR1 register are not equal to
'00'. The Output compare interrupt flag of channels configured in output is set when: the
counter counts down (Center aligned mode 1, CMS = “01”), the counter counts up (Center
aligned mode 2, CMS = “10”) the counter counts up and down (Center aligned mode 3,
CMS = “11”).
In this mode, the DIR direction bit in the TIMx_CR1 register cannot be written. It is updated
by hardware and gives the current direction of the counter.
The update event can be generated at each counter overflow and at each counter underflow
or by setting the UG bit in the TIMx_EGR register (by software or by using the slave mode
controller) also generates an update event. In this case, the counter restarts counting from
0, as well as the counter of the prescaler.
The UEV update event can be disabled by software by setting the UDIS bit in the TIMx_CR1
register. This is to avoid updating the shadow registers while writing new values in the
preload registers. Then no update event occurs until UDIS bit has been written to 0.
However, the counter continues counting up and down, based on the current auto-reload
value.
In addition, if the URS bit (update request selection) in TIMx_CR1 register is set, setting the
UG bit generates an UEV update event but without setting the UIF flag (thus no interrupt or
DMA request is sent). This is to avoid generating both update and capture interrupts when
clearing the counter on the capture event.

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Advanced-control timers (TIM1)

RM0360

When an update event occurs, all the registers are updated and the update flag (UIF bit in
TIMx_SR register) is set (depending on the URS bit):


The repetition counter is reloaded with the content of TIMx_RCR register



The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC
register)



The auto-reload active register is updated with the preload value (content of the
TIMx_ARR register). Note that if the update source is a counter overflow, the autoreload is updated before the counter is reloaded, so that the next period is the expected
one (the counter is loaded with the new value).

The following figures show some examples of the counter behavior for different clock
frequencies.
Figure 54. Counter timing diagram, internal clock divided by 1, TIMx_ARR = 0x6
CK_PSC
CNT_EN
Timer clock = CK_CNT
Counter register

04

03 02 01 00 01 02 03 04 05 06 05 04 03

Counter underflow
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)

1. Here, center-aligned mode 1 is used (for more details refer to Section 13.4: TIM1 registers on page 268).

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Advanced-control timers (TIM1)
Figure 55. Counter timing diagram, internal clock divided by 2

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Figure 56. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36

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1. Center-aligned mode 2 or 3 is used with an UIF on overflow.

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Figure 57. Counter timing diagram, internal clock divided by N

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Figure 58. Counter timing diagram, update event with ARPE=1 (counter underflow)
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Advanced-control timers (TIM1)
Figure 59. Counter timing diagram, Update event with ARPE=1 (counter overflow)
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13.3.3

Repetition counter
Section 13.3.1: Time-base unit describes how the update event (UEV) is generated with
respect to the counter overflows/underflows. It is actually generated only when the repetition
counter has reached zero. This can be useful when generating PWM signals.
This means that data are transferred from the preload registers to the shadow registers
(TIMx_ARR auto-reload register, TIMx_PSC prescaler register, but also TIMx_CCRx
capture/compare registers in compare mode) every N counter overflows or underflows,
where N is the value in the TIMx_RCR repetition counter register.
The repetition counter is decremented:


At each counter overflow in upcounting mode,



At each counter underflow in downcounting mode,



At each counter overflow and at each counter underflow in center-aligned mode.
Although this limits the maximum number of repetition to 128 PWM cycles, it makes it
possible to update the duty cycle twice per PWM period. When refreshing compare
registers only once per PWM period in center-aligned mode, maximum resolution is
2xTck, due to the symmetry of the pattern.

The repetition counter is an auto-reload type; the repetition rate is maintained as defined by
the TIMx_RCR register value (refer to Figure 60). When the update event is generated by
software (by setting the UG bit in TIMx_EGR register) or by hardware through the slave
mode controller, it occurs immediately whatever the value of the repetition counter is and the
repetition counter is reloaded with the content of the TIMx_RCR register.

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Advanced-control timers (TIM1)

RM0360

In center-aligned mode, for odd values of RCR, the update event occurs either on the
overflow or on the underflow depending on when the RCR register was written and when
the counter was started. If the RCR was written before starting the counter, the UEV occurs
on the overflow. If the RCR was written after starting the counter, the UEV occurs on the
underflow. For example for RCR = 3, the UEV is generated on each 4th overflow or
underflow event depending on when RCR was written.
Figure 60. Update rate examples depending on mode and TIMx_RCR register settings

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13.3.4

Advanced-control timers (TIM1)

Clock sources
The counter clock can be provided by the following clock sources:


Internal clock (CK_INT)



External clock mode1: external input pin



External clock mode2: external trigger input ETR



Internal trigger inputs (ITRx): using one timer as prescaler for another timer, for
example, you can configure Timer 1 to act as a prescaler for Timer 2. Refer to Using
one timer as prescaler for another on page 332 for more details.

Internal clock source (CK_INT)
If the slave mode controller is disabled (SMS=000), then the CEN, DIR (in the TIMx_CR1
register) and UG bits (in the TIMx_EGR register) are actual control bits and can be changed
only by software (except UG which remains cleared automatically). As soon as the CEN bit
is written to 1, the prescaler is clocked by the internal clock CK_INT.
Figure 61 shows the behavior of the control circuit and the upcounter in normal mode,
without prescaler.
Figure 61. Control circuit in normal mode, internal clock divided by 1

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Advanced-control timers (TIM1)

RM0360

External clock source mode 1
This mode is selected when SMS=111 in the TIMx_SMCR register. The counter can count at
each rising or falling edge on a selected input.
Figure 62. TI2 external clock connection example
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For example, to configure the upcounter to count in response to a rising edge on the TI2
input, use the following procedure:

Note:

1.

Configure channel 2 to detect rising edges on the TI2 input by writing CC2S = ‘01’ in
the TIMx_CCMR1 register.

2.

Configure the input filter duration by writing the IC2F[3:0] bits in the TIMx_CCMR1
register (if no filter is needed, keep IC2F=0000).

3.

Select rising edge polarity by writing CC2P=0 in the TIMx_CCER register.

4.

Configure the timer in external clock mode 1 by writing SMS=111 in the TIMx_SMCR
register.

5.

Select TI2 as the trigger input source by writing TS=110 in the TIMx_SMCR register.

6.

Enable the counter by writing CEN=1 in the TIMx_CR1 register.

The capture prescaler is not used for triggering, so you don’t need to configure it.
For code examples refer to the Appendix section A.8.1: Upcounter on TI2 rising edge code
example.
When a rising edge occurs on TI2, the counter counts once and the TIF flag is set.
The delay between the rising edge on TI2 and the actual clock of the counter is due to the
resynchronization circuit on TI2 input.

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Advanced-control timers (TIM1)
Figure 63. Control circuit in external clock mode 1

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External clock source mode 2
This mode is selected by writing ECE=1 in the TIMx_SMCR register.
The counter can count at each rising or falling edge on the external trigger input ETR.
The Figure 64 gives an overview of the external trigger input block.
Figure 64. External trigger input block

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For example, to configure the upcounter to count each 2 rising edges on ETR, use the
following procedure:

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Advanced-control timers (TIM1)

RM0360

1.

As no filter is needed in this example, write ETF[3:0]=0000 in the TIMx_SMCR register.

2.

Set the prescaler by writing ETPS[1:0]=01 in the TIMx_SMCR register

3.

Select rising edge detection on the ETR pin by writing ETP=0 in the TIMx_SMCR
register

4.

Enable external clock mode 2 by writing ECE=1 in the TIMx_SMCR register.

5.

Enable the counter by writing CEN=1 in the TIMx_CR1 register.

The counter counts once each 2 ETR rising edges.
For code example refer to the Appendix section A.8.2: Up counter on each 2 ETR rising
edges code example.
The delay between the rising edge on ETR and the actual clock of the counter is due to the
resynchronization circuit on the ETRP signal.
Figure 65. Control circuit in external clock mode 2

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13.3.5

Capture/compare channels
Each Capture/Compare channel is built around a capture/compare register (including a
shadow register), a input stage for capture (with digital filter, multiplexing and prescaler) and
an output stage (with comparator and output control).
Figure 66 to Figure 69 give an overview of one Capture/Compare channel.
The input stage samples the corresponding TIx input to generate a filtered signal TIxF.
Then, an edge detector with polarity selection generates a signal (TIxFPx) which can be
used as trigger input by the slave mode controller or as the capture command. It is
prescaled before the capture register (ICxPS).

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Advanced-control timers (TIM1)
Figure 66. Capture/compare channel (example: channel 1 input stage)

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The output stage generates an intermediate waveform which is then used for reference:
OCxRef (active high). The polarity acts at the end of the chain.
Figure 67. Capture/compare channel 1 main circuit

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Figure 68. Output stage of capture/compare channel (channel 1 to 3)
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The capture/compare block is made of one preload register and one shadow register. Write
and read always access the preload register.
In capture mode, captures are actually done in the shadow register, which is copied into the
preload register.
In compare mode, the content of the preload register is copied into the shadow register
which is compared to the counter.

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13.3.6

Advanced-control timers (TIM1)

Input capture mode
In Input capture mode, the Capture/Compare Registers (TIMx_CCRx) are used to latch the
value of the counter after a transition detected by the corresponding ICx signal. When a
capture occurs, the corresponding CCXIF flag (TIMx_SR register) is set and an interrupt or
a DMA request can be sent if they are enabled. If a capture occurs while the CCxIF flag was
already high, then the over-capture flag CCxOF (TIMx_SR register) is set. CCxIF can be
cleared by software by writing it to ‘0’ or by reading the captured data stored in the
TIMx_CCRx register. CCxOF is cleared when you write it to ‘0’.
The following example shows how to capture the counter value in TIMx_CCR1 when TI1
input rises. To do this, use the following procedure:


Select the active input: TIMx_CCR1 must be linked to the TI1 input, so write the CC1S
bits to 01 in the TIMx_CCMR1 register. As soon as CC1S becomes different from 00,
the channel is configured in input and the TIMx_CCR1 register becomes read-only.



Program the input filter duration you need with respect to the signal you connect to the
timer (when the input is one of the TIx (ICxF bits in the TIMx_CCMRx register). Let’s
imagine that, when toggling, the input signal is not stable during at must 5 internal clock
cycles. We must program a filter duration longer than these 5 clock cycles. We can
validate a transition on TI1 when 8 consecutive samples with the new level have been
detected (sampled at fDTS frequency). Then write IC1F bits to 0011 in the
TIMx_CCMR1 register.



Select the edge of the active transition on the TI1 channel by writing CC1P and CC1NP
bits to 0 in the TIMx_CCER register (rising edge in this case).



Program the input prescaler. In our example, we wish the capture to be performed at
each valid transition, so the prescaler is disabled (write IC1PS bits to ‘00’ in the
TIMx_CCMR1 register).



Enable capture from the counter into the capture register by setting the CC1E bit in the
TIMx_CCER register.



If needed, enable the related interrupt request by setting the CC1IE bit in the
TIMx_DIER register, and/or the DMA request by setting the CC1DE bit in the
TIMx_DIER register.

For code example refer to the Appendix section A.8.3: Input capture configuration code
example.
When an input capture occurs:


The TIMx_CCR1 register gets the value of the counter on the active transition.



CC1IF flag is set (interrupt flag). CC1OF is also set if at least two consecutive captures
occurred whereas the flag was not cleared.



An interrupt is generated depending on the CC1IE bit.



A DMA request is generated depending on the CC1DE bit.

For code example refer to the Appendix section A.8.4: Input capture data management
code example.
In order to handle the overcapture, it is recommended to read the data before the
overcapture flag. This is to avoid missing an overcapture which could happen after reading
the flag and before reading the data.
Note:

IC interrupt and/or DMA requests can be generated by software by setting the
corresponding CCxG bit in the TIMx_EGR register.

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13.3.7

RM0360

PWM input mode
This mode is a particular case of input capture mode. The procedure is the same except:


Two ICx signals are mapped on the same TIx input.



These 2 ICx signals are active on edges with opposite polarity.



One of the two TIxFP signals is selected as trigger input and the slave mode controller
is configured in reset mode.

For example, you can measure the period (in TIMx_CCR1 register) and the duty cycle (in
TIMx_CCR2 register) of the PWM applied on TI1 using the following procedure (depending
on CK_INT frequency and prescaler value):


Select the active input for TIMx_CCR1: write the CC1S bits to 01 in the TIMx_CCMR1
register (TI1 selected).



Select the active polarity for TI1FP1 (used both for capture in TIMx_CCR1 and counter
clear): write the CC1P and CC1NP bits to ‘0’ (active on rising edge).



Select the active input for TIMx_CCR2: write the CC2S bits to 10 in the TIMx_CCMR1
register (TI1 selected).



Select the active polarity for TI1FP2 (used for capture in TIMx_CCR2): write the CC2P
bit to ‘1’ (active on falling edge).



Select the valid trigger input: write the TS bits to 101 in the TIMx_SMCR register
(TI1FP1 selected).



Configure the slave mode controller in reset mode: write the SMS bits to 100 in the
TIMx_SMCR register.



Enable the captures: write the CC1E and CC2E bits to ‘1’ in the TIMx_CCER register.

For code example refer to the Appendix section A.8.5: PWM input configuration code
example.
Figure 70. PWM input mode timing
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13.3.8

Advanced-control timers (TIM1)

Forced output mode
In output mode (CCxS bits = 00 in the TIMx_CCMRx register), each output compare signal
(OCxREF and then OCx/OCxN) can be forced to active or inactive level directly by software,
independently of any comparison between the output compare register and the counter.
To force an output compare signal (OCXREF/OCx) to its active level, you just need to write
101 in the OCxM bits in the corresponding TIMx_CCMRx register. Thus OCXREF is forced
high (OCxREF is always active high) and OCx get opposite value to CCxP polarity bit.
For example: CCxP=0 (OCx active high) => OCx is forced to high level.
The OCxREF signal can be forced low by writing the OCxM bits to 100 in the TIMx_CCMRx
register.
Anyway, the comparison between the TIMx_CCRx shadow register and the counter is still
performed and allows the flag to be set. Interrupt and DMA requests can be sent
accordingly. This is described in the output compare mode section below.

13.3.9

Output compare mode
This function is used to control an output waveform or indicating when a period of time has
elapsed.
When a match is found between the capture/compare register and the counter, the output
compare function:


Assigns the corresponding output pin to a programmable value defined by the output
compare mode (OCxM bits in the TIMx_CCMRx register) and the output polarity (CCxP
bit in the TIMx_CCER register). The output pin can keep its level (OCXM=000), be set
active (OCxM=001), be set inactive (OCxM=010) or can toggle (OCxM=011) on match.



Sets a flag in the interrupt status register (CCxIF bit in the TIMx_SR register).



Generates an interrupt if the corresponding interrupt mask is set (CCXIE bit in the
TIMx_DIER register).



Sends a DMA request if the corresponding enable bit is set (CCxDE bit in the
TIMx_DIER register, CCDS bit in the TIMx_CR2 register for the DMA request
selection).

The TIMx_CCRx registers can be programmed with or without preload registers using the
OCxPE bit in the TIMx_CCMRx register.
In output compare mode, the update event UEV has no effect on OCxREF and OCx output.
The timing resolution is one count of the counter. Output compare mode can also be used to
output a single pulse (in One Pulse mode).

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Procedure:
1.

Select the counter clock (internal, external, prescaler).

2.

Write the desired data in the TIMx_ARR and TIMx_CCRx registers.

3.

Set the CCxIE bit if an interrupt request is to be generated.

4.

Select the output mode. For example:

5.

–

Write OCxM = 011 to toggle OCx output pin when CNT matches CCRx

–

Write OCxPE = 0 to disable preload register

–

Write CCxP = 0 to select active high polarity

–

Write CCxE = 1 to enable the output

Enable the counter by setting the CEN bit in the TIMx_CR1 register.

For code example refer to the Appendix section A.8.7: Output compare configuration code
example.
The TIMx_CCRx register can be updated at any time by software to control the output
waveform, provided that the preload register is not enabled (OCxPE=’0’, else TIMx_CCRx
shadow register is updated only at the next update event UEV). An example is given in
Figure 71.
Figure 71. Output compare mode, toggle on OC1
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13.3.10

PWM mode
Pulse Width Modulation mode allows you to generate a signal with a frequency determined
by the value of the TIMx_ARR register and a duty cycle determined by the value of the
TIMx_CCRx register.
The PWM mode can be selected independently on each channel (one PWM per OCx
output) by writing ‘110’ (PWM mode 1) or ‘111’ (PWM mode 2) in the OCxM bits in the
TIMx_CCMRx register. You must enable the corresponding preload register by setting the

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Advanced-control timers (TIM1)
OCxPE bit in the TIMx_CCMRx register, and eventually the auto-reload preload register (in
upcounting or center-aligned modes) by setting the ARPE bit in the TIMx_CR1 register.
As the preload registers are transferred to the shadow registers only when an update event
occurs, before starting the counter, you have to initialize all the registers by setting the UG
bit in the TIMx_EGR register.
OCx polarity is software programmable using the CCxP bit in the TIMx_CCER register. It
can be programmed as active high or active low. OCx output is enabled by a combination of
the CCxE, CCxNE, MOE, OSSI and OSSR bits (TIMx_CCER and TIMx_BDTR registers).
Refer to the TIMx_CCER register description for more details.
In PWM mode (1 or 2), TIMx_CNT and TIMx_CCRx are always compared to determine
whether TIMx_CCRx ≤ TIMx_CNT or TIMx_CNT ≤ TIMx_CCRx (depending on the direction
of the counter).
The timer is able to generate PWM in edge-aligned mode or center-aligned mode
depending on the CMS bits in the TIMx_CR1 register.

PWM edge-aligned mode


Upcounting configuration
Upcounting is active when the DIR bit in the TIMx_CR1 register is low. Refer to the
Upcounting mode on page 225.
In the following example, we consider PWM mode 1. The reference PWM signal
OCxREF is high as long as TIMx_CNT < TIMx_CCRx else it becomes low. If the
compare value in TIMx_CCRx is greater than the auto-reload value (in TIMx_ARR)
then OCxREF is held at ‘1’. If the compare value is 0 then OCxRef is held at ‘0’.
Figure 72 shows some edge-aligned PWM waveforms in an example where
TIMx_ARR=8.

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Figure 72. Edge-aligned PWM waveforms (ARR=8)



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For code example refer to the Appendix section A.8.8: Edge-aligned PWM configuration
example.


Downcounting configuration
Downcounting is active when DIR bit in TIMx_CR1 register is high. Refer to the
Downcounting mode on page 229
In PWM mode 1, the reference signal OCxRef is low as long as
TIMx_CNT > TIMx_CCRx else it becomes high. If the compare value in TIMx_CCRx is
greater than the auto-reload value in TIMx_ARR, then OCxREF is held at ‘1’. 0% PWM
is not possible in this mode.

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Advanced-control timers (TIM1)

PWM center-aligned mode
Center-aligned mode is active when the CMS bits in TIMx_CR1 register are different from
‘00’ (all the remaining configurations having the same effect on the OCxRef/OCx signals).
The compare flag is set when the counter counts up, when it counts down or both when it
counts up and down depending on the CMS bits configuration. The direction bit (DIR) in the
TIMx_CR1 register is updated by hardware and must not be changed by software. Refer to
the Center-aligned mode (up/down counting) on page 231.
Figure 73 shows some center-aligned PWM waveforms in an example where:


TIMx_ARR=8,



PWM mode is the PWM mode 1,



The flag is set when the counter counts down corresponding to the center-aligned
mode 1 selected for CMS=01 in TIMx_CR1 register.

For code example refer to the Appendix section A.8.9: Center-aligned PWM configuration
example.
Figure 73. Center-aligned PWM waveforms (ARR=8)
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Hints on using center-aligned mode:


When starting in center-aligned mode, the current up-down configuration is used. It
means that the counter counts up or down depending on the value written in the DIR bit
in the TIMx_CR1 register. Moreover, the DIR and CMS bits must not be changed at the
same time by the software.



Writing to the counter while running in center-aligned mode is not recommended as it
can lead to unexpected results. In particular:



13.3.11

–

The direction is not updated if you write a value in the counter that is greater than
the auto-reload value (TIMx_CNT>TIMx_ARR). For example, if the counter was
counting up, it continues to count up.

–

The direction is updated if you write 0 or write the TIMx_ARR value in the counter
but no Update Event UEV is generated.

The safest way to use center-aligned mode is to generate an update by software
(setting the UG bit in the TIMx_EGR register) just before starting the counter and not to
write the counter while it is running.

Complementary outputs and dead-time insertion
The advanced-control timers (TIM1) can output two complementary signals and manage the
switching-off and the switching-on instants of the outputs.
This time is generally known as dead-time and you have to adjust it depending on the
devices you have connected to the outputs and their characteristics (intrinsic delays of levelshifters, delays due to power switches...)
You can select the polarity of the outputs (main output OCx or complementary OCxN)
independently for each output. This is done by writing to the CCxP and CCxNP bits in the
TIMx_CCER register.
The complementary signals OCx and OCxN are activated by a combination of several
control bits: the CCxE and CCxNE bits in the TIMx_CCER register and the MOE, OISx,
OISxN, OSSI and OSSR bits in the TIMx_BDTR and TIMx_CR2 registers. Refer to
Table 46: Output control bits for complementary OCx and OCxN channels with break
feature on page 286 for more details. In particular, the dead-time is activated when
switching to the IDLE state (MOE falling down to 0).
Dead-time insertion is enabled by setting both CCxE and CCxNE bits, and the MOE bit if the
break circuit is present. There is one 10-bit dead-time generator for each channel. From a
reference waveform OCxREF, it generates 2 outputs OCx and OCxN. If OCx and OCxN are
active high:


The OCx output signal is the same as the reference signal except for the rising edge,
which is delayed relative to the reference rising edge.



The OCxN output signal is the opposite of the reference signal except for the rising
edge, which is delayed relative to the reference falling edge.

If the delay is greater than the width of the active output (OCx or OCxN) then the
corresponding pulse is not generated.
The following figures show the relationships between the output signals of the dead-time
generator and the reference signal OCxREF. (we suppose CCxP=0, CCxNP=0, MOE=1,
CCxE=1 and CCxNE=1 in these examples)

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Advanced-control timers (TIM1)
Figure 74. Complementary output with dead-time insertion.

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Figure 75. Dead-time waveforms with delay greater than the negative pulse.

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Figure 76. Dead-time waveforms with delay greater than the positive pulse.

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The dead-time delay is the same for each of the channels and is programmable with the
DTG bits in the TIMx_BDTR register. Refer to Section 13.4.18: TIM1 break and dead-time
register (TIM1_BDTR) on page 290 for delay calculation.

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Re-directing OCxREF to OCx or OCxN
In output mode (forced, output compare or PWM), OCxREF can be re-directed to the OCx
output or to OCxN output by configuring the CCxE and CCxNE bits in the TIMx_CCER
register.
This allows you to send a specific waveform (such as PWM or static active level) on one
output while the complementary remains at its inactive level. Other alternative possibilities
are to have both outputs at inactive level or both outputs active and complementary with
dead-time.
Note:

When only OCxN is enabled (CCxE=0, CCxNE=1), it is not complemented and becomes
active as soon as OCxREF is high. For example, if CCxNP=0 then OCxN=OCxRef. On the
other hand, when both OCx and OCxN are enabled (CCxE=CCxNE=1) OCx becomes
active when OCxREF is high whereas OCxN is complemented and becomes active when
OCxREF is low.

13.3.12

Using the break function
When using the break function, the output enable signals and inactive levels are modified
according to additional control bits (MOE, OSSI and OSSR bits in the TIMx_BDTR register,
OISx and OISxN bits in the TIMx_CR2 register). In any case, the OCx and OCxN outputs
cannot be set both to active level at a given time. Refer to Table 46: Output control bits for
complementary OCx and OCxN channels with break feature on page 286 for more details.
The source for break (BRK) channel can be an external source connected to the BKIN pin or
one of the following internal sources:


the core LOCKUP output



the PVD output



the SRAM parity error signal



a clock failure event generated by the CSS detector



the output from a comparator

When exiting from reset, the break circuit is disabled and the MOE bit is low. You can enable
the break function by setting the BKE bit in the TIMx_BDTR register. The break input
polarity can be selected by configuring the BKP bit in the same register. BKE and BKP can
be modified at the same time. When the BKE and BKP bits are written, a delay of 1 APB
clock cycle is applied before the writing is effective. Consequently, it is necessary to wait 1
APB clock period to correctly read back the bit after the write operation.
Because MOE falling edge can be asynchronous, a resynchronization circuit has been
inserted between the actual signal (acting on the outputs) and the synchronous control bit
(accessed in the TIMx_BDTR register). It results in some delays between the asynchronous
and the synchronous signals. In particular, if you write MOE to 1 whereas it was low, you
must insert a delay (dummy instruction) before reading it correctly. This is because you write
the asynchronous signal and read the synchronous signal.

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Advanced-control timers (TIM1)
When a break occurs (selected level on the break input):

Note:



The MOE bit is cleared asynchronously, putting the outputs in inactive state, idle state
or in reset state (selected by the OSSI bit). This feature functions even if the MCU
oscillator is off.



Each output channel is driven with the level programmed in the OISx bit in the
TIMx_CR2 register as soon as MOE=0. If OSSI=0 then the timer releases the enable
output else the enable output remains high.



When complementary outputs are used:
–

The outputs are first put in reset state inactive state (depending on the polarity).
This is done asynchronously so that it works even if no clock is provided to the
timer.

–

If the timer clock is still present, then the dead-time generator is reactivated in
order to drive the outputs with the level programmed in the OISx and OISxN bits
after a dead-time. Even in this case, OCx and OCxN cannot be driven to their
active level together. Note that because of the resynchronization on MOE, the
dead-time duration is a bit longer than usual (around 2 ck_tim clock cycles).

–

If OSSI=0 then the timer releases the enable outputs else the enable outputs
remain or become high as soon as one of the CCxE or CCxNE bits is high.



The break status flag (BIF bit in the TIMx_SR register) is set. An interrupt can be
generated if the BIE bit in the TIMx_DIER register is set.



If the AOE bit in the TIMx_BDTR register is set, the MOE bit is automatically set again
at the next update event UEV. This can be used to perform a regulation, for instance.
Else, MOE remains low until you write it to ‘1’ again. In this case, it can be used for
security and you can connect the break input to an alarm from power drivers, thermal
sensors or any security components.

The break inputs is acting on level. Thus, the MOE cannot be set while the break input is
active (neither automatically nor by software). In the meantime, the status flag BIF cannot
be cleared.
The break can be generated by the BRK input which has a programmable polarity and an
enable bit BKE in the TIMx_BDTR Register.
In addition to the break input and the output management, a write protection has been
implemented inside the break circuit to safeguard the application. It allows you to freeze the
configuration of several parameters (dead-time duration, OCx/OCxN polarities and state
when disabled, OCxM configurations, break enable and polarity). You can choose from 3
levels of protection selected by the LOCK bits in the TIMx_BDTR register. Refer to
Section 13.4.18: TIM1 break and dead-time register (TIM1_BDTR) on page 290. The LOCK
bits can be written only once after an MCU reset.
The Figure 77 shows an example of behavior of the outputs in response to a break.

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Figure 77. Output behavior in response to a break
BREAK (MOE

)

OCxREF

OCx
(OCxN not implemented, CCxP=0, OISx=1)

OCx
(OCxN not implemented, CCxP=0, OISx=0)

OCx
(OCxN not implemented, CCxP=1, OISx=1)

OCx
(OCxN not implemented, CCxP=1, OISx=0)

OCx
delay
delay
OCxN
(CCxE=1, CCxP=0, OISx=0, CCxNE=1, CCxNP=0, OISxN=1)

delay

OCx
delay
delay
OCxN
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delay

OCx
OCxN
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delay

OCx
OCxN
(CCxE=1, CCxP=0, OISx=1, CCxNE=0, CCxNP=0, OISxN=0)

delay

OCx
OCxN
(CCxE=1, CCxP=0, CCxNE=0, CCxNP=0, OISx=OISxN=0 or OISx=OISxN=1)

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13.3.13

Advanced-control timers (TIM1)

Clearing the OCxREF signal on an external event
The OCxREF signal of a given channel can be cleared when a high level is applied on the
OCREF_CLR_INPUT (OCxCE enable bit in the corresponding TIMx_CCMRx register set to
1). OCxREF remains low until the next update event (UEV) occurs. This function can only
be used in Output compare and PWM modes. It does not work in Forced mode.
OCREF_CLR_INPUT can be selected between the OCREF_CLR input and ETRF (ETR
after the filter) by configuring the OCCS bit in the TIMx_SMCR register.
When ETRF is chosen, ETR must be configured as follows:
The OCxREF signal for a given channel can be driven Low by applying a High level to the
ETRF input (OCxCE enable bit of the corresponding TIMx_CCMRx register set to ‘1’). The
OCxREF signal remains Low until the next update event, UEV, occurs.
This function can only be used in output compare and PWM modes, and does not work in
forced mode.
For example, the OCxREF signal can be connected to the output of a comparator to be
used for current handling. In this case, the ETR must be configured as follow:
1.

The External Trigger Prescaler should be kept off: bits ETPS[1:0] of the TIMx_SMCR
register set to ‘00’.

2.

The external clock mode 2 must be disabled: bit ECE of the TIMx_SMCR register set to
‘0’.

3.

The External Trigger Polarity (ETP) and the External Trigger Filter (ETF) can be
configured according to the user needs.

For code example refer to the Appendix section A.8.10: ETR configuration to clear OCxREF
code example.
Figure 78 shows the behavior of the OCxREF signal when the ETRF Input becomes High,
for both values of the enable bit OCxCE. In this example, the timer TIMx is programmed in
PWM mode.

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Figure 78. Clearing TIMx OCxREF

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Note:

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In case of a PWM with a 100% duty cycle (if CCRx>ARR), then OCxREF is enabled again at
the next counter overflow.

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Advanced-control timers (TIM1)

13.3.14

6-step PWM generation
When complementary outputs are used on a channel, preload bits are available on the
OCxM, CCxE and CCxNE bits. The preload bits are transferred to the shadow bits at the
COM commutation event. Thus you can program in advance the configuration for the next
step and change the configuration of all the channels at the same time. COM can be
generated by software by setting the COM bit in the TIMx_EGR register or by hardware (on
TRGI rising edge).
A flag is set when the COM event occurs (COMIF bit in the TIMx_SR register), which can
generate an interrupt (if the COMIE bit is set in the TIMx_DIER register) or a DMA request
(if the COMDE bit is set in the TIMx_DIER register).
The Figure 79 describes the behavior of the OCx and OCxN outputs when a COM event
occurs, in 3 different examples of programmed configurations.
Figure 79. 6-step generation, COM example (OSSR=1)

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13.3.15

RM0360

One-pulse mode
One-pulse mode (OPM) is a particular case of the previous modes. It allows the counter to
be started in response to a stimulus and to generate a pulse with a programmable length
after a programmable delay.
Starting the counter can be controlled through the slave mode controller. Generating the
waveform can be done in output compare mode or PWM mode. You select One-pulse mode
by setting the OPM bit in the TIMx_CR1 register. This makes the counter stop automatically
at the next update event UEV.
A pulse can be correctly generated only if the compare value is different from the counter
initial value. Before starting (when the timer is waiting for the trigger), the configuration must
be:


In upcounting: CNT < CCRx ≤ ARR (in particular, 0 < CCRx)



In downcounting: CNT > CCRx
Figure 80. Example of one pulse mode
TI2
OC1REF

Counter

OC1

TIM1_ARR
TIM1_CCR1

0
tDELAY

tPULSE

t

For example you may want to generate a positive pulse on OC1 with a length of tPULSE and
after a delay of tDELAY as soon as a positive edge is detected on the TI2 input pin.
Let’s use TI2FP2 as trigger 1:

258/779



Map TI2FP2 to TI2 by writing CC2S=’01’ in the TIMx_CCMR1 register.



TI2FP2 must detect a rising edge, write CC2P=’0’ and CC2NP=’0’ in the TIMx_CCER
register.



Configure TI2FP2 as trigger for the slave mode controller (TRGI) by writing TS=’110’ in
the TIMx_SMCR register.



TI2FP2 is used to start the counter by writing SMS to ‘110’ in the TIMx_SMCR register
(trigger mode).

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Advanced-control timers (TIM1)
The OPM waveform is defined by writing the compare registers (taking into account the
clock frequency and the counter prescaler).


The tDELAY is defined by the value written in the TIMx_CCR1 register.



The tPULSE is defined by the difference between the auto-reload value and the compare
value (TIMx_ARR - TIMx_CCR1+1).



Let’s say you want to build a waveform with a transition from ‘0’ to ‘1’ when a compare
match occurs and a transition from ‘1’ to ‘0’ when the counter reaches the auto-reload
value. To do this you enable PWM mode 2 by writing OC1M=111 in the TIMx_CCMR1
register. You can optionally enable the preload registers by writing OC1PE=’1’ in the
TIMx_CCMR1 register and ARPE in the TIMx_CR1 register. In this case you have to
write the compare value in the TIMx_CCR1 register, the auto-reload value in the
TIMx_ARR register, generate an update by setting the UG bit and wait for external
trigger event on TI2. CC1P is written to ‘0’ in this example.

In our example, the DIR and CMS bits in the TIMx_CR1 register should be low.
For code example refer to the Appendix section A.8.16: One-Pulse mode code example.
You only want 1 pulse (Single mode), so you write '1 in the OPM bit in the TIMx_CR1
register to stop the counter at the next update event (when the counter rolls over from the
auto-reload value back to 0). When OPM bit in the TIMx_CR1 register is set to '0', so the
Repetitive Mode is selected.

Particular case: OCx fast enable
In One-pulse mode, the edge detection on TIx input set the CEN bit which enables the
counter. Then the comparison between the counter and the compare value makes the
output toggle. But several clock cycles are needed for these operations and it limits the
minimum delay tDELAY min we can get.
If you want to output a waveform with the minimum delay, you can set the OCxFE bit in the
TIMx_CCMRx register. Then OCxRef (and OCx) are forced in response to the stimulus,
without taking in account the comparison. Its new level is the same as if a compare match
had occurred. OCxFE acts only if the channel is configured in PWM1 or PWM2 mode.
For code example refer to the part of code, conditioned by PULSE_WITHOUT_DELAY > 0
in the Appendix section A.8.16: One-Pulse mode code example.

13.3.16

Encoder interface mode
To select Encoder Interface mode write SMS=‘001’ in the TIMx_SMCR register if the
counter is counting on TI2 edges only, SMS=’010’ if it is counting on TI1 edges only and
SMS=’011’ if it is counting on both TI1 and TI2 edges.
Select the TI1 and TI2 polarity by programming the CC1P and CC2P bits in the TIMx_CCER
register. When needed, you can program the input filter as well. CC1NP and CC2NP must
be kept low.
The two inputs TI1 and TI2 are used to interface to an incremental encoder. Refer to
Table 44. The counter is clocked by each valid transition on TI1FP1 or TI2FP2 (TI1 and TI2
after input filter and polarity selection, TI1FP1=TI1 if not filtered and not inverted,
TI2FP2=TI2 if not filtered and not inverted) assuming that it is enabled (CEN bit in
TIMx_CR1 register written to ‘1’). The sequence of transitions of the two inputs is evaluated
and generates count pulses as well as the direction signal. Depending on the sequence the
counter counts up or down, the DIR bit in the TIMx_CR1 register is modified by hardware

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Advanced-control timers (TIM1)

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accordingly. The DIR bit is calculated at each transition on any input (TI1 or TI2), whatever
the counter is counting on TI1 only, TI2 only or both TI1 and TI2.
Encoder interface mode acts simply as an external clock with direction selection. This
means that the counter just counts continuously between 0 and the auto-reload value in the
TIMx_ARR register (0 to ARR or ARR down to 0 depending on the direction). So you must
configure TIMx_ARR before starting. in the same way, the capture, compare, prescaler,
repetition counter, trigger output features continue to work as normal. Encoder mode and
External clock mode 2 are not compatible and must not be selected together.
In this mode, the counter is modified automatically following the speed and the direction of
the incremental encoder and its content, therefore, always represents the encoder’s
position. The count direction correspond to the rotation direction of the connected sensor.
The table summarizes the possible combinations, assuming TI1 and TI2 don’t switch at the
same time.
Table 44. Counting direction versus encoder signals

Active edge

Level on
opposite
signal (TI1FP1
for TI2,
TI2FP2 for
TI1)

TI1FP1 signal

TI2FP2 signal

Rising

Falling

Rising

Falling

Counting on
TI1 only

High

Down

Up

No Count

No Count

Low

Up

Down

No Count

No Count

Counting on
TI2 only

High

No Count

No Count

Up

Down

Low

No Count

No Count

Down

Up

Counting on
TI1 and TI2

High

Down

Up

Up

Down

Low

Up

Down

Down

Up

An external incremental encoder can be connected directly to the MCU without external
interface logic. However, comparators are normally be used to convert the encoder’s
differential outputs to digital signals. This greatly increases noise immunity. The third
encoder output which indicate the mechanical zero position, may be connected to an
external interrupt input and trigger a counter reset.
Figure 81 gives an example of counter operation, showing count signal generation and
direction control. It also shows how input jitter is compensated where both edges are
selected. This might occur if the sensor is positioned near to one of the switching points. For
this example we assume that the configuration is the following:


CC1S=’01’ (TIMx_CCMR1 register, TI1FP1 mapped on TI1).



CC2S=’01’ (TIMx_CCMR2 register, TI1FP2 mapped on TI2).



CC1P=’0’ (TIMx_CCER register, TI1FP1 non-inverted, TI1FP1=TI1).



CC2P=’0’ (TIMx_CCER register, TI1FP2 non-inverted, TI1FP2= TI2).



SMS=’011’ (TIMx_SMCR register, both inputs are active on both rising and falling
edges).



CEN=’1’ (TIMx_CR1 register, Counter enabled).

For code example refer to the Appendix section A.8.11: Encoder interface code example.

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Advanced-control timers (TIM1)
Figure 81. Example of counter operation in encoder interface mode.
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Figure 82 gives an example of counter behavior when TI1FP1 polarity is inverted (same
configuration as above except CC1P=’1’).
Figure 82. Example of encoder interface mode with TI1FP1 polarity inverted.
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The timer, when configured in Encoder Interface mode provides information on the sensor’s
current position. You can obtain dynamic information (speed, acceleration, deceleration) by
measuring the period between two encoder events using a second timer configured in
capture mode. The output of the encoder which indicates the mechanical zero can be used
for this purpose. Depending on the time between two events, the counter can also be read
at regular times. You can do this by latching the counter value into a third input capture
register if available (then the capture signal must be periodic and can be generated by
another timer). when available, it is also possible to read its value through a DMA request
generated by a real-time clock.

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13.3.17

RM0360

Timer input XOR function
The TI1S bit in the TIMx_CR2 register, allows the input filter of channel 1 to be connected to
the output of a XOR gate, combining the three input pins TIMx_CH1, TIMx_CH2 and
TIMx_CH3.
The XOR output can be used with all the timer input functions such as trigger or input
capture. An example of this feature used to interface Hall sensors is given in
Section 13.3.18 below.

13.3.18

Interfacing with Hall sensors
This is done using the advanced-control timers (TIM1) to generate PWM signals to drive the
motor and another timer (TIM3) referred to as “interfacing timer” in Figure 83. The
“interfacing timer” captures the 3 timer input pins (CC1, CC2, CC3) connected through a
XOR to the TI1 input channel (selected by setting the TI1S bit in the TIMx_CR2 register).
The slave mode controller is configured in reset mode; the slave input is TI1F_ED. Thus,
each time one of the 3 inputs toggles, the counter restarts counting from 0. This creates a
time base triggered by any change on the Hall inputs.
On the “interfacing timer”, capture/compare channel 1 is configured in capture mode,
capture signal is TRC (See Figure 66: Capture/compare channel (example: channel 1 input
stage) on page 241). The captured value, which corresponds to the time elapsed between 2
changes on the inputs, gives information about motor speed.
The “interfacing timer” can be used in output mode to generate a pulse which changes the
configuration of the channels of the advanced-control timer (TIM1) (by triggering a COM
event). The TIM1 timer is used to generate PWM signals to drive the motor. To do this, the
interfacing timer channel must be programmed so that a positive pulse is generated after a
programmed delay (in output compare or PWM mode). This pulse is sent to the advancedcontrol timer (TIM1) through the TRGO output.
Example: you want to change the PWM configuration of your advanced-control timer TIM1
after a programmed delay each time a change occurs on the Hall inputs connected to one of
the TIMx timers.


Configure 3 timer inputs XORed to the TI1 input channel by writing the TI1S bit in the
TIMx_CR2 register to ‘1’,



Program the time base: write the TIMx_ARR to the max value (the counter must be
cleared by the TI1 change. Set the prescaler to get a maximum counter period longer
than the time between 2 changes on the sensors,



Program channel 1 in capture mode (TRC selected): write the CC1S bits in the
TIMx_CCMR1 register to ‘01’. You can also program the digital filter if needed,



Program channel 2 in PWM 2 mode with the desired delay: write the OC2M bits to ‘111’
and the CC2S bits to ‘00’ in the TIMx_CCMR1 register,



Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2
register to ‘101’,

In the advanced-control timer TIM1, the right ITR input must be selected as trigger input, the
timer is programmed to generate PWM signals, the capture/compare control signals are
preloaded (CCPC=1 in the TIMx_CR2 register) and the COM event is controlled by the
trigger input (CCUS=1 in the TIMx_CR2 register). The PWM control bits (CCxE, OCxM) are
written after a COM event for the next step (this can be done in an interrupt subroutine
generated by the rising edge of OC2REF).

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Advanced-control timers (TIM1)
Figure 83 describes this example.
Figure 83. Example of hall sensor interface

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Advanced-control timers (TIM1)

13.3.19

RM0360

TIMx and external trigger synchronization
The TIMx timer can be synchronized with an external trigger in several modes: Reset mode,
Gated mode and Trigger mode.

Slave mode: Reset mode
The counter and its prescaler can be reinitialized in response to an event on a trigger input.
Moreover, if the URS bit from the TIMx_CR1 register is low, an update event UEV is
generated. Then all the preloaded registers (TIMx_ARR, TIMx_CCRx) are updated.
In the following example, the upcounter is cleared in response to a rising edge on TI1 input:


Configure the channel 1 to detect rising edges on TI1. Configure the input filter duration
(in this example, we don’t need any filter, so we keep IC1F=0000). The capture
prescaler is not used for triggering, so you don’t need to configure it. The CC1S bits
select the input capture source only, CC1S = 01 in the TIMx_CCMR1 register. Write
CC1P=0 and CC1NP=’0’ in TIMx_CCER register to validate the polarity (and detect
rising edges only).



Configure the timer in reset mode by writing SMS=100 in TIMx_SMCR register. Select
TI1 as the input source by writing TS=101 in TIMx_SMCR register.



Start the counter by writing CEN=1 in the TIMx_CR1 register.

For code example refer to the Appendix section A.8.12: Reset mode code example.
The counter starts counting on the internal clock, then behaves normally until TI1 rising
edge. When TI1 rises, the counter is cleared and restarts from 0. In the meantime, the
trigger flag is set (TIF bit in the TIMx_SR register) and an interrupt request, or a DMA
request can be sent if enabled (depending on the TIE and TDE bits in TIMx_DIER register).
The following figure shows this behavior when the auto-reload register TIMx_ARR=0x36.
The delay between the rising edge on TI1 and the actual reset of the counter is due to the
resynchronization circuit on TI1 input.
Figure 84. Control circuit in reset mode
TI1
UG
Counter clock = ck_cnt = ck_psc
Counter register

30 31 32 33 34 35 36 00 01 02 03 00 01 02 03

TIF

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Advanced-control timers (TIM1)

Slave mode: Gated mode
The counter can be enabled depending on the level of a selected input.
In the following example, the upcounter counts only when TI1 input is low:


Configure the channel 1 to detect low levels on TI1. Configure the input filter duration
(in this example, we don’t need any filter, so we keep IC1F=0000). The capture
prescaler is not used for triggering, so you don’t need to configure it. The CC1S bits
select the input capture source only, CC1S=01 in TIMx_CCMR1 register. Write
CC1P=1 and CC1NP=’0’ in TIMx_CCER register to validate the polarity (and detect
low level only).



Configure the timer in gated mode by writing SMS=101 in TIMx_SMCR register. Select
TI1 as the input source by writing TS=101 in TIMx_SMCR register.



Enable the counter by writing CEN=1 in the TIMx_CR1 register (in gated mode, the
counter doesn’t start if CEN=0, whatever is the trigger input level).

For code example refer to the Appendix section A.8.13: Gated mode code example.
The counter starts counting on the internal clock as long as TI1 is low and stops as soon as
TI1 becomes high. The TIF flag in the TIMx_SR register is set both when the counter starts
or stops.
The delay between the rising edge on TI1 and the actual stop of the counter is due to the
resynchronization circuit on TI1 input.
Figure 85. Control circuit in gated mode
TI1
cnt_en
Counter clock = ck_cnt = ck_psc
Counter register

30 31 32 33

34

35 36 37 38

TIF

Write TIF=0

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Slave mode: Trigger mode
The counter can start in response to an event on a selected input.
In the following example, the upcounter starts in response to a rising edge on TI2 input:


Configure the channel 2 to detect rising edges on TI2. Configure the input filter duration
(in this example, we don’t need any filter, so we keep IC2F=0000). The capture
prescaler is not used for triggering, so you don’t need to configure it. The CC2S bits are
configured to select the input capture source only, CC2S=01 in TIMx_CCMR1 register.
Write CC2P=1 and CC2NP=0 in TIMx_CCER register to validate the polarity (and
detect low level only).



Configure the timer in trigger mode by writing SMS=110 in TIMx_SMCR register. Select
TI2 as the input source by writing TS=110 in TIMx_SMCR register.

For code example refer to the Appendix section A.8.14: Trigger mode code example.
When a rising edge occurs on TI2, the counter starts counting on the internal clock and the
TIF flag is set.
The delay between the rising edge on TI2 and the actual start of the counter is due to the
resynchronization circuit on TI2 input.
Figure 86. Control circuit in trigger mode
TI2
cnt_en
Counter clock = ck_cnt = ck_psc
Counter register

34

35 36 37 38

TIF

Slave mode: external clock mode 2 + trigger mode
The external clock mode 2 can be used in addition to another slave mode (except external
clock mode 1 and encoder mode). In this case, the ETR signal is used as external clock
input, and another input can be selected as trigger input (in reset mode, gated mode or
trigger mode). It is recommended not to select ETR as TRGI through the TS bits of
TIMx_SMCR register.
In the following example, the upcounter is incremented at each rising edge of the ETR
signal as soon as a rising edge of TI1 occurs:
1.

266/779

Configure the external trigger input circuit by programming the TIMx_SMCR register as
follows:
–

ETF = 0000: no filter

–

ETPS=00: prescaler disabled

–

ETP=0: detection of rising edges on ETR and ECE=1 to enable the external clock
mode 2.

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Advanced-control timers (TIM1)
2.

3.

Configure the channel 1 as follows, to detect rising edges on TI:
–

IC1F=0000: no filter.

–

The capture prescaler is not used for triggering and does not need to be
configured.

–

CC1S=01in TIMx_CCMR1 register to select only the input capture source

–

CC1P=0 and CC1NP=’0’ in TIMx_CCER register to validate the polarity (and
detect rising edge only).

Configure the timer in trigger mode by writing SMS=110 in TIMx_SMCR register. Select
TI1 as the input source by writing TS=101 in TIMx_SMCR register.

For code example refer to the Appendix section A.8.15: External clock mode 2 + trigger
mode code example.
A rising edge on TI1 enables the counter and sets the TIF flag. The counter then counts on
ETR rising edges.
The delay between the rising edge of the ETR signal and the actual reset of the counter is
due to the resynchronization circuit on ETRP input.
Figure 87. Control circuit in external clock mode 2 + trigger mode

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13.3.20

Timer synchronization
The TIM timers are linked together internally for timer synchronization or chaining. Refer to
Section 14.3.15: Timer synchronization on page 331 for details.

13.3.21

Debug mode
When the microcontroller enters debug mode (Cortex™-M0 core halted), the TIMx counter
either continues to work normally or stops, depending on DBG_TIMx_STOP configuration
bit in DBG module.

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Advanced-control timers (TIM1)

13.4

RM0360

TIM1 registers
Refer to Section 1.1 on page 33 for a list of abbreviations used in register descriptions.

13.4.1

TIM1 control register 1 (TIM1_CR1)
Address offset: 0x00
Reset value: 0x0000

15

14

13

12

11

10

Res.

Res.

Res.

Res.

Res.

Res.

9

8

CKD[1:0]
rw

7

6

ARPE

rw

rw

5

CMS[1:0]
rw

rw

4

3

2

1

0

DIR

OPM

URS

UDIS

CEN

rw

rw

rw

rw

rw

Bits 15:10 Reserved, must be kept at reset value.
Bits 9:8 CKD[1:0]: Clock division
This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and the
dead-time and sampling clock (tDTS)used by the dead-time generators and the digital filters
(ETR, TIx),
00: tDTS=tCK_INT
01: tDTS=2*tCK_INT
10: tDTS=4*tCK_INT
11: Reserved, do not program this value
Bit 7 ARPE: Auto-reload preload enable
0: TIMx_ARR register is not buffered
1: TIMx_ARR register is buffered
Bits 6:5 CMS[1:0]: Center-aligned mode selection
00: Edge-aligned mode. The counter counts up or down depending on the direction bit
(DIR).
01: Center-aligned mode 1. The counter counts up and down alternatively. Output compare
interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set
only when the counter is counting down.
10: Center-aligned mode 2. The counter counts up and down alternatively. Output compare
interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set
only when the counter is counting up.
11: Center-aligned mode 3. The counter counts up and down alternatively. Output compare
interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set
both when the counter is counting up or down.
Note: It is not allowed to switch from edge-aligned mode to center-aligned mode as long as
the counter is enabled (CEN=1).
Bit 4 DIR: Direction
0: Counter used as upcounter
1: Counter used as downcounter
Note: This bit is read only when the timer is configured in Center-aligned mode or Encoder
mode.
Bit 3 OPM: One pulse mode
0: Counter is not stopped at update event
1: Counter stops counting at the next update event (clearing the bit CEN)

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Bit 2 URS: Update request source
This bit is set and cleared by software to select the UEV event sources.
0: Any of the following events generate an update interrupt or DMA request if enabled.
These events can be:
–
Counter overflow/underflow
–
Setting the UG bit
–
Update generation through the slave mode controller
1: Only counter overflow/underflow generates an update interrupt or DMA request if
enabled.
Bit 1 UDIS: Update disable
This bit is set and cleared by software to enable/disable UEV event generation.
0: UEV enabled. The Update (UEV) event is generated by one of the following events:
–
Counter overflow/underflow
–
Setting the UG bit
–
Update generation through the slave mode controller
Buffered registers are then loaded with their preload values.
1: UEV disabled. The Update event is not generated, shadow registers keep their value
(ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is
set or if a hardware reset is received from the slave mode controller.
Bit 0 CEN: Counter enable
0: Counter disabled
1: Counter enabled
Note: External clock, gated mode and encoder mode can work only if the CEN bit has been
previously set by software. However trigger mode can set the CEN bit automatically by
hardware.

13.4.2

TIM1 control register 2 (TIM1_CR2)
Address offset: 0x04
Reset value: 0x0000

15

14

13

12

11

10

9

8

7

Res.

OIS4

OIS3N

OIS3

OIS2N

OIS2

OIS1N

OIS1

TI1S

rw

rw

rw

rw

rw

rw

rw

rw

6

5

4

MMS[2:0]
rw

rw

rw

3

2

1

0

CCDS

CCUS

Res.

CCPC

rw

rw

rw

Bit 15 Reserved, must be kept at reset value.
Bit 14 OIS4: Output Idle state 4 (OC4 output)
refer to OIS1 bit
Bit 13 OIS3N: Output Idle state 3 (OC3N output)
refer to OIS1N bit
Bit 12 OIS3: Output Idle state 3 (OC3 output)
refer to OIS1 bit
Bit 11 OIS2N: Output Idle state 2 (OC2N output)
refer to OIS1N bit
Bit 10 OIS2: Output Idle state 2 (OC2 output)
refer to OIS1 bit

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Bit 9 OIS1N: Output Idle state 1 (OC1N output)
0: OC1N=0 after a dead-time when MOE=0
1: OC1N=1 after a dead-time when MOE=0
Note: This bit cannot be modified as long as LOCK level 1, 2 or 3 has been programmed
(LOCK bits in TIMx_BDTR register).
Bit 8 OIS1: Output Idle state 1 (OC1 output)
0: OC1=0 (after a dead-time if OC1N is implemented) when MOE=0
1: OC1=1 (after a dead-time if OC1N is implemented) when MOE=0
Note: This bit cannot be modified as long as LOCK level 1, 2 or 3 has been programmed
(LOCK bits in TIMx_BDTR register).
Bit 7 TI1S: TI1 selection
0: The TIMx_CH1 pin is connected to TI1 input
1: The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination)
Bits 6:4 MMS[1:0]: Master mode selection
These bits allow to select the information to be sent in master mode to slave timers for
synchronization (TRGO). The combination is as follows:
000: Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO). If the
reset is generated by the trigger input (slave mode controller configured in reset mode) then
the signal on TRGO is delayed compared to the actual reset.
001: Enable - the Counter Enable signal CNT_EN is used as trigger output (TRGO). It is
useful to start several timers at the same time or to control a window in which a slave timer is
enable. The Counter Enable signal is generated by a logic OR between CEN control bit and
the trigger input when configured in gated mode. When the Counter Enable signal is
controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is
selected (see the MSM bit description in TIMx_SMCR register).
010: Update - The update event is selected as trigger output (TRGO). For instance a master
timer can then be used as a prescaler for a slave timer.
011: Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be
set (even if it was already high), as soon as a capture or a compare match occurred.
(TRGO).
100: Compare - OC1REF signal is used as trigger output (TRGO)
101: Compare - OC2REF signal is used as trigger output (TRGO)
110: Compare - OC3REF signal is used as trigger output (TRGO)
111: Compare - OC4REF signal is used as trigger output (TRGO)
Bit 3 CCDS: Capture/compare DMA selection
0: CCx DMA request sent when CCx event occurs
1: CCx DMA requests sent when update event occurs
Bit 2 CCUS: Capture/compare control update selection
0: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting
the COMG bit only
1: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting
the COMG bit or when an rising edge occurs on TRGI
Note: This bit acts only on channels that have a complementary output.
Bit 1 Reserved, must be kept at reset value.
Bit 0 CCPC: Capture/compare preloaded control
0: CCxE, CCxNE and OCxM bits are not preloaded
1: CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are updated
only when a communication event (COM) occurs (COMG bit set or rising edge detected on
TRGI, depending on the CCUS bit).
Note: This bit acts only on channels that have a complementary output.

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13.4.3

TIM1 slave mode control register (TIM1_SMCR)
Address offset: 0x08
Reset value: 0x0000

15

14

ETP

ECE

rw

rw

13

12

11

ETPS[1:0]
rw

rw

10

9

8

ETF[3:0]
rw

rw

7

6

MSM

rw

rw

rw

5

4

TS[2:0]
rw

rw

3

2

OCCS
rw

rw

1

0

SMS[2:0]
rw

rw

rw

Bit 15 ETP: External trigger polarity
This bit selects whether ETR or ETR is used for trigger operations
0: ETR is non-inverted, active at high level or rising edge.
1: ETR is inverted, active at low level or falling edge.
Bit 14 ECE: External clock enable
This bit enables External clock mode 2.
0: External clock mode 2 disabled
1: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF
signal.
Note: 1: Setting the ECE bit has the same effect as selecting external clock mode 1 with
TRGI connected to ETRF (SMS=111 and TS=111).
2: It is possible to simultaneously use external clock mode 2 with the following slave
modes: reset mode, gated mode and trigger mode. Nevertheless, TRGI must not be
connected to ETRF in this case (TS bits must not be 111).
3: If external clock mode 1 and external clock mode 2 are enabled at the same time,
the external clock input is ETRF.
Bits 13:12 ETPS[1:0]: External trigger prescaler
External trigger signal ETRP frequency must be at most 1/4 of TIMxCLK frequency. A
prescaler can be enabled to reduce ETRP frequency. It is useful when inputting fast external
clocks.
00: Prescaler OFF
01: ETRP frequency divided by 2
10: ETRP frequency divided by 4
11: ETRP frequency divided by 8

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Bits 11:8 ETF[3:0]: External trigger filter
This bit-field then defines the frequency used to sample ETRP signal and the length of the
digital filter applied to ETRP. The digital filter is made of an event counter in which N
consecutive events are needed to validate a transition on the output:
0000: No filter, sampling is done at fDTS
0001: fSAMPLING = fCK_INT, N = 2
0010: fSAMPLING = fCK_INT, N = 4
0011: fSAMPLING = fCK_INT, N = 8
0100: fSAMPLING = fDTS / 2, N = 6 
0101: fSAMPLING = fDTS / 2, N = 8
0110: fSAMPLING = fDTS / 4, N = 6
0111: fSAMPLING = fDTS / 4, N = 8 
1000: fSAMPLING = fDTS / 8, N = 6
1001: fSAMPLING = fDTS / 8, N = 8
1010: fSAMPLING = fDTS / 16, N = 5
1011: fSAMPLING = fDTS / 16, N = 6
1100: fSAMPLING = fDTS / 16, N = 8
1101: fSAMPLING = fDTS / 32, N = 5
1110: fSAMPLING = fDTS / 32, N = 6
1111: fSAMPLING = fDTS / 32, N = 8
Note: Care must be taken that fDTS is replaced in the formula by CK_INT when ETF[3:0] = 1,
2 or 3.
Bit 7 MSM: Master/slave mode
0: No action
1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect
synchronization between the current timer and its slaves (through TRGO). It is useful if we
want to synchronize several timers on a single external event.

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Bits 6:4 TS[2:0]: Trigger selection
This bit-field selects the trigger input to be used to synchronize the counter.
000: Internal Trigger 0 (ITR0) 
001: Reserved
010: Internal Trigger 2 (ITR2)
011: Internal Trigger 3 (ITR3)
100: TI1 Edge Detector (TI1F_ED)
101: Filtered Timer Input 1 (TI1FP1)
110: Filtered Timer Input 2 (TI2FP2)
111: External Trigger input (ETRF)
See Table 45: TIMx Internal trigger connection on page 273 for more details on ITRx meaning
for each Timer.
Note: These bits must be changed only when they are not used (e.g. when SMS=000) to
avoid wrong edge detections at the transition.
Bit 3 OCCS: OCREF clear selection.
This bit is used to select the OCREF clear source.
0:OCREF_CLR_INT is connected to the OCREF_CLR input
1: OCREF_CLR_INT is connected to ETRF
Bits 2:0 SMS: Slave mode selection
When external signals are selected the active edge of the trigger signal (TRGI) is linked to the
polarity selected on the external input (see Input Control register and Control Register
description.
000: Slave mode disabled - if CEN = ‘1’ then the prescaler is clocked directly by the internal
clock.
001: Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2
level.
010: Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1
level.
011: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges
depending on the level of the other input.
100: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter
and generates an update of the registers.
101: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The
counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of
the counter are controlled.
110: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not
reset). Only the start of the counter is controlled.
111: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.
Note: The gated mode must not be used if TI1F_ED is selected as the trigger input
(TS=’100’). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the
gated mode checks the level of the trigger signal.
Note: The clock of the slave timer must be enabled prior to receive events from the master
timer, and must not be changed on-the-fly while triggers are received from the master
timer.

Table 45. TIMx Internal trigger connection
Slave TIM

ITR0 (TS = 000)

ITR2 (TS = 010)

ITR3 (TS = 011)

TIM1

TIM15

TIM3

TIM17

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13.4.4

RM0360

TIM1 DMA/interrupt enable register (TIM1_DIER)
Address offset: 0x0C
Reset value: 0x0000

15

14

Res.

TDE
rw

13

12

11

10

9

COMDE CC4DE CC3DE CC2DE CC1DE
rw

rw

rw

rw

rw

8

7

6

5

4

3

2

1

0

UDE

BIE

TIE

COMIE

CC4IE

CC3IE

CC2IE

CC1IE

UIE

rw

rw

rw

rw

rw

rw

rw

rw

rw

Bit 15 Reserved, must be kept at reset value.
Bit 14 TDE: Trigger DMA request enable
0: Trigger DMA request disabled
1: Trigger DMA request enabled
Bit 13 COMDE: COM DMA request enable
0: COM DMA request disabled
1: COM DMA request enabled
Bit 12 CC4DE: Capture/Compare 4 DMA request enable
0: CC4 DMA request disabled
1: CC4 DMA request enabled
Bit 11 CC3DE: Capture/Compare 3 DMA request enable
0: CC3 DMA request disabled
1: CC3 DMA request enabled
Bit 10 CC2DE: Capture/Compare 2 DMA request enable
0: CC2 DMA request disabled
1: CC2 DMA request enabled
Bit 9 CC1DE: Capture/Compare 1 DMA request enable
0: CC1 DMA request disabled
1: CC1 DMA request enabled
Bit 8 UDE: Update DMA request enable
0: Update DMA request disabled
1: Update DMA request enabled
Bit 7 BIE: Break interrupt enable
0: Break interrupt disabled
1: Break interrupt enabled
Bit 6 TIE: Trigger interrupt enable
0: Trigger interrupt disabled
1: Trigger interrupt enabled
Bit 5 COMIE: COM interrupt enable
0: COM interrupt disabled
1: COM interrupt enabled
Bit 4 CC4IE: Capture/Compare 4 interrupt enable
0: CC4 interrupt disabled
1: CC4 interrupt enabled
Bit 3 CC3IE: Capture/Compare 3 interrupt enable
0: CC3 interrupt disabled
1: CC3 interrupt enabled

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Bit 2 CC2IE: Capture/Compare 2 interrupt enable
0: CC2 interrupt disabled
1: CC2 interrupt enabled
Bit 1 CC1IE: Capture/Compare 1 interrupt enable
0: CC1 interrupt disabled
1: CC1 interrupt enabled
Bit 0 UIE: Update interrupt enable
0: Update interrupt disabled
1: Update interrupt enabled

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13.4.5

RM0360

TIM1 status register (TIM1_SR)
Address offset: 0x10
Reset value: 0x0000

15

14

13

Res.

Res.

Res.

12

11

10

9

CC4OF CC3OF CC2OF CC1OF
rc_w0

rc_w0

rc_w0

8

7

6

5

4

3

2

1

0

Res.

BIF

TIF

COMIF

CC4IF

CC3IF

CC2IF

CC1IF

UIF

rc_w0

rc_w0

rc_w0

rc_w0

rc_w0

rc_w0

rc_w0

rc_w0

rc_w0

Bits 15:13 Reserved, must be kept at reset value.
Bit 12 CC4OF: Capture/Compare 4 overcapture flag
refer to CC1OF description
Bit 11 CC3OF: Capture/Compare 3 overcapture flag
refer to CC1OF description
Bit 10 CC2OF: Capture/Compare 2 overcapture flag
refer to CC1OF description
Bit 9 CC1OF: Capture/Compare 1 overcapture flag
This flag is set by hardware only when the corresponding channel is configured in input
capture mode. It is cleared by software by writing it to ‘0’.
0: No overcapture has been detected.
1: The counter value has been captured in TIMx_CCR1 register while CC1IF flag was
already set
Bit 8 Reserved, must be kept at reset value.
Bit 7 BIF: Break interrupt flag
This flag is set by hardware as soon as the break input goes active. It can be cleared by
software if the break input is not active.
0: No break event occurred.
1: An active level has been detected on the break input.
Bit 6 TIF: Trigger interrupt flag
This flag is set by hardware on trigger event (active edge detected on TRGI input when the
slave mode controller is enabled in all modes but gated mode.It is cleared by software.
0: No trigger event occurred.
1: Trigger interrupt pending.
Bit 5 COMIF: COM interrupt flag
This flag is set by hardware on COM event (when Capture/compare Control bits - CCxE,
CCxNE, OCxM - have been updated). It is cleared by software by writing it to ‘0’.
0: No COM event occurred.
1: COM interrupt pending.
Bit 4 CC4IF: Capture/Compare 4 interrupt flag
refer to CC1IF description
Bit 3 CC3IF: Capture/Compare 3 interrupt flag
refer to CC1IF description

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Bit 2 CC2IF: Capture/Compare 2 interrupt flag
refer to CC1IF description
Bit 1 CC1IF: Capture/Compare 1 interrupt flag
If channel CC1 is configured as output:
This flag is set by hardware when the counter matches the compare value, with some
exception in center-aligned mode (refer to the CMS bits in the TIMx_CR1 register description).
It is cleared by software.
0: No match.
1: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register.
When the contents of TIMx_CCR1 are greater than the contents of TIMx_ARR, the CC1IF
bit goes high on the counter overflow (in upcounting and up/down-counting modes) or
underflow (in downcounting mode)
If channel CC1 is configured as input:
This bit is set by hardware on a capture. It is cleared by software or by reading the
TIMx_CCR1 register.
0: No input capture occurred
1: The counter value has been captured in TIMx_CCR1 register (An edge has been
detected on IC1 which matches the selected polarity)
Bit 0 UIF: Update interrupt flag
This bit is set by hardware on an update event. It is cleared by software.
0: No update occurred.
1: Update interrupt pending. This bit is set by hardware when the registers are updated:
–At overflow or underflow regarding the repetition counter value (update if repetition
counter = 0) and if the UDIS=0 in the TIMx_CR1 register.
–When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0
and UDIS=0 in the TIMx_CR1 register.
–When CNT is reinitialized by a trigger event (refer to Section 13.4.3: TIM1 slave mode
control register (TIM1_SMCR)), if URS=0 and UDIS=0 in the TIMx_CR1 register.

13.4.6

TIM1 event generation register (TIM1_EGR)
Address offset: 0x14
Reset value: 0x0000

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

BG

TG

COMG

CC4G

CC3G

CC2G

CC1G

UG

w

w

w

w

w

w

w

w

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Bits 15:8 Reserved, must be kept at reset value.
Bit 7 BG: Break generation
This bit is set by software in order to generate an event, it is automatically cleared by
hardware.
0: No action
1: A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or
DMA transfer can occur if enabled.
Bit 6 TG: Trigger generation
This bit is set by software in order to generate an event, it is automatically cleared by
hardware.
0: No action
1: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if
enabled.
Bit 5 COMG: Capture/Compare control update generation
This bit can be set by software, it is automatically cleared by hardware
0: No action
1: When CCPC bit is set, it allows to update CCxE, CCxNE and OCxM bits
Note: This bit acts only on channels having a complementary output.
Bit 4 CC4G: Capture/Compare 4 generation
Refer to CC1G description
Bit 3 CC3G: Capture/Compare 3 generation
Refer to CC1G description
Bit 2 CC2G: Capture/Compare 2 generation
Refer to CC1G description
Bit 1 CC1G: Capture/Compare 1 generation
This bit is set by software in order to generate an event, it is automatically cleared by
hardware.
0: No action
1: A capture/compare event is generated on channel 1:
If channel CC1 is configured as output:
CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled.
If channel CC1 is configured as input:
The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set, the
corresponding interrupt or DMA request is sent if enabled. The CC1OF flag is set if the CC1IF
flag was already high.
Bit 0 UG: Update generation
This bit can be set by software, it is automatically cleared by hardware.
0: No action
1: Reinitialize the counter and generates an update of the registers. Note that the prescaler
counter is cleared too (anyway the prescaler ratio is not affected). The counter is cleared if
the center-aligned mode is selected or if DIR=0 (upcounting), else it takes the auto-reload
value (TIMx_ARR) if DIR=1 (downcounting).

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13.4.7

TIM1 capture/compare mode register 1 (TIM1_CCMR1)
Address offset: 0x18
Reset value: 0x0000
The channels can be used in input (capture mode) or in output (compare mode). The
direction of a channel is defined by configuring the corresponding CCxS bits. All the other
bits of this register have a different function in input and in output mode. For a given bit,
OCxx describes its function when the channel is configured in output, ICxx describes its
function when the channel is configured in input. So you must take care that the same bit
can have a different meaning for the input stage and for the output stage.

15

14

OC2
CE

13

12

OC2M[2:0]
IC2F[3:0]

rw

rw

rw

11

10

OC2
PE

OC2
FE

9

8

CC2S[1:0]

7

6

OC1
CE

rw

rw

4

OC1M[2:0]

IC2PSC[1:0]
rw

5

IC1F[3:0]
rw

rw

rw

rw

rw

3

2

OC1
PE

OC1
FE

1

0

CC1S[1:0]

IC1PSC[1:0]
rw

rw

rw

rw

rw

Output compare mode
Bit 15 OC2CE: Output Compare 2 clear enable
Bits 14:12 OC2M[2:0]: Output Compare 2 mode
Bit 11 OC2PE: Output Compare 2 preload enable
Bit 10 OC2FE: Output Compare 2 fast enable
Bits 9:8 CC2S[1:0]: Capture/Compare 2 selection
This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC2 channel is configured as output
01: CC2 channel is configured as input, IC2 is mapped on TI2
10: CC2 channel is configured as input, IC2 is mapped on TI1
11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if
an internal trigger input is selected through the TS bit (TIMx_SMCR register)
Note: CC2S bits are writable only when the channel is OFF (CC2E = ‘0’ in TIMx_CCER).
Bit 7 OC1CE: Output Compare 1 clear enable
OC1CE: Output Compare 1 Clear Enable
0: OC1Ref is not affected by the ETRF Input
1: OC1Ref is cleared as soon as a High level is detected on ETRF input

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Bits 6:4 OC1M: Output Compare 1 mode
These bits define the behavior of the output reference signal OC1REF from which OC1 and
OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on
CC1P and CC1NP bits.
000: Frozen - The comparison between the output compare register TIMx_CCR1 and the
counter TIMx_CNT has no effect on the outputs (this mode is used to generate a timing
base).
001: Set channel 1 to active level on match. OC1REF signal is forced high when the counter
TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).
010: Set channel 1 to inactive level on match. OC1REF signal is forced low when the
counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).
011: Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1.
100: Force inactive level - OC1REF is forced low.
101: Force active level - OC1REF is forced high.
110: PWM mode 1 - In upcounting, channel 1 is active as long as TIMx_CNTTIMx_CCR1 else active (OC1REF=’1’).
111: PWM mode 2 - In upcounting, channel 1 is inactive as long as TIMx_CNTTIMx_CCR1 else
inactive.
Note: 1: These bits can not be modified as long as LOCK level 3 has been programmed
(LOCK bits in TIMx_BDTR register) and CC1S=’00’ (the channel is configured in
output).
2: In PWM mode 1 or 2, the OCREF level changes only when the result of the
comparison changes or when the output compare mode switches from “frozen” mode
to “PWM” mode.
3: On channels having a complementary output, this bit field is preloaded. If the CCPC
bit is set in the TIMx_CR2 register then the OC1M active bits take the new value from
the preloaded bits only when a COM event is generated.

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Bit 3 OC1PE: Output Compare 1 preload enable
0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the
new value is taken in account immediately.
1: Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload
register. TIMx_CCR1 preload value is loaded in the active register at each update event.
Note: 1: These bits can not be modified as long as LOCK level 3 has been programmed
(LOCK bits in TIMx_BDTR register) and CC1S=’00’ (the channel is configured in
output).
2: The PWM mode can be used without validating the preload register only in one
pulse mode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed.
Bit 2 OC1FE: Output Compare 1 fast enable
This bit is used to accelerate the effect of an event on the trigger in input on the CC output.
0: CC1 behaves normally depending on counter and CCR1 values even when the trigger is
ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is
5 clock cycles.
1: An active edge on the trigger input acts like a compare match on CC1 output. Then, OC is
set to the compare level independently from the result of the comparison. Delay to sample
the trigger input and to activate CC1 output is reduced to 3 clock cycles. OCFE acts only if
the channel is configured in PWM1 or PWM2 mode.
Bits 1:0 CC1S: Capture/Compare 1 selection
This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC1 channel is configured as output
01: CC1 channel is configured as input, IC1 is mapped on TI1
10: CC1 channel is configured as input, IC1 is mapped on TI2
11: CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if
an internal trigger input is selected through TS bit (TIMx_SMCR register)
Note: CC1S bits are writable only when the channel is OFF (CC1E = ‘0’ in TIMx_CCER).

Input capture mode
Bits 15:12 IC2F: Input capture 2 filter
Bits 11:10 IC2PSC[1:0]: Input capture 2 prescaler
Bits 9:8 CC2S: Capture/Compare 2 selection
This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC2 channel is configured as output
01: CC2 channel is configured as input, IC2 is mapped on TI2
10: CC2 channel is configured as input, IC2 is mapped on TI1
11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if an
internal trigger input is selected through TS bit (TIMx_SMCR register)
Note: CC2S bits are writable only when the channel is OFF (CC2E = ‘0’ in TIMx_CCER).

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Bits 7:4 IC1F[3:0]: Input capture 1 filter
This bit-field defines the frequency used to sample TI1 input and the length of the digital filter applied to
TI1. The digital filter is made of an event counter in which N consecutive events are needed to validate
a transition on the output:
0000: No filter, sampling is done at fDTS
0001: fSAMPLING = fCK_INT, N = 2
0010: fSAMPLING = fCK_INT, N = 4
0011: fSAMPLING = fCK_INT, N = 8
0100: fSAMPLING = fDTS / 2, N = 6 
0101: fSAMPLING = fDTS / 2, N = 8
0110: fSAMPLING = fDTS / 4, N = 6
0111: fSAMPLING = fDTS / 4, N = 8 
1000: fSAMPLING = fDTS / 8, N = 6
1001: fSAMPLING = fDTS / 8, N = 8
1010: fSAMPLING = fDTS / 16, N = 5
1011: fSAMPLING = fDTS / 16, N = 6
1100: fSAMPLING = fDTS / 16, N = 8
1101: fSAMPLING = fDTS / 32, N = 5
1110: fSAMPLING = fDTS / 32, N = 6
1111: fSAMPLING = fDTS / 32, N = 8
Note: Care must be taken that fDTS is replaced in the formula by CK_INT when ICxF[3:0] = 1, 2 or 3.
Bits 3:2 IC1PSC: Input capture 1 prescaler
This bit-field defines the ratio of the prescaler acting on CC1 input (IC1).
The prescaler is reset as soon as CC1E=’0’ (TIMx_CCER register).
00: no prescaler, capture is done each time an edge is detected on the capture input
01: capture is done once every 2 events
10: capture is done once every 4 events
11: capture is done once every 8 events
Bits 1:0 CC1S: Capture/Compare 1 Selection
This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC1 channel is configured as output
01: CC1 channel is configured as input, IC1 is mapped on TI1
10: CC1 channel is configured as input, IC1 is mapped on TI2
11: CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if an
internal trigger input is selected through TS bit (TIMx_SMCR register)
Note: CC1S bits are writable only when the channel is OFF (CC1E = ‘0’ in TIMx_CCER).

13.4.8

TIM1 capture/compare mode register 2 (TIM1_CCMR2)
Address offset: 0x1C
Reset value: 0x0000
Refer to the above CCMR1 register description.

15

14

OC4
CE

13

12

OC4M[2:0]
IC4F[3:0]

rw

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rw

rw

11

10

OC4
PE

OC4
FE

9

8

CC4S[1:0]

7

6

OC3
CE.

rw

rw

4

OC3M[2:0]

IC4PSC[1:0]
rw

5

IC3F[3:0]
rw

rw

rw

rw

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3

2

OC3
PE

OC3
FE

1

0

CC3S[1:0]

IC3PSC[1:0]
rw

rw

rw

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rw

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Advanced-control timers (TIM1)

Output compare mode
Bit 15 OC4CE: Output compare 4 clear enable
Bits 14:12 OC4M: Output compare 4 mode
Bit 11 OC4PE: Output compare 4 preload enable
Bit 10 OC4FE: Output compare 4 fast enable
Bits 9:8 CC4S: Capture/Compare 4 selection
This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC4 channel is configured as output
01: CC4 channel is configured as input, IC4 is mapped on TI4
10: CC4 channel is configured as input, IC4 is mapped on TI3
11: CC4 channel is configured as input, IC4 is mapped on TRC. This mode is working only if
an internal trigger input is selected through TS bit (TIMx_SMCR register)
Note: CC4S bits are writable only when the channel is OFF (CC4E = ‘0’ in TIMx_CCER).
Bit 7 OC3CE: Output compare 3 clear enable
Bits 6:4 OC3M: Output compare 3 mode
Bit 3 OC3PE: Output compare 3 preload enable
Bit 2 OC3FE: Output compare 3 fast enable
Bits 1:0 CC3S: Capture/Compare 3 selection
This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC3 channel is configured as output
01: CC3 channel is configured as input, IC3 is mapped on TI3
10: CC3 channel is configured as input, IC3 is mapped on TI4
11: CC3 channel is configured as input, IC3 is mapped on TRC. This mode is working only if
an internal trigger input is selected through TS bit (TIMx_SMCR register)
Note: CC3S bits are writable only when the channel is OFF (CC3E = ‘0’ in TIMx_CCER).

Input capture mode
Bits 15:12 IC4F: Input capture 4 filter
Bits 11:10 IC4PSC: Input capture 4 prescaler
Bits 9:8 CC4S: Capture/Compare 4 selection
This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC4 channel is configured as output
01: CC4 channel is configured as input, IC4 is mapped on TI4
10: CC4 channel is configured as input, IC4 is mapped on TI3
11: CC4 channel is configured as input, IC4 is mapped on TRC. This mode is working only if
an internal trigger input is selected through TS bit (TIMx_SMCR register)
Note: CC4S bits are writable only when the channel is OFF (CC4E = ‘0’ in TIMx_CCER).

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Bits 7:4 IC3F: Input capture 3 filter
Bits 3:2 IC3PSC: Input capture 3 prescaler
Bits 1:0 CC3S: Capture/compare 3 selection
This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC3 channel is configured as output
01: CC3 channel is configured as input, IC3 is mapped on TI3
10: CC3 channel is configured as input, IC3 is mapped on TI4
11: CC3 channel is configured as input, IC3 is mapped on TRC. This mode is working only if
an internal trigger input is selected through TS bit (TIMx_SMCR register)
Note: CC3S bits are writable only when the channel is OFF (CC3E = ‘0’ in TIMx_CCER).

13.4.9

TIM1 capture/compare enable register (TIM1_CCER)
Address offset: 0x20
Reset value: 0x0000

15

14

13

12

Res.

Res.

CC4P

CC4E

rw

rw

11

10

CC3NP CC3NE
rw

rw

9

8

CC3P

CC3E

rw

rw

7

6

CC2NP CC2NE
rw

rw

5

4

CC2P

CC2E

rw

rw

Bits 15:14 Reserved, must be kept at reset value.
Bit 13 CC4P: Capture/Compare 4 output polarity
refer to CC1P description
Bit 12 CC4E: Capture/Compare 4 output enable
refer to CC1E description
Bit 11 CC3NP: Capture/Compare 3 complementary output polarity
refer to CC1NP description
Bit 10 CC3NE: Capture/Compare 3 complementary output enable
refer to CC1NE description
Bit 9 CC3P: Capture/Compare 3 output polarity
refer to CC1P description
Bit 8 CC3E: Capture/Compare 3 output enable
refer to CC1E description
Bit 7 CC2NP: Capture/Compare 2 complementary output polarity
refer to CC1NP description
Bit 6 CC2NE: Capture/Compare 2 complementary output enable
refer to CC1NE description
Bit 5 CC2P: Capture/Compare 2 output polarity
refer to CC1P description
Bit 4 CC2E: Capture/Compare 2 output enable
refer to CC1E description

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2

CC1NP CC1NE
rw

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1

0

CC1P

CC1E

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RM0360

Advanced-control timers (TIM1)

Bit 3 CC1NP: Capture/Compare 1 complementary output polarity
CC1 channel configuration as output:
0: OC1N active high.
1: OC1N active low.
CC1 channel configuration as input:
This bit is used in conjunction with CC1P to define the polarity of TI1FP1 and TI2FP1. Refer to
CC1P description.
Note: On channels having a complementary output, this bit is preloaded. If the CCPC bit is
set in the TIMx_CR2 register then the CC1NP active bit takes the new value from the
preloaded bits only when a Commutation event is generated.
Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits
in TIMx_BDTR register) and CC1S=”00” (the channel is configured in output).
Bit 2 CC1NE: Capture/Compare 1 complementary output enable
0: Off - OC1N is not active. OC1N level is then function of MOE, OSSI, OSSR, OIS1, OIS1N
and CC1E bits.
1: On - OC1N signal is output on the corresponding output pin depending on MOE, OSSI,
OSSR, OIS1, OIS1N and CC1E bits.
Note: On channels having a complementary output, this bit is preloaded. If the CCPC bit is
set in the TIMx_CR2 register then the CC1NE active bit takes the new value from the
preloaded bits only when a Commutation event is generated.
Bit 1 CC1P: Capture/Compare 1 output polarity
CC1 channel configured as output:
0: OC1 active high
1: OC1 active low
CC1 channel configured as input:
CC1NP/CC1P bits select the active polarity of TI1FP1 and TI2FP1 for trigger or capture
operations.
00: non-inverted/rising edge
The circuit is sensitive to TIxFP1 rising edge (capture or trigger operations in reset, external
clock or trigger mode), TIxFP1 is not inverted (trigger operation in gated mode or encoder
mode).
01: inverted/falling edge
The circuit is sensitive to TIxFP1 falling edge (capture or trigger operations in reset, external
clock or trigger mode), TIxFP1 is inverted (trigger operation in gated mode or encoder
mode).
10: reserved, do not use this configuration.
11: non-inverted/both edges
The circuit is sensitive to both TIxFP1 rising and falling edges (capture or trigger operations
in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger operation in gated
mode). This configuration must not be used in encoder mode.
Note: On channels having a complementary output, this bit is preloaded. If the CCPC bit is
set in the TIMx_CR2 register then the CC1P active bit takes the new value from the
preloaded bits only when a Commutation event is generated.
Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits
in TIMx_BDTR register).

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Bit 0 CC1E: Capture/Compare 1 output enable
CC1 channel configured as output:
0: Off - OC1 is not active. OC1 level is then function of MOE, OSSI, OSSR, OIS1, OIS1N
and CC1NE bits.
1: On - OC1 signal is output on the corresponding output pin depending on MOE, OSSI,
OSSR, OIS1, OIS1N and CC1NE bits.
CC1 channel configured as input:
This bit determines if a capture of the counter value can actually be done into the input
capture/compare register 1 (TIMx_CCR1) or not.
0: Capture disabled.
1: Capture enabled.
Note: On channels having a complementary output, this bit is preloaded. If the CCPC bit is
set in the TIMx_CR2 register then the CC1E active bit takes the new value from the
preloaded bits only when a Commutation event is generated.

Table 46. Output control bits for complementary OCx and OCxN channels with
break feature
Output states(1)

Control bits
MOE
bit

1

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OSSI
bit

OSSR
bit

CCxE
bit

CCxNE
OCx output state
bit

0

0

0

Output Disabled (not driven by Output Disabled (not driven by the
the timer)
timer)
OCx=0, OCx_EN=0
OCxN=0, OCxN_EN=0

0

0

1

Output Disabled (not driven by
OCxREF + Polarity OCxN=OCxREF
the timer)
xor CCxNP, OCxN_EN=1
OCx=0, OCx_EN=0

0

1

0

OCxREF + Polarity
OCx=OCxREF xor CCxP,
OCx_EN=1

0

1

1

Complementary to OCREF (not
OCREF + Polarity + dead-time
OCREF) + Polarity + dead-time
OCx_EN=1
OCxN_EN=1

1

0

0

Output Disabled (not driven by Output Disabled (not driven by the
the timer)
timer)
OCx=CCxP, OCx_EN=0
OCxN=CCxNP, OCxN_EN=0

1

0

1

Off-State (output enabled with
inactive state)
OCx=CCxP, OCx_EN=1

OCxREF + Polarity
OCxN=OCxREF xor CCxNP,
OCxN_EN=1

1

1

0

OCxREF + Polarity
OCx=OCxREF xor CCxP,
OCx_EN=1

Off-State (output enabled with
inactive state)
OCxN=CCxNP, OCxN_EN=1

1

1

1

Complementary to OCREF (not
OCREF + Polarity + dead-time
OCREF) + Polarity + dead-time
OCx_EN=1
OCxN_EN=1

X

DocID025023 Rev 4

OCxN output state

Output Disabled (not driven by the
timer)
OCxN=0, OCxN_EN=0

RM0360

Advanced-control timers (TIM1)
Table 46. Output control bits for complementary OCx and OCxN channels with
break feature (continued)
Output states(1)

Control bits
MOE
bit

OSSI
bit

OSSR
bit

CCxE
bit

CCxNE
OCx output state
bit

0

0

0

0

0

1

0

1

0

0

1

1

1

0

0

1

0

1

1

1

0

1

1

1

0

X

OCxN output state

Output Disabled (not driven by Output Disabled (not driven by the
the timer)
timer)
OCx=CCxP, OCx_EN=0
OCxN=CCxNP, OCxN_EN=0
Output Disabled (not driven by the timer)
Asynchronously: OCx=CCxP, OCx_EN=0, OCxN=CCxNP,
OCxN_EN=0
Then if the clock is present: OCx=OISx and OCxN=OISxN after a
dead-time, assuming that OISx and OISxN do not correspond to OCX
and OCxN both in active state.
Output Disabled (not driven by Output Disabled (not driven by the
the timer)
timer)
OCx=CCxP, OCx_EN=0
OCxN=CCxNP, OCxN_EN=0
Off-State (output enabled with inactive state)
Asynchronously: OCx=CCxP, OCx_EN=1, OCxN=CCxNP,
OCxN_EN=1
Then if the clock is present: OCx=OISx and OCxN=OISxN after a
dead-time, assuming that OISx and OISxN do not correspond to OCX
and OCxN both in active state.

1. When both outputs of a channel are not used (CCxE = CCxNE = 0), the OISx, OISxN, CCxP and CCxNP bits must be kept
cleared.

Note:

The state of the external I/O pins connected to the complementary OCx and OCxN channels
depends on the OCx and OCxN channel state and the GPIO registers.

13.4.10

TIM1 counter (TIM1_CNT)
Address offset: 0x24
Reset value: 0x0000

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

CNT[15:0]
rw

rw

rw

Bits 15:0

13.4.11

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

8

7

6

5

4

3

2

1

0

rw

rw

rw

rw

rw

rw

rw

CNT[15:0]: Counter value

TIM1 prescaler (TIM1_PSC)
Address offset: 0x28
Reset value: 0x0000

15

14

13

12

11

10

9

PSC[15:0]
rw

rw

rw

rw

rw

rw

rw

rw

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Bits 15:0 PSC[15:0]: Prescaler value
The counter clock frequency (CK_CNT) is equal to fCK_PSC / (PSC[15:0] + 1).
PSC contains the value to be loaded in the active prescaler register at each update event
(including when the counter is cleared through UG bit of TIMx_EGR register or through trigger
controller when configured in “reset mode”).

13.4.12

TIM1 auto-reload register (TIM1_ARR)
Address offset: 0x2C
Reset value: 0xFFFF

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

rw

rw

rw

rw

rw

rw

rw

ARR[15:0]
rw

rw

rw

rw

rw

rw

rw

rw

rw

Bits 15:0 ARR[15:0]: Auto-reload value
ARR is the value to be loaded in the actual auto-reload register.
Refer to the Section 13.3.1: Time-base unit on page 223 for more details about ARR update
and behavior.
The counter is blocked while the auto-reload value is null.

13.4.13

TIM1 repetition counter register (TIM1_RCR)
Address offset: 0x30
Reset value: 0x0000

15

14

13

12

11

10

9

8

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

7

6

5

4

3

2

1

0

rw

rw

rw

REP[7:0]
rw

rw

rw

rw

rw

Bits 15:8 Reserved, must be kept at reset value.
Bits 7:0 REP[7:0]: Repetition counter value
These bits allow the user to set-up the update rate of the compare registers (i.e. periodic
transfers from preload to active registers) when preload registers are enable, as well as the
update interrupt generation rate, if this interrupt is enable.
Each time the REP_CNT related downcounter reaches zero, an update event is generated
and it restarts counting from REP value. As REP_CNT is reloaded with REP value only at the
repetition update event U_RC, any write to the TIMx_RCR register is not taken in account until
the next repetition update event.
It means in PWM mode (REP+1) corresponds to:
–
the number of PWM periods in edge-aligned mode
–
the number of half PWM period in center-aligned mode.

13.4.14

TIM1 capture/compare register 1 (TIM1_CCR1)
Address offset: 0x34
Reset value: 0x0000

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

rw

rw

rw

rw

rw

rw

rw

CCR1[15:0]
rw

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Advanced-control timers (TIM1)

Bits 15:0 CCR1[15:0]: Capture/Compare 1 value
If channel CC1 is configured as output:
CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value).
It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (bit
OC1PE). Else the preload value is copied in the active capture/compare 1 register when an
update event occurs.
The active capture/compare register contains the value to be compared to the counter
TIMx_CNT and signaled on OC1 output.

If channel CC1 is configured as input:
CCR1 is the counter value transferred by the last input capture 1 event (IC1).

13.4.15

TIM1 capture/compare register 2 (TIM1_CCR2)
Address offset: 0x38
Reset value: 0x0000

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

rw

rw

rw

rw

rw

rw

rw

CCR2[15:0]
rw

rw

rw

rw

rw

rw

rw

rw

rw

Bits 15:0 CCR2[15:0]: Capture/Compare 2 value
If channel CC2 is configured as output:
CCR2 is the value to be loaded in the actual capture/compare 2 register (preload value).
It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register (bit
OC2PE). Else the preload value is copied in the active capture/compare 2 register when an
update event occurs.
The active capture/compare register contains the value to be compared to the counter
TIMx_CNT and signalled on OC2 output.
If channel CC2 is configured as input:
CCR2 is the counter value transferred by the last input capture 2 event (IC2).

13.4.16

TIM1 capture/compare register 3 (TIM1_CCR3)
Address offset: 0x3C
Reset value: 0x0000

15

14

13

12

11

10

9

8

rw

rw

rw

rw

rw

rw

rw

7

6

5

4

3

2

1

0

rw

rw

rw

rw

rw

rw

rw

CCR3[15:0]
rw

rw

Bits 15:0 CCR3[15:0]: Capture/Compare value
If channel CC3 is configured as output:
CCR3 is the value to be loaded in the actual capture/compare 3 register (preload value).
It is loaded permanently if the preload feature is not selected in the TIMx_CCMR3 register (bit
OC3PE). Else the preload value is copied in the active capture/compare 3 register when an
update event occurs.
The active capture/compare register contains the value to be compared to the counter
TIMx_CNT and signalled on OC3 output.

If channel CC3 is configured as input:
CCR3 is the counter value transferred by the last input capture 3 event (IC3).

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13.4.17

RM0360

TIM1 capture/compare register 4 (TIM1_CCR4)
Address offset: 0x40
Reset value: 0x0000

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

rw

rw

rw

rw

rw

rw

rw

CCR4[15:0]
rw

rw

rw

rw

rw

rw

rw

rw

rw

Bits 15:0 CCR4[15:0]: Capture/Compare value
If channel CC4 is configured as output:
CCR4 is the value to be loaded in the actual capture/compare 4 register (preload value).
It is loaded permanently if the preload feature is not selected in the TIMx_CCMR4 register (bit
OC4PE). Else the preload value is copied in the active capture/compare 4 register when an
update event occurs.
The active capture/compare register contains the value to be compared to the counter
TIMx_CNT and signalled on OC4 output.
If channel CC4 is configured as input:
CCR4 is the counter value transferred by the last input capture 4 event (IC4).

13.4.18

TIM1 break and dead-time register (TIM1_BDTR)
Address offset: 0x44
Reset value: 0x0000

15

14

13

12

11

10

MOE

AOE

BKP

BKE

OSSR

OSSI

rw

rw

rw

rw

rw

rw

Note:

9

8

7

6

5

LOCK[1:0]
rw

rw

4

3

2

1

0

rw

rw

rw

DTG[7:0]
rw

rw

rw

rw

rw

As the bits AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] can be write-locked depending on
the LOCK configuration, it can be necessary to configure all of them during the first write
access to the TIMx_BDTR register.
Bit 15 MOE: Main output enable
This bit is cleared asynchronously by hardware as soon as the break input is active. It is set by
software or automatically depending on the AOE bit. It is acting only on the channels which are
configured in output.
0: OC and OCN outputs are disabled or forced to idle state.
1: OC and OCN outputs are enabled if their respective enable bits are set (CCxE, CCxNE in
TIMx_CCER register).
See OC/OCN enable description for more details (Section 13.4.9: TIM1 capture/compare
enable register (TIM1_CCER) on page 284).
Bit 14 AOE: Automatic output enable
0: MOE can be set only by software
1: MOE can be set by software or automatically at the next update event (if the break input is
not be active)
Note: This bit cannot be modified as long as LOCK level 1 has been programmed (LOCK bits
in TIMx_BDTR register).

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Advanced-control timers (TIM1)

Bit 13 BKP: Break polarity
0: Break input BRK is active low
1: Break input BRK is active high
Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits
in TIMx_BDTR register).
Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
Bit 12 BKE: Break enable
0: Break inputs (BRK and CCS clock failure event) disabled
1; Break inputs (BRK and CCS clock failure event) enabled
Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in
TIMx_BDTR register).
Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
Bit 11 OSSR: Off-state selection for Run mode
This bit is used when MOE=1 on channels having a complementary output which are
configured as outputs. OSSR is not implemented if no complementary output is implemented in
the timer.
See OC/OCN enable description for more details (Section 13.4.9: TIM1 capture/compare
enable register (TIM1_CCER) on page 284).
0: When inactive, OC/OCN outputs are disabled (OC/OCN enable output signal=0).
1: When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1
or CCxNE=1. Then, OC/OCN enable output signal=1
Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK
bits in TIMx_BDTR register).
Bit 10 OSSI: Off-state selection for Idle mode
This bit is used when MOE=0 on channels configured as outputs.
See OC/OCN enable description for more details (Section 13.4.9: TIM1 capture/compare
enable register (TIM1_CCER) on page 284).
0: When inactive, OC/OCN outputs are disabled (OC/OCN enable output signal=0).
1: When inactive, OC/OCN outputs are forced first with their idle level as soon as CCxE=1 or
CCxNE=1. OC/OCN enable output signal=1)
Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK
bits in TIMx_BDTR register).
Bits 9:8 LOCK[1:0]: Lock configuration
These bits offer a write protection against software errors.
00: LOCK OFF - No bit is write protected.
01: LOCK Level 1 = DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2
register and BKE/BKP/AOE bits in TIMx_BDTR register can no longer be written.
10: LOCK Level 2 = LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER
register, as long as the related channel is configured in output through the CCxS bits) as well
as OSSR and OSSI bits can no longer be written.
11: LOCK Level 3 = LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in
TIMx_CCMRx registers, as long as the related channel is configured in output through the
CCxS bits) can no longer be written.
Note: The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register
has been written, their content is frozen until the next reset.

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Advanced-control timers (TIM1)

RM0360

Bits 7:0 DTG[7:0]: Dead-time generator setup
This bit-field defines the duration of the dead-time inserted between the complementary
outputs. DT correspond to this duration.
DTG[7:5]=0xx => DT=DTG[7:0]x tdtg with tdtg=tDTS.
DTG[7:5]=10x => DT=(64+DTG[5:0])xtdtg with Tdtg=2xtDTS.
DTG[7:5]=110 => DT=(32+DTG[4:0])xtdtg with Tdtg=8xtDTS.
DTG[7:5]=111 => DT=(32+DTG[4:0])xtdtg with Tdtg=16xtDTS.
Example if TDTS=125 ns (8 MHz), dead-time possible values are:
0 to 15875 ns by 125 ns steps,
16 us to 31750 ns by 250 ns steps,
32 us to 63 us by 1 us steps,
64 us to 126 us by 2 us steps
Note: This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed
(LOCK bits in TIMx_BDTR register).

13.4.19

TIM1 DMA control register (TIM1_DCR)
Address offset: 0x48
Reset value: 0x0000

15

14

13

Res.

Res.

Res.

12

11

10

9

8

DBL[4:0]
rw

rw

rw

rw

7

6

5

Res.

Res.

Res.

rw

4

3

2

1

0

rw

rw

DBA[4:0]
rw

rw

rw

Bits 15:13 Reserved, must be kept at reset value.
Bits 12:8 DBL[4:0]: DMA burst length
This 5-bit vector defines the number of DMA transfers (the timer recognizes a burst transfer
when a read or a write access is done to the TIMx_DMAR address)
00000: 1 transfer
00001: 2 transfers
00010: 3 transfers
...
10001: 18 transfers
Bits 7:5 Reserved, must be kept at reset value.
Bits 4:0 DBA[4:0]: DMA base address
This 5-bit vector defines the base-address for DMA transfers (when read/write access are
done through the TIMx_DMAR address). DBA is defined as an offset starting from the address
of the TIMx_CR1 register.
Example:
00000: TIMx_CR1,
00001: TIMx_CR2,
00010: TIMx_SMCR,
...
Example: Let us consider the following transfer: DBL = 7 transfers and DBA = TIMx_CR1. In
this case the transfer is done to/from 7 registers starting from the TIMx_CR1 address.

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Advanced-control timers (TIM1)

13.4.20

TIM1 DMA address for full transfer (TIM1_DMAR)
Address offset: 0x4C
Reset value: 0x0000

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

rw

rw

rw

rw

rw

rw

rw

DMAB[15:0]
rw

rw

rw

rw

rw

rw

rw

rw

rw

Bits 15:0 DMAB[15:0]: DMA register for burst accesses
A read or write operation to the DMAR register accesses the register located at the address
(TIMx_CR1 address) + (DBA + DMA index) x 4
where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base
address configured in TIMx_DCR register, DMA index is automatically controlled by the DMA
transfer, and ranges from 0 to DBL (DBL configured in TIMx_DCR).

Example of how to use the DMA burst feature
In this example the timer DMA burst feature is used to update the contents of the CCRx
registers (x = 2, 3, 4) with the DMA transferring half words into the CCRx registers.
This is done in the following steps:
1.

Note:

Configure the corresponding DMA channel as follows:
–

DMA channel peripheral address is the DMAR register address

–

DMA channel memory address is the address of the buffer in the RAM containing
the data to be transferred by DMA into CCRx registers.

–

Number of data to transfer = 3 (See note below).

–

Circular mode disabled.

2.

Configure the DCR register by configuring the DBA and DBL bit fields as follows: 
DBL = 3 transfers, DBA = 0xE.

3.

Enable the TIMx update DMA request (set the UDE bit in the DIER register).

4.

Enable TIMx

5.

Enable the DMA channel

This example is for the case where every CCRx register to be updated once. If every CCRx
register is to be updated twice for example, the number of data to transfer should be 6. Let's
take the example of a buffer in the RAM containing data1, data2, data3, data4, data5 and
data6. The data is transferred to the CCRx registers as follows: on the first update DMA
request, data1 is transferred to CCR2, data2 is transferred to CCR3, data3 is transferred to
CCR4 and on the second update DMA request, data4 is transferred to CCR2, data5 is
transferred to CCR3 and data6 is transferred to CCR4.

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0x30

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TIM1_RCR

Reset value

DocID025023 Rev 4

1

1

1

1

1

1

1

1

Res.

Res.

Res.

Res.

Reset value

Res.

Reset value

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Reset value

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

0

0

0

0

0

0

OC4M
[2:0]

0
0

IC4F[3:0]

0
0
0
0
0

0

0

0

0

0

0

0

0
CC1E

0

TIE
COMIE
CC4IE
CC3IE
CC2IE
CC1IE
UIE

0
0
0

CC2S
[1:0]

CC4S
[1:0]

0

0

0

0

1

0

CC1IF
UIF

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

ARPE

DIR
OPM
URS
UDIS
CEN

0
0
0
0

MMS[2:0]
CCDS
CCUS
Res.
CCPC

0

0
0
0
0
0
0

0
0
OC1M
[2:0]

0

0

1

0

UG

CC2IF

0

CC1G

0

CC2G

TI1S

0

0

0
0

0

0

PSC[15:0]

ARR[15:0]

REP[7:0]

0

0

0

0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

0

0

0

0

0

TS[2:0]

0 0 0 0 0 0 0 0
IC2
CC2S
PSC
IC1F[3:0]
[1:0]
[1:0]
0 0 0 0 0 0 0 0

OC3M
[2:0]

0 0 0 0 0 0 0 0
IC4
CC4S
PSC
IC3F[3:0]
[1:0]
[1:0]
0 0 0 0 0 0 0 0

0

OCCS

OIS1

0

0
0
0
0
0
0

OC1FE

CC3IF

OIS1N

0

CC3G

CC4IF

OIS2

0

OC1PE

COMIF

OIS2N

0

0

COM

TIF
0

TG

MSM

OIS3

0

CC4G

BIF
0

BG

OIS3N

OIS4

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

0

0

OC3FE

BIE

0

CC1OF

0

Res.

0

CC2OF

0

Res.

0

CC3OF

0

Res.

0

CC4OF

0

Res.

UDE

0

Res.

0

0

0
Res.

0

ETF[3:0]

OC1CE

0

CC1DE

0

CC2DE

0

0

0

CC1P

0

0

CMS
[1:0]

OC3PE

IC2F[3:0]
OC2FE

0

CC3DE

0

0

0

CC1NE

0
0

CKD
[1:0]

OC3CE

0
0
OC2PE

0

CC4DE

0

COMDE

0

Res.

ECE

0

TDE

ETP

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

0

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

0

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

0

0

0

CC1NP

CC3P

0
OC2M
[2:0]

OC4FE

0
0
Res.

Reset value

CC2E

CC3NE

0
Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Reset value

OC4PE

OC2CE

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

0

ETPS
[1:0]

CC2P

CC3NP

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

0

CC2NE

0

CC4E

O24CE

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Reset value

CC3E

0

CC4P

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Reset value

CC2NP

0

Res.

Reset value
0

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Reset value

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

TIM1_ARR

Res.

TIM1_PSC

Res.

0x2C
TIM1_CNT

Res.

0x28
TIM1_CCER

Res.

0x24
Reset value
TIM1_CCMR1
Input capture
mode
Reset value
TIM1_CCMR2
Output compare
mode

Res.

Reset value
TIM1_CCMR1
Output compare
mode

Res.

0x20
Reset value
TIM1_CCMR2
Input capture
mode
Reset value
Res.

0x1C
TIM1_EGR

Res.

0x18

Res.

0x14
TIM1_SR

Res.

0x10
TIM1_DIER

Res.

0x0C
TIM1_SMCR

Res.

0x08
TIM1_CR2

Res.

0x04
TIM1_CR1

Res.

0x00

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0

Register

Res.

Offset

Res.

13.4.21

Res.

Advanced-control timers (TIM1)
RM0360

TIM1 register map
TIM1 registers are mapped as 16-bit addressable registers as described in the table below:
Table 47. TIM1 register map and reset values

0

SMS[2:0]

CC1S
[1:0]

0 0 0 0
IC1
CC1S
PSC
[1:0]
[1:0]
0 0 0 0
CC3S
[1:0]

0 0 0 0
IC3
CC3S
PSC
[1:0]
[1:0]
0 0 0 0

0
0
0
0
0
0
0
0
0

CNT[15:0]

RM0360

Advanced-control timers (TIM1)

Res.

0

0

0

0

0

0

Reset value

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

DT[7:0]

0

DBL[4:0]
0

0

0

0

0
Res.

0

0

LOCK
[1:0]

Res.

0

0

Res.

BKE

OSSR

0

BKP

0

AOE

0

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

0

Res.

0

0
Res.

TIM1_DMAR

0

Res.

0

Reset value
0x4C

0

MOE

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

TIM1_DCR

Res.

Reset value
0x48

0

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

TIM1_BDTR

0

CCR4[15:0]
0

Res.

Reset value
0x44

0

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

TIM1_CCR4

0

CCR3[15:0]
0

Res.

Reset value
0x40

0

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

TIM1_CCR3

0

CCR2[15:0]
0

Res.

Reset value
0x3C

0

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

TIM1_CCR2

Res.

0x38

0
Res.

Reset value

CCR1[15:0]

OSSI

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

TIM1_CCR1

Res.

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0

0x34

Register

Res.

Offset

Res.

Table 47. TIM1 register map and reset values (continued)

0

0

0

DBA[4:0]
0

0

0

0

0

0

0

0

0

0

DMAB[15:0]
0

0

0

0

0

0

0

0

0

0

0

Refer to Section 2.2.2 on page 37 for the register boundary addresses.

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General-purpose timers (TIM3)

RM0360

14

General-purpose timers (TIM3)

14.1

TIM3 introduction
The general-purpose timers consist of a 16-bit auto-reload counter driven by a
programmable prescaler.
They may be used for a variety of purposes, including measuring the pulse lengths of input
signals (input capture) or generating output waveforms (output compare and PWM).
Pulse lengths and waveform periods can be modulated from a few microseconds to several
milliseconds using the timer prescaler and the RCC clock controller prescalers.
The timers are completely independent, and do not share any resources. They can be
synchronized together as described in Section 14.3.15.

14.2

TIM3 main features
General-purpose TIMx timer features include:

296/779



16-bit (TIM3) up, down, up/down auto-reload counter.



16-bit programmable prescaler used to divide (also “on the fly”) the counter clock
frequency by any factor between 1 and 65535.



Up to 4 independent channels for:
–

Input capture

–

Output compare

–

PWM generation (Edge- and Center-aligned modes)

–

One-pulse mode output



Synchronization circuit to control the timer with external signals and to interconnect
several timers.



Interrupt/DMA generation on the following events:
–

Update: counter overflow/underflow, counter initialization (by software or
internal/external trigger)

–

Trigger event (counter start, stop, initialization or count by internal/external trigger)

–

Input capture

–

Output compare



Supports incremental (quadrature) encoder and hall-sensor circuitry for positioning
purposes



Trigger input for external clock or cycle-by-cycle current management

DocID025023 Rev 4

RM0360

General-purpose timers (TIM3)
Figure 88. General-purpose timer block diagram (TIM3)

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14.3

TIM3 functional description

14.3.1

Time-base unit
The main block of the programmable timer is a 16-bit/32-bit counter with its related autoreload register. The counter can count up but also down or both up and down. The counter
clock can be divided by a prescaler.
The counter, the auto-reload register and the prescaler register can be written or read by
software. This is true even when the counter is running.

DocID025023 Rev 4

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360

General-purpose timers (TIM3)

RM0360

The time-base unit includes:


Counter Register (TIMx_CNT)



Prescaler Register (TIMx_PSC)



Auto-Reload Register (TIMx_ARR)

The auto-reload register is preloaded. Writing to or reading from the auto-reload register
accesses the preload register. The content of the preload register are transferred into the
shadow register permanently or at each update event (UEV), depending on the auto-reload
preload enable bit (ARPE) in TIMx_CR1 register. The update event is sent when the counter
reaches the overflow (or underflow when downcounting) and if the UDIS bit equals 0 in the
TIMx_CR1 register. It can also be generated by software. The generation of the update
event is described in detail for each configuration.
The counter is clocked by the prescaler output CK_CNT, which is enabled only when the
counter enable bit (CEN) in TIMx_CR1 register is set (refer also to the slave mode controller
description to get more details on counter enabling).
Note that the actual counter enable signal CNT_EN is set 1 clock cycle after CEN.

Prescaler description
The prescaler can divide the counter clock frequency by any factor between 1 and 65536. It
is based on a 16-bit counter controlled through a 16-bit/32-bit register (in the TIMx_PSC
register). It can be changed on the fly as this control register is buffered. The new prescaler
ratio is taken into account at the next update event.
Figure 89 and Figure 90 give some examples of the counter behavior when the prescaler
ratio is changed on the fly:
Figure 89. Counter timing diagram with prescaler division change from 1 to 2

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Figure 90. Counter timing diagram with prescaler division change from 1 to 4

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14.3.2

Counter modes
Upcounting mode
In upcounting mode, the counter counts from 0 to the auto-reload value (content of the
TIMx_ARR register), then restarts from 0 and generates a counter overflow event.
An Update event can be generated at each counter overflow or by setting the UG bit in the
TIMx_EGR register (by software or by using the slave mode controller).
The UEV event can be disabled by software by setting the UDIS bit in TIMx_CR1 register.
This is to avoid updating the shadow registers while writing new values in the preload
registers. Then no update event occurs until the UDIS bit has been written to 0. However,
the counter restarts from 0, as well as the counter of the prescaler (but the prescale rate
does not change). In addition, if the URS bit (update request selection) in TIMx_CR1
register is set, setting the UG bit generates an update event UEV but without setting the UIF
flag (thus no interrupt or DMA request is sent). This is to avoid generating both update and
capture interrupts when clearing the counter on the capture event.
When an update event occurs, all the registers are updated and the update flag (UIF bit in
TIMx_SR register) is set (depending on the URS bit):


The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC
register)



The auto-reload shadow register is updated with the preload value (TIMx_ARR)

The following figures show some examples of the counter behavior for different clock
frequencies when TIMx_ARR=0x36.
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Figure 91. Counter timing diagram, internal clock divided by 1

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Figure 92. Counter timing diagram, internal clock divided by 2

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Figure 93. Counter timing diagram, internal clock divided by 4

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Figure 94. Counter timing diagram, internal clock divided by N

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Figure 95. Counter timing diagram, Update event when ARPE=0
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Figure 96. Counter timing diagram, Update event when ARPE=1
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Downcounting mode
In downcounting mode, the counter counts from the auto-reload value (content of the
TIMx_ARR register) down to 0, then restarts from the auto-reload value and generates a
counter underflow event.
An Update event can be generate at each counter underflow or by setting the UG bit in the
TIMx_EGR register (by software or by using the slave mode controller)
The UEV update event can be disabled by software by setting the UDIS bit in TIMx_CR1
register. This is to avoid updating the shadow registers while writing new values in the
preload registers. Then no update event occurs until UDIS bit has been written to 0.
However, the counter restarts from the current auto-reload value, whereas the counter of the
prescaler restarts from 0 (but the prescale rate doesn’t change).
In addition, if the URS bit (update request selection) in TIMx_CR1 register is set, setting the
UG bit generates an update event UEV but without setting the UIF flag (thus no interrupt or
DMA request is sent). This is to avoid generating both update and capture interrupts when
clearing the counter on the capture event.
When an update event occurs, all the registers are updated and the update flag (UIF bit in
TIMx_SR register) is set (depending on the URS bit):


The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC
register).



The auto-reload active register is updated with the preload value (content of the
TIMx_ARR register). Note that the auto-reload is updated before the counter is
reloaded, so that the next period is the expected one.

The following figures show some examples of the counter behavior for different clock
frequencies when TIMx_ARR=0x36.
Figure 97. Counter timing diagram, internal clock divided by 1

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Figure 98. Counter timing diagram, internal clock divided by 2

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Figure 99. Counter timing diagram, internal clock divided by 4

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Figure 100. Counter timing diagram, internal clock divided by N

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Figure 101. Counter timing diagram, Update event when repetition counter is not
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Center-aligned mode (up/down counting)
In center-aligned mode, the counter counts from 0 to the auto-reload value (content of the
TIMx_ARR register) – 1, generates a counter overflow event, then counts from the autoreload value down to 1 and generates a counter underflow event. Then it restarts counting
from 0.
Center-aligned mode is active when the CMS bits in TIMx_CR1 register are not equal to
'00'. The Output compare interrupt flag of channels configured in output is set when: the
counter counts down (Center aligned mode 1, CMS = “01”), the counter counts up (Center
aligned mode 2, CMS = “10”) the counter counts up and down (Center aligned mode 3,
CMS = “11”).
In this mode, the direction bit (DIR from TIMx_CR1 register) cannot be written. It is updated
by hardware and gives the current direction of the counter.
The update event can be generated at each counter overflow and at each counter underflow
or by setting the UG bit in the TIMx_EGR register (by software or by using the slave mode
controller) also generates an update event. In this case, the counter restarts counting from
0, as well as the counter of the prescaler.
The UEV update event can be disabled by software by setting the UDIS bit in TIMx_CR1
register. This is to avoid updating the shadow registers while writing new values in the
preload registers. Then no update event occurs until the UDIS bit has been written to 0.
However, the counter continues counting up and down, based on the current auto-reload
value.
In addition, if the URS bit (update request selection) in TIMx_CR1 register is set, setting the
UG bit generates an update event UEV but without setting the UIF flag (thus no interrupt or
DMA request is sent). This is to avoid generating both update and capture interrupt when
clearing the counter on the capture event.
When an update event occurs, all the registers are updated and the update flag (UIF bit in
TIMx_SR register) is set (depending on the URS bit):


The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC
register).



The auto-reload active register is updated with the preload value (content of the
TIMx_ARR register). Note that if the update source is a counter overflow, the autoreload is updated before the counter is reloaded, so that the next period is the expected
one (the counter is loaded with the new value).

The following figures show some examples of the counter behavior for different clock
frequencies.

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Figure 102. Counter timing diagram, internal clock divided by 1, TIMx_ARR=0x6
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1. Here, center-aligned mode 1 is used (for more details refer to Section 14.4.1: TIM3 control register 1
(TIM3_CR1) on page 338).

Figure 103. Counter timing diagram, internal clock divided by 2

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Figure 104. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36

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1. Center-aligned mode 2 or 3 is used with an UIF on overflow.

Figure 105. Counter timing diagram, internal clock divided by N

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Figure 106. Counter timing diagram, Update event with ARPE=1 (counter underflow)
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Figure 107. Counter timing diagram, Update event with ARPE=1 (counter overflow)
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14.3.3

RM0360

Clock sources
The counter clock can be provided by the following clock sources:


Internal clock (CK_INT)



External clock mode1: external input pin (TIx)



External clock mode2: external trigger input (ETR)



Internal trigger inputs (ITRx): using one timer as prescaler for another timer, for
example, you can configure Timer 1 to act as a prescaler for Timer 2. Refer to : Using
one timer as prescaler for another on page 332 for more details.

Internal clock source (CK_INT)
If the slave mode controller is disabled (SMS=000 in the TIMx_SMCR register), then the
CEN, DIR (in the TIMx_CR1 register) and UG bits (in the TIMx_EGR register) are actual
control bits and can be changed only by software (except UG which remains cleared
automatically). As soon as the CEN bit is written to 1, the prescaler is clocked by the internal
clock CK_INT.
Figure 108 shows the behavior of the control circuit and the upcounter in normal mode,
without prescaler.
Figure 108. Control circuit in normal mode, internal clock divided by 1

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External clock source mode 1
This mode is selected when SMS=111 in the TIMx_SMCR register. The counter can count at
each rising or falling edge on a selected input.

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Figure 109. TI2 external clock connection example
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For example, to configure the upcounter to count in response to a rising edge on the TI2
input, use the following procedure:

Note:

1.

Configure channel 2 to detect rising edges on the TI2 input by writing CC2S= ‘01 in the
TIMx_CCMR1 register.

2.

Configure the input filter duration by writing the IC2F[3:0] bits in the TIMx_CCMR1
register (if no filter is needed, keep IC2F=0000).

The capture prescaler is not used for triggering, so you don’t need to configure it.
3.

Select rising edge polarity by writing CC2P=0 and CC2NP=0 in the TIMx_CCER
register.

4.

Configure the timer in external clock mode 1 by writing SMS=111 in the TIMx_SMCR
register.

5.

Select TI2 as the input source by writing TS=110 in the TIMx_SMCR register.

6.

Enable the counter by writing CEN=1 in the TIMx_CR1 register.

For code example refer to the Appendix section A.8.2: Up counter on each 2 ETR rising
edges code example.
When a rising edge occurs on TI2, the counter counts once and the TIF flag is set.
The delay between the rising edge on TI2 and the actual clock of the counter is due to the
resynchronization circuit on TI2 input.

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Figure 110. Control circuit in external clock mode 1

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External clock source mode 2
This mode is selected by writing ECE=1 in the TIMx_SMCR register.
The counter can count at each rising or falling edge on the external trigger input ETR.
The Figure 111 gives an overview of the external trigger input block.
Figure 111. External trigger input block

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For example, to configure the upcounter to count each 2 rising edges on ETR, use the
following procedure:

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1.

As no filter is needed in this example, write ETF[3:0]=0000 in the TIMx_SMCR register.

2.

Set the prescaler by writing ETPS[1:0]=01 in the TIMx_SMCR register

3.

Select rising edge detection on the ETR pin by writing ETP=0 in the TIMx_SMCR
register

4.

Enable external clock mode 2 by writing ECE=1 in the TIMx_SMCR register.

5.

Enable the counter by writing CEN=1 in the TIMx_CR1 register.

The counter counts once each 2 ETR rising edges.
The delay between the rising edge on ETR and the actual clock of the counter is due to the
resynchronization circuit on the ETRP signal.
Figure 112. Control circuit in external clock mode 2

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14.3.4

Capture/compare channels
Each Capture/Compare channel is built around a capture/compare register (including a
shadow register), a input stage for capture (with digital filter, multiplexing and prescaler) and
an output stage (with comparator and output control).
The following figure gives an overview of one Capture/Compare channel.
The input stage samples the corresponding TIx input to generate a filtered signal TIxF.
Then, an edge detector with polarity selection generates a signal (TIxFPx) which can be
used as trigger input by the slave mode controller or as the capture command. It is
prescaled before the capture register (ICxPS).

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Figure 113. Capture/compare channel (example: channel 1 input stage)

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The output stage generates an intermediate waveform which is then used for reference:
OCxRef (active high). The polarity acts at the end of the chain.
Figure 114. Capture/compare channel 1 main circuit

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Figure 115. Output stage of capture/compare channel (channel 1)
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The capture/compare block is made of one preload register and one shadow register. Write
and read always access the preload register.
In capture mode, captures are actually done in the shadow register, which is copied into the
preload register.
In compare mode, the content of the preload register is copied into the shadow register
which is compared to the counter.

14.3.5

Input capture mode
In Input capture mode, the Capture/Compare Registers (TIMx_CCRx) are used to latch the
value of the counter after a transition detected by the corresponding ICx signal. When a
capture occurs, the corresponding CCXIF flag (TIMx_SR register) is set and an interrupt or
a DMA request can be sent if they are enabled. If a capture occurs while the CCxIF flag was
already high, then the over-capture flag CCxOF (TIMx_SR register) is set. CCxIF can be
cleared by software by writing it to 0 or by reading the captured data stored in the
TIMx_CCRx register. CCxOF is cleared when you write it to 0.
The following example shows how to capture the counter value in TIMx_CCR1 when TI1
input rises. To do this, use the following procedure:




Select the active input: TIMx_CCR1 must be linked to the TI1 input, so write the CC1S
bits to 01 in the TIMx_CCMR1 register. As soon as CC1S becomes different from 00,
the channel is configured in input and the TIMx_CCR1 register becomes read-only.
Program the input filter duration you need with respect to the signal you connect to the
timer (when the input is one of the TIx (ICxF bits in the TIMx_CCMRx register). Let’s
imagine that, when toggling, the input signal is not stable during at must 5 internal clock
cycles. We must program a filter duration longer than these 5 clock cycles. We can
validate a transition on TI1 when 8 consecutive samples with the new level have been

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





RM0360

detected (sampled at fDTS frequency). Then write IC1F bits to 0011 in the
TIMx_CCMR1 register.
Select the edge of the active transition on the TI1 channel by writing the CC1P and
CC1NP bits to 0 in the TIMx_CCER register (rising edge in this case).
Program the input prescaler. In our example, we wish the capture to be performed at
each valid transition, so the prescaler is disabled (write IC1PS bits to 00 in the
TIMx_CCMR1 register).
Enable capture from the counter into the capture register by setting the CC1E bit in the
TIMx_CCER register.
If needed, enable the related interrupt request by setting the CC1IE bit in the
TIMx_DIER register, and/or the DMA request by setting the CC1DE bit in the
TIMx_DIER register.

For code example refer to the Appendix section A.8.3: Input capture configuration code
example.
When an input capture occurs:





The TIMx_CCR1 register gets the value of the counter on the active transition.
CC1IF flag is set (interrupt flag). CC1OF is also set if at least two consecutive captures
occurred whereas the flag was not cleared.
An interrupt is generated depending on the CC1IE bit.
A DMA request is generated depending on the CC1DE bit.

For code example refer to the Appendix section A.8.4: Input capture data management
code example.
In order to handle the overcapture, it is recommended to read the data before the
overcapture flag. This is to avoid missing an overcapture which could happen after reading
the flag and before reading the data.
Note:

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IC interrupt and/or DMA requests can be generated by software by setting the
corresponding CCxG bit in the TIMx_EGR register.

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14.3.6

General-purpose timers (TIM3)

PWM input mode
This mode is a particular case of input capture mode. The procedure is the same except:


Two ICx signals are mapped on the same TIx input.



These 2 ICx signals are active on edges with opposite polarity.



One of the two TIxFP signals is selected as trigger input and the slave mode controller
is configured in reset mode.

For example, you can measure the period (in TIMx_CCR1 register) and the duty cycle (in
TIMx_CCR2 register) of the PWM applied on TI1 using the following procedure (depending
on CK_INT frequency and prescaler value):


Select the active input for TIMx_CCR1: write the CC1S bits to 01 in the TIMx_CCMR1
register (TI1 selected).



Select the active polarity for TI1FP1 (used both for capture in TIMx_CCR1 and counter
clear): write the CC1P to ‘0’ and the CC1NP bit to ‘0’ (active on rising edge).



Select the active input for TIMx_CCR2: write the CC2S bits to 10 in the TIMx_CCMR1
register (TI1 selected).



Select the active polarity for TI1FP2 (used for capture in TIMx_CCR2): write the CC2P
bit to ‘1’ and the CC2NP bit to ’0’(active on falling edge).



Select the valid trigger input: write the TS bits to 101 in the TIMx_SMCR register
(TI1FP1 selected).



Configure the slave mode controller in reset mode: write the SMS bits to 100 in the
TIMx_SMCR register.



Enable the captures: write the CC1E and CC2E bits to ‘1 in the TIMx_CCER register.

For code example refer to the Appendix section A.8.5: PWM input configuration code
example.
Figure 116. PWM input mode timing
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14.3.7

RM0360

Forced output mode
In output mode (CCxS bits = 00 in the TIMx_CCMRx register), each output compare signal
(OCxREF and then OCx) can be forced to active or inactive level directly by software,
independently of any comparison between the output compare register and the counter.
To force an output compare signal (ocxref/OCx) to its active level, you just need to write 101
in the OCxM bits in the corresponding TIMx_CCMRx register. Thus ocxref is forced high
(OCxREF is always active high) and OCx get opposite value to CCxP polarity bit.
e.g.: CCxP=0 (OCx active high) => OCx is forced to high level.
ocxref signal can be forced low by writing the OCxM bits to 100 in the TIMx_CCMRx
register.
Anyway, the comparison between the TIMx_CCRx shadow register and the counter is still
performed and allows the flag to be set. Interrupt and DMA requests can be sent
accordingly. This is described in the Output Compare Mode section.

14.3.8

Output compare mode
This function is used to control an output waveform or indicating when a period of time has
elapsed.
When a match is found between the capture/compare register and the counter, the output
compare function:


Assigns the corresponding output pin to a programmable value defined by the output
compare mode (OCxM bits in the TIMx_CCMRx register) and the output polarity (CCxP
bit in the TIMx_CCER register). The output pin can keep its level (OCXM=000), be set
active (OCxM=001), be set inactive (OCxM=010) or can toggle (OCxM=011) on match.



Sets a flag in the interrupt status register (CCxIF bit in the TIMx_SR register).



Generates an interrupt if the corresponding interrupt mask is set (CCXIE bit in the
TIMx_DIER register).



Sends a DMA request if the corresponding enable bit is set (CCxDE bit in the
TIMx_DIER register, CCDS bit in the TIMx_CR2 register for the DMA request
selection).

The TIMx_CCRx registers can be programmed with or without preload registers using the
OCxPE bit in the TIMx_CCMRx register.
In output compare mode, the update event UEV has no effect on ocxref and OCx output.
The timing resolution is one count of the counter. Output compare mode can also be used to
output a single pulse (in One-pulse mode).
Procedure:

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1.

Select the counter clock (internal, external, prescaler).

2.

Write the desired data in the TIMx_ARR and TIMx_CCRx registers.

3.

Set the CCxIE and/or CCxDE bits if an interrupt and/or a DMA request is to be
generated.

4.

Select the output mode. For example, you must write OCxM=011, OCxPE=0, CCxP=0
and CCxE=1 to toggle OCx output pin when CNT matches CCRx, CCRx preload is not
used, OCx is enabled and active high.

5.

Enable the counter by setting the CEN bit in the TIMx_CR1 register.

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General-purpose timers (TIM3)
For code example refer to the Appendix section A.8.7: Output compare configuration code
example.
The TIMx_CCRx register can be updated at any time by software to control the output
waveform, provided that the preload register is not enabled (OCxPE=0, else TIMx_CCRx
shadow register is updated only at the next update event UEV). An example is given in
Figure 117.
Figure 117. Output compare mode, toggle on OC1
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14.3.9

PWM mode
Pulse width modulation mode allows you to generate a signal with a frequency determined
by the value of the TIMx_ARR register and a duty cycle determined by the value of the
TIMx_CCRx register.
The PWM mode can be selected independently on each channel (one PWM per OCx
output) by writing 110 (PWM mode 1) or ‘111 (PWM mode 2) in the OCxM bits in the
TIMx_CCMRx register. You must enable the corresponding preload register by setting the
OCxPE bit in the TIMx_CCMRx register, and eventually the auto-reload preload register (in
upcounting or center-aligned modes) by setting the ARPE bit in the TIMx_CR1 register.
As the preload registers are transferred to the shadow registers only when an update event
occurs, before starting the counter, you have to initialize all the registers by setting the UG
bit in the TIMx_EGR register.
OCx polarity is software programmable using the CCxP bit in the TIMx_CCER register. It
can be programmed as active high or active low. OCx output is enabled by the CCxE bit in
the TIMx_CCER register. Refer to the TIMx_CCERx register description for more details.
In PWM mode (1 or 2), TIMx_CNT and TIMx_CCRx are always compared to determine
whether TIMx_CCRx ≤ TIMx_CNT or TIMx_CNT ≤ TIMx_CCRx (depending on the direction
of the counter). However, to comply with the OCREF_CLR functionality (OCREF can be

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cleared by an external event through the ETR signal until the next PWM period), the
OCREF signal is asserted only:


When the result of the comparison changes, or



When the output compare mode (OCxM bits in TIMx_CCMRx register) switches from
the “frozen” configuration (no comparison, OCxM=‘000) to one of the PWM modes
(OCxM=‘110 or ‘111).

This forces the PWM by software while the timer is running.
The timer is able to generate PWM in edge-aligned mode or center-aligned mode
depending on the CMS bits in the TIMx_CR1 register.

PWM edge-aligned mode
Upcounting configuration
Upcounting is active when the DIR bit in the TIMx_CR1 register is low. Refer to the Section :
Upcounting mode on page 299.
In the following example, we consider PWM mode 1. The reference PWM signal OCxREF is
high as long as TIMx_CNT TIMx_CCRx else
it becomes high. If the compare value in TIMx_CCRx is greater than the auto-reload value in
TIMx_ARR, then ocxref is held at ‘1. 0% PWM is not possible in this mode.

PWM center-aligned mode
Center-aligned mode is active when the CMS bits in TIMx_CR1 register are different from
‘00 (all the remaining configurations having the same effect on the ocxref/OCx signals). The
compare flag is set when the counter counts up, when it counts down or both when it counts
up and down depending on the CMS bits configuration. The direction bit (DIR) in the
TIMx_CR1 register is updated by hardware and must not be changed by software. Refer to
the Center-aligned mode (up/down counting) on page 306.
Figure 119 shows some center-aligned PWM waveforms in an example where:




TIMx_ARR=8,
PWM mode is the PWM mode 1,
The flag is set when the counter counts down corresponding to the center-aligned
mode 1 selected for CMS=01 in TIMx_CR1 register.

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Figure 119. Center-aligned PWM waveforms (ARR=8)
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When starting in center-aligned mode, the current up-down configuration is used. It
means that the counter counts up or down depending on the value written in the DIR bit
in the TIMx_CR1 register. Moreover, the DIR and CMS bits must not be changed at the
same time by the software.
Writing to the counter while running in center-aligned mode is not recommended as it
can lead to unexpected results. In particular:
–
The direction is not updated if you write a value in the counter that is greater than
the auto-reload value (TIMx_CNT>TIMx_ARR). For example, if the counter was
counting up, it continues to count up.
–
The direction is updated if you write 0 or write the TIMx_ARR value in the counter
but no Update Event UEV is generated.
The safest way to use center-aligned mode is to generate an update by software
(setting the UG bit in the TIMx_EGR register) just before starting the counter and not to
write the counter while it is running.

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One-pulse mode
One-pulse mode (OPM) is a particular case of the previous modes. It allows the counter to
be started in response to a stimulus and to generate a pulse with a programmable length
after a programmable delay.
Starting the counter can be controlled through the slave mode controller. Generating the
waveform can be done in output compare mode or PWM mode. You select One-pulse mode
by setting the OPM bit in the TIMx_CR1 register. This makes the counter stop automatically
at the next update event UEV.
A pulse can be correctly generated only if the compare value is different from the counter
initial value. Before starting (when the timer is waiting for the trigger), the configuration must
be:


In upcounting: CNTCCRx.
Figure 120. Example of one-pulse mode

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For example you may want to generate a positive pulse on OC1 with a length of tPULSE and
after a delay of tDELAY as soon as a positive edge is detected on the TI2 input pin.
Use TI2FP2 as trigger 1:


Map TI2FP2 on TI2 by writing CC2S=01 in the TIMx_CCMR1 register.



TI2FP2 must detect a rising edge, write CC2P=0 and CC2NP=’0’ in the TIMx_CCER
register.



Configure TI2FP2 as trigger for the slave mode controller (TRGI) by writing TS=110 in
the TIMx_SMCR register.



TI2FP2 is used to start the counter by writing SMS to ‘110 in the TIMx_SMCR register
(trigger mode).

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The OPM waveform is defined by writing the compare registers (taking into account the
clock frequency and the counter prescaler).


The tDELAY is defined by the value written in the TIMx_CCR1 register.



The tPULSE is defined by the difference between the auto-reload value and the compare
value (TIMx_ARR - TIMx_CCR1 + 1).



Let’s say you want to build a waveform with a transition from ‘0 to ‘1 when a compare
match occurs and a transition from ‘1 to ‘0 when the counter reaches the auto-reload
value. To do this you enable PWM mode 2 by writing OC1M=111 in the TIMx_CCMR1
register. You can optionally enable the preload registers by writing OC1PE=1 in the
TIMx_CCMR1 register and ARPE in the TIMx_CR1 register. In this case you have to
write the compare value in the TIMx_CCR1 register, the auto-reload value in the
TIMx_ARR register, generate an update by setting the UG bit and wait for external
trigger event on TI2. CC1P is written to ‘0 in this example.

In our example, the DIR and CMS bits in the TIMx_CR1 register should be low.
For code example refer to the Appendix section A.8.16: One-Pulse mode code example.
You only want 1 pulse (Single mode), so you write '1 in the OPM bit in the TIMx_CR1
register to stop the counter at the next update event (when the counter rolls over from the
auto-reload value back to 0). When OPM bit in the TIMx_CR1 register is set to '0', so the
Repetitive Mode is selected.

Particular case: OCx fast enable
In One-pulse mode, the edge detection on TIx input set the CEN bit which enables the
counter. Then the comparison between the counter and the compare value makes the
output toggle. But several clock cycles are needed for these operations and it limits the
minimum delay tDELAY min we can get.
If you want to output a waveform with the minimum delay, you can set the OCxFE bit in the
TIMx_CCMRx register. Then OCxRef (and OCx) are forced in response to the stimulus,
without taking in account the comparison. Its new level is the same as if a compare match
had occurred. OCxFE acts only if the channel is configured in PWM1 or PWM2 mode.
For code example refer to the part of code, conditioned by PULSE_WITHOUT_DELAY > 0
in the Appendix section A.8.16: One-Pulse mode code example.

14.3.11

Clearing the OCxREF signal on an external event
1.

The external trigger prescaler should be kept off: bits ETPS[1:0] in the TIMx_SMCR
register are cleared to 00.

2.

The external clock mode 2 must be disabled: bit ECE in the TIM1_SMCR register is
cleared to 0.

3.

The external trigger polarity (ETP) and the external trigger filter (ETF) can be
configured according to the application’s needs.

For code example refer to the Appendix section A.8.10: ETR configuration to clear OCxREF
code example.
Figure 121 shows the behavior of the OCxREF signal when the ETRF input becomes high,
for both values of the OCxCE enable bit. In this example, the timer TIMx is programmed in
PWM mode.

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General-purpose timers (TIM3)
Figure 121. Clearing TIMx OCxREF

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overflow.

14.3.12

Encoder interface mode
To select Encoder Interface mode write SMS=‘001 in the TIMx_SMCR register if the counter
is counting on TI2 edges only, SMS=010 if it is counting on TI1 edges only and SMS=011 if
it is counting on both TI1 and TI2 edges.
Select the TI1 and TI2 polarity by programming the CC1P and CC2P bits in the TIMx_CCER
register. CC1NP and CC2NP must be kept cleared. When needed, you can program the
input filter as well.
The two inputs TI1 and TI2 are used to interface to an incremental encoder. Refer to
Table 48. The counter is clocked by each valid transition on TI1FP1 or TI2FP2 (TI1 and TI2
after input filter and polarity selection, TI1FP1=TI1 if not filtered and not inverted,
TI2FP2=TI2 if not filtered and not inverted) assuming that it is enabled (CEN bit in
TIMx_CR1 register written to ‘1). The sequence of transitions of the two inputs is evaluated
and generates count pulses as well as the direction signal. Depending on the sequence the
counter counts up or down, the DIR bit in the TIMx_CR1 register is modified by hardware
accordingly. The DIR bit is calculated at each transition on any input (TI1 or TI2), whatever
the counter is counting on TI1 only, TI2 only or both TI1 and TI2.
Encoder interface mode acts simply as an external clock with direction selection. This
means that the counter just counts continuously between 0 and the auto-reload value in the
TIMx_ARR register (0 to ARR or ARR down to 0 depending on the direction). So you must
configure TIMx_ARR before starting. In the same way, the capture, compare, prescaler,
trigger output features continue to work as normal.
In this mode, the counter is modified automatically following the speed and the direction of
the incremental encoder and its content, therefore, always represents the encoder’s

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General-purpose timers (TIM3)

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position. The count direction correspond to the rotation direction of the connected sensor.
The table summarizes the possible combinations, assuming TI1 and TI2 don’t switch at the
same time.
Table 48. Counting direction versus encoder signals
Level on opposite
signal (TI1FP1 for
TI2, TI2FP2 for TI1)

Rising

Falling

Rising

Falling

Counting on
TI1 only

High

Down

Up

No Count

No Count

Low

Up

Down

No Count

No Count

Counting on
TI2 only

High

No Count

No Count

Up

Down

Low

No Count

No Count

Down

Up

Counting on
TI1 and TI2

High

Down

Up

Up

Down

Low

Up

Down

Down

Up

Active edge

TI1FP1 signal

TI2FP2 signal

An external incremental encoder can be connected directly to the MCU without external
interface logic. However, comparators are normally be used to convert the encoder’s
differential outputs to digital signals. This greatly increases noise immunity. The third
encoder output which indicate the mechanical zero position, may be connected to an
external interrupt input and trigger a counter reset.
Figure 122 gives an example of counter operation, showing count signal generation and
direction control. It also shows how input jitter is compensated where both edges are
selected. This might occur if the sensor is positioned near to one of the switching points. For
this example we assume that the configuration is the following:


CC1S= 01 (TIMx_CCMR1 register, TI1FP1 mapped on TI1)



CC2S= 01 (TIMx_CCMR2 register, TI2FP2 mapped on TI2)



CC1P=0, CC1NP = ‘0’ (TIMx_CCER register, TI1FP1 noninverted, TI1FP1=TI1)



CC2P=0, CC2NP = ‘0’ (TIMx_CCER register, TI2FP2 noninverted, TI2FP2=TI2)



SMS= 011 (TIMx_SMCR register, both inputs are active on both rising and falling
edges)



CEN= 1 (TIMx_CR1 register, Counter is enabled)

For code example refer to the Appendix section A.8.10: ETR configuration to clear OCxREF
code example.

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General-purpose timers (TIM3)
Figure 122. Example of counter operation in encoder interface mode
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Figure 123 gives an example of counter behavior when TI1FP1 polarity is inverted (same
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Figure 123. Example of encoder interface mode with TI1FP1 polarity inverted
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The timer, when configured in Encoder Interface mode provides information on the sensor’s
current position. You can obtain dynamic information (speed, acceleration, deceleration) by
measuring the period between two encoder events using a second timer configured in
capture mode. The output of the encoder which indicates the mechanical zero can be used
for this purpose. Depending on the time between two events, the counter can also be read
at regular times. You can do this by latching the counter value into a third input capture
register if available (then the capture signal must be periodic and can be generated by
another timer). when available, it is also possible to read its value through a DMA request
generated by a Real-Time clock.

14.3.13

Timer input XOR function
The TI1S bit in the TIM1_CR2 register, allows the input filter of channel 1 to be connected to
the output of a XOR gate, combining the three input pins TIMx_CH1 to TIMx_CH3.
The XOR output can be used with all the timer input functions such as trigger or input
capture.

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An example of this feature used to interface Hall sensors is given in Section 13.3.18 on
page 262.

14.3.14

Timers and external trigger synchronization
The TIMx Timers can be synchronized with an external trigger in several modes: Reset
mode, Gated mode and Trigger mode.

Slave mode: Reset mode
The counter and its prescaler can be reinitialized in response to an event on a trigger input.
Moreover, if the URS bit from the TIMx_CR1 register is low, an update event UEV is
generated. Then all the preloaded registers (TIMx_ARR, TIMx_CCRx) are updated.
In the following example, the upcounter is cleared in response to a rising edge on TI1 input:


Configure the channel 1 to detect rising edges on TI1. Configure the input filter duration
(in this example, we don’t need any filter, so we keep IC1F=0000). The capture
prescaler is not used for triggering, so you don’t need to configure it. The CC1S bits
select the input capture source only, CC1S = 01 in the TIMx_CCMR1 register. Write
CC1P=0 and CC1NP=0 in TIMx_CCER register to validate the polarity (and detect
rising edges only).



Configure the timer in reset mode by writing SMS=100 in TIMx_SMCR register. Select
TI1 as the input source by writing TS=101 in TIMx_SMCR register.



Start the counter by writing CEN=1 in the TIMx_CR1 register.

For code example refer to the Appendix section A.8.12: Reset mode code example.
The counter starts counting on the internal clock, then behaves normally until TI1 rising
edge. When TI1 rises, the counter is cleared and restarts from 0. In the meantime, the
trigger flag is set (TIF bit in the TIMx_SR register) and an interrupt request, or a DMA
request can be sent if enabled (depending on the TIE and TDE bits in TIMx_DIER register).
The following figure shows this behavior when the auto-reload register TIMx_ARR=0x36.
The delay between the rising edge on TI1 and the actual reset of the counter is due to the
resynchronization circuit on TI1 input.
Figure 124. Control circuit in reset mode

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General-purpose timers (TIM3)

Slave mode: Gated mode
The counter can be enabled depending on the level of a selected input.
In the following example, the upcounter counts only when TI1 input is low:


Configure the channel 1 to detect low levels on TI1. Configure the input filter duration
(in this example, we don’t need any filter, so we keep IC1F=0000). The capture
prescaler is not used for triggering, so you don’t need to configure it. The CC1S bits
select the input capture source only, CC1S=01 in TIMx_CCMR1 register. Write
CC1P=1 and CC1NP=0 in TIMx_CCER register to validate the polarity (and detect low
level only).



Configure the timer in gated mode by writing SMS=101 in TIMx_SMCR register. Select
TI1 as the input source by writing TS=101 in TIMx_SMCR register.



Enable the counter by writing CEN=1 in the TIMx_CR1 register (in gated mode, the
counter doesn’t start if CEN=0, whatever is the trigger input level).

For code example refer to the Appendix section A.8.13: Gated mode code example.
The counter starts counting on the internal clock as long as TI1 is low and stops as soon as
TI1 becomes high. The TIF flag in the TIMx_SR register is set both when the counter starts
or stops.
The delay between the rising edge on TI1 and the actual stop of the counter is due to the
resynchronization circuit on TI1 input.
Figure 125. Control circuit in gated mode

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1. The configuration “CCxP=CCxNP=1” (detection of both rising and falling edges) does not have any effect
in gated mode because gated mode acts on a level and not on an edge.

Slave mode: Trigger mode
The counter can start in response to an event on a selected input.
In the following example, the upcounter starts in response to a rising edge on TI2 input:


Configure the channel 2 to detect rising edges on TI2. Configure the input filter duration
(in this example, we don’t need any filter, so we keep IC2F=0000). The capture
prescaler is not used for triggering, so you don’t need to configure it. CC2S bits are
selecting the input capture source only, CC2S=01 in TIMx_CCMR1 register. Write

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CC2P=1 and CC2NP=0 in TIMx_CCER register to validate the polarity (and detect low
level only).


Configure the timer in trigger mode by writing SMS=110 in TIMx_SMCR register. Select
TI2 as the input source by writing TS=110 in TIMx_SMCR register.

For code example refer to the Appendix section A.8.14: Trigger mode code example.
When a rising edge occurs on TI2, the counter starts counting on the internal clock and the
TIF flag is set.
The delay between the rising edge on TI2 and the actual start of the counter is due to the
resynchronization circuit on TI2 input.
Figure 126. Control circuit in trigger mode
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069

Slave mode: External Clock mode 2 + trigger mode
The external clock mode 2 can be used in addition to another slave mode (except external
clock mode 1 and encoder mode). In this case, the ETR signal is used as external clock
input, and another input can be selected as trigger input when operating in reset mode,
gated mode or trigger mode. It is recommended not to select ETR as TRGI through the TS
bits of TIMx_SMCR register.
In the following example, the upcounter is incremented at each rising edge of the ETR
signal as soon as a rising edge of TI1 occurs:

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General-purpose timers (TIM3)
1.

2.

3.

Configure the external trigger input circuit by programming the TIMx_SMCR register as
follows:
–

ETF = 0000: no filter

–

ETPS=00: prescaler disabled

–

ETP=0: detection of rising edges on ETR and ECE=1 to enable the external clock
mode 2.

Configure the channel 1 as follows, to detect rising edges on TI:
–

IC1F=0000: no filter.

–

The capture prescaler is not used for triggering and does not need to be
configured.

–

CC1S=01in TIMx_CCMR1 register to select only the input capture source

–

CC1P=0 and CC1NP=0 in TIMx_CCER register to validate the polarity (and detect
rising edge only).

Configure the timer in trigger mode by writing SMS=110 in TIMx_SMCR register. Select
TI1 as the input source by writing TS=101 in TIMx_SMCR register.

For code example refer to the Appendix section A.8.15: External clock mode 2 + trigger
mode code example.
A rising edge on TI1 enables the counter and sets the TIF flag. The counter then counts on
ETR rising edges.
The delay between the rising edge of the ETR signal and the actual reset of the counter is
due to the resynchronization circuit on ETRP input.
Figure 127. Control circuit in external clock mode 2 + trigger mode

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069

14.3.15

Timer synchronization
The TIMx timers are linked together internally for timer synchronization or chaining. When
one Timer is configured in Master Mode, it can reset, start, stop or clock the counter of
another Timer configured in Slave Mode.

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Figure 128: Master/Slave timer example presents an overview of the trigger selection and
the master mode selection blocks.

Using one timer as prescaler for another
Figure 128. Master/Slave timer example

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For example, you can configure Timer 1 to act as a prescaler for Timer 3. Refer to
Figure 128. To do this:


Configure Timer 1 in master mode so that it outputs a periodic trigger signal on each
update event UEV. If you write MMS=010 in the TIM1_CR2 register, a rising edge is
output on TRGO1 each time an update event is generated.



To connect the TRGO1 output of Timer 1 to Timer 3, Timer 3 must be configured in
slave mode using ITR1 as internal trigger. You select this through the TS bits in the
TIM3_SMCR register (writing TS=000).



Then the Timer2's slave mode controller should be configured in external clock mode 1
(write SMS=111 in the TIM3_SMCR register). This causes Timer 3 to be clocked by the
rising edge of the periodic Timer 1 trigger signal (which correspond to the timer 1
counter overflow).



Finally both timers must be enabled by setting their respective CEN bits within their
respective TIMx_CR1 registers. Make sure to enable Timer2 before enabling Timer1.

For code example refer to the Appendix section A.8.17: Timer prescaling another timer code
example.
Note:

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If OCx is selected on Timer 1 as trigger output (MMS=1xx), its rising edge is used to clock
the counter of timer 3.

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RM0360

General-purpose timers (TIM3)

Using one timer to enable another timer
In this example, we control the enable of Timer 3 with the output compare 1 of Timer 1.
Refer to Figure 128 for connections. Timer 3 counts on the divided internal clock only when
OC1REF of Timer 1 is high. Both counter clock frequencies are divided by 3 by the
prescaler compared to CK_INT (fCK_CNT = fCK_INT/3).


Configure Timer 1 master mode to send its Output Compare 1 Reference (OC1REF)
signal as trigger output (MMS=100 in the TIM1_CR2 register).



Configure the Timer 1 OC1REF waveform (TIM1_CCMR1 register).



Configure Timer 3 to get the input trigger from Timer 1 (TS=000 in the TIM3_SMCR
register).



Configure Timer 3 in gated mode (SMS=101 in TIM3_SMCR register).



Enable Timer 3 by writing ‘1 in the CEN bit (TIM3_CR1 register).



Start Timer 1 by writing ‘1 in the CEN bit (TIM1_CR1 register).

For code example refer to the Appendix section A.8.18: Timer enabling another timer code
example.
Note:

The counter 3 clock is not synchronized with counter 1, this mode only affects the Timer 3
counter enable signal.
Figure 129. Gating timer 3 with OC1REF of timer 1
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069

In the example in Figure 129, the Timer 3 counter and prescaler are not initialized before
being started. So they start counting from their current value. It is possible to start from a
given value by resetting both timers before starting Timer 1. You can then write any value
you want in the timer counters. The timers can easily be reset by software using the UG bit
in the TIMx_EGR registers.
In the next example, we synchronize Timer 1 and Timer 3. Timer 1 is the master and starts
from 0. Timer 3 is the slave and starts from 0xE7. The prescaler ratio is the same for both

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timers. Timer 3 stops when Timer 1 is disabled by writing ‘0 to the CEN bit in the TIM1_CR1
register:


Configure Timer 1 master mode to send its Counter Enable signal (CNT_EN) as a
trigger output (MMS=001 in the TIM1_CR2 register).



Configure the Timer 1 OC1REF waveform (TIM1_CCMR1 register).



Configure Timer 3 to get the input trigger from Timer 1 (TS=000 in the TIM3_SMCR
register).



Configure Timer 3 in gated mode (SMS=101 in TIM3_SMCR register).



Reset Timer 1 by writing ‘1 in UG bit (TIM1_EGR register).



Reset Timer 3 by writing ‘1 in UG bit (TIM3_EGR register).



Initialize Timer 3 to 0xE7 by writing ‘0xE7’ in the timer 3 counter (TIM3_CNTL).



Enable Timer 3 by writing ‘1 in the CEN bit (TIM3_CR1 register).



Start Timer 1 by writing ‘1 in the CEN bit (TIM1_CR1 register).



Stop Timer 1 by writing ‘0 in the CEN bit (TIM1_CR1 register).

For code example refer to the Appendix section A.8.19: Master and slave synchronization
code example.
Figure 130. Gating timer 3 with Enable of timer 1
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RM0360

General-purpose timers (TIM3)

Using one timer to start another timer
In this example, we set the enable of Timer 3 with the update event of Timer 1. Refer to
Figure 128 for connections. Timer 3 starts counting from its current value (which can be
nonzero) on the divided internal clock as soon as the update event is generated by Timer 1.
When Timer 3 receives the trigger signal its CEN bit is automatically set and the counter
counts until we write ‘0 to the CEN bit in the TIM3_CR1 register. Both counter clock
frequencies are divided by 3 by the prescaler compared to CK_INT (fCK_CNT = fCK_INT/3).


Configure Timer 1 master mode to send its Update Event (UEV) as trigger output
(MMS=010 in the TIM1_CR2 register).



Configure the Timer 1 period (TIM1_ARR registers).



Configure Timer 3 to get the input trigger from Timer 1 (TS=000 in the TIM3_SMCR
register).



Configure Timer 3 in trigger mode (SMS=110 in TIM3_SMCR register).



Start Timer 1 by writing ‘1 in the CEN bit (TIM1_CR1 register).
Figure 131. Triggering timer 3 with update of timer 1
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069

As in the previous example, you can initialize both counters before starting counting.
Figure 132 shows the behavior with the same configuration as in Figure 131 but in trigger
mode instead of gated mode (SMS=110 in the TIM3_SMCR register).

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General-purpose timers (TIM3)

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Figure 132. Triggering timer 3 with Enable of timer 1
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Starting 2 timers synchronously in response to an external trigger
In this example, we set the enable of timer 1 when its TI1 input rises, and the enable of
Timer 3 with the enable of Timer 1. Refer to Figure 128 for connections. To ensure the
counters are aligned, Timer 1 must be configured in Master/Slave mode (slave with respect
to TI1, master with respect to Timer 3):


Configure Timer 1 master mode to send its Enable as trigger output (MMS=001 in the
TIM1_CR2 register).



Configure Timer 1 slave mode to get the input trigger from TI1 (TS=100 in the
TIM1_SMCR register).



Configure Timer 1 in trigger mode (SMS=110 in the TIM1_SMCR register).



Configure the Timer 1 in Master/Slave mode by writing MSM=1 (TIM1_SMCR register).



Configure Timer 3 to get the input trigger from Timer 1 (TS=000 in the TIM3_SMCR
register).



Configure Timer 3 in trigger mode (SMS=110 in the TIM3_SMCR register).

For code example refer to the Appendix section A.8.20: Two timers synchronized by an
external trigger code example.
When a rising edge occurs on TI1 (Timer 1), both counters starts counting synchronously on
the internal clock and both TIF flags are set.
Note:

336/779

In this example both timers are initialized before starting (by setting their respective UG
bits). Both counters starts from 0, but you can easily insert an offset between them by
writing any of the counter registers (TIMx_CNT). You can see that the master/slave mode
insert a delay between CNT_EN and CK_PSC on timer 1.

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General-purpose timers (TIM3)
Figure 133. Triggering timer 1 and 3 with timer 1 TI1 input
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14.3.16

Debug mode
When the microcontroller enters debug mode (ARM® Cortex®-M0 core - halted), the TIMx
counter either continues to work normally or stops, depending on DBG_TIMx_STOP
configuration bit in DBGMCU module.

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14.4

RM0360

TIM3 registers
Refer to Section 1.1 on page 33 for a list of abbreviations used in register descriptions.
The peripheral registers can be accessed by half-words (16-bit) or words (32-bit).

14.4.1

TIM3 control register 1 (TIM3_CR1)
Address offset: 0x00
Reset value: 0x0000

15

14

13

12

11

10

Res.

Res.

Res.

Res.

Res.

Res.

9

8

CKD[1:0]
rw

rw

7

6

ARPE
rw

5
CMS

rw

rw

4

3

2

1

0

DIR

OPM

URS

UDIS

CEN

rw

rw

rw

rw

rw

Bits 15:10 Reserved, always read as 0.
Bits 9:8 CKD: Clock division
This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and
sampling clock used by the digital filters (ETR, TIx),
00: tDTS = tCK_INT
01: tDTS = 2 × tCK_INT
10: tDTS = 4 × tCK_INT
11: Reserved
Bit 7 ARPE: Auto-reload preload enable
0: TIMx_ARR register is not buffered
1: TIMx_ARR register is buffered
Bits 6:5 CMS: Center-aligned mode selection
00: Edge-aligned mode. The counter counts up or down depending on the direction bit
(DIR).
01: Center-aligned mode 1. The counter counts up and down alternatively. Output compare
interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set
only when the counter is counting down.
10: Center-aligned mode 2. The counter counts up and down alternatively. Output compare
interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set
only when the counter is counting up.
11: Center-aligned mode 3. The counter counts up and down alternatively. Output compare
interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set
both when the counter is counting up or down.
Note: It is not allowed to switch from edge-aligned mode to center-aligned mode as long as
the counter is enabled (CEN=1)
Bit 4 DIR: Direction
0: Counter used as upcounter
1: Counter used as downcounter
Note: This bit is read only when the timer is configured in Center-aligned mode or Encoder
mode.
Bit 3 OPM: One-pulse mode
0: Counter is not stopped at update event
1: Counter stops counting at the next update event (clearing the bit CEN)

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Bit 2 URS: Update request source
This bit is set and cleared by software to select the UEV event sources.
0: Any of the following events generate an update interrupt or DMA request if enabled.
These events can be:
–
Counter overflow/underflow
–
Setting the UG bit
–
Update generation through the slave mode controller
1: Only counter overflow/underflow generates an update interrupt or DMA request if
enabled.
Bit 1 UDIS: Update disable
This bit is set and cleared by software to enable/disable UEV event generation.
0: UEV enabled. The Update (UEV) event is generated by one of the following events:
–
Counter overflow/underflow
–
Setting the UG bit
–
Update generation through the slave mode controller
Buffered registers are then loaded with their preload values.
1: UEV disabled. The Update event is not generated, shadow registers keep their value
(ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is
set or if a hardware reset is received from the slave mode controller.
Bit 0 CEN: Counter enable
0: Counter disabled
1: Counter enabled
Note: External clock, gated mode and encoder mode can work only if the CEN bit has been
previously set by software. However trigger mode can set the CEN bit automatically by
hardware.
CEN is cleared automatically in one-pulse mode, when an update event occurs.

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14.4.2

RM0360

TIM3 control register 2 (TIM3_CR2)
Address offset: 0x04
Reset value: 0x0000

15

14

13

12

11

10

9

8

7

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

TI1S
rw

6

5

4

MMS[2:0]
rw

rw

rw

3

2

1

0

CCDS

Res.

Res.

Res.

rw

Bits 15:8 Reserved, must be kept at reset value.
Bit 7 TI1S: TI1 selection
0: The TIMx_CH1 pin is connected to TI1 input
1: The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination)
See also Section 13.3.18: Interfacing with Hall sensors on page 262
Bits 6:4 MMS: Master mode selection
These bits allow to select the information to be sent in master mode to slave timers for
synchronization (TRGO). The combination is as follows:
000: Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO). If the
reset is generated by the trigger input (slave mode controller configured in reset mode) then
the signal on TRGO is delayed compared to the actual reset.
001: Enable - the Counter enable signal, CNT_EN, is used as trigger output (TRGO). It is
useful to start several timers at the same time or to control a window in which a slave timer is
enabled. The Counter Enable signal is generated by a logic OR between CEN control bit
and the trigger input when configured in gated mode.
When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO,
except if the master/slave mode is selected (see the MSM bit description in TIMx_SMCR
register).
010: Update - The update event is selected as trigger output (TRGO). For instance a master
timer can then be used as a prescaler for a slave timer.
011: Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be
set (even if it was already high), as soon as a capture or a compare match occurred.
(TRGO)
100: Compare - OC1REF signal is used as trigger output (TRGO)
101: Compare - OC2REF signal is used as trigger output (TRGO)
110: Compare - OC3REF signal is used as trigger output (TRGO)
111: Compare - OC4REF signal is used as trigger output (TRGO)
Bit 3 CCDS: Capture/compare DMA selection
0: CCx DMA request sent when CCx event occurs
1: CCx DMA requests sent when update event occurs
Bits 2:0 Reserved, always read as 0.

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14.4.3

TIM3 slave mode control register (TIM3_SMCR)
Address offset: 0x08
Reset value: 0x0000

15

14

ETP

ECE

rw

rw

13

12

11

ETPS[1:0]
rw

rw

10

9

8

ETF[3:0]
rw

rw

7

6

MSM

rw

rw

rw

5

4

TS[2:0]
rw

rw

3

2

OCCS
rw

rw

1

0

SMS[2:0]
rw

rw

rw

Bit 15 ETP: External trigger polarity
This bit selects whether ETR or ETR is used for trigger operations
0: ETR is noninverted, active at high level or rising edge
1: ETR is inverted, active at low level or falling edge
Bit 14 ECE: External clock enable
This bit enables External clock mode 2.
0: External clock mode 2 disabled
1: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF
signal.
1: Setting the ECE bit has the same effect as selecting external clock mode 1 with TRGI
connected to ETRF (SMS=111 and TS=111).
2: It is possible to simultaneously use external clock mode 2 with the following slave modes:
reset mode, gated mode and trigger mode. Nevertheless, TRGI must not be connected to
ETRF in this case (TS bits must not be 111).
3: If external clock mode 1 and external clock mode 2 are enabled at the same time, the
external clock input is ETRF.
Bits 13:12 ETPS: External trigger prescaler
External trigger signal ETRP frequency must be at most 1/4 of CK_INT frequency. A prescaler
can be enabled to reduce ETRP frequency. It is useful when inputting fast external clocks.
00: Prescaler OFF
01: ETRP frequency divided by 2
10: ETRP frequency divided by 4
11: ETRP frequency divided by 8

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Bits 11:8 ETF[3:0]: External trigger filter
This bit-field defines the frequency used to sample ETRP signal and the length of the digital
filter applied to ETRP. The digital filter is made of an event counter in which N consecutive
events are needed to validate a transition on the output:
0000: No filter, sampling is done at fDTS
0001: fSAMPLING = fCK_INT, N = 2
0010: fSAMPLING = fCK_INT, N = 4
0011: fSAMPLING = fCK_INT, N = 8
0100: fSAMPLING = fDTS / 2, N = 6 
0101: fSAMPLING = fDTS / 2, N = 8
0110: fSAMPLING = fDTS / 4, N = 6
0111: fSAMPLING = fDTS / 4, N = 8 
1000: fSAMPLING = fDTS / 8, N = 6
1001: fSAMPLING = fDTS / 8, N = 8
1010: fSAMPLING = fDTS / 16, N = 5
1011: fSAMPLING = fDTS / 16, N = 6
1100: fSAMPLING = fDTS / 16, N = 8
1101: fSAMPLING = fDTS / 32, N = 5
1110: fSAMPLING = fDTS / 32, N = 6
1111: fSAMPLING = fDTS / 32, N = 8
Note: Care must be taken that fDTS is replaced in the formula by CK_INT when ETF[3:0] = 1,
2 or 3.
Bit 7 MSM: Master/Slave mode
0: No action
1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect
synchronization between the current timer and its slaves (through TRGO). It is useful if we
want to synchronize several timers on a single external event.
Bits 6:4 TS: Trigger selection
This bit-field selects the trigger input to be used to synchronize the counter.
000: Internal Trigger 0 (ITR0). 
001: Internal Trigger 1 (ITR1). 
010: Internal Trigger 2 (ITR2). 
011: Internal Trigger 3 (ITR3). 
100: TI1 Edge Detector (TI1F_ED)
101: Filtered Timer Input 1 (TI1FP1)
110: Filtered Timer Input 2 (TI2FP2)
111: External Trigger input (ETRF)
See Table 49: TIM3 internal trigger connection on page 343 for more details on ITRx
meaning for each Timer.
Note: These bits must be changed only when they are not used (e.g. when SMS=000) to
avoid wrong edge detections at the transition.
Bit 3 OCCS: OCREF clear selection.
This bit is used to select the OCREF clear source.
0:OCREF_CLR_INT is connected to the OCREF_CLR input
1: OCREF_CLR_INT is connected to ETRF

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General-purpose timers (TIM3)

Bits 2:0 SMS: Slave mode selection
When external signals are selected the active edge of the trigger signal (TRGI) is linked to the
polarity selected on the external input (see Input Control register and Control Register
description.
000: Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal
clock.
001: Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2
level.
010: Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1
level.
011: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges
depending on the level of the other input.
100: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter
and generates an update of the registers.
101: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The
counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of
the counter are controlled.
110: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not
reset). Only the start of the counter is controlled.
111: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.
Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=100).
Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode
checks the level of the trigger signal.
Note: The clock of the slave timer must be enabled prior to receive events from the master
timer, and must not be changed on-the-fly while triggers are received from the master
timer.

Table 49. TIM3 internal trigger connection

14.4.4

Slave TIM

ITR0 (TS = 000)

ITR2 (TS = 010)

ITR3 (TS = 011)

TIM3

TIM1

TIM15

TIM14

TIM3 DMA/Interrupt enable register (TIM3_DIER)
Address offset: 0x0C
Reset value: 0x0000

15

14

13

Res.

TDE

Res.

rw

12

11

10

9

CC4DE CC3DE CC2DE CC1DE
rw

rw

rw

rw

8

7

6

5

4

3

2

1

0

UDE

Res.

TIE

Res.

CC4IE

CC3IE

CC2IE

CC1IE

UIE

rw

rw

rw

rw

rw

rw

rw

Bit 15 Reserved, must be kept at reset value.
Bit 14 TDE: Trigger DMA request enable
0: Trigger DMA request disabled.
1: Trigger DMA request enabled.
Bit 13 Reserved, always read as 0
Bit 12 CC4DE: Capture/Compare 4 DMA request enable
0: CC4 DMA request disabled.
1: CC4 DMA request enabled.

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Bit 11 CC3DE: Capture/Compare 3 DMA request enable
0: CC3 DMA request disabled.
1: CC3 DMA request enabled.
Bit 10 CC2DE: Capture/Compare 2 DMA request enable
0: CC2 DMA request disabled.
1: CC2 DMA request enabled.
Bit 9 CC1DE: Capture/Compare 1 DMA request enable
0: CC1 DMA request disabled.
1: CC1 DMA request enabled.
Bit 8 UDE: Update DMA request enable
0: Update DMA request disabled.
1: Update DMA request enabled.
Bit 7 Reserved, must be kept at reset value.
Bit 6 TIE: Trigger interrupt enable
0: Trigger interrupt disabled.
1: Trigger interrupt enabled.
Bit 5 Reserved, must be kept at reset value.
Bit 4 CC4IE: Capture/Compare 4 interrupt enable
0: CC4 interrupt disabled.
1: CC4 interrupt enabled.
Bit 3 CC3IE: Capture/Compare 3 interrupt enable
0: CC3 interrupt disabled
1: CC3 interrupt enabled
Bit 2 CC2IE: Capture/Compare 2 interrupt enable
0: CC2 interrupt disabled
1: CC2 interrupt enabled
Bit 1 CC1IE: Capture/Compare 1 interrupt enable
0: CC1 interrupt disabled
1: CC1 interrupt enabled
Bit 0 UIE: Update interrupt enable
0: Update interrupt disabled
1: Update interrupt enabled

14.4.5

TIM3 status register (TIM3_SR)
Address offset: 0x10
Reset value: 0x0000

15

14

13

Res.

Res.

Res.

12

rc_w0

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11

10

9

CC4OF CC3OF CC2OF CC1OF
rc_w0

rc_w0

rc_w0

8

7

6

5

4

3

2

1

0

Res.

Res.

TIF

Res.

CC4IF

CC3IF

CC2IF

CC1IF

UIF

rc_w0

rc_w0

rc_w0

rc_w0

rc_w0

rc_w0

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General-purpose timers (TIM3)

Bit 15:13 Reserved, always read as 0.
Bit 12 CC4OF: Capture/Compare 4 overcapture flag
Refer to CC1OF description
Bit 11 CC3OF: Capture/Compare 3 overcapture flag
Refer to CC1OF description
Bit 10 CC2OF: Capture/compare 2 overcapture flag
Refer to CC1OF description
Bit 9 CC1OF: Capture/Compare 1 overcapture flag
This flag is set by hardware only when the corresponding channel is configured in input capture
mode. It is cleared by software by writing it to ‘0.
0: No overcapture has been detected
1: The counter value has been captured in TIMx_CCR1 register while CC1IF flag was
already set
Bits 8:7 Reserved, always read as 0.
Bit 6 TIF: Trigger interrupt flag
This flag is set by hardware on trigger event (active edge detected on TRGI input when the
slave mode controller is enabled in all modes but gated mode. It is set when the counter starts
or stops when gated mode is selected. It is cleared by software.
0: No trigger event occurred
1: Trigger interrupt pending
Bit 5 Reserved, always read as 0.
Bit 4 CC4IF: Capture/Compare 4 interrupt flag
Refer to CC1IF description
Bit 3 CC3IF: Capture/Compare 3 interrupt flag
Refer to CC1IF description

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Bit 2 CC2IF: Capture/Compare 2 interrupt flag
Refer to CC1IF description
Bit 1 CC1IF: Capture/compare 1 interrupt flag
If channel CC1 is configured as output:
This flag is set by hardware when the counter matches the compare value, with some
exception in center-aligned mode (refer to the CMS bits in the TIMx_CR1 register description).
It is cleared by software.
0: No match
1: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register.
When the contents of TIMx_CCR1 are greater than the contents of TIMx_ARR, the CC1IF bit
goes high on the counter overflow (in upcounting and up/down-counting modes) or underflow
(in downcounting mode)
If channel CC1 is configured as input:
This bit is set by hardware on a capture. It is cleared by software or by reading the
TIMx_CCR1 register.
0: No input capture occurred
1: The counter value has been captured in TIMx_CCR1 register (An edge has been detected
on IC1 which matches the selected polarity)
Bit 0 UIF: Update interrupt flag
This bit is set by hardware on an update event. It is cleared by software.
0: No update occurred.
1: Update interrupt pending.
This bit is set by hardware when the registers are updated:
At overflow or underflow and if UDIS=0 in the TIMx_CR1 register.
When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and
UDIS=0 in the TIMx_CR1 register.
When CNT is reinitialized by a trigger event (refer to the synchro control register description), if
URS=0 and UDIS=0 in the TIMx_CR1 register.

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General-purpose timers (TIM3)

14.4.6

TIM3 event generation register (TIM3_EGR)
Address offset: 0x14
Reset value: 0x0000

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

TG

Res.

CC4G

CC3G

CC2G

CC1G

UG

w

w

w

w

w

w

Bits 15:7 Reserved, must be kept at reset value.
Bit 6 TG: Trigger generation
This bit is set by software in order to generate an event, it is automatically cleared by hardware.
0: No action
1: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if
enabled.
Bit 5 Reserved, must be kept at reset value.
Bit 4 CC4G: Capture/compare 4 generation
Refer to CC1G description
Bit 3 CC3G: Capture/compare 3 generation
Refer to CC1G description
Bit 2 CC2G: Capture/compare 2 generation
Refer to CC1G description
Bit 1 CC1G: Capture/compare 1 generation
This bit is set by software in order to generate an event, it is automatically cleared by hardware.
0: No action
1: A capture/compare event is generated on channel 1:
If channel CC1 is configured as output:
CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled.
If channel CC1 is configured as input:
The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set,
the corresponding interrupt or DMA request is sent if enabled. The CC1OF flag is set if the
CC1IF flag was already high.
Bit 0 UG: Update generation
This bit can be set by software, it is automatically cleared by hardware.
0: No action
1: Re-initialize the counter and generates an update of the registers. Note that the prescaler
counter is cleared too (anyway the prescaler ratio is not affected). The counter is cleared if
the center-aligned mode is selected or if DIR=0 (upcounting), else it takes the auto-reload
value (TIMx_ARR) if DIR=1 (downcounting).

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14.4.7

RM0360

TIM3 capture/compare mode register 1 (TIM3_CCMR1)
Address offset: 0x18
Reset value: 0x0000
The channels can be used in input (capture mode) or in output (compare mode). The
direction of a channel is defined by configuring the corresponding CCxS bits. All the other
bits of this register have a different function in input and in output mode. For a given bit,
OCxx describes its function when the channel is configured in output, ICxx describes its
function when the channel is configured in input. So you must take care that the same bit
can have a different meaning for the input stage and for the output stage.

15

14

OC2CE

13

12

OC2M[2:0]
IC2F[3:0]

rw

rw

rw

11

10

OC2PE OC2FE
IC2PSC[1:0]
rw

rw

rw

9

8

CC2S[1:0]
rw

7

6

OC1CE

rw

5

4

OC1M[2:0]
IC1F[3:0]

rw

rw

rw

3

2

OC1PE OC1FE
IC1PSC[1:0]
rw

rw

rw

1

0

CC1S[1:0]
rw

rw

Output compare mode
Bit 15 OC2CE: Output compare 2 clear enable
Bits 14:12 OC2M[2:0]: Output compare 2 mode
Bit 11 OC2PE: Output compare 2 preload enable
Bit 10 OC2FE: Output compare 2 fast enable
Bits 9:8 CC2S[1:0]: Capture/Compare 2 selection
This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC2 channel is configured as output
01: CC2 channel is configured as input, IC2 is mapped on TI2
10: CC2 channel is configured as input, IC2 is mapped on TI1
11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if
an internal trigger input is selected through the TS bit (TIMx_SMCR register)
Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in TIMx_CCER).
Bit 7 OC1CE: Output compare 1 clear enable
OC1CE: Output Compare 1 Clear Enable
0: OC1Ref is not affected by the ETRF input
1: OC1Ref is cleared as soon as a High level is detected on ETRF input

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General-purpose timers (TIM3)

Bits 6:4 OC1M: Output compare 1 mode
These bits define the behavior of the output reference signal OC1REF from which OC1 and
OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on
CC1P and CC1NP bits.
000: Frozen - The comparison between the output compare register TIMx_CCR1 and the
counter TIMx_CNT has no effect on the outputs.(this mode is used to generate a timing base).
001: Set channel 1 to active level on match. OC1REF signal is forced high when the counter
TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).
010: Set channel 1 to inactive level on match. OC1REF signal is forced low when the
counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).
011: Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1.
100: Force inactive level - OC1REF is forced low.
101: Force active level - OC1REF is forced high.
110: PWM mode 1 - In upcounting, channel 1 is active as long as TIMx_CNTTIMx_CCR1 else active (OC1REF=1).
111: PWM mode 2 - In upcounting, channel 1 is inactive as long as TIMx_CNTTIMx_CCR1 else
inactive.
Note: 1: These bits can not be modified as long as LOCK level 3 has been programmed
(LOCK bits in TIMx_BDTR register) and CC1S=00 (the channel is configured in
output).
2: In PWM mode 1 or 2, the OCREF level changes only when the result of the
comparison changes or when the output compare mode switches from “frozen” mode
to “PWM” mode.
Bit 3 OC1PE: Output compare 1 preload enable
0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the
new value is taken in account immediately.
1: Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload
register. TIMx_CCR1 preload value is loaded in the active register at each update event.
Note: 1: These bits can not be modified as long as LOCK level 3 has been programmed
(LOCK bits in TIMx_BDTR register) and CC1S=00 (the channel is configured in
output).
2: The PWM mode can be used without validating the preload register only in onepulse mode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed.
Bit 2 OC1FE: Output compare 1 fast enable
This bit is used to accelerate the effect of an event on the trigger in input on the CC output.
0: CC1 behaves normally depending on counter and CCR1 values even when the trigger is
ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is
5 clock cycles.
1: An active edge on the trigger input acts like a compare match on CC1 output. Then, OC
is set to the compare level independently from the result of the comparison. Delay to sample
the trigger input and to activate CC1 output is reduced to 3 clock cycles. OCFE acts only if
the channel is configured in PWM1 or PWM2 mode.
Bits 1:0 CC1S: Capture/Compare 1 selection
This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC1 channel is configured as output.
01: CC1 channel is configured as input, IC1 is mapped on TI1.
10: CC1 channel is configured as input, IC1 is mapped on TI2.
11: CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if
an internal trigger input is selected through TS bit (TIMx_SMCR register)
Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER).

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Input capture mode
Bits 15:12 IC2F: Input capture 2 filter
Bits 11:10 IC2PSC[1:0]: Input capture 2 prescaler
Bits 9:8 CC2S: Capture/compare 2 selection
This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC2 channel is configured as output.
01: CC2 channel is configured as input, IC2 is mapped on TI2.
10: CC2 channel is configured as input, IC2 is mapped on TI1.
11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if
an internal trigger input is selected through TS bit (TIMx_SMCR register)
Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in TIMx_CCER).
Bits 7:4 IC1F: Input capture 1 filter
This bit-field defines the frequency used to sample TI1 input and the length of the digital filter
applied to TI1. The digital filter is made of an event counter in which N consecutive events are
needed to validate a transition on the output:
0000: No filter, sampling is done at fDTS
0001: fSAMPLING = fCK_INT, N = 2
0010: fSAMPLING = fCK_INT, N = 4
0011: fSAMPLING = fCK_INT, N = 8
0100: fSAMPLING = fDTS / 2, N = 6 
0101: fSAMPLING = fDTS / 2, N = 8
0110: fSAMPLING = fDTS / 4, N = 6
0111: fSAMPLING = fDTS / 4, N = 8 
1000: fSAMPLING = fDTS / 8, N = 6
1001: fSAMPLING = fDTS / 8, N = 8
1010: fSAMPLING = fDTS / 16, N = 5
1011: fSAMPLING = fDTS / 16, N = 6
1100: fSAMPLING = fDTS / 16, N = 8
1101: fSAMPLING = fDTS / 32, N = 5
1110: fSAMPLING = fDTS / 32, N = 6
1111: fSAMPLING = fDTS / 32, N = 8
Note: Care must be taken that fDTS is replaced in the formula by CK_INT when ICxF[3:0] = 1,
2 or 3.
Bits 3:2 IC1PSC: Input capture 1 prescaler
This bit-field defines the ratio of the prescaler acting on CC1 input (IC1).
The prescaler is reset as soon as CC1E=0 (TIMx_CCER register).
00: no prescaler, capture is done each time an edge is detected on the capture input
01: capture is done once every 2 events
10: capture is done once every 4 events
11: capture is done once every 8 events
Bits 1:0 CC1S: Capture/Compare 1 selection
This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC1 channel is configured as output
01: CC1 channel is configured as input, IC1 is mapped on TI1
10: CC1 channel is configured as input, IC1 is mapped on TI2
11: CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if
an internal trigger input is selected through TS bit (TIMx_SMCR register)
Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER).

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General-purpose timers (TIM3)

14.4.8

TIM3 capture/compare mode register 2 (TIM3_CCMR2)
Address offset: 0x1C
Reset value: 0x0000
Refer to the above CCMR1 register description.

15

14

OC4CE

13

12

OC4M[2:0]
IC4F[3:0]

rw

rw

rw

11

10

OC4PE OC4FE
IC4PSC[1:0]
rw

rw

rw

9

8

CC4S[1:0]
rw

7

6

OC3CE

rw

5

4

OC3M[2:0]
IC3F[3:0]

rw

rw

rw

3

2

OC3PE OC3FE
IC3PSC[1:0]
rw

rw

rw

1

0

CC3S[1:0]
rw

rw

Output compare mode
Bit 15 OC4CE: Output compare 4 clear enable
Bits 14:12 OC4M: Output compare 4 mode
Bit 11 OC4PE: Output compare 4 preload enable
Bit 10 OC4FE: Output compare 4 fast enable
Bits 9:8 CC4S: Capture/Compare 4 selection
This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC4 channel is configured as output
01: CC4 channel is configured as input, IC4 is mapped on TI4
10: CC4 channel is configured as input, IC4 is mapped on TI3
11: CC4 channel is configured as input, IC4 is mapped on TRC. This mode is working only if
an internal trigger input is selected through TS bit (TIMx_SMCR register)
Note: CC4S bits are writable only when the channel is OFF (CC4E = 0 in TIMx_CCER).
Bit 7 OC3CE: Output compare 3 clear enable
Bits 6:4 OC3M: Output compare 3 mode
Bit 3 OC3PE: Output compare 3 preload enable
Bit 2 OC3FE: Output compare 3 fast enable
Bits 1:0 CC3S: Capture/Compare 3 selection
This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC3 channel is configured as output
01: CC3 channel is configured as input, IC3 is mapped on TI3
10: CC3 channel is configured as input, IC3 is mapped on TI4
11: CC3 channel is configured as input, IC3 is mapped on TRC. This mode is working only if
an internal trigger input is selected through TS bit (TIMx_SMCR register)
Note: CC3S bits are writable only when the channel is OFF (CC3E = 0 in TIMx_CCER).

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Input capture mode
Bits 15:12 IC4F: Input capture 4 filter
Bits 11:10 IC4PSC: Input capture 4 prescaler
Bits 9:8 CC4S: Capture/Compare 4 selection
This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC4 channel is configured as output
01: CC4 channel is configured as input, IC4 is mapped on TI4
10: CC4 channel is configured as input, IC4 is mapped on TI3
11: CC4 channel is configured as input, IC4 is mapped on TRC. This mode is working only if
an internal trigger input is selected through TS bit (TIMx_SMCR register)
Note: CC4S bits are writable only when the channel is OFF (CC4E = 0 in TIMx_CCER).
Bits 7:4 IC3F: Input capture 3 filter
Bits 3:2 IC3PSC: Input capture 3 prescaler
Bits 1:0 CC3S: Capture/Compare 3 selection
This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC3 channel is configured as output
01: CC3 channel is configured as input, IC3 is mapped on TI3
10: CC3 channel is configured as input, IC3 is mapped on TI4
11: CC3 channel is configured as input, IC3 is mapped on TRC. This mode is working only if
an internal trigger input is selected through TS bit (TIMx_SMCR register)
Note: CC3S bits are writable only when the channel is OFF (CC3E = 0 in TIMx_CCER).

14.4.9

TIM3 capture/compare enable register (TIM3_CCER)
Address offset: 0x20
Reset value: 0x0000

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

CC4NP

Res.

CC4P

CC4E

CC3NP

Res.

CC3P

CC3E

CC2NP

Res.

CC2P

CC2E

CC1NP

Res.

CC1P

CC1E

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

Bit 15 CC4NP: Capture/Compare 4 output Polarity.
Refer to CC1NP description
Bit 14

Reserved, always read as 0.

Bit 13 CC4P: Capture/Compare 4 output Polarity.
Refer to CC1P description
Bit 12 CC4E: Capture/Compare 4 output enable.
Refer to CC1E description
Bit 11 CC3NP: Capture/Compare 3 output Polarity.
Refer to CC1NP description
Bit 10

Reserved, always read as 0.

Bit 9 CC3P: Capture/Compare 3 output Polarity.
Refer to CC1P description
Bit 8 CC3E: Capture/Compare 3 output enable.
Refer to CC1E description

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General-purpose timers (TIM3)

Bit 7 CC2NP: Capture/Compare 2 output Polarity.
Refer to CC1NP description
Bit 6 Reserved, always read as 0.
Bit 5 CC2P: Capture/Compare 2 output Polarity.
Refer to CC1P description
Bit 4 CC2E: Capture/Compare 2 output enable.
Refer to CC1E description
Bit 3 CC1NP: Capture/Compare 1 output Polarity.
CC1 channel configured as output:
CC1NP must be kept cleared in this case.
CC1 channel configured as input:
This bit is used in conjunction with CC1P to define TI1FP1/TI2FP1 polarity. refer to CC1P
description.
Bit 2

Reserved, always read as 0.

Bit 1 CC1P: Capture/Compare 1 output Polarity.
CC1 channel configured as output:
0: OC1 active high
1: OC1 active low
CC1 channel configured as input:
CC1NP/CC1P bits select TI1FP1 and TI2FP1 polarity for trigger or capture operations.
00: noninverted/rising edge
Circuit is sensitive to TIxFP1 rising edge (capture, trigger in reset, external clock or trigger
mode), TIxFP1 is not inverted (trigger in gated mode, encoder mode).
01: inverted/falling edge
Circuit is sensitive to TIxFP1 falling edge (capture, trigger in reset, external clock or trigger
mode), TIxFP1 is inverted (trigger in gated mode, encoder mode).
10: reserved, do not use this configuration.
11: noninverted/both edges
Circuit is sensitive to both TIxFP1 rising and falling edges (capture, trigger in reset, external
clock or trigger mode), TIxFP1 is not inverted (trigger in gated mode). This configuration
must not be used for encoder mode.
Bit 0 CC1E: Capture/Compare 1 output enable.
CC1 channel configured as output:
0: Off - OC1 is not active
1: On - OC1 signal is output on the corresponding output pin
CC1 channel configured as input:
This bit determines if a capture of the counter value can actually be done into the input
capture/compare register 1 (TIMx_CCR1) or not.
0: Capture disabled
1: Capture enabled

Table 50. Output control bit for standard OCx channels
CCxE bit

OCx output state

0

Output Disabled (OCx=0, OCx_EN=0)

1

OCx=OCxREF + Polarity, OCx_EN=1

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Note:

The state of the external IO pins connected to the standard OCx channels depends on the
OCx channel state and the GPIO registers.

14.4.10

TIM3 counter (TIM3_CNT)
Address offset: 0x24
Reset value: 0x00000000

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

CNT[15:0]
rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

7

6

5

4

3

2

1

0

rw

rw

rw

rw

rw

rw

rw

Bits 15:0 CNT[15:0]: Low counter value

14.4.11

TIM3 prescaler (TIM3_PSC)
Address offset: 0x28
Reset value: 0x0000

15

14

13

12

11

10

9

8

rw

rw

rw

rw

rw

rw

rw

rw

PSC[15:0]
rw

Bits 15:0 PSC[15:0]: Prescaler value
The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
PSC contains the value to be loaded in the active prescaler register at each update event.

14.4.12

TIM3 auto-reload register (TIM3_ARR)
Address offset: 0x2C
Reset value: 0xFFFFFFFF

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

rw

rw

rw

rw

rw

rw

rw

ARR[15:0]
rw

rw

rw

rw

rw

rw

rw

rw

rw

Bits 15:0 ARR[15:0]: Low Auto-reload value
ARR is the value to be loaded in the actual auto-reload register.
Refer to Section 14.3.1: Time-base unit on page 297 for more details about ARR update and
behavior.
The counter is blocked while the auto-reload value is null.

14.4.13

TIM3 capture/compare register 1 (TIM3_CCR1)
Address offset: 0x34
Reset value: 0x00000000

15

14

13

12

11

10

9

8

rw

rw

rw

rw

rw

rw

rw

7

6

5

4

3

2

1

0

rw

rw

rw

rw

rw

rw

rw

CCR1[15:0]

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General-purpose timers (TIM3)

Bits 15:0 CCR1[15:0]: Low Capture/Compare 1 value
If channel CC1 is configured as output:
CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value).
It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (bit
OC1PE). Otherwise the preload value is copied in the active capture/compare 1 register when
an update event occurs.
The active capture/compare register contains the value to be compared to the counter
TIMx_CNT and signaled on OC1 output.
If channel CC1is configured as input:
CCR1 is the counter value transferred by the last input capture 1 event (IC1).

14.4.14

TIM3 capture/compare register 2 (TIM3_CCR2)
Address offset: 0x38
Reset value: 0x00000000

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

rw

rw

rw

rw

rw

rw

rw

CCR2[15:0]
rw

rw

rw

rw

rw

rw

rw

rw

rw

Bits 15:0 CCR2[15:0]: Low Capture/Compare 2 value
If channel CC2 is configured as output:
CCR2 is the value to be loaded in the actual capture/compare 2 register (preload value).
It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register (bit
OC2PE). Else the preload value is copied in the active capture/compare 2 register when an
update event occurs.
The active capture/compare register contains the value to be compared to the counter
TIMx_CNT and signaled on OC2 output.
If channel CC2 is configured as input:
CCR2 is the counter value transferred by the last input capture 2 event (IC2).

14.4.15

TIM3 capture/compare register 3 (TIM3_CCR3)
Address offset: 0x3C
Reset value: 0x00000000

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

rw

rw

rw

rw

rw

rw

rw

CCR3[15:0]
rw

rw

rw

rw

rw

rw

rw

rw

rw

Bits 15:0 CCR3[15:0]: Low Capture/Compare 3 value
If channel CC3 is configured as output:
CCR3 is the value to be loaded in the actual capture/compare 3 register (preload value).
It is loaded permanently if the preload feature is not selected in the TIMx_CCMR3 register (bit
OC3PE). Else the preload value is copied in the active capture/compare 3 register when an
update event occurs.
The active capture/compare register contains the value to be compared to the counter
TIMx_CNT and signaled on OC3 output.
If channel CC3is configured as input:
CCR3 is the counter value transferred by the last input capture 3 event (IC3).

DocID025023 Rev 4

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360

General-purpose timers (TIM3)

14.4.16

RM0360

TIM3 capture/compare register 4 (TIM3_CCR4)
Address offset: 0x40
Reset value: 0x00000000

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

rw

rw

rw

rw

rw

rw

rw

CCR4[15:0]
rw

rw

rw

rw

rw

rw

rw

rw

rw

Bits 15:0 CCR4[15:0]: Low Capture/Compare 4 value
1.
If CC4 channel is configured as output (CC4S bits):
CCR4 is the value to be loaded in the actual capture/compare 4 register (preload value).
It is loaded permanently if the preload feature is not selected in the TIMx_CCMR4
register (bit OC4PE). Otherwise, the preload value is copied in the active
capture/compare 4 register when an update event occurs.
The active capture/compare register contains the value to be compared to the counter
TIMx_CNT and signaled on OC4 output.
2.
If CC4 channel is configured as input (CC4S bits in TIMx_CCMR4 register):
CCR4 is the counter value transferred by the last input capture 4 event (IC4).

14.4.17

TIM3 DMA control register (TIM3_DCR)
Address offset: 0x48
Reset value: 0x0000

15

14

13

Res.

Res.

Res.

12

11

10

9

8

DBL[4:0]
rw

rw

rw

rw

7

6

5

Res.

Res.

Res.

rw

4

3

2

1

0

rw

rw

DBA[4:0]
rw

rw

rw

Bits 15:13 Reserved, always read as 0.
Bits 12:8 DBL[4:0]: DMA burst length
This 5-bit vector defines the number of DMA transfers (the timer recognizes a burst transfer
when a read or a write access is done to the TIMx_DMAR address).
00000: 1 transfer,
00001: 2 transfers,
00010: 3 transfers,
...
10001: 18 transfers.
Bits 7:5 Reserved, always read as 0.
Bits 4:0 DBA[4:0]: DMA base address
This 5-bit vector defines the base-address for DMA transfers (when read/write access are done
through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the
TIMx_CR1 register.
Example:
00000: TIMx_CR1,
00001: TIMx_CR2,
00010: TIMx_SMCR,
...
Example: Let us consider the following transfer: DBL = 7 transfers & DBA = TIMx_CR1. In this
case the transfer is done to/from 7 registers starting from the TIMx_CR1 address.

356/779

DocID025023 Rev 4

RM0360

General-purpose timers (TIM3)

14.4.18

TIM3 DMA address for full transfer (TIM3_DMAR)
Address offset: 0x4C
Reset value: 0x0000

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

rw

rw

rw

rw

rw

rw

rw

DMAB[15:0]
rw

rw

rw

rw

rw

rw

rw

rw

rw

Bits 15:0 DMAB[15:0]: DMA register for burst accesses
A read or write operation to the DMAR register accesses the register located at the address
(TIMx_CR1 address) + (DBA + DMA index) x 4
where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base
address configured in TIMx_DCR register, DMA index is automatically controlled by the DMA
transfer, and ranges from 0 to DBL (DBL configured in TIMx_DCR).

DocID025023 Rev 4

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360

General-purpose timers (TIM3)

RM0360

Example of how to use the DMA burst feature
In this example the timer DMA burst feature is used to update the contents of the CCRx
registers (x = 2, 3, 4) with the DMA transferring half words into the CCRx registers.
This is done in the following steps:
1.

Configure the corresponding DMA channel as follows:
–

DMA channel peripheral address is the DMAR register address

–

DMA channel memory address is the address of the buffer in the RAM containing
the data to be transferred by DMA into CCRx registers.

–

Number of data to transfer = 3 (See note below).

–

Circular mode disabled.

2.

Configure the DCR register by configuring the DBA and DBL bit fields as follows: 
DBL = 3 transfers, DBA = 0xE.

3.

Enable the TIMx update DMA request (set the UDE bit in the DIER register).

4.

Enable TIMx

5.

Enable the DMA channel

For code example refer to the Appendix section A.8.20: Two timers synchronized by an
external trigger code example.
Note:

358/779

This example is for the case where every CCRx register to be updated once. If every CCRx
register is to be updated twice for example, the number of data to transfer should be 6. Let
us take the example of a buffer in the RAM containing data1, data2, data3, data4, data5 and
data6. The data is transferred to the CCRx registers as follows: on the first update DMA
request, data1 is transferred to CCR2, data2 is transferred to CCR3, data3 is transferred to
CCR4 and on the second update DMA request, data4 is transferred to CCR2, data5 is
transferred to CCR3 and data6 is transferred to CCR4.

DocID025023 Rev 4

0x30

Reserved

0

0

0

TIM3_PSC

Reset value

Reset value

DocID025023 Rev 4

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Res.

Res.

0

Res.

Res.

0

Res.

Res.

0

Res.

Res.

0

Res.

Res.

0

Res.

Res.

0

Res.

Res.

0

Res.

Res.

0

Res.

Res.

0

Res.

Res.

0

Res.

Res.

0

Res.

Res.

0

Res.

Res.

0

Res.

Res.

Reset value

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Reset value

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

TIM3_CNT

Res.

0
0

CC4P
CC4E
CC3NP

0

0

0
0

IC4F[3:0]

0
0
0

0

0

0
0
0
0

0

0

0

0

0

0

0

UG

UIE

UIF

CC1G

CC1IE

CC1IF

CC2G

0
0
0
0
0

OC1FE

OC1M
[2:0]

CC3G

0
0
0
0

0
0
0
0
0
0

Res.
0

Res.

CC2IE

CC2IF

0

TG

MSM

0 0 0 0 0 0 0 0
IC2
CC2S
PSC
IC1F[3:0]
[1:0]
[1:0]
0 0 0 0 0 0 0 0

OC3M
[2:0]

0 0 0 0 0 0 0 0
IC4
CC4S
PSC
IC3F[3:0]
[1:0]
[1:0]
0 0 0 0 0 0 0 0

OCCS

TS[2:0]

CNT[15:0]

PSC[15:0]
0
0
0

0

0

0

0

0

OC3FE

0

CC3IE

CC3IF
0

CC4IE

CC4IF
0

Res.
0

0

TIF
0

OC1PE

0

0

CC1E

0
CC4S
[1:0]

0

0
0

0

0

0

0

0

0

0

Res.

0

0

OC3PE

0
CC2S
[1:0]

Res.
TI1S

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

ARPE

DIR
OPM
URS
UDIS
CEN

0
0
0
0
0

MMS[2:0]
CCDS
Res.
Res.
Res.

0

CC4G

TIE

0

Res.

Res.

UDE

0
Res.

0

Res.

Res.

0

CMS
[1:0]

CC1P

OC4M
[2:0]

Res.

0

0

OC1CE

0

CC1DE

CC1OF
0

Res.

0

CC2DE

CC2OF
0

Res.

0

ETF[3:0]

0

CC1NP

IC2F[3:0]
OC2FE

0

CC3DE

CC3OF
0

Res.

0

0

CC2E

0
OC2PE

Res.
0

Res.

Res.

ECE
0

TDE

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

ETP

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

0

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

0

0
CC4DE

CC4OF
0

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Reset value

ETPS
[1:0]

0

CC2P

0
Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

0

Res.

0
0
0

CKD
[1:0]

OC3CE

0
0

CC3E

0
OC2M
[2:0]

OC4FE

OC2CE

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Reset value

OC4PE

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

0

CC2NP

O24CE

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Reset value

CC3P

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Reset value

Res.

0

Res.

0
0

CC4NP

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Reset value

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

TIM3_CCER

Res.

TIM3_ARR
Res.

Reset value
TIM3_CCMR1
Input capture
mode
Reset value
TIM3_CCMR2
Output compare
mode
Res.

Reset value
TIM3_CCMR1
Output compare
mode

Res.

TIM3_EGR

Res.

0x2C
TIM3_SR

Res.

0x28
TIM3_DIER

Res.

0x24
TIM3_SMCR

Res.

0x20
Reset value
TIM3_CCMR2
Input capture
mode
Reset value
Res.

0x1C
TIM3_CR2

Res.

0x18

Res.

0x14

Res.

0x10

Res.

0x0C

Res.

0x08

Res.

0x04
TIM3_CR1

Res.

0x00

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0

Register

Res.

Offset

Res.

14.4.19

Res.

RM0360
General-purpose timers (TIM3)

TIM3 register map
TIM3 registers are mapped as described in the table below:
Table 51. TIM3 register map and reset values

0
SMS[2:0]

CC1S
[1:0]

0 0 0 0
IC1
CC1S
PSC
[1:0]
[1:0]
0 0 0 0
CC3S
[1:0]

0 0 0 0
IC3
CC3S
PSC
[1:0]
[1:0]
0 0 0 0

ARR[15:0]

Reset value

359/779

360

0x4C

360/779
TIM3_DMAR
Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Reset value
0

DocID025023 Rev 4
0

Res.

Res.

0
0
0
0
0
0

Res.

Res.

Res.

0
Res.

Res.

Res.

0
Res.

Res.

Res.

0
Res.

Res.

Res.

0
Res.

Res.

Res.

0
Res.

Res.

Res.

0
Res.

Res.

Res.

0

Res.

Res.

Res.

0
Res.

Res.

Res.

0

Res.

Res.

Res.

0
Res.

Res.

Res.

Reset value
Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

0

Res.

Res.

Res.

Res.

0

Res.

Res.

Res.

Res.

Reset value

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Reset value

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Reset value

Res.

Res.

Res.

Reset value

Res.

TIM3_DCR

Res.

0x48
Reserved

Res.

0x44
TIM3_CCR4

Res.

0x40
TIM3_CCR3

Res.

0x3C
TIM3_CCR2

Res.

0x38

Res.

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0

TIM3_CCR1
Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Register

Res.

0x34

Res.

Offset

Res.

General-purpose timers (TIM3)
RM0360

Table 51. TIM3 register map and reset values (continued)

CCR2[15:0]

0
0
0
0
0
0
0

CCR1[15:0]

0
0
0
0
0
0
0

0

Reset value

0

0

0

0

0

0

0

0

0

0

0

0

0

0

DBL[4:0]

0

0
0

0
0

0

Refer to Section 2.2.2 on page 37 for the register boundary addresses.
0

0

CCR3[15:0]

0

0

0

0
0
0
0
0
0

0
0
0
0
0
0

CCR4[15:0]

0
0
0
0
0
0

0

0

DBA[4:0]

DMAB[15:0]

0
0
0
0
0

0
0
0
0
0

RM0360

15

Basic timer (TIM6/TIM7)

Basic timer (TIM6/TIM7)
This section applies to STM32F030x8, STM32F070xB and STM32F030xC devices only.
TIM7 is available only on STM32F070xB and STM32F030xC devices.

15.1

TIM6/TIM7 introduction
The basic timer TIM6 consists of a 16-bit auto-reload counter driven by a programmable
prescaler.

15.2

TIM6/TIM7 main features


16-bit auto-reload upcounter



16-bit programmable prescaler used to divide (also “on the fly”) the counter clock
frequency by any factor between 1 and 65535



Interrupt/DMA generation on the update event: counter overflow
Figure 134. Basic timer block diagram

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361/779
373

Basic timer (TIM6/TIM7)

RM0360

15.3

TIM6/TIM7 functional description

15.3.1

Time-base unit
The main block of the programmable timer is a 16-bit upcounter with its related auto-reload
register. The counter clock can be divided by a prescaler.
The counter, the auto-reload register and the prescaler register can be written or read by
software. This is true even when the counter is running.
The time-base unit includes:


Counter Register (TIMx_CNT)



Prescaler Register (TIMx_PSC)



Auto-Reload Register (TIMx_ARR)

The auto-reload register is preloaded. The preload register is accessed each time an
attempt is made to write or read the auto-reload register. The contents of the preload
register are transferred into the shadow register permanently or at each update event UEV,
depending on the auto-reload preload enable bit (ARPE) in the TIMx_CR1 register. The
update event is sent when the counter reaches the overflow value and if the UDIS bit equals
0 in the TIMx_CR1 register. It can also be generated by software. The generation of the
update event is described in detail for each configuration.
The counter is clocked by the prescaler output CK_CNT, which is enabled only when the
counter enable bit (CEN) in the TIMx_CR1 register is set.
Note that the actual counter enable signal CNT_EN is set 1 clock cycle after CEN.

Prescaler description
The prescaler can divide the counter clock frequency by any factor between 1 and 65536. It
is based on a 16-bit counter controlled through a 16-bit register (in the TIMx_PSC register).
It can be changed on the fly as the TIMx_PSC control register is buffered. The new
prescaler ratio is taken into account at the next update event.
Figure 135 and Figure 136 give some examples of the counter behavior when the prescaler
ratio is changed on the fly.

362/779

DocID025023 Rev 4

RM0360

Basic timer (TIM6/TIM7)
Figure 135. Counter timing diagram with prescaler division change from 1 to 2

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Figure 136. Counter timing diagram with prescaler division change from 1 to 4

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363/779
373

Basic timer (TIM6/TIM7)

15.3.2

RM0360

Counter modes
The counter counts from 0 to the auto-reload value (contents of the TIMx_ARR register),
then restarts from 0 and generates a counter overflow event.
An update event can be generate at each counter overflow or by setting the UG bit in the
TIMx_EGR register (by software or by using the slave mode controller).
The UEV event can be disabled by software by setting the UDIS bit in the TIMx_CR1
register. This avoids updating the shadow registers while writing new values into the preload
registers. In this way, no update event occurs until the UDIS bit has been written to 0,
however, the counter and the prescaler counter both restart from 0 (but the prescale rate
does not change). In addition, if the URS (update request selection) bit in the TIMx_CR1
register is set, setting the UG bit generates an update event UEV, but the UIF flag is not set
(so no interrupt or DMA request is sent).
When an update event occurs, all the registers are updated and the update flag (UIF bit in
the TIMx_SR register) is set (depending on the URS bit):


The buffer of the prescaler is reloaded with the preload value (contents of the
TIMx_PSC register)



The auto-reload shadow register is updated with the preload value (TIMx_ARR)

The following figures show some examples of the counter behavior for different clock
frequencies when TIMx_ARR = 0x36.
Figure 137. Counter timing diagram, internal clock divided by 1

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364/779

DocID025023 Rev 4

RM0360

Basic timer (TIM6/TIM7)
Figure 138. Counter timing diagram, internal clock divided by 2

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Figure 139. Counter timing diagram, internal clock divided by 4

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365/779
373

Basic timer (TIM6/TIM7)

RM0360

Figure 140. Counter timing diagram, internal clock divided by N

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Figure 141. Counter timing diagram, update event when ARPE = 0
(TIMx_ARR not preloaded)
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RM0360

Basic timer (TIM6/TIM7)
Figure 142. Counter timing diagram, update event when ARPE=1
(TIMx_ARR preloaded)
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069

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373

Basic timer (TIM6/TIM7)

15.3.3

RM0360

Clock source
The counter clock is provided by the Internal clock (CK_INT) source.
The CEN (in the TIMx_CR1 register) and UG bits (in the TIMx_EGR register) are actual
control bits and can be changed only by software (except for UG that remains cleared
automatically). As soon as the CEN bit is written to 1, the prescaler is clocked by the internal
clock CK_INT.
Figure 143 shows the behavior of the control circuit and the upcounter in normal mode,
without prescaler.
Figure 143. Control circuit in normal mode, internal clock divided by 1

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15.3.4

Debug mode
When the microcontroller enters the debug mode (Cortex™-M0 core - halted), the TIMx
counter either continues to work normally or stops, depending on the DBG_TIMx_STOP
configuration bit in the DBG module.

368/779

DocID025023 Rev 4

RM0360

Basic timer (TIM6/TIM7)

TIM6/TIM7 registers

15.4

Refer to Section 1.1 on page 33 for a list of abbreviations used in register descriptions.
The peripheral registers can be accessed by half-words (16-bit) or words (32-bit).

15.4.1

TIM6/TIM7 control register 1 (TIMx_CR1)
Address offset: 0x00
Reset value: 0x0000

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

ARPE

Res.

Res.

Res.

OPM

URS

UDIS

CEN

rw

rw

rw

rw

rw

Bits 15:8 Reserved, always read as 0.
Bit 7 ARPE: Auto-reload preload enable
0: TIMx_ARR register is not buffered.
1: TIMx_ARR register is buffered.
Bits 6:4 Reserved, always read as 0.
Bit 3 OPM: One-pulse mode
0: Counter is not stopped at update event
1: Counter stops counting at the next update event (clearing the CEN bit).
Bit 2 URS: Update request source
This bit is set and cleared by software to select the UEV event sources.
0: Any of the following events generates an update interrupt or DMA request if enabled.
These events can be:
–
Counter overflow/underflow
–
Setting the UG bit
–
Update generation through the slave mode controller
1: Only counter overflow/underflow generates an update interrupt or DMA request if
enabled.
Bit 1 UDIS: Update disable
This bit is set and cleared by software to enable/disable UEV event generation.
0: UEV enabled. The Update (UEV) event is generated by one of the following events:
–
Counter overflow/underflow
–
Setting the UG bit
–
Update generation through the slave mode controller
Buffered registers are then loaded with their preload values.
1: UEV disabled. The Update event is not generated, shadow registers keep their value
(ARR, PSC). However the counter and the prescaler are reinitialized if the UG bit is set or if
a hardware reset is received from the slave mode controller.
Bit 0 CEN: Counter enable
0: Counter disabled
1: Counter enabled
Note: Gated mode can work only if the CEN bit has been previously set by software.
However trigger mode can set the CEN bit automatically by hardware.
CEN is cleared automatically in one-pulse mode, when an update event occurs.

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373

Basic timer (TIM6/TIM7)

15.4.2

RM0360

TIM6/TIM7 DMA/Interrupt enable register (TIMx_DIER)
Address offset: 0x0C
Reset value: 0x0000

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Res.

Res.

Res.

Res.

Res.

Res.

Res.

UDE

Res.

Res.

Res.

Res.

Res.

Res.

Res.

UIE

rw

Bit 15:9 Reserved, must be kept at reset value.
Bit 8 UDE: Update DMA request enable
0: Update DMA request disabled.
1: Update DMA request enabled.
Bits 7:1 Reserved, must be kept at reset value.
Bit 0 UIE: Update interrupt enable
0: Update interrupt disabled.
1: Update interrupt enabled.

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rw

RM0360

Basic timer (TIM6/TIM7)

15.4.3

TIM6/TIM7 status register (TIMx_SR)
Address offset: 0x10
Reset value: 0x0000

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

0
UIF
rc_w0

Bits 15:1 Reserved, must be kept at reset value.
Bit 0 UIF: Update interrupt flag
This bit is set by hardware on an update event. It is cleared by software.
0: No update occurred.
1: Update interrupt pending. This bit is set by hardware when the registers are updated:
–At overflow or underflow regarding the repetition counter value and if UDIS = 0 in the
TIMx_CR1 register.
–When CNT is reinitialized by software using the UG bit in the TIMx_EGR register, if
URS = 0 and UDIS = 0 in the TIMx_CR1 register.

15.4.4

TIM6/TIM7 event generation register (TIMx_EGR)
Address offset: 0x14
Reset value: 0x0000

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

UG
w

Bits 15:1 Reserved, must be kept at reset value.
Bit 0 UG: Update generation
This bit can be set by software, it is automatically cleared by hardware.
0: No action.
1: Re-initializes the timer counter and generates an update of the registers. Note that the
prescaler counter is cleared too (but the prescaler ratio is not affected).

15.4.5

TIM6/TIM7 counter (TIMx_CNT)
Address offset: 0x24
Reset value: 0x0000

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

rw

rw

rw

rw

rw

rw

rw

CNT[15:0]
rw

rw

Bits 15:0

rw

rw

rw

rw

rw

rw

rw

CNT[15:0]: Counter value

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373

Basic timer (TIM6/TIM7)

15.4.6

RM0360

TIM6/TIM7 prescaler (TIMx_PSC)
Address offset: 0x28
Reset value: 0x0000

15

14

13

12

11

10

9

8

rw

rw

rw

rw

rw

rw

rw

rw

7

6

5

4

3

2

1

0

rw

rw

rw

rw

rw

rw

rw

PSC[15:0]
rw

Bits 15:0 PSC[15:0]: Prescaler value
The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
PSC contains the value to be loaded into the active prescaler register at each update event.

15.4.7

TIM6/TIM7 auto-reload register (TIMx_ARR)
Address offset: 0x2C
Reset value: 0xFFFF

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

rw

rw

rw

rw

rw

rw

rw

ARR[15:0]
rw

rw

rw

rw

rw

rw

rw

rw

rw

Bits 15:0 ARR[15:0]: Auto-reload value
ARR is the value to be loaded into the actual auto-reload register.
Refer to Section 15.3.1: Time-base unit on page 362 for more details about ARR update and
behavior.
The counter is blocked while the auto-reload value is null.

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0x2C
TIMx_ARR
Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

TIMx_PSC

Res.

0x28
Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

TIMx_CNT

Res.

0x24
Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Reset value

Reset value

Reset value

DocID025023 Rev 4
0

0

1

0

0

1

0

0

1

0

0

1

0

0

1

0

0

1

0

0

1

0

0

1

0

0

1

0

0

1

Reset value

Reset value
UIF

Res.

Res.

0

UG

Res.

Res.

Res.

Res.

Res.

Res.

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0

TIMx_CR1
Res.

OPM
URS
UDIS
CEN

0
0
0
0

Res.
Res.
UIE

Res.

Res.

Res.

ARPE

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Register

Res.

Res.

Res.

Res.

Res.

0

Res.

Res.

Res.

Res.

UDE

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Reset value

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Reset value

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

TIMx_EGR

Res.

0x14
TIMx_SR

Res.

0x10
TIMx_DIER

Res.

0x0C

Res.

0x00

Res.

Offset

Res.

15.4.8

Res.

RM0360
Basic timer (TIM6/TIM7)

TIM6/TIM7 register map
TIMx registers are mapped as 16-bit addressable registers as described in the table below:
Table 52. TIM6/TIM7 register map and reset values

0

0

0

CNT[15:0]

PSC[15:0]

ARR[15:0]

0
0
0
0
0
0

0
0
0
0
0
0

1
1
1
1
1
1

Refer to Section 2.2.2 on page 37 for the register boundary addresses.

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General-purpose timer (TIM14)

RM0360

16

General-purpose timer (TIM14)

16.1

TIM14 introduction
The TIM14 general-purpose timer consists of a 16-bit auto-reload counter driven by a
programmable prescaler.
It may be used for a variety of purposes, including measuring the pulse lengths of input
signals (input capture) or generating output waveforms (output compare, PWM).
Pulse lengths and waveform periods can be modulated from a few microseconds to several
milliseconds using the timer prescaler and the RCC clock controller prescalers.
The TIM14 timer is completely independent, and does not share any resources. It can be
synchronized together as described in Section 14.3.15.

16.2

TIM14 main features


16-bit auto-reload upcounter



16-bit programmable prescaler used to divide the counter clock frequency by any factor
between 1 and 65535 (can be changed “on the fly”)



independent channel for:



374/779

–

Input capture

–

Output compare

–

PWM generation (edge-aligned mode)

Interrupt generation on the following events:
–

Update: counter overflow, counter initialization (by software)

–

Input capture

–

Output compare

DocID025023 Rev 4

RM0360

General-purpose timer (TIM14)
Figure 144. General-purpose timer block diagram (TIM14)

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16.3

TIM14 functional description

16.3.1

Time-base unit
The main block of the programmable advanced-control timer is a 16-bit counter with its
related auto-reload register. The counter can count up. The counter clock can be divided by
a prescaler.
The counter, the auto-reload register and the prescaler register can be written or read by
software. This is true even when the counter is running.
The time-base unit includes:


Counter register (TIMx_CNT)



Prescaler register (TIMx_PSC)



Auto-reload register (TIMx_ARR)

The auto-reload register is preloaded. Writing to or reading from the auto-reload register
accesses the preload register. The content of the preload register are transferred into the
shadow register permanently or at each update event (UEV), depending on the auto-reload
preload enable bit (ARPE) in TIMx_CR1 register. The update event is sent when the counter
reaches the overflow and if the UDIS bit equals 0 in the TIMx_CR1 register. It can also be
generated by software. The generation of the update event is described in detailed for each
configuration.
The counter is clocked by the prescaler output CK_CNT, which is enabled only when the
counter enable bit (CEN) in TIMx_CR1 register is set (refer also to the slave mode controller
description to get more details on counter enabling).

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General-purpose timer (TIM14)

RM0360

Note that the counter starts counting 1 clock cycle after setting the CEN bit in the TIMx_CR1
register.

Prescaler description
The prescaler can divide the counter clock frequency by any factor between 1 and 65536. It
is based on a 16-bit counter controlled through a 16-bit register (in the TIMx_PSC register).
It can be changed on the fly as this control register is buffered. The new prescaler ratio is
taken into account at the next update event.
Figure 146 and Figure 147 give some examples of the counter behavior when the prescaler
ratio is changed on the fly.
Figure 145. Counter timing diagram with prescaler division change from 1 to 2
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Figure 146. Counter timing diagram with prescaler division change from 1 to 4

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.47

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RM0360

16.3.2

General-purpose timer (TIM14)

Counter modes
Upcounting mode
In upcounting mode, the counter counts from 0 to the auto-reload value (content of the
TIMx_ARR register), then restarts from 0 and generates a counter overflow event.
Setting the UG bit in the TIMx_EGR register also generates an update event.
The UEV event can be disabled by software by setting the UDIS bit in the TIMx_CR1
register. This is to avoid updating the shadow registers while writing new values in the
preload registers. Then no update event occurs until the UDIS bit has been written to 0.
However, the counter restarts from 0, as well as the counter of the prescaler (but the
prescale rate does not change). In addition, if the URS bit (update request selection) in
TIMx_CR1 register is set, setting the UG bit generates an update event UEV but without
setting the UIF flag (thus no interrupt is sent). This is to avoid generating both update and
capture interrupts when clearing the counter on the capture event.
When an update event occurs, all the registers are updated and the update flag (UIF bit in
TIMx_SR register) is set (depending on the URS bit):


The auto-reload shadow register is updated with the preload value (TIMx_ARR),



The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC
register).

The following figures show some examples of the counter behavior for different clock
frequencies when TIMx_ARR=0x36.
Figure 147. Counter timing diagram, internal clock divided by 1
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469

General-purpose timer (TIM14)

RM0360

Figure 148. Counter timing diagram, internal clock divided by 2
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Figure 149. Counter timing diagram, internal clock divided by 4
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Figure 150. Counter timing diagram, internal clock divided by N
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RM0360

General-purpose timer (TIM14)
Figure 151. Counter timing diagram, update event when ARPE=0
(TIMx_ARR not preloaded)
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Figure 152. Counter timing diagram, update event when ARPE=1
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.47

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General-purpose timer (TIM14)

16.3.3

RM0360

Clock source
The counter clock is provided by the Internal clock (CK_INT) source.
The CEN (in the TIMx_CR1 register) and UG bits (in the TIMx_EGR register) are actual
control bits and can be changed only by software (except for UG that remains cleared
automatically). As soon as the CEN bit is written to 1, the prescaler is clocked by the internal
clock CK_INT.
Figure 153 shows the behavior of the control circuit and the upcounter in normal mode,
without prescaler.
Figure 153. Control circuit in normal mode, internal clock divided by 1
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16.3.4

Capture/compare channels
Each Capture/Compare channel is built around a capture/compare register (including a
shadow register), a input stage for capture (with digital filter, multiplexing and prescaler) and
an output stage (with comparator and output control).
Figure 154 to Figure 156 give an overview of one capture/compare channel.
The input stage samples the corresponding TIx input to generate a filtered signal TIxF.
Then, an edge detector with polarity selection generates a signal (TIxFPx) which can be
used as trigger input by the slave mode controller or as the capture command. It is
prescaled before the capture register (ICxPS).
Figure 154. Capture/compare channel (example: channel 1 input stage)
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RM0360

General-purpose timer (TIM14)
The output stage generates an intermediate waveform which is then used for reference:
OCxRef (active high). The polarity acts at the end of the chain.
Figure 155. Capture/compare channel 1 main circuit
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Figure 156. Output stage of capture/compare channel (channel 1)
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The capture/compare block is made of one preload register and one shadow register. Write
and read always access the preload register.
In capture mode, captures are actually done in the shadow register, which is copied into the
preload register.
In compare mode, the content of the preload register is copied into the shadow register
which is compared to the counter.

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469

General-purpose timer (TIM14)

16.3.5

RM0360

Input capture mode
In Input capture mode, the Capture/Compare Registers (TIMx_CCRx) are used to latch the
value of the counter after a transition detected by the corresponding ICx signal. When a
capture occurs, the corresponding CCXIF flag (TIMx_SR register) is set and an interrupt or
a DMA request can be sent if they are enabled. If a capture occurs while the CCxIF flag was
already high, then the over-capture flag CCxOF (TIMx_SR register) is set. CCxIF can be
cleared by software by writing it to ‘0’ or by reading the captured data stored in the
TIMx_CCRx register. CCxOF is cleared when you write it to ‘0’.
The following example shows how to capture the counter value in TIMx_CCR1 when TI1
input rises. To do this, use the following procedure:
1.

Select the active input: TIMx_CCR1 must be linked to the TI1 input, so write the CC1S
bits to ‘01’ in the TIMx_CCMR1 register. As soon as CC1S becomes different from ‘00’,
the channel is configured in input mode and the TIMx_CCR1 register becomes readonly.

2.

Program the input filter duration you need with respect to the signal you connect to the
timer (when the input is one of the TIx (ICxF bits in the TIMx_CCMRx register). Let us
imagine that, when toggling, the input signal is not stable during at must 5 internal clock
cycles. We must program a filter duration longer than these 5 clock cycles. We can
validate a transition on TI1 when 8 consecutive samples with the new level have been
detected (sampled at fDTS frequency). Then write IC1F bits to ‘0011’ in the
TIMx_CCMR1 register.

3.

Select the edge of the active transition on the TI1 channel by programming CC1P and
CC1NP bits to ‘00’ in the TIMx_CCER register (rising edge in this case).

4.

Program the input prescaler. In our example, we wish the capture to be performed at
each valid transition, so the prescaler is disabled (write IC1PS bits to ‘00’ in the
TIMx_CCMR1 register).

5.

Enable capture from the counter into the capture register by setting the CC1E bit in the
TIMx_CCER register.

6.

If needed, enable the related interrupt request by setting the CC1IE bit in the
TIMx_DIER register.

For code example refer to the Appendix section A.8.3: Input capture configuration code
example.
When an input capture occurs:


The TIMx_CCR1 register gets the value of the counter on the active transition.



CC1IF flag is set (interrupt flag). CC1OF is also set if at least two consecutive captures
occurred whereas the flag was not cleared.



An interrupt is generated depending on the CC1IE bit.

For code example refer to the Appendix section A.8.4: Input capture data management
code example.
In order to handle the overcapture, it is recommended to read the data before the
overcapture flag. This is to avoid missing an overcapture which could happen after reading
the flag and before reading the data.
Note:

382/779

IC interrupt requests can be generated by software by setting the corresponding CCxG bit in
the TIMx_EGR register.

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16.3.6

General-purpose timer (TIM14)

Forced output mode
In output mode (CCxS bits = ‘00’ in the TIMx_CCMRx register), each output compare signal
(OCxREF and then OCx) can be forced to active or inactive level directly by software,
independently of any comparison between the output compare register and the counter.
To force an output compare signal (OCXREF/OCx) to its active level, you just need to write
‘101’ in the OCxM bits in the corresponding TIMx_CCMRx register. Thus OCXREF is forced
high (OCxREF is always active high) and OCx get opposite value to CCxP polarity bit.
For example: CCxP=’0’ (OCx active high) => OCx is forced to high level.
The OCxREF signal can be forced low by writing the OCxM bits to ‘100’ in the
TIMx_CCMRx register.
The comparison between the TIMx_CCRx shadow register and the counter is still performed
and allows the flag to be set. Interrupt requests can be sent accordingly. This is described in
the output compare mode section below.

16.3.7

Output compare mode
This function is used to control an output waveform or to indicate when a period of time has
elapsed.
When a match is found between the capture/compare register and the counter, the output
compare function:
1.

Assigns the corresponding output pin to a programmable value defined by the output
compare mode (OCxM bits in the TIMx_CCMRx register) and the output polarity (CCxP
bit in the TIMx_CCER register). The output pin can keep its level (OCXM=’000’), be set
active (OCxM=’001’), be set inactive (OCxM=’010’) or can toggle (OCxM=’011’) on
match.

2.

Sets a flag in the interrupt status register (CCxIF bit in the TIMx_SR register).

3.

Generates an interrupt if the corresponding interrupt mask is set (CCXIE bit in the
TIMx_DIER register).

The TIMx_CCRx registers can be programmed with or without preload registers using the
OCxPE bit in the TIMx_CCMRx register.
In output compare mode, the update event UEV has no effect on OCxREF and OCx output.
The timing resolution is one count of the counter. Output compare mode can also be used to
output a single pulse (in One-pulse mode).
Procedure:
1.

Select the counter clock (internal, external, prescaler).

2.

Write the desired data in the TIMx_ARR and TIMx_CCRx registers.

3.

Set the CCxIE bit if an interrupt request is to be generated.

4.

5.

Select the output mode. For example:
–

Write OCxM = ‘011’ to toggle OCx output pin when CNT matches CCRx

–

Write OCxPE = ‘0’ to disable preload register

–

Write CCxP = ‘0’ to select active high polarity

–

Write CCxE = ‘1’ to enable the output

Enable the counter by setting the CEN bit in the TIMx_CR1 register.

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For code example refer to the Appendix section A.8.7: Output compare configuration code
example.
The TIMx_CCRx register can be updated at any time by software to control the output
waveform, provided that the preload register is not enabled (OCxPE=’0’, else TIMx_CCRx
shadow register is updated only at the next update event UEV). An example is given in
Figure 157.
Figure 157. Output compare mode, toggle on OC1
:ULWH%KLQWKH&&5UHJLVWHU

7,0B&17



7,0B&&5

%

$

%

%

%

$

2&5() 2&

0DWFKGHWHFWHGRQ&&5
,QWHUUXSWJHQHUDWHGLIHQDEOHG
069

16.3.8

PWM mode
Pulse Width Modulation mode allows you to generate a signal with a frequency determined
by the value of the TIMx_ARR register and a duty cycle determined by the value of the
TIMx_CCRx register.
The PWM mode can be selected independently on each channel (one PWM per OCx
output) by writing ‘110’ (PWM mode 1) or ‘111’ (PWM mode 2) in the OCxM bits in the
TIMx_CCMRx register. You must enable the corresponding preload register by setting the
OCxPE bit in the TIMx_CCMRx register, and eventually the auto-reload preload register (in
upcounting or center-aligned modes) by setting the ARPE bit in the TIMx_CR1 register.
As the preload registers are transferred to the shadow registers only when an update event
occurs, before starting the counter, you have to initialize all the registers by setting the UG
bit in the TIMx_EGR register.
The OCx polarity is software programmable using the CCxP bit in the TIMx_CCER register.
It can be programmed as active high or active low. The OCx output is enabled by the CCxE
bit in the TIMx_CCER register. Refer to the TIMx_CCERx register description for more
details.
In PWM mode (1 or 2), TIMx_CNT and TIMx_CCRx are always compared to determine
whether TIMx_CNT ≤ TIMx_CCRx.

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General-purpose timer (TIM14)
The timer is able to generate PWM in edge-aligned mode only since the counter is
upcounting.

PWM edge-aligned mode
In the following example, we consider PWM mode 1. The reference PWM signal OCxREF is
high as long as TIMx_CNT < TIMx_CCRx else it becomes low. If the compare value in
TIMx_CCRx is greater than the auto-reload value (in TIMx_ARR) then OCxREF is held at
‘1’. If the compare value is 0 then OCxRef is held at ‘0’. Figure 158 shows some edgealigned PWM waveforms in an example where TIMx_ARR=8.
Figure 158. Edge-aligned PWM waveforms (ARR=8)



&RXQWHUUHJLVWHU

&&5[ 





















2&;5()
&&[,)

2&;5()
&&5[ 
&&[,)

2&;5()

µ¶

&&5[!
&&[,)

2&;5()

µ¶

&&5[ 
&&[,)

069

For code example refer to the Appendix section A.8.8: Edge-aligned PWM configuration
example.

16.3.9

Debug mode
When the microcontroller enters debug mode (Cortex™-M0 core halted), the TIMx counter
either continues to work normally or stops, depending on DBG_TIMx_STOP configuration
bit in DBG module.

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General-purpose timer (TIM14)

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16.4

TIM14 registers

16.4.1

TIM14 control register 1 (TIM14_CR1)
Address offset: 0x00
Reset value: 0x0000

15

14

13

12

11

10

Res.

Res.

Res.

Res.

Res.

Res.

9

8

CKD[1:0]
rw

7

6

5

4

3

2

1

0

ARPE

Res.

Res.

Res.

Res.

URS

UDIS

CEN

rw

rw

rw

rw

rw

Bits 15:10 Reserved, must be kept at reset value.
Bits 9:8 CKD: Clock division
This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and
sampling clock used by the digital filters (ETR, TIx),
00: tDTS = tCK_INT
01: tDTS = 2 × tCK_INT
10: tDTS = 4 × tCK_INT
11: Reserved
Bit 7 ARPE: Auto-reload preload enable
0: TIMx_ARR register is not buffered
1: TIMx_ARR register is buffered
Bits 6:3 Reserved, must be kept at reset value.
Bit 2 URS: Update request source
This bit is set and cleared by software to select the update interrupt (UEV) sources.
0: Any of the following events generate an UEV if enabled:
–
Counter overflow
–
Setting the UG bit
1: Only counter overflow generates an UEV if enabled.
Bit 1 UDIS: Update disable
This bit is set and cleared by software to enable/disable update interrupt (UEV) event
generation.
0: UEV enabled. An UEV is generated by one of the following events:
–
Counter overflow
–
Setting the UG bit.
Buffered registers are then loaded with their preload values.
1: UEV disabled. No UEV is generated, shadow registers keep their value (ARR, PSC,
CCRx). The counter and the prescaler are reinitialized if the UG bit is set.
Bit 0 CEN: Counter enable
0: Counter disabled
1: Counter enabled

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General-purpose timer (TIM14)

16.4.2

TIM14 interrupt enable register (TIM14_DIER)
Address offset: 0x0C
Reset value: 0x0000

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

CC1IE

UIE

rw

rw

0

Bits 15:2

Reserved, must be kept at reset value.

Bit 1 CC1IE: Capture/Compare 1 interrupt enable
0: CC1 interrupt disabled
1: CC1 interrupt enabled
Bit 0 UIE: Update interrupt enable
0: Update interrupt disabled
1: Update interrupt enabled

16.4.3

TIM14 status register (TIM14_SR)
Address offset: 0x10
Reset value: 0x0000

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

Res.

Res.

Res.

Res.

Res.

Res.

CC1OF

Res.

Res.

Res.

Res.

Res.

Res.

Res.

CC1IF

UIF

rc_w0

rc_w0

rc_w0

Bit 15:10 Reserved, must be kept at reset value.
Bit 9 CC1OF: Capture/Compare 1 overcapture flag
This flag is set by hardware only when the corresponding channel is configured in input
capture mode. It is cleared by software by writing it to ‘0’.
0: No overcapture has been detected.
1: The counter value has been captured in TIMx_CCR1 register while CC1IF flag was
already set

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Bits 8:2 Reserved, must be kept at reset value.
Bit 1 CC1IF: Capture/compare 1 interrupt flag
If channel CC1 is configured as output:
This flag is set by hardware when the counter matches the compare value. It is cleared by
software.
0: No match.
1: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register.
When the contents of TIMx_CCR1 are greater than the contents of TIMx_ARR, the CC1IF bit
goes high on the counter overflow.
If channel CC1 is configured as input:
This bit is set by hardware on a capture. It is cleared by software or by reading the TIMx_CCR1
register.
0: No input capture occurred.
1: The counter value has been captured in TIMx_CCR1 register (an edge has been detected
on IC1 which matches the selected polarity).
Bit 0 UIF: Update interrupt flag
This bit is set by hardware on an update event. It is cleared by software.
0: No update occurred.
1: Update interrupt pending. This bit is set by hardware when the registers are updated:
–
At overflow and if UDIS=’0’ in the TIMx_CR1 register.
–
When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if
URS=’0’ and UDIS=’0’ in the TIMx_CR1 register.

16.4.4

TIM14 event generation register (TIM14_EGR)
Address offset: 0x14
Reset value: 0x0000

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

CC1G

UG

w

w

Bits 15:2 Reserved, must be kept at reset value.
Bit 1 CC1G: Capture/compare 1 generation
This bit is set by software in order to generate an event, it is automatically cleared by hardware.
0: No action
1: A capture/compare event is generated on channel 1:
If channel CC1 is configured as output:
CC1IF flag is set, Corresponding interrupt or is sent if enabled.
If channel CC1 is configured as input:
The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set,
the corresponding interrupt is sent if enabled. The CC1OF flag is set if the CC1IF flag was
already high.
Bit 0 UG: Update generation
This bit can be set by software, it is automatically cleared by hardware.
0: No action
1: Re-initialize the counter and generates an update of the registers. Note that the prescaler
counter is cleared too (anyway the prescaler ratio is not affected). The counter is cleared.

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General-purpose timer (TIM14)

16.4.5

TIM14 capture/compare mode register 1 (TIM14_CCMR1)
Address offset: 0x18
Reset value: 0x0000
The channels can be used in input (capture mode) or in output (compare mode). The
direction of a channel is defined by configuring the corresponding CCxS bits. All the other
bits of this register have a different function in input and in output mode. For a given bit,
OCxx describes its function when the channel is configured in output, ICxx describes its
function when the channel is configured in input. So you must take care that the same bit
can have a different meaning for the input stage and for the output stage.

15

14

13

12

11

10

9

8

7

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

6

5

4

OC1M[2:0]
IC1F[3:0]

rw

rw

rw

3

2

OC1PE OC1FE
IC1PSC[1:0]
rw

rw

rw

1

0

CC1S[1:0]
rw

rw

Output compare mode
Bits 15:7 Reserved
Bits 6:4 OC1M: Output compare 1 mode
These bits define the behavior of the output reference signal OC1REF from which OC1 is
derived. OC1REF is active high whereas OC1 active level depends on CC1P bit.
000: Frozen. The comparison between the output compare register TIMx_CCR1 and the
counter TIMx_CNT has no effect on the outputs.
001: Set channel 1 to active level on match. OC1REF signal is forced high when the counter
TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).
010: Set channel 1 to inactive level on match. OC1REF signal is forced low when the
counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).
011: Toggle - OC1REF toggles when TIMx_CNT = TIMx_CCR1.
100: Force inactive level - OC1REF is forced low.
101: Force active level - OC1REF is forced high.
110: PWM mode 1 - Channel 1 is active as long as TIMx_CNT < TIMx_CCR1 else inactive.
111: PWM mode 2 - Channel 1 is inactive as long as TIMx_CNT < TIMx_CCR1 else active.
Note: In PWM mode 1 or 2, the OCREF level changes when the result of the comparison
changes or when the output compare mode switches from frozen to PWM mode.

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Bit 3 OC1PE: Output compare 1 preload enable
0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new
value is taken in account immediately.
1: Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload
register. TIMx_CCR1 preload value is loaded in the active register at each update event.
Note: The PWM mode can be used without validating the preload register only in one pulse
mode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed.
Bit 2 OC1FE: Output compare 1 fast enable
This bit is used to accelerate the effect of an event on the trigger in input on the CC output.
0: CC1 behaves normally depending on counter and CCR1 values even when the trigger is
ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is
5 clock cycles.
1: An active edge on the trigger input acts like a compare match on CC1 output. OC is then
set to the compare level independently of the result of the comparison. Delay to sample the
trigger input and to activate CC1 output is reduced to 3 clock cycles. OC1FE acts only if the
channel is configured in PWM1 or PWM2 mode.
Bits 1:0 CC1S: Capture/Compare 1 selection
This bit-field defines the direction of the channel (input/output) as well as the used input. 
00: CC1 channel is configured as output.
01: CC1 channel is configured as input, IC1 is mapped on TI1.
10: Reserved
11: Reserved
Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER).

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General-purpose timer (TIM14)

Input capture mode
Bits 15:8 Reserved
Bits 7:4 IC1F: Input capture 1 filter
This bit-field defines the frequency used to sample TI1 input and the length of the digital filter
applied to TI1. The digital filter is made of an event counter in which N events are needed to
validate a transition on the output:
0000: No filter, sampling is done at fDTS
0001: fSAMPLING = fCK_INT, N = 2
0010: fSAMPLING = fCK_INT, N = 4
0011: fSAMPLING = fCK_INT, N = 8
0100: fSAMPLING = fDTS / 2, N = 6 
0101: fSAMPLING = fDTS / 2, N = 8
0110: fSAMPLING = fDTS / 4, N = 6
0111: fSAMPLING = fDTS / 4, N = 8 
1000: fSAMPLING = fDTS / 8, N = 6
1001: fSAMPLING = fDTS / 8, N = 8
1010: fSAMPLING = fDTS / 16, N = 5
1011: fSAMPLING = fDTS / 16, N = 6
1100: fSAMPLING = fDTS / 16, N = 8
1101: fSAMPLING = fDTS / 32, N = 5
1110: fSAMPLING = fDTS / 32, N = 6
1111: fSAMPLING = fDTS / 32, N = 8
Note: Care must be taken that fDTS is replaced in the formula by CK_INT when ICxF[3:0] = 1,
2 or 3.
Bits 3:2 IC1PSC: Input capture 1 prescaler
This bit-field defines the ratio of the prescaler acting on CC1 input (IC1).
The prescaler is reset as soon as CC1E=’0’ (TIMx_CCER register).
00: no prescaler, capture is done each time an edge is detected on the capture input
01: capture is done once every 2 events
10: capture is done once every 4 events
11: capture is done once every 8 events
Bits 1:0 CC1S: Capture/Compare 1 selection
This bit-field defines the direction of the channel (input/output) as well as the used input.
0: CC1 channel is configured as output
01: CC1 channel is configured as input, IC1 is mapped on TI1
10: 
11:
Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER).

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General-purpose timer (TIM14)

16.4.6

RM0360

TIM14 capture/compare enable register (TIM14_CCER)
Address offset: 0x20
Reset value: 0x0000

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

CC1NP

Res.

CC1P

CC1E

rw

rw

rw

Bits 15:4 Reserved, must be kept at reset value.
Bit 3 CC1NP: Capture/Compare 1 complementary output Polarity.
CC1 channel configured as output: CC1NP must be kept cleared.
CC1 channel configured as input: CC1NP bit is used in conjunction with CC1P to define
TI1FP1 polarity (refer to CC1P description).
Bit 2 Reserved, must be kept at reset value.
Bit 1 CC1P: Capture/Compare 1 output Polarity.
CC1 channel configured as output:
0: OC1 active high
1: OC1 active low
CC1 channel configured as input:
The CC1P bit selects TI1FP1 and TI2FP1 polarity for trigger or capture operations.
00: noninverted/rising edge
Circuit is sensitive to TI1FP1 rising edge (capture mode), TI1FP1 is not inverted.
01: inverted/falling edge
Circuit is sensitive to TI1FP1 falling edge (capture mode), TI1FP1 is inverted.
10: reserved, do not use this configuration.
11: noninverted/both edges
Circuit is sensitive to both TI1FP1 rising and falling edges (capture mode), TI1FP1 is not
inverted.
Bit 0 CC1E: Capture/Compare 1 output enable.
CC1 channel configured as output:
0: Off - OC1 is not active
1: On - OC1 signal is output on the corresponding output pin
CC1 channel configured as input:
This bit determines if a capture of the counter value can actually be done into the input
capture/compare register 1 (TIMx_CCR1) or not.
0: Capture disabled
1: Capture enabled

Table 53. Output control bit for standard OCx channels
CCxE bit

Note:

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OCx output state

0

Output Disabled (OCx=’0’, OCx_EN=’0’)

1

OCx=OCxREF + Polarity, OCx_EN=’1’

The state of the external I/O pins connected to the standard OCx channels depends on the
OCx channel state and the GPIO registers.

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General-purpose timer (TIM14)

16.4.7

TIM14 counter (TIM14_CNT)
Address offset: 0x24
Reset value: 0x0000

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

rw

rw

rw

rw

rw

rw

rw

rw

7

6

5

4

3

2

1

0

rw

rw

rw

rw

rw

rw

rw

CNT[15:0]
rw

rw

rw

rw

rw

rw

rw

rw

Bits 15:0 CNT[15:0]: Counter value

16.4.8

TIM14 prescaler (TIM14_PSC)
Address offset: 0x28
Reset value: 0x0000

15

14

13

12

11

10

9

8

PSC[15:0]
rw

rw

rw

rw

rw

rw

rw

rw

rw

Bits 15:0 PSC[15:0]: Prescaler value
The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
PSC contains the value to be loaded in the active prescaler register at each update event.

16.4.9

TIM14 auto-reload register (TIM14_ARR)
Address offset: 0x2C
Reset value: 0xFFFF

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

rw

rw

rw

rw

rw

rw

rw

ARR[15:0]
rw

rw

rw

rw

rw

rw

rw

rw

rw

Bits 15:0 ARR[15:0]: Auto-reload value
ARR is the value to be loaded in the actual auto-reload register.
Refer to the Section 16.3.1: Time-base unit on page 375 for more details about ARR update
and behavior.
The counter is blocked while the auto-reload value is null.

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16.4.10

RM0360

TIM14 capture/compare register 1 (TIM14_CCR1)
Address offset: 0x34
Reset value: 0x0000

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

rw

rw

rw

rw

rw

rw

rw

CCR1[15:0]
rw

rw

rw

rw

rw

rw

rw

rw

rw

Bits 15:0 CCR1[15:0]: Capture/Compare 1 value
If channel CC1 is configured as output:
CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value).
It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (bit
OC1PE). Else the preload value is copied in the active capture/compare 1 register when an
update event occurs.
The active capture/compare register contains the value to be compared to the counter
TIMx_CNT and signaled on OC1 output.

If channel CC1is configured as input:
CCR1 is the counter value transferred by the last input capture 1 event (IC1).

16.4.11

TIM14 option register (TIM14_OR)
Address offset: 0x50
Reset value: 0x0000

15
Res.

14
Res.

13
Res.

12
Res.

11
Res.

10
Res.

9

8

Res.

Res.

7
Res.

6
Res.

5
Res.

4
Res.

3
Res.

2

1

0
TI1_
RMP

Res.
rw

rw

Bits 15:2 Reserved, must be kept at reset value.
Bit 1:0 TI1_RMP [1:0]: Timer Input 1 remap
Set and cleared by software.
00: TIM14 Channel1 is connected to the GPIO. Refer to the alternate function mapping in the
device datasheets.
01: TIM14 Channel1 is connected to the RTCCLK.
10: TIM14 Channel1 is connected to the HSE/32 Clock.
11: TIM14 Channel1 is connected to the microcontroller clock output (MCO), this selection is
controlled by the MCO[2:0] bits of the Clock configuration register (RCC_CFGR) (see
Section 7.4.2: Clock configuration register (RCC_CFGR)).

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0x30

0x34

Reset value

DocID025023 Rev 4

1

1

1

1

1

1

1

1

Res.

Res.

Res.

Res.

Res.

Res.

Res.

1

Res.

Res.

Res.

1

Res.

Res.

Res.

1

Res.

Res.

Res.

1

Res.

Res.

Res.

1

Res.

Res.

Res.

1

Res.

Res.

Res.

1

Res.

0

1

Res.

Res.

Res.

Reset value

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Reset value

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Reset value

Res.

Res.

TIM14_CCR1

Res.

Reset value

Res.

Reserved

Res.

TIM14_ARR

Res.

0x2C
TIM14_PSC

Res.

0x28
TIM14_CNT

Res.

0x24
Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
CC1NP
Res.
CC1P
CC1E

Reset value
Res.

Reset value

Res.

TIM14_CCER

Res.

0x20
Reserved

Res.

0x1C

0

0
0

0

0

0

0

0

0

0

0
0

0

0
0

0

0
0

0

0
0

0

0
0

0

0
0

0

0
0

0

0

0

0

0

0

0

0

0

OC1M
[2:0]
0
0

IC1F[3:0]
0

0

CC1IF
UIF

Res.

Res.

0
0

UG

0
CC1G

Res.

Res.

Res.

Res.

Res.

Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
CC1IE
UIE

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

UDIS
CEN

Res.

Res.

Res.

Res.

ARPE

URS

0

OC1FE

OC1PE

Res.

Res.

Res.

Res.

Res.

Res.

0

Res.

Res.

Res.

Reset value
Res.

Reset value

Res.

CKD
[1:0]

Res.

Res.

CC1OF

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

0

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Reset value

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Reset value

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Reset value
TIM14_CCMR1
Output compare
mode
Reset value
TIM14_CCMR1
Input capture
mode
Reset value

Res.

0x18
TIM14_EGR

Res.

0x14
TIM14_SR

Res.

0x10
TIM14_DIER

Res.

0x0C
Reserved

Res.

0x08
TIM14_CR1

Res.

0x00

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0

Register

Res.

Offset

Res.

16.4.12

Res.

RM0360
General-purpose timer (TIM14)

TIM14 register map
TIM14 registers are mapped as 16-bit addressable registers as described in the table
below:
Table 54. TIM14 register map and reset values

0
0
0

0
0

0
0

CC1S
[1:0]

0 0 0 0
IC1
CC1S
PSC
[1:0]
[1:0]
0 0 0 0

0
0

CNT[15:0]

PSC[15:0]
0
0
0
0
0
0

0
0
0
0
0
0

ARR[15:0]

CCR1[15:0]

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Reset value

DocID025023 Rev 4

Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0

Res.

Res.

Res.
Res.

TI1_RMP

Res.

Res.

Reset value

Res.

TIM14_OR

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0

Reserved
Res.

0x38 to
0x4C
Res.

Register

Res.

Offset

Res.

General-purpose timer (TIM14)
RM0360

Table 54. TIM14 register map and reset values (continued)

0

RM0360

17

General-purpose timers (TIM15/16/17)

General-purpose timers (TIM15/16/17)
TIM15 is not available on STM32F030x4 and STM32F030x6 devices.

17.1

TIM15/16/17 introduction
The TIM15/16/17 timers consist of a 16-bit auto-reload counter driven by a programmable
prescaler.
They may be used for a variety of purposes, including measuring the pulse lengths of input
signals (input capture) or generating output waveforms (output compare, PWM,
complementary PWM with dead-time insertion).
Pulse lengths and waveform periods can be modulated from a few microseconds to several
milliseconds using the timer prescaler and the RCC clock controller prescalers.
The TIM15/16/17 timers are completely independent, and do not share any resources. The
TIM15 can be synchronized with other timers.

17.2

TIM15 main features
TIM15 includes the following features:


16-bit auto-reload upcounter



16-bit programmable prescaler used to divide (also “on the fly”) the counter clock
frequency by any factor between 1 and 65535



Up to 2 independent channels for:
–

Input capture

–

Output compare

–

PWM generation (Edge-aligned mode)

–

One-pulse mode output



Complementary outputs with programmable dead-time (for channel 1 only)



Synchronization circuit to control the timer with external signals and to interconnect
several timers together



Repetition counter to update the timer registers only after a given number of cycles of
the counter



Break input to put the timer’s output signals in the reset state or a known state



Interrupt/DMA generation on the following events:
–

Update: counter overflow, counter initialization (by software or internal/external
trigger)

–

Trigger event (counter start, stop, initialization or count by internal/external trigger)

–

Input capture

–

Output compare

–

Break input (interrupt request)

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General-purpose timers (TIM15/16/17)

RM0360

Figure 159. TIM15 block diagram

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398/779

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RM0360

17.3

General-purpose timers (TIM15/16/17)

TIM16 and TIM17 main features
The TIM16 and TIM17 timers include the following features:


16-bit auto-reload upcounter



16-bit programmable prescaler used to divide (also “on the fly”) the counter clock
frequency by any factor between 1 and 65535



One channel for:
–

Input capture

–

Output compare

–

PWM generation (Edge-aligned mode)

–

One-pulse mode output



Complementary outputs with programmable dead-time



Repetition counter to update the timer registers only after a given number of cycles of
the counter



Break input to put the timer’s output signals in the reset state or a known state



Interrupt/DMA generation on the following events:
–

Update: counter overflow

–

Input capture

–

Output compare

–

Break input

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General-purpose timers (TIM15/16/17)

RM0360

Figure 160. TIM16 and TIM17 block diagram

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RM0360

General-purpose timers (TIM15/16/17)

17.4

TIM15/16/17 functional description

17.4.1

Time-base unit
The main block of the programmable advanced-control timer is a 16-bit counter with its
related auto-reload register. The counter can count up, down or both up and down. The
counter clock can be divided by a prescaler.
The counter, the auto-reload register and the prescaler register can be written or read by
software. This is true even when the counter is running.
The time-base unit includes:


Counter register (TIMx_CNT)



Prescaler register (TIMx_PSC)



Auto-reload register (TIMx_ARR)



Repetition counter register (TIMx_RCR)

The auto-reload register is preloaded. Writing to or reading from the auto-reload register
accesses the preload register. The content of the preload register are transferred into the
shadow register permanently or at each update event (UEV), depending on the auto-reload
preload enable bit (ARPE) in TIMx_CR1 register. The update event is sent when the counter
reaches the overflow (or underflow when downcounting) and if the UDIS bit equals 0 in the
TIMx_CR1 register. It can also be generated by software. The generation of the update
event is described in detailed for each configuration.
The counter is clocked by the prescaler output CK_CNT, which is enabled only when the
counter enable bit (CEN) in TIMx_CR1 register is set (refer also to the slave mode controller
description to get more details on counter enabling).
Note that the counter starts counting 1 clock cycle after setting the CEN bit in the TIMx_CR1
register.

Prescaler description
The prescaler can divide the counter clock frequency by any factor between 1 and 65536. It
is based on a 16-bit counter controlled through a 16-bit register (in the TIMx_PSC register).
It can be changed on the fly as this control register is buffered. The new prescaler ratio is
taken into account at the next update event.
Figure 146 and Figure 147 give some examples of the counter behavior when the prescaler
ratio is changed on the fly:

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General-purpose timers (TIM15/16/17)

RM0360

Figure 161. Counter timing diagram with prescaler division change from 1 to 2

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Figure 162. Counter timing diagram with prescaler division change from 1 to 4

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17.4.2

General-purpose timers (TIM15/16/17)

Counter modes
Upcounting mode
In upcounting mode, the counter counts from 0 to the auto-reload value (content of the
TIMx_ARR register), then restarts from 0 and generates a counter overflow event.
If the repetition counter is used, the update event (UEV) is generated after upcounting is
repeated for the number of times programmed in the repetition counter register
(TIMx_RCR). Else the update event is generated at each counter overflow.
Setting the UG bit in the TIMx_EGR register (by software or by using the slave mode
controller) also generates an update event.

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General-purpose timers (TIM15/16/17)

RM0360

The UEV event can be disabled by software by setting the UDIS bit in the TIMx_CR1
register. This is to avoid updating the shadow registers while writing new values in the
preload registers. Then no update event occurs until the UDIS bit has been written to 0.
However, the counter restarts from 0, as well as the counter of the prescaler (but the
prescale rate does not change). In addition, if the URS bit (update request selection) in
TIMx_CR1 register is set, setting the UG bit generates an update event UEV but without
setting the UIF flag (thus no interrupt or DMA request is sent). This is to avoid generating
both update and capture interrupts when clearing the counter on the capture event.
When an update event occurs, all the registers are updated and the update flag (UIF bit in
TIMx_SR register) is set (depending on the URS bit):


The repetition counter is reloaded with the content of TIMx_RCR register,



The auto-reload shadow register is updated with the preload value (TIMx_ARR),



The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC
register).

The following figures show some examples of the counter behavior for different clock
frequencies when TIMx_ARR=0x36.
Figure 163. Counter timing diagram, internal clock divided by 1

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General-purpose timers (TIM15/16/17)
Figure 164. Counter timing diagram, internal clock divided by 2

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Figure 165. Counter timing diagram, internal clock divided by 4

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General-purpose timers (TIM15/16/17)

RM0360

Figure 166. Counter timing diagram, internal clock divided by N

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Figure 167. Counter timing diagram, update event when ARPE=0
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General-purpose timers (TIM15/16/17)
Figure 168. Counter timing diagram, update event when ARPE=1
(TIMx_ARR preloaded)
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069

Repetition counter
Section 16.3.1: Time-base unit describes how the update event (UEV) is generated with
respect to the counter overflows/underflows. It is actually generated only when the repetition
counter has reached zero. This can be useful when generating PWM signals.
This means that data are transferred from the preload registers to the shadow registers
(TIMx_ARR auto-reload register, TIMx_PSC prescaler register, but also TIMx_CCRx
capture/compare registers in compare mode) every N counter overflows or underflows,
where N is the value in the TIMx_RCR repetition counter register.
The repetition counter is decremented at each counter overflow in upcounting mode.
The repetition counter is an auto-reload type; the repetition rate is maintained as defined by
the TIMx_RCR register value (refer to Figure 169). When the update event is generated by
software (by setting the UG bit in TIMx_EGR register) or by hardware through the slave
mode controller, it occurs immediately whatever the value of the repetition counter is and the
repetition counter is reloaded with the content of the TIMx_RCR register.

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RM0360

Figure 169. Update rate examples depending on mode and TIMx_RCR register
settings
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17.4.4

Clock sources
The counter clock can be provided by the following clock sources:


Internal clock (CK_INT)



External clock mode1: external input pin (only for TIM15)



Internal trigger inputs (ITRx) (only for TIM15): using one timer as the prescaler for
another timer, for example, you can configure TIM1 to act as a prescaler for TIM15.
Refer to Using one timer as prescaler for another for more details.

Internal clock source (CK_INT)
For TIM5 if the slave mode controller is disabled (SMS=000), then the CEN, DIR (in the
TIMx_CR1 register) and UG bits (in the TIMx_EGR register) are actual control bits and can

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General-purpose timers (TIM15/16/17)
be changed only by software (except UG which remains cleared automatically). As soon as
the CEN bit is written to 1, the prescaler is clocked by the internal clock CK_INT.
Figure 16.3.4 shows the behavior of the control circuit and the upcounter in normal mode,
without prescaler.
Figure 170. Control circuit in normal mode, internal clock divided by 1

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External clock source mode 1
This mode is selected when SMS=111 in the TIMx_SMCR register. The counter can count at
each rising or falling edge on a selected input.
Figure 171. TI2 external clock connection example
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For example, to configure the upcounter to count in response to a rising edge on the TI2
input, use the following procedure:

Note:

1.

Configure channel 2 to detect rising edges on the TI2 input by writing CC2S = ‘01’ in
the TIMx_CCMR1 register.

2.

Configure the input filter duration by writing the IC2F[3:0] bits in the TIMx_CCMR1
register (if no filter is needed, keep IC2F=0000).

3.

Select rising edge polarity by writing CC2P=0 in the TIMx_CCER register.

4.

Configure the timer in external clock mode 1 by writing SMS=111 in the TIMx_SMCR
register.

5.

Select TI2 as the trigger input source by writing TS=110 in the TIMx_SMCR register.

6.

Enable the counter by writing CEN=1 in the TIMx_CR1 register.

The capture prescaler is not used for triggering, so you don’t need to configure it.
For code example refer to the Appendix section A.8.1: Upcounter on TI2 rising edge code
example.
When a rising edge occurs on TI2, the counter counts once and the TIF flag is set.
The delay between the rising edge on TI2 and the actual clock of the counter is due to the
resynchronization circuit on TI2 input.
Figure 172. Control circuit in external clock mode 1

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17.4.5

Capture/compare channels
Each Capture/Compare channel is built around a capture/compare register (including a
shadow register), a input stage for capture (with digital filter, multiplexing and prescaler) and
an output stage (with comparator and output control).
Figure 154 to Figure 176 give an overview of one Capture/Compare channel.
The input stage samples the corresponding TIx input to generate a filtered signal TIxF.
Then, an edge detector with polarity selection generates a signal (TIxFPx) which can be

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General-purpose timers (TIM15/16/17)
used as trigger input by the slave mode controller or as the capture command. It is
prescaled before the capture register (ICxPS).
Figure 173. Capture/compare channel (example: channel 1 input stage)

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The output stage generates an intermediate waveform which is then used for reference:
OCxRef (active high). The polarity acts at the end of the chain.

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Figure 174. Capture/compare channel 1 main circuit

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General-purpose timers (TIM15/16/17)
Figure 176. Output stage of capture/compare channel (channel 2 for TIM15)
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The capture/compare block is made of one preload register and one shadow register. Write
and read always access the preload register.
In capture mode, captures are actually done in the shadow register, which is copied into the
preload register.
In compare mode, the content of the preload register is copied into the shadow register
which is compared to the counter.

17.4.6

Input capture mode
In Input capture mode, the Capture/Compare Registers (TIMx_CCRx) are used to latch the
value of the counter after a transition detected by the corresponding ICx signal. When a
capture occurs, the corresponding CCXIF flag (TIMx_SR register) is set and an interrupt or
a DMA request can be sent if they are enabled. If a capture occurs while the CCxIF flag was
already high, then the over-capture flag CCxOF (TIMx_SR register) is set. CCxIF can be
cleared by software by writing it to ‘0’ or by reading the captured data stored in the
TIMx_CCRx register. CCxOF is cleared when you write it to ‘0’.
The following example shows how to capture the counter value in TIMx_CCR1 when TI1
input rises. To do this, use the following procedure:


Select the active input: TIMx_CCR1 must be linked to the TI1 input, so write the CC1S
bits to 01 in the TIMx_CCMR1 register. As soon as CC1S becomes different from 00,
the channel is configured in input and the TIMx_CCR1 register becomes read-only.



Program the input filter duration you need with respect to the signal you connect to the
timer (when the input is one of the TIx (ICxF bits in the TIMx_CCMRx register). Let’s
imagine that, when toggling, the input signal is not stable during at must 5 internal clock
cycles. We must program a filter duration longer than these 5 clock cycles. We can
validate a transition on TI1 when 8 consecutive samples with the new level have been

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detected (sampled at fDTS frequency). Then write IC1F bits to 0011 in the
TIMx_CCMR1 register.


Select the edge of the active transition on the TI1 channel by writing CC1P bit to 0 in
the TIMx_CCER register (rising edge in this case).



Program the input prescaler. In our example, we wish the capture to be performed at
each valid transition, so the prescaler is disabled (write IC1PS bits to ‘00’ in the
TIMx_CCMR1 register).



Enable capture from the counter into the capture register by setting the CC1E bit in the
TIMx_CCER register.



If needed, enable the related interrupt request by setting the CC1IE bit in the
TIMx_DIER register, and/or the DMA request by setting the CC1DE bit in the
TIMx_DIER register.

For code example refer to the Appendix section A.8.3: Input capture configuration code
example.
When an input capture occurs:


The TIMx_CCR1 register gets the value of the counter on the active transition.



CC1IF flag is set (interrupt flag). CC1OF is also set if at least two consecutive captures
occurred whereas the flag was not cleared.



An interrupt is generated depending on the CC1IE bit.



A DMA request is generated depending on the CC1DE bit.

For code example refer to the Appendix section A.8.4: Input capture data management
code example.
In order to handle the overcapture, it is recommended to read the data before the
overcapture flag. This is to avoid missing an overcapture which could happen after reading
the flag and before reading the data.
Note:

IC interrupt and/or DMA requests can be generated by software by setting the
corresponding CCxG bit in the TIMx_EGR register.

17.4.7

PWM input mode (only for TIM15)
This mode is a particular case of input capture mode. The procedure is the same except:

414/779



Two ICx signals are mapped on the same TIx input.



These 2 ICx signals are active on edges with opposite polarity.



One of the two TIxFP signals is selected as trigger input and the slave mode controller
is configured in reset mode.

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General-purpose timers (TIM15/16/17)
For example, you can measure the period (in TIMx_CCR1 register) and the duty cycle (in
TIMx_CCR2 register) of the PWM applied on TI1 using the following procedure (depending
on CK_INT frequency and prescaler value):


Select the active input for TIMx_CCR1: write the CC1S bits to 01 in the TIMx_CCMR1
register (TI1 selected).



Select the active polarity for TI1FP1 (used both for capture in TIMx_CCR1 and counter
clear): write the CC1P bit to ‘0’ (active on rising edge).



Select the active input for TIMx_CCR2: write the CC2S bits to 10 in the TIMx_CCMR1
register (TI1 selected).



Select the active polarity for TI1FP2 (used for capture in TIMx_CCR2): write the CC2P
bit to ‘1’ (active on falling edge).



Select the valid trigger input: write the TS bits to 101 in the TIMx_SMCR register
(TI1FP1 selected).



Configure the slave mode controller in reset mode: write the SMS bits to 100 in the
TIMx_SMCR register.



Enable the captures: write the CC1E and CC2E bits to ‘1’ in the TIMx_CCER register.

For code example refer to the Appendix section A.8.5: PWM input configuration code
example.
Figure 177. PWM input mode timing
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1. The PWM input mode can be used only with the TIMx_CH1/TIMx_CH2 signals due to the fact that only
TI1FP1 and TI2FP2 are connected to the slave mode controller.

17.4.8

Forced output mode
In output mode (CCxS bits = 00 in the TIMx_CCMRx register), each output compare signal
(OCxREF and then OCx/OCxN) can be forced to active or inactive level directly by software,
independently of any comparison between the output compare register and the counter.
To force an output compare signal (OCXREF/OCx) to its active level, you just need to write
101 in the OCxM bits in the corresponding TIMx_CCMRx register. Thus OCXREF is forced
high (OCxREF is always active high) and OCx get opposite value to CCxP polarity bit.
For example: CCxP=0 (OCx active high) => OCx is forced to high level.

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The OCxREF signal can be forced low by writing the OCxM bits to 100 in the TIMx_CCMRx
register.
Anyway, the comparison between the TIMx_CCRx shadow register and the counter is still
performed and allows the flag to be set. Interrupt and DMA requests can be sent
accordingly. This is described in the output compare mode section below.

17.4.9

Output compare mode
This function is used to control an output waveform or indicating when a period of time has
elapsed.
When a match is found between the capture/compare register and the counter, the output
compare function:


Assigns the corresponding output pin to a programmable value defined by the output
compare mode (OCxM bits in the TIMx_CCMRx register) and the output polarity (CCxP
bit in the TIMx_CCER register). The output pin can keep its level (OCXM=000), be set
active (OCxM=001), be set inactive (OCxM=010) or can toggle (OCxM=011) on match.



Sets a flag in the interrupt status register (CCxIF bit in the TIMx_SR register).



Generates an interrupt if the corresponding interrupt mask is set (CCXIE bit in the
TIMx_DIER register).



Sends a DMA request if the corresponding enable bit is set (CCxDE bit in the
TIMx_DIER register, CCDS bit in the TIMx_CR2 register for the DMA request
selection).

The TIMx_CCRx registers can be programmed with or without preload registers using the
OCxPE bit in the TIMx_CCMRx register.
In output compare mode, the update event UEV has no effect on OCxREF and OCx output.
The timing resolution is one count of the counter. Output compare mode can also be used to
output a single pulse (in One-pulse mode).
Procedure:
1.

Select the counter clock (internal, external, prescaler).

2.

Write the desired data in the TIMx_ARR and TIMx_CCRx registers.

3.

Set the CCxIE bit if an interrupt request is to be generated.

4.

5.

Select the output mode. For example:
–

Write OCxM = 011 to toggle OCx output pin when CNT matches CCRx

–

Write OCxPE = 0 to disable preload register

–

Write CCxP = 0 to select active high polarity

–

Write CCxE = 1 to enable the output

Enable the counter by setting the CEN bit in the TIMx_CR1 register.

For code example refer to the Appendix section A.8.2: Up counter on each 2 ETR rising
edges code example.
The TIMx_CCRx register can be updated at any time by software to control the output
waveform, provided that the preload register is not enabled (OCxPE=’0’, else TIMx_CCRx
shadow register is updated only at the next update event UEV). An example is given in
Figure 157.

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Figure 178. Output compare mode, toggle on OC1
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17.4.10

PWM mode
Pulse Width Modulation mode allows you to generate a signal with a frequency determined
by the value of the TIMx_ARR register and a duty cycle determined by the value of the
TIMx_CCRx register.
The PWM mode can be selected independently on each channel (one PWM per OCx
output) by writing ‘110’ (PWM mode 1) or ‘111’ (PWM mode 2) in the OCxM bits in the
TIMx_CCMRx register. You must enable the corresponding preload register by setting the
OCxPE bit in the TIMx_CCMRx register, and eventually the auto-reload preload register (in
upcounting or center-aligned modes) by setting the ARPE bit in the TIMx_CR1 register.
As the preload registers are transferred to the shadow registers only when an update event
occurs, before starting the counter, you have to initialize all the registers by setting the UG
bit in the TIMx_EGR register.
OCx polarity is software programmable using the CCxP bit in the TIMx_CCER register. It
can be programmed as active high or active low. OCx output is enabled by a combination of
the CCxE, CCxNE, MOE, OSSI and OSSR bits (TIMx_CCER and TIMx_BDTR registers).
Refer to the TIMx_CCER register description for more details.
In PWM mode (1 or 2), TIMx_CNT and TIMx_CCRx are always compared to determine
whether TIMx_CCRx ≤ TIMx_CNT or TIMx_CNT ≤ TIMx_CCRx (depending on the direction
of the counter).
The timer is able to generate PWM in edge-aligned mode or center-aligned mode
depending on the CMS bits in the TIMx_CR1 register.

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PWM edge-aligned mode


Upcounting configuration
Upcounting is active when the DIR bit in the TIMx_CR1 register is low. Refer to the
Upcounting mode on page 377.
In the following example, we consider PWM mode 1. The reference PWM signal
OCxREF is high as long as TIMx_CNT < TIMx_CCRx else it becomes low. If the
compare value in TIMx_CCRx is greater than the auto-reload value (in TIMx_ARR)
then OCxREF is held at ‘1’. If the compare value is 0 then OCxRef is held at ‘0’.
Figure 158 shows some edge-aligned PWM waveforms in an example where
TIMx_ARR=8.
Figure 179. Edge-aligned PWM waveforms (ARR=8)



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For code example refer to the Appendix section A.8.9: Center-aligned PWM configuration
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

Downcounting configuration
Downcounting is active when DIR bit in TIMx_CR1 register is high. Refer to the
Repetition counter on page 407
In PWM mode 1, the reference signal OCxRef is low as long as
TIMx_CNT > TIMx_CCRx else it becomes high. If the compare value in TIMx_CCRx is
greater than the auto-reload value in TIMx_ARR, then OCxREF is held at ‘1’. 0% PWM
is not possible in this mode.

17.4.11

Complementary outputs and dead-time insertion
The TIM15/16/17 general-purpose timers can output one complementary signal and
manage the switching-off and switching-on of the outputs.

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General-purpose timers (TIM15/16/17)
This time is generally known as dead-time and you have to adjust it depending on the
devices you have connected to the outputs and their characteristics (intrinsic delays of levelshifters, delays due to power switches...)
You can select the polarity of the outputs (main output OCx or complementary OCxN)
independently for each output. This is done by writing to the CCxP and CCxNP bits in the
TIMx_CCER register.
The complementary signals OCx and OCxN are activated by a combination of several
control bits: the CCxE and CCxNE bits in the TIMx_CCER register and the MOE, OISx,
OISxN, OSSI and OSSR bits in the TIMx_BDTR and TIMx_CR2 registers. Refer to
Table 56: Output control bits for complementary OCx and OCxN channels with break feature
on page 442 for more details. In particular, the dead-time is activated when switching to the
IDLE state (MOE falling down to 0).
Dead-time insertion is enabled by setting both CCxE and CCxNE bits, and the MOE bit if the
break circuit is present. There is one 10-bit dead-time generator for each channel. From a
reference waveform OCxREF, it generates 2 outputs OCx and OCxN. If OCx and OCxN are
active high:


The OCx output signal is the same as the reference signal except for the rising edge,
which is delayed relative to the reference rising edge.



The OCxN output signal is the opposite of the reference signal except for the rising
edge, which is delayed relative to the reference falling edge.

If the delay is greater than the width of the active output (OCx or OCxN) then the
corresponding pulse is not generated.
The following figures show the relationships between the output signals of the dead-time
generator and the reference signal OCxREF. (we suppose CCxP=0, CCxNP=0, MOE=1,
CCxE=1 and CCxNE=1 in these examples)
Figure 180. Complementary output with dead-time insertion

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Figure 181. Dead-time waveforms with delay greater than the negative pulse

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Figure 182. Dead-time waveforms with delay greater than the positive pulse

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The dead-time delay is the same for each of the channels and is programmable with the
DTG bits in the TIMx_BDTR register. Refer to Section 17.5.15: TIM15 break and dead-time
register (TIM15_BDTR) on page 445 for delay calculation.

Re-directing OCxREF to OCx or OCxN
In output mode (forced, output compare or PWM), OCxREF can be re-directed to the OCx
output or to OCxN output by configuring the CCxE and CCxNE bits in the TIMx_CCER
register.
This allows you to send a specific waveform (such as PWM or static active level) on one
output while the complementary remains at its inactive level. Other alternative possibilities
are to have both outputs at inactive level or both outputs active and complementary with
dead-time.
Note:

420/779

When only OCxN is enabled (CCxE=0, CCxNE=1), it is not complemented and becomes
active as soon as OCxREF is high. For example, if CCxNP=0 then OCxN=OCxRef. On the
other hand, when both OCx and OCxN are enabled (CCxE=CCxNE=1) OCx becomes
active when OCxREF is high whereas OCxN is complemented and becomes active when
OCxREF is low.

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17.4.12

General-purpose timers (TIM15/16/17)

Using the break function
When using the break function, the output enable signals and inactive levels are modified
according to additional control bits (MOE, OSSI and OSSR bits in the TIMx_BDTR register,
OISx and OISxN bits in the TIMx_CR2 register). In any case, the OCx and OCxN outputs
cannot be set both to active level at a given time. Refer to Table 56: Output control bits for
complementary OCx and OCxN channels with break feature on page 442 for more details.
The source for break (BRK) channel can be an external source connected to the BKIN pin or
one of the following internal sources:


the core LOCKUP output



the PVD output



the SRAM parity error signal



a clock failure event generated by the CSS detector

When exiting from reset, the break circuit is disabled and the MOE bit is low. You can enable
the break function by setting the BKE bit in the TIMx_BDTR register. The break input
polarity can be selected by configuring the BKP bit in the same register. BKE and BKP can
be modified at the same time. When the BKE and BKP bits are written, a delay of 1 APB
clock cycle is applied before the writing is effective. Consequently, it is necessary to wait 1
APB clock period to correctly read back the bit after the write operation.

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Because MOE falling edge can be asynchronous, a resynchronization circuit has been
inserted between the actual signal (acting on the outputs) and the synchronous control bit
(accessed in the TIMx_BDTR register). It results in some delays between the asynchronous
and the synchronous signals. In particular, if you write MOE to 1 whereas it was low, you
must insert a delay (dummy instruction) before reading it correctly. This is because you write
the asynchronous signal and read the synchronous signal.
When a break occurs (selected level on the break input):

Note:



The MOE bit is cleared asynchronously, putting the outputs in inactive state, idle state
or in reset state (selected by the OSSI bit). This feature functions even if the MCU
oscillator is off.



Each output channel is driven with the level programmed in the OISx bit in the
TIMx_CR2 register as soon as MOE=0. If OSSI=0 then the timer releases the enable
output else the enable output remains high.



When complementary outputs are used:
–

The outputs are first put in reset state inactive state (depending on the polarity).
This is done asynchronously so that it works even if no clock is provided to the
timer.

–

If the timer clock is still present, then the dead-time generator is reactivated in
order to drive the outputs with the level programmed in the OISx and OISxN bits
after a dead-time. Even in this case, OCx and OCxN cannot be driven to their
active level together. Note that because of the resynchronization on MOE, the
dead-time duration is a bit longer than usual (around 2 ck_tim clock cycles).

–

If OSSI=0 then the timer releases the enable outputs else the enable outputs
remain or become high as soon as one of the CCxE or CCxNE bits is high.



The break status flag (BIF bit in the TIMx_SR register) is set. An interrupt can be
generated if the BIE bit in the TIMx_DIER register is set.



If the AOE bit in the TIMx_BDTR register is set, the MOE bit is automatically set again
at the next update event UEV. This can be used to perform a regulation, for instance.
Else, MOE remains low until you write it to ‘1’ again. In this case, it can be used for
security and you can connect the break input to an alarm from power drivers, thermal
sensors or any security components.

The break inputs is acting on level. Thus, the MOE cannot be set while the break input is
active (neither automatically nor by software). In the meantime, the status flag BIF cannot
be cleared.
The break can be generated by the BRK input which has a programmable polarity and an
enable bit BKE in the TIMx_BDTR Register.
In addition to the break input and the output management, a write protection has been
implemented inside the break circuit to safeguard the application. It allows you to freeze the
configuration of several parameters (dead-time duration, OCx/OCxN polarities and state
when disabled, OCxM configurations, break enable and polarity). You can choose from 3
levels of protection selected by the LOCK bits in the TIMx_BDTR register. Refer to
Section 17.5.15: TIM15 break and dead-time register (TIM15_BDTR) on page 445. The
LOCK bits can be written only once after an MCU reset.
The Figure 183 shows an example of behavior of the outputs in response to a break.

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Figure 183. Output behavior in response to a break
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17.4.13

RM0360

One-pulse mode
One-pulse mode (OPM) is a particular case of the previous modes. It allows the counter to
be started in response to a stimulus and to generate a pulse with a programmable length
after a programmable delay.
Starting the counter can be controlled through the slave mode controller. Generating the
waveform can be done in output compare mode or PWM mode. You select One-pulse mode
by setting the OPM bit in the TIMx_CR1 register. This makes the counter stop automatically
at the next update event UEV.
A pulse can be correctly generated only if the compare value is different from the counter
initial value. Before starting (when the timer is waiting for the trigger), the configuration must
be:


In upcounting: CNT < CCRx ≤ ARR (in particular, 0 < CCRx)



In downcounting: CNT > CCRx
Figure 184. Example of One-pulse mode
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For example you may want to generate a positive pulse on OC1 with a length of tPULSE and
after a delay of tDELAY as soon as a positive edge is detected on the TI2 input pin.
Let’s use TI2FP2 as trigger 1:


Map TI2FP2 to TI2 by writing CC2S=’01’ in the TIMx_CCMR1 register.



TI2FP2 must detect a rising edge, write CC2P=’0’ in the TIMx_CCER register.



Configure TI2FP2 as trigger for the slave mode controller (TRGI) by writing TS=’110’ in
the TIMx_SMCR register.



TI2FP2 is used to start the counter by writing SMS to ‘110’ in the TIMx_SMCR register
(trigger mode).

For code example refer to the Appendix section A.8.16: One-Pulse mode code example.

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The OPM waveform is defined by writing the compare registers (taking into account the
clock frequency and the counter prescaler).


The tDELAY is defined by the value written in the TIMx_CCR1 register.



The tPULSE is defined by the difference between the auto-reload value and the compare
value (TIMx_ARR - TIMx_CCR1).



Let’s say you want to build a waveform with a transition from ‘0’ to ‘1’ when a compare
match occurs and a transition from ‘1’ to ‘0’ when the counter reaches the auto-reload
value. To do this you enable PWM mode 2 by writing OC1M=111 in the TIMx_CCMR1
register. You can optionally enable the preload registers by writing OC1PE=’1’ in the
TIMx_CCMR1 register and ARPE in the TIMx_CR1 register. In this case you have to
write the compare value in the TIMx_CCR1 register, the auto-reload value in the
TIMx_ARR register, generate an update by setting the UG bit and wait for external
trigger event on TI2. CC1P is written to ‘0’ in this example.

In our example, the DIR and CMS bits in the TIMx_CR1 register should be low.
You only want 1 pulse, so you write ‘1’ in the OPM bit in the TIMx_CR1 register to stop the
counter at the next update event (when the counter rolls over from the auto-reload value
back to 0).

Particular case: OCx fast enable
In One-pulse mode, the edge detection on TIx input set the CEN bit which enables the
counter. Then the comparison between the counter and the compare value makes the
output toggle. But several clock cycles are needed for these operations and it limits the
minimum delay tDELAY min we can get.
If you want to output a waveform with the minimum delay, you can set the OCxFE bit in the
TIMx_CCMRx register. Then OCxRef (and OCx) are forced in response to the stimulus,
without taking in account the comparison. Its new level is the same as if a compare match
had occurred. OCxFE acts only if the channel is configured in PWM1 or PWM2 mode.
For code example refer to the part of code conditioned by PULSE_WITHOUT_DELAY > 0 in
the Appendix section A.8.16: One-Pulse mode code example.

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17.4.14

RM0360

TIM15 external trigger synchronization
This section applies to STM32F030x8, STM32F070xB and STM32F030xC devices only.
The TIM15 timer can be synchronized with an external trigger in several modes: Reset
mode, Gated mode and Trigger mode.

Slave mode: Reset mode
The counter and its prescaler can be reinitialized in response to an event on a trigger input.
Moreover, if the URS bit from the TIMx_CR1 register is low, an update event UEV is
generated. Then all the preloaded registers (TIMx_ARR, TIMx_CCRx) are updated.
In the following example, the upcounter is cleared in response to a rising edge on TI1 input:


Configure the channel 1 to detect rising edges on TI1. Configure the input filter duration
(in this example, we don’t need any filter, so we keep IC1F=0000). The capture
prescaler is not used for triggering, so you don’t need to configure it. The CC1S bits
select the input capture source only, CC1S = 01 in the TIMx_CCMR1 register. Write
CC1P=0 in TIMx_CCER register to validate the polarity (and detect rising edges only).



Configure the timer in reset mode by writing SMS=100 in TIMx_SMCR register. Select
TI1 as the input source by writing TS=101 in TIMx_SMCR register.



Start the counter by writing CEN=1 in the TIMx_CR1 register.

For code example refer to the Appendix section A.8.12: Reset mode code example.
The counter starts counting on the internal clock, then behaves normally until TI1 rising
edge. When TI1 rises, the counter is cleared and restarts from 0. In the meantime, the
trigger flag is set (TIF bit in the TIMx_SR register) and an interrupt request, or a DMA
request can be sent if enabled (depending on the TIE and TDE bits in TIMx_DIER register).
The following figure shows this behavior when the auto-reload register TIMx_ARR=0x36.
The delay between the rising edge on TI1 and the actual reset of the counter is due to the
resynchronization circuit on TI1 input.
Figure 185. Control circuit in reset mode

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Slave mode: Gated mode
The counter can be enabled depending on the level of a selected input.
In the following example, the upcounter counts only when TI1 input is low:


Configure the channel 1 to detect low levels on TI1. Configure the input filter duration
(in this example, we don’t need any filter, so we keep IC1F=0000). The capture
prescaler is not used for triggering, so you don’t need to configure it. The CC1S bits
select the input capture source only, CC1S=01 in TIMx_CCMR1 register. Write
CC1P=1 in TIMx_CCER register to validate the polarity (and detect low level only).



Configure the timer in gated mode by writing SMS=101 in TIMx_SMCR register. Select
TI1 as the input source by writing TS=101 in TIMx_SMCR register.



Enable the counter by writing CEN=1 in the TIMx_CR1 register (in gated mode, the
counter doesn’t start if CEN=0, whatever is the trigger input level).

For code example refer to the Appendix section A.8.13: Gated mode code example.
The counter starts counting on the internal clock as long as TI1 is low and stops as soon as
TI1 becomes high. The TIF flag in the TIMx_SR register is set both when the counter starts
or stops.
The delay between the rising edge on TI1 and the actual stop of the counter is due to the
resynchronization circuit on TI1 input.
Figure 186. Control circuit in gated mode

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RM0360

Slave mode: Trigger mode
The counter can start in response to an event on a selected input.
In the following example, the upcounter starts in response to a rising edge on TI2 input:


Configure the channel 2 to detect rising edges on TI2. Configure the input filter duration
(in this example, we don’t need any filter, so we keep IC2F=0000). The capture
prescaler is not used for triggering, so you don’t need to configure it. The CC2S bits are
configured to select the input capture source only, CC2S=01 in TIMx_CCMR1 register.
Write CC2P=1 in TIMx_CCER register to validate the polarity (and detect low level
only).



Configure the timer in trigger mode by writing SMS=110 in TIMx_SMCR register. Select
TI2 as the input source by writing TS=110 in TIMx_SMCR register.

For code example refer to the Appendix section A.8.14: Trigger mode code example.
When a rising edge occurs on TI2, the counter starts counting on the internal clock and the
TIF flag is set.
The delay between the rising edge on TI2 and the actual start of the counter is due to the
resynchronization circuit on TI2 input.
Figure 187. Control circuit in trigger mode
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The TIM timers are linked together internally for timer synchronization or chaining. Refer to
Section 14.3.15: Timer synchronization on page 331 for details.

17.4.15

Timer synchronization (TIM15)
This section applies to STM32F030x8 STM32F070xB and STM32F030xC devices only.
The TIM timers are linked together internally for timer synchronization or chaining. Refer to
Section 14.3.15: Timer synchronization on page 331 for details.

17.4.16

Debug mode
When the microcontroller enters debug mode (Cortex™-M0 core halted), the TIMx counter
either continues to work normally or stops, depending on DBG_TIMx_STOP configuration
bit in DBG module.

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17.5

TIM15 registers
Refer to Section 1.1 on page 33 for a list of abbreviations used in register descriptions.

17.5.1

TIM15 control register 1 (TIM15_CR1)
Address offset: 0x00
Reset value: 0x0000

15

14

13

12

11

10

Res.

Res.

Res.

Res.

Res.

Res.

9

8

CKD[1:0]
rw

rw

7

6

5

4

3

2

1

0

ARPE

Res.

Res.

Res.

OPM

URS

UDIS

CEN

rw

rw

rw

rw

rw

Bits 15:10 Reserved, always read as 0.
Bits 9:8 CKD[1:0]: Clock division
This bit field indicates the division ratio between the timer clock (CK_INT) frequency and the
dead-time and sampling clock (tDTS) used by the dead-time generators and the digital filters
(TIx)
00: tDTS = tCK_INT
01: tDTS = 2*tCK_INT
10: tDTS = 4*tCK_INT
11: Reserved, do not program this value
Bit 7 ARPE: Auto-reload preload enable
0: TIMx_ARR register is not buffered
1: TIMx_ARR register is buffered
Bits 6:4 Reserved, always read as 0.
Bit 3 OPM: One-pulse mode
0: Counter is not stopped at update event
1: Counter stops counting at the next update event (clearing the bit CEN)

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RM0360

Bit 2 URS: Update request source
This bit is set and cleared by software to select the UEV event sources.
0: Any of the following events generate an update interrupt if enabled. These events can be:
–
Counter overflow/underflow
–
Setting the UG bit
–
Update generation through the slave mode controller
1: Only counter overflow/underflow generates an update interrupt if enabled
Bit 1 UDIS: Update disable
This bit is set and cleared by software to enable/disable UEV event generation.
0: UEV enabled. The Update (UEV) event is generated by one of the following events:
–
Counter overflow/underflow
–
Setting the UG bit
–
Update generation through the slave mode controller
Buffered registers are then loaded with their preload values.
1: UEV disabled. The Update event is not generated, shadow registers keep their value
(ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is
set or if a hardware reset is received from the slave mode controller.
Bit 0 CEN: Counter enable
0: Counter disabled
1: Counter enabled
Note: External clock and gated mode can work only if the CEN bit has been previously set by
software. However trigger mode can set the CEN bit automatically by hardware.

17.5.2

TIM15 control register 2 (TIM15_CR2)
Address offset: 0x04
Reset value: 0x0000

15

14

13

12

11

10

9

8

7

Res.

Res.

Res.

Res.

Res.

OIS2

OIS1N

OIS1

Res.

rw

rw

rw

Bit 15:11

6

5

4

MMS[2:0]
rw

rw

rw

3

2

1

0

CCDS

CCUS

Res.

CCPC

rw

rw

rw

Reserved, always read as 0.

Bit 10 OIS2: Output idle state 2 (OC2 output)
0: OC2=0 when MOE=0
1: OC2=1 when MOE=0
Note: This bit cannot be modified as long as LOCK level 1, 2 or 3 has been programmed
(LOCK bits in the TIMx_BKR register).
Bit 9 OIS1N: Output Idle state 1 (OC1N output)
0: OC1N=0 after a dead-time when MOE=0
1: OC1N=1 after a dead-time when MOE=0
Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed
(LOCK bits in TIMx_BKR register).
Bit 8 OIS1: Output Idle state 1 (OC1 output)
0: OC1=0 (after a dead-time if OC1N is implemented) when MOE=0
1: OC1=1 (after a dead-time if OC1N is implemented) when MOE=0
Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed
(LOCK bits in TIMx_BKR register).

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Bit 7

Reserved, always read as 0.

Bits 6:4 MMS[1:0]: Master mode selection
These bits allow to select the information to be sent in master mode to slave timers for
synchronization (TRGO). The combination is as follows:
000: Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO). If the
reset is generated by the trigger input (slave mode controller configured in reset mode) then
the signal on TRGO is delayed compared to the actual reset.
001: Enable - the Counter Enable signal CNT_EN is used as trigger output (TRGO). It is
useful to start several timers at the same time or to control a window in which a slave timer is
enable. The Counter Enable signal is generated by a logic OR between CEN control bit and
the trigger input when configured in gated mode. When the Counter Enable signal is
controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is
selected (see the MSM bit description in TIMx_SMCR register).
010: Update - The update event is selected as trigger output (TRGO). For instance a master
timer can then be used as a prescaler for a slave timer.
011: Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be
set (even if it was already high), as soon as a capture or a compare match occurred.
(TRGO).
100: Compare - OC1REF signal is used as trigger output (TRGO).
101: Compare - OC2REF signal is used as trigger output (TRGO).
Bit 3 CCDS: Capture/compare DMA selection
0: CCx DMA request sent when CCx event occurs
1: CCx DMA requests sent when update event occurs
Bit 2 CCUS: Capture/compare control update selection
0: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting
the COMG bit only.
1: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting
the COMG bit or when an rising edge occurs on TRGI.
Note: This bit acts only on channels that have a complementary output.
Bit 1 Reserved, always read as 0.
Bit 0 CCPC: Capture/compare preloaded control
0: CCxE, CCxNE and OCxM bits are not preloaded
1: CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are updated
only when COM bit is set.
Note: This bit acts only on channels that have a complementary output.

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17.5.3

RM0360

TIM15 slave mode control register (TIM15_SMCR)
Address offset: 0x08
Reset value: 0x0000

15

14

13

12

11

10

9

8

7

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

MSM
rw

Bits 15:8

6

5

4

TS[2:0]
rw

rw

3

2

Res.

1

0

SMS[2:0]

rw

rw

rw

rw

Reserved, always read as 0.

Bit 7 MSM: Master/slave mode
0: No action
1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect
synchronization between the current timer and its slaves (through TRGO). It is useful if we
want to synchronize several timers on a single external event.
Bits 6:4 TS[2:0]: Trigger selection
This bit field selects the trigger input to be used to synchronize the counter.
000: Reserved
001: Internal Trigger 1 (ITR1)
010: Internal Trigger 2 (ITR2)
011: Internal Trigger 3 (ITR3)
100: TI1 Edge Detector (TI1F_ED)
101: Filtered Timer Input 1 (TI1FP1)
110: Filtered Timer Input 2 (TI2FP2)
See Table 55: TIMx Internal trigger connection on page 432 for more details on ITRx meaning
for each Timer.
Note: These bits must be changed only when they are not used (e.g. when SMS=000) to
avoid wrong edge detections at the transition.
Bit 3

Reserved, always read as 0.

Bits 2:0 SMS: Slave mode selection
When external signals are selected the active edge of the trigger signal (TRGI) is linked to the
polarity selected on the external input (see Input Control register and Control Register
description.
000: Slave mode disabled - if CEN = ‘1’ then the prescaler is clocked directly by the internal
clock.
100: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter
and generates an update of the registers.
101: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The
counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of
the counter are controlled.
110: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not
reset). Only the start of the counter is controlled.
111: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.
Note: The gated mode must not be used if TI1F_ED is selected as the trigger input
(TS=’100’). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the
gated mode checks the level of the trigger signal.

Table 55. TIMx Internal trigger connection

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ITR2 (TS = 010)

ITR3 (TS = 011)

TIM15

TIM3

TIM16_OC

TIM17_OC

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17.5.4

TIM15 DMA/interrupt enable register (TIM15_DIER)
Address offset: 0x0C
Reset value: 0x0000

15

14

13

12

11

Res.

TDE

Res.

Res.

Res.

10

rw

rw

Bit 15

9

CC2DE CC1DE
rw

8

7

6

5

4

3

2

1

0

UDE

BIE

TIE

COMIE

Res.

Res.

CC2IE

CC1IE

UIE

rw

rw

rw

rw

rw

rw

rw

Reserved, always read as 0.

Bit 14 TDE: Trigger DMA request enable
0: Trigger DMA request disabled
1: Trigger DMA request enabled
Bits 13:11 Reserved, always read as 0.
Bit 10 CC2DE: Capture/Compare 2 DMA request enable
0: CC2 DMA request disabled
1: CC2 DMA request enabled
Bit 9 CC1DE: Capture/Compare 1 DMA request enable
0: CC1 DMA request disabled
1: CC1 DMA request enabled
Bit 8 UDE: Update DMA request enable
0: Update DMA request disabled
1: Update DMA request enabled
Bit 7 BIE: Break interrupt enable
0: Break interrupt disabled
1: Break interrupt enabled
Bit 6 TIE: Trigger interrupt enable
0: Trigger interrupt disabled
1: Trigger interrupt enabled
Bit 5 COMIE: COM interrupt enable
0: COM interrupt disabled
1: COM interrupt enabled
Bits 4:3

Reserved, always read as 0.

Bit 2 CC2IE: Capture/Compare 2 interrupt enable
0: CC2 interrupt disabled
1: CC2 interrupt enabled
Bit 1 CC1IE: Capture/Compare 1 interrupt enable
0: CC1 interrupt disabled
1: CC1 interrupt enabled
Bit 0 UIE: Update interrupt enable
0: Update interrupt disabled
1: Update interrupt enabled

17.5.5

TIM15 status register (TIM15_SR)
Address offset: 0x10

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RM0360

Reset value: 0x0000
15

14

13

12

11

Res.

Res.

Res.

Res.

Res.

10

rc_w0

Bits 15:11

9

CC2OF CC1OF
rc_w0

8

7

6

5

4

3

2

1

0

Res.

BIF

TIF

COMIF

Res.

Res.

CC2IF

CC1IF

UIF

rc_w0

rc_w0

rc_w0

rc_w0

rc_w0

rc_w0

Reserved, always read as 0.

Bit 10 CC2OF: Capture/Compare 2 overcapture flag
refer to CC1OF description
Bit 9 CC1OF: Capture/Compare 1 overcapture flag
This flag is set by hardware only when the corresponding channel is configured in input
capture mode. It is cleared by software by writing it to ‘0’.
0: No overcapture has been detected
1: The counter value has been captured in TIMx_CCR1 register while CC1IF flag was
already set
Bit 8

Reserved, always read as 0.

Bit 7 BIF: Break interrupt flag
This flag is set by hardware as soon as the break input goes active. It can be cleared by
software if the break input is not active.
0: No break event occurred
1: An active level has been detected on the break input
Bit 6 TIF: Trigger interrupt flag
This flag is set by hardware on trigger event (active edge detected on TRGI input when the
slave mode controller is enabled in all modes but gated mode, both edges in case gated mode
is selected). It is cleared by software.
0: No trigger event occurred
1: Trigger interrupt pending
Bit 5 COMIF: COM interrupt flag
This flag is set by hardware on a COM event (once the capture/compare control bits –CCxE,
CCxNE, OCxM– have been updated). It is cleared by software by writing it to ‘0’.
0: No COM event occurred
1: COM interrupt pending
Bits 5:3 Reserved, always read as 0.

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Bit 2 CC2IF: Capture/Compare 2 interrupt flag
refer to CC1IF description
Bit 1 CC1IF: Capture/Compare 1 interrupt flag
If channel CC1 is configured as output:
This flag is set by hardware when the counter matches the compare value, with some
exception in center-aligned mode (refer to the CMS bits in the TIMx_CR1 register description).
It is cleared by software.
0: No match.
1: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register.
When the contents of TIMx_CCR1 are greater than the contents of TIMx_ARR, the CC1IF
bit goes high on the counter overflow (in upcounting and up/down-counting modes) or
underflow (in downcounting mode)
If channel CC1 is configured as input:
This bit is set by hardware on a capture. It is cleared by software or by reading the
TIMx_CCR1 register.
0: No input capture occurred
1: The counter value has been captured in TIMx_CCR1 register (An edge has been
detected on IC1 which matches the selected polarity)
Bit 0 UIF: Update interrupt flag
This bit is set by hardware on an update event. It is cleared by software.
0: No update occurred.
1: Update interrupt pending. This bit is set by hardware when the registers are updated:
–At overflow regarding the repetition counter value (update if repetition counter = 0) and if
the UDIS=0 in the TIMx_CR1 register.
–When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0
and UDIS=0 in the TIMx_CR1 register.
–When CNT is reinitialized by a trigger event (refer to Section 17.5.3: TIM15 slave mode
control register (TIM15_SMCR)), if URS=0 and UDIS=0 in the TIMx_CR1 register.

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17.5.6

RM0360

TIM15 event generation register (TIM15_EGR)
Address offset: 0x14
Reset value: 0x0000

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

BG

TG

COMG

Res.

Res.

CC2G

CC1G

UG

w

w

rw

w

w

w

Bits 15:8

Reserved, always read as 0.

Bit 7 BG: Break generation
This bit is set by software in order to generate an event, it is automatically cleared by
hardware.
0: No action
1: A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or
DMA transfer can occur if enabled.
Bit 6 TG: Trigger generation
This bit is set by software in order to generate an event, it is automatically cleared by
hardware.
0: No action
1: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if
enabled
Bit 5 COMG: Capture/Compare control update generation
This bit can be set by software, it is automatically cleared by hardware.
0: No action
1: When the CCPC bit is set, it is possible to update the CCxE, CCxNE and OCxM bits
Note: This bit acts only on channels that have a complementary output.
Bits 4:3 Reserved, always read as 0.
Bit 2 CC2G: Capture/Compare 2 generation
Refer to CC1G description
Bit 1 CC1G: Capture/Compare 1 generation
This bit is set by software in order to generate an event, it is automatically cleared by
hardware.
0: No action
1: A capture/compare event is generated on channel 1:
If channel CC1 is configured as output:
CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled.
If channel CC1 is configured as input:
The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set, the
corresponding interrupt or DMA request is sent if enabled. The CC1OF flag is set if the CC1IF
flag was already high.
Bit 0 UG: Update generation
This bit can be set by software, it is automatically cleared by hardware.
0: No action.
1: Reinitialize the counter and generates an update of the registers. Note that the prescaler
counter is cleared too (anyway the prescaler ratio is not affected). The counter is cleared if
the center-aligned mode is selected or if DIR=0 (upcounting), else it takes the auto-reload
value (TIMx_ARR) if DIR=1 (downcounting).

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17.5.7

TIM15 capture/compare mode register 1 (TIM15_CCMR1)
Address offset: 0x18
Reset value: 0x0000
The channels can be used in input (capture mode) or in output (compare mode). The
direction of a channel is defined by configuring the corresponding CCxS bits. All the other
bits of this register have a different function in input and in output mode. For a given bit,
OCxx describes its function when the channel is configured in output, ICxx describes its
function when the channel is configured in input. So you must take care that the same bit
can have a different meaning for the input stage and for the output stage.

15

14

Res.

13

12

OC2M[2:0]
IC2F[3:0]

rw

rw

rw

11

10

OC2
PE

OC2
FE

9

8

CC2S[1:0]

7

6

Res.

rw

rw

4

OC1M[2:0]

IC2PSC[1:0]
rw

5

IC1F[3:0]
rw

rw

rw

rw

rw

3

2

OC1
PE

OC1
FE

1

0

CC1S[1:0]

IC1PSC[1:0]
rw

rw

rw

rw

rw

Output compare mode:
Bit 15

Reserved, always read as 0.

Bits 14:12 OC2M[2:0]: Output Compare 2 mode
Bit 11 OC2PE: Output Compare 2 preload enable
Bit 10 OC2FE: Output Compare 2 fast enable
Bits 9:8 CC2S[1:0]: Capture/Compare 2 selection
This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC2 channel is configured as output.
01: CC2 channel is configured as input, IC2 is mapped on TI2.
10: CC2 channel is configured as input, IC2 is mapped on TI1.
11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if
an internal trigger input is selected through the TS bit (TIMx_SMCR register)
Note: CC2S bits are writable only when the channel is OFF (CC2E = ‘0’ in TIMx_CCER).
Bit 7

Reserved, always read as 0.

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Bits 6:4 OC1M: Output Compare 1 mode
These bits define the behavior of the output reference signal OC1REF from which OC1 and
OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on
CC1P and CC1NP bits.
000: Frozen - The comparison between the output compare register TIMx_CCR1 and the
counter TIMx_CNT has no effect on the outputs.
001: Set channel 1 to active level on match. OC1REF signal is forced high when the counter
TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).
010: Set channel 1 to inactive level on match. OC1REF signal is forced low when the
counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).
011: Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1.
100: Force inactive level - OC1REF is forced low.
101: Force active level - OC1REF is forced high.
110: PWM mode 1 - In upcounting, channel 1 is active as long as TIMx_CNTTIMx_CCR1 else active (OC1REF=’1’).
111: PWM mode 2 - In upcounting, channel 1 is inactive as long as TIMx_CNTTIMx_CCR1 else
inactive.
Note: 1: These bits can not be modified as long as LOCK level 3 has been programmed
(LOCK bits in TIMx_BDTR register) and CC1S=’00’ (the channel is configured in
output).
2: In PWM mode 1 or 2, the OCREF level changes only when the result of the
comparison changes or when the output compare mode switches from “frozen” mode
to “PWM” mode.
Bit 3 OC1PE: Output Compare 1 preload enable
0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the
new value is taken in account immediately.
1: Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload
register. TIMx_CCR1 preload value is loaded in the active register at each update event.
Note: 1: These bits can not be modified as long as LOCK level 3 has been programmed
(LOCK bits in TIMx_BDTR register) and CC1S=’00’ (the channel is configured in
output).
2: The PWM mode can be used without validating the preload register only in one
pulse mode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed.
Bit 2 OC1FE: Output Compare 1 fast enable
This bit is used to accelerate the effect of an event on the trigger in input on the CC output.
0: CC1 behaves normally depending on counter and CCR1 values even when the trigger is
ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is
5 clock cycles.
1: An active edge on the trigger input acts like a compare match on CC1 output. Then, OC is
set to the compare level independently of the result of the comparison. Delay to sample the
trigger input and to activate CC1 output is reduced to 3 clock cycles. OCFE acts only if the
channel is configured in PWM1 or PWM2 mode.
Bits 1:0 CC1S: Capture/Compare 1 selection
This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC1 channel is configured as output.
01: CC1 channel is configured as input, IC1 is mapped on TI1.
10: CC1 channel is configured as input, IC1 is mapped on TI2.
11: CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if
an internal trigger input is selected through TS bit (TIMx_SMCR register)
Note: CC1S bits are writable only when the channel is OFF (CC1E = ‘0’ in TIMx_CCER).

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Input capture mode
Bits 15:12 IC2F: Input capture 2 filter
Bits 11:10 IC2PSC[1:0]: Input capture 2 prescaler
Bits 9:8 CC2S: Capture/Compare 2 selection
This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC2 channel is configured as output
01: CC2 channel is configured as input, IC2 is mapped on TI2
10: CC2 channel is configured as input, IC2 is mapped on TI1
11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if an
internal trigger input is selected through TS bit (TIMx_SMCR register)
Note: CC2S bits are writable only when the channel is OFF (CC2E = ‘0’ in TIMx_CCER).
Bits 7:4 IC1F[3:0]: Input capture 1 filter
This bit-field defines the frequency used to sample TI1 input and the length of the digital filter applied to
TI1. The digital filter is made of an event counter in which N consecutive events are needed to validate
a transition on the output:
0000: No filter, sampling is done at fDTS
0001: fSAMPLING = fCK_INT, N = 2
0010: fSAMPLING = fCK_INT, N = 4
0011: fSAMPLING = fCK_INT, N = 8
0100: fSAMPLING = fDTS / 2, N = 6
0101: fSAMPLING = fDTS / 2, N = 8
0110: fSAMPLING = fDTS / 4, N = 6
0111: fSAMPLING = fDTS / 4, N = 8
1000: fSAMPLING = fDTS / 8, N = 6
1001: fSAMPLING = fDTS / 8, N = 8
1010: fSAMPLING = fDTS / 16, N = 5
1011: fSAMPLING = fDTS / 16, N = 6
1100: fSAMPLING = fDTS / 16, N = 8
1101: fSAMPLING = fDTS / 32, N = 5
1110: fSAMPLING = fDTS / 32, N = 6
1111: fSAMPLING = fDTS / 32, N = 8
Note: Care must be taken that fDTS is replaced in the formula by CK_INT when ICxF[3:0] = 1, 2 or 3.
Bits 3:2 IC1PSC: Input capture 1 prescaler
This bit-field defines the ratio of the prescaler acting on CC1 input (IC1).
The prescaler is reset as soon as CC1E=’0’ (TIMx_CCER register).
00: no prescaler, capture is done each time an edge is detected on the capture input
01: capture is done once every 2 events
10: capture is done once every 4 events
11: capture is done once every 8 events
Bits 1:0 CC1S: Capture/Compare 1 Selection
This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC1 channel is configured as output
01: CC1 channel is configured as input, IC1 is mapped on TI1
10: CC1 channel is configured as input, IC1 is mapped on TI2
11: CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if an
internal trigger input is selected through TS bit (TIMx_SMCR register)
Note: CC1S bits are writable only when the channel is OFF (CC1E = ‘0’ in TIMx_CCER).

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17.5.8

RM0360

TIM15 capture/compare enable register (TIM15_CCER)
Address offset: 0x20
Reset value: 0x0000

15

14

13

12

11

10

9

8

7

6

5

4

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

CC1NP

Res.

CC2P

CC2E

rw

rw

rw

Bits 15:8

3

2

CC1NP CC1NE
rw

rw

1

0

CC1P

CC1E

rw

rw

Reserved, always read as 0.

Bit 7 CC2NP: Capture/Compare 2 complementary output polarity
refer to CC1NP description
Bit 6 Reserved, always read as 0.
Bit 5 CC2P: Capture/Compare 2 output polarity
Refer to CC1P description
Bit 4 CC2E: Capture/Compare 2 output enable
Refer to CC1E description
Bit 3 CC1NP: Capture/Compare 1 complementary output polarity
0: OC1N active high
1: OC1N active low
Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits
in TIMx_BDTR register) and CC1S=”00” (the channel is configured in output).

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Bit 2 CC1NE: Capture/Compare 1 complementary output enable
0: Off - OC1N is not active. OC1N level is then function of MOE, OSSI, OSSR, OIS1, OIS1N
and CC1E bits.
1: On - OC1N signal is output on the corresponding output pin depending on MOE, OSSI,
OSSR, OIS1, OIS1N and CC1E bits.
Bit 1 CC1P: Capture/Compare 1 output polarity
CC1 channel configured as output:
0: OC1 active high
1: OC1 active low
CC1 channel configured as input:
The CC1NP/CC1P bits select the polarity of TI1FP1 and TI2FP1 for trigger or capture
operations.
00: noninverted/rising edge: circuit is sensitive to TIxFP1's rising edge (capture, trigger in
reset or trigger mode), TIxFP1 is not inverted (trigger in gated mode).
01: inverted/falling edge: circuit is sensitive to TIxFP1's falling edge (capture, trigger in reset,
or trigger mode), TIxFP1 is inverted (trigger in gated mode).
10: reserved, do not use this configuration.
11: noninverted/both edges: circuit is sensitive to both the rising and falling edges of TIxFP1
(capture, trigger in reset or trigger mode), TIxFP1 is not inverted (trigger in gated mode).
Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits
in TIMx_BDTR register).
Bit 0 CC1E: Capture/Compare 1 output enable
CC1 channel configured as output:
0: Off - OC1 is not active. OC1 level is then function of MOE, OSSI, OSSR, OIS1, OIS1N
and CC1NE bits.
1: On - OC1 signal is output on the corresponding output pin depending on MOE, OSSI,
OSSR, OIS1, OIS1N and CC1NE bits.
CC1 channel configured as input:
This bit determines if a capture of the counter value can actually be done into the input
capture/compare register 1 (TIMx_CCR1) or not.
0: Capture disabled
1: Capture enabled

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Table 56. Output control bits for complementary OCx and OCxN channels with break feature
Output states(1)

Control bits
MOE bit OSSI bit OSSR bit CCxE bit CCxNE bit OCx output state

1

0

OCxN output state

0

0

0

Output Disabled (not driven Output Disabled (not driven by
by the timer)
the timer)
OCx=0, OCx_EN=0
OCxN=0, OCxN_EN=0

0

0

1

Output Disabled (not driven OCxREF + Polarity
by the timer)
OCxN=OCxREF xor CCxNP,
OCxN_EN=1
OCx=0, OCx_EN=0

0

1

0

OCxREF + Polarity
OCx=OCxREF xor CCxP,
OCx_EN=1

Output Disabled (not driven by
the timer)
OCxN=0, OCxN_EN=0

0

1

1

OCREF + Polarity + deadtime
OCx_EN=1

Complementary to OCREF (not
OCREF) + Polarity + dead-time
OCxN_EN=1

1

0

0

Output Disabled (not driven Output Disabled (not driven by
by the timer)
the timer)
OCx=CCxP, OCx_EN=0
OCxN=CCxNP, OCxN_EN=0

1

0

1

Off-State (output enabled
with inactive state)
OCx=CCxP, OCx_EN=1

OCxREF + Polarity
OCxN=OCxREF xor CCxNP,
OCxN_EN=1

1

1

0

OCxREF + Polarity
OCx=OCxREF xor CCxP,
OCx_EN=1

Off-State (output enabled with
inactive state)
OCxN=CCxNP, OCxN_EN=1

1

1

1

OCREF + Polarity + deadtime
OCx_EN=1

Complementary to OCREF (not
OCREF) + Polarity + dead-time
OCxN_EN=1

0

0

0

0

0

1

0

1

0

0

1

1

0

0

1

0

1

1

1

0

1

1

1

X

1

X

Output Disabled (not driven by the timer)
Asynchronously: OCx=CCxP, OCx_EN=0, OCxN=CCxNP,
OCxN_EN=0
Then if the clock is present: OCx=OISx and OCxN=OISxN
after a dead-time, assuming that OISx and OISxN do not
correspond to OCX and OCxN both in active state.
Off-State (output enabled with inactive state)
Asynchronously: OCx=CCxP, OCx_EN=1, OCxN=CCxNP,
OCxN_EN=1
Then if the clock is present: OCx=OISx and OCxN=OISxN
after a dead-time, assuming that OISx and OISxN do not
correspond to OCX and OCxN both in active state

1. When both outputs of a channel are not used (CCxE = CCxNE = 0), the OISx, OISxN, CCxP and CCxNP bits must be kept
cleared.

Note:

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The state of the external I/O pins connected to the complementary OCx and OCxN channels
depends on the OCx and OCxN channel state and the GPIO and AFIO registers.

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17.5.9

TIM15 counter (TIM15_CNT)
Address offset: 0x24
Reset value: 0x0000

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

rw

rw

rw

rw

rw

rw

rw

rw

7

6

5

4

3

2

1

0

rw

rw

rw

rw

rw

rw

rw

CNT[15:0]
rw

rw

rw

Bits 15:0

17.5.10

rw

rw

rw

rw

rw

CNT[15:0]: Counter value

TIM15 prescaler (TIM15_PSC)
Address offset: 0x28
Reset value: 0x0000

15

14

13

12

11

10

9

8

PSC[15:0]
rw

rw

rw

rw

rw

rw

rw

rw

rw

Bits 15:0 PSC[15:0]: Prescaler value
The counter clock frequency (CK_CNT) is equal to fCK_PSC / (PSC[15:0] + 1).
PSC contains the value to be loaded in the active prescaler register at each update event
(including when the counter is cleared through UG bit of TIMx_EGR register or through trigger
controller when configured in “reset mode”).

17.5.11

TIM15 auto-reload register (TIM15_ARR)
Address offset: 0x2C
Reset value: 0xFFFF

15

14

13

12

11

10

9

8

rw

rw

rw

rw

rw

rw

rw

rw

7

6

5

4

3

2

1

0

rw

rw

rw

rw

rw

rw

rw

ARR[15:0]
rw

Bits 15:0 ARR[15:0]: Auto-reload value
ARR is the value to be loaded in the actual auto-reload register.
Refer to the Section 16.3.1: Time-base unit on page 375 for more details about ARR update
and behavior.
The counter is blocked while the auto-reload value is null.

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TIM15 repetition counter register (TIM15_RCR)
Address offset: 0x30
Reset value: 0x0000

15

14

13

12

11

10

9

8

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

7

6

5

4

3

2

1

0

rw

rw

rw

REP[7:0]
rw

rw

rw

rw

rw

Bits 15:8 Reserved, always read as 0.
Bits 7:0 REP[7:0]: Repetition counter value
These bits allow the user to set-up the update rate of the compare registers (i.e. periodic
transfers from preload to active registers) when preload registers are enable, as well as the
update interrupt generation rate, if this interrupt is enable.
Each time the REP_CNT related downcounter reaches zero, an update event is generated
and it restarts counting from REP value. As REP_CNT is reloaded with REP value only at the
repetition update event U_RC, any write to the TIMx_RCR register is not taken in account until
the next repetition update event.
It means in PWM mode (REP+1) corresponds to the number of PWM periods in edge-aligned
mode.

17.5.13

TIM15 capture/compare register 1 (TIM15_CCR1)
Address offset: 0x34
Reset value: 0x0000

15

14

13

12

11

10

9

8

rw

rw

rw

rw

rw

rw

rw

7

6

5

4

3

2

1

0

rw

rw

rw

rw

rw

rw

rw

CCR1[15:0]
rw

rw

Bits 15:0 CCR1[15:0]: Capture/Compare 1 value
If channel CC1 is configured as output:
CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value).
It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (bit
OC1PE). Else the preload value is copied in the active capture/compare 1 register when an
update event occurs.
The active capture/compare register contains the value to be compared to the counter
TIMx_CNT and signaled on OC1 output.

If channel CC1 is configured as input:
CCR1 is the counter value transferred by the last input capture 1 event (IC1).

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17.5.14

TIM15 capture/compare register 2 (TIM15_CCR2)
Address offset: 0x38
Reset value: 0x0000

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

rw

rw

rw

rw

rw

rw

rw

CCR2[15:0]
rw

rw

rw

rw

rw

rw

rw

rw

rw

Bits 15:0 CCR2[15:0]: Capture/Compare 2 value
If channel CC2 is configured as output:
CCR2 is the value to be loaded in the actual capture/compare 2 register (preload value).
It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register (bit
OC2PE). Else the preload value is copied in the active capture/compare 2 register when an
update event occurs.
The active capture/compare register contains the value to be compared to the counter
TIMx_CNT and signalled on OC2 output.
If channel CC2 is configured as input:
CCR2 is the counter value transferred by the last input capture 2 event (IC2).

17.5.15

TIM15 break and dead-time register (TIM15_BDTR)
Address offset: 0x44
Reset value: 0x0000

15

14

13

12

11

10

MOE

AOE

BKP

BKE

OSSR

OSSI

rw

rw

rw

rw

rw

rw

Note:

9

8

7

6

5

LOCK[1:0]
rw

rw

4

3

2

1

0

rw

rw

rw

DTG[7:0]
rw

rw

rw

rw

rw

As the bits AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] can be write-locked depending on
the LOCK configuration, it can be necessary to configure all of them during the first write
access to the TIMx_BDTR register.

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Bit 15 MOE: Main output enable
This bit is cleared asynchronously by hardware as soon as the break input is active. It is set by
software or automatically depending on the AOE bit. It is acting only on the channels which are
configured in output.
0: OC and OCN outputs are disabled or forced to idle state
1: OC and OCN outputs are enabled if their respective enable bits are set (CCxE, CCxNE in
TIMx_CCER register)
See OC/OCN enable description for more details (Section 17.5.8: TIM15 capture/compare
enable register (TIM15_CCER) on page 440).
Bit 14 AOE: Automatic output enable
0: MOE can be set only by software
1: MOE can be set by software or automatically at the next update event (if the break input is
not be active)
Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits
in TIMx_BDTR register).
Bit 13 BKP: Break polarity
0: Break input BRK is active low
1: Break input BRK is active high
Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits
in TIMx_BDTR register).
Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
Bit 12 BKE: Break enable
0: Break inputs (BRK and CCS clock failure event) disabled
1; Break inputs (BRK and CCS clock failure event) enabled
Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in
TIMx_BDTR register).
Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
Bit 11 OSSR: Off-state selection for Run mode
This bit is used when MOE=1 on channels having a complementary output which are
configured as outputs. OSSR is not implemented if no complementary output is implemented
in the timer.
See OC/OCN enable description for more details (Section 17.5.8: TIM15 capture/compare
enable register (TIM15_CCER) on page 440).
0: When inactive, OC/OCN outputs are disabled (OC/OCN enable output signal=0)
1: When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1
or CCxNE=1. Then, OC/OCN enable output signal=1
Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK
bits in TIMx_BDTR register).

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Bit 10 OSSI: Off-state selection for Idle mode
This bit is used when MOE=0 on channels configured as outputs.
See OC/OCN enable description for more details (Section 17.5.8: TIM15 capture/compare
enable register (TIM15_CCER) on page 440).
0: When inactive, OC/OCN outputs are disabled (OC/OCN enable output signal=0)
1: When inactive, OC/OCN outputs are forced first with their idle level as soon as CCxE=1 or
CCxNE=1. OC/OCN enable output signal=1)
Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK
bits in TIMx_BDTR register).
Bits 9:8 LOCK[1:0]: Lock configuration
These bits offer a write protection against software errors.
00: LOCK OFF - No bit is write protected
01: LOCK Level 1 = DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2
register and BKE/BKP/AOE bits in TIMx_BDTR register can no longer be written
10: LOCK Level 2 = LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER
register, as long as the related channel is configured in output through the CCxS bits) as well
as OSSR and OSSI bits can no longer be written.
11: LOCK Level 3 = LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in
TIMx_CCMRx registers, as long as the related channel is configured in output through the
CCxS bits) can no longer be written.
Note: The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register
has been written, their content is frozen until the next reset.
Bits 7:0 DTG[7:0]: Dead-time generator setup
This bit-field defines the duration of the dead-time inserted between the complementary
outputs. DT correspond to this duration.
DTG[7:5]=0xx => DT=DTG[7:0]x tdtg with tdtg=tDTS
DTG[7:5]=10x => DT=(64+DTG[5:0])xtdtg with Tdtg=2xtDTS
DTG[7:5]=110 => DT=(32+DTG[4:0])xtdtg with Tdtg=8xtDTS
DTG[7:5]=111 => DT=(32+DTG[4:0])xtdtg with Tdtg=16xtDTS
Example if TDTS=125ns (8MHz), dead-time possible values are:
0 to 15875 ns by 125 ns steps,
16 µs to 31750 ns by 250 ns steps,
32 µs to 63 µs by 1 µs steps,
64 µs to 126 µs by 2 µs steps
Note: This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed
(LOCK bits in TIMx_BDTR register).

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General-purpose timers (TIM15/16/17)

17.5.16

RM0360

TIM15 DMA control register (TIM15_DCR)
Address offset: 0x48
Reset value: 0x0000

15

14

13

Res.

Res.

Res.

12

11

10

9

8

DBL[4:0]
rw

rw

rw

rw

7

6

5

Res.

Res.

Res.

rw

4

3

2

1

0

rw

rw

DBA[4:0]
rw

rw

rw

Bits 15:13 Reserved, always read as 0.
Bits 12:8 DBL[4:0]: DMA burst length
This 5-bit vector defines the length of DMA transfers (the timer recognizes a burst transfer
when a read or a write access is done to the TIMx_DMAR address).
00000: 1 transfer,
00001: 2 transfers,
00010: 3 transfers,
...
10001: 18 transfers.
Bits 7:5 Reserved, always read as 0.
Bits 4:0 DBA[4:0]: DMA base address
This 5-bits vector defines the base-address for DMA transfers (when read/write access are
done through the TIMx_DMAR address). DBA is defined as an offset starting from the
address of the TIMx_CR1 register.
Example:
00000: TIMx_CR1,
00001: TIMx_CR2,
00010: TIMx_SMCR,
...

17.5.17

TIM15 DMA address for full transfer (TIM15_DMAR)
Address offset: 0x4C
Reset value: 0x0000

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

rw

rw

rw

rw

rw

rw

rw

DMAB[15:0]
rw

rw

rw

rw

rw

rw

rw

rw

rw

Bits 15:0 DMAB[15:0]: DMA register for burst accesses
A read or write operation to the DMAR register accesses the register located at the address
(TIMx_CR1 address) + (DBA + DMA index) x 4
where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base
address configured in TIMx_DCR register, DMA index is automatically controlled by the
DMA transfer, and ranges from 0 to DBL (DBL configured in TIMx_DCR).

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0x34

TIM15_CCR1

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

TIM15_RCR

Reset value

DocID025023 Rev 4

1

1

1

1

1

1

1

1

Res.

Res.

Res.

Res.

Res.

Reset value

Res.

Reset value

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Reset value

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

TIM15_ARR

Res.

0x30
TIM15_PSC

Res.

0x2C
TIM15_CNT

Res.

0x28
Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

0
0
0

Res.
Res.
Res.

0

0

0
0

0

0
0

0

0
0

0

0
0

0

0
0

0

0

Reset value

0

0

0
0

0

Reset value

0
0

0

1

0

0
0

PSC[15:0]

0

ARR[15:0]

1

0

0
CC1E

CNT[15:0]
CC1P

0
CC1NE

CC2S
[1:0]
Res.

0
0

0
0
0

OC1M
[2:0]

0 0 0 0
0 0 0
IC2
CC2S
PSC
IC1F[3:0]
[1:0]
[1:0]
0 0 0 0 0 0 0 0

CC2IF
CC1IF
UIF

0
0
0

CC1G
UG

0

CC2G

0
CC2IE
CC1IE
UIE

Res.

0

Res.

Res.

TS[2:0]

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

OPM
URS
UDIS
CEN

0
0
0

CCUS
Res.
CCPC

Res.

Res.

Res.

ARPE

0

CCDS

0

OC1FE

0

Res.

0

Res.

OIS1
MSM

Res.

OIS1N

Res.
Res.

OIS2

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

MMS[2:0]

OC1PE

Res.

0
Res.

COMIE
0

COMIF

0

COMG

TIE

0
TIF

BIE

0

TG

UDE

0
BIF

0

BG

Res.

CC1DE

CC1OF
0

Res.

CC2DE

CC2OF
0

Res.

Res.

Res.

Reset value
0

CC1NP

OC2FE

Res.

Res.

Res.

TDE

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

0

0

CC2E

IC2F[3:0]

0

0

CC2P

0

0

0

Res.

0
Res.

Reset value

Res.

OC2M
[2:0]
OC2PE

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

0

CKD
[1:0]

CC2NP

0
Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Reset value

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Reset value

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Reset value

Res.

0

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

TIM15_CCER

Res.

0x24
Res.

0x20
Reset value
TIM15_CCMR1
Input capture
mode
Reset value

Res.

Reset value
TIM15_CCMR1
Output compare
mode

Res.

0x18
TIM15_EGR

Res.

0x14
TIM15_SR

Res.

0x10
TIM15_DIER

Res.

0x0C
TIM15_SMCR

Res.

0x08
TIM15_CR2

Res.

0x04
TIM15_CR1

Res.

0x00

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0

Register

Res.

Offset

Res.

17.5.18

Res.

RM0360
General-purpose timers (TIM15/16/17)

TIM15 register map
TIM15 registers are mapped as 16-bit addressable registers as described in the table
below:
Table 57. TIM15 register map and reset values

0
0
0

SMS[2:0]
0
0
0

0
0
0

0
0
0

CC1S
[1:0]

0 0 0 0
IC1
CC1S
PSC
[1:0]
[1:0]
0 0 0 0

0
0
0
0
0
0

0
0
0
0
0
0

0
0
0
0
0
0

1

1

1

1

1

1

REP[7:0]

CCR1[15:0]

0

0

0

0

0

0

0

0

0

0

0

0

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General-purpose timers (TIM15/16/17)

RM0360

Res.

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

DBA[4:0]
0

0

0

0

0

0

0

0

0

0

DMAB[15:0]
0

DocID025023 Rev 4

0

DT[7:0]

0

0

0

0

0

0

0

Refer to Section 2.2.2 on page 37 for the register boundary addresses.

450/779

0

LOCK
[1:0]

DBL[4:0]

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Reset value

0

Res.

BKE

OSSR
0

0

Res.

BKP

0

0

Res.

AOE

0
Res.

0

0

0
Res.

TIM15_DMAR

0

0

Reset value
0x4C

0

Res.

0

MOE

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

TIM15_DCR

Res.

0x48

Res.

Reset value

0

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

TIM15_BDTR

Res.

0x44

0
Res.

Reset value

CCR2[15:0]

OSSI

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

TIM15_CCR2

Res.

0x38

Register

Res.

Offset

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0

Table 57. TIM15 register map and reset values (continued)

0

0

0

RM0360

General-purpose timers (TIM15/16/17)

17.6

TIM16 and TIM17 registers
Refer to Section 1.1 on page 33 for a list of abbreviations used in register descriptions.

17.6.1

TIM16 and TIM17 control register 1 (TIM16_CR1 and TIM17_CR1)
Address offset: 0x00
Reset value: 0x0000

15

14

13

12

11

10

Res.

Res.

Res.

Res.

Res.

Res.

9

8

CKD[1:0]
rw

rw

7

6

5

4

3

2

1

0

ARPE

Res.

Res.

Res.

OPM

URS

UDIS

CEN

rw

rw

rw

rw

rw

Bits 15:10 Reserved, always read as 0.
Bits 9:8 CKD[1:0]: Clock division
This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and the
dead-time and sampling clock (tDTS)used by the dead-time generators and the digital filters
(TIx),
00: tDTS=tCK_INT
01: tDTS=2*tCK_INT
10: tDTS=4*tCK_INT
11: Reserved, do not program this value
Bit 7 ARPE: Auto-reload preload enable
0: TIMx_ARR register is not buffered
1: TIMx_ARR register is buffered
Bits 6:4 Reserved, always read as 0.
Bit 3 OPM: One pulse mode
0: Counter is not stopped at update event
1: Counter stops counting at the next update event (clearing the bit CEN)

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General-purpose timers (TIM15/16/17)

RM0360

Bit 2 URS: Update request source
This bit is set and cleared by software to select the UEV event sources.
0: Any of the following events generate an update interrupt or DMA request if enabled.
These events can be:
–
Counter overflow/underflow
–
Setting the UG bit
–
Update generation through the slave mode controller
1: Only counter overflow/underflow generates an update interrupt or DMA request if
enabled.
Bit 1 UDIS: Update disable
This bit is set and cleared by software to enable/disable UEV event generation.
0: UEV enabled. The Update (UEV) event is generated by one of the following events:
–
Counter overflow/underflow
–
Setting the UG bit
–
Update generation through the slave mode controller
Buffered registers are then loaded with their preload values.
1: UEV disabled. The Update event is not generated, shadow registers keep their value
(ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is
set or if a hardware reset is received from the slave mode controller.
Bit 0 CEN: Counter enable
0: Counter disabled
1: Counter enabled

17.6.2

TIM16 and TIM17 control register 2 (TIM16_CR2 and TIM17_CR2)
Address offset: 0x04
Reset value: 0x0000

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Res.

Res.

Res.

Res.

Res.

Res.

OIS1N

OIS1

Res.

Res.

Res.

Res.

CCDS

CCUS

Res.

CCPC

rw

rw

rw

rw

rw

Bits 15:10 Reserved, always read as 0.
Bit 9 OIS1N: Output Idle state 1 (OC1N output)
0: OC1N=0 after a dead-time when MOE=0
1: OC1N=1 after a dead-time when MOE=0
Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed
(LOCK bits in TIMx_BKR register).
Bit 8 OIS1: Output Idle state 1 (OC1 output)
0: OC1=0 (after a dead-time if OC1N is implemented) when MOE=0
1: OC1=1 (after a dead-time if OC1N is implemented) when MOE=0
Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed
(LOCK bits in TIMx_BKR register).
Bits 7:4 Reserved, always read as 0.
Bit 3 CCDS: Capture/compare DMA selection
0: CCx DMA request sent when CCx event occurs
1: CCx DMA requests sent when update event occurs

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RM0360

General-purpose timers (TIM15/16/17)

Bit 2 CCUS: Capture/compare control update selection
0: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting
the COMG bit only.
1: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting
the COMG bit or when an rising edge occurs on TRGI.
Note: This bit acts only on channels that have a complementary output.
Bit 1 Reserved, always read as 0.
Bit 0 CCPC: Capture/compare preloaded control
0: CCxE, CCxNE and OCxM bits are not preloaded
1: CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are updated
only when COM bit is set.
Note: This bit acts only on channels that have a complementary output.

17.6.3

TIM16 and TIM17 DMA/interrupt enable register (TIM16_DIER and
TIM17_DIER)
Address offset: 0x0C
Reset value: 0x0000

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Res.

Res.

Res.

Res.

Res.

Res.

CC1DE

UDE

BIE

Res.

COMIE

Res.

Res.

Res.

CC1IE

UIE

rw

rw

rw

rw

rw

rw

Bit 15 Reserved, always read as 0.
Bit 14 Reserved, always read as 0.
Bits 13:10 Reserved, always read as 0.
Bit 9 CC1DE: Capture/Compare 1 DMA request enable
0: CC1 DMA request disabled
1: CC1 DMA request enabled
Bit 8 UDE: Update DMA request enable
0: Update DMA request disabled
1: Update DMA request enabled
Bit 7 BIE: Break interrupt enable
0: Break interrupt disabled
1: Break interrupt enabled
Bit 6 Reserved, always read as 0.
Bit 5 COMIE: COM interrupt enable
0: COM interrupt disabled
1: COM interrupt enabled
Bits 4:2 Reserved, always read as 0.
Bit 1 CC1IE: Capture/Compare 1 interrupt enable
0: CC1 interrupt disabled
1: CC1 interrupt enabled
Bit 0 UIE: Update interrupt enable
0: Update interrupt disabled
1: Update interrupt enabled

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General-purpose timers (TIM15/16/17)

17.6.4

RM0360

TIM16 and TIM17 status register (TIM16_SR and TIM17_SR)
Address offset: 0x10
Reset value: 0x0000

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Res.

Res.

Res.

Res.

Res.

Res.

CC1OF

Res.

BIF

Res.

COMIF

Res.

Res.

Res.

CC1IF

UIF

rc_w0

rc_w0

rc_w0

rc_w0

rc_w0

Bits 15:10 Reserved, always read as 0.
Bit 9 CC1OF: Capture/Compare 1 overcapture flag
This flag is set by hardware only when the corresponding channel is configured in input
capture mode. It is cleared by software by writing it to ‘0’.
0: No overcapture has been detected
1: The counter value has been captured in TIMx_CCR1 register while CC1IF flag was
already set
Bit 8 Reserved, always read as 0.
Bit 7 BIF: Break interrupt flag
This flag is set by hardware as soon as the break input goes active. It can be cleared by
software if the break input is not active.
0: No break event occurred
1: An active level has been detected on the break input
Bit 6 Reserved, always read as 0.
Bit 5 COMIF: COM interrupt flag
This flag is set by hardware on a COM event (once the capture/compare control bits –CCxE,
CCxNE, OCxM– have been updated). It is cleared by software by writing it to ‘0’.
0: No COM event occurred
1: COM interrupt pending

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General-purpose timers (TIM15/16/17)

Bits 4:2 Reserved, always read as 0.
Bit 1 CC1IF: Capture/Compare 1 interrupt flag
If channel CC1 is configured as output:
This flag is set by hardware when the counter matches the compare value, with some
exception in center-aligned mode (refer to the CMS bits in the TIMx_CR1 register description).
It is cleared by software.
0: No match.
1: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register.
When the contents of TIMx_CCR1 are greater than the contents of TIMx_ARR, the CC1IF
bit goes high on the counter overflow (in upcounting and up/down-counting modes) or
underflow (in downcounting mode)
If channel CC1 is configured as input:
This bit is set by hardware on a capture. It is cleared by software or by reading the
TIMx_CCR1 register.
0: No input capture occurred
1: The counter value has been captured in TIMx_CCR1 register (An edge has been
detected on IC1 which matches the selected polarity)
Bit 0 UIF: Update interrupt flag
This bit is set by hardware on an update event. It is cleared by software.
0: No update occurred.
1: Update interrupt pending. This bit is set by hardware when the registers are updated:
–
At overflow regarding the repetition counter value (update if repetition counter = 0)
and if the UDIS=0 in the TIMx_CR1 register.
–
When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if
URS=0 and UDIS=0 in the TIMx_CR1 register.

17.6.5

TIM16 and TIM17 event generation register (TIM16_EGR and
TIM17_EGR)
Address offset: 0x14
Reset value: 0x0000

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

BG

Res.

COMG

Res.

Res.

Res.

CC1G

UG

w

w

w

w

Bits 15:8 Reserved, always read as 0.
Bit 7 BG: Break generation
This bit is set by software in order to generate an event, it is automatically cleared by
hardware.
0: No action.
1: A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or
DMA transfer can occur if enabled.
Bit 6 Reserved, always read as 0.
Bit 5 COMG: Capture/Compare control update generation
This bit can be set by software, it is automatically cleared by hardware.
0: No action
1: When the CCPC bit is set, it is possible to update the CCxE, CCxNE and OCxM bits
Note: This bit acts only on channels that have a complementary output.

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General-purpose timers (TIM15/16/17)

RM0360

Bits 4:2 Reserved, always read as 0.
Bit 1 CC1G: Capture/Compare 1 generation
This bit is set by software in order to generate an event, it is automatically cleared by
hardware.
0: No action.
1: A capture/compare event is generated on channel 1:
If channel CC1 is configured as output:
CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled.
If channel CC1 is configured as input:
The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set, the
corresponding interrupt or DMA request is sent if enabled. The CC1OF flag is set if the CC1IF
flag was already high.
Bit 0 UG: Update generation
This bit can be set by software, it is automatically cleared by hardware.
0: No action.
1: Reinitialize the counter and generates an update of the registers. Note that the prescaler
counter is cleared too (anyway the prescaler ratio is not affected). The counter is cleared if
the center-aligned mode is selected or if DIR=0 (upcounting), else it takes the auto-reload
value (TIMx_ARR) if DIR=1 (downcounting).

17.6.6

TIM16 and TIM17 capture/compare mode register 1 (TIM16_CCMR1
and TIM17_CCMR1)
Address offset: 0x18
Reset value: 0x0000
The channels can be used in input (capture mode) or in output (compare mode). The
direction of a channel is defined by configuring the corresponding CCxS bits. All the other
bits of this register have a different function in input and in output mode. For a given bit,
OCxx describes its function when the channel is configured in output, ICxx describes its
function when the channel is configured in input. So you must take care that the same bit
can have a different meaning for the input stage and for the output stage.

15

14

13

12

11

10

9

8

7

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

5

4

OC1M[2:0]

rw

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3

2

OC1PE OC1FE

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IC1PSC[1:0]
rw

rw

rw

1

0

CC1S[1:0]
rw

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RM0360

General-purpose timers (TIM15/16/17)

Output compare mode:
Bits 15:7 Reserved, always read as 0.
Bits 6:4 OC1M: Output Compare 1 mode
These bits define the behavior of the output reference signal OC1REF from which OC1 and
OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on
CC1P and CC1NP bits.
000: Frozen - The comparison between the output compare register TIMx_CCR1 and the
counter TIMx_CNT has no effect on the outputs.
001: Set channel 1 to active level on match. OC1REF signal is forced high when the
counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).
010: Set channel 1 to inactive level on match. OC1REF signal is forced low when the
counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).
011: Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1.
100: Force inactive level - OC1REF is forced low.
101: Force active level - OC1REF is forced high.
110: PWM mode 1 - In upcounting, channel 1 is active as long as TIMx_CNTTIMx_CCR1 else active (OC1REF=’1’).
111: PWM mode 2 - In upcounting, channel 1 is inactive as long as
TIMx_CNTTIMx_CCR1 else inactive.
Note: 1: These bits can not be modified as long as LOCK level 3 has been programmed
(LOCK bits in TIMx_BDTR register) and CC1S=’00’ (the channel is configured in
output).
2: In PWM mode 1 or 2, the OCREF level changes only when the result of the
comparison changes or when the output compare mode switches from “frozen” mode
to “PWM” mode.

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RM0360

Bit 3 OC1PE: Output Compare 1 preload enable
0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the
new value is taken in account immediately.
1: Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload
register. TIMx_CCR1 preload value is loaded in the active register at each update event.
Note: 1: These bits can not be modified as long as LOCK level 3 has been programmed
(LOCK bits in TIMx_BDTR register) and CC1S=’00’ (the channel is configured in
output).
2: The PWM mode can be used without validating the preload register only in one
pulse mode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed.
Bit 2 OC1FE: Output Compare 1 fast enable
This bit is used to accelerate the effect of an event on the trigger in input on the CC output.
0: CC1 behaves normally depending on counter and CCR1 values even when the trigger is
ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is
5 clock cycles.
1: An active edge on the trigger input acts like a compare match on CC1 output. Then, OC
is set to the compare level independently of the result of the comparison. Delay to sample
the trigger input and to activate CC1 output is reduced to 3 clock cycles. OC1FE acts only if
the channel is configured in PWM1 or PWM2 mode.
Bits 1:0 CC1S: Capture/Compare 1 selection
This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC1 channel is configured as output
01: CC1 channel is configured as input, IC1 is mapped on TI1
10: CC1 channel is configured as input, IC1 is mapped on TI2
11: CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only
if an internal trigger input is selected through TS bit (TIMx_SMCR register)
Note: CC1S bits are writable only when the channel is OFF (CC1E = ‘0’ in TIMx_CCER).

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General-purpose timers (TIM15/16/17)

Input capture mode
Bits 15:8 Reserved, always read as 0.
Bits 7:4 IC1F[3:0]: Input capture 1 filter
This bit-field defines the frequency used to sample TI1 input and the length of the digital filter applied to
TI1. The digital filter is made of an event counter in which N events are needed to validate a transition
on the output:
0000: No filter, sampling is done at fDTS
0001: fSAMPLING = fCK_INT, N = 2
0010: fSAMPLING = fCK_INT, N = 4
0011: fSAMPLING = fCK_INT, N = 8
0100: fSAMPLING = fDTS / 2, N = 6
0101: fSAMPLING = fDTS / 2, N = 8
0110: fSAMPLING = fDTS / 4, N = 6
0111: fSAMPLING = fDTS / 4, N = 8
1000: fSAMPLING = fDTS / 8, N = 6
1001: fSAMPLING = fDTS / 8, N = 8
1010: fSAMPLING = fDTS / 16, N = 5
1011: fSAMPLING = fDTS / 16, N = 6
1100: fSAMPLING = fDTS / 16, N = 8
1101: fSAMPLING = fDTS / 32, N = 5
1110: fSAMPLING = fDTS / 32, N = 6
1111: fSAMPLING = fDTS / 32, N = 8
Note: Care must be taken that fDTS is replaced in the formula by CK_INT when ICxF[3:0] = 1, 2 or 3.
Bits 3:2 IC1PSC: Input capture 1 prescaler
This bit-field defines the ratio of the prescaler acting on CC1 input (IC1).
The prescaler is reset as soon as CC1E=’0’ (TIMx_CCER register).
00: no prescaler, capture is done each time an edge is detected on the capture input.
01: capture is done once every 2 events
10: capture is done once every 4 events
11: capture is done once every 8 events
Bits 1:0 CC1S: Capture/Compare 1 Selection
This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC1 channel is configured as output
01: CC1 channel is configured as input, IC1 is mapped on TI1
10: CC1 channel is configured as input, IC1 is mapped on TI2
11: CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if an
internal trigger input is selected through TS bit (TIMx_SMCR register)
Note: CC1S bits are writable only when the channel is OFF (CC1E = ‘0’ in TIMx_CCER).

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17.6.7

RM0360

TIM16 and TIM17 capture/compare enable register (TIM16_CCER
and TIM17_CCER)
Address offset: 0x20
Reset value: 0x0000

15

14

13

12

11

10

9

8

7

6

5

4

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

3

2

CC1NP CC1NE
rw

rw

1

0

CC1P

CC1E

rw

rw

Bits 15:4 Reserved, always read as 0.
Bit 3 CC1NP: Capture/Compare 1 complementary output polarity
0: OC1N active high
1: OC1N active low
Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits
in TIMx_BDTR register) and CC1S=”00” (the channel is configured in output).
Bit 2 CC1NE: Capture/Compare 1 complementary output enable
0: Off - OC1N is not active. OC1N level is then function of MOE, OSSI, OSSR, OIS1, OIS1N
and CC1E bits.
1: On - OC1N signal is output on the corresponding output pin depending on MOE, OSSI,
OSSR, OIS1, OIS1N and CC1E bits.
Bit 1 CC1P: Capture/Compare 1 output polarity
CC1 channel configured as output:
0: OC1 active high
1: OC1 active low
CC1 channel configured as input:
The CC1NP/CC1P bits select the polarity of TI1FP1 and TI2FP1 for capture operation.
00: Non-inverted/rising edge: circuit is sensitive to TIxFP1's rising edge TIxFP1 is not
inverted.
01: Inverted/falling edge: circuit is sensitive to TIxFP1's falling edge, TIxFP1 is inverted.
10: Reserved, do not use this configuration.
11: Non-inverted/both edges: circuit is sensitive to both the rising and falling edges of
TIxFP1, TIxFP1 is not inverted.
Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits
in TIMx_BDTR register)
Bit 0 CC1E: Capture/Compare 1 output enable
CC1 channel configured as output:
0: Off - OC1 is not active. OC1 level is then function of MOE, OSSI, OSSR, OIS1, OIS1N
and CC1NE bits.
1: On - OC1 signal is output on the corresponding output pin depending on MOE, OSSI,
OSSR, OIS1, OIS1N and CC1NE bits.
CC1 channel configured as input:
This bit determines if a capture of the counter value can actually be done into the input
capture/compare register 1 (TIMx_CCR1) or not.
0: Capture disabled
1: Capture enabled

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General-purpose timers (TIM15/16/17)
Table 58. Output control bits for complementary OCx and OCxN channels with break
feature
Output states(1)

Control bits
MOE OSSI OSSR CCxE CCxNE
OCx output state
bit
bit
bit
bit
bit

1

0

0

0

0

Output Disabled (not
driven by the timer)
OCx=0, OCx_EN=0

Output Disabled (not driven by
the timer)
OCxN=0, OCxN_EN=0

0

0

1

Output Disabled (not
driven by the timer)
OCx=0, OCx_EN=0

OCxREF + Polarity
OCxN=OCxREF xor CCxNP,
OCxN_EN=1

0

1

0

OCxREF + Polarity
OCx=OCxREF xor CCxP,
OCx_EN=1

Output Disabled (not driven by
the timer)
OCxN=0, OCxN_EN=0

0

1

1

OCREF + Polarity + deadtime
OCx_EN=1

Complementary to OCREF (not
OCREF) + Polarity + dead-time
OCxN_EN=1

1

0

0

Output Disabled (not
driven by the timer)
OCx=CCxP, OCx_EN=0

Output Disabled (not driven by
the timer)
OCxN=CCxNP, OCxN_EN=0

1

0

1

Off-State (output enabled
with inactive state)
OCx=CCxP, OCx_EN=1

OCxREF + Polarity
OCxN=OCxREF xor CCxNP,
OCxN_EN=1
Off-State (output enabled with
inactive state)
OCxN=CCxNP, OCxN_EN=1
Complementary to OCREF (not
OCREF) + Polarity + dead-time
OCxN_EN=1

X

1

1

0

OCxREF + Polarity
OCx=OCxREF xor CCxP,
OCx_EN=1

1

1

1

OCREF + Polarity + deadtime
OCx_EN=1

0

0

0

0

0

1

0

1

0

0

1

1

0

0

1

0

1

1

1

0

1

1

1

1

OCxN output state

X

Output Disabled (not driven by the timer)
Asynchronously: OCx=CCxP, OCx_EN=0, OCxN=CCxNP,
OCxN_EN=0
Then if the clock is present: OCx=OISx and OCxN=OISxN
after a dead-time, assuming that OISx and OISxN do not
correspond to OCX and OCxN both in active state.
Off-State (output enabled with inactive state)
Asynchronously: OCx=CCxP, OCx_EN=1, OCxN=CCxNP,
OCxN_EN=1
Then if the clock is present: OCx=OISx and OCxN=OISxN
after a dead-time, assuming that OISx and OISxN do not
correspond to OCX and OCxN both in active state

1. When both outputs of a channel are not used (CCxE = CCxNE = 0), the OISx, OISxN, CCxP and CCxNP
bits must be kept cleared.

Note:

The state of the external I/O pins connected to the complementary OCx and OCxN channels
depends on the OCx and OCxN channel state and the GPIO and AFIO registers.
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17.6.8

RM0360

TIM16 and TIM17 counter (TIM16_CNT and TIM17_CNT)
Address offset: 0x24
Reset value: 0x0000

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

rw

rw

rw

rw

rw

rw

rw

CNT[15:0]
rw

rw

rw

Bits 15:0

17.6.9

rw

rw

rw

rw

rw

rw

CNT[15:0]: Counter value

TIM16 and TIM17 prescaler (TIM16_PSC and TIM17_PSC)
Address offset: 0x28
Reset value: 0x0000

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

rw

rw

rw

rw

rw

rw

rw

PSC[15:0]
rw

rw

rw

rw

rw

rw

rw

rw

rw

Bits 15:0 PSC[15:0]: Prescaler value
The counter clock frequency (CK_CNT) is equal to fCK_PSC / (PSC[15:0] + 1).
PSC contains the value to be loaded in the active prescaler register at each update event
(including when the counter is cleared through UG bit of TIMx_EGR register or through trigger
controller when configured in “reset mode”).

TIM16 and TIM17 auto-reload register (TIM16_ARR and 
TIM17_ARR)

17.6.10

Address offset: 0x2C
Reset value: 0xFFFF
15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

rw

rw

rw

rw

rw

rw

rw

ARR[15:0]
rw

rw

rw

rw

rw

rw

rw

rw

rw

Bits 15:0 ARR[15:0]: Auto-reload value
ARR is the value to be loaded in the actual auto-reload register.
Refer to the Section 16.3.1: Time-base unit on page 375 for more details about ARR update
and behavior.
The counter is blocked while the auto-reload value is null.

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General-purpose timers (TIM15/16/17)

17.6.11

TIM16 and TIM17 repetition counter register (TIM16_RCR and
TIM17_RCR)
Address offset: 0x30
Reset value: 0x0000

15

14

13

12

11

10

9

8

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

7

6

5

4

3

2

1

0

rw

rw

rw

REP[7:0]
rw

rw

rw

rw

rw

Bits 15:8 Reserved, always read as 0.
Bits 7:0 REP[7:0]: Repetition counter value
These bits allow the user to set-up the update rate of the compare registers (i.e. periodic
transfers from preload to active registers) when preload registers are enable, as well as the
update interrupt generation rate, if this interrupt is enable.
Each time the REP_CNT related downcounter reaches zero, an update event is generated
and it restarts counting from REP value. As REP_CNT is reloaded with REP value only at the
repetition update event U_RC, any write to the TIMx_RCR register is not taken in account until
the next repetition update event.
It means in PWM mode (REP+1) corresponds to the number of PWM periods in edge-aligned
mode.

17.6.12

TIM16 and TIM17 capture/compare register 1 (TIM16_CCR1 and
TIM17_CCR1)
Address offset: 0x34
Reset value: 0x0000

15

14

13

12

11

10

9

8

rw

rw

rw

rw

rw

rw

rw

7

6

5

4

3

2

1

0

rw

rw

rw

rw

rw

rw

rw

CCR1[15:0]
rw

rw

Bits 15:0 CCR1[15:0]: Capture/Compare 1 value
If channel CC1 is configured as output:
CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value).
It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (bit
OC1PE). Else the preload value is copied in the active capture/compare 1 register when an
update event occurs.
The active capture/compare register contains the value to be compared to the counter
TIMx_CNT and signaled on OC1 output.

If channel CC1 is configured as input:
CCR1 is the counter value transferred by the last input capture 1 event (IC1).

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17.6.13

RM0360

TIM16 and TIM17 break and dead-time register (TIM16_BDTR and
TIM17_BDTR)
Address offset: 0x44
Reset value: 0x0000

15

14

13

12

11

10

MOE

AOE

BKP

BKE

OSSR

OSSI

rw

rw

rw

rw

rw

rw

Note:

9

8

7

6

5

LOCK[1:0]
rw

rw

4

3

2

1

0

rw

rw

rw

DTG[7:0]
rw

rw

rw

rw

rw

As the bits AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] can be write-locked depending on
the LOCK configuration, it can be necessary to configure all of them during the first write
access to the TIMx_BDTR register.
Bit 15 MOE: Main output enable
This bit is cleared asynchronously by hardware as soon as the break input is active. It is set by
software or automatically depending on the AOE bit. It is acting only on the channels which are
configured in output.
0: OC and OCN outputs are disabled or forced to idle state
1: OC and OCN outputs are enabled if their respective enable bits are set (CCxE, CCxNE in
TIMx_CCER register)
See OC/OCN enable description for more details (Section 17.5.8: TIM15 capture/compare
enable register (TIM15_CCER) on page 440).
Bit 14 AOE: Automatic output enable
0: MOE can be set only by software
1: MOE can be set by software or automatically at the next update event (if the break input is
not be active)
Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits
in TIMx_BDTR register).
Bit 13 BKP: Break polarity
0: Break input BRK is active low
1: Break input BRK is active high
Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits
in TIMx_BDTR register).
Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
Bit 12 BKE: Break enable
0: Break inputs (BRK and CCS clock failure event) disabled
1; Break inputs (BRK and CCS clock failure event) enabled
Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in
TIMx_BDTR register).
Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.

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General-purpose timers (TIM15/16/17)

Bit 11 OSSR: Off-state selection for Run mode
This bit is used when MOE=1 on channels having a complementary output which are
configured as outputs. OSSR is not implemented if no complementary output is implemented in
the timer.
See OC/OCN enable description for more details (Section 17.5.8: TIM15 capture/compare
enable register (TIM15_CCER) on page 440).
0: When inactive, OC/OCN outputs are disabled (OC/OCN enable output signal=0)
1: When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1
or CCxNE=1. Then, OC/OCN enable output signal=1
Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK
bits in TIMx_BDTR register).
Bit 10 OSSI: Off-state selection for Idle mode
This bit is used when MOE=0 on channels configured as outputs.
See OC/OCN enable description for more details (Section 17.5.8: TIM15 capture/compare
enable register (TIM15_CCER) on page 440).
0: When inactive, OC/OCN outputs are disabled (OC/OCN enable output signal=0)
1: When inactive, OC/OCN outputs are forced first with their idle level as soon as CCxE=1 or
CCxNE=1. OC/OCN enable output signal=1)
Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK
bits in TIMx_BDTR register).
Bits 9:8 LOCK[1:0]: Lock configuration
These bits offer a write protection against software errors.
00: LOCK OFF - No bit is write protected
01: LOCK Level 1 = DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2
register and BKE/BKP/AOE bits in TIMx_BDTR register can no longer be written.
10: LOCK Level 2 = LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER
register, as long as the related channel is configured in output through the CCxS bits) as well
as OSSR and OSSI bits can no longer be written.
11: LOCK Level 3 = LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in
TIMx_CCMRx registers, as long as the related channel is configured in output through the
CCxS bits) can no longer be written.
Note: The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register
has been written, their content is frozen until the next reset.
Bits 7:0 DTG[7:0]: Dead-time generator setup
This bit-field defines the duration of the dead-time inserted between the complementary
outputs. DT correspond to this duration.
DTG[7:5]=0xx => DT=DTG[7:0]x tdtg with tdtg=tDTS
DTG[7:5]=10x => DT=(64+DTG[5:0])xtdtg with Tdtg=2xtDTS
DTG[7:5]=110 => DT=(32+DTG[4:0])xtdtg with Tdtg=8xtDTS
DTG[7:5]=111 => DT=(32+DTG[4:0])xtdtg with Tdtg=16xtDTS
Example if TDTS=125ns (8MHz), dead-time possible values are:
0 to 15875 ns by 125 ns steps,
16 µs to 31750 ns by 250 ns steps,
32 µs to 63 µs by 1 µs steps,
64 µs to 126 µs by 2 µs steps
Note: This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed
(LOCK bits in TIMx_BDTR register).

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RM0360

TIM16 and TIM17 DMA control register (TIM16_DCR and 
TIM17_DCR)

17.6.14

Address offset: 0x48
Reset value: 0x0000
15

14

13

Res.

Res.

Res.

12

11

10

9

8

DBL[4:0]
rw

rw

rw

rw

7

6

5

Res.

Res.

Res.

rw

4

3

2

1

0

rw

rw

DBA[4:0]
rw

rw

rw

Bits 15:13 Reserved, always read as 0.
Bits 12:8 DBL[4:0]: DMA burst length
This 5-bit vector defines the length of DMA transfers (the timer recognizes a burst transfer
when a read or a write access is done to the TIMx_DMAR address), i.e. the number of
transfers. Transfers can be in half-words or in bytes (see example below).
00000: 1 transfer,
00001: 2 transfers,
00010: 3 transfers,
...
10001: 18 transfers.
Bits 7:5 Reserved, always read as 0.
Bits 4:0 DBA[4:0]: DMA base address
This 5-bits vector defines the base-address for DMA transfers (when read/write access are
done through the TIMx_DMAR address). DBA is defined as an offset starting from the address
of the TIMx_CR1 register.
Example:
00000: TIMx_CR1,
00001: TIMx_CR2,
00010: TIMx_SMCR,
...
Example: Let us consider the following transfer: DBL = 7 transfers and DBA = TIMx_CR1. In
this case the transfer is done to/from 7 registers starting from the TIMx_CR1 address.

17.6.15

TIM16 and TIM17 DMA address for full transfer (TIM16_DMAR and
TIM17_DMAR)
Address offset: 0x4C
Reset value: 0x0000

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

rw

rw

rw

rw

rw

rw

rw

DMAB[15:0]
rw

rw

rw

rw

rw

rw

rw

rw

rw

Bits 15:0 DMAB[15:0]: DMA register for burst accesses
A read or write access to the DMAR register accesses the register located at the address:
“(TIMx_CR1 address) + DBA + (DMA index)” in which:
TIMx_CR1 address is the address of the control register 1, DBA is the DMA base address
configured in TIMx_DCR register, DMA index is the offset automatically controlled by the
DMA transfer, depending on the length of the transfer DBL in the TIMx_DCR register.

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General-purpose timers (TIM15/16/17)

Example of how to use the DMA burst feature
In this example the timer DMA burst feature is used to update the contents of the CCRx
registers (x = 2, 3, 4) with the DMA transferring half words into the CCRx registers.
This is done in the following steps:
1.

Note:

Configure the corresponding DMA channel as follows:
–

DMA channel peripheral address is the DMAR register address

–

DMA channel memory address is the address of the buffer in the RAM containing
the data to be transferred by DMA into CCRx registers.

–

Number of data to transfer = 3 (See note below).

–

Circular mode disabled.

2.

Configure the DCR register by configuring the DBA and DBL bit fields as follows: 
DBL = 3 transfers, DBA = 0xE.

3.

Enable the TIMx update DMA request (set the UDE bit in the DIER register).

4.

Enable TIMx

5.

Enable the DMA channel

This example is for the case where every CCRx register to be updated once. If every CCRx
register is to be updated twice for example, the number of data to transfer should be 6. Let
us take the example of a buffer in the RAM containing data1, data2, data3, data4, data5 and
data6. The data is transferred to the CCRx registers as follows: on the first update DMA
request, data1 is transferred to CCR2, data2 is transferred to CCR3, data3 is transferred to
CCR4 and on the second update DMA request, data4 is transferred to CCR2, data5 is
transferred to CCR3 and data6 is transferred to CCR4.

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0x34

0x44

468/779

Reset value
TIM16_CCR1
and
TIM17_CCR1
Reset value
TIM16_BDTR
and
TIM17_BDTR
Reset value

DocID025023 Rev 4

MOE

AOE

BKP

BKE

OSSR

OSSI

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

1

1

1

1

1

1

1

1

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

0

0

0
0

0

0
0

0

0
0

0
0

0

0

0
0

0

0

0

0

0

0

0

0
0

0

0

0
0

0

0

0
0

0

1

0

0

0

OC1M
[2:0]

0

0

1

0

0

0

0

LOCK
[1:0]

0

0

IC1F[3:0]

0
0
0
0
0
0
0

CCR1[15:0]

DT[7:0]

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0
CC1E

0
OC1FE

0

CC1P

0
OC1PE

0

0

0
0

CC1IF
UIF
0

UG

Res.

Res.

0

CC1G

Res.

Res.

Res.

0

CC1NE

0

CC1IE
UIE

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

OPM
URS
UDIS
CEN

0
0
0

CCUS
Res.
CCPC

Res.

Res.

Res.

ARPE

0

CCDS

Res.

Res.

Res.

0

Res.

OIS1

0
Res.

OIS1N

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

0

CC1NP

0

Res.

COMIE

COMIF

Res.
0
COMG

0

Res.

Res.
0

Res.

BIE
0

Res.

UDE
0

BIF

0

BG

Res.

CC1DE

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

0

CC1OF

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

0

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

0

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

CKD
[1:0]

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

0

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

0x30

TIM16_RCR and
TIM17_RCR

Res.

Reset value

0x2C

TIM16_ARR and
TIM17_ARR

Res.

Reset value

0x28
TIM16_PSC and
TIM17_PSC

Res.

Reset value

0x24
TIM16_CNT and
TIM17_CNT

Res.

Reset value

0x20

Res.

0x18

Reset value
TIM16_CCMR1
and
TIM17_CCMR1
Output compare
mode
Reset value
TIM16_CCMR1
and
TIM17_CCMR1
Input capture
mode
Reset value
TIM16_CCER
and
TIM17_CCER

Res.

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0

0x14
TIM16_EGR and
TIM17_EGR

Res.

0x10
TIM16_SR and
TIM17_SR

Res.

0x0C
Reset value
TIM16_DIER
and
TIM17_DIER

Res.

0x04
TIM16_CR2 and
TIM17_CR2

Res.

TIM16_CR1 and
TIM17_CR1

Res.

Reset value

0x00

Res.

Reset value

Register

Res.

Reset value

Offset

Res.

17.6.16

Res.

General-purpose timers (TIM15/16/17)
RM0360

TIM16 and TIM17 register map
TIM16 and TIM17 registers are mapped as 16-bit addressable registers as described in the
table below:
Table 59. TIM16 and TIM17 register map and reset values

0
0
0

0
0

0
0

CC1S
[1:0]
0
0

IC1
CC1S
PSC
[1:0]
[1:0]

0
0
0
0

CNT[15:0]

PSC[15:0]

ARR[15:0]
0
0
0
0
0
0

0
0
0
0
0
0

1

1

1

1

1

1

REP[7:0]

RM0360

General-purpose timers (TIM15/16/17)

0

0

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

0

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

DBL[4:0]
0

Res.

0x4C

Reset value
TIM16_DMAR
and
TIM17_DMAR
Reset value

Res.

TIM16_DCR and
TIM17_DCR

Res.

0x48

Res.

Register

Res.

Offset

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0

Table 59. TIM16 and TIM17 register map and reset values (continued)

0

DBA[4:0]
0

0

0

0

0

0

0

0

0

0

DMAB[15:0]
0

0

0

0

0

0

0

0

0

0

0

Refer to Section 2.2.2 on page 37 for the register boundary addresses.

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Infrared interface (IRTIM)

18

RM0360

Infrared interface (IRTIM)
An infrared interface (IRTIM) for remote control is available on the device. It can be used
with an infrared LED to perform remote control functions.
It uses internal connections with TIM16 as shown in Figure 188.
To generate the infrared remote control signals, the IR interface must be enabled and TIM16
channel 1 (TIM16_OC1) must be properly configured to generate correct waveforms.
The infrared receiver can be implemented easily through a basic input capture mode.
Figure 188. IR internal hardware connections with TIM16
7,0B&+

,57,0

,5B287

7,0B&+

069

All standard IR pulse modulation modes can be obtained by programming the two timer
output compare channels.
is used to generate the high frequency carrier signal, while TIM16 generates the modulation
envelope.
The infrared function is output on the IR_OUT pin. The activation of this function is done
through the GPIOx_AFRx register by enabling the related alternate function bit.
The high sink LED driver capability (only available on the PB9 pin) can be activated through
the I2C_PB9_FMP bit in the SYSCFG_CFGR1 register and used to sink the high current
needed to directly control an infrared LED.
For code example refer to the Appendix section A.9.1: TIM16 and TIM17 configuration code
example.

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RM0360

Independent watchdog (IWDG)

19

Independent watchdog (IWDG)

19.1

Introduction
The devices feature an embedded watchdog peripheral that offers a combination of high
safety level, timing accuracy and flexibility of use. The Independent watchdog peripheral
detects and solves malfunctions due to software failure, and triggers system reset when the
counter reaches a given timeout value.
The independent watchdog (IWDG) is clocked by its own dedicated low-speed clock (LSI)
and thus stays active even if the main clock fails.
The IWDG is best suited for applications that require the watchdog to run as a totally
independent process outside the main application, but have lower timing accuracy
constraints. For further information on the window watchdog, refer to Section 20 on page
480.

19.2

IWDG main features


Free-running downcounter



Clocked from an independent RC oscillator (can operate in Standby and Stop modes)



Conditional Reset
–

Reset (if watchdog activated) when the downcounter value becomes lower than
0x000

–

Reset (if watchdog activated) if the downcounter is reloaded outside the window

19.3

IWDG functional description

19.3.1

IWDG block diagram
Figure 189 shows the functional blocks of the independent watchdog module.
Figure 189. Independent watchdog block diagram
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3UHVFDOHUUHJLVWHU
,:'*B35

ELW
/6,
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N+] 

6WDWXVUHJLVWHU
,:'*B65

5HORDGUHJLVWHU
,:'*B5/5

.H\UHJLVWHU

,:'*B.5


ELWUHORDGYDOXH

ELWGRZQFRXQWHU


,:'*UHVHW

9''YROWDJHGRPDLQ
069

1. The watchdog function is implemented in the CORE voltage domain that is still functional in Stop and
Standby modes.

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Independent watchdog (IWDG)

RM0360

When the independent watchdog is started by writing the value 0x0000 CCCC in the Key
register (IWDG_KR), the counter starts counting down from the reset value of 0xFFF. When
it reaches the end of count value (0x000) a reset signal is generated (IWDG reset).
Whenever the key value 0x0000 AAAA is written in the IWDG_KR register, the IWDG_RLR
value is reloaded in the counter and the watchdog reset is prevented.

19.3.2

Window option
The IWDG can also work as a window watchdog by setting the appropriate window in the
IWDG_WINR register.
If the reload operation is performed while the counter is greater than the value stored in the
window register (IWDG_WINR), then a reset is provided.
The default value of the IWDG_WINR is 0x0000 0FFF, so if it is not updated, the window
option is disabled.
As soon as the window value is changed, a reload operation is performed in order to reset
the downcounter to the IWDG_RLR value and ease the cycle number calculation to
generate the next reload.

Configuring the IWDG when the window option is enabled

Note:

1.

Enable the IWDG by writing 0x0000 CCCC in the IWDG_KR register.

2.

Enable register access by writing 0x0000 5555 in the IWDG_KR register.

3.

Write the IWDG prescaler by programming IWDG_PR from 0 to 7.

4.

Write the reload register (IWDG_RLR).

5.

Wait for the registers to be updated (IWDG_SR = 0x0000 0000).

6.

Write to the window register IWDG_WINR. This automatically refreshes the counter
value IWDG_RLR.

Writing the window value allows to refresh the Counter value by the RLR when IWDG_SR is
set to 0x0000 0000.
For code example refer to the Appendix section A.12.2: IWDG configuration with window
code example.

Configuring the IWDG when the window option is disabled
When the window option it is not used, the IWDG can be configured as follows:
1.

Enable the IWDG by writing 0x0000 CCCC in the IWDG_KR register.

2.

Enable register access by writing 0x0000 5555 in the IWDG_KR register.

3.

Write the IWDG prescaler by programming IWDG_PR from 0 to 7.

4.

Write the reload register (IWDG_RLR).

5.

Wait for the registers to be updated (IWDG_SR = 0x0000 0000).

6.

Refresh the counter value with IWDG_RLR (IWDG_KR = 0x0000 AAAA)

For code example refer to the Appendix section A.12.1: IWDG configuration code example.

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RM0360

19.3.3

Independent watchdog (IWDG)

Hardware watchdog
If the “Hardware watchdog” feature is enabled through the device option bits, the watchdog
is automatically enabled at power-on, and generates a reset unless the Key register is
written by the software before the counter reaches end of count or if the downcounter is
reloaded inside the window.

19.3.4

Behavior in Stop and Standby modes
Once running, the IWDG cannot be stopped.

19.3.5

Register access protection
Write access to the IWDG_PR, IWDG_RLR and IWDG_WINR registers is protected. To
modify them, you must first write the code 0x0000 5555 in the IWDG_KR register. A write
access to this register with a different value will break the sequence and register access will
be protected again. This implies that it is the case of the reload operation
(writing 0x0000 AAAA).
A status register is available to indicate that an update of the prescaler or the down-counter
reload value or the window value is on going.
For code example refer to the Appendix section A.12.1: IWDG configuration code example.

19.3.6

Debug mode
When the microcontroller enters debug mode (core halted), the IWDG counter either
continues to work normally or stops, depending on DBG_IWDG_STOP configuration bit in
DBG module.

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Independent watchdog (IWDG)

19.4

RM0360

IWDG registers
Refer to Section 1.1 on page 33 for a list of abbreviations used in register descriptions.
The peripheral registers can be accessed by half-words (16-bit) or words (32-bit).

19.4.1

Key register (IWDG_KR)
Address offset: 0x00
Reset value: 0x0000 0000 (reset by Standby mode)

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

w

w

w

w

w

w

w

KEY[15:0]
w

w

w

w

w

w

w

w

w

Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 KEY[15:0]: Key value (write only, read 0x0000)
These bits must be written by software at regular intervals with the key value 0xAAAA,
otherwise the watchdog generates a reset when the counter reaches 0.
Writing the key value 0x5555 to enable access to the IWDG_PR, IWDG_RLR and
IWDG_WINR registers (see Section 19.3.5: Register access protection)
Writing the key value 0xCCCC starts the watchdog (except if the hardware watchdog option is
selected)

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Independent watchdog (IWDG)

19.4.2

Prescaler register (IWDG_PR)
Address offset: 0x04
Reset value: 0x0000 0000

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

2

1

0

15

14

13

12

11

10

9

8

7

6

5

4

3

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

PR[2:0]
rw

rw

rw

Bits 31:3 Reserved, must be kept at reset value.
Bits 2:0 PR[2:0]: Prescaler divider
These bits are write access protected see Section 19.3.5: Register access protection. They are
written by software to select the prescaler divider feeding the counter clock. PVU bit of
IWDG_SR must be reset in order to be able to change the prescaler divider.
000: divider /4
001: divider /8
010: divider /16
011: divider /32
100: divider /64
101: divider /128
110: divider /256
111: divider /256
Note: Reading this register returns the prescaler value from the VDD voltage domain. This
value may not be up to date/valid if a write operation to this register is ongoing. For this
reason the value read from this register is valid only when the PVU bit in the IWDG_SR
register is reset.

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Independent watchdog (IWDG)

19.4.3

RM0360

Reload register (IWDG_RLR)
Address offset: 0x08
Reset value: 0x0000 0FFF (reset by Standby mode)

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

11

10

9

8

7

6

5

4

3

2

1

0

rw

rw

rw

rw

rw

15

14

13

12

Res.

Res.

Res.

Res.

RL[11:0]
rw

rw

rw

rw

rw

rw

rw

Bits 31:12 Reserved, must be kept at reset value.
Bits11:0 RL[11:0]: Watchdog counter reload value
These bits are write access protected see Section 19.3.5. They are written by software to
define the value to be loaded in the watchdog counter each time the value 0xAAAA is written in
the IWDG_KR register. The watchdog counter counts down from this value. The timeout period
is a function of this value and the clock prescaler. Refer to the datasheet for the timeout
information.
The RVU bit in the IWDG_SR register must be reset in order to be able to change the reload
value.
Note: Reading this register returns the reload value from the VDD voltage domain. This value
may not be up to date/valid if a write operation to this register is ongoing on this
register. For this reason the value read from this register is valid only when the RVU bit
in the IWDG_SR register is reset.

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RM0360

Independent watchdog (IWDG)

19.4.4

Status register (IWDG_SR)
Address offset: 0x0C
Reset value: 0x0000 0000 (not reset by Standby mode)

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

WVU

RVU

PVU

r

r

r

Bits 31:3 Reserved, must be kept at reset value.
Bit 2 WVU: Watchdog counter window value update
This bit is set by hardware to indicate that an update of the window value is ongoing. It is reset
by hardware when the reload value update operation is completed in the VDD voltage domain
(takes up to 5 RC 40 kHz cycles).
Window value can be updated only when WVU bit is reset.
Bit 1 RVU: Watchdog counter reload value update
This bit is set by hardware to indicate that an update of the reload value is ongoing. It is reset
by hardware when the reload value update operation is completed in the VDD voltage domain
(takes up to 5 RC 40 kHz cycles).
Reload value can be updated only when RVU bit is reset.
Bit 0 PVU: Watchdog prescaler value update
This bit is set by hardware to indicate that an update of the prescaler value is ongoing. It is
reset by hardware when the prescaler update operation is completed in the VDD voltage
domain (takes up to 5 RC 40 kHz cycles).
Prescaler value can be updated only when PVU bit is reset.

Note:

If several reload, prescaler, or window values are used by the application, it is mandatory to
wait until RVU bit is reset before changing the reload value, to wait until PVU bit is reset
before changing the prescaler value, and to wait until WVU bit is reset before changing the
window value. However, after updating the prescaler and/or the reload/window value it is not
necessary to wait until RVU or PVU or WVU is reset before continuing code execution
except in case of low-power mode entry.

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Independent watchdog (IWDG)

19.4.5

RM0360

Window register (IWDG_WINR)
Address offset: 0x10
Reset value: 0x0000 0FFF (reset by Standby mode)

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

11

10

9

8

7

6

5

4

3

2

1

0

rw

rw

rw

rw

rw

15

14

13

12

Res.

Res.

Res.

Res.

WIN[11:0]
rw

rw

rw

rw

rw

rw

rw

Bits 31:12 Reserved, must be kept at reset value.
Bits11:0 WIN[11:0]: Watchdog counter window value
These bits are write access protected see Section 19.3.5. These bits contain the high limit of
the window value to be compared to the downcounter.
To prevent a reset, the downcounter must be reloaded when its value is lower than the
window register value and greater than 0x0
The WVU bit in the IWDG_SR register must be reset in order to be able to change the reload
value.
Note: Reading this register returns the reload value from the VDD voltage domain. This value
may not be valid if a write operation to this register is ongoing. For this reason the value
read from this register is valid only when the WVU bit in the IWDG_SR register is reset.

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0x0C

0x10
Reset value

DocID025023 Rev 4
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
1
1
1
1
1

Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

0
0

1
1
1
1
1

WIN[11:0]
1
1
1
1

PVU

Res.

Res.

0
Res.

Res.

Res.

0
Res.

Res.

Res.

0

RVU

1
Res.

Res.

Res.

0
Res.

Res.

Res.

0
Res.

Res.

Res.

0
Res.

Res.

Res.

0
Res.

Res.

Res.

0
Res.

Res.

Res.

0
Res.

Res.

Res.

0
Res.

Res.

0

WVU

1
Res.

1
Res.

1
Res.

1
Res.

Res.

Res.

1
Res.

Res.

Res.

1
Res.

Res.

Res.

Reset value

Res.

Res.

Res.

Res.

Res.

Reset value

Res.

Reset value

Res.

Res.

Res.

Reset value
Res.

IWDG_WINR
Res.

IWDG_SR

Res.

0x08
IWDG_RLR

Res.

0x04
IWDG_PR

Res.

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0

IWDG_KR
Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Register

Res.

0x00

Res.

Offset

Res.

19.4.6

Res.

RM0360
Independent watchdog (IWDG)

IWDG register map
The following table gives the IWDG register map and reset values.
Table 60. IWDG register map and reset values

KEY[15:0]
0
PR[2:0]

0
0

RL[11:0]
0
0
0

0
0
0

1
1
1

Refer to Section 2.2.2: Memory map and register boundary addresses for the register
boundary addresses.

479/779

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System window watchdog (WWDG)

RM0360

20

System window watchdog (WWDG)

20.1

Introduction
The system window watchdog (WWDG) is used to detect the occurrence of a software fault,
usually generated by external interference or by unforeseen logical conditions, which
causes the application program to abandon its normal sequence. The watchdog circuit
generates an MCU reset on expiry of a programmed time period, unless the program
refreshes the contents of the downcounter before the T6 bit becomes cleared. An MCU
reset is also generated if the 7-bit downcounter value (in the control register) is refreshed
before the downcounter has reached the window register value. This implies that the
counter must be refreshed in a limited window.
The WWDG clock is prescaled from the APB clock and has a configurable time-window that
can be programmed to detect abnormally late or early application behavior.
The WWDG is best suited for applications which require the watchdog to react within an
accurate timing window.

20.2

WWDG main features


Programmable free-running downcounter



Conditional reset



20.3

–

Reset (if watchdog activated) when the downcounter value becomes less than
0x40

–

Reset (if watchdog activated) if the downcounter is reloaded outside the window
(see Figure 191)

Early wakeup interrupt (EWI): triggered (if enabled and the watchdog activated) when
the downcounter is equal to 0x40.

WWDG functional description
If the watchdog is activated (the WDGA bit is set in the WWDG_CR register) and when the
7-bit downcounter (T[6:0] bits) is decremented from 0x40 to 0x3F (T6 becomes cleared), it
initiates a reset. If the software reloads the counter while the counter is greater than the
value stored in the window register, then a reset is generated.
The application program must write in the WWDG_CR register at regular intervals during
normal operation to prevent an MCU reset. This operation must occur only when the counter
value is lower than the window register value and higher than 0x3F. The value to be stored
in the WWDG_CR register must be between 0xFF and 0xC0.
Refer to Figure 190 for WWDG block diagram.

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System window watchdog (WWDG)
Figure 190. Watchdog block diagram
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20.3.1

Enabling the watchdog
The watchdog is always disabled after a reset. It is enabled by setting the WDGA bit in the
WWDG_CR register, then it cannot be disabled again except by a reset.

20.3.2

Controlling the downcounter
This downcounter is free-running, counting down even if the watchdog is disabled. When
the watchdog is enabled, the T6 bit must be set to prevent generating an immediate reset.
The T[5:0] bits contain the number of increments which represents the time delay before the
watchdog produces a reset. The timing varies between a minimum and a maximum value
due to the unknown status of the prescaler when writing to the WWDG_CR register (see
Figure 191). The Configuration register (WWDG_CFR) contains the high limit of the window:
To prevent a reset, the downcounter must be reloaded when its value is lower than the
window register value and greater than 0x3F. Figure 191 describes the window watchdog
process.

Note:

The T6 bit can be used to generate a software reset (the WDGA bit is set and the T6 bit is
cleared).

20.3.3

Advanced watchdog interrupt feature
The Early Wakeup Interrupt (EWI) can be used if specific safety operations or data logging
must be performed before the actual reset is generated. The EWI interrupt is enabled by
setting the EWI bit in the WWDG_CFR register. When the downcounter reaches the value
0x40, an EWI interrupt is generated and the corresponding interrupt service routine (ISR)
can be used to trigger specific actions (such as communications or data logging), before
resetting the device.
In some applications, the EWI interrupt can be used to manage a software system check
and/or system recovery/graceful degradation, without generating a WWDG reset. In this
case, the corresponding interrupt service routine (ISR) should reload the WWDG counter to
avoid the WWDG reset, then trigger the required actions.
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System window watchdog (WWDG)

RM0360

The EWI interrupt is cleared by writing '0' to the EWIF bit in the WWDG_SR register.
Note:

When the EWI interrupt cannot be served, e.g. due to a system lock in a higher priority task,
the WWDG reset will eventually be generated.

20.3.4

How to program the watchdog timeout
You can use the formula in Figure 191 to calculate the WWDG timeout.

Warning:

When writing to the WWDG_CR register, always write 1 in the
T6 bit to avoid generating an immediate reset.

Figure 191. Window watchdog timing diagram
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The formula to calculate the timeout value is given by:
WDGTB[1:0]
  T  5:0  + 1 
t WWDG = t PCLK  4096  2

 ms 

where:
tWWDG: WWDG timeout
tPCLK: APB clock period measured in ms
4096: value corresponding to internal divider
As an example, lets assume APB frequency is equal to 48 MHz, WDGTB[1:0] is set to 3 and
T[5:0] is set to 63:
3
t WWDG = 1  48000  4096  2   63 + 1  = 43.69 ms

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System window watchdog (WWDG)

Refer to the datasheet for the minimum and maximum values of the tWWDG.

20.3.5

Debug mode
When the microcontroller enters debug mode (ARM® Cortex®-M0 core halted), the WWDG
counter either continues to work normally or stops, depending on DBG_WWDG_STOP
configuration bit in DBG module. For more details, refer to Section 26.9.2: Debug support
for timers, watchdog and I2C.

20.4

WWDG registers
Refer to Section 1.1 on page 33 for a list of abbreviations used in register descriptions.
The peripheral registers can be accessed by half-words (16-bit) or words (32-bit).

20.4.1

Control register (WWDG_CR)
Address offset: 0x00
Reset value: 0x0000 007F

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

6

5

4

3

2

1

0

15

14

13

12

11

10

9

8

7

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

WDGA

T[6:0]

rs

rw

Bits 31:8 Reserved, must be kept at reset value.
Bit 7 WDGA: Activation bit
This bit is set by software and only cleared by hardware after a reset. When WDGA = 1, the
watchdog can generate a reset.
0: Watchdog disabled
1: Watchdog enabled
Bits 6:0 T[6:0]: 7-bit counter (MSB to LSB)
These bits contain the value of the watchdog counter. It is decremented every (4096 x
2WDGTB[1:0]) PCLK cycles. A reset is produced when it is decremented from 0x40 to 0x3F (T6
becomes cleared).

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System window watchdog (WWDG)

20.4.2

RM0360

Configuration register (WWDG_CFR)
Address offset: 0x04
Reset value: 0x0000 007F

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

8

7

6

5

4

3

2

1

0

rw

rw

rw

15

14

13

12

11

10

9

Res.

Res.

Res.

Res.

Res.

Res.

EWI
rs

WDGTB[1:0]
rw

rw

W[6:0]
rw

rw

rw

rw

Bits 31:10 Reserved, must be kept at reset value.
Bit 9 EWI: Early wakeup interrupt
When set, an interrupt occurs whenever the counter reaches the value 0x40. This interrupt is
only cleared by hardware after a reset.
Bits 8:7 WDGTB[1:0]: Timer base
The time base of the prescaler can be modified as follows:
00: CK Counter Clock (PCLK div 4096) div 1
01: CK Counter Clock (PCLK div 4096) div 2
10: CK Counter Clock (PCLK div 4096) div 4
11: CK Counter Clock (PCLK div 4096) div 8
Bits 6:0 W[6:0]: 7-bit window value
These bits contain the window value to be compared to the downcounter.

20.4.3

Status register (WWDG_SR)
Address offset: 0x08
Reset value: 0x0000 0000

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

EWIF
rc_w0

Bits 31:1 Reserved, must be kept at reset value.
Bit 0 EWIF: Early wakeup interrupt flag
This bit is set by hardware when the counter has reached the value 0x40. It must be cleared by
software by writing ‘0’. A write of ‘1’ has no effect. This bit is also set if the interrupt is not
enabled.

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20.4.4

System window watchdog (WWDG)

WWDG register map
The following table gives the WWDG register map and reset values.

0

1

1

1

1

1

Res.

Res.

Res.

Res.

1

1

1

Res.

0

1

EWIF

Res.

0

Res.

1

WDGTB0

1

Res.

1

WDGTB1

1

Res.

1

EWI

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

WWDG_
SR

Res.

0x08

Res.

Reset value

T[6:0]

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

WWDG_
CFR

Res.

0x04

0
Res.

Reset value

WDGA

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

WWDG_
CR

Res.

0x00

Res.

Register

Res.

Offset

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0

Table 61. WWDG register map and reset values

W[6:0]

Reset value

0

Refer to Section 2.2.2: Memory map and register boundary addresses for the register
boundary addresses.

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Real-time clock (RTC)

RM0360

21

Real-time clock (RTC)

21.1

Introduction
The RTC provides an automatic wakeup to manage all low-power modes.
The real-time clock (RTC) is an independent BCD timer/counter. The RTC provides a timeof-day clock/calendar with programmable alarm interrupt.
The RTC includes also a periodic programmable wakeup flag with interrupt capability.
Two 32-bit registers contain the seconds, minutes, hours (12- or 24-hour format), day (day
of week), date (day of month), month, and year, expressed in binary coded decimal format
(BCD). The sub-seconds value is also available in binary format.
Compensations for 28-, 29- (leap year), 30-, and 31-day months are performed
automatically. Daylight saving time compensation can also be performed.
Additional 32-bit registers contain the programmable alarm subseconds, seconds, minutes,
hours, day, and date.
A digital calibration feature is available to compensate for any deviation in crystal oscillator
accuracy.
After RTC domain reset, all RTC registers are protected against possible parasitic write
accesses.
As long as the supply voltage remains in the operating range, the RTC never stops,
regardless of the device status (Run mode, low-power mode or under reset).

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21.2

Real-time clock (RTC)

RTC main features
The RTC unit main features are the following (see Figure 192: RTC block diagram in
STM32F030x4/6, STM32F070x6 and STM32F030x8 devices and Figure 193: RTC block
diagram for STM32F070xB and STM32F030xC devices):

21.3



Calendar with subseconds, seconds, minutes, hours (12 or 24 format), day (day of
week), date (day of month), month, and year.



Daylight saving compensation programmable by software.



Programmable alarm with interrupt function. The alarm can be triggered by any
combination of the calendar fields.



Automatic wakeup unit generating a periodic flag that triggers an automatic wakeup
interrupt.



Reference clock detection: a more precise second source clock (50 or 60 Hz) can be
used to enhance the calendar precision.



Accurate synchronization with an external clock using the subsecond shift feature.



Digital calibration circuit (periodic counter correction): 0.95 ppm accuracy, obtained in a
calibration window of several seconds



Time-stamp function for event saving



Tamper detection event with configurable filter and internal pull-up



Maskable interrupts/events:
–

Alarm A

–

Wakeup interrupt

–

Time-stamp

–

Tamper detection

RTC implementation
Table 62. STM32F0x0 RTC implementation(1)
STM32F030x4,
STM32F030x6
STM32F070x6
STM32F030x8

STM32F070xB
STM32F030xC

Periodic wakeup timer

-

X

RTC_TAMP1

X

X

RTC_TAMP2

X

X

RTC_TAMP3

-

-

Alarm A

X

X

RTC Features

1. X = supported, ‘-’= not supported.

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Real-time clock (RTC)

RM0360

21.4

RTC functional description

21.4.1

RTC block diagram

Figure 192. RTC block diagram in STM32F030x4/6, STM32F070x6 and STM32F030x8 devices
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Real-time clock (RTC)
Figure 193. RTC block diagram for STM32F070xB and STM32F030xC devices
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The RTC includes:


One alarm



Two tamper events from I/Os
–

Tamper detection erases the backup registers.



One timestamp event from I/O



Tamper event detection can generate a timestamp event



Alternate function outputs: RTC_OUT which selects one of the following two outputs:



–

RTC_CALIB: 512 Hz or 1Hz clock output (with an LSE frequency of 32.768 kHz).
This output is enabled by setting the COE bit in the RTC_CR register.

–

RTC_ALARM: Alarm A. This output is selected by configuring the OSEL[1:0] bits
in the RTC_CR register.

Alternate function inputs:
–

RTC_TS: timestamp event

–

RTC_TAMP1: tamper1 event detection

–

RTC_TAMP2: tamper2 event detection

–

RTC_REFIN: 50 or 60 Hz reference clock input

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Real-time clock (RTC)

21.4.2

RM0360

GPIOs controlled by the RTC
RTC_OUT, RTC_TS and RTC_TAMP1 are mapped on the same pin (PC13).
The selection of the RTC_ALARM output is performed through the RTC_TAFCR register as
follows: the PC13VALUE bit is used to select whether the RTC_ALARM output is configured
in push-pull or open drain mode.
When PC13 is not used as RTC alternate function, it can be forced in output push-pull mode
by setting the PC13MODE bit in the RTC_TAFCR. The output data value is then given by
the PC13VALUE bit. In this case, PC13 output push-pull state and data are preserved in
Standby mode.
The output mechanism follows the priority order shown in Table 63.
When PC14 and PC15 are not used as LSE oscillator, they can be forced in output push-pull
mode by setting the PC14MODE and PC15MODE bits in the RTC_TAFCR register
respectively. The output data values are then given by PC14VALUE and PC15VALUE. In
this case, the PC14 and PC15 output push-pull states and data values are preserved in
Standby mode.
The output mechanism follows the priority order shown in Table 64 and Table 65.
Table 63. RTC pin PC13 configuration(1)

Pin
configuration
and function

RTC_ALARM
output
enabled

RTC_CALIB
output
enabled

RTC_TAMP1
input
enabled

RTC_TS
input
enabled

PC13MODE
bit

PC13VALUE
bit

RTC_ALARM
output OD

1

Don’t care

Don’t care

Don’t care

Don’t care

0

RTC_ALARM
output PP

1

Don’t care

Don’t care

Don’t care

Don’t care

1

RTC_CALIB
output PP

0

1

Don’t care

Don’t care

Don’t care

Don’t care

RTC_TAMP1
input floating

0

0

1

0

Don’t care

Don’t care

RTC_TS and
RTC_TAMP1
input floating

0

0

1

1

Don’t care

Don’t care

RTC_TS input
floating

0

0

0

1

Don’t care

Don’t care

Output PP
forced

0

0

0

0

1

PC13 output
data value

Wakeup pin or
Standard
GPIO

0

0

0

0

0

Don’t care

1. OD: open drain; PP: push-pull.

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Real-time clock (RTC)
Table 64. LSE pin PC14 configuration (1)

Pin configuration and
function

LSEON bit in
RCC_BDCR register

LSEBYP bit in
RCC_BDCR register

PC14MODE
bit

PC14VALUE
bit

LSE oscillator

1

0

Don’t care

Don’t care

LSE bypass

1

1

Don’t care

Don’t care

Output PP forced

0

Don’t care

1

PC14 output data
value

Standard GPIO

0

Don’t care

0

Don’t care

1. OD: open drain; PP: push-pull.

Table 65. LSE pin PC15 configuration (1)
Pin configuration and
function

LSEON bit in
RCC_BDCR register

LSEBYP bit in
RCC_BDCR register

PC15MODE
bit

PC15VALUE
bit

1

0

Don’t care

Don’t care

1

1

0

Don’t care

1

PC15 output data
value

0

Don’t care

0

Don’t care

LSE oscillator
Output PP forced
Standard GPIO
1. OD: open drain; PP: push-pull.

21.4.3

Clock and prescalers
The RTC clock source (RTCCLK) is selected through the clock controller among the LSE
clock, the LSI oscillator clock, and the HSE clock. For more information on the RTC clock
source configuration, refer to .
A programmable prescaler stage generates a 1 Hz clock which is used to update the
calendar. To minimize power consumption, the prescaler is split into 2 programmable
prescalers (see Figure 192: RTC block diagram in STM32F030x4/6, STM32F070x6 and
STM32F030x8 devices):

Note:



A 7-bit asynchronous prescaler configured through the PREDIV_A bits of the
RTC_PRER register.



A 15-bit synchronous prescaler configured through the PREDIV_S bits of the
RTC_PRER register.

When both prescalers are used, it is recommended to configure the asynchronous prescaler
to a high value to minimize consumption.
The asynchronous prescaler division factor is set to 128, and the synchronous division
factor to 256, to obtain an internal clock frequency of 1 Hz (ck_spre) with an LSE frequency
of 32.768 kHz.
The minimum division factor is 1 and the maximum division factor is 222.
This corresponds to a maximum input frequency of around 4 MHz.

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fck_apre is given by the following formula:
f RTCCLK
f CK_APRE = --------------------------------------PREDIV_A + 1

The ck_apre clock is used to clock the binary RTC_SSR subseconds downcounter. When it
reaches 0, RTC_SSR is reloaded with the content of PREDIV_S.
fck_spre is given by the following formula:
f RTCCLK
f CK_SPRE = --------------------------------------------------------------------------------------------- PREDIV_S + 1    PREDIV_A + 1 

The ck_spre clock can be used either to update the calendar or as timebase for the 16-bit
wakeup auto-reload timer. To obtain short timeout periods, the 16-bit wakeup auto-reload
timer can also run with the RTCCLK divided by the programmable 4-bit asynchronous
prescaler (see Section 21.4.6: Periodic auto-wakeup for details).

21.4.4

Real-time clock and calendar
The RTC calendar time and date registers are accessed through shadow registers which
are synchronized with PCLK (APB clock). They can also be accessed directly in order to
avoid waiting for the synchronization duration.


RTC_SSR for the subseconds



RTC_TR for the time



RTC_DR for the date

Every two RTCCLK periods, the current calendar value is copied into the shadow registers,
and the RSF bit of RTC_ISR register is set (see Section 21.7.4: RTC initialization and status
register (RTC_ISR)). The copy is not performed in Stop and Standby mode. When exiting
these modes, the shadow registers are updated after up to 2 RTCCLK periods.
When the application reads the calendar registers, it accesses the content of the shadow
registers. It is possible to make a direct access to the calendar registers by setting the
BYPSHAD control bit in the RTC_CR register. By default, this bit is cleared, and the user
accesses the shadow registers.
When reading the RTC_SSR, RTC_TR or RTC_DR registers in BYPSHAD=0 mode, the
frequency of the APB clock (fAPB) must be at least 7 times the frequency of the RTC clock
(fRTCCLK).
The shadow registers are reset by system reset.

21.4.5

Programmable alarm
The RTC unit provides programmable alarm: Alarm A.
The programmable alarm function is enabled through the ALRAE bit in the RTC_CR
register. The ALRAF is set to 1 if the calendar subseconds, seconds, minutes, hours, date
or day match the values programmed in the alarm registers RTC_ALRMASSR and
RTC_ALRMAR. Each calendar field can be independently selected through the MSKx bits
of the RTC_ALRMAR register, and through the MASKSSx bits of the RTC_ALRMASSR
register. The alarm interrupt is enabled through the ALRAIE bit in the RTC_CR register.

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If the seconds field is selected (MSK1 bit reset in RTC_ALRMAR), the synchronous
prescaler division factor set in the RTC_PRER register must be at least 3 to ensure correct
behavior.
Alarm A (if enabled by bits OSEL[1:0] in RTC_CR register) can be routed to the
RTC_ALARM output. RTC_ALARM output polarity can be configured through bit POL the
RTC_CR register.

21.4.6

Periodic auto-wakeup
The periodic wakeup flag is generated by a 16-bit programmable auto-reload down-counter.
The wakeup timer range can be extended to 17 bits.
The wakeup function is enabled through the WUTE bit in the RTC_CR register.
The wakeup timer clock input can be:


RTC clock (RTCCLK) divided by 2, 4, 8, or 16.
When RTCCLK is LSE(32.768kHz), this allows to configure the wakeup interrupt period
from 122 µs to 32 s, with a resolution down to 61 µs.



ck_spre (usually 1 Hz internal clock)
When ck_spre frequency is 1Hz, this allows to achieve a wakeup time from 1 s to
around 36 hours with one-second resolution. This large programmable time range is
divided in 2 parts:
–

from 1s to 18 hours when WUCKSEL [2:1] = 10

–

and from around 18h to 36h when WUCKSEL[2:1] = 11. In this last case 216 is
added to the 16-bit counter current value.When the initialization sequence is
complete (see Programming the wakeup timer on page 495), the timer starts
counting down.When the wakeup function is enabled, the down-counting remains
active in low-power modes. In addition, when it reaches 0, the WUTF flag is set in
the RTC_ISR register, and the wakeup counter is automatically reloaded with its
reload value (RTC_WUTR register value).

The WUTF flag must then be cleared by software.
When the periodic wakeup interrupt is enabled by setting the WUTIE bit in the RTC_CR2
register, it can exit the device from low-power modes.
The periodic wakeup flag can be routed to the RTC_ALARM output provided it has been
enabled through bits OSEL[1:0] of RTC_CR register. RTC_ALARM output polarity can be
configured through the POL bit in the RTC_CR register.
System reset, as well as low-power modes (Sleep, Stop and Standby) have no influence on
the wakeup timer.

21.4.7

RTC initialization and configuration
RTC register access
The RTC registers are 32-bit registers. The APB interface introduces 2 wait-states in RTC
register accesses except on read accesses to calendar shadow registers when
BYPSHAD=0.

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RTC register write protection
After system reset, the RTC registers are protected against parasitic write access by
clearing the DBP bit in the PWR_CR register (refer to the power control section). DBP bit
must be set in order to enable RTC registers write access.
After RTC domain reset, all the RTC registers are write-protected. Writing to the RTC
registers is enabled by writing a key into the Write Protection register, RTC_WPR.
The following steps are required to unlock the write protection on all the RTC registers
except for RTC_TAFCR and RTC_ISR[13:8].
1.

Write ‘0xCA’ into the RTC_WPR register.

2.

Write ‘0x53’ into the RTC_WPR register.

Writing a wrong key reactivates the write protection.
The protection mechanism is not affected by system reset.

Calendar initialization and configuration
To program the initial time and date calendar values, including the time format and the
prescaler configuration, the following sequence is required:
1.

Set INIT bit to 1 in the RTC_ISR register to enter initialization mode. In this mode, the
calendar counter is stopped and its value can be updated.

2.

Poll INITF bit of in the RTC_ISR register. The initialization phase mode is entered when
INITF is set to 1. It takes around 2 RTCCLK clock cycles (due to clock synchronization).

3.

To generate a 1 Hz clock for the calendar counter, program both the prescaler factors in
RTC_PRER register.

4.

Load the initial time and date values in the shadow registers (RTC_TR and RTC_DR),
and configure the time format (12 or 24 hours) through the FMT bit in the RTC_CR
register.

5.

Exit the initialization mode by clearing the INIT bit. The actual calendar counter value is
then automatically loaded and the counting restarts after 4 RTCCLK clock cycles.

When the initialization sequence is complete, the calendar starts counting.
Note:

After a system reset, the application can read the INITS flag in the RTC_ISR register to
check if the calendar has been initialized or not. If this flag equals 0, the calendar has not
been initialized since the year field is set at its RTC domain reset default value (0x00).
To read the calendar after initialization, the software must first check that the RSF flag is set
in the RTC_ISR register.
For code example refer to the Appendix section A.13.1: RTC calendar configuration code
example.

Daylight saving time
The daylight saving time management is performed through bits SUB1H, ADD1H, and BKP
of the RTC_CR register.
Using SUB1H or ADD1H, the software can subtract or add one hour to the calendar in one
single operation without going through the initialization procedure.
In addition, the software can use the BKP bit to memorize this operation.

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Programming the alarm
A similar procedure must be followed to program or update the programmable alarms.

Note:

1.

Clear ALRAE in RTC_CR to disable Alarm A.

2.

Program the Alarm A registers (RTC_ALRMASSR/RTC_ALRMAR).

3.

Set ALRAE in the RTC_CR register to enable Alarm A again.

Each change of the RTC_CR register is taken into account after around 2 RTCCLK clock
cycles due to clock synchronization.
For code example refer to the Appendix section A.13.2: RTC alarm configuration code
example.

Programming the wakeup timer
The following sequence is required to configure or change the wakeup timer auto-reload
value (WUT[15:0] in RTC_WUTR):
1.

Clear WUTE in RTC_CR to disable the wakeup timer.

2.

Poll WUTWF until it is set in RTC_ISR to make sure the access to wakeup auto-reload
counter and to WUCKSEL[2:0] bits is allowed. It takes around 2 RTCCLK clock cycles
(due to clock synchronization).

3.

Program the wakeup auto-reload value WUT[15:0], and the wakeup clock selection
(WUCKSEL[2:0] bits in RTC_CR). Set WUTE in RTC_CR to enable the timer again.
The wakeup timer restarts down-counting. The WUTWF bit is cleared up to 2 RTCCLK
clock cycles after WUTE is cleared, due to clock synchronization.

For code example refer to the Appendix section A.13.3: RTC WUT configuration code
example.

21.4.8

Reading the calendar
When BYPSHAD control bit is cleared in the RTC_CR register
To read the RTC calendar registers (RTC_SSR, RTC_TR and RTC_DR) properly, the APB
clock frequency (fPCLK) must be equal to or greater than seven times the RTC clock
frequency (fRTCCLK). This ensures a secure behavior of the synchronization mechanism.
If the APB clock frequency is less than seven times the RTC clock frequency, the software
must read the calendar time and date registers twice. If the second read of the RTC_TR
gives the same result as the first read, this ensures that the data is correct. Otherwise a third
read access must be done. In any case the APB clock frequency must never be lower than
the RTC clock frequency.
The RSF bit is set in RTC_ISR register each time the calendar registers are copied into the
RTC_SSR, RTC_TR and RTC_DR shadow registers. The copy is performed every two
RTCCLK cycles. To ensure consistency between the 3 values, reading either RTC_SSR or
RTC_TR locks the values in the higher-order calendar shadow registers until RTC_DR is
read. In case the software makes read accesses to the calendar in a time interval smaller
than 2 RTCCLK periods: RSF must be cleared by software after the first calendar read, and
then the software must wait until RSF is set before reading again the RTC_SSR, RTC_TR
and RTC_DR registers.
After waking up from low-power mode (Stop or Standby), RSF must be cleared by software.
The software must then wait until it is set again before reading the RTC_SSR, RTC_TR and
RTC_DR registers.
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The RSF bit must be cleared after wakeup and not before entering low-power mode.
After a system reset, the software must wait until RSF is set before reading the RTC_SSR,
RTC_TR and RTC_DR registers. Indeed, a system reset resets the shadow registers to
their default values.
After an initialization (refer to Calendar initialization and configuration on page 494): the
software must wait until RSF is set before reading the RTC_SSR, RTC_TR and RTC_DR
registers.
After synchronization (refer to Section 21.4.10: RTC synchronization): the software must
wait until RSF is set before reading the RTC_SSR, RTC_TR and RTC_DR registers.
For code example refer to the Appendix section A.13.4: RTC read calendar code example.

When the BYPSHAD control bit is set in the RTC_CR register (bypass shadow
registers)
Reading the calendar registers gives the values from the calendar counters directly, thus
eliminating the need to wait for the RSF bit to be set. This is especially useful after exiting
from low-power modes (STOP or Standby), since the shadow registers are not updated
during these modes.
When the BYPSHAD bit is set to 1, the results of the different registers might not be
coherent with each other if an RTCCLK edge occurs between two read accesses to the
registers. Additionally, the value of one of the registers may be incorrect if an RTCCLK edge
occurs during the read operation. The software must read all the registers twice, and then
compare the results to confirm that the data is coherent and correct. Alternatively, the
software can just compare the two results of the least-significant calendar register.
Note:

While BYPSHAD=1, instructions which read the calendar registers require one extra APB
cycle to complete.

21.4.9

Resetting the RTC
The calendar shadow registers (RTC_SSR, RTC_TR and RTC_DR) and some bits of the
RTC status register (RTC_ISR) are reset to their default values by all available system reset
sources.
On the contrary, the following registers are reset to their default values by a RTC domain
reset and are not affected by a system reset: the RTC current calendar registers, the RTC
control register (RTC_CR), the prescaler register (RTC_PRER), the RTC calibration register
(RTC_CALR), the RTC shift register (RTC_SHIFTR), the RTC timestamp registers
(RTC_TSSSR, RTC_TSTR and RTC_TSDR), the RTC tamper and alternate function
configuration register (RTC_TAFCR), the wakeup timer register (RTC_WUTR), the Alarm A
registers (RTC_ALRMASSR/RTC_ALRMAR).
In addition, when it is clocked by the LSE, the RTC keeps on running under system reset if
the reset source is different from the RTC domain reset one (refer to the RTC clock section
of the Reset and clock controller for details on the list of RTC clock sources not affected by
system reset). When a RTC domain reset occurs, the RTC is stopped and all the RTC
registers are set to their reset values.

21.4.10

RTC synchronization
The RTC can be synchronized to a remote clock with a high degree of precision. After
reading the sub-second field (RTC_SSR or RTC_TSSSR), a calculation can be made of the

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precise offset between the times being maintained by the remote clock and the RTC. The
RTC can then be adjusted to eliminate this offset by “shifting” its clock by a fraction of a
second using RTC_SHIFTR.
RTC_SSR contains the value of the synchronous prescaler counter. This allows one to
calculate the exact time being maintained by the RTC down to a resolution of 
1 / (PREDIV_S + 1) seconds. As a consequence, the resolution can be improved by
increasing the synchronous prescaler value (PREDIV_S[14:0]. The maximum resolution
allowed (30.52 μs with a 32768 Hz clock) is obtained with PREDIV_S set to 0x7FFF.
However, increasing PREDIV_S means that PREDIV_A must be decreased in order to
maintain the synchronous prescaler output at 1 Hz. In this way, the frequency of the
asynchronous prescaler output increases, which may increase the RTC dynamic
consumption.
The RTC can be finely adjusted using the RTC shift control register (RTC_SHIFTR). Writing
to RTC_SHIFTR can shift (either delay or advance) the clock by up to a second with a
resolution of 1 / (PREDIV_S + 1) seconds. The shift operation consists of adding the
SUBFS[14:0] value to the synchronous prescaler counter SS[15:0]: this will delay the clock.
If at the same time the ADD1S bit is set, this results in adding one second and at the same
time subtracting a fraction of second, so this will advance the clock.

Caution:

Before initiating a shift operation, the user must check that SS[15] = 0 in order to ensure that
no overflow will occur.
As soon as a shift operation is initiated by a write to the RTC_SHIFTR register, the SHPF
flag is set by hardware to indicate that a shift operation is pending. This bit is cleared by
hardware as soon as the shift operation has completed.

Caution:

This synchronization feature is not compatible with the reference clock detection feature:
firmware must not write to RTC_SHIFTR when REFCKON=1.

21.4.11

RTC reference clock detection
The update of the RTC calendar can be synchronized to a reference clock, RTC_REFIN,
which is usually the mains frequency (50 or 60 Hz). The precision of the RTC_REFIN
reference clock should be higher than the 32.768 kHz LSE clock. When the RTC_REFIN
detection is enabled (REFCKON bit of RTC_CR set to 1), the calendar is still clocked by the
LSE, and RTC_REFIN is used to compensate for the imprecision of the calendar update
frequency (1 Hz).
Each 1 Hz clock edge is compared to the nearest RTC_REFIN clock edge (if one is found
within a given time window). In most cases, the two clock edges are properly aligned. When
the 1 Hz clock becomes misaligned due to the imprecision of the LSE clock, the RTC shifts
the 1 Hz clock a bit so that future 1 Hz clock edges are aligned. Thanks to this mechanism,
the calendar becomes as precise as the reference clock.
The RTC detects if the reference clock source is present by using the 256 Hz clock
(ck_apre) generated from the 32.768 kHz quartz. The detection is performed during a time
window around each of the calendar updates (every 1 s). The window equals 7 ck_apre
periods when detecting the first reference clock edge. A smaller window of 3 ck_apre
periods is used for subsequent calendar updates.
Each time the reference clock is detected in the window, the asynchronous prescaler which
outputs the ck_apre clock is forced to reload. This has no effect when the reference clock
and the 1 Hz clock are aligned because the prescaler is being reloaded at the same

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moment. When the clocks are not aligned, the reload shifts future 1 Hz clock edges a little
for them to be aligned with the reference clock.
If the reference clock halts (no reference clock edge occurred during the 3 ck_apre window),
the calendar is updated continuously based solely on the LSE clock. The RTC then waits for
the reference clock using a large 7 ck_apre period detection window centered on the
ck_spre edge.
When the RTC_REFIN detection is enabled, PREDIV_A and PREDIV_S must be set to their
default values:


PREDIV_A = 0x007F



PREVID_S = 0x00FF

Note:

RTC_REFIN clock detection is not available in Standby mode.

21.4.12

RTC smooth digital calibration
The RTC frequency can be digitally calibrated with a resolution of about 0.954 ppm with a
range from -487.1 ppm to +488.5 ppm. The correction of the frequency is performed using
series of small adjustments (adding and/or subtracting individual RTCCLK pulses). These
adjustments are fairly well distributed so that the RTC is well calibrated even when observed
over short durations of time.
The smooth digital calibration is performed during a cycle of about 220 RTCCLK pulses, or
32 seconds when the input frequency is 32768 Hz. This cycle is maintained by a 20-bit
counter, cal_cnt[19:0], clocked by RTCCLK.
The smooth calibration register (RTC_CALR) specifies the number of RTCCLK clock cycles
to be masked during the 32-second cycle:


Setting the bit CALM[0] to 1 causes exactly one pulse to be masked during the 32-

second cycle.

Note:



Setting CALM[1] to 1 causes two additional cycles to be masked



Setting CALM[2] to 1 causes four additional cycles to be masked



and so on up to CALM[8] set to 1 which causes 256 clocks to be masked.

CALM[8:0] (RTC_CALR) specifies the number of RTCCLK pulses to be masked during the
32-second cycle. Setting the bit CALM[0] to ‘1’ causes exactly one pulse to be masked
during the 32-second cycle at the moment when cal_cnt[19:0] is 0x80000; CALM[1]=1
causes two other cycles to be masked (when cal_cnt is 0x40000 and 0xC0000); CALM[2]=1
causes four other cycles to be masked (cal_cnt = 0x20000/0x60000/0xA0000/ 0xE0000);
and so on up to CALM[8]=1 which causes 256 clocks to be masked (cal_cnt = 0xXX800).
While CALM allows the RTC frequency to be reduced by up to 487.1 ppm with fine
resolution, the bit CALP can be used to increase the frequency by 488.5 ppm. Setting CALP
to ‘1’ effectively inserts an extra RTCCLK pulse every 211 RTCCLK cycles, which means
that 512 clocks are added during every 32-second cycle.
Using CALM together with CALP, an offset ranging from -511 to +512 RTCCLK cycles can
be added during the 32-second cycle, which translates to a calibration range of -487.1 ppm
to +488.5 ppm with a resolution of about 0.954 ppm.
The formula to calculate the effective calibrated frequency (FCAL) given the input frequency
(FRTCCLK) is as follows:
FCAL = FRTCCLK x [1 + (CALP x 512 - CALM) / (220 + CALM - CALP x 512)]

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Calibration when PREDIV_A<3
The CALP bit can not be set to 1 when the asynchronous prescaler value (PREDIV_A bits in
RTC_PRER register) is less than 3. If CALP was already set to 1 and PREDIV_A bits are
set to a value less than 3, CALP is ignored and the calibration operates as if CALP was
equal to 0.
To perform a calibration with PREDIV_A less than 3, the synchronous prescaler value
(PREDIV_S) should be reduced so that each second is accelerated by 8 RTCCLK clock
cycles, which is equivalent to adding 256 clock cycles every 32 seconds. As a result,
between 255 and 256 clock pulses (corresponding to a calibration range from 243.3 to
244.1 ppm) can effectively be added during each 32-second cycle using only the CALM bits.
With a nominal RTCCLK frequency of 32768 Hz, when PREDIV_A equals 1 (division factor
of 2), PREDIV_S should be set to 16379 rather than 16383 (4 less). The only other
interesting case is when PREDIV_A equals 0, PREDIV_S should be set to 32759 rather
than 32767 (8 less).
If PREDIV_S is reduced in this way, the formula given the effective frequency of the
calibrated input clock is as follows:
FCAL = FRTCCLK x [1 + (256 - CALM) / (220 + CALM - 256)]
In this case, CALM[7:0] equals 0x100 (the midpoint of the CALM range) is the correct
setting if RTCCLK is exactly 32768.00 Hz.

Verifying the RTC calibration
RTC precision is ensured by measuring the precise frequency of RTCCLK and calculating
the correct CALM value and CALP values. An optional 1 Hz output is provided to allow
applications to measure and verify the RTC precision.
Measuring the precise frequency of the RTC over a limited interval can result in a
measurement error of up to 2 RTCCLK clock cycles over the measurement period,
depending on how the digital calibration cycle is aligned with the measurement period.
However, this measurement error can be eliminated if the measurement period is the same
length as the calibration cycle period. In this case, the only error observed is the error due to
the resolution of the digital calibration.


By default, the calibration cycle period is 32 seconds.

Using this mode and measuring the accuracy of the 1 Hz output over exactly 32 seconds
guarantees that the measure is within 0.477 ppm (0.5 RTCCLK cycles over 32 seconds, due
to the limitation of the calibration resolution).


CALW16 bit of the RTC_CALR register can be set to 1 to force a 16- second calibration
cycle period.

In this case, the RTC precision can be measured during 16 seconds with a maximum error
of 0.954 ppm (0.5 RTCCLK cycles over 16 seconds). However, since the calibration
resolution is reduced, the long term RTC precision is also reduced to 0.954 ppm: CALM[0]
bit is stuck at 0 when CALW16 is set to 1.


CALW8 bit of the RTC_CALR register can be set to 1 to force a 8- second calibration
cycle period.

In this case, the RTC precision can be measured during 8 seconds with a maximum error of
1.907 ppm (0.5 RTCCLK cycles over 8s). The long term RTC precision is also reduced to
1.907 ppm: CALM[1:0] bits are stuck at 00 when CALW8 is set to 1.

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Re-calibration on-the-fly
The calibration register (RTC_CALR) can be updated on-the-fly while RTC_ISR/INITF=0, by
using the follow process:
1.

Poll the RTC_ISR/RECALPF (re-calibration pending flag).

2.

If it is set to 0, write a new value to RTC_CALR, if necessary. RECALPF is then
automatically set to 1

3.

Within three ck_apre cycles after the write operation to RTC_CALR, the new calibration
settings take effect.

For code example refer to the Appendix section A.13.5: RTC calibration code example.

21.4.13

Time-stamp function
Time-stamp is enabled by setting the TSE bit of RTC_CR register to 1.
The calendar is saved in the time-stamp registers (RTC_TSSSR, RTC_TSTR, RTC_TSDR)
when a time-stamp event is detected on the RTC_TS pin.
When a time-stamp event occurs, the time-stamp flag bit (TSF) in RTC_ISR register is set.
By setting the TSIE bit in the RTC_CR register, an interrupt is generated when a time-stamp
event occurs.
If a new time-stamp event is detected while the time-stamp flag (TSF) is already set, the
time-stamp overflow flag (TSOVF) flag is set and the time-stamp registers (RTC_TSTR and
RTC_TSDR) maintain the results of the previous event.

Note:

TSF is set 2 ck_apre cycles after the time-stamp event occurs due to synchronization
process.
There is no delay in the setting of TSOVF. This means that if two time-stamp events are
close together, TSOVF can be seen as '1' while TSF is still '0'. As a consequence, it is
recommended to poll TSOVF only after TSF has been set.

Caution:

If a time-stamp event occurs immediately after the TSF bit is supposed to be cleared, then
both TSF and TSOVF bits are set.To avoid masking a time-stamp event occurring at the
same moment, the application must not write ‘0’ into TSF bit unless it has already read it to
‘1’.
Optionally, a tamper event can cause a time-stamp to be recorded. See the description of
the TAMPTS control bit in Section 21.7.15: RTC tamper and alternate function configuration
register (RTC_TAFCR).

21.4.14

Tamper detection
The RTC_TAMPx input events can be configured either for edge detection, or for level
detection with filtering.
The tamper detection can be configured for the following purpose:


generate an interrupt, capable to wakeup from Stop and Standby modes

Tamper detection initialization
Each input can be enabled by setting the corresponding TAMPxE bits to 1 in the
RTC_TAFCR register.

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Each RTC_TAMPx tamper detection input is associated with a flag TAMPxF in the RTC_ISR
register.
The TAMPxF flag is asserted after the tamper event on the pin, with the latency provided
below:


3 ck_apre cycles when TAMPFLT differs from 0x0 (Level detection with filtering)



3 ck_apre cycles when TAMPTS=1 (Timestamp on tamper event)



No latency when TAMPFLT=0x0 (Edge detection) and TAMPTS=0

A new tamper occurring on the same pin during this period and as long as TAMPxF is set
cannot be detected.
By setting the TAMPIE bit in the RTC_TAFCR register, an interrupt is generated when a
tamper detection event occurs. .

Timestamp on tamper event
With TAMPTS set to ‘1’, any tamper event causes a timestamp to occur. In this case, either
the TSF bit or the TSOVF bit are set in RTC_ISR, in the same manner as if a normal
timestamp event occurs. The affected tamper flag register TAMPxF is set at the same time
that TSF or TSOVF is set.

Edge detection on tamper inputs
If the TAMPFLT bits are “00”, the RTC_TAMPx pins generate tamper detection events when
either a rising edge or a falling edge is observed depending on the corresponding
TAMPxTRG bit. The internal pull-up resistors on the RTC_TAMPx inputs are deactivated
when edge detection is selected.
Caution:

To avoid losing tamper detection events, the signal used for edge detection is logically
ANDed with the corresponding TAMPxE bit in order to detect a tamper detection event in
case it occurs before the RTC_TAMPx pin is enabled.


When TAMPxTRG = 0: if the RTC_TAMPx alternate function is already high before
tamper detection is enabled (TAMPxE bit set to 1), a tamper event is detected as soon
as the RTC_TAMPx input is enabled, even if there was no rising edge on the
RTC_TAMPx input after TAMPxE was set.



When TAMPxTRG = 1: if the RTC_TAMPx alternate function is already low before
tamper detection is enabled, a tamper event is detected as soon as the RTC_TAMPx
input is enabled (even if there was no falling edge on the RTC_TAMPx input after
TAMPxE was set.

Level detection with filtering on RTC_TAMPx inputs
Level detection with filtering is performed by setting TAMPFLT to a non-zero value. A tamper
detection event is generated when either 2, 4, or 8 (depending on TAMPFLT) consecutive
samples are observed at the level designated by the TAMPxTRG bits.
The RTC_TAMPx inputs are precharged through the I/O internal pull-up resistance before
its state is sampled, unless disabled by setting TAMPPUDIS to 1,The duration of the
precharge is determined by the TAMPPRCH bits, allowing for larger capacitances on the
RTC_TAMPx inputs.
The trade-off between tamper detection latency and power consumption through the pull-up
can be optimized by using TAMPFREQ to determine the frequency of the sampling for level
detection.

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Note:

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Refer to the datasheets for the electrical characteristics of the pull-up resistors.
For code example refer to the Appendix sections: A.13.6: RTC tamper and time stamp
configuration code example and A.13.7: RTC tamper and time stamp code example.

21.4.15

Calibration clock output
When the COE bit is set to 1 in the RTC_CR register, a reference clock is provided on the
RTC_CALIB device output.
If the COSEL bit in the RTC_CR register is reset and PREDIV_A = 0x7F, the RTC_CALIB
frequency is fRTCCLK/64. This corresponds to a calibration output at 512 Hz for an RTCCLK
frequency at 32.768 kHz. The RTC_CALIB duty cycle is irregular: there is a light jitter on
falling edges. It is therefore recommended to use rising edges.
When COSEL is set and “PREDIV_S+1” is a non-zero multiple of 256 (i.e: PREDIV_S[7:0] =
0xFF), the RTC_CALIB frequency is fRTCCLK/(256 * (PREDIV_A+1)). This corresponds to a
calibration output at 1 Hz for prescaler default values (PREDIV_A = Ox7F, PREDIV_S =
0xFF), with an RTCCLK frequency at 32.768 kHz. The 1 Hz output is affected when a shift
operation is on going and may toggle during the shift operation (SHPF=1).

Note:

When the RTC_CALIB or RTC_ALARM output is selected, the RTC_OUT pin is
automatically configured in output alternate function.
When COSEL bit is cleared, the RTC_CALIB output is the output of the 6th stage of the
asynchronous prescaler.
When COSEL bit is set, the RTC_CALIB output is the output of the 8th stage of the
synchronous prescaler.
For code example refer to the Appendix section A.13.8: RTC clock output code example.

21.4.16

Alarm output
The OSEL[1:0] control bits in the RTC_CR register are used to activate the alarm alternate
function output RTC_ALARM, and to select the function which is output. These functions
reflect the contents of the corresponding flags in the RTC_ISR register.
The polarity of the output is determined by the POL control bit in RTC_CR so that the
opposite of the selected flag bit is output when POL is set to 1.

Alarm alternate function output
The RTC_ALARM pin can be configured in output open drain or output push-pull using the
control bit ALARMOUTTYPE in the RTC_TAFCR register.
Note:

Once the RTC_ALARM output is enabled, it has priority over RTC_CALIB (COE bit is don't
care and must be kept cleared).
When the RTC_CALIB or RTC_ALARM output is selected, the RTC_OUT pin is
automatically configured in output alternate function.

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21.5

Real-time clock (RTC)

RTC low-power modes
Table 66. Effect of low-power modes on RTC
Mode

Description

Sleep

No effect 
RTC interrupts cause the device to exit the Sleep mode.

Stop

The RTC remains active when the RTC clock source is LSE or LSI. RTC alarm, RTC
tamper event, RTC timestamp event, and RTC Wakeup cause the device to exit the Stop
mode.

The RTC remains active when the RTC clock source is LSE or LSI. RTC alarm, RTC
Standby tamper event, RTC timestamp event, and RTC Wakeup cause the device to exit the
Standby mode.

21.6

RTC interrupts
All RTC interrupts are connected to the NVIC controller. Refer to .
To enable RTC interrupt(s), the following sequence is required:
1.

Configure and enable the NVIC line(s) corresponding to the RTC event(s) in interrupt
mode and select the rising edge sensitivity.

2.

Configure and enable the RTC IRQ channel in the NVIC.

3.

Configure the RTC to generate RTC interrupt(s).
Table 67. Interrupt control bits
Interrupt event

Event flag

Enable
control
bit

Exit the
Sleep
mode

Exit the
Stop
mode

Exit the
Standby
mode

Alarm A

ALRAF

ALRAIE

yes

yes(1)

yes(1)

RTC_TS input (timestamp)

TSF

TSIE

yes

yes(1)

yes(1)

RTC_TAMP1 input detection

TAMP1F

TAMPIE

yes

yes(1)

yes(1)

RTC_TAMP2 input detection

TAMP2F

TAMPIE

yes

yes(1)

yes(1)

1. Wakeup from STOP and Standby modes is possible only when the RTC clock source is LSE or LSI.

21.7

RTC registers
Refer to Section 1.1 on page 33 of the reference manual for a list of abbreviations used in
register descriptions.
The peripheral registers can be accessed by words (32-bit).

21.7.1

RTC time register (RTC_TR)
The RTC_TR is the calendar time shadow register. This register must be written in
initialization mode only. Refer to Calendar initialization and configuration on page 494 and
Reading the calendar on page 495.

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This register is write protected. The write access procedure is described in RTC register
write protection on page 494.
Address offset: 0x00
RTC domain reset value: 0x0000 0000
System reset: 0x0000 0000 when BYPSHAD = 0. Not affected when BYPSHAD = 1.
31

30

29

28

27

26

25

24

23

22

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

PM
rw

15

14

13

Res.

12

11

MNT[2:0]
rw

rw

10

9

8

MNU[3:0]
rw

rw

rw

7

rw

20

19

18

HT[1:0]

16

HU[3:0]

rw

rw

rw

rw

rw

5

4

3

2

1

0

rw

rw

ST[2:0]
rw

17

rw

6

Res.

rw

21

rw

SU[3:0]
rw

rw

rw

Bits 31-23 Reserved, must be kept at reset value
Bit 22 PM: AM/PM notation
0: AM or 24-hour format
1: PM
Bits 21:20 HT[1:0]: Hour tens in BCD format
Bits 19:16 HU[3:0]: Hour units in BCD format
Bit 15 Reserved, must be kept at reset value.
Bits 14:12 MNT[2:0]: Minute tens in BCD format
Bits 11:8 MNU[3:0]: Minute units in BCD format
Bit 7 Reserved, must be kept at reset value.
Bits 6:4 ST[2:0]: Second tens in BCD format
Bits 3:0 SU[3:0]: Second units in BCD format

21.7.2

RTC date register (RTC_DR)
The RTC_DR is the calendar date shadow register. This register must be written in
initialization mode only. Refer to Calendar initialization and configuration on page 494 and
Reading the calendar on page 495.
This register is write protected. The write access procedure is described in RTC register
write protection on page 494.
Address offset: 0x04
RTC domain reset value: 0x0000 2101
System reset: 0x0000 2101 when BYPSHAD = 0. Not affected when BYPSHAD = 1.

31

30

29

28

27

26

25

24

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

15

14

13

12

11

10

9

8

rw

rw

rw

rw

WDU[2:0]
rw

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rw

MT
rw

rw

MU[3:0]

23

22

21

20

19

18

YT[3:0]

17

16

YU[3:0]

rw

rw

rw

rw

rw

rw

rw

rw

7

6

5

4

3

2

1

0

Res.

Res.

rw

rw

rw

rw

rw

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Real-time clock (RTC)

Bits 31:24 Reserved, must be kept at reset value
Bits 23:20 YT[3:0]: Year tens in BCD format
Bits 19:16 YU[3:0]: Year units in BCD format
Bits 15:13 WDU[2:0]: Week day units
000: forbidden
001: Monday
...
111: Sunday
Bit 12 MT: Month tens in BCD format
Bits 11:8 MU: Month units in BCD format
Bits 7:6 Reserved, must be kept at reset value.
Bits 5:4 DT[1:0]: Date tens in BCD format
Bits 3:0 DU[3:0]: Date units in BCD format

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RTC control register (RTC_CR)
Address offset: 0x08
RTC domain reset value: 0x0000 0000
System reset: not affected

31

30

29

28

27

26

25

24

23

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

COE

15

14

13

12

11

10

9

8

TSIE

WUTIE

rw

rw

Res.

ALRAIE

TSE

WUTE

rw

rw

rw

Res.

ALRAE

22

21

OSEL[1:0]

20

19

18

POL

COSEL

BKP

17

16

SUB1H ADD1H

rw

rw

rw

rw

rw

rw

w

w

7

6

5

4

3

2

1

0

Res.

rw

FMT
rw

BYPS
REFCKON TSEDGE
HAD
rw

rw

rw

WUCKSEL[2:0]
rw

rw

rw

Bits 31:24 Reserved, must be kept at reset value.
Bit 23 COE: Calibration output enable
This bit enables the RTC_CALIB output
0: Calibration output disabled
1: Calibration output enabled
Bits 22:21 OSEL[1:0]: Output selection
These bits are used to select the flag to be routed to RTC_ALARM output
00: Output disabled
01: Alarm A output enabled
10: Reserved
11: Wakeup output enabled
Bit 20 POL: Output polarity
This bit is used to configure the polarity of RTC_ALARM output
0: The pin is high when ALRAF/WUTF is asserted (depending on OSEL[1:0])
1: The pin is low when ALRAF/WUTF is asserted (depending on OSEL[1:0]).
Bit 19 COSEL: Calibration output selection
When COE=1, this bit selects which signal is output on RTC_CALIB.
0: Calibration output is 512 Hz
1: Calibration output is 1 Hz
These frequencies are valid for RTCCLK at 32.768 kHz and prescalers at their default values
(PREDIV_A=127 and PREDIV_S=255). Refer to Section 21.4.15: Calibration clock output
Bit 18 BKP: Backup
This bit can be written by the user to memorize whether the daylight saving time change has
been performed or not.
Bit 17 SUB1H: Subtract 1 hour (winter time change)
When this bit is set, 1 hour is subtracted to the calendar time if the current hour is not 0. This
bit is always read as 0.
Setting this bit has no effect when current hour is 0.
0: No effect
1: Subtracts 1 hour to the current time. This can be used for winter time change outside
initialization mode.

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Bit 16 ADD1H: Add 1 hour (summer time change)
When this bit is set, 1 hour is added to the calendar time. This bit is always read as 0.
0: No effect
1: Adds 1 hour to the current time. This can be used for summer time change outside
initialization mode.
Bit 15 TSIE: Time-stamp interrupt enable
0: Time-stamp Interrupt disable
1: Time-stamp Interrupt enable
Bit 14 WUTIE: Wakeup timer interrupt enable
0: Wakeup timer interrupt disabled
1: Wakeup timer interrupt enabled
Bit 13 Reserved, must be kept at reset value
Bit 12 ALRAIE: Alarm A interrupt enable
0: Alarm A interrupt disabled
1: Alarm A interrupt enabled
Bit 11 TSE: timestamp enable
0: timestamp disable
1: timestamp enable
Bit 10 WUTE: Wakeup timer enable
0: Wakeup timer disabled
1: Wakeup timer enabled
Bit 9 Reserved, must be kept at reset value
Bit 8 ALRAE: Alarm A enable
0: Alarm A disabled
1: Alarm A enabled
Bit 7 Reserved, must be kept at reset value.
Bit 6 FMT: Hour format
0: 24 hour/day format
1: AM/PM hour format
Bit 5 BYPSHAD: Bypass the shadow registers
0: Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken from
the shadow registers, which are updated once every two RTCCLK cycles.
1: Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken
directly from the calendar counters.
Note: If the frequency of the APB clock is less than seven times the frequency of RTCCLK,
BYPSHAD must be set to ‘1’.

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Bit 4 REFCKON: RTC_REFIN reference clock detection enable (50 or 60 Hz)
0: RTC_REFIN detection disabled
1: RTC_REFIN detection enabled
Note: PREDIV_S must be 0x00FF.
Bit 3 TSEDGE: Time-stamp event active edge
0: RTC_TS input rising edge generates a time-stamp event
1: RTC_TS input falling edge generates a time-stamp event
TSE must be reset when TSEDGE is changed to avoid unwanted TSF setting.
Bits 2:0 WUCKSEL[2:0]: Wakeup clock selection
000: RTC/16 clock is selected
001: RTC/8 clock is selected
010: RTC/4 clock is selected
011: RTC/2 clock is selected
10x: ck_spre (usually 1 Hz) clock is selected
11x: ck_spre (usually 1 Hz) clock is selected and 216 is added to the WUT counter value
(see note below)

Note:

Bits 7, 6 and 4 of this register can be written in initialization mode only (RTC_ISR/INITF = 1).
WUT = Wakeup unit counter value. WUT = (0x0000 to 0xFFFF) + 0x10000 added when
WUCKSEL[2:1 = 11].
Bits 2 to 0 of this register can be written only when RTC_CR WUTE bit = 0 and RTC_ISR
WUTWF bit = 1.
It is recommended not to change the hour during the calendar hour increment as it could
mask the incrementation of the calendar hour.
ADD1H and SUB1H changes are effective in the next second.
This register is write protected. The write access procedure is described in RTC register
write protection on page 494.

Caution:

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Real-time clock (RTC)

21.7.4

RTC initialization and status register (RTC_ISR)
This register is write protected (except for RTC_ISR[13:8] bits). The write access procedure
is described in RTC register write protection on page 494.
Address offset: 0x0C
RTC domain reset value: 0x0000 0007
System reset: not affected except INIT, INITF, and RSF bits which are cleared to ‘0’

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

RECALPF

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

TSF

WUTF

Res.

ALRAF

INIT

INITF

RSF

INITS

Res.

ALRAWF

rc_w0

rc_w0

rc_w0

rw

r

rc_w0

r

r

Res.

TAMP2F TAMP1F TSOVF
rc_w0

rc_w0

rc_w0

SHPF WUTWF
r

r

r

Bits 31:17 Reserved, must be kept at reset value
Bit 16 RECALPF: Recalibration pending Flag
The RECALPF status flag is automatically set to ‘1’ when software writes to the RTC_CALR
register, indicating that the RTC_CALR register is blocked. When the new calibration settings
are taken into account, this bit returns to ‘0’. Refer to Re-calibration on-the-fly.
Bit 15 Reserved, must be kept at reset value
Bit 14 TAMP2F: RTC_TAMP2 detection flag
This flag is set by hardware when a tamper detection event is detected on the RTC_TAMP2
input.
It is cleared by software writing 0
Bit 13 TAMP1F: RTC_TAMP1 detection flag
This flag is set by hardware when a tamper detection event is detected on the RTC_TAMP1
input.
It is cleared by software writing 0
Bit 12 TSOVF: Time-stamp overflow flag
This flag is set by hardware when a time-stamp event occurs while TSF is already set.
This flag is cleared by software by writing 0. It is recommended to check and then clear
TSOVF only after clearing the TSF bit. Otherwise, an overflow might not be noticed if a timestamp event occurs immediately before the TSF bit is cleared.
Bit 11 TSF: Time-stamp flag
This flag is set by hardware when a time-stamp event occurs.
This flag is cleared by software by writing 0.
Bit 10 WUTF: Wakeup timer flag
This flag is set by hardware when the wakeup auto-reload counter reaches 0.
This flag is cleared by software by writing 0.
This flag must be cleared by software at least 1.5 RTCCLK periods before WUTF is set to 1
again.
Bit 9 Reserved, must be kept at reset value.

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Bit 8 ALRAF: Alarm A flag
This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the
Alarm A register (RTC_ALRMAR).
This flag is cleared by software by writing 0.
Bit 7 INIT: Initialization mode
0: Free running mode
1: Initialization mode used to program time and date register (RTC_TR and RTC_DR), and
prescaler register (RTC_PRER). Counters are stopped and start counting from the new
value when INIT is reset.
Bit 6 INITF: Initialization flag
When this bit is set to 1, the RTC is in initialization state, and the time, date and prescaler
registers can be updated.
0: Calendar registers update is not allowed
1: Calendar registers update is allowed
Bit 5 RSF: Registers synchronization flag
This bit is set by hardware each time the calendar registers are copied into the shadow
registers (RTC_SSRx, RTC_TRx and RTC_DRx). This bit is cleared by hardware in
initialization mode, while a shift operation is pending (SHPF=1), or when in bypass shadow
register mode (BYPSHAD=1). This bit can also be cleared by software.
It is cleared either by software or by hardware in initialization mode.
0: Calendar shadow registers not yet synchronized
1: Calendar shadow registers synchronized
Bit 4 INITS: Initialization status flag
This bit is set by hardware when the calendar year field is different from 0 (RTC domain reset
state).
0: Calendar has not been initialized
1: Calendar has been initialized
Bit 3 SHPF: Shift operation pending
0: No shift operation is pending
1: A shift operation is pending
This flag is set by hardware as soon as a shift operation is initiated by a write to the
RTC_SHIFTR register. It is cleared by hardware when the corresponding shift operation has
been executed. Writing to the SHPF bit has no effect.
Bit 2 WUTWF: Wakeup timer write flag
This bit is set by hardware up to 2 RTCCLK cycles after the WUTE bit has been set to 0 in
RTC_CR, and is cleared up to 2 RTCCLK cycles after the WUTE bit has been set to 1. The
wakeup timer values can be changed when WUTE bit is cleared and WUTWF is set.
0: Wakeup timer configuration update not allowed
1: Wakeup timer configuration update allowed
Bit 1 Reserved, must be kept at reset value.
Bit 0 ALRAWF: Alarm A write flag
This bit is set by hardware when Alarm A values can be changed, after the ALRAE bit has
been set to 0 in RTC_CR.
It is cleared by hardware in initialization mode.
0: Alarm A update not allowed
1: Alarm A update allowed

Note:

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Real-time clock (RTC)

21.7.5

RTC prescaler register (RTC_PRER)
This register must be written in initialization mode only. The initialization must be performed
in two separate write accesses. Refer to Calendar initialization and configuration on
page 494.
This register is write protected. The write access procedure is described in RTC register
write protection on page 494.
Address offset: 0x10
RTC domain reset value: 0x007F 00FF
System reset: not affected

31

30

29

28

27

26

25

24

23

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

15

14

13

12

11

10

9

8

7

rw

rw

rw

rw

rw

rw

rw

Res.

22

21

20

19

18

17

16

PREDIV_A[6:0]
rw

rw

rw

rw

rw

rw

rw

6

5

4

3

2

1

0

rw

rw

rw

rw

rw

rw

rw

PREDIV_S[14:0]
rw

Bits 31:23 Reserved, must be kept at reset value
Bits 22:16 PREDIV_A[6:0]: Asynchronous prescaler factor
This is the asynchronous division factor: 
ck_apre frequency = RTCCLK frequency/(PREDIV_A+1)
Bit 15 Reserved, must be kept at reset value.
Bits 14:0 PREDIV_S[14:0]: Synchronous prescaler factor
This is the synchronous division factor:
ck_spre frequency = ck_apre frequency/(PREDIV_S+1)

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RM0360

RTC wakeup timer register (RTC_WUTR)
This register can be written only when WUTWF is set to 1 in RTC_ISR.
This register is write protected. The write access procedure is described in RTC register
write protection on page 494.
Address offset: 0x14
RTC domain reset value: 0x0000 FFFF
System reset: not affected

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

WUT[15:0]
rw

Bits 31:16 Reserved, must be kept at reset value
Bits 15:0 WUT[15:0]: Wakeup auto-reload value bits
When the wakeup timer is enabled (WUTE set to 1), the WUTF flag is set every (WUT[15:0]
+ 1) ck_wut cycles. The ck_wut period is selected through WUCKSEL[2:0] bits of the
RTC_CR register
When WUCKSEL[2] = 1, the wakeup timer becomes 17-bits and WUCKSEL[1] effectively
becomes WUT[16] the most-significant bit to be reloaded into the timer.
The first assertion of WUTF occurs (WUT+1) ck_wut cycles after WUTE is set. Setting
WUT[15:0] to 0x0000 with WUCKSEL[2:0] =011 (RTCCLK/2) is forbidden.

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21.7.7

RTC alarm A register (RTC_ALRMAR)
This register can be written only when ALRAWF is set to 1 in RTC_ISR, or in initialization
mode.
This register is write protected. The write access procedure is described in RTC register
write protection on page 494.
Address offset: 0x1C
RTC domain reset value: 0x0000 0000
System reset: not affected

31

30

MSK4

WDSEL

29

28

27

DT[1:0]

26

25

24

DU[3:0]

23

22

MSK3

PM

21

20

19

18

HT[1:0]

17

16

HU[3:0]

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

rw

rw

MSK2
rw

MNT[2:0]
rw

rw

MNU[3:0]
rw

rw

rw

MSK1

rw

rw

rw

ST[2:0]
rw

rw

SU[3:0]
rw

rw

rw

Bit 31 MSK4: Alarm A date mask
0: Alarm A set if the date/day match
1: Date/day don’t care in Alarm A comparison
Bit 30 WDSEL: Week day selection
0: DU[3:0] represents the date units
1: DU[3:0] represents the week day. DT[1:0] is don’t care.
Bits 29:28 DT[1:0]: Date tens in BCD format.
Bits 27:24 DU[3:0]: Date units or day in BCD format.
Bit 23 MSK3: Alarm A hours mask
0: Alarm A set if the hours match
1: Hours don’t care in Alarm A comparison
Bit 22 PM: AM/PM notation
0: AM or 24-hour format
1: PM
Bits 21:20 HT[1:0]: Hour tens in BCD format.
Bits 19:16 HU[3:0]: Hour units in BCD format.
Bit 15 MSK2: Alarm A minutes mask
0: Alarm A set if the minutes match
1: Minutes don’t care in Alarm A comparison
Bits 14:12 MNT[2:0]: Minute tens in BCD format.
Bits 11:8 MNU[3:0]: Minute units in BCD format.
Bit 7 MSK1: Alarm A seconds mask
0: Alarm A set if the seconds match
1: Seconds don’t care in Alarm A comparison
Bits 6:4 ST[2:0]: Second tens in BCD format.
Bits 3:0 SU[3:0]: Second units in BCD format.

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525

Real-time clock (RTC)

21.7.8

RM0360

RTC write protection register (RTC_WPR)
Address offset: 0x24
Reset value: 0x0000 0000

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

7

6

5

4

3

2

1

0

w

w

w

w

15

14

13

12

11

10

9

8

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

KEY
w

w

w

w

Bits 31:8 Reserved, must be kept at reset value.
Bits 7:0 KEY: Write protection key
This byte is written by software.
Reading this byte always returns 0x00.
Refer to RTC register write protection for a description of how to unlock RTC register write
protection.

21.7.9

RTC sub second register (RTC_SSR)
Address offset: 0x28
RTC domain reset value: 0x0000 0000
System reset: 0x0000 0000 when BYPSHAD = 0. Not affected when BYPSHAD = 1.

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

r

r

r

r

r

r

r

SS[15:0]
r

r

r

r

r

r

r

r

r

Bits31:16 Reserved, must be kept at reset value
Bits 15:0 SS: Sub second value
SS[15:0] is the value in the synchronous prescaler counter. The fraction of a second is given by
the formula below:
Second fraction = (PREDIV_S - SS) / (PREDIV_S + 1)
Note: SS can be larger than PREDIV_S only after a shift operation. In that case, the correct
time/date is one second less than as indicated by RTC_TR/RTC_DR.

514/779

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RM0360

Real-time clock (RTC)

21.7.10

RTC shift control register (RTC_SHIFTR)
This register is write protected. The write access procedure is described in RTC register
write protection on page 494.
Address offset: 0x2C
RTC domain reset value: 0x0000 0000
System reset: not affected

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

ADD1S

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

w

w

w

w

w

w

w

w
15
Res.

SUBFS[14:0]
w

w

w

w

w

w

w

w

Bit 31 ADD1S: Add one second
0: No effect
1: Add one second to the clock/calendar
This bit is write only and is always read as zero. Writing to this bit has no effect when a shift
operation is pending (when SHPF=1, in RTC_ISR).
This function is intended to be used with SUBFS (see description below) in order to effectively
add a fraction of a second to the clock in an atomic operation.
Bits 30:15 Reserved, must be kept at reset value
Bits 14:0 SUBFS: Subtract a fraction of a second
These bits are write only and is always read as zero. Writing to this bit has no effect when a
shift operation is pending (when SHPF=1, in RTC_ISR).
The value which is written to SUBFS is added to the synchronous prescaler counter. Since this
counter counts down, this operation effectively subtracts from (delays) the clock by:
Delay (seconds) = SUBFS / (PREDIV_S + 1)
A fraction of a second can effectively be added to the clock (advancing the clock) when the
ADD1S function is used in conjunction with SUBFS, effectively advancing the clock by:
Advance (seconds) = (1 - (SUBFS / (PREDIV_S + 1))).
Note: Writing to SUBFS causes RSF to be cleared. Software can then wait until RSF=1 to be
sure that the shadow registers have been updated with the shifted time.

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Real-time clock (RTC)

21.7.11

RM0360

RTC timestamp time register (RTC_TSTR)
The content of this register is valid only when TSF is set to 1 in RTC_ISR. It is cleared when
TSF bit is reset.
Address offset: 0x30
RTC domain reset value: 0x0000 0000
System reset: not affected

31

30

29

28

27

26

25

24

23

22

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

PM
r

15

14

Res.

13

12

11

MNT[2:0]
r

r

10

9

8

MNU[3:0]
r

r

r

7

r

r

Bits 31:23 Reserved, must be kept at reset value
Bit 22 PM: AM/PM notation
0: AM or 24-hour format
1: PM
Bits 21:20 HT[1:0]: Hour tens in BCD format.
Bits 19:16 HU[3:0]: Hour units in BCD format.
Bit 15 Reserved, must be kept at reset value
Bits 14:12 MNT[2:0]: Minute tens in BCD format.
Bits 11:8 MNU[3:0]: Minute units in BCD format.
Bit 7 Reserved, must be kept at reset value
Bits 6:4 ST[2:0]: Second tens in BCD format.
Bits 3:0 SU[3:0]: Second units in BCD format.

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6

Res.

DocID025023 Rev 4

21

20

19

18

HT[1:0]
r

r

r

r

5

4

3

2

ST[2:0]
r

r

17

16

HU[3:0]
r

r

1

0

r

r

SU[3:0]
r

r

r

RM0360

Real-time clock (RTC)

21.7.12

RTC timestamp date register (RTC_TSDR)
The content of this register is valid only when TSF is set to 1 in RTC_ISR. It is cleared when
TSF bit is reset.
Address offset: 0x34
RTC domain reset value: 0x0000 0000
System reset: not affected

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Res.

Res.

r

r

15

WDU[1:0]
r

r

MT
r

r

MU[3:0]
r

r

r

r

DT[1:0]
r

DU[3:0]
r

r

r

Bits 31:16 Reserved, must be kept at reset value
Bits 15:13 WDU[1:0]: Week day units
Bit 12 MT: Month tens in BCD format
Bits 11:8 MU[3:0]: Month units in BCD format
Bits 7:6 Reserved, must be kept at reset value
Bits 5:4 DT[1:0]: Date tens in BCD format
Bits 3:0 DU[3:0]: Date units in BCD format

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Real-time clock (RTC)

21.7.13

RM0360

RTC time-stamp sub second register (RTC_TSSSR)
The content of this register is valid only when RTC_ISR/TSF is set. It is cleared when the
RTC_ISR/TSF bit is reset.
Address offset: 0x38
RTC domain reset value: 0x0000 0000
System reset: not affected

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

r

r

r

r

r

r

r

SS[15:0]
r

r

r

r

r

r

r

r

r

Bits 31:16 Reserved, must be kept at reset value
Bits 15:0 SS: Sub second value
SS[15:0] is the value of the synchronous prescaler counter when the timestamp event
occurred.

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RM0360

Real-time clock (RTC)

21.7.14

RTC calibration register (RTC_CALR)
This register is write protected. The write access procedure is described in RTC register
write protection on page 494.
Address offset: 0x3C
RTC domain reset value: 0x0000 0000
System reset: not affected

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

CALP

CALW8

CALW
16

Res.

Res.

Res.

Res.

rw

rw

rw

rw

rw

rw

rw

CALM[8:0]
rw

rw

rw

rw

rw

Bits 31:16 Reserved, must be kept at reset value
Bit 15 CALP: Increase frequency of RTC by 488.5 ppm
0: No RTCCLK pulses are added.
1: One RTCCLK pulse is effectively inserted every 211 pulses (frequency increased by
488.5 ppm).
This feature is intended to be used in conjunction with CALM, which lowers the frequency of
the calendar with a fine resolution. if the input frequency is 32768 Hz, the number of RTCCLK
pulses added during a 32-second window is calculated as follows: (512 * CALP) - CALM.
Refer to Section 21.4.12: RTC smooth digital calibration.
Bit 14 CALW8: Use an 8-second calibration cycle period
When CALW8 is set to ‘1’, the 8-second calibration cycle period is selected.
Note: CALM[1:0] are stuck at “00” when CALW8=’1’. Refer to Section 21.4.12: RTC smooth
digital calibration.
Bit 13 CALW16: Use a 16-second calibration cycle period
When CALW16 is set to ‘1’, the 16-second calibration cycle period is selected.This bit must
not be set to ‘1’ if CALW8=1.
Note: CALM[0] is stuck at ‘0’ when CALW16=’1’. Refer to Section 21.4.12: RTC smooth
digital calibration.
Bits 12:9 Reserved, must be kept at reset value
Bits 8:0 CALM[8:0]: Calibration minus
The frequency of the calendar is reduced by masking CALM out of 220 RTCCLK pulses (32
seconds if the input frequency is 32768 Hz). This decreases the frequency of the calendar
with a resolution of 0.9537 ppm.
To increase the frequency of the calendar, this feature should be used in conjunction with
CALP. See Section 21.4.12: RTC smooth digital calibration on page 498.

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Real-time clock (RTC)

21.7.15

RM0360

RTC tamper and alternate function configuration register
(RTC_TAFCR)
Address offset: 0x40
RTC domain reset value: 0x0000 0000
System reset: not affected

31

30

29

28

27

26

25

24

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

15

14

13

12

11

10

9

8

TAMPP
UDIS
rw

TAMPPRCH
[1:0]
rw

rw

TAMPFLT[1:0]
rw

rw

TAMPFREQ[2:0]
rw

rw

rw

23

22

21

20

19

PC15 PC15 PC14 PC14 PC13
MODE VALUE MODE VALUE MODE

18

17

16

PC13
VALUE

Res.

Res.

1

0

rw

rw

rw

rw

rw

rw

7

6

5

4

3

2

TAMPT
S

Res.

rw

Res.

TAMP2 TAMP2
TRG
E
rw

rw

TAMPIE
rw

TAMP1 TAMP1
TRG
E
rw

rw

Bits 31:24 Reserved, must be kept at reset value.
Bit 23 PC15MODE: PC15 mode
0: PC15 is controlled by the GPIO configuration registers. Consequently PC15 is floating in
Standby mode.
1: PC15 is forced to push-pull output if LSE is disabled.
Bit 22 PC15VALUE: PC15 value
If the LSE is disabled and PC15MODE = 1, PC15VALUE configures the PC15 output data.
Bit 21 PC14MODE: PC14 mode
0: PC14 is controlled by the GPIO configuration registers. Consequently PC14 is floating in
Standby mode.
1: PC14 is forced to push-pull output if LSE is disabled.
Bit 20 PC14VALUE: PC14 value
If the LSE is disabled and PC14MODE = 1, PC14VALUE configures the PC14 output data.
Bit 19 PC13MODE: PC13 mode
0: PC13 is controlled by the GPIO configuration registers. Consequently PC13 is floating in
Standby mode.
1: PC13 is forced to push-pull output if all RTC alternate functions are disabled.
Bit 18 PC13VALUE: RTC_ALARM output type/PC13 value
If PC13 is used to output RTC_ALARM, PC13VALUE configures the output configuration:
0: RTC_ALARM is an open-drain output
1: RTC_ALARM is a push-pull output
If all RTC alternate functions are disabled and PC13MODE = 1, PC13VALUE configures the
PC13 output data.
Bits 17:16 Reserved, must be kept at reset value.
Bit 15 TAMPPUDIS: RTC_TAMPx pull-up disable
This bit determines if each of the RTC_TAMPx pins are pre-charged before each sample.
0: Precharge RTC_TAMPx pins before sampling (enable internal pull-up)
1: Disable precharge of RTC_TAMPx pins.

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RM0360

Real-time clock (RTC)

Bits 14:13 TAMPPRCH[1:0]: RTC_TAMPx precharge duration
These bit determines the duration of time during which the pull-up/is activated before each
sample. TAMPPRCH is valid for each of the RTC_TAMPx inputs.
0x0: 1 RTCCLK cycle
0x1: 2 RTCCLK cycles
0x2: 4 RTCCLK cycles
0x3: 8 RTCCLK cycles
Bits 12:11 TAMPFLT[1:0]: RTC_TAMPx filter count
These bits determines the number of consecutive samples at the specified level (TAMP*TRG)
needed to activate a Tamper event. TAMPFLT is valid for each of the RTC_TAMPx inputs.
0x0: Tamper event is activated on edge of RTC_TAMPx input transitions to the active level
(no internal pull-up on RTC_TAMPx input).
0x1: Tamper event is activated after 2 consecutive samples at the active level.
0x2: Tamper event is activated after 4 consecutive samples at the active level.
0x3: Tamper event is activated after 8 consecutive samples at the active level.
Bits 10:8 TAMPFREQ[2:0]: Tamper sampling frequency
Determines the frequency at which each of the RTC_TAMPx inputs are sampled.
0x0: RTCCLK / 32768 (1 Hz when RTCCLK = 32768 Hz)
0x1: RTCCLK / 16384 (2 Hz when RTCCLK = 32768 Hz)
0x2: RTCCLK / 8192 (4 Hz when RTCCLK = 32768 Hz)
0x3: RTCCLK / 4096 (8 Hz when RTCCLK = 32768 Hz)
0x4: RTCCLK / 2048 (16 Hz when RTCCLK = 32768 Hz)
0x5: RTCCLK / 1024 (32 Hz when RTCCLK = 32768 Hz)
0x6: RTCCLK / 512 (64 Hz when RTCCLK = 32768 Hz)
0x7: RTCCLK / 256 (128 Hz when RTCCLK = 32768 Hz)
Bit 7 TAMPTS: Activate timestamp on tamper detection event
0: Tamper detection event does not cause a timestamp to be saved
1: Save timestamp on tamper detection event
TAMPTS is valid even if TSE=0 in the RTC_CR register.
Bits 6:5 Reserved, must be kept at reset value.
Bit 4 TAMP2TRG: Active level for RTC_TAMP2 input
if TAMPFLT != 00:
0: RTC_TAMP2 input staying low triggers a tamper detection event.
1: RTC_TAMP2 input staying high triggers a tamper detection event.
if TAMPFLT = 00:
0: RTC_TAMP2 input rising edge triggers a tamper detection event.
1: RTC_TAMP2 input falling edge triggers a tamper detection event.
Bit 3 TAMP2E: RTC_TAMP2 input detection enable
0: RTC_TAMP2 detection disabled
1: RTC_TAMP2 detection enabled

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Real-time clock (RTC)

RM0360

Bit 2 TAMPIE: Tamper interrupt enable
0: Tamper interrupt disabled
1: Tamper interrupt enabled.
Bit 1 TAMP1TRG: Active level for RTC_TAMP1 input
If TAMPFLT != 00
0: RTC_TAMP1 input staying low triggers a tamper detection event.
1: RTC_TAMP1 input staying high triggers a tamper detection event.
if TAMPFLT = 00:
0: RTC_TAMP1 input rising edge triggers a tamper detection event.
1: RTC_TAMP1 input falling edge triggers a tamper detection event.
Bit 0 TAMP1E: RTC_TAMP1 input detection enable
0: RTC_TAMP1 detection disabled
1: RTC_TAMP1 detection enabled

Caution:

522/779

When TAMPFLT = 0, TAMPxE must be reset when TAMPxTRG is changed to avoid
spuriously setting TAMPxF.

DocID025023 Rev 4

RM0360

Real-time clock (RTC)

21.7.16

RTC alarm A sub second register (RTC_ALRMASSR)
This register can be written only when ALRAE is reset in RTC_CR register, or in initialization
mode.
This register is write protected. The write access procedure is described in RTC register
write protection on page 494
Address offset: 0x44
RTC domain reset value: 0x0000 0000
System reset: not affected

31

30

29

28

Res.

Res.

Res.

Res.

27

26

25

24

rw

rw

rw

rw

15

14

13

12

11

10

9

8

rw

rw

rw

rw

rw

rw

rw

MASKSS[3:0]

Res.

23

22

21

20

19

18

17

16

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

7

6

5

4

3

2

1

0

rw

rw

rw

rw

w

rw

rw

SS[14:0]
rw

Bits 31:28 Reserved, must be kept at reset value.
Bits 27:24 MASKSS[3:0]: Mask the most-significant bits starting at this bit
0: No comparison on sub seconds for Alarm A. The alarm is set when the seconds unit is
incremented (assuming that the rest of the fields match).
1: SS[14:1] are don’t care in Alarm A comparison. Only SS[0] is compared.
2: SS[14:2] are don’t care in Alarm A comparison. Only SS[1:0] are compared.
3: SS[14:3] are don’t care in Alarm A comparison. Only SS[2:0] are compared.
...
12: SS[14:12] are don’t care in Alarm A comparison. SS[11:0] are compared.
13: SS[14:13] are don’t care in Alarm A comparison. SS[12:0] are compared.
14: SS[14] is don’t care in Alarm A comparison. SS[13:0] are compared.
15: All 15 SS bits are compared and must match to activate alarm.
The overflow bits of the synchronous counter (bits 15) is never compared. This bit can be
different from 0 only after a shift operation.
Bits23:15 Reserved, must be kept at reset value.
Bits 14:0 SS[14:0]: Sub seconds value
This value is compared with the contents of the synchronous prescaler counter to determine if
Alarm A is to be activated. Only bits 0 up MASKSS-1 are compared.

21.7.17

RTC register map

Reset value

0

YT[3:0]
0

0

0

0

0

0

YU[3:0]
0

0

0

0

0

DocID025023 Rev 4

0

0

0

WDU[2:0]
0

0

1

0

Res.

MNT[2:0]

MNU[3:0]
0

0

0

0

MU[3:0]
0

0

0

1

ST[2:0]
0
Res.

0

HU[3:0]

Res.

0

Res.

HT
[1:0]

MT

Res.

Res.

Res.

Res.

Res.

Res.

RTC_DR

Res.

0x04

0
Res.

Reset value

PM

Res.

Res.

Res.

Res.

Res.

Res.

Res.

RTC_TR

Res.

0x00

Register

Res.

Offset

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0

Table 68. RTC register map and reset values

0

0

SU[3:0]
0

DT
[1:0]
0

0

0

0

0

DU[3:0]
0

0

0

1

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0x40

524/779

RTC_TAFCR

Res.

Res.

PC13VALUE

PC13VALUE

0

0

0

0

0

Reset value

Reset value

DocID025023 Rev 4

0

0

Res.
Res.

PREDIV_A[6:0]
0
0

1
1

0
0

0
0

0
0

WDU[1:0]

0
0

0

0

0

0

1

MNT[2:0]

0

0

0

0

0

0

1
1

0
0

0
0

0

0
0

0

0

0

1

MNU[3:0]

0

0

0

0

0
0
0
0
0
0
0

0

0

0

0

MSK1

.TAMP2F

TSF
WUTF
ALRAF
0

Reset value

0

0

MNU[3:0]

MU[3:0]

0

0

0

0
0
0
0
1

1
1
1
1
1
1

1
1
1
1
1
1

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

FMT
BYPSHAD
REFCKON
TSEDGE

Res.

0
0
0
0

1

1
ST[2:0]

0

0

0

0

0

0

0

0

0

0

ST[2:0]

DT
[1:0]
0
0

0
0

Res.

WUT WF

0

1

0
ALRAWF

INITS

1

SHPF

WUT[15:0]

RSF

0

INIT

PREDIV_S[14:0]

INITF

ALRAE

Res.

TSE
WUTE

TSOVF

0

Res.

ALRAIE

TAMP1F

0

TAMP1E

RTC_WPR
Res.

Res.

Res.

TSIE
WUTIE

RECALPF

0

TAMP1TRG

0

0

TAMPIE

0

0

TAMP2E

0

0

TAMP2TRG

0

Res.

1

0

Res.

0

Res.

ADD1H

Res.

0

Res.

0

Res.

Res.

BKP
SUB1H

Res.

0

0

Res.

0

Res.

Res.

POL
COSEL

0

Res.

0

MSK2

Res.

Res.

Res.

0

Res.

0

Res.

Res.

Res.

0

TAMPTS

Reset value

Res.

0

Res.

Res.

Res.

COE

Res.

Res.

Res.

Res.

Res.

0

TAMPFREQ[2:0]

Reset value

Res.

0

HU[3:0]

Res.

0

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

0

TAMPFLT[1:0]

0

Res.

Reset value
0

MNT[2:0]

0

Res.

1

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

0

MT

Res.

0

Res.

1

Res.

Res.

0

Res.

1

Res.

HU[3:0]
Res.

0

Res.

Res.

1

CALW16

Res.

0

Res.

Res.

1

TAMPPRCH[1:0]

Res.

0

Res.

Res.

1

CALW8

Res.

Res.

Res.

0

Res.

Res.

1

CALP

0

Res.

Res.

Res.

0

Res.

Res.

Res.

Res.

Reset value

TAMPPUDIS

Res.

Res.
0

Res.

Res.

0

Res.

0
HT
[1:0]

Res.

0
Res.

Res.

PM

0

Res.

Res.

Res.

0

Res.

Res.

Res.

Res.

MSK3

0

Res.

Res.

Res.

0

Res.

HT[1:0]

Res.

Res.

Res.

Res.

Res.

Res.

0

Res.

Res.

Res.

0

Res.

Res.

PM

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

0

Res.

Res.

Res.

Res.
0

Res.

Res.

Res.
0

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

0

Res.

OSE
L
[1:0]

Res.

PC14MODE

0

Res.

Reset value

PC15MODE

Res.

Res.

Res.

Res.

Res.

Res.

Res.

0

Res.

Reset value

PC14VALUE

Res.

Res.

Res.

Res.

Res.

Res.

Res.

MSK4
WDSEL

Reset value
DU[3:0]

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Reset value

PC15MODE

Reset value
Res.

RTC_ALRMAR
DT
[1:0]

Res.

RTC_ CALR

Res.

RTC_TSSSR

Res.

RTC_TSDR
Res.

RTC_TSTR

Res.

0x3C
0

Res.

0x38
Reset value

Res.

0x34
RTC_SSR

Res.

0x30
RTC_SHIFTR
ADD1S

0x2C

Res.

0x28

Res.

0x24

Res.

0x1C
RTC_WUTR

Res.

0x14
RTC_PRER

Res.

0x10
RTC_ISR

Res.

0x0C
RTC_CR

Res.

0x08

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0

Register

Res.

Offset

Res.

Real-time clock (RTC)
RM0360

Table 68. RTC register map and reset values (continued)

WUCKS
EL[2:0]

1

SU[3:0]
0
0
0

KEY

SS[15:0]

SUBFS[14:0]

0
0
0
0
0
0
0

0
0
0
0
0
0
0

0
0
0
0
0
0

SU[3:0]
0
0

DU[3:0]

SS[15:0]
0
0
0
0
0
0

0
0
0
0
0
0

CALM[8:0]

RM0360

Real-time clock (RTC)

Reset value

0

0

0

0

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

MASKSS
[3:0]

Res.

RTC_
ALRMASSR

Res.

0x44

Res.

Register

Res.

Offset

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0

Table 68. RTC register map and reset values (continued)

SS[14:0]
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Refer to Section 2.2.2 on page 37 for the register boundary addresses.

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Inter-integrated circuit (I2C) interface

RM0360

22

Inter-integrated circuit (I2C) interface

22.1

Introduction
The I2C (inter-integrated circuit) bus interface handles communications between the
microcontroller and the serial I2C bus. It provides multimaster capability, and controls all I2C
bus-specific sequencing, protocol, arbitration and timing. It supports Standard-mode (Sm),
Fast-mode (Fm) and Fast-mode Plus (Fm+).
It is also SMBus (system management bus) and PMBus (power management bus)
compatible.
DMA can be used to reduce CPU overload.

22.2

I2C main features


I2C bus specification rev03 compatibility:
–

Slave and master modes

–

Multimaster capability

–

Standard-mode (up to 100 kHz)

–

Fast-mode (up to 400 kHz)

–

Fast-mode Plus (up to 1 MHz)

–

7-bit and 10-bit addressing mode

–

Multiple 7-bit slave addresses (2 addresses, 1 with configurable mask)

–

All 7-bit addresses acknowledge mode

–

General call

–

Programmable setup and hold times

–

Easy to use event management

–

Optional clock stretching

–

Software reset



1-byte buffer with DMA capability



Programmable analog and digital noise filters

The following additional features are also available depending on the product
implementation (see Section 22.3: I2C implementation):


526/779

SMBus specification rev 2.0 compatibility:
–

Hardware PEC (Packet Error Checking) generation and verification with ACK
control

–

Command and data acknowledge control

–

Address resolution protocol (ARP) support

–

Host and Device support

–

SMBus alert

–

Timeouts and idle condition detection



PMBus rev 1.1 standard compatibility



Independent clock: a choice of independent clock sources allowing the I2C
communication speed to be independent from the PCLK reprogramming
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RM0360

22.3

Inter-integrated circuit (I2C) interface

I2C implementation
This manual describes the full set of features implemented in I2C1 I2C2 supports a smaller
set of features, but is otherwise identical to I2C1. The differences are listed below.
Table 69. STM32F0x0 I2C implementation

(1)

I2C features

STM32F030x4,
STM32F030x6,
STM32F070x6

STM32F030x8

STM32F070xB
STM32F030xC

I2C1

I2C1

I2C2

I2C1

I2C2

7-bit addressing mode

X

X

X

X

X

10-bit addressing mode

X

X

X

X

X

Standard mode (up to 100 kbit/s)

X

X

X

X

X

Fast mode (up to 400 kbit/s)

X

X

X

X

X

Independent clock

X

X

-

X

-

SMBus

X

X

-

X

-

Wakeup from Stop mode

-

-

-

-

-

Fast Mode Plus with extra output
drive I/Os (up to 1 Mbit/s)

X

X

-

X

-

1. X = supported.

22.4

I2C functional description
In addition to receiving and transmitting data, this interface converts it from serial to parallel
format and vice versa. The interrupts are enabled or disabled by software. The interface is
connected to the I2C bus by a data pin (SDA) and by a clock pin (SCL). It can be connected
with a standard (up to 100 kHz), Fast-mode (up to 400 kHz) or Fast-mode Plus (up to
1 MHz) I2C bus.
This interface can also be connected to a SMBus with the data pin (SDA) and clock pin
(SCL).
If SMBus feature is supported: the additional optional SMBus Alert pin (SMBA) is also
available.

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22.4.1

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I2C block diagram
The block diagram of the I2C interface is shown in Figure 194.
Figure 194. I2C block diagram

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The I2C is clocked by an independent clock source which allows to the I2C to operate
independently from the PCLK frequency.
This independent clock source can be selected for either of the following clock sources:


SYSCLK: system clock

Refer to for more details.
I2C I/Os support 20 mA output current drive for Fast-mode Plus operation. This is enabled
by setting the driving capability control bits for SCL and SDA in

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22.4.2

Inter-integrated circuit (I2C) interface

I2C2 block diagram
The block diagram of the I2C2 interface is shown in Figure 195.
Figure 195. I2C2 block diagram

22.4.3

I2C clock requirements
The I2C kernel is clocked by I2CCLK.
The I2CCLK period tI2CCLK must respect the following conditions:
tI2CCLK < (tLOW - tfilters ) / 4 and tI2CCLK < tHIGH
with:
tLOW: SCL low time and tHIGH : SCL high time
tfilters: when enabled, sum of the delays brought by the analog filter and by the digital filter.
Analog filter delay is maximum 260 ns. Digital filter delay is DNF x tI2CCLK.
The PCLK clock period tPCLK must respect the following condition:
tPCLK < 4/3 tSCL
with tSCL: SCL period

Caution:

When the I2C kernel is clocked by PCLK. PCLK must respect the conditions for tI2CCLK.

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22.4.4

RM0360

Mode selection
The interface can operate in one of the four following modes:


Slave transmitter



Slave receiver



Master transmitter



Master receiver

By default, it operates in slave mode. The interface automatically switches from slave to
master when it generates a START condition, and from master to slave if an arbitration loss
or a STOP generation occurs, allowing multimaster capability.

Communication flow
In Master mode, the I2C interface initiates a data transfer and generates the clock signal. A
serial data transfer always begins with a START condition and ends with a STOP condition.
Both START and STOP conditions are generated in master mode by software.
In Slave mode, the interface is capable of recognizing its own addresses (7 or 10-bit), and
the General Call address. The General Call address detection can be enabled or disabled
by software. The reserved SMBus addresses can also be enabled by software.
Data and addresses are transferred as 8-bit bytes, MSB first. The first byte(s) following the
START condition contain the address (one in 7-bit mode, two in 10-bit mode). The address
is always transmitted in Master mode.
A 9th clock pulse follows the 8 clock cycles of a byte transfer, during which the receiver must
send an acknowledge bit to the transmitter. Refer to the following figure.
Figure 196. I2C bus protocol

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Acknowledge can be enabled or disabled by software. The I2C interface addresses can be
selected by software.

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RM0360

22.4.5

Inter-integrated circuit (I2C) interface

I2C initialization
Enabling and disabling the peripheral
The I2C peripheral clock must be configured and enabled in the clock controller (refer to ).
Then the I2C can be enabled by setting the PE bit in the I2C_CR1 register.
When the I2C is disabled (PE=0), the I2C performs a software reset. Refer to
Section 22.4.6: Software reset for more details.

Noise filters
Before enabling the I2C peripheral by setting the PE bit in I2C_CR1 register, the user must
configure the noise filters, if needed. By default, an analog noise filter is present on the SDA
and SCL inputs. This analog filter is compliant with the I2C specification which requires the
suppression of spikes with a pulse width up to 50 ns in Fast-mode and Fast-mode Plus. The
user can disable this analog filter by setting the ANFOFF bit, and/or select a digital filter by
configuring the DNF[3:0] bit in the I2C_CR1 register.
When the digital filter is enabled, the level of the SCL or the SDA line is internally changed
only if it remains stable for more than DNF x I2CCLK periods. This allows to suppress
spikes with a programmable length of 1 to 15 I2CCLK periods.
Table 70. Comparison of analog vs. digital filters

Pulse width of
suppressed spikes

Caution:

Analog filter

Digital filter

≥ 50 ns

Programmable length from 1 to 15 I2C peripheral
clocks

Changing the filter configuration is not allowed when the I2C is enabled.

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I2C timings
The timings must be configured in order to guarantee a correct data hold and setup time,
used in master and slave modes. This is done by programming the PRESC[3:0],
SCLDEL[3:0] and SDADEL[3:0] bits in the I2C_TIMINGR register.
The STM32CubeMX tool calculates and provides the I2C_TIMINGR content in the I2C
configuration window
Figure 197. Setup and hold timings
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RM0360

Inter-integrated circuit (I2C) interface


When the SCL falling edge is internally detected, a delay is inserted before sending
SDA output. This delay is tSDADEL = SDADEL x tPRESC + tI2CCLK where tPRESC = (PRESC+1)
x tI2CCLK.
TSDADEL impacts the hold time tHD;DAT.

The total SDA output delay is:
tSYNC1 + {[SDADEL x (PRESC+1) + 1] x tI2CCLK }
tSYNC1 duration depends on these parameters:

–

SCL falling slope

–

When enabled, input delay brought by the analog filter: tAF(min) < tAF < tAF(max) ns.

–

When enabled, input delay brought by the digital filter: tDNF = DNF x tI2CCLK

–

Delay due to SCL synchronization to I2CCLK clock (2 to 3 I2CCLK periods)

In order to bridge the undefined region of the SCL falling edge, the user must program
SDADEL in such a way that:
{tf (max) +tHD;DAT (min) -tAF(min) - [(DNF +3) x tI2CCLK]} / {(PRESC +1) x tI2CCLK } ≤ SDADEL
SDADEL ≤ {tHD;DAT (max) -tAF(max) - [(DNF+4) x tI2CCLK]} / {(PRESC +1) x tI2CCLK }
Note:

tAF(min) / tAF(max) are part of the equation only when the analog filter is enabled. Refer to
device datasheet for tAF values.
The maximum tHD;DAT could be 3.45 µs, 0.9 µs and 0.45 µs for Standard-mode, Fast-mode
and Fast-mode Plus, but must be less than the maximum of tVD;DAT by a transition time.
This maximum must only be met if the device does not stretch the LOW period (tLOW) of the
SCL signal. If the clock stretches the SCL, the data must be valid by the set-up time before
it releases the clock.
The SDA rising edge is usually the worst case, so in this case the previous equation
becomes:
SDADEL ≤ {tVD;DAT (max) -tr (max) -260 ns - [(DNF+4) x tI2CCLK]} / {(PRESC +1) x tI2CCLK }.

Note:

This condition can be violated when NOSTRETCH=0, because the device stretches SCL
low to guarantee the set-up time, according to the SCLDEL value.
Refer to Table 71: I2C-SMBUS specification data setup and hold times for tf, tr, tHD;DAT and
tVD;DAT standard values.


After tSDADEL delay, or after sending SDA output in case the slave had to stretch the
clock because the data was not yet written in I2C_TXDR register, SCL line is kept at
low level during the setup time. This setup time is tSCLDEL = (SCLDEL+1) x tPRESC where
tPRESC = (PRESC+1) x tI2CCLK.
tSCLDEL impacts the setup time tSU;DAT .

In order to bridge the undefined region of the SDA transition (rising edge usually worst
case), the user must program SCLDEL in such a way that:
{[tr (max) + tSU;DAT (min)] / [(PRESC+1)] x tI2CCLK]} - 1 <= SCLDEL
Refer to Table 71: I2C-SMBUS specification data setup and hold times for tr and tSU;DAT
standard values.
The SDA and SCL transition time values to be used are the ones in the application. Using
the maximum values from the standard increases the constraints for the SDADEL and
SCLDEL calculation, but ensures the feature whatever the application.

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Inter-integrated circuit (I2C) interface
Note:

RM0360

At every clock pulse, after SCL falling edge detection, the I2C master or slave stretches SCL
low during at least [(SDADEL+SCLDEL+1) x (PRESC+1) + 1] x tI2CCLK, in both transmission
and reception modes. In transmission mode, in case the data is not yet written in I2C_TXDR
when SDADEL counter is finished, the I2C keeps on stretching SCL low until the next data
is written. Then new data MSB is sent on SDA output, and SCLDEL counter starts,
continuing stretching SCL low to guarantee the data setup time.
If NOSTRETCH=1 in slave mode, the SCL is not stretched. Consequently the SDADEL
must be programmed in such a way to guarantee also a sufficient setup time.
Table 71. I2C-SMBUS specification data setup and hold times

Symbol

Parameter

Standard-mode
(Sm)

Fast-mode
(Fm)

Fast-mode Plus
(Fm+)

SMBUS
Unit

Min.

Max

Min.

Max

Min.

Max

Min.

Max

tHD;DAT

Data hold time

0

-

0

-

0

-

0.3

-

tVD;DAT

Data valid time

-

3.45

-

0.9

-

0.45

-

-

tSU;DAT

Data setup time

250

-

100

-

50

-

250

-

tr

Rise time of both SDA
and SCL signals

-

1000

-

300

-

120

-

1000

tf

Fall time of both SDA
and SCL signals

-

300

-

300

-

120

-

300

µs

ns

Additionally, in master mode, the SCL clock high and low levels must be configured by
programming the PRESC[3:0], SCLH[7:0] and SCLL[7:0] bits in the I2C_TIMINGR register.


When the SCL falling edge is internally detected, a delay is inserted before releasing
the SCL output. This delay is tSCLL = (SCLL+1) x tPRESC where tPRESC = (PRESC+1) x
tI2CCLK.
tSCLL impacts the SCL low time tLOW .



When the SCL rising edge is internally detected, a delay is inserted before forcing the
SCL output to low level. This delay is tSCLH = (SCLH+1) x tPRESC where tPRESC =
(PRESC+1) x tI2CCLK. tSCLH impacts the SCL high time tHIGH .

Refer to I2C master initialization for more details.
Caution:

Changing the timing configuration is not allowed when the I2C is enabled.
The I2C slave NOSTRETCH mode must also be configured before enabling the peripheral.
Refer to I2C slave initialization for more details.

Caution:

534/779

Changing the NOSTRETCH configuration is not allowed when the I2C is enabled.

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RM0360

Inter-integrated circuit (I2C) interface
Figure 198. I2C initialization flowchart

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22.4.6

Software reset
A software reset can be performed by clearing the PE bit in the I2C_CR1 register. In that
case I2C lines SCL and SDA are released. Internal states machines are reset and
communication control bits, as well as status bits come back to their reset value. The
configuration registers are not impacted.
Here is the list of impacted register bits:
1.

I2C_CR2 register: START, STOP, NACK

2.

I2C_ISR register: BUSY, TXE, TXIS, RXNE, ADDR, NACKF, TCR, TC, STOPF, BERR,
ARLO, OVR

and in addition when the SMBus feature is supported:
1.

I2C_CR2 register: PECBYTE

2.

I2C_ISR register: PECERR, TIMEOUT, ALERT

PE must be kept low during at least 3 APB clock cycles in order to perform the software
reset. This is ensured by writing the following software sequence: - Write PE=0 - Check
PE=0 - Write PE=1.

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Data transfer
The data transfer is managed through transmit and receive data registers and a shift
register.

Reception
The SDA input fills the shift register. After the 8th SCL pulse (when the complete data byte is
received), the shift register is copied into I2C_RXDR register if it is empty (RXNE=0). If
RXNE=1, meaning that the previous received data byte has not yet been read, the SCL line
is stretched low until I2C_RXDR is read. The stretch is inserted between the 8th and 9th
SCL pulse (before the Acknowledge pulse).
Figure 199. Data reception

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Inter-integrated circuit (I2C) interface

Transmission
If the I2C_TXDR register is not empty (TXE=0), its content is copied into the shift register
after the 9th SCL pulse (the Acknowledge pulse). Then the shift register content is shifted
out on SDA line. If TXE=1, meaning that no data is written yet in I2C_TXDR, SCL line is
stretched low until I2C_TXDR is written. The stretch is done after the 9th SCL pulse.
Figure 200. Data transmission

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Hardware transfer management
The I2C has a byte counter embedded in hardware in order to manage byte transfer and to
close the communication in various modes such as:
–

NACK, STOP and ReSTART generation in master mode

–

ACK control in slave receiver mode

–

PEC generation/checking when SMBus feature is supported

The byte counter is always used in master mode. By default it is disabled in slave mode, but
it can be enabled by software by setting the SBC (Slave Byte Control) bit in the I2C_CR2
register.
The number of bytes to be transferred is programmed in the NBYTES[7:0] bit field in the
I2C_CR2 register. If the number of bytes to be transferred (NBYTES) is greater than 255, or
if a receiver wants to control the acknowledge value of a received data byte, the reload
mode must be selected by setting the RELOAD bit in the I2C_CR2 register. In this mode,
TCR flag is set when the number of bytes programmed in NBYTES has been transferred,
and an interrupt is generated if TCIE is set. SCL is stretched as long as TCR flag is set. TCR
is cleared by software when NBYTES is written to a non-zero value.
When the NBYTES counter is reloaded with the last number of bytes, RELOAD bit must be
cleared.

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When RELOAD=0 in master mode, the counter can be used in 2 modes:

Caution:



Automatic end mode (AUTOEND = ‘1’ in the I2C_CR2 register). In this mode, the
master automatically sends a STOP condition once the number of bytes programmed
in the NBYTES[7:0] bit field has been transferred.



Software end mode (AUTOEND = ‘0’ in the I2C_CR2 register). In this mode, software
action is expected once the number of bytes programmed in the NBYTES[7:0] bit field
has been transferred; the TC flag is set and an interrupt is generated if the TCIE bit is
set. The SCL signal is stretched as long as the TC flag is set. The TC flag is cleared by
software when the START or STOP bit is set in the I2C_CR2 register. This mode must
be used when the master wants to send a RESTART condition.

The AUTOEND bit has no effect when the RELOAD bit is set.
Table 72. I2C configuration table

22.4.8

Function

SBC bit

RELOAD bit

AUTOEND bit

Master Tx/Rx NBYTES + STOP

x

0

1

Master Tx/Rx + NBYTES + RESTART

x

0

0

Slave Tx/Rx
all received bytes ACKed

0

x

x

Slave Rx with ACK control

1

1

x

I2C slave mode
I2C slave initialization
In order to work in slave mode, the user must enable at least one slave address. Two
registers I2C_OAR1 and I2C_OAR2 are available in order to program the slave own
addresses OA1 and OA2.


OA1 can be configured either in 7-bit mode (by default) or in 10-bit addressing mode by
setting the OA1MODE bit in the I2C_OAR1 register.
OA1 is enabled by setting the OA1EN bit in the I2C_OAR1 register.



If additional slave addresses are required, the 2nd slave address OA2 can be
configured. Up to 7 OA2 LSB can be masked by configuring the OA2MSK[2:0] bits in
the I2C_OAR2 register. Therefore for OA2MSK configured from 1 to 6, only OA2[7:2],
OA2[7:3], OA2[7:4], OA2[7:5], OA2[7:6] or OA2[7] are compared with the received
address. As soon as OA2MSK is not equal to 0, the address comparator for OA2
excludes the I2C reserved addresses (0000 XXX and 1111 XXX), which are not
acknowledged. If OA2MSK=7, all received 7-bit addresses are acknowledged (except
reserved addresses). OA2 is always a 7-bit address.
These reserved addresses can be acknowledged if they are enabled by the specific
enable bit, if they are programmed in the I2C_OAR1 or I2C_OAR2 register with
OA2MSK=0.
OA2 is enabled by setting the OA2EN bit in the I2C_OAR2 register.



The General Call address is enabled by setting the GCEN bit in the I2C_CR1 register.

When the I2C is selected by one of its enabled addresses, the ADDR interrupt status flag is
set, and an interrupt is generated if the ADDRIE bit is set.

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Inter-integrated circuit (I2C) interface
By default, the slave uses its clock stretching capability, which means that it stretches the
SCL signal at low level when needed, in order to perform software actions. If the master
does not support clock stretching, the I2C must be configured with NOSTRETCH=1 in the
I2C_CR1 register.
After receiving an ADDR interrupt, if several addresses are enabled the user must read the
ADDCODE[6:0] bits in the I2C_ISR register in order to check which address matched. DIR
flag must also be checked in order to know the transfer direction.

Slave clock stretching (NOSTRETCH = 0)
In default mode, the I2C slave stretches the SCL clock in the following situations:


When the ADDR flag is set: the received address matches with one of the enabled
slave addresses. This stretch is released when the ADDR flag is cleared by software
setting the ADDRCF bit.



In transmission, if the previous data transmission is completed and no new data is
written in I2C_TXDR register, or if the first data byte is not written when the ADDR flag
is cleared (TXE=1). This stretch is released when the data is written to the I2C_TXDR
register.



In reception when the I2C_RXDR register is not read yet and a new data reception is
completed. This stretch is released when I2C_RXDR is read.



When TCR = 1 in Slave Byte Control mode, reload mode (SBC=1 and RELOAD=1),
meaning that the last data byte has been transferred. This stretch is released when
then TCR is cleared by writing a non-zero value in the NBYTES[7:0] field.



After SCL falling edge detection, the I2C stretches SCL low during
[(SDADEL+SCLDEL+1) x (PRESC+1) + 1] x tI2CCLK.

Slave without clock stretching (NOSTRETCH = 1)
When NOSTRETCH = 1 in the I2C_CR1 register, the I2C slave does not stretch the SCL
signal.


The SCL clock is not stretched while the ADDR flag is set.



In transmission, the data must be written in the I2C_TXDR register before the first SCL
pulse corresponding to its transfer occurs. If not, an underrun occurs, the OVR flag is
set in the I2C_ISR register and an interrupt is generated if the ERRIE bit is set in the
I2C_CR1 register. The OVR flag is also set when the first data transmission starts and
the STOPF bit is still set (has not been cleared). Therefore, if the user clears the
STOPF flag of the previous transfer only after writing the first data to be transmitted in
the next transfer, he ensures that the OVR status is provided, even for the first data to
be transmitted.



In reception, the data must be read from the I2C_RXDR register before the 9th SCL
pulse (ACK pulse) of the next data byte occurs. If not an overrun occurs, the OVR flag
is set in the I2C_ISR register and an interrupt is generated if the ERRIE bit is set in the
I2C_CR1 register.

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RM0360

Slave Byte Control mode
In order to allow byte ACK control in slave reception mode, Slave Byte Control mode must
be enabled by setting the SBC bit in the I2C_CR1 register. This is required to be compliant
with SMBus standards.
Reload mode must be selected in order to allow byte ACK control in slave reception mode
(RELOAD=1). To get control of each byte, NBYTES must be initialized to 0x1 in the ADDR
interrupt subroutine, and reloaded to 0x1 after each received byte. When the byte is
received, the TCR bit is set, stretching the SCL signal low between the 8th and 9th SCL
pulses. The user can read the data from the I2C_RXDR register, and then decide to
acknowledge it or not by configuring the ACK bit in the I2C_CR2 register. The SCL stretch is
released by programming NBYTES to a non-zero value: the acknowledge or notacknowledge is sent and next byte can be received.
NBYTES can be loaded with a value greater than 0x1, and in this case, the reception flow is
continuous during NBYTES data reception.
Note:

The SBC bit must be configured when the I2C is disabled, or when the slave is not
addressed, or when ADDR=1.
The RELOAD bit value can be changed when ADDR=1, or when TCR=1.

Caution:

540/779

Slave Byte Control mode is not compatible with NOSTRETCH mode. Setting SBC when
NOSTRETCH=1 is not allowed.

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RM0360

Inter-integrated circuit (I2C) interface
Figure 201. Slave initialization flowchart

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For code example refer to the Appendix section A.11.3: I2C configured in slave mode code
example.

Slave transmitter
A transmit interrupt status (TXIS) is generated when the I2C_TXDR register becomes
empty. An interrupt is generated if the TXIE bit is set in the I2C_CR1 register.
The TXIS bit is cleared when the I2C_TXDR register is written with the next data byte to be
transmitted.
When a NACK is received, the NACKF bit is set in the I2C_ISR register and an interrupt is
generated if the NACKIE bit is set in the I2C_CR1 register. The slave automatically releases
the SCL and SDA lines in order to let the master perform a STOP or a RESTART condition.
The TXIS bit is not set when a NACK is received.
When a STOP is received and the STOPIE bit is set in the I2C_CR1 register, the STOPF
flag is set in the I2C_ISR register and an interrupt is generated. In most applications, the
SBC bit is usually programmed to ‘0’. In this case, If TXE = 0 when the slave address is
received (ADDR=1), the user can choose either to send the content of the I2C_TXDR
register as the first data byte, or to flush the I2C_TXDR register by setting the TXE bit in
order to program a new data byte.

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Inter-integrated circuit (I2C) interface

RM0360

In Slave Byte Control mode (SBC=1), the number of bytes to be transmitted must be
programmed in NBYTES in the address match interrupt subroutine (ADDR=1). In this case,
the number of TXIS events during the transfer corresponds to the value programmed in
NBYTES.
Caution:

When NOSTRETCH=1, the SCL clock is not stretched while the ADDR flag is set, so the
user cannot flush the I2C_TXDR register content in the ADDR subroutine, in order to
program the first data byte. The first data byte to be sent must be previously programmed in
the I2C_TXDR register:


This data can be the data written in the last TXIS event of the previous transmission
message.



If this data byte is not the one to be sent, the I2C_TXDR register can be flushed by
setting the TXE bit in order to program a new data byte. The STOPF bit must be
cleared only after these actions, in order to guarantee that they are executed before the
first data transmission starts, following the address acknowledge.
If STOPF is still set when the first data transmission starts, an underrun error will be
generated (the OVR flag is set).
If a TXIS event is needed, (Transmit Interrupt or Transmit DMA request), the user must
set the TXIS bit in addition to the TXE bit, in order to generate a TXIS event.
Figure 202. Transfer sequence flowchart for I2C slave transmitter, NOSTRETCH=0
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1. For details on coding USARTDIV in the USART_BRR register, please refer to Section 23.4.4: USART baud
rate generation.

23.4.1

USART character description
The word length can be selected as being either 8 or 9 bits by programming the M bit (M0:
bit 12) in the USART_CR1 register (see Figure 227).


8-bit character length: M0 = 0



9-bit character length: M0 = 1

By default, the signal (TX or RX) is in low state during the start bit. It is in high state during
the stop bit.
These values can be inverted, separately for each signal, through polarity configuration
control.

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RM0360

An Idle character is interpreted as an entire frame of “1”s (the number of “1”s includes the
number of stop bits).
A Break character is interpreted on receiving “0”s for a frame period. At the end of the
break frame, the transmitter inserts 2 stop bits.
Transmission and reception are driven by a common baud rate generator, the clock for each
is generated when the enable bit is set respectively for the transmitter and receiver.
The details of each block is given below.
Figure 227. Word length programming
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23.4.2

USART transmitter
The transmitter can send data words of either 8 or 9 bits depending on the M bit status. The
Transmit Enable bit (TE) must be set in order to activate the transmitter function. The data in
the transmit shift register is output on the TX pin and the corresponding clock pulses are
output on the CK pin.

Character transmission
During an USART transmission, data shifts out least significant bit first (default
configuration) on the TX pin. In this mode, the USART_TDR register consists of a buffer
(TDR) between the internal bus and the transmit shift register (see Figure 226).

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RM0360

Universal synchronous asynchronous receiver transmitter (USART)
Every character is preceded by a start bit which is a logic level low for one bit period. The
character is terminated by a configurable number of stop bits.
The following stop bits are supported by USART: 1 and 2 stop bits.

Note:

The TE bit must be set before writing the data to be transmitted to the USART_TDR.
The TE bit should not be reset during transmission of data. Resetting the TE bit during the
transmission will corrupt the data on the TX pin as the baud rate counters will get frozen.
The current data being transmitted will be lost.
An idle frame will be sent after the TE bit is enabled.
Configurable stop bits
The number of stop bits to be transmitted with every character can be programmed in
Control register 2, bits 13,12.


1 stop bit: This is the default value of number of stop bits.



2 stop bits: This will be supported by normal USART, Single-wire and Modem modes.

An idle frame transmission will include the stop bits.
A break transmission will be 10 low bits (when M0= 0) or 11 low bits (when M0= 1) followed
by 2 stop bits (see Figure 228). It is not possible to transmit long breaks (break of length
greater than 10/11 low bits).
Figure 228. Configurable stop bits
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RM0360

Character transmission procedure
1.

Program the M bit in USART_CR1 to define the word length.

2.

Select the desired baud rate using the USART_BRR register.

3.

Program the number of stop bits in USART_CR2.

4.

Enable the USART by writing the UE bit in USART_CR1 register to 1.

5.

Select DMA enable (DMAT) in USART_CR3 if multibuffer communication is to take
place. Configure the DMA register as explained in multibuffer communication.

6.

Set the TE bit in USART_CR1 to send an idle frame as first transmission.

7.

Write the data to send in the USART_TDR register (this clears the TXE bit). Repeat this
for each data to be transmitted in case of single buffer.

8.

After writing the last data into the USART_TDR register, wait until TC=1. This indicates
that the transmission of the last frame is complete. This is required for instance when
the USART is disabled or enters the Halt mode to avoid corrupting the last
transmission.

For code example refer to Appendix section A.15.1: USART transmitter configuration code
example.

Single byte communication
Clearing the TXE bit is always performed by a write to the transmit data register.
The TXE bit is set by hardware and it indicates:


The data has been moved from the USART_TDR register to the shift register and the
data transmission has started.



The USART_TDR register is empty.



The next data can be written in the USART_TDR register without overwriting the
previous data.

For code example refer to the Appendix section A.15.2: USART transmit byte code
example.
This flag generates an interrupt if the TXEIE bit is set.
When a transmission is taking place, a write instruction to the USART_TDR register stores
the data in the TDR register; next, the data is copied in the shift register at the end of the
currently ongoing transmission.
When no transmission is taking place, a write instruction to the USART_TDR register places
the data in the shift register, the data transmission starts, and the TXE bit is set.
If a frame is transmitted (after the stop bit) and the TXE bit is set, the TC bit goes high. An
interrupt is generated if the TCIE bit is set in the USART_CR1 register.
After writing the last data in the USART_TDR register, it is mandatory to wait for TC=1
before disabling the USART or causing the microcontroller to enter the low-power mode
(see Figure 229: TC/TXE behavior when transmitting).

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RM0360

Universal synchronous asynchronous receiver transmitter (USART)
Figure 229. TC/TXE behavior when transmitting
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For code example refer to the Appendix section A.15.3: USART transfer complete code
example.

Break characters
Setting the SBKRQ bit transmits a break character. The break frame length depends on the
M bit (see Figure 227).
If a ‘1’ is written to the SBKRQ bit, a break character is sent on the TX line after completing
the current character transmission. The SBKF bit is set by the write operation and it is reset
by hardware when the break character is completed (during the stop bits after the break
character). The USART inserts a logic 1 signal (STOP) for the duration of 2 bits at the end of
the break frame to guarantee the recognition of the start bit of the next frame.
In the case the application needs to send the break character following all previously
inserted data, including the ones not yet transmitted, the software should wait for the TXE
flag assertion before setting the SBKRQ bit.

Idle characters
Setting the TE bit drives the USART to send an idle frame before the first data frame.

23.4.3

USART receiver
The USART can receive data words of either 8 or 9 bits depending on the M bit in the
USART_CR1 register.

Start bit detection
The start bit detection sequence is the same when oversampling by 16 or by 8.
In the USART, the start bit is detected when a specific sequence of samples is recognized.
This sequence is: 1 1 1 0 X 0 X 0X 0X 0 X 0X 0.

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RM0360

Figure 230. Start bit detection when oversampling by 16 or 8
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If the sequence is not complete, the start bit detection aborts and the receiver returns to the
idle state (no flag is set), where it waits for a falling edge.
The start bit is confirmed (RXNE flag set, interrupt generated if RXNEIE=1) if the 3 sampled
bits are at 0 (first sampling on the 3rd, 5th and 7th bits finds the 3 bits at 0 and second
sampling on the 8th, 9th and 10th bits also finds the 3 bits at 0).
The start bit is validated (RXNE flag set, interrupt generated if RXNEIE=1) but the NF noise
flag is set if,
a)

for both samplings, 2 out of the 3 sampled bits are at 0 (sampling on the 3rd, 5th
and 7th bits and sampling on the 8th, 9th and 10th bits)

or
b)

for one of the samplings (sampling on the 3rd, 5th and 7th bits or sampling on the
8th, 9th and 10th bits), 2 out of the 3 bits are found at 0.

If neither conditions a. or b. are met, the start detection aborts and the receiver returns to the
idle state (no flag is set).

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RM0360

Universal synchronous asynchronous receiver transmitter (USART)

Character reception
During an USART reception, data shifts in least significant bit first (default configuration)
through the RX pin. In this mode, the USART_RDR register consists of a buffer (RDR)
between the internal bus and the receive shift register.
Character reception procedure
1.

Program the M bit in USART_CR1 to define the word length.

2.

Select the desired baud rate using the baud rate register USART_BRR

3.

Program the number of stop bits in USART_CR2.

4.

Enable the USART by writing the UE bit in USART_CR1 register to 1.

5.

Select DMA enable (DMAR) in USART_CR3 if multibuffer communication is to take
place. Configure the DMA register as explained in multibuffer communication.

6.

Set the RE bit USART_CR1. This enables the receiver which begins searching for a
start bit.

For code example refer to the Appendix section A.15.4: USART receiver configuration code
example.
When a character is received:


The RXNE bit is set to indicate that the content of the shift register is transferred to the
RDR. In other words, data has been received and can be read (as well as its
associated error flags).



An interrupt is generated if the RXNEIE bit is set.



The error flags can be set if a frame error, noise or an overrun error has been detected
during reception. PE flag can also be set with RXNE.



In multibuffer, RXNE is set after every byte received and is cleared by the DMA read of
the Receive data Register.



In single buffer mode, clearing the RXNE bit is performed by a software read to the
USART_RDR register. The RXNE flag can also be cleared by writing 1 to the RXFRQ
in the USART_RQR register. The RXNE bit must be cleared before the end of the
reception of the next character to avoid an overrun error.

For code example refer to the Appendix section A.15.5: USART receive byte code
example.Break character
When a break character is received, the USART handles it as a framing error.

Idle character
When an idle frame is detected, there is the same procedure as for a received data
character plus an interrupt if the IDLEIE bit is set.

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Overrun error
An overrun error occurs when a character is received when RXNE has not been reset. Data
can not be transferred from the shift register to the RDR register until the RXNE bit is
cleared.
The RXNE flag is set after every byte received. An overrun error occurs if RXNE flag is set
when the next data is received or the previous DMA request has not been serviced. When
an overrun error occurs:

Note:



The ORE bit is set.



The RDR content will not be lost. The previous data is available when a read to
USART_RDR is performed.



The shift register will be overwritten. After that point, any data received during overrun
is lost.



An interrupt is generated if either the RXNEIE bit is set or EIE bit is set.



The ORE bit is reset by setting the ORECF bit in the ICR register.

The ORE bit, when set, indicates that at least 1 data has been lost. There are two
possibilities:
- if RXNE=1, then the last valid data is stored in the receive register RDR and can be read,
- if RXNE=0, then it means that the last valid data has already been read and thus there is
nothing to be read in the RDR. This case can occur when the last valid data is read in the
RDR at the same time as the new (and lost) data is received.

Selecting the clock source and the proper oversampling method
The choice of the clock source is done through the Clock Control system (see Section Reset
and clock control (RCC))). The clock source must be chosen before enabling the USART
(by setting the UE bit).
The choice of the clock source must be done according to two criteria:


Possible use of the USART in low-power mode



Communication speed.

The clock source frequency is fCK.
The communication speed range (specially the maximum communication speed) is also
determined by the clock source.
The receiver implements different user-configurable oversampling techniques for data
recovery by discriminating between valid incoming data and noise. This allows a trade-off
between the maximum communication speed and noise/clock inaccuracy immunity.
The oversampling method can be selected by programming the OVER8 bit in the
USART_CR1 register and can be either 16 or 8 times the baud rate clock (Figure 231 and
Figure 232).
Depending on the application:

606/779



Select oversampling by 8 (OVER8=1) to achieve higher speed (up to fCK/8). In this
case the maximum receiver tolerance to clock deviation is reduced (refer to
Section 23.4.5: Tolerance of the USART receiver to clock deviation on page 611)



Select oversampling by 16 (OVER8=0) to increase the tolerance of the receiver to
clock deviations. In this case, the maximum speed is limited to maximum fCK/16 where
fCK is the clock source frequency.

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RM0360

Universal synchronous asynchronous receiver transmitter (USART)
Programming the ONEBIT bit in the USART_CR3 register selects the method used to
evaluate the logic level. There are two options:


The majority vote of the three samples in the center of the received bit. In this case,
when the 3 samples used for the majority vote are not equal, the NF bit is set



A single sample in the center of the received bit
Depending on the application:
–

select the three samples’ majority vote method (ONEBIT=0) when operating in a
noisy environment and reject the data when a noise is detected (refer to
Figure 86) because this indicates that a glitch occurred during the sampling.

–

select the single sample method (ONEBIT=1) when the line is noise-free to
increase the receiver’s tolerance to clock deviations (see Section 23.4.5:
Tolerance of the USART receiver to clock deviation on page 611). In this case the
NF bit will never be set.

When noise is detected in a frame:


The NF bit is set at the rising edge of the RXNE bit.



The invalid data is transferred from the Shift register to the USART_RDR register.



No interrupt is generated in case of single byte communication. However this bit rises
at the same time as the RXNE bit which itself generates an interrupt. In case of
multibuffer communication an interrupt will be issued if the EIE bit is set in the
USART_CR3 register.

The NF bit is reset by setting NFCF bit in ICR register.
Figure 231. Data sampling when oversampling by 16

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Figure 232. Data sampling when oversampling by 8

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Table 86. Noise detection from sampled data
Sampled value

NE status

Received bit value

000

0

0

001

1

0

010

1

0

011

1

1

100

1

0

101

1

1

110

1

1

111

0

1

Framing error
A framing error is detected when the stop bit is not recognized on reception at the expected
time, following either a de-synchronization or excessive noise.
When the framing error is detected:


The FE bit is set by hardware



The invalid data is transferred from the Shift register to the USART_RDR register.



No interrupt is generated in case of single byte communication. However this bit rises
at the same time as the RXNE bit which itself generates an interrupt. In case of
multibuffer communication an interrupt will be issued if the EIE bit is set in the
USART_CR3 register.

The FE bit is reset by writing 1 to the FECF in the USART_ICR register.

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Universal synchronous asynchronous receiver transmitter (USART)

Configurable stop bits during reception
The number of stop bits to be received can be configured through the control bits of Control
Register 2 - it can be either 1 or 2 in normal mode.

23.4.4



1 stop bit: Sampling for 1 stop Bit is done on the 8th, 9th and 10th samples.



2 stop bits: Sampling for 2 stop bits is done on the 8th, 9th and 10th samples of the
first stop bit. If a framing error is detected during the first stop bit the framing error flag
will be set. The second stop bit is not checked for framing error. The RXNE flag will be
set at the end of the first stop bit.

USART baud rate generation
The baud rate for the receiver and transmitter (Rx and Tx) are both set to the same value as
programmed in the USART_BRR register.
Equation 1: Baud rate for standard USART (SPI mode included) (OVER8 = 0 or 1)
In case of oversampling by 16, the equation is:
f CK
Tx/Rx baud = -------------------------------USARTDIV

In case of oversampling by 8, the equation is:
2  f CK
Tx/Rx baud = -------------------------------USARTDIV

USARTDIV is an unsigned fixed point number that is coded on the USART_BRR register.

Note:



When OVER8 = 0, BRR = USARTDIV.



When OVER8 = 1
–

BRR[2:0] = USARTDIV[3:0] shifted 1 bit to the right.

–

BRR[3] must be kept cleared.

–

BRR[15:4] = USARTDIV[15:4]

The baud counters are updated to the new value in the baud registers after a write operation
to USART_BRR. Hence the baud rate register value should not be changed during
communication.
In case of oversampling by 16 or 8, USARTDIV must be greater than or equal to 0d16.

How to derive USARTDIV from USART_BRR register values
Example 1
To obtain 9600 baud with fCK = 8 MHz.


In case of oversampling by 16:
USARTDIV = 8 000 000/9600
BRR = USARTDIV = 833d = 0341h



In case of oversampling by 8:
USARTDIV = 2 * 8 000 000/9600
USARTDIV = 1666,66 (1667d = 683h)
BRR[3:0] = 3h << 1 = 1h
BRR = 0x681
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Example 2
To obtain 921.6 Kbaud with fCK = 48 MHz.


In case of oversampling by 16:
USARTDIV = 48 000 000/921 600
BRR = USARTDIV = 52d = 34h



In case of oversampling by 8:
USARTDIV = 2 * 48 000 000/921 600
USARTDIV = 104 (104d = 68h)
BRR[3:0] = USARTDIV[3:0] >> 1 = 8h >> 1 = 4h
BRR = 0x64

Table 87. Error calculation for programmed baud rates at fCK = 48 MHz in both cases of
oversampling by 16 or by 8(1)
Baud rate

Oversampling by 16 (OVER8 = 0)

Oversampling by 8 (OVER8 = 1)

S.No

Desired

Actual

BRR

% Error =
(Calculated Desired)B.Rate /
Desired B.Rate

2

2.4 KBps

2.4 KBps

0x4E20

0

2.4 KBps

0x9C40

0

3

9.6 KBps

9.6 KBps

0x1388

0

9.6 KBps

0x2710

0

4

19.2 KBps

19.2 KBps

0x9C4

0

19.2 KBps

0x1384

0

5

38.4 KBps

38.4 KBps

0x4E2

0

38.4 KBps

0x9C2

0

6

57.6 KBps

57.62 KBps

0x341

0.03

57.59 KBps

0x681

0.02

7

115.2 KBps

115.11 KBps

0x1A1

0.08

115.25 KBps

0x340

0.04

8

230.4 KBps

230.76KBps

0xD0

0.16

230.21 KBps

0x1A0

0.08

9

460.8 KBps

461.54KBps

0x68

0.16

461.54KBps

0xD0

0.16

10

921.6KBps

923.07KBps

0x34

0.16

923.07KBps

0x64

0.16

11

2 MBps

2 MBps

0x18

0

2 MBps

0x30

0

12

3 MBps

3 MBps

0x10

0

3 MBps

0x20

0

13

4MBps

N.A

N.A

N.A

4MBps

0x14

0

14

5MBps

N.A

N.A

N.A

5052.63KBps

0x11

1.05

15

6MBps

N.A

N.A

N.A

6MBps

0x10

0

Actual

BRR

% Error

1. The lower the CPU clock the lower the accuracy for a particular baud rate. The upper limit of the achievable baud rate can
be fixed with these data.

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23.4.5

Universal synchronous asynchronous receiver transmitter (USART)

Tolerance of the USART receiver to clock deviation
The asynchronous receiver of the USART works correctly only if the total clock system
deviation is less than the tolerance of the USART receiver. The causes which contribute to
the total deviation are:


DTRA: Deviation due to the transmitter error (which also includes the deviation of the
transmitter’s local oscillator)



DQUANT: Error due to the baud rate quantization of the receiver



DREC: Deviation of the receiver’s local oscillator



DTCL: Deviation due to the transmission line (generally due to the transceivers which
can introduce an asymmetry between the low-to-high transition timing and the high-tolow transition timing)
DTRA + DQUANT + DREC + DTCL  USART receivers tolerance

The USART receiver can receive data correctly at up to the maximum tolerated deviation
specified in Table 88 and Table 88 depending on the following choices:


10- or 11-bit character length defined by the M bit in the USART_CR1 register



Oversampling by 8 or 16 defined by the OVER8 bit in the USART_CR1 register



Bits BRR[3:0] of USART_BRR register are equal to or different from 0000.



Use of 1 bit or 3 bits to sample the data, depending on the value of the ONEBIT bit in
the USART_CR3 register.
Table 88. Tolerance of the USART receiver when BRR [3:0] = 0000
OVER8 bit = 0

OVER8 bit = 1

M bit
ONEBIT=0

ONEBIT=1

ONEBIT=0

ONEBIT=1

0

3.75%

4.375%

2.50%

3.75%

1

3.41%

3.97%

2.27%

3.41%

Table 89. Tolerance of the USART receiver when BRR [3:0] is different from 0000
OVER8 bit = 0

OVER8 bit = 1

M bit

Note:

ONEBIT=0

ONEBIT=1

ONEBIT=0

ONEBIT=1

0

3.33%

3.88%

2%

3%

1

3.03%

3.53%

1.82%

2.73%

The data specified in Table 88,and Table 89 may slightly differ in the special case when the
received frames contain some Idle frames of exactly 10-bit durations when M = 0 (11-bit
durations when M = 1).

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23.4.6

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USART auto baud rate detection
The USART is able to detect and automatically set the USART_BRR register value based
on the reception of one character. Automatic baud rate detection is useful under two
circumstances:


The communication speed of the system is not known in advance



The system is using a relatively low accuracy clock source and this mechanism allows
the correct baud rate to be obtained without measuring the clock deviation.

The clock source frequency must be compatible with the expected communication speed
(Oversampling by 16 must be selected for a baud rate between fCK/65535 and fCK/16).
Before activating the auto baud rate detection, the auto baud rate detection mode must be
chosen. There are various modes based on different character patterns.
They can be chosen through the ABRMOD[1:0] field in the USART_CR2 register. In these
auto baud rate modes, the baud rate is measured several times during the synchronization
data reception and each measurement is compared to the previous one.
These modes are:


Mode 0: Any character starting with a bit at 1. In this case the USART measures the
duration of the Start bit (falling edge to rising edge).



Mode 1: Any character starting with a 10xx bit pattern. In this case, the USART
measures the duration of the Start and of the 1st data bit. The measurement is done
falling edge to falling edge, ensuring better accuracy in the case of slow signal slopes.
In parallel, another check is performed for each intermediate transition of RX line. An
error is generated if the transitions on RX are not sufficiently synchronized with the
receiver (the receiver being based on the baud rate calculated on bit 0).

Prior to activating auto baud rate detection, the USART_BRR register must be initialized by
writing a non-zero baud rate value.
The automatic baud rate detection is activated by setting the ABREN bit in the USART_CR2
register. The USART will then wait for the first character on the RX line. The auto baud rate
operation completion is indicated by the setting of the ABRF flag in the USART_ISR
register. If the line is noisy, the correct baud rate detection cannot be guaranteed. In this
case the BRR value may be corrupted and the ABRE error flag will be set. This also
happens if the communication speed is not compatible with the automatic baud rate
detection range (bit duration not between 16 and 65536 clock periods (oversampling by 16)
and not between 8 and 65536 clock periods (oversampling by 8)).
The RXNE interrupt will signal the end of the operation.
At any later time, the auto baud rate detection may be relaunched by resetting the ABRF
flag (by writing a 0).
Note:

If the USART is disabled (UE=0) during an auto baud rate operation, the BRR value may be
corrupted.

23.4.7

Multiprocessor communication using USART
In multiprocessor communication, the following bits are to be kept cleared:

612/779



LINEN bit in the USART_CR2 register,



HDSEL, IREN and SCEN bits in the USART_CR3 register.

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Universal synchronous asynchronous receiver transmitter (USART)
It is possible to perform multiprocessor communication with the USART (with several
USARTs connected in a network). For instance one of the USARTs can be the master, its TX
output connected to the RX inputs of the other USARTs. The others are slaves, their
respective TX outputs are logically ANDed together and connected to the RX input of the
master.
In multiprocessor configurations it is often desirable that only the intended message
recipient should actively receive the full message contents, thus reducing redundant USART
service overhead for all non addressed receivers.
The non addressed devices may be placed in mute mode by means of the muting function.
In order to use the mute mode feature, the MME bit must be set in the USART_CR1
register.
In mute mode:


None of the reception status bits can be set.



All the receive interrupts are inhibited.



The RWU bit in USART_ISR register is set to 1. RWU can be controlled automatically
by hardware or by software, through the MMRQ bit in the USART_RQR register, under
certain conditions.

The USART can enter or exit from mute mode using one of two methods, depending on the
WAKE bit in the USART_CR1 register:


Idle Line detection if the WAKE bit is reset,



Address Mark detection if the WAKE bit is set.

Idle line detection (WAKE=0)
The USART enters mute mode when the MMRQ bit is written to 1 and the RWU is
automatically set.
It wakes up when an Idle frame is detected. Then the RWU bit is cleared by hardware but
the IDLE bit is not set in the USART_ISR register. An example of mute mode behavior using
Idle line detection is given in Figure 233.
Figure 233. Mute mode using Idle line detection

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Note:

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If the MMRQ is set while the IDLE character has already elapsed, mute mode will not be
entered (RWU is not set).
If the USART is activated while the line is IDLE, the idle state is detected after the duration
of one IDLE frame (not only after the reception of one character frame).

4-bit/7-bit address mark detection (WAKE=1)
In this mode, bytes are recognized as addresses if their MSB is a ‘1’ otherwise they are
considered as data. In an address byte, the address of the targeted receiver is put in the 4
or 7 LSBs. The choice of 7 or 4-bit address detection is done using the ADDM7 bit. This 4bit/7-bit word is compared by the receiver with its own address which is programmed in the
ADD bits in the USART_CR2 register.
Note:

In 7-bit and 9-bit data modes, address detection is done on 6-bit and 8-bit addresses
(ADD[5:0] and ADD[7:0]) respectively.
The USART enters mute mode when an address character is received which does not
match its programmed address. In this case, the RWU bit is set by hardware. The RXNE
flag is not set for this address byte and no interrupt or DMA request is issued when the
USART enters mute mode.
The USART also enters mute mode when the MMRQ bit is written to 1. The RWU bit is also
automatically set in this case.
The USART exits from mute mode when an address character is received which matches
the programmed address. Then the RWU bit is cleared and subsequent bytes are received
normally. The RXNE bit is set for the address character since the RWU bit has been
cleared.
An example of mute mode behavior using address mark detection is given in Figure 234.
Figure 234. Mute mode using address mark detection
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23.4.8

Universal synchronous asynchronous receiver transmitter (USART)

USART parity control
Parity control (generation of parity bit in transmission and parity checking in reception) can
be enabled by setting the PCE bit in the USART_CR1 register. Depending on the frame
length defined by the M bit, the possible USART frame formats are as listed in Table 90.
Table 90. Frame formats
M bit

PCE bit

USART frame(1)

0

0

| SB | 8-bit data | STB |

0

1

| SB | 7-bit data | PB | STB |

1

0

| SB | 9-bit data | STB |

1

1

| SB | 8-bit data PB | STB |

1. Legends: SB: start bit, STB: stop bit, PB: parity bit. In the data register, the PB is always taking the MSB
position (8th or 7th, depending on the M bits value).

Even parity
The parity bit is calculated to obtain an even number of “1s” inside the frame of the 7 or 8
LSB bits (depending on M bit value) and the parity bit.
As an example, if data=00110101, and 4 bits are set, then the parity bit will be 0 if even
parity is selected (PS bit in USART_CR1 = 0).

Odd parity
The parity bit is calculated to obtain an odd number of “1s” inside the frame made of the 7 or
8 LSB bits (depending on M bit value) and the parity bit.
As an example, if data=00110101 and 4 bits set, then the parity bit will be 1 if odd parity is
selected (PS bit in USART_CR1 = 1).

Parity checking in reception
If the parity check fails, the PE flag is set in the USART_ISR register and an interrupt is
generated if PEIE is set in the USART_CR1 register. The PE flag is cleared by software
writing 1 to the PECF in the USART_ICR register.

Parity generation in transmission
If the PCE bit is set in USART_CR1, then the MSB bit of the data written in the data register
is transmitted but is changed by the parity bit (even number of “1s” if even parity is selected
(PS=0) or an odd number of “1s” if odd parity is selected (PS=1)).

23.4.9

A.15.6: USART synchronous mode code exampleUSART

synchronous mode

The synchronous mode is selected by writing the CLKEN bit in the USART_CR2 register to
1. In synchronous mode, the following bits must be kept cleared:


SCEN, HDSEL and IREN bits in the USART_CR3 register.

In this mode, the USART can be used to control bidirectional synchronous serial
communications in master mode. The CK pin is the output of the USART transmitter clock.
No clock pulses are sent to the CK pin during start bit and stop bit. Depending on the state

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of the LBCL bit in the USART_CR2 register, clock pulses are, or are not, generated during
the last valid data bit (address mark). The CPOL bit in the USART_CR2 register is used to
select the clock polarity, and the CPHA bit in the USART_CR2 register is used to select the
phase of the external clock (see Figure 235, Figure 236 and Figure 237).
During the Idle state, preamble and send break, the external CK clock is not activated.
In synchronous mode the USART transmitter works exactly like in asynchronous mode. But
as CK is synchronized with TX (according to CPOL and CPHA), the data on TX is
synchronous.
In this mode the USART receiver works in a different manner compared to the
asynchronous mode. If RE=1, the data is sampled on CK (rising or falling edge, depending
on CPOL and CPHA), without any oversampling. A setup and a hold time must be
respected (which depends on the baud rate: 1/16 bit duration).
Note:

The CK pin works in conjunction with the TX pin. Thus, the clock is provided only if the
transmitter is enabled (TE=1) and data is being transmitted (the data register USART_TDR
written). This means that it is not possible to receive synchronous data without transmitting
data.
The LBCL, CPOL and CPHA bits have to be selected when the USART is disabled (UE=0)
to ensure that the clock pulses function correctly.

Note:

For code example refer to the Appendix A.15.6: USART synchronous mode code example
Figure 235. USART example of synchronous transmission

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Universal synchronous asynchronous receiver transmitter (USART)
Figure 236. USART data clock timing diagram (M=0)
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Figure 238. RX data setup/hold time

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23.4.10

USART Single-wire Half-duplex communication
Single-wire Half-duplex mode is selected by setting the HDSEL bit in the USART_CR3
register. In this mode, the following bits must be kept cleared:


CLKEN bit in the USART_CR2 register,



SCEN and IREN bits in the USART_CR3 register.

The USART can be configured to follow a Single-wire Half-duplex protocol where the TX
and RX lines are internally connected. The selection between half- and Full-duplex
communication is made with a control bit HDSEL in USART_CR3.
As soon as HDSEL is written to 1:


The TX and RX lines are internally connected



The RX pin is no longer used



The TX pin is always released when no data is transmitted. Thus, it acts as a standard
I/O in idle or in reception. It means that the I/O must be configured so that TX is
configured as alternate function open-drain with an external pull-up.

Apart from this, the communication protocol is similar to normal USART mode. Any conflicts
on the line must be managed by software (by the use of a centralized arbiter, for instance).
In particular, the transmission is never blocked by hardware and continues as soon as data
is written in the data register while the TE bit is set.
For code example refer to the Appendix section A.15.7: USART DMA code example.

23.4.11

USART continuous communication in DMA mode
The USART is capable of performing continuous communication using the DMA. The DMA
requests for Rx buffer and Tx buffer are generated independently.

Note:

Please refer to Section 23.3: USART implementation on page 597 to determine if the DMA
mode is supported. If DMA is not supported, use the USART as explained in Section 23.4.2:
USART transmitter or Section 23.4.3: USART receiver. To perform continuous
communication, the user can clear the TXE/ RXNE flags In the USART_ISR register.
For code example refer to the Appendix section A.15.7: USART DMA code example.

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Universal synchronous asynchronous receiver transmitter (USART)

Transmission using DMA
DMA mode can be enabled for transmission by setting DMAT bit in the USART_CR3
register. Data is loaded from a SRAM area configured using the DMA peripheral (refer to ) to
the USART_TDR register whenever the TXE bit is set. To map a DMA channel for USART
transmission, use the following procedure (x denotes the channel number):
1.

Write the USART_TDR register address in the DMA control register to configure it as
the destination of the transfer. The data is moved to this address from memory after
each TXE event.

2.

Write the memory address in the DMA control register to configure it as the source of
the transfer. The data is loaded into the USART_TDR register from this memory area
after each TXE event.

3.

Configure the total number of bytes to be transferred to the DMA control register.

4.

Configure the channel priority in the DMA register

5.

Configure DMA interrupt generation after half/ full transfer as required by the
application.

6.

Clear the TC flag in the USART_ISR register by setting the TCCF bit in the
USART_ICR register.

7.

Activate the channel in the DMA register.

When the number of data transfers programmed in the DMA Controller is reached, the DMA
controller generates an interrupt on the DMA channel interrupt vector.
In transmission mode, once the DMA has written all the data to be transmitted (the TCIF flag
is set in the DMA_ISR register), the TC flag can be monitored to make sure that the USART
communication is complete. This is required to avoid corrupting the last transmission before
disabling the USART or entering Stop mode. Software must wait until TC=1. The TC flag
remains cleared during all data transfers and it is set by hardware at the end of transmission
of the last frame.

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Figure 239. Transmission using DMA
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Reception using DMA
DMA mode can be enabled for reception by setting the DMAR bit in USART_CR3 register.
Data is loaded from the USART_RDR register to a SRAM area configured using the DMA
peripheral (refer to Section 10: Direct memory access controller (DMA) on page 152)
whenever a data byte is received. To map a DMA channel for USART reception, use the
following procedure:
1.

Write the USART_RDR register address in the DMA control register to configure it as
the source of the transfer. The data is moved from this address to the memory after
each RXNE event.

2.

Write the memory address in the DMA control register to configure it as the destination
of the transfer. The data is loaded from USART_RDR to this memory area after each
RXNE event.

3.

Configure the total number of bytes to be transferred to the DMA control register.

4.

Configure the channel priority in the DMA control register

5.

Configure interrupt generation after half/ full transfer as required by the application.

6.

Activate the channel in the DMA control register.

When the number of data transfers programmed in the DMA Controller is reached, the DMA
controller generates an interrupt on the DMA channel interrupt vector.

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Universal synchronous asynchronous receiver transmitter (USART)
Figure 240. Reception using DMA
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Error flagging and interrupt generation in multibuffer communication
In multibuffer communication if any error occurs during the transaction the error flag is
asserted after the current byte. An interrupt is generated if the interrupt enable flag is set.
For framing error, overrun error and noise flag which are asserted with RXNE in single byte
reception, there is a separate error flag interrupt enable bit (EIE bit in the USART_CR3
register), which, if set, enables an interrupt after the current byte if any of these errors occur.

23.4.12

RS232 hardware flow control and RS485 driver enable
using USART
It is possible to control the serial data flow between 2 devices by using the CTS input and
the RTS output. The Figure 241 shows how to connect 2 devices in this mode:
Figure 241. Hardware flow control between 2 USARTs

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RS232 RTS and CTS flow control can be enabled independently by writing the RTSE and
CTSE bits respectively to 1 (in the USART_CR3 register).

RS232 RTS flow control
If the RTS flow control is enabled (RTSE=1), then RTS is asserted (tied low) as long as the
USART receiver is ready to receive a new data. When the receive register is full, RTS is deasserted, indicating that the transmission is expected to stop at the end of the current frame.
Figure 242 shows an example of communication with RTS flow control enabled.
Figure 242. RS232 RTS flow control

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RS232 CTS flow control
If the CTS flow control is enabled (CTSE=1), then the transmitter checks the CTS input
before transmitting the next frame. If CTS is asserted (tied low), then the next data is
transmitted (assuming that data is to be transmitted, in other words, if TXE=0), else the
transmission does not occur. when CTS is de-asserted during a transmission, the current
transmission is completed before the transmitter stops.
When CTSE=1, the CTSIF status bit is automatically set by hardware as soon as the CTS
input toggles. It indicates when the receiver becomes ready or not ready for communication.
An interrupt is generated if the CTSIE bit in the USART_CR3 register is set. Figure 243
shows an example of communication with CTS flow control enabled.

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Figure 243. RS232 CTS flow control
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Note:

For correct behavior, CTS must be asserted at least 3 USART clock source periods before
the end of the current character. In addition it should be noted that the CTSCF flag may not
be set for pulses shorter than 2 x PCLK periods.
For code example refer to the Appendix section A.15.8: USART hardware flow control code
example.

RS485 Driver Enable
The driver enable feature is enabled by setting bit DEM in the USART_CR3 control register.
This allows the user to activate the external transceiver control, through the DE (Driver
Enable) signal. The assertion time is the time between the activation of the DE signal and
the beginning of the START bit. It is programmed using the DEAT [4:0] bit fields in the
USART_CR1 control register. The de-assertion time is the time between the end of the last
stop bit, in a transmitted message, and the de-activation of the DE signal. It is programmed
using the DEDT [4:0] bit fields in the USART_CR1 control register. The polarity of the DE
signal can be configured using the DEP bit in the USART_CR3 control register.
In USART, the DEAT and DEDT are expressed in sample time units (1/8 or 1/16 bit duration,
depending on the oversampling rate).

23.5

USART low-power modes
Table 91. Effect of low-power modes on the USART
Mode

Description

Sleep

No effect. USART interrupt causes the device to exit Sleep mode.

Stop

The USART is not clocked. It is not functional in Stop mode but its
configuration is kept upon wakeup.

Standby

The USART is powered down and must be reinitialized when the device
has exited from Standby mode.

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USART interrupts
Table 92. USART interrupt requests
Interrupt event
Transmit data register empty
CTS interrupt
Transmission Complete
Receive data register not empty (data ready to be read)

Event flag

Enable Control
bit

TXE

TXEIE

CTSIF

CTSIE

TC

TCIE

RXNE

RXNEIE

Overrun error detected

ORE

Idle line detected

IDLE

IDLEIE

PE

PEIE

NF or ORE or FE

EIE

Character match

CMF

CMIE

Receiver timeout

RTOF

RTOIE

Parity error
Noise Flag, Overrun error and Framing Error in multibuffer
communication.

The USART interrupt events are connected to the same interrupt vector (see Figure 244).


During transmission: Transmission Complete, Clear to Send, Transmit data Register
empty interrupt.



During reception: Idle Line detection, Overrun error, Receive data register not empty,
Parity error, Noise Flag, Framing Error, Character match, etc.

These events generate an interrupt if the corresponding Enable Control Bit is set.
Figure 244. USART interrupt mapping diagram

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Universal synchronous asynchronous receiver transmitter (USART)

23.7

USART registers
Refer to Section 1.1 on page 33 for a list of abbreviations used in register descriptions.

23.7.1

Control register 1 (USART_CR1)
Address offset: 0x00
Reset value: 0x0000

31

30

29

28

27

26

Res.

Res.

Res.

M1

Res.

RTOIE

rw

rw

25

24

23

22

21

20

19

DEAT[4:0]
rw

rw

rw

18

17

16

rw

rw

DEDT[4:0]
rw

15

14

13

12

11

10

9

8

7

6

OVER8

CMIE

MME

M0

WAKE

PCE

PS

PEIE

TXEIE

TCIE

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

5

4

RXNEIE IDLEIE
rw

rw

rw

rw

3

2

1

0

TE

RE

Res.

UE

rw

rw

rw

Bits 31:29 Reserved, must be kept at reset value
Bit 28 M1: Word length
This bit, with bit 12 (M0), determines the word length. It is set or cleared by software.
M[1:0] = 00: 1 Start bit, 8 data bits, n stop bits
M[1:0] = 01: 1 Start bit, 9 data bits, n stop bits
M[1:0] = 10: 1 Start bit, 7 data bits, n stop bits
This bit can only be written when the USART is disabled (UE=0).
Bit 27

Reserved, must be kept at reset value

Bit 26 RTOIE: Receiver timeout interrupt enable
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An USART interrupt is generated when the RTOF bit is set in the USART_ISR register.
Note: If the USART does not support the Receiver timeout feature, this bit is reserved and
forced by hardware to ‘0’. Section 23.3: USART implementation on page 597.
Bits 25:21 DEAT[4:0]: Driver Enable assertion time
This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and
the beginning of the start bit. It is expressed in sample time units (1/8 or 1/16 bit duration,
depending on the oversampling rate).
This bit field can only be written when the USART is disabled (UE=0).
Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept
cleared. Please refer to Section 23.3: USART implementation on page 597.
Bits 20:16 DEDT[4:0]: Driver Enable de-assertion time
This 5-bit value defines the time between the end of the last stop bit, in a transmitted
message, and the de-activation of the DE (Driver Enable) signal. It is expressed in sample
time units (1/8 or 1/16 bit duration, depending on the oversampling rate).
If the USART_TDR register is written during the DEDT time, the new data is transmitted only
when the DEDT and DEAT times have both elapsed.
This bit field can only be written when the USART is disabled (UE=0).
Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept
cleared. Please refer to Section 23.3: USART implementation on page 597.

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Bit 15 OVER8: Oversampling mode
0: Oversampling by 16
1: Oversampling by 8
This bit can only be written when the USART is disabled (UE=0).
Bit 14 CMIE: Character match interrupt enable
This bit is set and cleared by software.
0: Interrupt is inhibited
1: A USART interrupt is generated when the CMF bit is set in the USART_ISR register.
Bit 13 MME: Mute mode enable
This bit activates the mute mode function of the USART. when set, the USART can switch
between the active and mute modes, as defined by the WAKE bit. It is set and cleared by
software.
0: Receiver in active mode permanently
1: Receiver can switch between mute mode and active mode.
Bit 12 M0: Word length
This bit determines the word length. It is set or cleared by software.
0: 1 Start bit, 8 data bits, n stop bits
1: 1 Start bit, 9 data bits, n stop bits
Bit 11 WAKE: Receiver wakeup method
This bit determines the USART wakeup method from Mute mode. It is set or cleared by
software.
0: Idle line
1: Address mark
This bit field can only be written when the USART is disabled (UE=0).
Bit 10 PCE: Parity control enable
This bit selects the hardware parity control (generation and detection). When the parity
control is enabled, the computed parity is inserted at the MSB position (9th bit if M=1; 8th bit
if M=0) and parity is checked on the received data. This bit is set and cleared by software.
Once it is set, PCE is active after the current byte (in reception and in transmission).
0: Parity control disabled
1: Parity control enabled
This bit field can only be written when the USART is disabled (UE=0).
Bit 9 PS: Parity selection
This bit selects the odd or even parity when the parity generation/detection is enabled (PCE
bit set). It is set and cleared by software. The parity will be selected after the current byte.
0: Even parity
1: Odd parity
This bit field can only be written when the USART is disabled (UE=0).
Bit 8 PEIE: PE interrupt enable
This bit is set and cleared by software.
0: Interrupt is inhibited
1: A USART interrupt is generated whenever PE=1 in the USART_ISR register
Bit 7 TXEIE: interrupt enable
This bit is set and cleared by software.
0: Interrupt is inhibited
1: A USART interrupt is generated whenever TXE=1 in the USART_ISR register

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Bit 6 TCIE: Transmission complete interrupt enable
This bit is set and cleared by software.
0: Interrupt is inhibited
1: A USART interrupt is generated whenever TC=1 in the USART_ISR register
Bit 5 RXNEIE: RXNE interrupt enable
This bit is set and cleared by software.
0: Interrupt is inhibited
1: A USART interrupt is generated whenever ORE=1 or RXNE=1 in the USART_ISR
register
Bit 4 IDLEIE: IDLE interrupt enable
This bit is set and cleared by software.
0: Interrupt is inhibited
1: A USART interrupt is generated whenever IDLE=1 in the USART_ISR register
Bit 3 TE: Transmitter enable
This bit enables the transmitter. It is set and cleared by software.
0: Transmitter is disabled
1: Transmitter is enabled
During transmission, a “0” pulse on the TE bit (“0” followed by “1”) sends a preamble
(idle line) after the current word. In order to generate an idle character, the TE must not
be immediately written to 1.
Bit 2 RE: Receiver enable
This bit enables the receiver. It is set and cleared by software.
0: Receiver is disabled
1: Receiver is enabled and begins searching for a start bit
Bit 1 Reserved, must be kept at reset value.
Bit 0 UE: USART enable
When this bit is cleared, the USART prescalers and outputs are stopped immediately, and
current operations are discarded. The configuration of the USART is kept, but all the status
flags, in the USART_ISR are set to their default values. This bit is set and cleared by
software.
0: USART prescaler and outputs disabled, low-power mode
1: USART enabled
Note: In order to go into low-power mode without generating errors on the line, the TE bit
must be reset before and the software must wait for the TC bit in the USART_ISR to be
set before resetting the UE bit.
The DMA requests are also reset when UE = 0 so the DMA channel must be disabled
before resetting the UE bit.

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23.7.2

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Control register 2 (USART_CR2)
Address offset: 0x04
Reset value: 0x0000

31

30

29

28

27

ADD[7:4]

26

25

24

ADD[3:0]

23
RTOEN

22

21

ABRMOD[1:0]

20

19

18

17

MSBFI
DATAINV TXINV
ABREN
RST

16
RXINV

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

SWAP

Res.

CLKEN

CPOL

CPHA

LBCL

Res.

Res.

.Res.

ADDM7

Res.

Res.

Res.

Res.

rw

rw

rw

rw

rw

STOP[1:0]
rw

rw

rw

Bits 31:28 ADD[7:4]: Address of the USART node
This bit-field gives the address of the USART node or a character code to be recognized.
This is used in multiprocessor communication during Mute mode or Stop mode, for wakeup with 7bit address mark detection. The MSB of the character sent by the transmitter should be equal to 1.
It may also be used for character detection during normal reception, Mute mode inactive . In this
case, the whole received character (8-bit) is compared to the ADD[7:0] value and CMF flag is set on
match.
This bit field can only be written when reception is disabled (RE = 0) or the USART is disabled
(UE=0)
Bits 27:24 ADD[3:0]: Address of the USART node
This bit-field gives the address of the USART node or a character code to be recognized.
This is used in multiprocessor communication during Mute mode or Stop mode, for wakeup with
address mark detection.
This bit field can only be written when reception is disabled (RE = 0) or the USART is disabled
(UE=0)
Bit 23 RTOEN: Receiver timeout enable
This bit is set and cleared by software.
0: Receiver timeout feature disabled.
1: Receiver timeout feature enabled.
When this feature is enabled, the RTOF flag in the USART_ISR register is set if the RX line is idle
(no reception) for the duration programmed in the RTOR (receiver timeout register).
Note: If the USART does not support the Receiver timeout feature, this bit is reserved and forced by
hardware to ‘0’. Please refer to Section 23.3: USART implementation on page 597.
Bits 22:21 ABRMOD[1:0]: Auto baud rate mode
These bits are set and cleared by software.
00: Measurement of the start bit is used to detect the baud rate.
01: Falling edge to falling edge measurement. (the received frame must start with a single bit = 1 ->
Frame = Start10xxxxxx)
10: 0x7F frame detection.
11: 0x55 frame detection
This bit field can only be written when ABREN = 0 or the USART is disabled (UE=0).
Note: If DATAINV=1 and/or MSBFIRST=1 the patterns must be the same on the line, for example
0xAA for MSBFIRST)
If the USART does not support the auto baud rate feature, this bit is reserved and forced by
hardware to ‘0’. Please refer to Section 23.3: USART implementation on page 597.

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Bit 20 ABREN: Auto baud rate enable
This bit is set and cleared by software.
0: Auto baud rate detection is disabled.
1: Auto baud rate detection is enabled.
Note: If the USART does not support the auto baud rate feature, this bit is reserved and forced by
hardware to ‘0’. Please refer to Section 23.3: USART implementation on page 597.
Bit 19 MSBFIRST: Most significant bit first
This bit is set and cleared by software.
0: data is transmitted/received with data bit 0 first, following the start bit.
1: data is transmitted/received with the MSB (bit 7/8/9) first, following the start bit.
This bit field can only be written when the USART is disabled (UE=0).
Bit 18 DATAINV: Binary data inversion
This bit is set and cleared by software.
0: Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L)
1: Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The
parity bit is also inverted.
This bit field can only be written when the USART is disabled (UE=0).
Bit 17 TXINV: TX pin active level inversion
This bit is set and cleared by software.
0: TX pin signal works using the standard logic levels (VDD =1/idle, Gnd=0/mark)
1: TX pin signal values are inverted. (VDD =0/mark, Gnd=1/idle).
This allows the use of an external inverter on the TX line.
This bit field can only be written when the USART is disabled (UE=0).
Bit 16 RXINV: RX pin active level inversion
This bit is set and cleared by software.
0: RX pin signal works using the standard logic levels (VDD =1/idle, Gnd=0/mark)
1: RX pin signal values are inverted. (VDD =0/mark, Gnd=1/idle).
This allows the use of an external inverter on the RX line.
This bit field can only be written when the USART is disabled (UE=0).
Bit 15 SWAP: Swap TX/RX pins
This bit is set and cleared by software.
0: TX/RX pins are used as defined in standard pinout
1: The TX and RX pins functions are swapped. This allows to work in the case of a cross-wired
connection to another USART.
This bit field can only be written when the USART is disabled (UE=0).
Bit 14 Reserved, must be kept at reset value.
Bits 13:12 STOP[1:0]: STOP bits
These bits are used for programming the stop bits.
00: 1 stop bit
01: Reserved
10: 2 stop bits
11: Reserved
This bit field can only be written when the USART is disabled (UE=0).

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Bit 11 CLKEN: Clock enable
This bit allows the user to enable the CK pin.
0: CK pin disabled
1: CK pin enabled
This bit can only be written when the USART is disabled (UE=0).
Note: If synchronous mode is not supported, this bit is reserved and forced by hardware to ‘0’.
Please refer to Section 23.3: USART implementation on page 597.
Bit 10 CPOL: Clock polarity
This bit allows the user to select the polarity of the clock output on the CK pin in synchronous mode.
It works in conjunction with the CPHA bit to produce the desired clock/data relationship
0: Steady low value on CK pin outside transmission window
1: Steady high value on CK pin outside transmission window
This bit can only be written when the USART is disabled (UE=0).
Note: If synchronous mode is not supported, this bit is reserved and forced by hardware to ‘0’.
Please refer to Section 23.3: USART implementation on page 597.
Bit 9 CPHA: Clock phase
This bit is used to select the phase of the clock output on the CK pin in synchronous mode. It works
in conjunction with the CPOL bit to produce the desired clock/data relationship (see Figure 236 and
Figure 237)
0: The first clock transition is the first data capture edge
1: The second clock transition is the first data capture edge
This bit can only be written when the USART is disabled (UE=0).
Note: If synchronous mode is not supported, this bit is reserved and forced by hardware to ‘0’.
Please refer to Section 23.3: USART implementation on page 597.
Bit 8 LBCL: Last bit clock pulse
This bit is used to select whether the clock pulse associated with the last data bit transmitted (MSB)
has to be output on the CK pin in synchronous mode.
0: The clock pulse of the last data bit is not output to the CK pin
1: The clock pulse of the last data bit is output to the CK pin
Caution: The last bit is the 7th or 8th or 9th data bit transmitted depending on the 7 or 8 or 9 bit
format selected by the M bit in the USART_CR1 register.
This bit can only be written when the USART is disabled (UE=0).
Note: If synchronous mode is not supported, this bit is reserved and forced by hardware to ‘0’.
Please refer to Section 23.3: USART implementation on page 597.
Bits 7:5 Reserved, must be kept at reset value.
Bit 4 ADDM7:7-bit Address Detection/4-bit Address Detection
This bit is for selection between 4-bit address detection or 7-bit address detection.
0: 4-bit address detection
1: 7-bit address detection (in 8-bit data mode)
This bit can only be written when the USART is disabled (UE=0)
Note: In 7-bit and 9-bit data modes, the address detection is done on 6-bit and 8-bit address
(ADD[5:0] and ADD[7:0]) respectively.
Bits 3:0 Reserved, must be kept at reset value.

Note:

The 3 bits (CPOL, CPHA, LBCL) should not be written while the transmitter is enabled.

23.7.3

Control register 3 (USART_CR3)
Address offset: 0x08

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Reset value: 0x0000

31

30

29

28

27

26

25

24

23

22

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

ONE
BIT

CTSIE

CTSE

RTSE

DMAT

DMAR

Res.

Res.

HDSEL

Res.

Res.

EIE

rw

rw

rw

rw

rw

rw

DEP

DEM

DDRE

OVR
DIS

rw

rw

rw

rw

21

20

19

Res.

18

17

16

Res.

Res.

rw

rw

Bits 31:25 Reserved, must be kept at reset value.
Bit 24 Reserved, must be kept at reset value.
Bit 23 Reserved, must be kept at reset value.
Bits 19:17 Reserved, must be kept at reset value.
Bit:16 Reserved, must be kept at reset value.
Bit 15 DEP: Driver enable polarity selection
0: DE signal is active high.
1: DE signal is active low.
This bit can only be written when the USART is disabled (UE=0).
Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept
cleared. Please refer to Section 23.3: USART implementation on page 597.
Bit 14 DEM: Driver enable mode
This bit allows the user to activate the external transceiver control, through the DE signal.
0: DE function is disabled. 
1: DE function is enabled. The DE signal is output on the RTS pin.
This bit can only be written when the USART is disabled (UE=0).
Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept
cleared. Section 23.3: USART implementation on page 597.
Bit 13 DDRE: DMA Disable on Reception Error
0: DMA is not disabled in case of reception error. The corresponding error flag is set but
RXNE is kept 0 preventing from overrun. As a consequence, the DMA request is not
asserted, so the erroneous data is not transferred (no DMA request), but next correct
received data will be transferred .
1: DMA is disabled following a reception error. The corresponding error flag is set, as well as
RXNE. The DMA request is masked until the error flag is cleared. This means that the
software must first disable the DMA request (DMAR = 0) or clear RXNE before clearing the
error flag.
This bit can only be written when the USART is disabled (UE=0).
Note: The reception errors are: parity error, framing error or noise error.
Bit 12 OVRDIS: Overrun Disable
This bit is used to disable the receive overrun detection.
0: Overrun Error Flag, ORE, is set when received data is not read before receiving new data. 
1: Overrun functionality is disabled. If new data is received while the RXNE flag is still set
the ORE flag is not set and the new received data overwrites the previous content of the
USART_RDR register.
This bit can only be written when the USART is disabled (UE=0).
Note: This control bit allows checking the communication flow without reading the data.

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Bit 11 ONEBIT: One sample bit method enable
This bit allows the user to select the sample method. When the one sample bit method is
selected the noise detection flag (NF) is disabled.
0: Three sample bit method
1: One sample bit method
This bit can only be written when the USART is disabled (UE=0).
Note: ONEBIT feature applies only to data bits, It does not apply to Start bit.
Bit 10 CTSIE: CTS interrupt enable
0: Interrupt is inhibited
1: An interrupt is generated whenever CTSIF=1 in the USART_ISR register
Note: If the hardware flow control feature is not supported, this bit is reserved and forced by
hardware to ‘0’. Please refer to Section 23.3: USART implementation on page 597.
Bit 9 CTSE: CTS enable
0: CTS hardware flow control disabled
1: CTS mode enabled, data is only transmitted when the CTS input is asserted (tied to 0). If
the CTS input is de-asserted while data is being transmitted, then the transmission is
completed before stopping. If data is written into the data register while CTS is de-asserted,
the transmission is postponed until CTS is asserted.
This bit can only be written when the USART is disabled (UE=0)
Note: If the hardware flow control feature is not supported, this bit is reserved and forced by
hardware to ‘0’. Please refer to Section 23.3: USART implementation on page 597.
Bit 8 RTSE: RTS enable
0: RTS hardware flow control disabled
1: RTS output enabled, data is only requested when there is space in the receive buffer. The
transmission of data is expected to cease after the current character has been transmitted.
The RTS output is asserted (pulled to 0) when data can be received.
This bit can only be written when the USART is disabled (UE=0).
Note: If the hardware flow control feature is not supported, this bit is reserved and forced by
hardware to ‘0’. Please refer to Section 23.3: USART implementation on page 597.
Bit 7 DMAT: DMA enable transmitter
This bit is set/reset by software
1: DMA mode is enabled for transmission
0: DMA mode is disabled for transmission
Bit 6 DMAR: DMA enable receiver
This bit is set/reset by software
1: DMA mode is enabled for reception
0: DMA mode is disabled for reception
Bits 5:4 Reserved, must be kept at reset value.

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RM0360

Universal synchronous asynchronous receiver transmitter (USART)

Bit 3 HDSEL: Half-duplex selection
Selection of Single-wire Half-duplex mode
0: Half duplex mode is not selected
1: Half duplex mode is selected
This bit can only be written when the USART is disabled (UE=0).
Bits 2:1 Reserved, must be kept at reset value.
Bit 0 EIE: Error interrupt enable
Error Interrupt Enable Bit is required to enable interrupt generation in case of a framing
error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USART_ISR register).
0: Interrupt is inhibited
1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USART_ISR register.

23.7.4

Baud rate register (USART_BRR)
This register can only be written when the USART is disabled (UE=0). It may be
automatically updated by hardware in auto baud rate detection mode.
Address offset: 0x0C
Reset value: 0x0000

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

rw

rw

rw

rw

rw

rw

rw

20

19

18

17

16

BRR[15:0]
rw

rw

rw

rw

rw

rw

rw

rw

rw

Bits 31:16 Reserved, must be kept at reset value.
Bits 15:4 BRR[15:4]
BRR[15:4] = USARTDIV[15:4]
Bits 3:0 BRR[3:0]
When OVER8 = 0, BRR[3:0] = USARTDIV[3:0].
When OVER8 = 1:
BRR[2:0] = USARTDIV[3:0] shifted 1 bit to the right.
BRR[3] must be kept cleared.

23.7.5

Receiver timeout register (USART_RTOR)
Address offset: 0x14
Reset value: 0x0000

31

30

29

28

27

26

25

24

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

15

14

13

12

11

10

9

8

23

22

21

RTO[23:16]
rw

rw

rw

rw

rw

rw

rw

rw

7

6

5

4

3

2

1

0

rw

rw

rw

rw

rw

rw

rw

RTO[15:0]
rw

rw

rw

rw

rw

rw

rw

rw

rw

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Bits 31:24 Reserved, must be kept at reset value.
Bits 23:0 RTO[23:0]: Receiver timeout value
This bit-field gives the Receiver timeout value in terms of number of bit duration.
In standard mode, the RTOF flag is set if, after the last received character, no new start bit is
detected for more than the RTO value.
Note: This value must only be programmed once per received character.

Note:

RTOR can be written on the fly. If the new value is lower than or equal to the counter, the
RTOF flag is set.
This register is reserved and forced by hardware to “0x00000000” when the Receiver
timeout feature is not supported. Please refer to Section 23.3: USART implementation on
page 597.

23.7.6

Request register (USART_RQR)
Address offset: 0x18
Reset value: 0x0000

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

3

2

1

0

15

14

13

12

11

10

9

8

7

6

5

4

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

RXFRQ MMRQ SBKRQ ABRRQ
w

w

w

w

Bits 31:4 Reserved, must be kept at reset value
Bit 3 RXFRQ: Receive data flush request
Writing 1 to this bit clears the RXNE flag.
This allows to discard the received data without reading it, and avoid an overrun condition.
Bit 2 MMRQ: Mute mode request
Writing 1 to this bit puts the USART in mute mode and sets the RWU flag.
Bit 1 SBKRQ: Send break request
Writing 1 to this bit sets the SBKF flag and request to send a BREAK on the line, as soon as
the transmit machine is available.
Note: In the case the application needs to send the break character following all previously
inserted data, including the ones not yet transmitted, the software should wait for the
TXE flag assertion before setting the SBKRQ bit.
Bit 0 ABRRQ: Auto baud rate request
Writing 1 to this bit resets the ABRF flag in the USART_ISR and request an automatic baud
rate measurement on the next received data frame.
Note: If the USART does not support the auto baud rate feature, this bit is reserved and
forced by hardware to ‘0’. Please refer to Section 23.3: USART implementation on
page 597.

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Universal synchronous asynchronous receiver transmitter (USART)

23.7.7

Interrupt and status register (USART_ISR)
Address offset: 0x1C
Reset value: 0x0200 00C0

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

RWU

SBKF

CMF

BUSY

r

r

r

r

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

ABRF

ABRE

Res.

Res.

RTOF

CTS

CTSIF

Res.

TXE

TC

RXNE

IDLE

ORE

NF

FE

PE

r

r

r

r

r

r

r

r

r

r

r

r

r

Bits 31:25 Reserved, must be kept at reset value.
Bits 24:22 Reserved, must be kept at reset value.
Bit 21 Reserved, must be kept at reset value
Bit 20 Reserved, must be kept at reset value.
Bit 19 RWU: Receiver wakeup from Mute mode
This bit indicates if the USART is in mute mode. It is cleared/set by hardware when a
wakeup/mute sequence is recognized. The mute mode control sequence (address or IDLE)
is selected by the WAKE bit in the USART_CR1 register.
When wakeup on IDLE mode is selected, this bit can only be set by software, writing 1 to the
MMRQ bit in the USART_RQR register.
0: Receiver in active mode
1: Receiver in mute mode
Bit 18 SBKF: Send break flag
This bit indicates that a send break character was requested. It is set by software, by writing
1 to the SBKRQ bit in the USART_RQR register. It is automatically reset by hardware during
the stop bit of break transmission.
0: No break character is transmitted
1: Break character will be transmitted
Bit 17 CMF: Character match flag
This bit is set by hardware, when the character defined by ADD[7:0] is received. It is cleared
by software, writing 1 to the CMCF in the USART_ICR register.
An interrupt is generated if CMIE=1in the USART_CR1 register.
0: No Character match detected
1: Character Match detected
Bit 16 BUSY: Busy flag
This bit is set and reset by hardware. It is active when a communication is ongoing on the
RX line (successful start bit detected). It is reset at the end of the reception (successful or
not).
0: USART is idle (no reception)
1: Reception on going

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Bit 15 ABRF: Auto baud rate flag
This bit is set by hardware when the automatic baud rate has been set (RXNE will also be
set, generating an interrupt if RXNEIE = 1) or when the auto baud rate operation was
completed without success (ABRE=1) (ABRE, RXNE and FE are also set in this case)
It is cleared by software, in order to request a new auto baud rate detection, by writing 1 to
the ABRRQ in the USART_RQR register.
Note: If the USART does not support the auto baud rate feature, this bit is reserved and
forced by hardware to ‘0’.
Bit 14 ABRE: Auto baud rate error
This bit is set by hardware if the baud rate measurement failed (baud rate out of range or
character comparison failed)
It is cleared by software, by writing 1 to the ABRRQ bit in the USART_CR3 register.
Note: If the USART does not support the auto baud rate feature, this bit is reserved and
forced by hardware to ‘0’.
Bits 13:12 Reserved, must be kept at reset value.
Bit 11 RTOF: Receiver timeout
This bit is set by hardware when the timeout value, programmed in the RTOR register has
lapsed, without any communication. It is cleared by software, writing 1 to the RTOCF bit in
the USART_ICR register.
An interrupt is generated if RTOIE=1 in the USART_CR1 register.
0: Timeout value not reached
1: Timeout value reached without any data reception
Note: If a time equal to the value programmed in RTOR register separates 2 characters,
RTOF is not set. If this time exceeds this value + 2 sample times (2/16 or 2/8,
depending on the oversampling method), RTOF flag is set.
The counter counts even if RE = 0 but RTOF is set only when RE = 1. If the timeout has
already elapsed when RE is set, then RTOF will be set.
If the USART does not support the Receiver timeout feature, this bit is reserved and
forced by hardware to ‘0’.
Bit 10 CTS: CTS flag
This bit is set/reset by hardware. It is an inverted copy of the status of the CTS input pin.
0: CTS line set
1: CTS line reset
Note: If the hardware flow control feature is not supported, this bit is reserved and forced by
hardware to ‘0’.
Bit 9 CTSIF: CTS interrupt flag
This bit is set by hardware when the CTS input toggles, if the CTSE bit is set. It is cleared by
software, by writing 1 to the CTSCF bit in the USART_ICR register.
An interrupt is generated if CTSIE=1 in the USART_CR3 register.
0: No change occurred on the CTS status line
1: A change occurred on the CTS status line
Note: If the hardware flow control feature is not supported, this bit is reserved and forced by
hardware to ‘0’.
Bit 8 Reserved, must be kept at reset value.

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Universal synchronous asynchronous receiver transmitter (USART)

Bit 7 TXE: Transmit data register empty
This bit is set by hardware when the content of the USART_TDR register has been
transferred into the shift register. It is cleared by a write to the USART_TDR register.
An interrupt is generated if the TXEIE bit =1 in the USART_CR1 register.
0: data is not transferred to the shift register
1: data is transferred to the shift register)
Note: This bit is used during single buffer transmission.
Bit 6 TC: Transmission complete
This bit is set by hardware if the transmission of a frame containing data is complete and if
TXE is set. An interrupt is generated if TCIE=1 in the USART_CR1 register. It is cleared by
software, writing 1 to the TCCF in the USART_ICR register or by a write to the USART_TDR
register.
An interrupt is generated if TCIE=1 in the USART_CR1 register.
0: Transmission is not complete
1: Transmission is complete
Note: If TE bit is reset and no transmission is on going, the TC bit will be set immediately.
Bit 5 RXNE: Read data register not empty
This bit is set by hardware when the content of the RDR shift register has been transferred
to the USART_RDR register. It is cleared by a read to the USART_RDR register. The RXNE
flag can also be cleared by writing 1 to the RXFRQ in the USART_RQR register.
An interrupt is generated if RXNEIE=1 in the USART_CR1 register.
0: data is not received
1: Received data is ready to be read.
Bit 4 IDLE: Idle line detected
This bit is set by hardware when an Idle Line is detected. An interrupt is generated if
IDLEIE=1 in the USART_CR1 register. It is cleared by software, writing 1 to the IDLECF in
the USART_ICR register.
0: No Idle line is detected
1: Idle line is detected
Note: The IDLE bit will not be set again until the RXNE bit has been set (i.e. a new idle line
occurs).
If mute mode is enabled (MME=1), IDLE is set if the USART is not mute (RWU=0),
whatever the mute mode selected by the WAKE bit. If RWU=1, IDLE is not set.
Bit 3 ORE: Overrun error
This bit is set by hardware when the data currently being received in the shift register is
ready to be transferred into the RDR register while RXNE=1. It is cleared by a software,
writing 1 to the ORECF, in the USART_ICR register.
An interrupt is generated if RXNEIE=1 or EIE = 1 in the USART_CR1 register.
0: No overrun error
1: Overrun error is detected
Note: When this bit is set, the RDR register content is not lost but the shift register is
overwritten. An interrupt is generated if the ORE flag is set during multibuffer
communication if the EIE bit is set.
This bit is permanently forced to 0 (no overrun detection) when the OVRDIS bit is set in
the USART_CR3 register.

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Bit 2 NF: START bit Noise detection flag
This bit is set by hardware when noise is detected on a received frame. It is cleared by
software, writing 1 to the NFCF bit in the USART_ICR register.
0: No noise is detected
1: Noise is detected
Note: This bit does not generate an interrupt as it appears at the same time as the RXNE bit
which itself generates an interrupt. An interrupt is generated when the NF flag is set
during multibuffer communication if the EIE bit is set.
Note: When the line is noise-free, the NF flag can be disabled by programming the ONEBIT
bit to 1 to increase the USART tolerance to deviations (Refer to Section 23.4.5:
Tolerance of the USART receiver to clock deviation on page 611).
Bit 1 FE: Framing error
This bit is set by hardware when a de-synchronization, excessive noise or a break character
is detected. It is cleared by software, writing 1 to the FECF bit in the USART_ICR register.
An interrupt is generated if EIE = 1 in the USART_CR1 register.
0: No Framing error is detected
1: Framing error or break character is detected
Bit 0 PE: Parity error
This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by
software, writing 1 to the PECF in the USART_ICR register. 
An interrupt is generated if PEIE = 1 in the USART_CR1 register.
0: No parity error
1: Parity error

23.7.8

Interrupt flag clear register (USART_ICR)
Address offset: 0x20
Reset value: 0x0000

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

CMCF

Res.

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Res.

Res.

Res.

Res.

RTOCF

Res.

CTSCF

Res.

Res.

TCCF

Res.

NCF

FECF

PECF

rc_w1

rc_w1

rc_w1

rc_w1

rc_w1

rc_w1

rc_w1

IDLECF ORECF
rc_w1

rc_w1

Bits 31:20 Reserved, must be kept at reset value.
Bits 19:18 Reserved, must be kept at reset value.
Bit 17 CMCF: Character match clear flag
Writing 1 to this bit clears the CMF flag in the USART_ISR register.
Bits 16:12 Reserved, must be kept at reset value.
Bit 11 RTOCF: Receiver timeout clear flag
Writing 1 to this bit clears the RTOF flag in the USART_ISR register.
Note: If the USART does not support the Receiver timeout feature, this bit is reserved and
forced by hardware to ‘0’. Please refer to Section 23.3: USART implementation on
page 597.
Bit 10 Reserved, must be kept at reset value.

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RM0360

Universal synchronous asynchronous receiver transmitter (USART)

Bit 9 CTSCF: CTS clear flag
Writing 1 to this bit clears the CTSIF flag in the USART_ISR register.
Note: If the hardware flow control feature is not supported, this bit is reserved and forced by
hardware to ‘0’. Please refer to Section 23.3: USART implementation on page 597.
Bit 8 Reserved, must be kept at reset value.
Bit 7 Reserved, must be kept at reset value.
Bit 6 TCCF: Transmission complete clear flag
Writing 1 to this bit clears the TC flag in the USART_ISR register.
Bit 5 Reserved, must be kept at reset value.
Bit 4 IDLECF: Idle line detected clear flag
Writing 1 to this bit clears the IDLE flag in the USART_ISR register.
Bit 3 ORECF: Overrun error clear flag
Writing 1 to this bit clears the ORE flag in the USART_ISR register.
Bit 2 NCF: Noise detected clear flag
Writing 1 to this bit clears the NF flag in the USART_ISR register.
Bit 1 FECF: Framing error clear flag
Writing 1 to this bit clears the FE flag in the USART_ISR register.
Bit 0 PECF: Parity error clear flag
Writing 1 to this bit clears the PE flag in the USART_ISR register.

23.7.9

Receive data register (USART_RDR)
Address offset: 0x24
Reset value: Undefined

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

8

7

6

5

4

3

2

1

0

r

r

r

r

15

14

13

12

11

10

9

Res.

Res.

Res.

Res.

Res.

Res.

Res.

RDR[8:0]
r

r

r

r

r

Bits 31:9 Reserved, must be kept at reset value.
Bits 8:0 RDR[8:0]: Receive data value
Contains the received data character.
The RDR register provides the parallel interface between the input shift register and the
internal bus (see Figure 226).
When receiving with the parity enabled, the value read in the MSB bit is the received parity
bit.

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Universal synchronous asynchronous receiver transmitter (USART)

23.7.10

RM0360

Transmit data register (USART_TDR)
Address offset: 0x28
Reset value: Undefined

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Res.

Res.

Res.

Res.

Res.

Res.

Res.
rw

rw

rw

rw

rw

rw

rw

rw

TDR[8:0]
rw

Bits 31:9 Reserved, must be kept at reset value.
Bits 8:0 TDR[8:0]: Transmit data value
Contains the data character to be transmitted.
The TDR register provides the parallel interface between the internal bus and the output
shift register (see Figure 226).
When transmitting with the parity enabled (PCE bit set to 1 in the USART_CR1 register),
the value written in the MSB (bit 7 or bit 8 depending on the data length) has no effect
because it is replaced by the parity.
Note: This register must be written only when TXE=1.

23.7.11

USART register map
The table below gives the USART register map and reset values.

DMAT

DMAR

0

0

RXINV

SWAP

0

0

0

0

0

0

USART_CR3

Res.

Res.

DEP

DEM

DDRE

0

0

0

0x08

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

USART_BRR
0x0C

Res.

Reset value

Reset value

0

0

BRR[15:0]
0

DocID025023 Rev 4

0
Res.

TXINV

0

Res.

DATAINV

0

UE

RTSE
0

0

Res.

CTSE
0

0

Res.

CTSIE
0

0

Res.

TE

RE

ADDM7

ONEBIT
0

0

EIE

IDLEIE

.Res.

OVRDIS
0

0

Res.

TCIE

RXNEIE

Res.

0

0

Res.

TXEIE
Res.

0

0

0x04

Res.

PS

PEIE
LBCL

0

0

ADD[3:0]

Res.

PCE
CPOL

CPHA

0

0

ADD[7:4]

0

HDSEL

M0

WAKE
CLKEN

0

MME
0

CMIE

STOP
[1:0]

Res.

0

DEDT0

0

OVER8

0

MSBFIRST

DEDT1

0

Res.

DEDT2

0

Res.

DEDT3

0

ABREN

DEAT0

0

Res.

DEDT4

0

0

ABRMOD0

DEAT1

0

0

Res.

DEAT2

0

0

Reset value

USART_CR2

640/779

0

0

ABRMOD1

0

Res.

DEAT3

0

RTOEN

0

Res.

0

Res.

RTOIE

0

Res.

0

Res.

DEAT4

M1

0

Res.

0

Res.

0

Res.

0

Res.

0

Res.

Reset value

Res.

Res.

USART_CR1
0x00

Res.

Register

Res.

Offset

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0

Table 93. USART register map and reset values

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0x28
USART_TDR

Reset value

DocID025023 Rev 4
Res.

Res.

0

Res.

Res.

Res.

0

Res.

Res.

ABRF
ABRE
0

Res.

BUSY
0

Res.
CMCF
Res.
Res.
Res.

CTSIF
0

Reset value
Res.
CTSCF
0

ORE
NF
FE
PE

0
0
0
0

Res.
IDLECF
0

RDR[8:0]

X X X X X X
TDR[8:0]

X X X X X X

PECF

IDLE
0
FECF

RXNE
0
NCF

TC
1

TCCF

Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
Res.
Res.

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

ABRRQ

Res.

0
SBKRQ

Res.

0
MMRQ

Res.

0

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.
0

Res.

Res.

Res.

Res.

0

RXFRQ

Reset value

ORECF

TXE
0

1

Res.

Res.

CTS
0
Res.

RTOF

Res.
0

RTOCF

Res.

Res.

CMF

0

Res.

SBKF

0

Res.

Res.

Res.

Res.

RWU

Res.

Res.

Res.

0

Res.

Res.

Res.

Res.

0

Res.

Res.

Res.

Res.

Res.

Res.

Reset value

Res.

Res.

Res.

Res.

Res.

Res.

Reset value

Res.

Res.

Res.

Res.

Res.

Res.

0

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Reset value

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

USART_RTOR

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0

Reserved

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

0x10

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Register

Res.

Res.

Res.

Res.

USART_RDR

Res.

0x24

Res.

USART_ICR

Res.

0x20
Res.

USART_ISR

Res.

0x1C

Res.

USART_RQR

Res.

0x18

Res.

Offset

0x14

Res.

RM0360
Universal synchronous asynchronous receiver transmitter (USART)

Table 93. USART register map and reset values (continued)

RTO[23:0]

0
0
0
0

0
0
0
0

X
X
X

X
X
X

Refer to Section 2.2 on page 36 for the register boundary addresses.



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Serial peripheral interface (SPI)

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24

Serial peripheral interface (SPI)

24.1

Introduction
The SPI interface can be used to communicate with external devices using the SPI protocol.
SPI mode is selectable by software. SPI Motorola mode is selected by default after a device
reset.
The serial peripheral interface (SPI) protocol supports half-duplex, full-duplex and simplex
synchronous, serial communication with external devices. The interface can be configured
as master and in this case it provides the communication clock (SCK) to the external slave
device. The interface is also capable of operating in multimaster configuration.

24.2

642/779

SPI main features


Master or slave operation



Full-duplex synchronous transfers on three lines



Half-duplex synchronous transfer on two lines (with bidirectional data line)



Simplex synchronous transfers on two lines (with unidirectional data line)



4-bit to 16-bit data size selection



Multimaster mode capability



8 master mode baud rate prescalers up to fPCLK/2.



Slave mode frequency up to fPCLK/2.



NSS management by hardware or software for both master and slave: dynamic change
of master/slave operations



Programmable clock polarity and phase



Programmable data order with MSB-first or LSB-first shifting



Dedicated transmission and reception flags with interrupt capability



SPI bus busy status flag



SPI Motorola support



Hardware CRC feature for reliable communication:
–

CRC value can be transmitted as last byte in Tx mode

–

Automatic CRC error checking for last received byte



Master mode fault, overrun flags with interrupt capability



CRC Error flag



Two 32-bit embedded Rx and Tx FIFOs with DMA capability



SPI TI mode support

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Serial peripheral interface (SPI)

24.3

SPI implementation
This manual describes the SPI implementation in STM32F0x0 devices.
Table 94. STM32F0x0 SPI implementation(1)

SPI Features

STM32F030x4,
STM32F030x6
STM32F070x6

STM32F070xB
STM32F030xC

STM32F030x8

SPI1

SPI1

SPI2

SPI1

SPI2

Hardware CRC calculation

X

X

X

X

X

Rx/Tx FIFO

X

X

X

X

X

NSS pulse mode

X

X

X

X

X

I2S mode

-

-

-

-

-

TI mode

X

X

X

X

X

1. X = supported.

24.4

SPI functional description

24.4.1

General description
The SPI allows synchronous, serial communication between the MCU and external devices.
Application software can manage the communication by polling the status flag or using
dedicated SPI interrupt. The main elements of SPI and their interactions are shown in the
following block diagram Figure 245.
Figure 245. SPI block diagram
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Four I/O pins are dedicated to SPI communication with external devices.


MISO: Master In / Slave Out data. In the general case, this pin is used to transmit data
in slave mode and receive data in master mode.



MOSI: Master Out / Slave In data. In the general case, this pin is used to transmit data
in master mode and receive data in slave mode.



SCK: Serial Clock output pin for SPI masters and input pin for SPI slaves.



NSS: Slave select pin. Depending on the SPI and NSS settings, this pin can be used to
either:
–

select an individual slave device for communication

–

synchronize the data frame or

–

detect a conflict between multiple masters

See Section 24.4.5: Slave select (NSS) pin management for details.
The SPI bus allows the communication between one master device and one or more slave
devices. The bus consists of at least two wires - one for the clock signal and the other for
synchronous data transfer. Other signals can be added depending on the data exchange
between SPI nodes and their slave select signal management.

24.4.2

Communications between one master and one slave
The SPI allows the MCU to communicate using different configurations, depending on the
device targeted and the application requirements. These configurations use 2 or 3 wires
(with software NSS management) or 3 or 4 wires (with hardware NSS management).
Communication is always initiated by the master.

Full-duplex communication
By default, the SPI is configured for full-duplex communication. In this configuration, the
shift registers of the master and slave are linked using two unidirectional lines between the
MOSI and the MISO pins. During SPI communication, data is shifted synchronously on the
SCK clock edges provided by the master. The master transmits the data to be sent to the
slave via the MOSI line and receives data from the slave via the MISO line. When the data
frame transfer is complete (all the bits are shifted) the information between the master and
slave is exchanged.
Figure 246. Full-duplex single master/ single slave application

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1. The NSS pins can be used to provide a hardware control flow between master and slave. Optionally, the
pins can be left unused by the peripheral. Then the flow has to be handled internally for both master and
slave. For more details see Section 24.4.5: Slave select (NSS) pin management.

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Serial peripheral interface (SPI)

Half-duplex communication
The SPI can communicate in half-duplex mode by setting the BIDIMODE bit in the
SPIx_CR1 register. In this configuration, one single cross connection line is used to link the
shift registers of the master and slave together. During this communication, the data is
synchronously shifted between the shift registers on the SCK clock edge in the transfer
direction selected reciprocally by both master and slave with the BDIOE bit in their
SPIx_CR1 registers. In this configuration, the master’s MISO pin and the slave’s MOSI pin
are free for other application uses and act as GPIOs.
Figure 247. Half-duplex single master/ single slave application

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1. The NSS pins can be used to provide a hardware control flow between master and slave. Optionally, the
pins can be left unused by the peripheral. Then the flow has to be handled internally for both master and
slave. For more details see Section 24.4.5: Slave select (NSS) pin management.
2. In this configuration, the master’s MISO pin and the slave’s MOSI pin can be used as GPIOs.
3. A critical situation can happen when communication direction is changed not synchronously between two
nodes working at bidirectionnal mode and new transmitter accesses the common data line while former
transmitter still keeps an opposite value on the line (the value depends on SPI configuration and
communication data). Both nodes then fight while providing opposite output levels on the common line
temporary till next node changes its direction settings correspondingly, too. It is suggested to insert a serial
resistance between MISO and MOSI pins at this mode to protect the outputs and limit the current blowing
between them at this situation.

Simplex communications
The SPI can communicate in simplex mode by setting the SPI in transmit-only or in receiveonly using the RXONLY bit in the SPIx_CR2 register. In this configuration, only one line is
used for the transfer between the shift registers of the master and slave. The remaining
MISO and MOSI pins pair is not used for communication and can be used as standard
GPIOs.


Transmit-only mode (RXONLY=0): The configuration settings are the same as for fullduplex. The application has to ignore the information captured on the unused input pin.
This pin can be used as a standard GPIO.



Receive-only mode (RXONLY=1): The application can disable the SPI output function
by setting the RXONLY bit. In slave configuration, the MISO output is disabled and the
pin can be used as a GPIO. The slave continues to receive data from the MOSI pin
while its slave select signal is active (see 24.4.5: Slave select (NSS) pin management).
Received data events appear depending on the data buffer configuration. In the master
configuration, the MOSI output is disabled and the pin can be used as a GPIO. The
clock signal is generated continuously as long as the SPI is enabled. The only way to
stop the clock is to clear the RXONLY bit or the SPE bit and wait until the incoming
pattern from the MISO pin is finished and fills the data buffer structure, depending on its
configuration.

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Figure 248. Simplex single master/single slave application (master in transmit-only/
slave in receive-only mode)

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1. The NSS pins can be used to provide a hardware control flow between master and slave. Optionally, the
pins can be left unused by the peripheral. Then the flow has to be handled internally for both master and
slave. For more details see Section 24.4.5: Slave select (NSS) pin management.
2. An accidental input information is captured at the input of transmitter Rx shift register. All the events
associated with the transmitter receive flow must be ignored in standard transmit only mode (e.g. OVF
flag).
3. In this configuration, both the MISO pins can be used as GPIOs.

Note:

Any simplex communication can be alternatively replaced by a variant of the half-duplex
communication with a constant setting of the transaction direction (bidirectional mode is
enabled while BDIO bit is not changed).

24.4.3

Standard multi-slave communication
In a configuration with two or more independent slaves, the master uses GPIO pins to
manage the chip select lines for each slave (see Figure 249.). The master must select one
of the slaves individually by pulling low the GPIO connected to the slave NSS input. When
this is done, a standard master and dedicated slave communication is established.

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Figure 249. Master and three independent slaves

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1. NSS pin is not used on master side at this configuration. It has to be managed internally (SSM=1, SSI=1) to
prevent any MODF error.
2. As MISO pins of the slaves are connected together, all slaves must have the GPIO configuration of their
MISO pin set as alternate function open-drain (see Section 8.3.7: I/O alternate function input/output on
page 131.

24.4.4

Multi-master communication
Unless SPI bus is not designed for a multi-master capability primarily, the user can use build
in feature which detects a potential conflict between two nodes trying to master the bus at
the same time. For this detection, NSS pin is used configured at hardware input mode.
The connection of more than two SPI nodes working at this mode is impossible as only one
node can apply its output on a common data line at time.
When nodes are non active, both stay at slave mode by default. Once one node wants to
overtake control on the bus, it switches itself into master mode and applies active level on
the slave select input of the other node via dedicated GPIO pin. After the session is

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completed, the active slave select signal is released and the node mastering the bus
temporary returns back to passive slave mode waiting for next session start.
If potentially both nodes raised their mastering request at the same time a bus conflict event
appears (see mode fault MODF event). Then the user can apply some simple arbitration
process (e.g. to postpone next attempt by predefined different time-outs applied at both
nodes).

Figure 250. Multi-master application

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1. The NSS pin is configured at hardware input mode at both nodes. Its active level enables the MISO line
output control as the passive node is configured as a slave.

24.4.5

Slave select (NSS) pin management
In slave mode, the NSS works as a standard “chip select” input and lets the slave
communicate with the master. In master mode, NSS can be used either as output or input.
As an input it can prevent multimaster bus collision, and as an output it can drive a slave
select signal of a single slave.
Hardware or software slave select management can be set using the SSM bit in the
SPIx_CR1 register:

648/779



Software NSS management (SSM = 1): in this configuration, slave select information
is driven internally by the SSI bit value in register SPIx_CR1. The external NSS pin is
free for other application uses.



Hardware NSS management (SSM = 0): in this case, there are two possible
configurations. The configuration used depends on the NSS output configuration
(SSOE bit in register SPIx_CR1).
–

NSS output enable (SSM=0,SSOE = 1): this configuration is only used when the
MCU is set as master. The NSS pin is managed by the hardware. The NSS signal
is driven low as soon as the SPI is enabled in master mode (SPE=1), and is kept
low until the SPI is disabled (SPE =0). A pulse can be generated between
continuous communications if NSS pulse mode is activated (NSSP=1). The SPI
cannot work in multimaster configuration with this NSS setting.

–

NSS output disable (SSM=0, SSOE = 0): if the microcontroller is acting as the
master on the bus, this configuration allows multimaster capability. If the NSS pin
is pulled low in this mode, the SPI enters master mode fault state and the device is
automatically reconfigured in slave mode. In slave mode, the NSS pin works as a
standard “chip select” input and the slave is selected while NSS line is at low level.

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Serial peripheral interface (SPI)
Figure 251. Hardware/software slave select management
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24.4.6

Communication formats
During SPI communication, receive and transmit operations are performed simultaneously.
The serial clock (SCK) synchronizes the shifting and sampling of the information on the data
lines. The communication format depends on the clock phase, the clock polarity and the
data frame format. To be able to communicate together, the master and slaves devices must
follow the same communication format.

Clock phase and polarity controls
Four possible timing relationships may be chosen by software, using the CPOL and CPHA
bits in the SPIx_CR1 register. The CPOL (clock polarity) bit controls the idle state value of
the clock when no data is being transferred. This bit affects both master and slave modes. If
CPOL is reset, the SCK pin has a low-level idle state. If CPOL is set, the SCK pin has a
high-level idle state.
If the CPHA bit is set, the second edge on the SCK pin captures the first data bit transacted
(falling edge if the CPOL bit is reset, rising edge if the CPOL bit is set). Data are latched on
each occurrence of this clock transition type. If the CPHA bit is reset, the first edge on the
SCK pin captures the first data bit transacted (falling edge if the CPOL bit is set, rising edge
if the CPOL bit is reset). Data are latched on each occurrence of this clock transition type.
The combination of CPOL (clock polarity) and CPHA (clock phase) bits selects the data
capture clock edge.

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Figure 252, shows an SPI full-duplex transfer with the four combinations of the CPHA and
CPOL bits.
Note:

Prior to changing the CPOL/CPHA bits the SPI must be disabled by resetting the SPE bit.
The idle state of SCK must correspond to the polarity selected in the SPIx_CR1 register (by
pulling up SCK if CPOL=1 or pulling down SCK if CPOL=0).
Figure 252. Data clock timing diagram
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1. The order of data bits depends on LSBFIRST bit setting.

Data frame format
The SPI shift register can be set up to shift out MSB-first or LSB-first, depending on the
value of the LSBFIRST bit. The data frame size is chosen by using the DS bits. It can be set
from 4-bit up to 16-bit length and the setting applies for both transmission and reception.
Whatever the selected data frame size, read access to the FIFO must be aligned with the
FRXTH level. When the SPIx_DR register is accessed, data frames are always right-aligned
into either a byte (if the data fits into a byte) or a half-word (see Figure 253). During
communication, only bits within the data frame are clocked and transferred.

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Serial peripheral interface (SPI)
Figure 253. Data alignment when data length is not equal to 8-bit or 16-bit
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The minimum data length is 4 bits. If a data length of less than 4 bits is selected, it is forced
to an 8-bit data frame size.

24.4.7

Configuration of SPI
The configuration procedure is almost the same for master and slave. For specific mode
setups, follow the dedicated sections. When a standard communication is to be initialized,
perform these steps:
1.
2.

3.

Write proper GPIO registers: Configure GPIO for MOSI, MISO and SCK pins.
Write to the SPI_CR1 register:
a)

Configure the serial clock baud rate using the BR[2:0] bits (Note: 4).

b)

Configure the CPOL and CPHA bits combination to define one of the four
relationships between the data transfer and the serial clock (CPHA must be
cleared in NSSP mode). (Note: 2 - except the case when CRC is enabled at TI
mode).

c)

Select simplex or half-duplex mode by configuring RXONLY or BIDIMODE and
BIDIOE (RXONLY and BIDIMODE can't be set at the same time).

d)

Configure the LSBFIRST bit to define the frame format (Note: 2).

e)

Configure the CRCL and CRCEN bits if CRC is needed (while SCK clock signal is
at idle state).

f)

Configure SSM and SSI (Notes: 2 & 3).

g)

Configure the MSTR bit (in multimaster NSS configuration, avoid conflict state on
NSS if master is configured to prevent MODF error).

Write to SPI_CR2 register:
a)

Configure the DS[3:0] bits to select the data length for the transfer.

b)

Configure SSOE (Notes: 1 & 2 & 3).

c)

Set the FRF bit if the TI protocol is required (keep NSSP bit cleared in TI mode).

d)

Set the NSSP bit if the NSS pulse mode between two data units is required (keep
CHPA and TI bits cleared in NSSP mode).

e)

Configure the FRXTH bit. The RXFIFO threshold must be aligned to the read
access size for the SPIx_DR register.

f)

Initialize LDMA_TX and LDMA_RX bits if DMA is used in packed mode.

4.

Write to SPI_CRCPR register: Configure the CRC polynomial if needed.

5.

Write proper DMA registers: Configure DMA streams dedicated for SPI Tx and Rx in
DMA registers if the DMA streams are used.

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Note:

RM0360

(1) Step is not required in slave mode.
(2) Step is not required in TI mode.
(3) Step is not required in NSSP mode.
(4) The step is not required in slave mode except slave working at TI mode
For code example refer to the Appendix sections A.14.1: SPI master configuration code
example and A.14.2: SPI slave configuration code example.

24.4.8

Procedure for enabling SPI
It is recommended to enable the SPI slave before the master sends the clock. If not,
undesired data transmission might occur. The data register of the slave must already
contain data to be sent before starting communication with the master (either on the first
edge of the communication clock, or before the end of the ongoing communication if the
clock signal is continuous). The SCK signal must be settled at an idle state level
corresponding to the selected polarity before the SPI slave is enabled.
The master at full-duplex (or in any transmit-only mode) starts to communicate when the
SPI is enabled and TXFIFO is not empty, or with the next write to TXFIFO.
In any master receive only mode (RXONLY=1 or BIDIMODE=1 & BIDIOE=0), master starts
to communicate and the clock starts running immediately after SPI is enabled.
For handling DMA, follow the dedicated section.

24.4.9

Data transmission and reception procedures
RXFIFO and TXFIFO
All SPI data transactions pass through the 32-bit embedded FIFOs. This enables the SPI to
work in a continuous flow, and prevents overruns when the data frame size is short. Each
direction has its own FIFO called TXFIFO and RXFIFO. These FIFOs are used in all SPI
modes except for receiver-only mode (slave or master) with CRC calculation enabled (see
Section 24.4.14: CRC calculation).
The handling of FIFOs depends on the data exchange mode (duplex, simplex), data frame
format (number of bits in the frame), access size performed on the FIFO data registers (8-bit
or 16-bit), and whether or not data packing is used when accessing the FIFOs (see
Section 24.4.13: TI mode).
A read access to the SPIx_DR register returns the oldest value stored in RXFIFO that has
not been read yet. A write access to the SPIx_DR stores the written data in the TXFIFO at
the end of a send queue. The read access must be always aligned with the RXFIFO
threshold configured by the FRXTH bit in SPIx_CR2 register. FTLVL[1:0] and FRLVL[1:0]
bits indicate the current occupancy level of both FIFOs.
A read access to the SPIx_DR register must be managed by the RXNE event. This event is
triggered when data is stored in RXFIFO and the threshold (defined by FRXTH bit) is
reached. When RXNE is cleared, RXFIFO is considered to be empty. In a similar way, write
access of a data frame to be transmitted is managed by the TXE event. This event is
triggered when the TXFIFO level is less than or equal to half of its capacity. Otherwise TXE
is cleared and the TXFIFO is considered as full. In this way, RXFIFO can store up to four
data frames, whereas TXFIFO can only store up to three when the data frame format is not
greater than 8 bits. This difference prevents possible corruption of 3x 8-bit data frames
already stored in the TXFIFO when software tries to write more data in 16-bit mode into

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Serial peripheral interface (SPI)
TXFIFO. Both TXE and RXNE events can be polled or handled by interrupts. See
Figure 255 through Figure 258.
Another way to manage the data exchange is to use DMA (see Section 10.2: DMA main
features).
If the next data is received when the RXFIFO is full, an overrun event occurs (see
description of OVR flag at Section 24.4.10: SPI status flags). An overrun event can be
polled or handled by an interrupt.
The BSY bit being set indicates ongoing transaction of a current data frame. When the clock
signal runs continuously, the BSY flag stays set between data frames at master but
becomes low for a minimum duration of one SPI clock at slave between each data frame
transfer.

Sequence handling
A few data frames can be passed at single sequence to complete a message. When
transmission is enabled, a sequence begins and continues while any data is present in the
TXFIFO of the master. The clock signal is provided continuously by the master until TXFIFO
becomes empty, then it stops waiting for additional data.
In receive-only modes, half-duplex (BIDIMODE=1, BIDIOE=0) or simplex (BIDIMODE=0,
RXONLY=1) the master starts the sequence immediately when both SPI is enabled and
receive-only mode is activated. The clock signal is provided by the master and it does not
stop until either SPI or receive-only mode is disabled by the master. The master receives
data frames continuously up to this moment.
While the master can provide all the transactions in continuous mode (SCK signal is
continuous) it has to respect slave capability to handle data flow and its content at anytime.
When necessary, the master must slow down the communication and provide either a
slower clock or separate frames or data sessions with sufficient delays. Be aware there is no
underflow error signal for master or slave in SPI mode, and data from the slave is always
transacted and processed by the master even if the slave could not prepare it correctly in
time. It is preferable for the slave to use DMA, especially when data frames are shorter and
bus rate is high.
Each sequence must be encased by the NSS pulse in parallel with the multislave system to
select just one of the slaves for communication. In a single slave system it is not necessary
to control the slave with NSS, but it is often better to provide the pulse here too, to
synchronize the slave with the beginning of each data sequence. NSS can be managed by
both software and hardware (see Section 24.4.5: Slave select (NSS) pin management).
When the BSY bit is set it signifies an ongoing data frame transaction. When the dedicated
frame transaction is finished, the RXNE flag is raised. The last bit is just sampled and the
complete data frame is stored in the RXFIFO.

Procedure for disabling the SPI
When SPI is disabled, it is mandatory to follow the disable procedures described in this
paragraph. It is important to do this before the system enters a low-power mode when the
peripheral clock is stopped. Ongoing transactions can be corrupted in this case. In some
modes the disable procedure is the only way to stop continuous communication running.
Master in full-duplex or transmit only mode can finish any transaction when it stops
providing data for transmission. In this case, the clock stops after the last data transaction.
Special care must be taken in packing mode when an odd number of data frames are

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transacted to prevent some dummy byte exchange (refer to Data packing section). Before
the SPI is disabled in these modes, the user must follow standard disable procedure. When
the SPI is disabled at the master transmitter while a frame transaction is ongoing or next
data frame is stored in TXFIFO, the SPI behavior is not guaranteed.
When the master is in any receive only mode, the only way to stop the continuous clock is to
disable the peripheral by SPE=0. This must occur in specific time window within last data
frame transaction just between the sampling time of its first bit and before its last bit transfer
starts (in order to receive a complete number of expected data frames and to prevent any
additional “dummy” data reading after the last valid data frame). Specific procedure must be
followed when disabling SPI in this mode.
Data received but not read remains stored in RXFIFO when the SPI is disabled, and must
be processed the next time the SPI is enabled, before starting a new sequence. To prevent
having unread data, ensure that RXFIFO is empty when disabling the SPI, by using the
correct disabling procedure, or by initializing all the SPI registers with a software reset via
the control of a specific register dedicated to peripheral reset (see the SPIiRST bits in the
RCC_APBiRSTR registers).
Standard disable procedure is based on pulling BSY status together with FTLVL[1:0] to
check if a transmission session is fully completed. This check can be done in specific cases,
too, when it is necessary to identify the end of ongoing transactions, for example:


When NSS signal is managed by software and master has to provide proper end of
NSS pulse for slave, or



When transactions’ streams from DMA or FIFO are completed while the last data frame
or CRC frame transaction is still ongoing in the peripheral bus.

The correct disable procedure is (except when receive only mode is used):
1.

Wait until FTLVL[1:0] = 00 (no more data to transmit).

2.

Wait until BSY=0 (the last data frame is processed).

3.

Disable the SPI (SPE=0).

4.

Read data until FRLVL[1:0] = 00 (read all the received data).

The correct disable procedure for certain receive only modes is:

Note:

1.

Interrupt the receive flow by disabling SPI (SPE=0) in the specific time window while
the last data frame is ongoing.

2.

Wait until BSY=0 (the last data frame is processed).

3.

Read data until FRLVL[1:0] = 00 (read all the received data).

If packing mode is used and an odd number of data frames with a format less than or equal
to 8 bits (fitting into one byte) has to be received, FRXTH must be set when FRLVL[1:0] =
01, in order to generate the RXNE event to read the last odd data frame and to keep good
FIFO pointer alignment.

Data packing
When the data frame size fits into one byte (less than or equal to 8 bits), data packing is
used automatically when any read or write 16-bit access is performed on the SPIx_DR
register. The double data frame pattern is handled in parallel in this case. At first, the SPI
operates using the pattern stored in the LSB of the accessed word, then with the other half
stored in the MSB. Figure 254 provides an example of data packing mode sequence
handling. Two data frames are sent after the single 16-bit access the SPIx_DR register of
the transmitter. This sequence can generate just one RXNE event in the receiver if the

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Serial peripheral interface (SPI)
RXFIFO threshold is set to 16 bits (FRXTH=0). The receiver then has to access both data
frames by a single 16-bit read of SPIx_DR as a response to this single RXNE event. The
RxFIFO threshold setting and the following read access must be always kept aligned at the
receiver side, as data can be lost if it is not in line.
A specific problem appears if an odd number of such “fit into one byte” data frames must be
handled. On the transmitter side, writing the last data frame of any odd sequence with an 8bit access to SPIx_DR is enough. The receiver has to change the Rx_FIFO threshold level
for the last data frame received in the odd sequence of frames in order to generate the
RXNE event.
Figure 254. Packing data in FIFO for transmission and reception
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Communication using DMA (direct memory addressing)
To operate at its maximum speed and to facilitate the data register read/write process
required to avoid overrun, the SPI features a DMA capability, which implements a simple
request/acknowledge protocol.
A DMA access is requested when the TXE or RXNE enable bit in the SPIx_CR2 register is
set. Separate requests must be issued to the Tx and Rx buffers.


In transmission, a DMA request is issued each time TXE is set to 1. The DMA then
writes to the SPIx_DR register.



In reception, a DMA request is issued each time RXNE is set to 1. The DMA then reads
the SPIx_DR register.

See Figure 255 through Figure 258.
When the SPI is used only to transmit data, it is possible to enable only the SPI Tx DMA
channel. In this case, the OVR flag is set because the data received is not read. When the
SPI is used only to receive data, it is possible to enable only the SPI Rx DMA channel.
In transmission mode, when the DMA has written all the data to be transmitted (the TCIF
flag is set in the DMA_ISR register), the BSY flag can be monitored to ensure that the SPI
communication is complete. This is required to avoid corrupting the last transmission before
disabling the SPI or entering the Stop mode. The software must first wait until
FTLVL[1:0]=00 and then until BSY=0.
When starting communication using DMA, to prevent DMA channel management raising
error events, these steps must be followed in order:

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1.

Enable DMA Rx buffer in the RXDMAEN bit in the SPI_CR2 register, if DMA Rx is
used.

2.

Enable DMA streams for Tx and Rx in DMA registers, if the streams are used.

3.

Enable DMA Tx buffer in the TXDMAEN bit in the SPI_CR2 register, if DMA Tx is used.

4.

Enable the SPI by setting the SPE bit.

For code example refer to the Appendix sections A.14.5: SPI master configuration with DMA
code example and A.14.6: SPI slave configuration with DMA code example.
To close communication it is mandatory to follow these steps in order:
1.

Disable DMA streams for Tx and Rx in the DMA registers, if the streams are used.

2.

Disable the SPI by following the SPI disable procedure.

3.

Disable DMA Tx and Rx buffers by clearing the TXDMAEN and RXDMAEN bits in the
SPI_CR2 register, if DMA Tx and/or DMA Rx are used.

Packing with DMA
If the transfers are managed by DMA (TXDMAEN and RXDMAEN set in the SPIx_CR2
register) packing mode is enabled/disabled automatically depending on the PSIZE value
configured for SPI TX and the SPI RX DMA channel. If the DMA channel PSIZE value is
equal to 16-bit and SPI data size is less than or equal to 8-bit, then packing mode is
enabled. The DMA then automatically manages the write operations to the SPIx_DR
register.
If data packing mode is used and the number of data to transfer is not a multiple of two, the
LDMA_TX/LDMA_RX bits must be set. The SPI then considers only one data for the
transmission or reception to serve the last DMA transfer (for more details refer to Data
packing on page 654.)

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Communication diagrams
Some typical timing schemes are explained in this section. These schemes are valid no
matter if the SPI events are handled by polling, interrupts or DMA. For simplicity, the
LSBFIRST=0, CPOL=0 and CPHA=1 setting is used as a common assumption here. No
complete configuration of DMA streams is provided.
The following numbered notes are common for Figure 255 on page 658 through Figure 258
on page 661.
1.

The slave starts to control MISO line as NSS is active and SPI is enabled, and is
disconnected from the line when one of them is released. Sufficient time must be
provided for the slave to prepare data dedicated to the master in advance before its
transaction starts.
At the master, the SPI peripheral takes control at MOSI and SCK signals (occasionally
at NSS signal as well) only if SPI is enabled. If SPI is disabled the SPI peripheral is
disconnected from GPIO logic, so the levels at these lines depends on GPIO setting
exclusively.

2.

At the master, BSY stays active between frames if the communication (clock signal) is
continuous. At the slave, BSY signal always goes down for at least one clock cycle
between data frames.

3.

The TXE signal is cleared only if TXFIFO is full.

4.

The DMA arbitration process starts just after the TXDMAEN bit is set. The TXE
interrupt is generated just after the TXEIE is set. As the TXE signal is at an active level,
data transfers to TxFIFO start, until TxFIFO becomes full or the DMA transfer
completes.

5.

If all the data to be sent can fit into TxFIFO, the DMA Tx TCIF flag can be raised even
before communication on the SPI bus starts. This flag always rises before the SPI
transaction is completed.

6.

The CRC value for a package is calculated continuously frame by frame in the
SPIx_TxCRCR and SPIx_RxCRCR registers. The CRC information is processed after
the entire data package has completed, either automatically by DMA (Tx channel must
be set to the number of data frames to be processed) or by SW (the user must handle
CRCNEXT bit during the last data frame processing). 
While the CRC value calculated in SPIx_TxCRCR is simply sent out by transmitter,
received CRC information is loaded into RxFIFO and then compared with the
SPIx_RxCRCR register content (CRC error flag can be raised here if any difference).
This is why the user must take care to flush this information from the FIFO, either by
software reading out all the stored content of RxFIFO, or by DMA when the proper
number of data frames is preset for Rx channel (number of data frames + number of
CRC frames) (see the settings at the example assumption).

7.

In data packed mode, TxE and RxNE events are paired and each read/write access to
the FIFO is 16 bits wide until the number of data frames are even. If the TxFIFO is ¾
full FTLVL status stays at FIFO full level. That is why the last odd data frame cannot be
stored before the TxFIFO becomes ½ full. This frame is stored into TxFIFO with an 8bit access either by software or automatically by DMA when LDMA_TX control is set.

8.

To receive the last odd data frame in packed mode, the Rx threshold must be changed
to 8-bit when the last data frame is processed, either by software setting FRXTH=1 or
automatically by a DMA internal signal when LDMA_RX is set.

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Figure 255. Master full-duplex communication
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Assumptions for master full-duplex communication example:


Data size > 8 bit

If DMA is used:


Number of Tx frames transacted by DMA is set to 3



Number of Rx frames transacted by DMA is set to 3

See also : Communication diagrams on page 657 for details about common assumptions
and notes.

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Serial peripheral interface (SPI)
Figure 256. Slave full-duplex communication
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Assumptions for slave full-duplex communication example:


Data size > 8 bit

If DMA is used:


Number of Tx frames transacted by DMA is set to 3



Number of Rx frames transacted by DMA is set to 3

See also : Communication diagrams on page 657 for details about common assumptions
and notes.
For code example refer to the Appendix section A.14.3: SPI full duplex communication code
example.

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Figure 257. Master full-duplex communication with CRC
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Assumptions for master full-duplex communication with CRC example:


Data size = 16 bit



CRC enabled

If DMA is used:


Number of Tx frames transacted by DMA is set to 2



Number of Rx frames transacted by DMA is set to 3

See also : Communication diagrams on page 657 for details about common assumptions
and notes.

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Figure 258. Master full-duplex communication in packed mode
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Assumptions for master full-duplex communication in packed mode example:


Data size = 5 bit



Read/write FIFO is performed mostly by 16-bit access



FRXTH=0

If DMA is used:


Number of Tx frames to be transacted by DMA is set to 3



Number of Rx frames to be transacted by DMA is set to 3



PSIZE for both Tx and Rx DMA channel is set to 16-bit



LDMA_TX=1 and LDMA_RX=1

See also : Communication diagrams on page 657 for details about common assumptions
and notes.

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24.4.10

RM0360

SPI status flags
Three status flags are provided for the application to completely monitor the state of the SPI
bus.

Tx buffer empty flag (TXE)
The TXE flag is set when transmission TXFIFO has enough space to store data to send.
TXE flag is linked to the TXFIFO level. The flag goes high and stays high until the TXFIFO
level is lower or equal to 1/2 of the FIFO depth. An interrupt can be generated if the TXEIE
bit in the SPIx_CR2 register is set. The bit is cleared automatically when the TXFIFO level
becomes greater than 1/2.

Rx buffer not empty (RXNE)
The RXNE flag is set depending on the FRXTH bit value in the SPIx_CR2 register:


If FRXTH is set, RXNE goes high and stays high until the RXFIFO level is greater or
equal to 1/4 (8-bit).



If FRXTH is cleared, RXNE goes high and stays high until the RXFIFO level is greater
than or equal to 1/2 (16-bit).

An interrupt can be generated if the RXNEIE bit in the SPIx_CR2 register is set.
The RXNE is cleared by hardware automatically when the above conditions are no longer
true.

Busy flag (BSY)
The BSY flag is set and cleared by hardware (writing to this flag has no effect).
When BSY is set, it indicates that a data transfer is in progress on the SPI (the SPI bus is
busy).
The BSY flag can be used in certain modes to detect the end of a transfer so that the
software can disable the SPI or its peripheral clock before entering a low-power mode which
does not provide a clock for the peripheral. This avoids corrupting the last transfer.
The BSY flag is also useful for preventing write collisions in a multimaster system.
The BSY flag is cleared under any one of the following conditions:

Note:

662/779



When the SPI is correctly disabled



When a fault is detected in Master mode (MODF bit set to 1)



In Master mode, when it finishes a data transmission and no new data is ready to be
sent



In Slave mode, when the BSY flag is set to '0' for at least one SPI clock cycle between
each data transfer.

When the next transmission can be handled immediately by the master (e.g. if the master is
in Receive-only mode or its Transmit FIFO is not empty), communication is continuous and
the BSY flag remains set to '1' between transfers on the master side. Although this is not the
case with a slave, it is recommended to use always the TXE and RXNE flags (instead of the
BSY flags) to handle data transmission or reception operations.

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24.4.11

Serial peripheral interface (SPI)

SPI error flags
An SPI interrupt is generated if one of the following error flags is set and interrupt is enabled
by setting the ERRIE bit.

Overrun flag (OVR)
An overrun condition occurs when data is received by a master or slave and the RXFIFO
has not enough space to store this received data. This can happen if the software or the
DMA did not have enough time to read the previously received data (stored in the RXFIFO)
or when space for data storage is limited e.g. the RXFIFO is not available when CRC is
enabled in receive only mode so in this case the reception buffer is limited into a single data
frame buffer (see Section 24.4.14: CRC calculation).
When an overrun condition occurs, the newly received value does not overwrite the
previous one in the RXFIFO. The newly received value is discarded and all data transmitted
subsequently is lost. Clearing the OVR bit is done by a read access to the SPI_DR register
followed by a read access to the SPI_SR register.

Mode fault (MODF)
Mode fault occurs when the master device has its internal NSS signal (NSS pin in NSS
hardware mode, or SSI bit in NSS software mode) pulled low. This automatically sets the
MODF bit. Master mode fault affects the SPI interface in the following ways:


The MODF bit is set and an SPI interrupt is generated if the ERRIE bit is set.



The SPE bit is cleared. This blocks all output from the device and disables the SPI
interface.



The MSTR bit is cleared, thus forcing the device into slave mode.

Use the following software sequence to clear the MODF bit:
1.

Make a read or write access to the SPIx_SR register while the MODF bit is set.

2.

Then write to the SPIx_CR1 register.

To avoid any multiple slave conflicts in a system comprising several MCUs, the NSS pin
must be pulled high during the MODF bit clearing sequence. The SPE and MSTR bits can
be restored to their original state after this clearing sequence. As a security, hardware does
not allow the SPE and MSTR bits to be set while the MODF bit is set. In a slave device the
MODF bit cannot be set except as the result of a previous multimaster conflict.

CRC error (CRCERR)
This flag is used to verify the validity of the value received when the CRCEN bit in the
SPIx_CR1 register is set. The CRCERR flag in the SPIx_SR register is set if the value
received in the shift register does not match the receiver SPIx_RXCRCR value. The flag is
cleared by the software.

TI mode frame format error (FRE)
A TI mode frame format error is detected when an NSS pulse occurs during an ongoing
communication when the SPI is operating in slave mode and configured to conform to the TI
mode protocol. When this error occurs, the FRE flag is set in the SPIx_SR register. The SPI
is not disabled when an error occurs, the NSS pulse is ignored, and the SPI waits for the
next NSS pulse before starting a new transfer. The data may be corrupted since the error
detection may result in the loss of two data bytes.

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The FRE flag is cleared when SPIx_SR register is read. If the ERRIE bit is set, an interrupt
is generated on the NSS error detection. In this case, the SPI should be disabled because
data consistency is no longer guaranteed and communications should be reinitiated by the
master when the slave SPI is enabled again.

24.4.12

NSS pulse mode
This mode is activated by the NSSP bit in the SPIx_CR2 register and it takes effect only if
the SPI interface is configured as Motorola SPI master (FRF=0) with capture on the first
edge (SPIx_CR1 CPHA = 0, CPOL setting is ignored). When activated, an NSS pulse is
generated between two consecutive data frame transfers when NSS stays at high level for
the duration of one clock period at least. This mode allows the slave to latch data. NSSP
pulse mode is designed for applications with a single master-slave pair.
Figure 259 illustrates NSS pin management when NSSP pulse mode is enabled.
Figure 259. NSSP pulse generation in Motorola SPI master mode
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Similar behavior is encountered when CPOL = 0. In this case the sampling edge is the rising
edge of SCK, and NSS assertion and deassertion refer to this sampling edge.

24.4.13

TI mode
TI protocol in master mode
The SPI interface is compatible with the TI protocol. The FRF bit of the SPIx_CR2 register
can be used to configure the SPI to be compliant with this protocol.
The clock polarity and phase are forced to conform to the TI protocol requirements whatever
the values set in the SPIx_CR1 register. NSS management is also specific to the TI protocol
which makes the configuration of NSS management through the SPIx_CR1 and SPIx_CR2
registers (SSM, SSI, SSOE) impossible in this case.
In slave mode, the SPI baud rate prescaler is used to control the moment when the MISO
pin state changes to HiZ when the current transaction finishes (see Figure 260). Any baud
rate can be used, making it possible to determine this moment with optimal flexibility.
However, the baud rate is generally set to the external master clock baud rate. The delay for
the MISO signal to become HiZ (trelease) depends on internal resynchronization and on the

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Serial peripheral interface (SPI)
baud rate value set in through the BR[2:0] bits in the SPIx_CR1 register. It is given by the
formula:

t baud_rate
t baud_rate
---------------------- + 4  t pclk  t release  --------------------- + 6  t pclk
2
2
If the slave detects a misplaced NSS pulse during a data frame transaction the TIFRE flag is
set.
If the data size is equal to 4-bits or 5-bits, the master in full-duplex mode or transmit-only
mode uses a protocol with one more dummy data bit added after LSB. TI NSS pulse is
generated above this dummy bit clock cycle instead of the LSB in each period.
This feature is not available for Motorola SPI communications (FRF bit set to 0).
Figure 260: TI mode transfer shows the SPI communication waveforms when TI mode is
selected.
Figure 260. TI mode transfer

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069

24.4.14

CRC calculation
Two separate CRC calculators are implemented in order to check the reliability of
transmitted and received data. The SPI offers CRC8 or CRC16 calculation independently of
the frame data length, which can be fixed to 8-bit or 16-bit. For all the other data frame
lengths, no CRC is available.

CRC principle
CRC calculation is enabled by setting the CRCEN bit in the SPIx_CR1 register before the
SPI is enabled (SPE = 1). The CRC value is calculated using an odd programmable
polynomial on each bit. The calculation is processed on the sampling clock edge defined by
the CPHA and CPOL bits in the SPIx_CR1 register. The calculated CRC value is checked
automatically at the end of the data block as well as for transfer managed by CPU or by the
DMA. When a mismatch is detected between the CRC calculated internally on the received
data and the CRC sent by the transmitter, a CRCERR flag is set to indicate a data corruption
error. The right procedure for handling the CRC calculation depends on the SPI
configuration and the chosen transfer management.

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Note:

RM0360

The polynomial value should only be odd. No even values are supported.

CRC transfer managed by CPU
Communication starts and continues normally until the last data frame has to be sent or
received in the SPIx_DR register. Then CRCNEXT bit has to be set in the SPIx_CR1
register to indicate that the CRC frame transaction will follow after the transaction of the
currently processed data frame. The CRCNEXT bit must be set before the end of the last
data frame transaction. CRC calculation is frozen during CRC transaction.
The received CRC is stored in the RXFIFO like a data byte or word. That is why in CRC
mode only, the reception buffer has to be considered as a single 16-bit buffer used to
receive only one data frame at a time.
A CRC-format transaction usually takes one more data frame to communicate at the end of
data sequence. However, when setting an 8-bit data frame checked by 16-bit CRC, two
more frames are necessary to send the complete CRC.
When the last CRC data is received, an automatic check is performed comparing the
received value and the value in the SPIx_RXCRC register. Software has to check the
CRCERR flag in the SPIx_SR register to determine if the data transfers were corrupted or
not. Software clears the CRCERR flag by writing '0' to it.
After the CRC reception, the CRC value is stored in the RXFIFO and must be read in the
SPIx_DR register in order to clear the RXNE flag.

CRC transfer managed by DMA
When SPI communication is enabled with CRC communication and DMA mode, the
transmission and reception of the CRC at the end of communication is automatic (with the
exception of reading CRC data in receive only mode). The CRCNEXT bit does not have to
be handled by the software. The counter for the SPI transmission DMA channel has to be
set to the number of data frames to transmit excluding the CRC frame. On the receiver side,
the received CRC value is handled automatically by DMA at the end of the transaction but
user must take care to flush out received CRC information from RXFIFO as it is always
loaded into it. In full-duplex mode, the counter of the reception DMA channel can be set to
the number of data frames to receive including the CRC, which means, for example, in the
specific case of an 8-bit data frame checked by 16-bit CRC:
DMA_RX = Numb_of_data + 2
In receive only mode, the DMA reception channel counter should contain only the amount of
data transferred, excluding the CRC calculation. Then based on the complete transfer from
DMA, all the CRC values must be read back by software from FIFO as it works as a single
buffer in this mode.
At the end of the data and CRC transfers, the CRCERR flag in the SPIx_SR register is set if
corruption occurred during the transfer.
If packing mode is used, the LDMA_RX bit needs managing if the number of data is odd.

Resetting the SPIx_TXCRC and SPIx_RXCRC values
The SPIx_TXCRC and SPIx_RXCRC values are cleared automatically when new data is
sampled after a CRC phase. This allows the use of DMA circular mode (not available in
receive-only mode) in order to transfer data without any interruption, (several data blocks
covered by intermediate CRC checking phases).

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Serial peripheral interface (SPI)
If the SPI is disabled during a communication the following sequence must be followed:

Note:

1.

Disable the SPI

2.

Clear the CRCEN bit

3.

Enable the CRCEN bit

4.

Enable the SPI

When the SPI is in slave mode, the CRC calculator is sensitive to the SCK slave input clock
as soon as the CRCEN bit is set, and this is the case whatever the value of the SPE bit. In
order to avoid any wrong CRC calculation, the software must enable CRC calculation only
when the clock is stable (in steady state).
When the SPI interface is configured as a slave, the NSS internal signal needs to be kept
low during transaction of the CRC phase once the CRCNEXT signal is released. That is why
the CRC calculation can’t be used at NSS Pulse mode when NSS hardware mode should
be applied at slave normally (see more details at the product errata sheet).
At TI mode, despite the fact that clock phase and clock polarity setting is fixed and
independent on SPIx_CR1 register, the corresponding setting CPOL=0 CPHA=1 has to be
kept at the SPIx_CR1 register anyway if CRC is applied. In addition, the CRC calculation
has to be reset between sessions by SPI disable sequence with re-enable the CRCEN bit
described above at both master and slave side, else CRC calculation can be corrupted at
this specific mode.

24.5

SPI interrupts
During SPI communication an interrupts can be generated by the following events:


Transmit TXFIFO ready to be loaded



Data received in Receive RXFIFO



Master mode fault



Overrun error



TI frame format error



CRC protocol error

Interrupts can be enabled and disabled separately.
Table 95. SPI interrupt requests
Interrupt event

Event flag

Enable Control bit

TXE

TXEIE

Data received in RXFIFO

RXNE

RXNEIE

Master Mode fault event

MODF

Transmit TXFIFO ready to be loaded

Overrun error

OVR

TI frame format error

FRE

CRC protocol error

ERRIE

CRCERR

For code example refer to the Appendix section A.14.4: SPI interrupt code example.

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24.6

RM0360

SPI registers
The peripheral registers can be accessed by half-words (16-bit) or words (32-bit). SPI_DR
in addition by can be accessed by 8-bit access.

24.6.1

SPI control register 1 (SPIx_CR1)
Address offset: 0x00
Reset value: 0x0000

15

14

13

12

11

10

9

8

7

6

BIDI
MODE

BIDI
OE

CRC
EN

CRC
NEXT

CRCL

RX
ONLY

SSM

SSI

LSB
FIRST

SPE

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

5

4

3

BR [2:0]
rw

rw

rw

2

1

0

MSTR

CPOL

CPHA

rw

rw

rw

Bit 15 BIDIMODE: Bidirectional data mode enable. This bit enables half-duplex communication using
common single bidirectional data line. Keep RXONLY bit clear when bidirectional mode is
active.
0: 2-line unidirectional data mode selected
1: 1-line bidirectional data mode selected
Bit 14 BIDIOE: Output enable in bidirectional mode
This bit combined with the BIDIMODE bit selects the direction of transfer in bidirectional mode
0: Output disabled (receive-only mode)
1: Output enabled (transmit-only mode)
Note: In master mode, the MOSI pin is used and in slave mode, the MISO pin is used.
Bit 13 CRCEN: Hardware CRC calculation enable
0: CRC calculation disabled
1: CRC calculation Enabled
Note: This bit should be written only when SPI is disabled (SPE = ‘0’) for correct operation.
Bit 12 CRCNEXT: Transmit CRC next
0: Next transmit value is from Tx buffer
1: Next transmit value is from Tx CRC register
Note: This bit has to be written as soon as the last data is written in the SPIx_DR register.
Bit 11 CRCL: CRC length
This bit is set and cleared by software to select the CRC length.
0: 8-bit CRC length
1: 16-bit CRC length
Note: This bit should be written only when SPI is disabled (SPE = ‘0’) for correct operation.

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Bit 10 RXONLY: Receive only mode enabled.
This bit enables simplex communication using a single unidirectional line to receive data
exclusively. Keep BIDIMODE bit clear when receive only mode is active.This bit is also useful
in a multislave system in which this particular slave is not accessed, the output from the
accessed slave is not corrupted.
0: Full-duplex (Transmit and receive)
1: Output disabled (Receive-only mode)
Bit 9 SSM: Software slave management
When the SSM bit is set, the NSS pin input is replaced with the value from the SSI bit.
0: Software slave management disabled
1: Software slave management enabled
Note: This bit is not used in SPI TI mode.
Bit 8 SSI: Internal slave select
This bit has an effect only when the SSM bit is set. The value of this bit is forced onto the NSS
pin and the I/O value of the NSS pin is ignored.
Note: This bit is not used in SPI TI mode.
Bit 7 LSBFIRST: Frame format
0: data is transmitted / received with the MSB first
1: data is transmitted / received with the LSB first
Note: 1. This bit should not be changed when communication is ongoing.
2. This bit is not used in SPI TI mode.
Bit 6 SPE: SPI enable
0: Peripheral disabled
1: Peripheral enabled
Note: When disabling the SPI, follow the procedure described in Procedure for disabling the
SPI on page 653.
Bits 5:3 BR[2:0]: Baud rate control
000: fPCLK/2
001: fPCLK/4
010: fPCLK/8
011: fPCLK/16
100: fPCLK/32
101: fPCLK/64
110: fPCLK/128
111: fPCLK/256
Note: These bits should not be changed when communication is ongoing.

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Bit 2 MSTR: Master selection
0: Slave configuration
1: Master configuration
Note: This bit should not be changed when communication is ongoing.
Bit1 CPOL: Clock polarity
0: CK to 0 when idle
1: CK to 1 when idle
Note: This bit should not be changed when communication is ongoing.
This bit is not used in SPI TI mode except the case when CRC is applied at TI mode.
Bit 0 CPHA: Clock phase
0: The first clock transition is the first data capture edge
1: The second clock transition is the first data capture edge
Note: This bit should not be changed when communication is ongoing.
This bit is not used in SPI TI mode except the case when CRC is applied at TI mode.

24.6.2

SPI control register 2 (SPIx_CR2)
Address offset: 0x04
Reset value: 0x0700

15

14

13

12

Res.

LDMA
_TX

LDMA
_RX

FRXT
H

rw

rw

rw

11

10

9

8

DS [3:0]
rw

rw

rw

7

6

5

TXEIE RXNEIE ERRIE
rw

rw

rw

rw

4

3

2

FRF

NSSP

SSOE

rw

rw

rw

1

0

TXDMAEN RXDMAEN
rw

rw

Bit 15 Reserved, must be kept at reset value.
Bit 14 LDMA_TX: Last DMA transfer for transmission
This bit is used in data packing mode, to define if the total number of data to transmit by DMA
is odd or even. It has significance only if the TXDMAEN bit in the SPIx_CR2 register is set and
if packing mode is used (data length =< 8-bit and write access to SPIx_DR is 16-bit wide). It
has to be written when the SPI is disabled (SPE = 0 in the SPIx_CR1 register).
0: Number of data to transfer is even
1: Number of data to transfer is odd
Note: Refer to Procedure for disabling the SPI on page 653 if the CRCEN bit is set.
Bit 13 LDMA_RX: Last DMA transfer for reception
This bit is used in data packing mode, to define if the total number of data to receive by DMA is
odd or even. It has significance only if the RXDMAEN bit in the SPIx_CR2 register is set and if
packing mode is used (data length =< 8-bit and write access to SPIx_DR is 16-bit wide). It has
to be written when the SPI is disabled (SPE = 0 in the SPIx_CR1 register).
0: Number of data to transfer is even
1: Number of data to transfer is odd
Note: Refer to Procedure for disabling the SPI on page 653 if the CRCEN bit is set.
Bit 12 FRXTH: FIFO reception threshold
This bit is used to set the threshold of the RXFIFO that triggers an RXNE event
0: RXNE event is generated if the FIFO level is greater than or equal to 1/2 (16-bit)
1: RXNE event is generated if the FIFO level is greater than or equal to 1/4 (8-bit)

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Serial peripheral interface (SPI)

Bits 11:8 DS [3:0]: Data size
These bits configure the data length for SPI transfers:
0000: Not used
0001: Not used
0010: Not used
0011: 4-bit
0100: 5-bit
0101: 6-bit
0110: 7-bit
0111: 8-bit
1000: 9-bit
1001: 10-bit
1010: 11-bit
1011: 12-bit
1100: 13-bit
1101: 14-bit
1110: 15-bit
1111: 16-bit
If software attempts to write one of the “Not used” values, they are forced to the value “0111”(8bit).
Bit 7 TXEIE: Tx buffer empty interrupt enable
0: TXE interrupt masked
1: TXE interrupt not masked. Used to generate an interrupt request when the TXE flag is set.
Bit 6 RXNEIE: RX buffer not empty interrupt enable
0: RXNE interrupt masked
1: RXNE interrupt not masked. Used to generate an interrupt request when the RXNE flag is
set.
Bit 5 ERRIE: Error interrupt enable
This bit controls the generation of an interrupt when an error condition occurs (CRCERR,
OVR, MODF in SPI mode, FRE at TI mode).
0: Error interrupt is masked
1: Error interrupt is enabled
Bit 4 FRF: Frame format
0: SPI Motorola mode
1 SPI TI mode
Note: This bit must be written only when the SPI is disabled (SPE=0).
Bit 3 NSSP: NSS pulse management
This bit is used in master mode only. it allow the SPI to generate an NSS pulse between two
consecutive data when doing continuous transfers. In the case of a single data transfer, it
forces the NSS pin high level after the transfer.
It has no meaning if CPHA = ’1’, or FRF = ’1’.
0: No NSS pulse
1: NSS pulse generated
Note: 1. This bit must be written only when the SPI is disabled (SPE=0).
2. This bit is not used in SPI TI mode.

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Bit 2 SSOE: SS output enable
0: SS output is disabled in master mode and the SPI interface can work in multimaster
configuration
1: SS output is enabled in master mode and when the SPI interface is enabled. The SPI
interface cannot work in a multimaster environment.
Note: This bit is not used in SPI TI mode.
Bit 1 TXDMAEN: Tx buffer DMA enable
When this bit is set, a DMA request is generated whenever the TXE flag is set.
0: Tx buffer DMA disabled
1: Tx buffer DMA enabled
Bit 0 RXDMAEN: Rx buffer DMA enable
When this bit is set, a DMA request is generated whenever the RXNE flag is set.
0: Rx buffer DMA disabled
1: Rx buffer DMA enabled

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Serial peripheral interface (SPI)

24.6.3

SPI status register (SPIx_SR)
Address offset: 0x08
Reset value: 0x0002

15
Res.

14
Res.

13
Res.

12

11

10

9

FTLVL[1:0]

FRLVL[2:0]

r

r

r

r

8

7

6

5

4

3

2

1

0

Res.

Res.

TXE

RXNE

r

r

FRE

BSY

OVR

MODF

CRC
ERR

r

r

r

r

rc_w0

Bits 15:13 Reserved, must be kept at reset value.
Bits 12:11 FTLVL[1:0]: FIFO Transmission Level
These bits are set and cleared by hardware.
00: FIFO empty
01: 1/4 FIFO
10: 1/2 FIFO
11: FIFO full (considered as FULL when the FIFO threshold is greater than 1/2)
Bits 10:9 FRLVL[1:0]: FIFO reception level
These bits are set and cleared by hardware.
00: FIFO empty
01: 1/4 FIFO
10: 1/2 FIFO
11: FIFO full
Note: These bits are not used in SPI receive-only mode while CRC calculation is enabled.
Bit 8 FRE: Frame format error
This flag is used for SPI in TI slave mode. Refer to Section 24.4.11: SPI error flags.
This flag is set by hardware and reset when SPIx_SR is read by software.
0: No frame format error
1: A frame format error occurred
Bit 7 BSY: Busy flag
0: SPI not busy
1: SPI is busy in communication or Tx buffer is not empty
This flag is set and cleared by hardware.
Note: The BSY flag must be used with caution: refer to Section 24.4.10: SPI status flags and
Procedure for disabling the SPI on page 653.
Bit 6 OVR: Overrun flag
0: No overrun occurred
1: Overrun occurred
This flag is set by hardware and reset by a software sequence.
Bit 5 MODF: Mode fault
0: No mode fault occurred
1: Mode fault occurred
This flag is set by hardware and reset by a software sequence. Refer to Section : Mode fault
(MODF) on page 663 for the software sequence.
Bit 4 CRCERR: CRC error flag
0: CRC value received matches the SPIx_RXCRCR value
1: CRC value received does not match the SPIx_RXCRCR value
This flag is set by hardware and cleared by software writing 0.

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Bits 3:2 Reserved, must be kept at reset value.
Bit 1 TXE: Transmit buffer empty
0: Tx buffer not empty
1: Tx buffer empty
Bit 0 RXNE: Receive buffer not empty
0: Rx buffer empty
1: Rx buffer not empty

24.6.4

SPI data register (SPIx_DR)
Address offset: 0x0C
Reset value: 0x0000

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

rw

rw

rw

rw

rw

rw

rw

DR[15:0]
rw

rw

rw

rw

rw

rw

rw

rw

rw

Bits 15:0 DR[15:0]: Data register
Data received or to be transmitted
The data register serves as an interface between the Rx and Tx FIFOs. When the data
register is read, RxFIFO is accessed while the write to data register accesses TxFIFO (See
Section 24.4.9: Data transmission and reception procedures).
Note: Data is always right-aligned. Unused bits are ignored when writing to the register, and
read as zero when the register is read. The Rx threshold setting must always
correspond with the read access currently used.

24.6.5

SPI CRC polynomial register (SPIx_CRCPR)
Address offset: 0x10
Reset value: 0x0007

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

rw

rw

rw

rw

rw

rw

rw

CRCPOLY[15:0]
rw

rw

rw

rw

rw

rw

rw

rw

rw

Bits 15:0 CRCPOLY[15:0]: CRC polynomial register
This register contains the polynomial for the CRC calculation.
The CRC polynomial (0007h) is the reset value of this register. Another polynomial can be
configured as required.
Note: The polynomial value should be odd only. No even value is supported.

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Serial peripheral interface (SPI)

24.6.6

SPI Rx CRC register (SPIx_RXCRCR)
Address offset: 0x14
Reset value: 0x0000

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

r

r

r

r

r

r

r

RxCRC[15:0]
r

r

r

r

r

r

r

r

r

Bits 15:0 RXCRC[15:0]: Rx CRC register
When CRC calculation is enabled, the RxCRC[15:0] bits contain the computed CRC value of
the subsequently received bytes. This register is reset when the CRCEN bit in SPIx_CR1
register is written to 1. The CRC is calculated serially using the polynomial programmed in the
SPIx_CRCPR register.
Only the 8 LSB bits are considered when the CRC frame format is set to be 8-bit length (CRCL
bit in the SPIx_CR1 is cleared). CRC calculation is done based on any CRC8 standard.
The entire 16-bits of this register are considered when a 16-bit CRC frame format is selected
(CRCL bit in the SPIx_CR1 register is set). CRC calculation is done based on any CRC16
standard.
A read to this register when the BSY Flag is set could return an incorrect value.

24.6.7

SPI Tx CRC register (SPIx_TXCRCR)
Address offset: 0x18
Reset value: 0x0000

15

14

13

12

11

10

9

r

r

r

r

r

r

r

8

7

6

5

4

3

2

1

0

r

r

r

r

r

r

r

TxCRC[15:0]
r

r

Bits 15:0 TxCRC[15:0]: Tx CRC register
When CRC calculation is enabled, the TxCRC[7:0] bits contain the computed CRC value of
the subsequently transmitted bytes. This register is reset when the CRCEN bit of SPIx_CR1 is
written to 1. The CRC is calculated serially using the polynomial programmed in the
SPIx_CRCPR register.
Only the 8 LSB bits are considered when the CRC frame format is set to be 8-bit length
(CRCL bit in the SPIx_CR1 is cleared). CRC calculation is done based on any CRC8
standard.
The entire 16-bits of this register are considered when a 16-bit CRC frame format is selected
(CRCL bit in the SPIx_CR1 register is set). CRC calculation is done based on any CRC16
standard.
A read to this register when the BSY flag is set could return an incorrect value.

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SPIx_TXCRCR
Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

SPIx_RXCRCR

Res.

0x14
Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

SPIx_CRCPR

Res.

0x10
Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

SPIx_DR

Res.

0x0C
Reset value

Reset value

Reset value

Reset value

DocID025023 Rev 4
0

0

0

0

FRXTH

0
0

Reset value

0

0

0

0
0

0

0

0

0

0

0

0

0

0
1

0
0

0

0

0

0

0

0

0

0

0

0

0

0

RXDMAEN

0
0
0

0

DR[15:0]
0

CRCPOLY[15:0]
0

RxCRC[15:0]
0

TxCRC[15:0]

0

Refer to Section 2.2.2 on page 37 for the register boundary addresses.
RXNE

SSOE
TXDMAEN

0

TXE

0
Res.

FRF
NSSP

0
Res.

0
CRCERR

0
OVR

1
MODF

ERRIE

0

RXNEIE

1

TXEIE

DS[3:0]

BSY

SSI
LSBFIRST

0
0
0
0
0

0
0
0
0
0
0
1
0

0
0
0
0
0
0
0

0
0
0
1
1
1

0
0
0
0
0
0

0
0
0
0
0
0

0

0

0

0

0
0
0

0

0

0

CPOL

0

CPHA

BR [2:0]
MSTR

SPE

SSM

0

FRE

CRCNEXT

0

CRCL

BIDIOE
CRCEN

0

RXONLY

BIDIMODE

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

0

FRLVL[1:0]

FTLVL[1:0]

LDMA_TX
LDMA_RX

0
Res.

Reset value

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Reset value

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

SPIx_SR

Res.

0x08
SPIx_CR2

Res.

0x04
SPIx_CR1

Res.

0x00

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0

Register

Res.

Offset

Res.

24.6.8

Res.

Serial peripheral interface (SPI)
RM0360

SPI register map
Table 96 shows the SPI register map and reset values.
Table 96. SPI register map and reset values

0
0
0

RM0360

25

Universal serial bus full-speed device interface (USB)

Universal serial bus full-speed device interface (USB)
This section applies to STM32F070x6 and STM32F070xB devices only.

25.1

Introduction
The USB peripheral implements an interface between a full-speed USB 2.0 bus and the
APB bus.
USB suspend/resume are supported which allows to stop the device clocks for low-power
consumption.

25.2

25.3

USB main features


USB specification version 2.0 full-speed compliant



Configurable number of endpoints from 1 to 8



1024 bytes of dedicated packet buffer memory SRAM



Cyclic redundancy check (CRC) generation/checking, Non-return-to-zero Inverted
(NRZI) encoding/decoding and bit-stuffing



Isochronous transfers support



Double-buffered bulk/isochronous endpoint support



USB Suspend/Resume operations



Frame locked clock pulse generation



USB 2.0 Link Power Management support



Battery Charging Specification Revision 1.2 support



USB connect / disconnect capability (controllable embedded pull-up resistor on
USB_DP line)

USB implementation
Table 97 describes the USB implementation in the devices.
Table 97. STM32F0x0 USB implementation
USB

features(1)

STM32F070x6,
STM32F070xB
USB

Number of endpoints

8

Size of dedicated packet buffer memory SRAM
Dedicated packet buffer memory SRAM access scheme

1024 bytes
2 x 16 bits / word

USB 2.0 Link Power Management (LPM) support

X

Battery Charging Detection (BCD) support

X

Embedded pull-up resistor on USB_DP line

X

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1. X= supported

25.4

USB functional description
Figure 261 shows the block diagram of the USB peripheral.
Figure 261. USB peripheral block diagram

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The USB peripheral provides an USB-compliant connection between the host PC and the
function implemented by the microcontroller. Data transfer between the host PC and the
system memory occurs through a dedicated packet buffer memory accessed directly by the
USB peripheral. This dedicated memory size is 1024 bytes, and up to 16 mono-directional
or 8 bidirectional endpoints can be used. The USB peripheral interfaces with the USB host,
detecting token packets, handling data transmission/reception, and processing handshake
packets as required by the USB standard. Transaction formatting is performed by the
hardware, including CRC generation and checking.

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Each endpoint is associated with a buffer description block indicating where the endpointrelated memory area is located, how large it is or how many bytes must be transmitted.
When a token for a valid function/endpoint pair is recognized by the USB peripheral, the
related data transfer (if required and if the endpoint is configured) takes place. The data
buffered by the USB peripheral is loaded in an internal 16-bit register and memory access to
the dedicated buffer is performed. When all the data has been transferred, if needed, the
proper handshake packet over the USB is generated or expected according to the direction
of the transfer.
At the end of the transaction, an endpoint-specific interrupt is generated, reading status
registers and/or using different interrupt response routines. The microcontroller can
determine:


which endpoint has to be served,



which type of transaction took place, if errors occurred (bit stuffing, format, CRC,
protocol, missing ACK, over/underrun, etc.).

Special support is offered to isochronous transfers and high throughput bulk transfers,
implementing a double buffer usage, which allows to always have an available buffer for the
USB peripheral while the microcontroller uses the other one.
The unit can be placed in low-power mode (SUSPEND mode), by writing in the control
register, whenever required. At this time, all static power dissipation is avoided, and the USB
clock can be slowed down or stopped. The detection of activity at the USB inputs, while in
low-power mode, wakes the device up asynchronously. A special interrupt source can be
connected directly to a wakeup line to allow the system to immediately restart the normal
clock generation and/or support direct clock start/stop.

25.4.1

Description of USB blocks
The USB peripheral implements all the features related to USB interfacing, which include
the following blocks:


USB Physical Interface (USB PHY): This block is maintaining the electrical interface to
an external USB host. It contains the differential analog transceiver itself, controllable
embedded pull-up resistor (connected to USB_DP line) and support for Battery
Charging Detection (BCD), multiplexed on same USB_DP and USB_DM lines. The
output enable control signal of the analog transceiver (active low) is provided externally
on USB_NOE. It can be used to drive some activity LED or to provide information about
the actual communication direction to some other circuitry.



Serial Interface Engine (SIE): The functions of this block include: synchronization
pattern recognition, bit-stuffing, CRC generation and checking, PID
verification/generation, and handshake evaluation. It must interface with the USB
transceivers and uses the virtual buffers provided by the packet buffer interface for
local data storage. This unit also generates signals according to USB peripheral
events, such as Start of Frame (SOF), USB_Reset, Data errors etc. and to Endpoint
related events like end of transmission or correct reception of a packet; these signals
are then used to generate interrupts.



Timer: This block generates a start-of-frame locked clock pulse and detects a global
suspend (from the host) when no traffic has been received for 3 ms.



Packet Buffer Interface: This block manages the local memory implementing a set of
buffers in a flexible way, both for transmission and reception. It can choose the proper
buffer according to requests coming from the SIE and locate them in the memory
addresses pointed by the Endpoint registers. It increments the address after each

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exchanged byte until the end of packet, keeping track of the number of exchanged
bytes and preventing the buffer to overrun the maximum capacity.

Note:



Endpoint-Related Registers: Each endpoint has an associated register containing the
endpoint type and its current status. For mono-directional/single-buffer endpoints, a
single register can be used to implement two distinct endpoints. The number of
registers is 8, allowing up to 16 mono-directional/single-buffer or up to 7 double-buffer
endpoints in any combination. For example the USB peripheral can be programmed to
have 4 double buffer endpoints and 8 single-buffer/mono-directional endpoints.



Control Registers: These are the registers containing information about the status of
the whole USB peripheral and used to force some USB events, such as resume and
power-down.



Interrupt Registers: These contain the Interrupt masks and a record of the events. They
can be used to inquire an interrupt reason, the interrupt status or to clear the status of a
pending interrupt.

* Endpoint 0 is always used for control transfer in single-buffer mode.
The USB peripheral is connected to the APB bus through an APB interface, containing the
following blocks:

25.5



Packet Memory: This is the local memory that physically contains the Packet Buffers. It
can be used by the Packet Buffer interface, which creates the data structure and can
be accessed directly by the application software. The size of the Packet Memory is
1024 bytes, structured as512 half-words by 16 bits.



Arbiter: This block accepts memory requests coming from the APB bus and from the
USB interface. It resolves the conflicts by giving priority to APB accesses, while always
reserving half of the memory bandwidth to complete all USB transfers. This time-duplex
scheme implements a virtual dual-port SRAM that allows memory access, while an
USB transaction is happening. Multiword APB transfers of any length are also allowed
by this scheme.



Register Mapper: This block collects the various byte-wide and bit-wide registers of the
USB peripheral in a structured 16-bit wide half-word set addressed by the APB.



APB Wrapper: This provides an interface to the APB for the memory and register. It
also maps the whole USB peripheral in the APB address space.



Interrupt Mapper: This block is used to select how the possible USB events can
generate interrupts and map them to the NVIC.

Programming considerations
In the following sections, the expected interactions between the USB peripheral and the
application program are described, in order to ease application software development.

25.5.1

Generic USB device programming
This part describes the main tasks required of the application software in order to obtain
USB compliant behavior. The actions related to the most general USB events are taken into
account and paragraphs are dedicated to the special cases of double-buffered endpoints
and Isochronous transfers. Apart from system reset, action is always initiated by the USB
peripheral, driven by one of the USB events described below.

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Universal serial bus full-speed device interface (USB)

System and power-on reset
Upon system and power-on reset, the first operation the application software should perform
is to provide all required clock signals to the USB peripheral and subsequently de-assert its
reset signal so to be able to access its registers. The whole initialization sequence is
hereafter described.
As a first step application software needs to activate register macrocell clock and de-assert
macrocell specific reset signal using related control bits provided by device clock
management logic.
After that, the analog part of the device related to the USB transceiver must be switched on
using the PDWN bit in CNTR register, which requires a special handling. This bit is intended
to switch on the internal voltage references that supply the port transceiver. This circuit has
a defined startup time (tSTARTUP specified in the datasheet) during which the behavior of the
USB transceiver is not defined. It is thus necessary to wait this time, after setting the PDWN
bit in the CNTR register, before removing the reset condition on the USB part (by clearing
the FRES bit in the CNTR register). Clearing the ISTR register then removes any spurious
pending interrupt before any other macrocell operation is enabled.
At system reset, the microcontroller must initialize all required registers and the packet
buffer description table, to make the USB peripheral able to properly generate interrupts and
data transfers. All registers not specific to any endpoint must be initialized according to the
needs of application software (choice of enabled interrupts, chosen address of packet
buffers, etc.). Then the process continues as for the USB reset case (see further
paragraph).

USB reset (RESET interrupt)
When this event occurs, the USB peripheral is put in the same conditions it is left by the
system reset after the initialization described in the previous paragraph: communication is
disabled in all endpoint registers (the USB peripheral will not respond to any packet). As a
response to the USB reset event, the USB function must be enabled, having as USB
address 0, implementing only the default control endpoint (endpoint address is 0 too). This
is accomplished by setting the Enable Function (EF) bit of the USB_DADDR register and
initializing the EP0R register and its related packet buffers accordingly. During USB
enumeration process, the host assigns a unique address to this device, which must be
written in the ADD[6:0] bits of the USB_DADDR register, and configures any other
necessary endpoint.
When a RESET interrupt is received, the application software is responsible to enable again
the default endpoint of USB function 0 within 10 ms from the end of reset sequence which
triggered the interrupt.

Structure and usage of packet buffers
Each bidirectional endpoint may receive or transmit data from/to the host. The received data
is stored in a dedicated memory buffer reserved for that endpoint, while another memory
buffer contains the data to be transmitted by the endpoint. Access to this memory is
performed by the packet buffer interface block, which delivers a memory access request
and waits for its acknowledgment. Since the packet buffer memory has to be accessed by
the microcontroller also, an arbitration logic takes care of the access conflicts, using half
APB cycle for microcontroller access and the remaining half for the USB peripheral access.
In this way, both the agents can operate as if the packet memory is a dual-port SRAM,
without being aware of any conflict even when the microcontroller is performing back-to-

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back accesses. The USB peripheral logic uses a dedicated clock. The frequency of this
dedicated clock is fixed by the requirements of the USB standard at 48 MHz, and this can be
different from the clock used for the interface to the APB bus. Different clock configurations
are possible where the APB clock frequency can be higher or lower than the USB peripheral
one.
Note:

Due to USB data rate and packet memory interface requirements, the APB clock must have
a minimum frequency of 10 MHz to avoid data overrun/underrun problems.
Each endpoint is associated with two packet buffers (usually one for transmission and the
other one for reception). Buffers can be placed anywhere inside the packet memory
because their location and size is specified in a buffer description table, which is also
located in the packet memory at the address indicated by the USB_BTABLE register. Each
table entry is associated to an endpoint register and it is composed of four 16-bit half-words
so that table start address must always be aligned to an 8-byte boundary (the lowest three
bits of USB_BTABLE register are always “000”). Buffer descriptor table entries are
described in the Section 25.6.2: Buffer descriptor table. If an endpoint is unidirectional and it
is neither an Isochronous nor a double-buffered bulk, only one packet buffer is required (the
one related to the supported transfer direction). Other table locations related to unsupported
transfer directions or unused endpoints, are available to the user. Isochronous and doublebuffered bulk endpoints have special handling of packet buffers (Refer to Section 25.5.4:
Isochronous transfers and Section 25.5.3: Double-buffered endpoints respectively). The
relationship between buffer description table entries and packet buffer areas is depicted in
Figure 262.
Figure 262. Packet buffer areas with examples of buffer description table locations

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Each packet buffer is used either during reception or transmission starting from the bottom.
The USB peripheral will never change the contents of memory locations adjacent to the
allocated memory buffers; if a packet bigger than the allocated buffer length is received
(buffer overrun condition) the data will be copied to the memory only up to the last available
location.

Endpoint initialization
The first step to initialize an endpoint is to write appropriate values to the
ADDRn_TX/ADDRn_RX registers so that the USB peripheral finds the data to be
transmitted already available and the data to be received can be buffered. The EP_TYPE
bits in the USB_EPnR register must be set according to the endpoint type, eventually using
the EP_KIND bit to enable any special required feature. On the transmit side, the endpoint
must be enabled using the STAT_TX bits in the USB_EPnR register and COUNTn_TX must
be initialized. For reception, STAT_RX bits must be set to enable reception and
COUNTn_RX must be written with the allocated buffer size using the BL_SIZE and
NUM_BLOCK fields. Unidirectional endpoints, except Isochronous and double-buffered bulk
endpoints, need to initialize only bits and registers related to the supported direction. Once
the transmission and/or reception are enabled, register USB_EPnR and locations
ADDRn_TX/ADDRn_RX, COUNTn_TX/COUNTn_RX (respectively), should not be modified
by the application software, as the hardware can change their value on the fly. When the
data transfer operation is completed, notified by a CTR interrupt event, they can be
accessed again to re-enable a new operation.

IN packets (data transmission)
When receiving an IN token packet, if the received address matches a configured and valid
endpoint, the USB peripheral accesses the contents of ADDRn_TX and COUNTn_TX
locations inside the buffer descriptor table entry related to the addressed endpoint. The
content of these locations is stored in its internal 16 bit registers ADDR and COUNT (not
accessible by software). The packet memory is accessed again to read the first byte to be
transmitted (Refer to Structure and usage of packet buffers on page 681) and starts sending
a DATA0 or DATA1 PID according to USB_EPnR bit DTOG_TX. When the PID is
completed, the first byte, read from buffer memory, is loaded into the output shift register to
be transmitted on the USB bus. After the last data byte is transmitted, the computed CRC is
sent. If the addressed endpoint is not valid, a NAK or STALL handshake packet is sent
instead of the data packet, according to STAT_TX bits in the USB_EPnR register.
The ADDR internal register is used as a pointer to the current buffer memory location while
COUNT is used to count the number of remaining bytes to be transmitted. Each half-word
read from the packet buffer memory is transmitted over the USB bus starting from the least
significant byte. Transmission buffer memory is read starting from the address pointed by
ADDRn_TX for COUNTn_TX/2 half-words. If a transmitted packet is composed of an odd
number of bytes, only the lower half of the last half-word accessed will be used.
On receiving the ACK receipt by the host, the USB_EPnR register is updated in the
following way: DTOG_TX bit is toggled, the endpoint is made invalid by setting
STAT_TX=10 (NAK) and bit CTR_TX is set. The application software must first identify the
endpoint, which is requesting microcontroller attention by examining the EP_ID and DIR bits
in the USB_ISTR register. Servicing of the CTR_TX event starts clearing the interrupt bit;
the application software then prepares another buffer full of data to be sent, updates the
COUNTn_TX table location with the number of byte to be transmitted during the next
transfer, and finally sets STAT_TX to ‘11 (VALID) to re-enable transmissions. While the
STAT_TX bits are equal to ‘10 (NAK), any IN request addressed to that endpoint is NAKed,

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indicating a flow control condition: the USB host will retry the transaction until it succeeds. It
is mandatory to execute the sequence of operations in the above mentioned order to avoid
losing the notification of a second IN transaction addressed to the same endpoint
immediately following the one which triggered the CTR interrupt.

OUT and SETUP packets (data reception)
These two tokens are handled by the USB peripheral more or less in the same way; the
differences in the handling of SETUP packets are detailed in the following paragraph about
control transfers. When receiving an OUT/SETUP PID, if the address matches a valid
endpoint, the USB peripheral accesses the contents of the ADDRn_RX and COUNTn_RX
locations inside the buffer descriptor table entry related to the addressed endpoint. The
content of the ADDRn_RX is stored directly in its internal register ADDR. While COUNT is
now reset and the values of BL_SIZE and NUM_BLOCK bit fields, which are read within
COUNTn_RX content are used to initialize BUF_COUNT, an internal 16 bit counter, which is
used to check the buffer overrun condition (all these internal registers are not accessible by
software). Data bytes subsequently received by the USB peripheral are packed in halfwords (the first byte received is stored as least significant byte) and then transferred to the
packet buffer starting from the address contained in the internal ADDR register while
BUF_COUNT is decremented and COUNT is incremented at each byte transfer. When the
end of DATA packet is detected, the correctness of the received CRC is tested and only if no
errors occurred during the reception, an ACK handshake packet is sent back to the
transmitting host.
In case of wrong CRC or other kinds of errors (bit-stuff violations, frame errors, etc.), data
bytes are still copied in the packet memory buffer, at least until the error detection point, but
ACK packet is not sent and the ERR bit in USB_ISTR register is set. However, there is
usually no software action required in this case: the USB peripheral recovers from reception
errors and remains ready for the next transaction to come. If the addressed endpoint is not
valid, a NAK or STALL handshake packet is sent instead of the ACK, according to bits
STAT_RX in the USB_EPnR register and no data is written in the reception memory buffers.
Reception memory buffer locations are written starting from the address contained in the
ADDRn_RX for a number of bytes corresponding to the received data packet length, CRC
included (i.e. data payload length + 2), or up to the last allocated memory location, as
defined by BL_SIZE and NUM_BLOCK, whichever comes first. In this way, the USB
peripheral never writes beyond the end of the allocated reception memory buffer area. If the
length of the data packet payload (actual number of bytes used by the application) is greater
than the allocated buffer, the USB peripheral detects a buffer overrun condition. in this case,
a STALL handshake is sent instead of the usual ACK to notify the problem to the host, no
interrupt is generated and the transaction is considered failed.
When the transaction is completed correctly, by sending the ACK handshake packet, the
internal COUNT register is copied back in the COUNTn_RX location inside the buffer
description table entry, leaving unaffected BL_SIZE and NUM_BLOCK fields, which
normally do not require to be re-written, and the USB_EPnR register is updated in the
following way: DTOG_RX bit is toggled, the endpoint is made invalid by setting STAT_RX =
‘10 (NAK) and bit CTR_RX is set. If the transaction has failed due to errors or buffer overrun
condition, none of the previously listed actions take place. The application software must
first identify the endpoint, which is requesting microcontroller attention by examining the
EP_ID and DIR bits in the USB_ISTR register. The CTR_RX event is serviced by first
determining the transaction type (SETUP bit in the USB_EPnR register); the application
software must clear the interrupt flag bit and get the number of received bytes reading the
COUNTn_RX location inside the buffer description table entry related to the endpoint being

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processed. After the received data is processed, the application software should set the
STAT_RX bits to ‘11 (Valid) in the USB_EPnR, enabling further transactions. While the
STAT_RX bits are equal to ‘10 (NAK), any OUT request addressed to that endpoint is
NAKed, indicating a flow control condition: the USB host will retry the transaction until it
succeeds. It is mandatory to execute the sequence of operations in the above mentioned
order to avoid losing the notification of a second OUT transaction addressed to the same
endpoint following immediately the one which triggered the CTR interrupt.

Control transfers
Control transfers are made of a SETUP transaction, followed by zero or more data stages,
all of the same direction, followed by a status stage (a zero-byte transfer in the opposite
direction). SETUP transactions are handled by control endpoints only and are very similar to
OUT ones (data reception) except that the values of DTOG_TX and DTOG_RX bits of the
addressed endpoint registers are set to 1 and 0 respectively, to initialize the control transfer,
and both STAT_TX and STAT_RX are set to ‘10 (NAK) to let software decide if subsequent
transactions must be IN or OUT depending on the SETUP contents. A control endpoint must
check SETUP bit in the USB_EPnR register at each CTR_RX event to distinguish normal
OUT transactions from SETUP ones. A USB device can determine the number and
direction of data stages by interpreting the data transferred in the SETUP stage, and is
required to STALL the transaction in the case of errors. To do so, at all data stages before
the last, the unused direction should be set to STALL, so that, if the host reverses the
transfer direction too soon, it gets a STALL as a status stage.
While enabling the last data stage, the opposite direction should be set to NAK, so that, if
the host reverses the transfer direction (to perform the status stage) immediately, it is kept
waiting for the completion of the control operation. If the control operation completes
successfully, the software will change NAK to VALID, otherwise to STALL. At the same time,
if the status stage will be an OUT, the STATUS_OUT (EP_KIND in the USB_EPnR register)
bit should be set, so that an error is generated if a status transaction is performed with notzero data. When the status transaction is serviced, the application clears the STATUS_OUT
bit and sets STAT_RX to VALID (to accept a new command) and STAT_TX to NAK (to delay
a possible status stage immediately following the next setup).
Since the USB specification states that a SETUP packet cannot be answered with a
handshake different from ACK, eventually aborting a previously issued command to start
the new one, the USB logic doesn’t allow a control endpoint to answer with a NAK or STALL
packet to a SETUP token received from the host.
When the STAT_RX bits are set to ‘01 (STALL) or ‘10 (NAK) and a SETUP token is
received, the USB accepts the data, performing the required data transfers and sends back
an ACK handshake. If that endpoint has a previously issued CTR_RX request not yet
acknowledged by the application (i.e. CTR_RX bit is still set from a previously completed
reception), the USB discards the SETUP transaction and does not answer with any
handshake packet regardless of its state, simulating a reception error and forcing the host to
send the SETUP token again. This is done to avoid losing the notification of a SETUP
transaction addressed to the same endpoint immediately following the transaction, which
triggered the CTR_RX interrupt.

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Double-buffered endpoints
All different endpoint types defined by the USB standard represent different traffic models,
and describe the typical requirements of different kind of data transfer operations. When
large portions of data are to be transferred between the host PC and the USB function, the
bulk endpoint type is the most suited model. This is because the host schedules bulk
transactions so as to fill all the available bandwidth in the frame, maximizing the actual
transfer rate as long as the USB function is ready to handle a bulk transaction addressed to
it. If the USB function is still busy with the previous transaction when the next one arrives, it
will answer with a NAK handshake and the host PC will issue the same transaction again
until the USB function is ready to handle it, reducing the actual transfer rate due to the
bandwidth occupied by re-transmissions. For this reason, a dedicated feature called
‘double-buffering’ can be used with bulk endpoints.
When ‘double-buffering’ is activated, data toggle sequencing is used to select, which buffer
is to be used by the USB peripheral to perform the required data transfers, using both
‘transmission’ and ‘reception’ packet memory areas to manage buffer swapping on each
successful transaction in order to always have a complete buffer to be used by the
application, while the USB peripheral fills the other one. For example, during an OUT
transaction directed to a ‘reception’ double-buffered bulk endpoint, while one buffer is being
filled with new data coming from the USB host, the other one is available for the
microcontroller software usage (the same would happen with a ‘transmission’ doublebuffered bulk endpoint and an IN transaction).
Since the swapped buffer management requires the usage of all 4 buffer description table
locations hosting the address pointer and the length of the allocated memory buffers, the
USB_EPnR registers used to implement double-buffered bulk endpoints are forced to be
used as unidirectional ones. Therefore, only one STAT bit pair must be set at a value
different from ‘00 (Disabled): STAT_RX if the double-buffered bulk endpoint is enabled for
reception, STAT_TX if the double-buffered bulk endpoint is enabled for transmission. In
case it is required to have double-buffered bulk endpoints enabled both for reception and
transmission, two USB_EPnR registers must be used.
To exploit the double-buffering feature and reach the highest possible transfer rate, the
endpoint flow control structure, described in previous chapters, has to be modified, in order
to switch the endpoint status to NAK only when a buffer conflict occurs between the USB
peripheral and application software, instead of doing it at the end of each successful
transaction. The memory buffer which is currently being used by the USB peripheral is
defined by the DTOG bit related to the endpoint direction: DTOG_RX (bit 14 of USB_EPnR
register) for ‘reception’ double-buffered bulk endpoints or DTOG_TX (bit 6 of USB_EPnR
register) for ‘transmission’ double-buffered bulk endpoints. To implement the new flow
control scheme, the USB peripheral should know which packet buffer is currently in use by
the application software, so to be aware of any conflict. Since in the USB_EPnR register,
there are two DTOG bits but only one is used by USB peripheral for data and buffer
sequencing (due to the unidirectional constraint required by double-buffering feature) the
other one can be used by the application software to show which buffer it is currently using.
This new buffer flag is called SW_BUF. In the following table the correspondence between
USB_EPnR register bits and DTOG/SW_BUF definition is explained, for the cases of
‘transmission’ and ‘reception’ double-buffered bulk endpoints.

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Table 98. Double-buffering buffer flag definition
Buffer flag

‘Transmission’ endpoint

DTOG
SW_BUF

‘Reception’ endpoint

DTOG_TX (USB_EPnR bit 6)

DTOG_RX (USB_EPnR bit 14)

USB_EPnR bit 14

USB_EPnR bit 6

The memory buffer which is currently being used by the USB peripheral is defined by DTOG
buffer flag, while the buffer currently in use by application software is identified by SW_BUF
buffer flag. The relationship between the buffer flag value and the used packet buffer is the
same in both cases, and it is listed in the following table.
Table 99. Bulk double-buffering memory buffers usage
Endpoint
DTOG SW_BUF
Type

Packet buffer used by USB
Peripheral

Packet buffer used by
Application Software

0

1

ADDRn_TX_0 / COUNTn_TX_0 ADDRn_TX_1 / COUNTn_TX_1
Buffer description table locations. Buffer description table locations.

1

0

ADDRn_TX_1 / COUNTn_TX_1
Buffer description table locations

ADDRn_TX_0 / COUNTn_TX_0
Buffer description table locations.

0

0

None (1)

ADDRn_TX_0 / COUNTn_TX_0
Buffer description table locations.

1

1

None (1)

ADDRn_TX_0 / COUNTn_TX_0
Buffer description table locations.

0

1

ADDRn_RX_0 / COUNTn_RX_0 ADDRn_RX_1 / COUNTn_RX_1
Buffer description table locations. Buffer description table locations.

1

0

ADDRn_RX_1 / COUNTn_RX_1 ADDRn_RX_0 / COUNTn_RX_0
Buffer description table locations. Buffer description table locations.

0

0

None (1)

ADDRn_RX_0 / COUNTn_RX_0
Buffer description table locations.

1

1

None (1)

ADDRn_RX_1 / COUNTn_RX_1
Buffer description table locations.

IN

OUT

1. Endpoint in NAK Status.

Double-buffering feature for a bulk endpoint is activated by:


Writing EP_TYPE bit field at ‘00 in its USB_EPnR register, to define the endpoint as a
bulk, and



Setting EP_KIND bit at ‘1 (DBL_BUF), in the same register.

The application software is responsible for DTOG and SW_BUF bits initialization according
to the first buffer to be used; this has to be done considering the special toggle-only property
that these two bits have. The end of the first transaction occurring after having set
DBL_BUF, triggers the special flow control of double-buffered bulk endpoints, which is used
for all other transactions addressed to this endpoint until DBL_BUF remain set. At the end of
each transaction the CTR_RX or CTR_TX bit of the addressed endpoint USB_EPnR
register is set, depending on the enabled direction. At the same time, the affected DTOG bit
in the USB_EPnR register is hardware toggled making the USB peripheral buffer swapping
completely software independent. Unlike common transactions, and the first one after

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DBL_BUF setting, STAT bit pair is not affected by the transaction termination and its value
remains ‘11 (Valid). However, as the token packet of a new transaction is received, the
actual endpoint status will be masked as ‘10 (NAK) when a buffer conflict between the USB
peripheral and the application software is detected (this condition is identified by DTOG and
SW_BUF having the same value, see Table 99 on page 687). The application software
responds to the CTR event notification by clearing the interrupt flag and starting any
required handling of the completed transaction. When the application packet buffer usage is
over, the software toggles the SW_BUF bit, writing ‘1 to it, to notify the USB peripheral about
the availability of that buffer. In this way, the number of NAKed transactions is limited only by
the application elaboration time of a transaction data: if the elaboration time is shorter than
the time required to complete a transaction on the USB bus, no re-transmissions due to flow
control will take place and the actual transfer rate will be limited only by the host PC.
The application software can always override the special flow control implemented for
double-buffered bulk endpoints, writing an explicit status different from ‘11 (Valid) into the
STAT bit pair of the related USB_EPnR register. In this case, the USB peripheral will always
use the programmed endpoint status, regardless of the buffer usage condition.

25.5.4

Isochronous transfers
The USB standard supports full speed peripherals requiring a fixed and accurate data
production/consume frequency, defining this kind of traffic as ‘Isochronous’. Typical
examples of this data are: audio samples, compressed video streams, and in general any
sort of sampled data having strict requirements for the accuracy of delivered frequency.
When an endpoint is defined to be ‘isochronous’ during the enumeration phase, the host
allocates in the frame the required bandwidth and delivers exactly one IN or OUT packet
each frame, depending on endpoint direction. To limit the bandwidth requirements, no retransmission of failed transactions is possible for Isochronous traffic; this leads to the fact
that an isochronous transaction does not have a handshake phase and no ACK packet is
expected or sent after the data packet. For the same reason, Isochronous transfers do not
support data toggle sequencing and always use DATA0 PID to start any data packet.
The Isochronous behavior for an endpoint is selected by setting the EP_TYPE bits at ‘10 in
its USB_EPnR register; since there is no handshake phase the only legal values for the
STAT_RX/STAT_TX bit pairs are ‘00 (Disabled) and ‘11 (Valid), any other value will produce
results not compliant to USB standard. Isochronous endpoints implement double-buffering
to ease application software development, using both ‘transmission’ and ‘reception’ packet
memory areas to manage buffer swapping on each successful transaction in order to have
always a complete buffer to be used by the application, while the USB peripheral fills the
other.
The memory buffer which is currently used by the USB peripheral is defined by the DTOG
bit related to the endpoint direction (DTOG_RX for ‘reception’ isochronous endpoints,
DTOG_TX for ‘transmission’ isochronous endpoints, both in the related USB_EPnR
register) according to Table 100.

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Table 100. Isochronous memory buffers usage
Endpoint
Type

DTOG bit
value

Packet buffer used by the
USB peripheral

Packet buffer used by the
application software

0

ADDRn_TX_0 / COUNTn_TX_0
buffer description table
locations.

ADDRn_TX_1 / COUNTn_TX_1
buffer description table
locations.

1

ADDRn_TX_1 / COUNTn_TX_1
buffer description table
locations.

ADDRn_TX_0 / COUNTn_TX_0
buffer description table
locations.

0

ADDRn_RX_0 / COUNTn_RX_0
buffer description table
locations.

ADDRn_RX_1 / COUNTn_RX_1
buffer description table
locations.

1

ADDRn_RX_1 / COUNTn_RX_1
buffer description table
locations.

ADDRn_RX_0 / COUNTn_RX_0
buffer description table
locations.

IN

OUT

As it happens with double-buffered bulk endpoints, the USB_EPnR registers used to
implement Isochronous endpoints are forced to be used as unidirectional ones. In case it is
required to have Isochronous endpoints enabled both for reception and transmission, two
USB_EPnR registers must be used.
The application software is responsible for the DTOG bit initialization according to the first
buffer to be used; this has to be done considering the special toggle-only property that these
two bits have. At the end of each transaction, the CTR_RX or CTR_TX bit of the addressed
endpoint USB_EPnR register is set, depending on the enabled direction. At the same time,
the affected DTOG bit in the USB_EPnR register is hardware toggled making buffer
swapping completely software independent. STAT bit pair is not affected by transaction
completion; since no flow control is possible for Isochronous transfers due to the lack of
handshake phase, the endpoint remains always ‘11 (Valid). CRC errors or buffer-overrun
conditions occurring during Isochronous OUT transfers are anyway considered as correct
transactions and they always trigger an CTR_RX event. However, CRC errors will anyway
set the ERR bit in the USB_ISTR register to notify the software of the possible data
corruption.

25.5.5

Suspend/Resume events
The USB standard defines a special peripheral state, called SUSPEND, in which the
average current drawn from the USB bus must not be greater than 2.5 mA. This
requirement is of fundamental importance for bus-powered devices, while self-powered
devices are not required to comply to this strict power consumption constraint. In suspend
mode, the host PC sends the notification by not sending any traffic on the USB bus for more
than 3 ms: since a SOF packet must be sent every 1 ms during normal operations, the USB
peripheral detects the lack of 3 consecutive SOF packets as a suspend request from the
host PC and set the SUSP bit to ‘1 in USB_ISTR register, causing an interrupt if enabled.
Once the device is suspended, its normal operation can be restored by a so called
RESUME sequence, which can be started from the host PC or directly from the peripheral
itself, but it is always terminated by the host PC. The suspended USB peripheral must be
anyway able to detect a RESET sequence, reacting to this event as a normal USB reset
event.

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The actual procedure used to suspend the USB peripheral is device dependent since
according to the device composition, different actions may be required to reduce the total
consumption.
A brief description of a typical suspend procedure is provided below, focused on the USBrelated aspects of the application software routine responding to the SUSP notification of
the USB peripheral:

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1.

Set the FSUSP bit in the USB_CNTR register to 1. This action activates the suspend
mode within the USB peripheral. As soon as the suspend mode is activated, the check
on SOF reception is disabled to avoid any further SUSP interrupts being issued while
the USB is suspended.

2.

Remove or reduce any static power consumption in blocks different from the USB
peripheral.

3.

Set LP_MODE bit in USB_CNTR register to 1 to remove static power consumption in
the analog USB transceivers but keeping them able to detect resume activity.

4.

Optionally turn off external oscillator and device PLL to stop any activity inside the
device.

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When an USB event occurs while the device is in SUSPEND mode, the RESUME
procedure must be invoked to restore nominal clocks and regain normal USB behavior.
Particular care must be taken to insure that this process does not take more than 10 ms
when the wakening event is an USB reset sequence (See “Universal Serial Bus
Specification” for more details). The start of a resume or reset sequence, while the USB
peripheral is suspended, clears the LP_MODE bit in USB_CNTR register asynchronously.
Even if this event can trigger an WKUP interrupt if enabled, the use of an interrupt response
routine must be carefully evaluated because of the long latency due to system clock restart;
to have the shorter latency before re-activating the nominal clock it is suggested to put the
resume procedure just after the end of the suspend one, so its code is immediately
executed as soon as the system clock restarts. To prevent ESD discharges or any other kind
of noise from waking-up the system (the exit from suspend mode is an asynchronous
event), a suitable analog filter on data line status is activated during suspend; the filter width
is about 70 ns.
The following is a list of actions a resume procedure should address:
1.

Optionally turn on external oscillator and/or device PLL.

2.

Clear FSUSP bit of USB_CNTR register.

3.

If the resume triggering event has to be identified, bits RXDP and RXDM in the
USB_FNR register can be used according to Table 101, which also lists the intended
software action in all the cases. If required, the end of resume or reset sequence can
be detected monitoring the status of the above mentioned bits by checking when they
reach the “10” configuration, which represent the Idle bus state; moreover at the end of
a reset sequence the RESET bit in USB_ISTR register is set to 1, issuing an interrupt if
enabled, which should be handled as usual.
Table 101. Resume event detection
[RXDP,RXDM] status

Wakeup event

Required resume software action

“00”

Root reset

None

“10”

None (noise on bus)

Go back in Suspend mode

“01”

Root resume

None

“11”

Not allowed (noise on bus) Go back in Suspend mode

A device may require to exit from suspend mode as an answer to particular events not
directly related to the USB protocol (e.g. a mouse movement wakes up the whole system).
In this case, the resume sequence can be started by setting the RESUME bit in the
USB_CNTR register to ‘1 and resetting it to 0 after an interval between 1 ms and 15 ms (this
interval can be timed using ESOF interrupts, occurring with a 1 ms period when the system
clock is running at nominal frequency). Once the RESUME bit is clear, the resume
sequence will be completed by the host PC and its end can be monitored again using the
RXDP and RXDM bits in the USB_FNR register.
Note:

The RESUME bit must be anyway used only after the USB peripheral has been put in
suspend mode, setting the FSUSP bit in USB_CNTR register to 1.

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USB registers
The USB peripheral registers can be divided into the following groups:


Common Registers: Interrupt and Control registers



Endpoint Registers: Endpoint configuration and status



Buffer Descriptor Table: Location of packet memory used to locate data buffers

All register addresses are expressed as offsets with respect to the USB peripheral registers
base address 0x4000 5C00, except the buffer descriptor table locations, which starts at the
address specified by the USB_BTABLE register.
Refer to Section 1.1 on page 33 for a list of abbreviations used in register descriptions.
The peripheral registers can be accessed by half-words (16-bit) or words (32-bit).

25.6.1

Common registers
These registers affect the general behavior of the USB peripheral defining operating mode,
interrupt handling, device address and giving access to the current frame number updated
by the host PC.

USB control register (USB_CNTR)
Address offset: 0x40
Reset value: 0x0003
15

14

13

12

11

10

9

8

CTR
M

PMAOVR
M

ERR
M

WKUP
M

SUSP
M

RESET
M

SOF
M

ESOF
M

rw

rw

rw

rw

rw

rw

rw

rw

7

6

L1REQ Res
M
.
rw

5

4

3

2

1

0

L1
RESUME

RE
SUME

F
SUSP

LP_
MODE

PDW
N

F
RES

rw

rw

rw

rw

rw

rw

Bit 15 CTRM: Correct transfer interrupt mask
0: Correct Transfer (CTR) Interrupt disabled.
1: CTR Interrupt enabled, an interrupt request is generated when the corresponding bit in the
USB_ISTR register is set.
Bit 14 PMAOVRM: Packet memory area over / underrun interrupt mask
0: PMAOVR Interrupt disabled.
1: PMAOVR Interrupt enabled, an interrupt request is generated when the corresponding bit
in the USB_ISTR register is set.
Bit 13 ERRM: Error interrupt mask
0: ERR Interrupt disabled.
1: ERR Interrupt enabled, an interrupt request is generated when the corresponding bit in
the USB_ISTR register is set.
Bit 12 WKUPM: Wakeup interrupt mask
0: WKUP Interrupt disabled.
1: WKUP Interrupt enabled, an interrupt request is generated when the corresponding bit in
the USB_ISTR register is set.
Bit 11 SUSPM: Suspend mode interrupt mask
0: Suspend Mode Request (SUSP) Interrupt disabled.
1: SUSP Interrupt enabled, an interrupt request is generated when the corresponding bit in
the USB_ISTR register is set.

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Bit 10 RESETM: USB reset interrupt mask
0: RESET Interrupt disabled.
1: RESET Interrupt enabled, an interrupt request is generated when the corresponding bit in
the USB_ISTR register is set.
Bit 9 SOFM: Start of frame interrupt mask
0: SOF Interrupt disabled.
1: SOF Interrupt enabled, an interrupt request is generated when the corresponding bit in the
USB_ISTR register is set.
Bit 8 ESOFM: Expected start of frame interrupt mask
0: Expected Start of Frame (ESOF) Interrupt disabled.
1: ESOF Interrupt enabled, an interrupt request is generated when the corresponding bit in
the USB_ISTR register is set.
Bit 7 L1REQM: LPM L1 state request interrupt mask
0: LPM L1 state request (L1REQ) Interrupt disabled.
1: L1REQ Interrupt enabled, an interrupt request is generated when the corresponding bit in
the USB_ISTR register is set.
Bit 6 Reserved.
Bit 5 L1RESUME: LPM L1 Resume request
The microcontroller can set this bit to send a LPM L1 Resume signal to the host. After the
signaling ends, this bit is cleared by hardware.
Bit 4 RESUME: Resume request
The microcontroller can set this bit to send a Resume signal to the host. It must be activated,
according to USB specifications, for no less than 1 ms and no more than 15 ms after which
the Host PC is ready to drive the resume sequence up to its end.
Bit 3 FSUSP: Force suspend
Software must set this bit when the SUSP interrupt is received, which is issued when no
traffic is received by the USB peripheral for 3 ms.
0: No effect.
1: Enter suspend mode. Clocks and static power dissipation in the analog transceiver are left
unaffected. If suspend power consumption is a requirement (bus-powered device), the
application software should set the LP_MODE bit after FSUSP as explained below.

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Bit 2 LP_MODE: Low-power mode
This mode is used when the suspend-mode power constraints require that all static power
dissipation is avoided, except the one required to supply the external pull-up resistor. This
condition should be entered when the application is ready to stop all system clocks, or
reduce their frequency in order to meet the power consumption requirements of the USB
suspend condition. The USB activity during the suspend mode (WKUP event)
asynchronously resets this bit (it can also be reset by software). 
0: No Low-power mode.
1: Enter Low-power mode.
Bit 1 PDWN: Power down
This bit is used to completely switch off all USB-related analog parts if it is required to
completely disable the USB peripheral for any reason. When this bit is set, the USB
peripheral is disconnected from the transceivers and it cannot be used.
0: Exit Power Down.
1: Enter Power down mode.
Bit 0 FRES: Force USB Reset
0: Clear USB reset.
1: Force a reset of the USB peripheral, exactly like a RESET signaling on the USB. The USB
peripheral is held in RESET state until software clears this bit. A “USB-RESET” interrupt is
generated, if enabled.

USB interrupt status register (USB_ISTR)
Address offset: 0x44
Reset value: 0x0000 0000
15

14

13

12

11

10

9

8

7

6

5

4

CTR

PMA
OVR

ERR

WKUP

SUSP

RESET

SOF

ESOF

L1REQ

Res.

Res.

DIR

r

rc_w0

rc_w0

rc_w0

rc_w0

rc_w0

rc_w0

rc_w0

rc_w0

r

3

2

1

0

EP_ID[3:0]
r

r

r

r

This register contains the status of all the interrupt sources allowing application software to
determine, which events caused an interrupt request.
The upper part of this register contains single bits, each of them representing a specific
event. These bits are set by the hardware when the related event occurs; if the
corresponding bit in the USB_CNTR register is set, a generic interrupt request is generated.
The interrupt routine, examining each bit, will perform all necessary actions, and finally it will
clear the serviced bits. If any of them is not cleared, the interrupt is considered to be still
pending, and the interrupt line will be kept high again. If several bits are set simultaneously,
only a single interrupt will be generated.
Endpoint transaction completion can be handled in a different way to reduce interrupt
response latency. The CTR bit is set by the hardware as soon as an endpoint successfully
completes a transaction, generating a generic interrupt request if the corresponding bit in
USB_CNTR is set. An endpoint dedicated interrupt condition is activated independently
from the CTRM bit in the USB_CNTR register. Both interrupt conditions remain active until
software clears the pending bit in the corresponding USB_EPnR register (the CTR bit is
actually a read only bit). For endpoint-related interrupts, the software can use the Direction
of Transaction (DIR) and EP_ID read-only bits to identify, which endpoint made the last
interrupt request and called the corresponding interrupt service routine.

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The user can choose the relative priority of simultaneously pending USB_ISTR events by
specifying the order in which software checks USB_ISTR bits in an interrupt service routine.
Only the bits related to events, which are serviced, are cleared. At the end of the service
routine, another interrupt will be requested, to service the remaining conditions.
To avoid spurious clearing of some bits, it is recommended to clear them with a load
instruction where all bits which must not be altered are written with 1, and all bits to be
cleared are written with ‘0 (these bits can only be cleared by software). Read-modify-write
cycles should be avoided because between the read and the write operations another bit
could be set by the hardware and the next write will clear it before the microprocessor has
the time to serve the event.
The following describes each bit in detail:
Bit 15 CTR: Correct transfer
This bit is set by the hardware to indicate that an endpoint has successfully completed a
transaction; using DIR and EP_ID bits software can determine which endpoint requested the
interrupt. This bit is read-only.
Bit 14 PMAOVR: Packet memory area over / underrun
This bit is set if the microcontroller has not been able to respond in time to an USB memory
request. The USB peripheral handles this event in the following way: During reception an
ACK handshake packet is not sent, during transmission a bit-stuff error is forced on the
transmitted stream; in both cases the host will retry the transaction. The PMAOVR interrupt
should never occur during normal operations. Since the failed transaction is retried by the
host, the application software has the chance to speed-up device operations during this
interrupt handling, to be ready for the next transaction retry; however this does not happen
during Isochronous transfers (no isochronous transaction is anyway retried) leading to a loss
of data in this case. This bit is read/write but only ‘0 can be written and writing ‘1 has no
effect.
Bit 13 ERR: Error
This flag is set whenever one of the errors listed below has occurred: 
NANS: No ANSwer. The timeout for a host response has expired.
CRC: Cyclic Redundancy Check error. One of the received CRCs, either in the token or in
the data, was wrong.
BST: Bit Stuffing error. A bit stuffing error was detected anywhere in the PID, data, and/or
CRC.
FVIO: Framing format Violation. A non-standard frame was received (EOP not in the right
place, wrong token sequence, etc.).
The USB software can usually ignore errors, since the USB peripheral and the PC host
manage retransmission in case of errors in a fully transparent way. This interrupt can be
useful during the software development phase, or to monitor the quality of transmission over
the USB bus, to flag possible problems to the user (e.g. loose connector, too noisy
environment, broken conductor in the USB cable and so on). This bit is read/write but only ‘0
can be written and writing ‘1 has no effect.
Bit 12 WKUP: Wakeup
This bit is set to 1 by the hardware when, during suspend mode, activity is detected that
wakes up the USB peripheral. This event asynchronously clears the LP_MODE bit in the
CTLR register and activates the USB_WAKEUP line, which can be used to notify the rest of
the device (e.g. wakeup unit) about the start of the resume process. This bit is read/write but
only ‘0 can be written and writing ‘1 has no effect.

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Bit 11 SUSP: Suspend mode request
This bit is set by the hardware when no traffic has been received for 3 ms, indicating a
suspend mode request from the USB bus. The suspend condition check is enabled
immediately after any USB reset and it is disabled by the hardware when the suspend mode
is active (FSUSP=1) until the end of resume sequence. This bit is read/write but only ‘0 can
be written and writing ‘1 has no effect.
Bit 10 RESET: USB reset request
Set when the USB peripheral detects an active USB RESET signal at its inputs. The USB
peripheral, in response to a RESET, just resets its internal protocol state machine, generating
an interrupt if RESETM enable bit in the USB_CNTR register is set. Reception and
transmission are disabled until the RESET bit is cleared. All configuration registers do not
reset: the microcontroller must explicitly clear these registers (this is to ensure that the
RESET interrupt can be safely delivered, and any transaction immediately followed by a
RESET can be completed). The function address and endpoint registers are reset by an USB
reset event. 
This bit is read/write but only ‘0 can be written and writing ‘1 has no effect.
Bit 9 SOF: Start of frame
This bit signals the beginning of a new USB frame and it is set when a SOF packet arrives
through the USB bus. The interrupt service routine may monitor the SOF events to have a
1 ms synchronization event to the USB host and to safely read the USB_FNR register which
is updated at the SOF packet reception (this could be useful for isochronous applications).
This bit is read/write but only ‘0 can be written and writing ‘1 has no effect.
Bit 8 ESOF: Expected start of frame
This bit is set by the hardware when an SOF packet is expected but not received. The host
sends an SOF packet each 1 ms, but if the hub does not receive it properly, the Suspend
Timer issues this interrupt. If three consecutive ESOF interrupts are generated (i.e. three
SOF packets are lost) without any traffic occurring in between, a SUSP interrupt is
generated. This bit is set even when the missing SOF packets occur while the Suspend
Timer is not yet locked. This bit is read/write but only ‘0 can be written and writing ‘1 has no
effect.
Bit 7 L1REQ: LPM L1 state request
This bit is set by the hardware when LPM command to enter the L1 state is successfully
received and acknowledged. This bit is read/write but only ‘0 can be written and writing ‘1 has
no effect.

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Bits 6:5 Reserved.
Bit 4 DIR: Direction of transaction
This bit is written by the hardware according to the direction of the successful transaction,
which generated the interrupt request.
If DIR bit=0, CTR_TX bit is set in the USB_EPnR register related to the interrupting endpoint.
The interrupting transaction is of IN type (data transmitted by the USB peripheral to the host
PC).
If DIR bit=1, CTR_RX bit or both CTR_TX/CTR_RX are set in the USB_EPnR register
related to the interrupting endpoint. The interrupting transaction is of OUT type (data
received by the USB peripheral from the host PC) or two pending transactions are waiting to
be processed.
This information can be used by the application software to access the USB_EPnR bits
related to the triggering transaction since it represents the direction having the interrupt
pending. This bit is read-only.
Bits 3:0 EP_ID[3:0]: Endpoint Identifier
These bits are written by the hardware according to the endpoint number, which generated
the interrupt request. If several endpoint transactions are pending, the hardware writes the
endpoint identifier related to the endpoint having the highest priority defined in the following
way: Two endpoint sets are defined, in order of priority: Isochronous and double-buffered
bulk endpoints are considered first and then the other endpoints are examined. If more than
one endpoint from the same set is requesting an interrupt, the EP_ID bits in USB_ISTR
register are assigned according to the lowest requesting endpoint register, EP0R having the
highest priority followed by EP1R and so on. The application software can assign a register
to each endpoint according to this priority scheme, so as to order the concurring endpoint
requests in a suitable way. These bits are read only.

USB frame number register (USB_FNR)
Address offset: 0x48
Reset value: 0x0XXX where X is undefined
15

14

13

RXDP

RXDM

LCK

r

r

r

12

11

10

9

8

7

6

r

r

r

r

r

LSOF[1:0]
r

r

5

4

3

2

1

0

r

r

r

r

r

FN[10:0]
r

Bit 15 RXDP: Receive data + line status
This bit can be used to observe the status of received data plus upstream port data line. It
can be used during end-of-suspend routines to help determining the wakeup event.
Bit 14 RXDM: Receive data - line status
This bit can be used to observe the status of received data minus upstream port data line. It
can be used during end-of-suspend routines to help determining the wakeup event.

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Bit 13 LCK: Locked
This bit is set by the hardware when at least two consecutive SOF packets have been
received after the end of an USB reset condition or after the end of an USB resume
sequence. Once locked, the frame timer remains in this state until an USB reset or USB
suspend event occurs.
Bits 12:11 LSOF[1:0]: Lost SOF
These bits are written by the hardware when an ESOF interrupt is generated, counting the
number of consecutive SOF packets lost. At the reception of an SOF packet, these bits are
cleared.
Bits 10:0 FN[10:0]: Frame number
This bit field contains the 11-bits frame number contained in the last received SOF packet.
The frame number is incremented for every frame sent by the host and it is useful for
Isochronous transfers. This bit field is updated on the generation of an SOF interrupt.

USB device address (USB_DADDR)
Address offset: 0x4C
Reset value: 0x0000
15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

EF

ADD6

ADD5

ADD4

ADD3

ADD2

ADD1

ADD0

rw

rw

rw

rw

rw

rw

rw

rw

Bits 15:8 Reserved
Bit 7 EF: Enable function
This bit is set by the software to enable the USB device. The address of this device is
contained in the following ADD[6:0] bits. If this bit is at ‘0 no transactions are handled,
irrespective of the settings of USB_EPnR registers.
Bits 6:0 ADD[6:0]: Device address
These bits contain the USB function address assigned by the host PC during the
enumeration process. Both this field and the Endpoint Address (EA) field in the associated
USB_EPnR register must match with the information contained in a USB token in order to
handle a transaction to the required endpoint.

Buffer table address (USB_BTABLE)
Address offset: 0x50
Reset value: 0x0000
15

14

13

12

11

10

9

8

7

6

5

4

3

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Bits 15:3 BTABLE[15:3]: Buffer table
These bits contain the start address of the buffer allocation table inside the dedicated packet
memory. This table describes each endpoint buffer location and size and it must be aligned
to an 8 byte boundary (the 3 least significant bits are always ‘0). At the beginning of every
transaction addressed to this device, the USB peripheral reads the element of this table
related to the addressed endpoint, to get its buffer start location and the buffer size (Refer to
Structure and usage of packet buffers on page 681).
Bits 2:0 Reserved, forced by hardware to 0.

LPM control and status register (USB_LPMCSR)
Address offset: 0x54
Reset value: 0x0000
15
Res.

14
Res.

13
Res.

12
Res.

11
Res.

10
Res.

9

8

Res.

7

6

Res.

5

4

3

BESL[3:0]

REM
WAKE

r

r

2

1

0

Res.

LPM
ACK

LPM
EN

rw

rw

Bits 15:8 Reserved.
Bits 7:4 BESL[3:0]: BESL value
These bits contain the BESL value received with last ACKed LPM Token
Bit 3 REMWAKE: bRemoteWake value
This bit contains the bRemoteWake value received with last ACKed LPM Token
Bit 2 Reserved
Bit 1 LPMACK: LPM Token acknowledge enable
0: the valid LPM Token will be NYET.
1: the valid LPM Token will be ACK.
The NYET/ACK will be returned only on a successful LPM transaction:
No errors in both the EXT token and the LPM token (else ERROR)
A valid bLinkState = 0001B (L1) is received (else STALL)
Bit 0 LPMEN: LPM support enable
This bit is set by the software to enable the LPM support within the USB device. If this bit is
at ‘0 no LPM transactions are handled.

Battery charging detector (USB_BCDR)
Address offset: 0x58
Reset value: 0x0000
15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

DPPU

Res.

Res.

Res.

Res.

Res.

Res.

Res.

PS2
DET

SDET

PDET

DC
DET

SDEN

PDEN

DCD
EN

BCD
EN

r

r

r

r

rw

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Bit 15 DPPU: DP pull-up control
This bit is set by software to enable the embedded pull-up on the DP line. Clearing it to ‘0’
can be used to signalize disconnect to the host when needed by the user software.
Bits 14:8 Reserved.
Bit 7 PS2DET: DM pull-up detection status
This bit is active only during PD and gives the result of comparison between DM voltage
level and VLGC threshold. In normal situation, the DM level should be below this threshold. If
it is above, it means that the DM is externally pulled high. This can be caused by connection
to a PS2 port (which pulls-up both DP and DM lines) or to some proprietary charger not
following the BCD specification.
0: Normal port detected (connected to SDP, ACA, CDP or DCP).
1: PS2 port or proprietary charger detected.
Bit 6 SDET: Secondary detection (SD) status
This bit gives the result of SD.
0: CDP detected.
1: DCP detected.
Bit 5 PDET: Primary detection (PD) status
This bit gives the result of PD.
0: no BCD support detected (connected to SDP or proprietary device).
1: BCD support detected (connected to ACA, CDP or DCP).
Bit 4 DCDET: Data contact detection (DCD) status
This bit gives the result of DCD.
0: data lines contact not detected.
1: data lines contact detected.
Bit 3 SDEN: Secondary detection (SD) mode enable
This bit is set by the software to put the BCD into SD mode. Only one detection mode (DCD,
PD, SD or OFF) should be selected to work correctly.
Bit 2 PDEN: Primary detection (PD) mode enable
This bit is set by the software to put the BCD into PD mode. Only one detection mode (DCD,
PD, SD or OFF) should be selected to work correctly.
Bit 1 DCDEN: Data contact detection (DCD) mode enable
This bit is set by the software to put the BCD into DCD mode. Only one detection mode
(DCD, PD, SD or OFF) should be selected to work correctly.
Bit 0 BCDEN: Battery charging detector (BCD) enable
This bit is set by the software to enable the BCD support within the USB device. When
enabled, the USB PHY is fully controlled by BCD and cannot be used for normal
communication. Once the BCD discovery is finished, the BCD should be placed in OFF
mode by clearing this bit to ‘0 in order to allow the normal USB operation.

Endpoint-specific registers
The number of these registers varies according to the number of endpoints that the USB
peripheral is designed to handle. The USB peripheral supports up to 8 bidirectional
endpoints. Each USB device must support a control endpoint whose address (EA bits) must
be set to 0. The USB peripheral behaves in an undefined way if multiple endpoints are
enabled having the same endpoint number value. For each endpoint, an USB_EPnR
register is available to store the endpoint specific information.

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USB endpoint n register (USB_EPnR), n=[0..7]
Address offset: 0x00 to 0x1C
Reset value: 0x0000
15

14

CTR_
RX

DTOG
_RX

rc_w0

t

13

12

STAT_RX[1:0]
t

t

11
SETUP
r

10

9

EP
TYPE[1:0]
rw

rw

8

7

6

EP_
KIND

CTR_
TX

DTOG_
TX

rw

rc_w0

t

5

4

3

STAT_TX[1:0]
t

t

2

1

0

rw

rw

EA[3:0]
rw

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They are also reset when an USB reset is received from the USB bus or forced through bit
FRES in the CTLR register, except the CTR_RX and CTR_TX bits, which are kept
unchanged to avoid missing a correct packet notification immediately followed by an USB
reset event. Each endpoint has its USB_EPnR register where n is the endpoint identifier.
Read-modify-write cycles on these registers should be avoided because between the read
and the write operations some bits could be set by the hardware and the next write would
modify them before the CPU has the time to detect the change. For this purpose, all bits
affected by this problem have an ‘invariant’ value that must be used whenever their
modification is not required. It is recommended to modify these registers with a load
instruction where all the bits, which can be modified only by the hardware, are written with
their ‘invariant’ value.

Bit 15 CTR_RX: Correct Transfer for reception
This bit is set by the hardware when an OUT/SETUP transaction is successfully completed
on this endpoint; the software can only clear this bit. If the CTRM bit in USB_CNTR register
is set accordingly, a generic interrupt condition is generated together with the endpoint
related interrupt condition, which is always activated. The type of occurred transaction, OUT
or SETUP, can be determined from the SETUP bit described below.
A transaction ended with a NAK or STALL handshake does not set this bit, since no data is
actually transferred, as in the case of protocol errors or data toggle mismatches.
This bit is read/write but only ‘0 can be written, writing 1 has no effect.
Bit 14 DTOG_RX: Data Toggle, for reception transfers
If the endpoint is not Isochronous, this bit contains the expected value of the data toggle bit
(0=DATA0, 1=DATA1) for the next data packet to be received. Hardware toggles this bit,
when the ACK handshake is sent to the USB host, following a data packet reception having
a matching data PID value; if the endpoint is defined as a control one, hardware clears this
bit at the reception of a SETUP PID addressed to this endpoint.
If the endpoint is using the double-buffering feature this bit is used to support packet buffer
swapping too (Refer to Section 25.5.3: Double-buffered endpoints).
If the endpoint is Isochronous, this bit is used only to support packet buffer swapping since
no data toggling is used for this sort of endpoints and only DATA0 packet are transmitted
(Refer to Section 25.5.4: Isochronous transfers). Hardware toggles this bit just after the end
of data packet reception, since no handshake is used for isochronous transfers.
This bit can also be toggled by the software to initialize its value (mandatory when the
endpoint is not a control one) or to force specific data toggle/packet buffer usage. When the
application software writes ‘0, the value of DTOG_RX remains unchanged, while writing ‘1
makes the bit value toggle. This bit is read/write but it can be only toggled by writing 1.

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Bits 13:12 STAT_RX [1:0]: Status bits, for reception transfers
These bits contain information about the endpoint status, which are listed in Table 102:
Reception status encoding on page 703.These bits can be toggled by software to initialize
their value. When the application software writes ‘0, the value remains unchanged, while
writing ‘1 makes the bit value toggle. Hardware sets the STAT_RX bits to NAK when a
correct transfer has occurred (CTR_RX=1) corresponding to a OUT or SETUP (control only)
transaction addressed to this endpoint, so the software has the time to elaborate the
received data before it acknowledge a new transaction
Double-buffered bulk endpoints implement a special transaction flow control, which control
the status based upon buffer availability condition (Refer to Section 25.5.3: Double-buffered
endpoints).
If the endpoint is defined as Isochronous, its status can be only “VALID” or “DISABLED”, so
that the hardware cannot change the status of the endpoint after a successful transaction. If
the software sets the STAT_RX bits to ‘STALL’ or ‘NAK’ for an Isochronous endpoint, the
USB peripheral behavior is not defined. These bits are read/write but they can be only
toggled by writing ‘1.
Bit 11 SETUP: Setup transaction completed
This bit is read-only and it is set by the hardware when the last completed transaction is a
SETUP. This bit changes its value only for control endpoints. It must be examined, in the
case of a successful receive transaction (CTR_RX event), to determine the type of
transaction occurred. To protect the interrupt service routine from the changes in SETUP
bits due to next incoming tokens, this bit is kept frozen while CTR_RX bit is at 1; its state
changes when CTR_RX is at 0. This bit is read-only.
Bits 10:9 EP_TYPE[1:0]: Endpoint type
These bits configure the behavior of this endpoint as described in Table 103: Endpoint type
encoding on page 704. Endpoint 0 must always be a control endpoint and each USB
function must have at least one control endpoint which has address 0, but there may be
other control endpoints if required. Only control endpoints handle SETUP transactions,
which are ignored by endpoints of other kinds. SETUP transactions cannot be answered
with NAK or STALL. If a control endpoint is defined as NAK, the USB peripheral will not
answer, simulating a receive error, in the receive direction when a SETUP transaction is
received. If the control endpoint is defined as STALL in the receive direction, then the
SETUP packet will be accepted anyway, transferring data and issuing the CTR interrupt.
The reception of OUT transactions is handled in the normal way, even if the endpoint is a
control one.
Bulk and interrupt endpoints have very similar behavior and they differ only in the special
feature available using the EP_KIND configuration bit.
The usage of Isochronous endpoints is explained in Section 25.5.4: Isochronous transfers
Bit 8 EP_KIND: Endpoint kind
The meaning of this bit depends on the endpoint type configured by the EP_TYPE bits.
Table 104 summarizes the different meanings.
DBL_BUF: This bit is set by the software to enable the double-buffering feature for this bulk
endpoint. The usage of double-buffered bulk endpoints is explained in Section 25.5.3:
Double-buffered endpoints.
STATUS_OUT: This bit is set by the software to indicate that a status out transaction is
expected: in this case all OUT transactions containing more than zero data bytes are
answered ‘STALL’ instead of ‘ACK’. This bit may be used to improve the robustness of the
application to protocol errors during control transfers and its usage is intended for control
endpoints only. When STATUS_OUT is reset, OUT transactions can have any number of
bytes, as required.

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Bit 7 CTR_TX: Correct Transfer for transmission
This bit is set by the hardware when an IN transaction is successfully completed on this
endpoint; the software can only clear this bit. If the CTRM bit in the USB_CNTR register is
set accordingly, a generic interrupt condition is generated together with the endpoint related
interrupt condition, which is always activated.
A transaction ended with a NAK or STALL handshake does not set this bit, since no data is
actually transferred, as in the case of protocol errors or data toggle mismatches.
This bit is read/write but only ‘0 can be written.
Bit 6 DTOG_TX: Data Toggle, for transmission transfers
If the endpoint is non-isochronous, this bit contains the required value of the data toggle bit
(0=DATA0, 1=DATA1) for the next data packet to be transmitted. Hardware toggles this bit
when the ACK handshake is received from the USB host, following a data packet
transmission. If the endpoint is defined as a control one, hardware sets this bit to 1 at the
reception of a SETUP PID addressed to this endpoint.
If the endpoint is using the double buffer feature, this bit is used to support packet buffer
swapping too (Refer to Section 25.5.3: Double-buffered endpoints)
If the endpoint is Isochronous, this bit is used to support packet buffer swapping since no
data toggling is used for this sort of endpoints and only DATA0 packet are transmitted (Refer
to Section 25.5.4: Isochronous transfers). Hardware toggles this bit just after the end of data
packet transmission, since no handshake is used for Isochronous transfers.
This bit can also be toggled by the software to initialize its value (mandatory when the
endpoint is not a control one) or to force a specific data toggle/packet buffer usage. When
the application software writes ‘0, the value of DTOG_TX remains unchanged, while writing
‘1 makes the bit value toggle. This bit is read/write but it can only be toggled by writing 1.
Bits 5:4 STAT_TX [1:0]: Status bits, for transmission transfers
These bits contain the information about the endpoint status, listed in Table 105. These bits
can be toggled by the software to initialize their value. When the application software writes
‘0, the value remains unchanged, while writing ‘1 makes the bit value toggle. Hardware sets
the STAT_TX bits to NAK, when a correct transfer has occurred (CTR_TX=1) corresponding
to a IN or SETUP (control only) transaction addressed to this endpoint. It then waits for the
software to prepare the next set of data to be transmitted.
Double-buffered bulk endpoints implement a special transaction flow control, which controls
the status based on buffer availability condition (Refer to Section 25.5.3: Double-buffered
endpoints).
If the endpoint is defined as Isochronous, its status can only be “VALID” or “DISABLED”.
Therefore, the hardware cannot change the status of the endpoint after a successful
transaction. If the software sets the STAT_TX bits to ‘STALL’ or ‘NAK’ for an Isochronous
endpoint, the USB peripheral behavior is not defined. These bits are read/write but they can
be only toggled by writing ‘1.
Bits 3:0 EA[3:0]: Endpoint address
Software must write in this field the 4-bit address used to identify the transactions directed to
this endpoint. A value must be written before enabling the corresponding endpoint.

Table 102. Reception status encoding
STAT_RX[1:0]

Meaning

00

DISABLED: all reception requests addressed to this endpoint are ignored.

01

STALL: the endpoint is stalled and all reception requests result in a STALL
handshake.

10

NAK: the endpoint is naked and all reception requests result in a NAK handshake.

11

VALID: this endpoint is enabled for reception.

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Table 103. Endpoint type encoding
EP_TYPE[1:0]

Meaning

00

BULK

01

CONTROL

10

ISO

11

INTERRUPT

Table 104. Endpoint kind meaning
EP_TYPE[1:0]

EP_KIND meaning

00

BULK

DBL_BUF

01

CONTROL

STATUS_OUT

10

ISO

Not used

11

INTERRUPT

Not used

Table 105. Transmission status encoding
STAT_TX[1:0]

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Meaning

00

DISABLED: all transmission requests addressed to this endpoint are ignored.

01

STALL: the endpoint is stalled and all transmission requests result in a STALL
handshake.

10

NAK: the endpoint is naked and all transmission requests result in a NAK
handshake.

11

VALID: this endpoint is enabled for transmission.

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25.6.2

Buffer descriptor table
Although the buffer descriptor table is located inside the packet buffer memory, its entries
can be considered as additional registers used to configure the location and size of the
packet buffers used to exchange data between the USB macro cell and the device.
The first packet memory location is located at 0x4000 6000. The buffer descriptor table
entry associated with the USB_EPnR registers is described below. The packet memory
should be accessed only by byte (8-bit) or half-word (16-bit) accesses. Word (32-bit)
accesses are not allowed.
A thorough explanation of packet buffers and the buffer descriptor table usage can be found
in Structure and usage of packet buffers on page 681.

Transmission buffer address n (USB_ADDRn_TX)
Address offset: [USB_BTABLE] + n*8
Note:

In case of double-buffered or isochronous endpoints in the IN direction, this address location
is referred to as USB_ADDRn_TX_0.
In case of double-buffered or isochronous endpoints in the OUT direction, this address
location is used for USB_ADDRn_RX_0.

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

ADDRn_TX[15:1]
rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

-

Bits 15:1 ADDRn_TX[15:1]: Transmission buffer address
These bits point to the starting address of the packet buffer containing data to be transmitted
by the endpoint associated with the USB_EPnR register at the next IN token addressed to it.
Bit 0 Must always be written as ‘0 since packet memory is half-word wide and all packet buffers
must be half-word aligned.

Transmission byte count n (USB_COUNTn_TX)
Address offset: [USB_BTABLE] + n*8 + 2
Note:

In case of double-buffered or isochronous endpoints in the IN direction, this address location
is referred to as USB_COUNTn_TX_0.
In case of double-buffered or isochronous endpoints in the OUT direction, this address
location is used for USB_COUNTn_RX_0.

15

14

13

12

11

10

Res.

Res.

Res.

Res.

Res.

Res.

9

8

7

6

rw

rw

rw

rw

5

4

3

2

1

0

rw

rw

rw

rw

COUNTn_TX[9:0]

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Bits 15:10 These bits are not used since packet size is limited by USB specifications to 1023 bytes. Their
value is not considered by the USB peripheral.
Bits 9:0 COUNTn_TX[9:0]: Transmission byte count
These bits contain the number of bytes to be transmitted by the endpoint associated with the
USB_EPnR register at the next IN token addressed to it.

Reception buffer address n (USB_ADDRn_RX)
Address offset: [USB_BTABLE] + n*8 + 4
Note:

In case of double-buffered or isochronous endpoints in the OUT direction, this address
location is referred to as USB_ADDRn_RX_1.
In case of double-buffered or isochronous endpoints in the IN direction, this address location
is used for USB_ADDRn_TX_1.

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

ADDRn_RX[15:1]
rw

rw

rw

rw

rw

rw

rw

rw

-

rw

rw

rw

rw

rw

rw

rw

-

Bits 15:1 ADDRn_RX[15:1]: Reception buffer address
These bits point to the starting address of the packet buffer, which will contain the data
received by the endpoint associated with the USB_EPnR register at the next OUT/SETUP
token addressed to it.
Bit 0 This bit must always be written as ‘0 since packet memory is half-word wide and all packet
buffers must be half-word aligned.

Reception byte count n (USB_COUNTn_RX)
Address offset: [USB_BTABLE] + n*8 + 6
Note:

In case of double-buffered or isochronous endpoints in the OUT direction, this address
location is referred to as USB_COUNTn_RX_1.
In case of double-buffered or isochronous endpoints in the IN direction, this address location
is used for USB_COUNTn_TX_1.

15

14

BLSIZE
rw

13

12

11

10

9

8

7

6

NUM_BLOCK[4:0]
rw

rw

rw

rw

5

4

3

2

1

0

r

r

r

r

COUNTn_RX[9:0]
rw

r

r

r

r

r

r

This table location is used to store two different values, both required during packet
reception. The most significant bits contains the definition of allocated buffer size, to allow
buffer overflow detection, while the least significant part of this location is written back by the
USB peripheral at the end of reception to give the actual number of received bytes. Due to
the restrictions on the number of available bits, buffer size is represented using the number
of allocated memory blocks, where block size can be selected to choose the trade-off
between fine-granularity/small-buffer and coarse-granularity/large-buffer. The size of
allocated buffer is a part of the endpoint descriptor and it is normally defined during the

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enumeration process according to its maxPacketSize parameter value (See “Universal
Serial Bus Specification”).
Bit 15 BL_SIZE: Block size
This bit selects the size of memory block used to define the allocated buffer area.
–
If BL_SIZE=0, the memory block is 2-byte large, which is the minimum block
allowed in a half-word wide memory. With this block size the allocated buffer size
ranges from 2 to 62 bytes.
–
If BL_SIZE=1, the memory block is 32-byte large, which allows to reach the
maximum packet length defined by USB specifications. With this block size the
allocated buffer size theoretically ranges from 32 to 1024 bytes, which is the longest
packet size allowed by USB standard specifications. However, the applicable size is
limited by the available buffer memory.
Bits 14:10 NUM_BLOCK[4:0]: Number of blocks
These bits define the number of memory blocks allocated to this packet buffer. The actual
amount of allocated memory depends on the BL_SIZE value as illustrated in Table 106.
Bits 9:0 COUNTn_RX[9:0]: Reception byte count
These bits contain the number of bytes received by the endpoint associated with the
USB_EPnR register during the last OUT/SETUP transaction addressed to it.

Table 106. Definition of allocated buffer memory
Value of
NUM_BLOCK[4:0]

Memory allocated
when BL_SIZE=0

Memory allocated
when BL_SIZE=1

0 (‘00000)

Not allowed

32 bytes

1 (‘00001)

2 bytes

64 bytes

2 (‘00010)

4 bytes

96 bytes

3 (‘00011)

6 bytes

128 bytes

...

...

...

14 (‘01110)

28 bytes

480 bytes

15 (‘01111)

30 bytes

512 bytes

16 (‘10000)

32 bytes

544 bytes

...

...

...

29 (‘11101)

58 bytes

960 bytes

30 (‘11110)

60 bytes

992 bytes

31 (‘11111)

62 bytes

N/A

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USB_DADDR

CTR

PMAOVR

ERR

0

0

0

USB_FNR

Reset value

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RXDM

LCK

0

0

0

0

0

x

x

x

x

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Reset value
EP_KIND
CTR_TX
DTOG_TX

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

Res.
L1RESUME
RESUME
FSUSP
LPMODE
PDWN
FRES

0

0

0

1

1

STAT_
RX
[1:0]
0
0

0

0

0

0
0

DTOG_RX

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

SETUP

EP_KIND
CTR_TX
DTOG_TX

SETUP

DTOG_TX

DTOG_TX

DTOG_TX

DTOG_TX

DTOG_TX

CTR_RX

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

CTR_TX

0

EP_KIND

SETUP

CTR_TX

0

EP_KIND
CTR_TX

0

EP_KIND
CTR_TX

0

EP_KIND

CTR_TX

0
EP_KIND

DTOG_TX

0

CTR_TX

0

EP_KIND

0

0
0
0

EP
TYPE
[1:0]
0
0
0
0

EP
TYPE
[1:0]
0
0
0
0

EP
TYPE
[1:0]
0
0
0
0

EP
TYPE
[1:0]
0
0
0
0

EP
TYPE
[1:0]

0
0
0
0

EP
TYPE
[1:0]

0
0
0
0

EP
TYPE
[1:0]

0

0

0

0

EF

LSOF
[1:0]

0

0

0

0

x

0

0

0

0

0

0

0

0

x

0

DIR

STAT_
RX
[1:0]

0

0

Res.

0
0

0

0

Res.

Reserved

L1REQM

STAT_
RX
[1:0]

0

EP
TYPE
[1:0]

L1REQ

0
0

SOFM

0

0

ESOFM

STAT_
RX
[1:0]

SOF

0

0

ESOF

STAT_
RX
[1:0]
SETUP

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

STAT_
RX
[1:0]

SETUP

0

0

SETUP

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

DTOG_RX

USB_EP3R
Res.

CTR_RX
0

STAT_
RX
[1:0]

SETUP

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

DTOG_RX

DTOG_RX

USB_EP4R
Res.

CTR_RX

0

Res.

USB_EP2R
0

0

SETUP

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

CTR_RX

USB_EP5R
Res.

0

Res.

Res.

USB_EP1R
0

SUSPM

0

SUSP

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

0

Res.

0

Res.

0

Res.

Reset value

Res.

0

Res.

0

RESETM

WKUPM

0

WKUP

USB_EP6R
Res.

DTOG_RX

0

Res.

CTR_RX

DTOG_RX

DTOG_RX

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

0

Res.

Reset value

Res.

Reset value

Res.

0

Res.

Reset value
STAT_
RX
[1:0]

RESET

ERRM

USB_EP7R
DTOG_RX

PMAOVRM
0

Res.

0

Res.

Reset value

Res.

CTR_RX

CTR_RX

0

Res.

Reset value

Res.

Reset value

CTR_RX

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

CTRM

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Reset value

RXDP

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Reset value

Res.

Res.

Res.

Res.

Reset value

Res.

0x200x3F

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

0x48

USB_ISTR

Res.

0x44
USB_CNTR

Res.

0x40

Res.

0x1C

Res.

0x18

Res.

0x14

Res.

0x10

Res.

0x0C

Res.

0x08

Res.

0x04
USB_EP0R

Res.

0x00

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0

Register

Res.

Offset

Res.

25.6.3

Res.

Universal serial bus full-speed device interface (USB)
RM0360

USB register map

The table below provides the USB register map and reset values.
Table 107. USB register map and reset values

STAT_
TX
[1:0]
0

0

0

0

0

0

0

0

x

0

EA[3:0]

0

STAT_
TX
[1:0]
0

STAT_
TX
[1:0]

STAT_
TX
[1:0]

0

STAT_
TX
[1:0]

0

0

STAT_
TX
[1:0]
0

STAT_
TX
[1:0]

STAT_
TX
[1:0]
0

FN[10:0]

ADD[6:0]

0

0

0

0

x

x

x

x

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

EA[3:0]
0

EA[3:0]
0

EA[3:0]
0

EA[3:0]
0

EA[3:0]
0

EA[3:0]
0

EA[3:0]

EP_ID[3:0]

0x58
USB_BCDR

Reset value

DocID025023 Rev 4

0
0
0

Reset value

0

Res.
Res.
Res.
Res.
Res.
Res.
Res.

0
0
0
0

BESL[3:0]

0
0
0

Res.

0

Res.

0

LPMEN

0
0
0

BCDEN

0

Res.

0

Res.

0

LPMACK

0

DCDEN

REMWAKE

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

BTABLE[15:3]

PDEN

0
SDEN

0

PDET

0

DCDET

0

SDET

0

PS2DET

Res.

Res.

Res.

Res.

Res.

Res.

Res.

0

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Reset value

DPPU

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

USB_LPMCSR

Res.

0x54
USB_BTABLE

Res.

0x50

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0

Register

Res.

Offset

Res.

RM0360
Universal serial bus full-speed device interface (USB)

Table 107. USB register map and reset values (continued)

0
0
0

Refer to Section 2.2.2 on page 37 for the register boundary addresses.

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26

Debug support (DBG)

26.1

Overview
The STM32F0x0 devices are built around a ARM® Cortex®-M0 core which contains
hardware extensions for advanced debugging features. The debug extensions allow the
core to be stopped either on a given instruction fetch (breakpoint) or data access
(watchpoint). When stopped, the core’s internal state and the system’s external state may
be examined. Once examination is complete, the core and the system may be restored and
program execution resumed.
The debug features are used by the debugger host when connecting to and debugging the
STM32F0x0 MCUs.
One interface for debug is available:


Serial wire
Figure 263. Block diagram of STM32F0x0 MCU and ARM® Cortex®-M0-level debug
support

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&RUWH[0GHEXJVXSSRUW

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&RUH

'HEXJ$3

%ULGJH

6:',2
6:&/.


'%*0&8

6:'3
'HEXJ$3



19,&

':7

%38

069

1. The debug features embedded in the ARM® Cortex®-M0 core are a subset of the ARM CoreSight Design
Kit.

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Debug support (DBG)
The ARM ARM® Cortex®-M0 core provides integrated on-chip debug support. It is
comprised of:


SW-DP: Serial wire



BPU: Break point unit



DWT: Data watchpoint trigger

It also includes debug features dedicated to the STM32F0x0:


Flexible debug pinout assignment



MCU debug box (support for low-power modes, control over peripheral clocks, etc.)

Note:

For further information on debug functionality supported by the ARM ARM® Cortex®-M0
core, refer to the ARM® Cortex®-M0 Technical Reference Manual (see Section 26.2:
Reference ARM documentation).

26.2

Reference ARM documentation

26.3



ARM® Cortex®-M0 Technical Reference Manual (TRM)
It is available from:
http://infocenter.arm.com



ARM Debug Interface V5



ARM CoreSight Design Kit revision r1p1 Technical Reference Manual

Pinout and debug port pins
The STM32F0x0 MCUs are available in various packages with different numbers of
available pins.

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26.3.1

RM0360

SWD port pins
Two pins are used as outputs for the SW-DP as alternate functions of general purpose I/Os.
These pins are available on all packages.
Table 108. SW debug port pins
SW debug port
SW-DP pin name
Type

26.3.2

SWDIO

IO

SWCLK

I

Debug assignment

Pin
assignment

Serial Wire Data Input/Output

PA13

Serial Wire Clock

PA14

SW-DP pin assignment
After reset (SYSRESETn or PORESETn), the pins used for the SW-DP are assigned as
dedicated pins which are immediately usable by the debugger host.
However, the MCU offers the possibility to disable the SWD port and can then release the
associated pins for general-purpose I/O (GPIO) usage. For more details on how to disable
SW-DP port pins, please refer to Section 8.3.2: I/O pin alternate function multiplexer and
mapping on page 129.

26.3.3

Internal pull-up & pull-down on SWD pins
Once the SW I/O is released by the user software, the GPIO controller takes control of these
pins. The reset states of the GPIO control registers put the I/Os in the equivalent states:


SWDIO: input pull-up



SWCLK: input pull-down

Having embedded pull-up and pull-down resistors removes the need to add external
resistors.

26.4

ID codes and locking mechanism
There are several ID codes inside the MCU. ST strongly recommends the tool
manufacturers (for example Keil, IAR, Raisonance) to lock their debugger using the MCU
device ID located at address 0x40015800.
Only the DEV_ID[15:0] should be used for identification by the debugger/programmer tools
(the revision ID must not be taken into account).

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Debug support (DBG)

26.4.1

MCU device ID code
The STM32F0xx products integrate an MCU ID code. This ID identifies the ST MCU part
number and the die revision.
This code is accessible by the software debug port (two pins) or by the user software.
For code example refer to the Appendix section A.10.1: DBG read device ID code example.

DBGMCU_IDCODE
Address: 0x40015800
Only 32-bit access supported. Read-only
31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

REV_ID
r

r

r

r

r

r

r

r

r

r

r

r

r

r

r

r

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Res.

Res.

Res.

Res.
r

r

r

r

r

r

r

r

r

r

r

DEV_ID
r

Bits 31:16 REV_ID[15:0] Revision identifier
This field indicates the revision of the device. Refer to Table 114.
Bits 15:12 Reserved: read 0b0110.
Bits 11:0 DEV_ID[11:0]: Device identifier
This field indicates the device ID. Refer to Table 114.

Table 109. DEV_ID and REV_ID field values
Device

DEV_ID

Revision code

Revision number

REV_ID

STM32F030x4
STM32F030x6

0x444

A or 1

1.0

0x1000

STM32F070x6

0x445

A

1.0

0x1000

STM32F030x8

0x440

B or 1

1.1

0x1001

STM32F070xB

0x448

Y or 1

2.1

0x2001

STM32F030xC

0x442

A

1.0

0x1000

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26.5

SWD port

26.5.1

SWD protocol introduction
This synchronous serial protocol uses two pins:


SWCLK: clock from host to target



SWDIO: bidirectional

The protocol allows two banks of registers (DPACC registers and APACC registers) to be
read and written to.
Bits are transferred LSB-first on the wire.
For SWDIO bidirectional management, the line must be pulled-up on the board (100 kΩ
recommended by ARM).
Each time the direction of SWDIO changes in the protocol, a turnaround time is inserted
where the line is not driven by the host nor the target. By default, this turnaround time is one
bit time, however this can be adjusted by configuring the SWCLK frequency.

26.5.2

SWD protocol sequence
Each sequence consist of three phases:
1.

Packet request (8 bits) transmitted by the host

2.

Acknowledge response (3 bits) transmitted by the target

3.

Data transfer phase (33 bits) transmitted by the host or the target
Table 110. Packet request (8-bits)
Bit

Name

Description

0

Start

Must be “1”

1

APnDP

0: DP Access
1: AP Access

2

RnW

0: Write Request
1: Read Request

4:3

A[3:2]

Address field of the DP or AP registers (refer to Table 114 on
page 718)

5

Parity

Single bit parity of preceding bits

6

Stop

0

7

Park

Not driven by the host. Must be read as “1” by the target
because of the pull-up

Refer to the ARM® Cortex®-M0 TRM for a detailed description of DPACC and APACC
registers.
The packet request is always followed by the turnaround time (default 1 bit) where neither
the host nor target drive the line.

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Debug support (DBG)
Table 111. ACK response (3 bits)
Bit
0..2

Name

Description
001: FAULT
010: WAIT
100: OK

ACK

The ACK Response must be followed by a turnaround time only if it is a READ transaction
or if a WAIT or FAULT acknowledge has been received.
Table 112. DATA transfer (33 bits)
Bit
0..31
32

Name

Description

WDATA or
RDATA

Write or Read data

Parity

Single parity of the 32 data bits

The DATA transfer must be followed by a turnaround time only if it is a READ transaction.

26.5.3

SW-DP state machine (reset, idle states, ID code)
The State Machine of the SW-DP has an internal ID code which identifies the SW-DP. It
follows the JEP-106 standard. This ID code is the default ARM one and is set to
0x0BB11477 (corresponding to ARM® Cortex®-M0).

Note:

Note that the SW-DP state machine is inactive until the target reads this ID code.


The SW-DP state machine is in RESET STATE either after power-on reset, or after the
line is high for more than 50 cycles



The SW-DP state machine is in IDLE STATE if the line is low for at least two cycles
after RESET state.



After RESET state, it is mandatory to first enter into an IDLE state AND to perform a
READ access of the DP-SW ID CODE register. Otherwise, the target will issue a
FAULT acknowledge response on another transactions.

Further details of the SW-DP state machine can be found in the ARM® Cortex®-M0 TRM
and the CoreSight Design Kit r1p0 TRM.

26.5.4

DP and AP read/write accesses


Read accesses to the DP are not posted: the target response can be immediate (if
ACK=OK) or can be delayed (if ACK=WAIT).



Read accesses to the AP are posted. This means that the result of the access is
returned on the next transfer. If the next access to be done is NOT an AP access, then
the DP-RDBUFF register must be read to obtain the result.
The READOK flag of the DP-CTRL/STAT register is updated on every AP read access
or RDBUFF read request to know if the AP read access was successful.



The SW-DP implements a write buffer (for both DP or AP writes), that enables it to
accept a write operation even when other transactions are still outstanding. If the write
buffer is full, the target acknowledge response is “WAIT”. With the exception of

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IDCODE read or CTRL/STAT read or ABORT write which are accepted even if the write
buffer is full.


716/779

Because of the asynchronous clock domains SWCLK and HCLK, two extra SWCLK
cycles are needed after a write transaction (after the parity bit) to make the write
effective internally. These cycles should be applied while driving the line low (IDLE
state)
This is particularly important when writing the CTRL/STAT for a power-up request. If the
next transaction (requiring a power-up) occurs immediately, it will fail.

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Debug support (DBG)

26.5.5

SW-DP registers
Access to these registers are initiated when APnDP=0
Table 113. SW-DP registers
CTRLSEL bit
of SELECT
register

A[3:2]

R/W

Register

00

Read

IDCODE

00

Write

ABORT

Notes
The manufacturer code is set to the default
ARM code for Cortex-M0:
0x0BB11477 (identifies the SW-DP)

01

Read/Write

0

Purpose is to:
– request a system or debug power-up
– configure the transfer operation for AP
accesses
DP-CTRL/STAT
– control the pushed compare and pushed
verify operations.
– read some status flags (overrun, power-up
acknowledges)

01

Read/Write

1

WIRE
CONTROL

Purpose is to configure the physical serial
port protocol (like the duration of the
turnaround time)

10

Read

READ
RESEND

Enables recovery of the read data from a
corrupted debugger transfer, without
repeating the original AP transfer.

10

Write

SELECT

The purpose is to select the current access
port and the active 4-words register window

11

Read/Write

This read buffer is useful because AP
accesses are posted (the result of a read AP
request is available on the next AP
READ BUFFER transaction).
This read buffer captures data from the AP,
presented as the result of a previous read,
without initiating a new transaction

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RM0360

SW-AP registers
Access to these registers are initiated when APnDP=1
There are many AP Registers addressed as the combination of:


The shifted value A[3:2]



The current value of the DP SELECT register.
Table 114. 32-bit debug port registers addressed through the shifted value A[3:2]
Address A[3:2] value
0x0

00

Reserved, must be kept at reset value.

01

DP CTRL/STAT register. Used to:
– Request a system or debug power-up
– Configure the transfer operation for AP accesses
– Control the pushed compare and pushed verify operations.
– Read some status flags (overrun, power-up acknowledges)

0x8

10

DP SELECT register: Used to select the current access port and the
active 4-words register window.
– Bits 31:24: APSEL: select the current AP
– Bits 23:8: reserved
– Bits 7:4: APBANKSEL: select the active 4-words register window on the
current AP
– Bits 3:0: reserved

0xC

11

DP RDBUFF register: Used to allow the debugger to get the final result
after a sequence of operations (without requesting new JTAG-DP
operation)

0x4

26.6

Description

Core debug
Core debug is accessed through the core debug registers. Debug access to these registers
is by means of the debug access port. It consists of four registers:
Table 115. Core debug registers

718/779

Register

Description

DHCSR

The 32-bit Debug Halting Control and Status Register
This provides status information about the state of the processor enable core debug
halt and step the processor

DCRSR

The 17-bit Debug Core Register Selector Register:
This selects the processor register to transfer data to or from.

DCRDR

The 32-bit Debug Core Register Data Register:
This holds data for reading and writing registers to and from the processor selected
by the DCRSR (Selector) register.

DEMCR

The 32-bit Debug Exception and Monitor Control Register:
This provides Vector Catching and Debug Monitor Control.

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Debug support (DBG)
These registers are not reset by a system reset. They are only reset by a power-on reset.
Refer to the ARM® Cortex®-M0 TRM for further details.
To Halt on reset, it is necessary to:

26.7



enable the bit0 (VC_CORRESET) of the Debug and Exception Monitor Control
Register



enable the bit0 (C_DEBUGEN) of the Debug Halting Control and Status Register

BPU (Break Point Unit)
The Cortex-M0 BPU implementation provides four breakpoint registers. The BPU is a
subset of the Flash Patch and Breakpoint (FPB) block available in ARMv7-M (Cortex-M3 &
Cortex-M4).

26.7.1

BPU functionality
The processor breakpoints implement PC based breakpoint functionality.
Refer the ARMv6-M ARM and the ARM CoreSight Components Technical Reference
Manual for more information about the BPU CoreSight identification registers, and their
addresses and access types.

26.8

DWT (Data Watchpoint)
The Cortex-M0 DWT implementation provides two watchpoint register sets.

26.8.1

DWT functionality
The processor watchpoints implement both data address and PC based watchpoint
functionality, a PC sampling register, and support comparator address masking, as
described in the ARMv6-M ARM.

26.8.2

DWT Program Counter Sample Register
A processor that implements the data watchpoint unit also implements the ARMv6-M
optional DWT Program Counter Sample Register (DWT_PCSR). This register permits a
debugger to periodically sample the PC without halting the processor. This provides coarse
grained profiling. See the ARMv6-M ARM for more information.
The Cortex-M0 DWT_PCSR records both instructions that pass their condition codes and
those that fail.

26.9

MCU debug component (DBGMCU)
The MCU debug component helps the debugger provide support for:


Low-power modes



Clock control for timers, watchdog and I2C during a breakpoint

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Debug support for low-power modes
To enter low-power mode, the instruction WFI or WFE must be executed.
The MCU implements several low-power modes which can either deactivate the CPU clock
or reduce the power of the CPU.
The core does not allow FCLK or HCLK to be turned off during a debug session. As these
are required for the debugger connection, during a debug, they must remain active. The
MCU integrates special means to allow the user to debug software in low-power modes.
For this, the debugger host must first set some debug configuration registers to change the
low-power mode behavior:


In Sleep mode: FCLK and HCLK are still active. Consequently, this mode does not
impose any restrictions on the standard debug features.



In Stop/Standby mode, the DBG_STOP bit must be previously set by the debugger.

This enables the internal RC oscillator clock to feed FCLK and HCLK in Stop mode.
For code example refer to the Appendix section A.10.2: DBG debug in Low-power mode
code example.

26.9.2

Debug support for timers, watchdog and I2C
During a breakpoint, it is necessary to choose how the counter of timers and watchdog
should behave:


They can continue to count inside a breakpoint. This is usually required when a PWM is
controlling a motor, for example.



They can stop to count inside a breakpoint. This is required for watchdog purposes.

For the I2C, the user can choose to block the SMBUS timeout during a breakpoint.

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Debug support (DBG)

26.9.3

Debug MCU configuration register (DBGMCU_CR)
This register allows the configuration of the MCU under DEBUG. This concerns:


Low-power mode support

This DBGMCU_CR is mapped at address 0x4001 5804.
It is asynchronously reset by the PORESET (and not the system reset). It can be written by
the debugger under system reset.
If the debugger host does not support these features, it is still possible for the user software
to write to these registers.
Address: 0x40015804
Only 32-bit access supported
POR Reset: 0x0000 0000 (not reset by system reset)
31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Res.

DBG_
STAND
BY

DBG_
STOP

Res.

rw

rw

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Bits 31:3 Reserved, must be kept at reset value.
Bit 2 DBG_STANDBY: Debug Standby mode
0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
From software point of view, exiting from Standby is identical than fetching reset vector
(except a few status bit indicated that the MCU is resuming from Standby)
1: (FCLK=On, HCLK=On) In this case, the digital part is not unpowered and FCLK and
HCLK are provided by the internal RC oscillator which remains active. In addition, the MCU
generate a system reset during Standby mode so that exiting from Standby is identical than
fetching from reset
Bit 1 DBG_STOP: Debug Stop mode
0: (FCLK=Off, HCLK=Off) In STOP mode, the clock controller disables all clocks (including
HCLK and FCLK). When exiting from STOP mode, the clock configuration is identical to the
one after RESET (CPU clocked by the 8 MHz internal RC oscillator (HSI)). Consequently,
the software must reprogram the clock controller to enable the PLL, the Xtal, etc.
1: (FCLK=On, HCLK=On) In this case, when entering STOP mode, FCLK and HCLK are
provided by the internal RC oscillator which remains active in STOP mode. When exiting
STOP mode, the software must reprogram the clock controller to enable the PLL, the Xtal,
etc. (in the same way it would do in case of DBG_STOP=0)

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26.9.4

RM0360

Debug MCU APB1 freeze register (DBGMCU_APB1_FZ)
The DBGMCU_APB1_FZ register is used to configure the MCU under DEBUG. It concerns
some APB peripherals:


Timer clock counter freeze



I2C SMBUS timeout freeze



System window watchdog and independent watchdog counter freeze support

This DBGMCU_APB1_FZ is mapped at address 0x4001 5808.
The register is asynchronously reset by the POR (and not the system reset). It can be
written by the debugger under system reset.
Address offset: 0x08
Only 32-bit access are supported.

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

DBG_I2C1_SMBUS_TIMEOUT

Res.

Res.

Res.

Res.

Res.

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Res.

Res.

Res.

DBG_IWDG_STOP

DBG_WWDG_STOP

DBG_RTC_STOP

Res.

DBG_TIM14_STOP

Res.

Res.

DBG_TIM7_STOP

DBG_TIM6_STOP

Res.

Res.

DBG_TIM3_STOP

Power on reset (POR): 0x0000 0000 (not reset by system reset)

Res.

rw

rw

rw

rw

rw

rw

rw

rw

Bits 31:22 Reserved, must be kept at reset value.
Bit 21 DBG_I2C1_SMBUS_TIMEOUT: SMBUS timeout mode stopped when core is halted
0: Same behavior as in normal mode
1: The SMBUS timeout is frozen
Bits 20:13 Reserved, must be kept at reset value.
Bit 12 DBG_IWDG_STOP: Debug independent watchdog stopped when core is halted
0: The independent watchdog counter clock continues even if the core is halted
1: The independent watchdog counter clock is stopped when the core is halted
Bit 11 DBG_WWDG_STOP: Debug window watchdog stopped when core is halted
0: The window watchdog counter clock continues even if the core is halted
1: The window watchdog counter clock is stopped when the core is halted

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Debug support (DBG)

Bit 10 DBG_RTC_STOP: Debug RTC stopped when core is halted
0: The clock of the RTC counter is fed even if the core is halted
1: The clock of the RTC counter is stopped when the core is halted
Bit 9 Reserved, must be kept at reset value.
Bit 8 DBG_TIM14_STOP: TIM14 counter stopped when core is halted
0: The counter clock of TIM14 is fed even if the core is halted
1: The counter clock of TIM14 is stopped when the core is halted
Bits 7:6 Reserved, must be kept at reset value.
Bit 5 DBG_TIM7_STOP: TIM7 counter stopped when core is halted.
0: The counter clock of TIM7 is fed even if the core is halted
1: The counter clock of TIM7 is stopped when the core is halted
Bit 4 DBG_TIM6_STOP: TIM6 counter stopped when core is halted
0: The counter clock of TIM6 is fed even if the core is halted
1: The counter clock of TIM6 is stopped when the core is halted
Bits 3:2 Reserved, must be kept at reset value.
Bit 1 DBG_TIM3_STOP: TIM3 counter stopped when core is halted
0: The counter clock of TIM3 is fed even if the core is halted
1: The counter clock of TIM3 is stopped when the core is halted
Bit 0 Reserved, must be kept at reset value.

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Debug support (DBG)

26.9.5

RM0360

Debug MCU APB2 freeze register (DBGMCU_APB2_FZ)
The DBGMCU_APB2_FZ register is used to configure the MCU under DEBUG. It concerns
some APB peripherals:


Timer clock counter freeze

This register is mapped at address 0x4001580C.
It is asynchronously reset by the POR (and not the system reset). It can be written by the
debugger under system reset.
Address offset: 0x0C
Only 32-bit access is supported.

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

DBG_TIM17_STOP

DBG_TIM16_STOP

DBG_TIM15_STOP

rw

rw

rw

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Res.

Res.

Res.

Res.

DBG_TIM1_STOP

POR: 0x0000 0000 (not reset by system reset)

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

rw

Bits 31:19 Reserved, must be kept at reset value.
Bit 18 DBG_TIM17_STOP: TIM17 counter stopped when core is halted
0: The counter clock of TIM17 is fed even if the core is halted
1: The counter clock of TIM17 is stopped when the core is halted
Bit 17 DBG_TIM16_STOP: TIM16 counter stopped when core is halted
0: The counter clock of TIM16 is fed even if the core is halted
1: The counter clock of TIM16 is stopped when the core is halted
Bit 16 DBG_TIM15_STOP: TIM15 counter stopped when core is halted
0: The counter clock of TIM15 is fed even if the core is halted
1: The counter clock of TIM15 is stopped when the core is halted
Bits 15:12 Reserved, must be kept at reset value.
Bit 11 DBG_TIM1_STOP: TIM1 counter stopped when core is halted
0: The counter clock of TIM 1 is fed even if the core is halted
1: The counter clock of TIM 1 is stopped when the core is halted
Bits 0:10 Reserved, must be kept at reset value.

26.9.6

DBG register map
The following table summarizes the Debug registers.

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DBGMCU_
APB2_FZ
DBG_TIM15_STOP

0
0
0

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DBG_RTC_STOP

0
0

DBG_TIM1_STOP
Res.

Res.

X
X
X
X

0

Res.
Res.
Res.
Res.
Res.
Res.
Res.

Reset value

DBG_TIM3_STOP
Res.

Res.

0

0
0

Res.

0

Res.

DBG_STOP

X

DBG_STANDBY

X

Res.

X

Res.

X

Res.

Res.

Res.

Res.

X

Res.

Res.

X

Res.

Res.

X

Res.

DBG_TIM6_STOP

0

Res.

Res.

Res.

DBG_TIM14_STOP

DBG_TIM7_STOP

0

Res.

Res.

Res.

Res.

Res.

DBG_WWDG_STOP

0

Res.

DBG_IWDG_STOP

0

Res.

Res.

Res.

Res.

Res.

Res.

Res.

X

Res.

Res.

X

Res.

Res.

X

Res.

Res.

X

Res.

Res.

X

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

REV_ID

Res.

DBG_TIM16_STOP

Res.

Reset value
Res.

Res.

X X X X

Res.

DBGMCU_CR

DBG_I2C1_SMBUS_TIMEOUT

X

Res.

X

Res.

X

Res.

X

Res.

X

Res.

X

Res.

X

Res.

Res.

Res.

Res.

Res.

Res.

Reset value(1)

Res.

DBGMCU_
IDCODE

Res.

Res.

Res.

Res.

Res.

Res.

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0

.

DBG_TIM17_STOP

Reset value
Res.

DBGMCU_
APB1_FZ
Res.

0x40015800

Register

Res.

0x40015804

Addr.

Res.

0x40015808

RM0360
Debug support (DBG)

Table 116. DBG register map and reset values

DEV_ID

X

0

1. The reset value is product dependent. For more information, refer to Section 26.4.1: MCU device ID code.

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27

RM0360

Device electronic signature
The device electronic signature is stored in the System memory area of the Flash memory
module, and can be read using the debug interface or by the CPU. It contains factoryprogrammed identification and calibration data that allow the user firmware or other external
devices to automatically match to the characteristics of the STM32F0x0 microcontroller.

27.1

Memory size data register

27.1.1

Flash size data register
Base address: 0x1FFF F7CC
Address offset: 0x00
Read only = 0xXXXX where X is factory-programmed

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

r

r

r

r

r

r

r

FLASH_SIZE
r

r

r

r

r

r

r

r

r

Bits 15:0 FLASH_SIZE[15:0]: Flash memory size
This bitfield indicates the size of the device Flash memory expressed in Kbytes.
As an example, 0x040 corresponds to 64 Kbytes.

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Code examples

Appendix A
A.1

Code examples

Introduction
This appendix shows the code examples of the sequence described in this Reference
Manual.
These code examples are extracted from the STM32F0xx Snippet firmware package
STM32SnippetsF0 available on www.st.com.
These code examples used the peripheral bit and register description from the CMSIS
header file (stm32f0xx.h).
Code lines starting with // should be uncommented if the given register has been modified
before.

A.2

Flash operation code example

A.2.1

Flash memory unlocking sequence code
/* (1) Wait till no operation is on going */
/* (2) Check that the Flash is unlocked */
/* (3) Perform unlock sequence */
while ((FLASH->SR & FLASH_SR_BSY) != 0) /* (1) */

{
/* For robust implementation, add here time-out management */

}
if ((FLASH->CR & FLASH_CR_LOCK) != 0) /* (2) */
{
FLASH->KEYR = FLASH_FKEY1; /* (3) */
FLASH->KEYR = FLASH_FKEY2;
}

A.2.2

Main Flash programming sequence code example
/* (1) Set the PG bit in the FLASH_CR register to enable programming */
/* (2) Perform the data write (half-word) at the desired address */
/* (3) Wait until the BSY bit is reset in the FLASH_SR register */
/* (4) Check the EOP flag in the FLASH_SR register */
/* (5) clear it by software by writing it at 1 */
/* (6) Reset the PG Bit to disable programming */
FLASH->CR |= FLASH_CR_PG; /* (1) */
*(__IO uint16_t*)(flash_addr) = data; /* (2) */
while ((FLASH->SR & FLASH_SR_BSY) != 0) /* (3) */
{
/* For robust implementation, add here time-out management */
}

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if ((FLASH->SR & FLASH_SR_EOP) != 0) /* (4) */
{
FLASH->SR = FLASH_SR_EOP; /* (5) */
}
else
{
/* Manage the error cases */
}
FLASH->CR &= ~FLASH_CR_PG; /* (6) */

A.2.3

Page erase sequence code example
/* (1) Set the PER bit in the FLASH_CR register to enable page erasing */
/* (2) Program the FLASH_AR register to select a page to erase */
/* (3) Set the STRT bit in the FLASH_CR register to start the erasing */
/* (4) Wait until the BSY bit is reset in the FLASH_SR register */
/* (5) Check the EOP flag in the FLASH_SR register */
/* (6) Clear EOP flag by software by writing EOP at 1 */
/* (7) Reset the PER Bit to disable the page erase */
FLASH->CR |= FLASH_CR_PER; /* (1) */
FLASH->AR = page_addr; /* (2) */
FLASH->CR |= FLASH_CR_STRT; /* (3) */
while ((FLASH->SR & FLASH_SR_BSY) != 0) /* (4) */
{
/* For robust implementation, add here time-out management */
}
if ((FLASH->SR & FLASH_SR_EOP) != 0) /* (5) */
{
FLASH->SR = FLASH_SR_EOP; /* (6)*/
}
else
{
/* Manage the error cases */
}
FLASH->CR &= ~FLASH_CR_PER; /* (7) */

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A.2.4

Code examples

Mass erase sequence code example
/* (1) Set the MER bit in the FLASH_CR register to enable mass erasing */
/* (2) Set the STRT bit in the FLASH_CR register to start the erasing */
/* (3) Wait until the BSY bit is reset in the FLASH_SR register */
/* (4) Check the EOP flag in the FLASH_SR register */
/* (5) Clear EOP flag by software by writing EOP at 1 */
/* (6) Reset the PER Bit to disable the mass erase */
FLASH->CR |= FLASH_CR_MER; /* (1) */
FLASH->CR |= FLASH_CR_STRT; /* (2) */
while ((FLASH->SR & FLASH_SR_BSY) != 0) /* (3) */
{
/* For robust implementation, add here time-out management */
}
if ((FLASH->SR & FLASH_SR_EOP) != 0) /* (4)*/
{
FLASH->SR = FLASH_SR_EOP; /* (5) */
}
else
{
/* Manage the error cases */
}
FLASH->CR &= ~FLASH_CR_MER; /* (6) */

A.2.5

Option byte unlocking sequence code example
/* (1) Wait till no operation is on going */
/* (2) Check that the Flash is unlocked */
/* (3) Perform unlock sequence for Flash */
/* (4) Check that the Option Bytes are unlocked */
/* (5) Perform unlock sequence for Option Bytes */
while ((FLASH->SR & FLASH_SR_BSY) != 0) /* (1) */
{
/* For robust implementation, add here time-out management */
}
if ((FLASH->CR & FLASH_CR_LOCK) != 0) /* (2) */
{
FLASH->KEYR = FLASH_FKEY1; /* (3) */
FLASH->KEYR = FLASH_FKEY2;
}
if ((FLASH->CR & FLASH_CR_OPTWRE) == 0) /* (4) */
{
FLASH->OPTKEYR = FLASH_OPTKEY1; /* (5) */
FLASH->OPTKEYR = FLASH_OPTKEY2;
}

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A.2.6

RM0360

Option byte programming sequence code example
/* (1) Set the PG bit in the FLASH_CR register to enable programming */
/* (2) Perform the data write */
/* (3) Wait until the BSY bit is reset in the FLASH_SR register */
/* (4) Check the EOP flag in the FLASH_SR register */
/* (5) Clear the EOP flag by software by writing it at 1 */
/* (6) Reset the PG Bit to disable programming */
FLASH->CR |= FLASH_CR_OPTPG; /* (1) */
*opt_addr = data; /* (2) */
while ((FLASH->SR & FLASH_SR_BSY) != 0) /* (3) */
{
/* For robust implementation, add here time-out management */
}
if ((FLASH->SR & FLASH_SR_EOP) != 0) /* (4) */
{
FLASH->SR = FLASH_SR_EOP; /* (5) */
}
else
{
/* Manage the error cases */
}
FLASH->CR &= ~FLASH_CR_OPTPG; /* (6) */

A.2.7

Option byte erasing sequence code example
/* (1) Set the OPTER bit in the FLASH_CR register to enable option byte
erasing */
/* (2) Set the STRT bit in the FLASH_CR register to start the erasing */
/* (3) Wait until the BSY bit is reset in the FLASH_SR register */
/* (4) Check the EOP flag in the FLASH_SR register */
/* (5) Clear EOP flag by software by writing EOP at 1 */
/* (6) Reset the PER Bit to disable the page erase */
FLASH->CR |= FLASH_CR_OPTER; /* (1) */
FLASH->CR |= FLASH_CR_STRT; /* (2) */
while ((FLASH->SR & FLASH_SR_BSY) != 0) /* (3) */
{
/* For robust implementation, add here time-out management */
}
if ((FLASH->SR & FLASH_SR_EOP) != 0) /* (4) */
{
FLASH->SR = FLASH_SR_EOP; /* (5)*/
}
else
{
/* Manage the error cases */
}
FLASH->CR &= ~FLASH_CR_OPTER; /* (6) */

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Code examples

A.3

Clock controller

A.3.1

HSE start sequence code example
/**
* Description: This function enables the interrupt on HSE ready,
*
and start the HSE as external clock.
*/
__INLINE void StartHSE(void)
{
/* Configure NVIC for RCC */
/* (1) Enable Interrupt on RCC */
/* (2) Set priority for RCC */
NVIC_EnableIRQ(RCC_CRS_IRQn); /* (1)*/
NVIC_SetPriority(RCC_CRS_IRQn,0); /* (2) */
/* (1) Enable interrupt on HSE ready */
/* (2) Enable the CSS
Enable the HSE and set HSEBYP to use the external clock
instead of an oscillator
Enable HSE */
/* Note : the clock is switched to HSE in the RCC_CRS_IRQHandler ISR */
RCC->CIR |= RCC_CIR_HSERDYIE; /* (1) */
RCC->CR |= RCC_CR_CSSON | RCC_CR_HSEBYP | RCC_CR_HSEON; /* (2) */
}
/**
* Description: This function handles RCC interrupt request
*
and switch the system clock to HSE.
*/
void RCC_CRS_IRQHandler(void)
{
/* (1) Check the flag HSE ready */
/* (2) Clear the flag HSE ready */
/* (3) Switch the system clock to HSE */
if ((RCC->CIR & RCC_CIR_HSERDYF) != 0) /* (1) */
{
RCC->CIR |= RCC_CIR_HSERDYC; /* (2) */
RCC->CFGR = ((RCC->CFGR & (~RCC_CFGR_SW)) | RCC_CFGR_SW_0); /* (3) */
}
else
{
/* Report an error */
}
}

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Code examples

A.3.2

RM0360

PLL configuration modification code example
/* (1) Test if PLL is used as System clock */
/* (2) Select HSI as system clock */
/* (3) Wait for HSI switched */
/* (4) Disable the PLL */
/* (5) Wait until PLLRDY is cleared */
/* (6) Set the PLL multiplier to 6 */
/* (7) Enable the PLL */
/* (8) Wait until PLLRDY is set */
/* (9) Select PLL as system clock */
/* (10) Wait until the PLL is switched on */
if ((RCC->CFGR & RCC_CFGR_SWS) == RCC_CFGR_SWS_PLL) /* (1) */
{
RCC->CFGR &= (uint32_t) (~RCC_CFGR_SW); /* (2) */
while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI) /* (3) */
{
/* For robust implementation, add here time-out management */
}
}
RCC->CR &= (uint32_t)(~RCC_CR_PLLON);/* (4) */
while((RCC->CR & RCC_CR_PLLRDY) != 0) /* (5) */
{
/* For robust implementation, add here time-out management */
}
RCC->CFGR = RCC->CFGR & (~RCC_CFGR_PLLMUL) | (RCC_CFGR_PLLMUL6); /* (6) */
RCC->CR |= RCC_CR_PLLON; /* (7) */
while((RCC->CR & RCC_CR_PLLRDY) == 0) /* (8) */
{
/* For robust implementation, add here time-out management */
}
RCC->CFGR |= (uint32_t) (RCC_CFGR_SW_PLL); /* (9) */
while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL) /* (10) */
{
/* For robust implementation, add here time-out management */
}

A.3.3

MCO selection code example
/* Select system clock to be output on the MCO without prescaler */
RCC->CFGR |= RCC_CFGR_MCO_SYSCLK;

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A.3.4

Code examples

Clock measurement configuration with TIM14 code example
/**
* Description: This function configures the TIM14 as input capture
*
and enables the interrupt on TIM14
*/
__INLINE void ConfigureTIM14asInputCapture(void)
{
/* (1) Enable the peripheral clock of Timer 14 */
/* (2) Select the active input TI1,Program the input filter, and prescaler
*/
/* (3) Enable interrupt on Capture/Compare */
RCC->APB1ENR |= RCC_APB1ENR_TIM14EN; /* (1) */
TIM14->CCMR1 |= TIM_CCMR1_IC1F_0 | TIM_CCMR1_IC1F_1 \
| TIM_CCMR1_CC1S_0 | TIM_CCMR1_IC1PSC_1; /* (2)*/
TIM14->DIER |= TIM_DIER_CC1IE; /* (3) */
/* Configure NVIC for TIM14 */
/* (4) Enable Interrupt on TIM14 */
/* (5) Set priority for TIM14 */
NVIC_EnableIRQ(TIM14_IRQn); /* (4) */
NVIC_SetPriority(TIM14_IRQn,0); /* (5) */
/* (6) Select HSE/32 as input on TI1 */
/* (7) Enable counter */
/* (8) Enable capture */
TIM14->OR |= TIM14_OR_TI1_RMP_1; /* (6) */
TIM14->CR1 |= TIM_CR1_CEN; /* (7) */
TIM14->CCER |= TIM_CCER_CC1E; /* (8) */
}

Note:

The measurement is done in the TIM14 interrupt subroutine.

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A.4

GPIO

A.4.1

Lock sequence code example
/**
* Description: This function locks the targeted pins of Port A
configuration
This function can be easily modified to lock Port B
* Parameter: lock contains the port pin mask to be locked
*/
void LockGPIOA(uint16_t lock)
{
/* (1) Write LCKK bit to 1 and set the pin bits to lock */
/* (2) Write LCKK bit to 0 and set the pin bits to lock */
/* (3) Write LCKK bit to 1 and set the pin bits to lock */
/* (4) Read the Lock register */
/* (5) Check the Lock register (optionnal) */
GPIOA->LCKR = GPIO_LCKR_LCKK + lock; /* (1) */
GPIOA->LCKR = lock; /* (2) */
GPIOA->LCKR = GPIO_LCKR_LCKK + lock; /* (3) */
GPIOA->LCKR; /* (4) */
if ((GPIOA->LCKR & GPIO_LCKR_LCKK) == 0) /* (5) */
{
/* Manage an error */
}
}

A.4.2

Alternate function selection sequence code example
/* This sequence select AF2 for GPIOA4, 8 and 9. This can be easily adapted
with another port by changing all GPIOA references by another GPIO port,
and the alternate function number can be changed by replacing 0x04 or
0x02 for
each pin by the targeted alternate function in the 2 last code lines. */
/* (1) Enable the peripheral clock of GPIOA */
/* (2) Select alternate function mode on GPIOA pin 4, 8 and 9 */
/* (3) Select AF4 on PA4 in AFRL for TIM14_CH1 */
/* (4) Select AF2 on PA8 and PA9 in AFRH for TIM1_CH1 and TIM1_CH2 */
RCC->AHBENR |= RCC_AHBENR_GPIOAEN; /* (1) */
GPIOA->MODER = (GPIOA->MODER & ~(GPIO_MODER_MODER4 | GPIO_MODER_MODER8
| GPIO_MODER_MODER9)) | GPIO_MODER_MODER4_1
| GPIO_MODER_MODER8_1 | GPIO_MODER_MODER9_1; /* (2) */
GPIOA->AFR[0] |= 0x04 << GPIO_AFRL_AFRL4_Pos; /* (3) */
GPIOA->AFR[1] |= (0x02 << GPIO_AFRL_AFRH8_Pos) | (0x02 <<
GPIO_AFRL_AFRH9_Pos); /* (4) */

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A.4.3

Code examples

Analog GPIO configuration code example
/* (1) Enable the peripheral clock of GPIOA, GPIOB and GPIOC */
/* (2) Select analog mode for PA1 */
/* (3) Select analog mode for PB1 */
/* (4) Select analog mode for PC0 */
RCC->AHBENR |= RCC_AHBENR_GPIOAEN | RCC_AHBENR_GPIOBEN
| RCC_AHBENR_GPIOCEN; /* (1) */
GPIOA->MODER |= GPIO_MODER_MODER1; /* (2) */
GPIOB->MODER |= GPIO_MODER_MODER1; /* (3) */
GPIOC->MODER |= GPIO_MODER_MODER0; /* (4) */

A.5

DMA

A.5.1

DMA Channel Configuration sequence code example
/* The following example is given for the ADC. It can be easily ported on
any peripheral supporting DMA transfer taking of the associated channel
to the peripheral, this must check in the datasheet. */
/* (1) Enable the peripheral clock on DMA */
/* (2) Enable DMA transfer on ADC */
/* (3) Configure the peripheral data register address */
/* (4) Configure the memory address */
/* (5) Configure the number of DMA tranfer to be performs on channel 1 */
/* (6) Configure increment, size and interrupts */
/* (7) Enable DMA Channel 1 */
RCC->AHBENR |= RCC_AHBENR_DMA1EN; /* (1) */
ADC1->CFGR1 |= ADC_CFGR1_DMAEN; /* (2) */
DMA1_Channel1->CPAR = (uint32_t) (&(ADC1->DR)); /* (3) */
DMA1_Channel1->CMAR = (uint32_t)(ADC_array); /* (4) */
DMA1_Channel1->CNDTR = 3; /* (5) */
DMA1_Channel1->CCR |= DMA_CCR_MINC | DMA_CCR_MSIZE_0 | DMA_CCR_PSIZE_0
| DMA_CCR_TEIE | DMA_CCR_TCIE ; /* (6) */
DMA1_Channel1->CCR |= DMA_CCR_EN; /* (7) */
/* Configure NVIC for DMA */
/* (1) Enable Interrupt on DMA Channel 1 */
/* (2) Set priority for DMA Channel 1 */
NVIC_EnableIRQ(DMA1_Channel1_IRQn); /* (1) */
NVIC_SetPriority(DMA1_Channel1_IRQn,0); /* (2) */

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A.6

Interrupts and event

A.6.1

NVIC initialization example
/* (1) Enable Interrupt on ADC */
/* (2) Set priority for ADC to 2*/
NVIC_EnableIRQ(ADC1_COMP_IRQn); /* (1) */
NVIC_SetPriority(ADC1_COMP_IRQn,2); /* (2) */

A.6.2

External interrupt selection code example
/* (1) Enable the peripheral clock of GPIOA */
/* (2) Select Port A for pin 0 external interrupt by writing 0000 in
EXTI0 (reset value)*/
/* (3) Configure the corresponding mask bit in the EXTI_IMR register */
/* (4) Configure the Trigger Selection bits of the Interrupt line on
rising edge*/
/* (5) Configure the Trigger Selection bits of the Interrupt line on
falling edge*/
RCC->AHBENR |= RCC_AHBENR_GPIOAEN; /* (1) */
//SYSCFG->EXTICR[1] &= (uint16_t)~SYSCFG_EXTICR1_EXTI0_PA; /* (2) */
EXTI->IMR = 0x0001; /* (3) */
EXTI->RTSR = 0x0001; /* (4) */
EXTI->FTSR = 0x0001; /* (5) */
/* Configure NVIC for External Interrupt */
/* (1) Enable Interrupt on EXTI0_1 */
/* (2) Set priority for EXTI0_1 */
NVIC_EnableIRQ(EXTI0_1_IRQn); /* (1) */
NVIC_SetPriority(EXTI0_1_IRQn,0); /* (2) */

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Code examples

A.7

ADC

A.7.1

ADC Calibration code example
/* (1) Ensure that ADEN = 0 */
/* (2) Clear ADEN by setting ADDIS*/
/* (3) Clear DMAEN */
/* (4) Launch the calibration by setting ADCAL */
/* (5) Wait until ADCAL=0 */
if ((ADC1->CR & ADC_CR_ADEN) != 0) /* (1) */
{
ADC1->CR |= ADC_CR_ADDIS; /* (2) */
}
while ((ADC1->CR & ADC_CR_ADEN) != 0)
{
/* For robust implementation, add here time-out management */
}
ADC1->CFGR1 &= ~ADC_CFGR1_DMAEN; /* (3) */
ADC1->CR |= ADC_CR_ADCAL; /* (4) */
while ((ADC1->CR & ADC_CR_ADCAL) != 0) /* (5) */
{
/* For robust implementation, add here time-out management */
}

A.7.2

ADC enable sequence code example
/* (1) Ensure that ADRDY = 0 */
/* (2) Clear ADRDY */
/* (3) Enable the ADC */
/* (4) Wait until ADC ready */
if ((ADC1->ISR & ADC_ISR_ADRDY) != 0) /* (1) */
{
ADC1->ISR |= ADC_CR_ADRDY; /* (2) */
}
ADC1->CR |= ADC_CR_ADEN; /* (3) */
while ((ADC1->ISR & ADC_ISR_ADRDY) == 0) /* (4) */
{
/* For robust implementation, add here time-out management */
}

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A.7.3

RM0360

ADC disable sequence code example
/* (1) Stop any ongoing conversion */
/* (2) Wait until ADSTP is reset by hardware i.e. conversion is stopped */
/* (3) Disable the ADC */
/* (4) Wait until the ADC is fully disabled */
ADC1->CR |= ADC_CR_ADSTP; /* (1) */
while ((ADC1->CR & ADC_CR_ADSTP) != 0) /* (2) */
{
/* For robust implementation, add here time-out management */
}
ADC1->CR |= ADC_CR_ADDIS; /* (3) */
while ((ADC1->CR & ADC_CR_ADEN) != 0) /* (4) */
{
/* For robust implementation, add here time-out management */
}

A.7.4

ADC Clock selection code example
/* This code selects the HSI14 as clock source. */
/* (1) Enable the peripheral clock of the ADC */
/* (2) Start HSI14 RC oscillator */
/* (3) Wait HSI14 is ready */
/* (4) Select HSI14 by writing 00 in CKMODE (reset value) */
RCC->APB2ENR |= RCC_APB2ENR_ADC1EN; /* (1) */
RCC->CR2 |= RCC_CR2_HSI14ON; /* (2) */
while ((RCC->CR2 & RCC_CR2_HSI14RDY) == 0) /* (3) */
{
/* For robust implementation, add here time-out management */
}
//ADC1->CFGR2 &= (~ADC_CFGR2_CKMODE); /* (4) */

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A.7.5

Code examples

Single conversion sequence code example - Software trigger
/* (1) Select HSI14 by writing 00 in CKMODE (reset value) */
/* (2) Select CHSEL0, CHSEL9, CHSEL10 andCHSEL17 for VRefInt */
/* (3) Select a sampling mode of 111 i.e. 239.5 ADC clk to be greater
than 17.1us */
/* (4) Wake-up the VREFINT (only for VBAT, Temp sensor and VRefInt) */
//ADC1->CFGR2 &= ~ADC_CFGR2_CKMODE; /* (1) */
ADC1->CHSELR = ADC_CHSELR_CHSEL0 | ADC_CHSELR_CHSEL9
| ADC_CHSELR_CHSEL10 | ADC_CHSELR_CHSEL17; /* (2) */
ADC1->SMPR |= ADC_SMPR_SMP_0 | ADC_SMPR_SMP_1 | ADC_SMPR_SMP_2; /* (3) */
ADC->CCR |= ADC_CCR_VREFEN; /* (4) */
while (1)
{
/* Performs the AD conversion */
ADC1->CR |= ADC_CR_ADSTART; /* Start the ADC conversion */
for (i=0; i < 4; i++)
{
while ((ADC1->ISR & ADC_ISR_EOC) == 0) /* Wait end of conversion */
{
/* For robust implementation, add here time-out management */
}
ADC_Result[i] = ADC1->DR; /* Store the ADC conversion result */
}
ADC1->CFGR1 ^= ADC_CFGR1_SCANDIR; /* Toggle the scan direction */
}

A.7.6

Continuous conversion sequence code example - Software trigger
/* This code example configures the AD conversion in continuous mode and in
backward scan. It also enable the interrupts. */
/* (1) Select HSI14 by writing 00 in CKMODE (reset value) */
/* (2) Select the continuous mode and scanning direction */
/* (3) Select CHSEL1, CHSEL9, CHSEL10 and CHSEL17 */
/* (4) Select a sampling mode of 111 i.e. 239.5 ADC clk to be greater than
17.1us */
/* (5) Enable interrupts on EOC, EOSEQ and overrrun */
/* (6) Wake-up the VREFINT (only for VBAT, Temp sensor and VRefInt) */
//ADC1->CFGR2 &= ~ADC_CFGR2_CKMODE; /* (1) */
ADC1->CFGR1 |= ADC_CFGR1_CONT | ADC_CFGR1_SCANDIR; /* (2) */
ADC1->CHSELR = ADC_CHSELR_CHSEL1 | ADC_CHSELR_CHSEL9
| ADC_CHSELR_CHSEL10 | ADC_CHSELR_CHSEL17; /* (3) */
ADC1->SMPR |= ADC_SMPR_SMP_0 | ADC_SMPR_SMP_1 | ADC_SMPR_SMP_2; /* (4) */
ADC1->IER = ADC_IER_EOCIE | ADC_IER_EOSEQIE | ADC_IER_OVRIE; /* (5) */
ADC->CCR |= ADC_CCR_VREFEN; /* (6) */
/* Configure NVIC for ADC */
/* (7) Enable Interrupt on ADC */
/* (8) Set priority for ADC */
NVIC_EnableIRQ(ADC1_COMP_IRQn); /* (7) */
NVIC_SetPriority(ADC1_COMP_IRQn,0); /* (8) */

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A.7.7

RM0360

Single conversion sequence code example - Hardware trigger
/* Configure the ADC, the ADC and its clock having previously been
enabled. */
/* (1) Select HSI14 by writing 00 in CKMODE (reset value) */
/* (2) Select the external trigger on falling edge and external trigger on
TIM15_TRGO */
/* (3) Select CHSEL0, 1, 2 and 3 */
//ADC1->CFGR2 &= ~ADC_CFGR2_CKMODE; /* (1) */
ADC1->CFGR1 |= ADC_CFGR1_EXTEN_0 | ADC_CFGR1_EXTSEL_2; /* (2) */
ADC1->CHSELR = ADC_CHSELR_CHSEL0 | ADC_CHSELR_CHSEL1
| ADC_CHSELR_CHSEL2 | ADC_CHSELR_CHSEL3; /* (3) */

A.7.8

Continuous conversion sequence code example - Hardware trigger
/* (1) Select HSI14 by writing 00 in CKMODE (reset value) */
/* (2) Select the external trigger on TIM15_TRGO (EXTSEL = 100),falling
edge (EXTEN = 10), the continuous mode (CONT = 1)*/
/* (3) Select CHSEL0/1/2/3 */
/* (4) Enable interrupts on EOC, EOSEQ and overrrun */
//ADC1->CFGR2 &= ~ADC_CFGR2_CKMODE; /* (1) */
ADC1->CFGR1 |= ADC_CFGR1_EXTEN_1 | ADC_CFGR1_EXTSEL_2
| ADC_CFGR1_CONT; /* (2) */
ADC1->CHSELR = ADC_CHSELR_CHSEL0 | ADC_CHSELR_CHSEL1
| ADC_CHSELR_CHSEL2 | ADC_CHSELR_CHSEL3; /* (3)*/
ADC1->IER = ADC_IER_EOCIE | ADC_IER_EOSEQIE | ADC_IER_OVRIE; /* (4) */
/* Configure NVIC for ADC */
/* (1) Enable Interrupt on ADC */
/* (2) Set priority for ADC */
NVIC_EnableIRQ(ADC1_COMP_IRQn); /* (1) */
NVIC_SetPriority(ADC1_COMP_IRQn,0); /* (2) */

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A.7.9

Code examples

DMA one shot mode sequence code example
/* (1) Enable the peripheral clock on DMA */
/* (2) Enable DMA transfer on ADC - DMACFG is kept at 0
for one shot mode */
/* (3) Configure the peripheral data register address */
/* (4) Configure the memory address */
/* (5) Configure the number of DMA tranfer to be performs
on DMA channel 1 */
/* (6) Configure increment, size and interrupts */
/* (7) Enable DMA Channel 1 */
RCC->AHBENR |= RCC_AHBENR_DMA1EN; /* (1) */
ADC1->CFGR1 |= ADC_CFGR1_DMAEN; /* (2) */
DMA1_Channel1->CPAR = (uint32_t) (&(ADC1->DR)); /* (3) */
DMA1_Channel1->CMAR = (uint32_t)(ADC_array); /* (4) */
DMA1_Channel1->CNDTR = NUMBER_OF_ADC_CHANNEL; /* (5) */
DMA1_Channel1->CCR |= DMA_CCR_MINC | DMA_CCR_MSIZE_0 | DMA_CCR_PSIZE_0
| DMA_CCR_TEIE | DMA_CCR_TCIE ; /* (6) */
DMA1_Channel1->CCR |= DMA_CCR_EN; /* (7) */

A.7.10

DMA circular mode sequence code example
/*
/*
/*
/*
/*

Enable the peripheral clock on DMA */
Enable DMA transfer on ADC and circular mode */
Configure the peripheral data register address */
Configure the memory address */
Configure the number of DMA tranfer to be performs
on DMA channel 1 */
/* (6) Configure increment, size, interrupts and circular mode */
/* (7) Enable DMA Channel 1 */
RCC->AHBENR |= RCC_AHBENR_DMA1EN; /* (1) */
ADC1->CFGR1 |= ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG; /* (2) */
DMA1_Channel1->CPAR = (uint32_t) (&(ADC1->DR)); /* (3) */
DMA1_Channel1->CMAR = (uint32_t)(ADC_array); /* (4) */
DMA1_Channel1->CNDTR = NUMBER_OF_ADC_CHANNEL; /* (5) */
DMA1_Channel1->CCR |= DMA_CCR_MINC | DMA_CCR_MSIZE_0 | DMA_CCR_PSIZE_0
| DMA_CCR_TEIE | DMA_CCR_CIRC; /* (6) */
DMA1_Channel1->CCR |= DMA_CCR_EN; /* (7) */

A.7.11

(1)
(2)
(3)
(4)
(5)

Wait mode sequence code example
/* (1) Select HSI14 by writing 00 in CKMODE (reset value) */
/* (2) Select the continuous mode and the wait mode */
/* (3) Select CHSEL1/2/3 */
ADC1->CFGR2 &= ~ADC_CFGR2_CKMODE; /* (1) */
ADC1->CFGR1 |= ADC_CFGR1_CONT | ADC_CFGR1_WAIT; /* (2) */
ADC1->CHSELR = ADC_CHSELR_CHSEL1 | ADC_CHSELR_CHSEL2
| ADC_CHSELR_CHSEL3; /* (3)*/
ADC1->CR |= ADC_CR_ADSTART; /* start the ADC conversions */

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A.7.12

RM0360

Auto Off and no wait mode sequence code example
/* (1) Select HSI14 by writing 00 in CKMODE (reset value) */
/* (2) Select the external trigger on TIM15_TRGO and rising edge
and auto off */
/* (3) Select CHSEL1/2/3/4 */
/* (4) Enable interrupts on EOC, EOSEQ and overrrun */
ADC1->CFGR2 &= ~ADC_CFGR2_CKMODE; /* (1) */
ADC1->CFGR1 |= ADC_CFGR1_EXTEN_1 | ADC_CFGR1_EXTSEL_2
| ADC_CFGR1_AUTOFF; /* (2) */
ADC1->CHSELR = ADC_CHSELR_CHSEL1 | ADC_CHSELR_CHSEL2
| ADC_CHSELR_CHSEL3 | ADC_CHSELR_CHSEL4; /* (3) */
ADC1->IER = ADC_IER_EOCIE | ADC_IER_EOSEQIE | ADC_IER_OVRIE; /* (4) */

A.7.13

Auto Off and wait mode sequence code example
/* (1) Select HSI14 by writing 00 in CKMODE (reset value) */
/* (2) Select the external trigger on TIM15_TRGO and falling edge,
the continuous mode, scanning direction and auto off */
/* (3) Select CHSEL1, CHSEL9, CHSEL10 and CHSEL17 */
/* (4) Enable interrupts on EOC, EOSEQ and overrrun */
ADC1->CFGR2 &= ~ADC_CFGR2_CKMODE; /* (1) */
ADC1->CFGR1 |= ADC_CFGR1_EXTEN_0 | ADC_CFGR1_EXTSEL_2
| ADC_CFGR1_SCANDIR | ADC_CFGR1_AUTOFF; /* (2) */
ADC1->CHSELR = ADC_CHSELR_CHSEL1 | ADC_CHSELR_CHSEL2
| ADC_CHSELR_CHSEL3 | ADC_CHSELR_CHSEL4; /* (3) */
ADC1->IER = ADC_IER_EOCIE | ADC_IER_EOSEQIE | ADC_IER_OVRIE; /* (4) */

A.7.14

Analog watchdog code example
/* (1) Select the continuous mode
and configure the Analog watchdog to monitor only CH17 */
/* (2) Define analog watchdog range : 16b-MSW is the high limit
and 16b-LSW is the low limit */
/* (3) Enable interrupt on Analog Watchdog */
ADC1->CFGR1 |= ADC_CFGR1_CONT
| (17 << 26) | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL; /* (1) */
ADC1->TR = (vrefint_high << 16) + vrefint_low; /* (2)*/
ADC1->IER = ADC_IER_AWDIE; /* (3) */

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A.7.15

Code examples

Temperature configuration code example
/* (1) Select CHSEL16 for temperature sensor */
/* (2) Select a sampling mode of 111 i.e. 239.5 ADC clk to be greater than
17.1us */
/* (3) Wake-up the Temperature sensor (only for VBAT, Temp sensor and
VRefInt) */
ADC1->CHSELR = ADC_CHSELR_CHSEL16; /* (1) */
ADC1->SMPR |= ADC_SMPR_SMP_0 | ADC_SMPR_SMP_1 | ADC_SMPR_SMP_2; /* (2) */
ADC->CCR |= ADC_CCR_TSEN; /* (3) */

A.7.16

Temperature computation code example
/* Temperature sensor calibration value address */
#define TEMP30_CAL_ADDR ((uint16_t*) ((uint32_t) 0x1FFFF7B8))
#define VDD_CALIB ((uint32_t) (3300))
#define VDD_APPLI ((uint32_t) (3000))
#define AVG_SLOPE ((uint32_t) (5336)) //AVG_SLOPE in ADC conversion step
(@3.3V)/°C multiplied by 1000 for precision on the division
int32_t temperature; /* will contain the temperature in degrees Celsius */
temperature = ((uint32_t) *TEMP30_CAL_ADDR
- ((uint32_t) ADC1->DR * VDD_APPLI / VDD_CALIB)) * 1000;
temperature = (temperature / AVG_SLOPE) + 30;

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RM0360

A.8

Timers

A.8.1

Upcounter on TI2 rising edge code example
/*
/*
/*
/*

Enable the peripheral clock of Timer 1 */
Enable the peripheral clock of GPIOA */
Select Alternate function mode (10) on GPIOA pin 9 */
Select TIM1_CH2 on PA9 by enabling AF2 for pin 9 in GPIOA AFRH
register */
RCC->APB2ENR |= RCC_APB2ENR_TIM1EN; /* (1) */
RCC->AHBENR |= RCC_AHBENR_GPIOAEN; /* (2) */
GPIOA->MODER = (GPIOA->MODER & ~(GPIO_MODER_MODER9))
| (GPIO_MODER_MODER9_1); /* (3) */
GPIOA->AFR[1] |= 0x2 << ((9-8)*4); /* (4) */
/* (1) Configure channel 2 to detect rising edges on the TI2 input by
writing CC2S = ‘01’, and configure the input filter duration by
writing the IC2F[3:0] bits in the TIMx_CCMR1 register (if no filter
is needed, keep IC2F=0000).*/
/* (2) Select rising edge polarity by writing CC2P=0 in the TIMx_CCER
register (reset value). */
/* (3) Configure the timer in external clock mode 1 by writing SMS=111
Select TI2 as the trigger input source by writing TS=110
in the TIMx_SMCR register.*/
/* (4) Enable the counter by writing CEN=1 in the TIMx_CR1 register. */
TIMx->CCMR1 |= TIM_CCMR1_IC2F_0 | TIM_CCMR1_IC2F_1
| TIM_CCMR1_CC2S_0; /* (1) */
TIMx->CCER &= (uint16_t)(~TIM_CCER_CC2P); /* (2) */
TIMx->SMCR |= TIM_SMCR_SMS | TIM_SMCR_TS_2 | TIM_SMCR_TS_1; /* (3) */
TIMx->CR1 |= TIM_CR1_CEN; /* (4) */

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(2)
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A.8.2

Code examples

Up counter on each 2 ETR rising edges code example
/*
/*
/*
/*

Enable the peripheral clock of Timer 1 */
Enable the peripheral clock of GPIOA */
Select Alternate function mode (10) on GPIOA pin 12 */
Select TIM1_ETR on PA12 by enabling AF2 for pin 12 in GPIOA AFRH
register */
RCC->APB2ENR |= RCC_APB2ENR_TIM1EN; /* (1) */
RCC->AHBENR |= RCC_AHBENR_GPIOAEN; /* (2) */
GPIOA->MODER = (GPIOA->MODER & ~(GPIO_MODER_MODER12))
| (GPIO_MODER_MODER12_1); /* (3) */
GPIOA->AFR[1] |= 0x2 << ((12-8)*4); /* (4) */
/* (1) As no filter is needed in this example, write ETF[3:0]=0000
in the TIMx_SMCR register. Keep the reset value.
Set the prescaler by writing ETPS[1:0]=01 in the TIMx_SMCR
register.
Select rising edge detection on the ETR pin by writing ETP=0
in the TIMx_SMCR register. Keep the reset value.
Enable external clock mode 2 by writing ECE=1 in the TIMx_SMCR
register. */
/* (2) Enable the counter by writing CEN=1 in the TIMx_CR1 register. */
TIMx->SMCR |= TIM_SMCR_ETPS_0 | TIM_SMCR_ECE; /* (1) */
TIMx->CR1 |= TIM_CR1_CEN; /* (2) */

A.8.3

(1)
(2)
(3)
(4)

Input capture configuration code example
/* (1) Select the active input TI1 (CC1S = 01),
program the input filter for 8 clock cycles (IC1F = 0011),
select the rising edge on CC1 (CC1P = 0, reset value)
and prescaler at each valid transition (IC1PS = 00, reset value) */
/* (2) Enable capture by setting CC1E */
/* (3) Enable interrupt on Capture/Compare */
/* (4) Enable counter */
TIMx->CCMR1 |= TIM_CCMR1_CC1S_0
| TIM_CCMR1_IC1F_0 | TIM_CCMR1_IC1F_1; /* (1)*/
TIMx->CCER |= TIM_CCER_CC1E; /* (2) */
TIMx->DIER |= TIM_DIER_CC1IE; /* (3) */
TIMx->CR1 |= TIM_CR1_CEN; /* (4) */

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A.8.4

RM0360

Input capture data management code example
This code must be inserted in the Timer interrupt subroutine.
if ((TIMx->SR & TIM_SR_CC1IF) != 0)
{
if ((TIMx->SR & TIM_SR_CC1OF) != 0) /* Check the overflow */
{
/* Overflow error management */
gap = 0; /* Reinitialize the laps computing */
TIMx->SR &= ~(TIM_SR_CC1OF | TIM_SR_CC1IF); /* Clear the flags */
return;
}
if (gap == 0) /* Test if it is the first rising edge */
{
counter0 = TIMx->CCR1; /* Read the capture counter which clears the
CC1ICF */
gap = 1; /* Indicate that the first rising edge has yet been detected */
}
else
{
counter1 = TIMx->CCR1; /* Read the capture counter which clears the
CC1ICF */
if (counter1 > counter0) /* Check capture counter overflow */
{
Counter = counter1 - counter0;
}
else
{
Counter = counter1 + 0xFFFF - counter0 + 1;
}
counter0 = counter1;
}
}
else
{
/* Unexpected Interrupt */
/* Manage an error for robust application */
}

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A.8.5

Code examples

PWM input configuration code example
/* (1) Select the active input TI1 for TIMx_CCR1 (CC1S = 01),
select the active input TI1 for TIMx_CCR2 (CC2S = 10) */
/* (2) Select TI1FP1 as valid trigger input (TS = 101)
configure the slave mode in reset mode (SMS = 100) */
/* (3) Enable capture by setting CC1E and CC2E
select the rising edge on CC1 and CC1N (CC1P = 0 and CC1NP = 0, reset
value),
select the falling edge on CC2 (CC2P = 1). */
/* (4) Enable interrupt on Capture/Compare 1 */
/* (5) Enable counter */
TIMx->CCMR1 |= TIM_CCMR1_CC1S_0 | TIM_CCMR1_CC2S_1; /* (1)*/
TIMx->SMCR |= TIM_SMCR_TS_2 | TIM_SMCR_TS_0
| TIM_SMCR_SMS_2; /* (2) */
TIMx->CCER |= TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC2P; /* (3) */
TIMx->DIER |= TIM_DIER_CC1IE; /* (4) */
TIMx->CR1 |= TIM_CR1_CEN; /* (5) */

A.8.6

PWM input with DMA configuration code example
/*
/*
/*
/*

(1)
(2)
(3)
(4)

Enable the peripheral clock on DMA */
Configure the peripheral data register address for DMA channel x */
Configure the memory address for DMA channel x */
Configure the number of DMA tranfers to be performed
on DMA channel x */
/* (5) Configure no increment (reset value), size (16-bits), interrupts,
transfer from peripheral to memory and circular mode
for DMA channel x */
/* (6) Enable DMA Channel x */
RCC->AHBENR |= RCC_AHBENR_DMA1EN; /* (1) */
DMA1_Channel2->CPAR = (uint32_t) (&(TIM1->CCR1)); /* (2) */
DMA1_Channel2->CMAR = (uint32_t)(&Period); /* (3) */
DMA1_Channel2->CNDTR = 1; /* (4) */
DMA1_Channel2->CCR |= DMA_CCR_MSIZE_0 | DMA_CCR_PSIZE_0
| DMA_CCR_TEIE | DMA_CCR_CIRC; /* (5) */
DMA1_Channel2->CCR |= DMA_CCR_EN; /* (6) */
/* repeat (2) to (6) for channel 3 */
DMA1_Channel3->CPAR = (uint32_t) (&(TIM1->CCR2)); /* (2) */
DMA1_Channel3->CMAR = (uint32_t)(&DutyCycle); /* (3) */
DMA1_Channel3->CNDTR = 1; /* (4) */
DMA1_Channel3->CCR |= DMA_CCR_MSIZE_0 | DMA_CCR_PSIZE_0
| DMA_CCR_TEIE | DMA_CCR_CIRC; /* (5) */
DMA1_Channel3->CCR |= DMA_CCR_EN; /* (6) */
/* Configure NVIC for DMA */
/* (7) Enable Interrupt on DMA Channels x */
/* (8) Set priority for DMA Channels x */
NVIC_EnableIRQ(DMA1_Channel2_3_IRQn); /* (7) */
NVIC_SetPriority(DMA1_Channel2_3_IRQn,3); /* (8) */

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A.8.7

RM0360

Output compare configuration code example
/*
/*
/*
/*

Set prescaler to 3, so APBCLK/4 i.e 12MHz */
Set ARR = 12000 -1 */
Set CCRx = ARR, as timer clock is 12MHz, an event occurs each 1 ms */
Select toggle mode on OC1 (OC1M = 011),
disable preload register on OC1 (OC1PE = 0, reset value) */
/* (5) Select active high polarity on OC1 (CC1P = 0, reset value),
enable the output on OC1 (CC1E = 1)*/
/* (6) Enable output (MOE = 1)*/
/* (7) Enable counter */
TIMx->PSC |= 3; /* (1) */
TIMx->ARR = 12000 - 1; /* (2) */
TIMx->CCR1 = 12000 - 1; /* (3) */
TIMx->CCMR1 |= TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_1; /* (4) */
TIMx->CCER |= TIM_CCER_CC1E; /* (5)*/
TIMx->BDTR |= TIM_BDTR_MOE; /* (6) */
TIMx->CR1 |= TIM_CR1_CEN; /* (7) */

A.8.8

(1)
(2)
(3)
(4)

Edge-aligned PWM configuration example
/*
/*
/*
/*

Set prescaler to 47, so APBCLK/48 i.e 1MHz */
Set ARR = 8, as timer clock is 1MHz the period is 9 us */
Set CCRx = 4, , the signal will be high during 4 us */
Select PWM mode 1 on OC1 (OC1M = 110),
enable preload register on OC1 (OC1PE = 1) */
/* (5) Select active high polarity on OC1 (CC1P = 0, reset value),
enable the output on OC1 (CC1E = 1)*/
/* (6) Enable output (MOE = 1)*/
/* (7) Enable counter (CEN = 1)
select edge aligned mode (CMS = 00, reset value)
select direction as upcounter (DIR = 0, reset value) */
/* (8) Force update generation (UG = 1) */
TIMx->PSC = 47; /* (1) */
TIMx->ARR = 8; /* (2) */
TIMx->CCR1 = 4; /* (3) */
TIMx->CCMR1 |= TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1
| TIM_CCMR1_OC1PE; /* (4) */
TIMx->CCER |= TIM_CCER_CC1E; /* (5) */
TIMx->BDTR |= TIM_BDTR_MOE; /* (6) */
TIMx->CR1 |= TIM_CR1_CEN; /* (7) */
TIMx->EGR |= TIM_EGR_UG; /* (8) */

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A.8.9

Code examples

Center-aligned PWM configuration example
/* (1) Set prescaler to 47, so APBCLK/48 i.e 1MHz */
/* (2) Set ARR = 8, as timer clock is 1MHz and center-aligned counting,
the period is 16 us */
/* (3) Set CCRx = 7, the signal will be high during 14 us */
/* (4) Select PWM mode 1 on OC1 (OC1M = 110),
enable preload register on OC1 (OC1PE = 1, reset value) */
/* (5) Select active high polarity on OC1 (CC1P = 0, reset value),
enable the output on OC1 (CC1E = 1)*/
/* (6) Enable output (MOE = 1)*/
/* (7) Enable counter (CEN = 1)
select center-aligned mode 1 (CMS = 01) */
/* (8) Force update generation (UG = 1) */
TIMx->PSC = 47; /* (1) */
TIMx->ARR = 8; /* (2) */
TIMx->CCR1 = 7; /* (3) */
TIMx->CCMR1 |= TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1
| TIM_CCMR1_OC1PE; /* (4) */
TIMx->CCER |= TIM_CCER_CC1E; /* (5) */
TIMx->BDTR |= TIM_BDTR_MOE; /* (6) */
TIMx->CR1 |= TIM_CR1_CMS_0 | TIM_CR1_CEN; /* (7) */
TIMx->EGR |= TIM_EGR_UG; /* (8) */

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RM0360

ETR configuration to clear OCxREF code example
/* This code is similar to the edge-aligned PWM configuration but it enables
the clearing on OC1 for ETRclearing (OC1CE = 1) in CCMR1 (5) and ETR is
configured in SMCR (7).*/
/* (1) Set prescaler to 47, so APBCLK/48 i.e 1MHz */
/* (2) Set ARR = 8, as timer clock is 1MHz the period is 9 us */
/* (3) Set CCRx = 4, , the signal will be high during 4 us */
/* (4) Select PWM mode 1 on OC1 (OC1M = 110),
enable preload register on OC1 (OC1PE = 1),
enable clearing on OC1 for ETR clearing (OC1CE = 1) */
/* (5) Select active high polarity on OC1 (CC1P = 0, reset value),
enable the output on OC1 (CC1E = 1) */
/* (6) Enable output (MOE = 1) */
/* (7) Select ETR as OCREF clear source (OCCS = 1),
select External Trigger Prescaler off (ETPS = 00, reset value),
disable external clock mode 2 (ECE = 0, reset value),
select active at high level (ETP = 0, reset value) */
/* (8) Enable counter (CEN = 1),
select edge aligned mode (CMS = 00, reset value),
select direction as upcounter (DIR = 0, reset value) */
/* (9) Force update generation (UG = 1) */
TIMx->PSC = 47; /* (1) */
TIMx->ARR = 8; /* (2) */
TIMx->CCR1 = 4; /* (3) */
TIMx->CCMR1 |= TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1PE
| TIM_CCMR1_OC1CE; /* (4) */
TIMx->CCER |= TIM_CCER_CC1E; /* (5) */
TIMx->BDTR |= TIM_BDTR_MOE; /* (6) */
TIMx->SMCR |= TIM_SMCR_OCCS; /* (7) */
TIMx->CR1 |= TIM_CR1_CEN; /* (8) */
TIMx->EGR |= TIM_EGR_UG; /* (9) */

A.8.11

Encoder interface code example
/* (1) Configure TI1FP1 on TI1 (CC1S = 01),
configure TI1FP2 on TI2 (CC2S = 01) */
/* (2) Configure TI1FP1 and TI1FP2 non inverted (CC1P = CC2P = 0, reset
value) */
/* (3) Configure both inputs are active on both rising and falling edges
(SMS = 011) */
/* (4) Enable the counter by writing CEN=1 in the TIMx_CR1 register. */
TIMx->CCMR1 |= TIM_CCMR1_CC1S_0 | TIM_CCMR1_CC2S_0; /* (1)*/
TIMx->CCER &= (uint16_t)(~(TIM_CCER_CC21 | TIM_CCER_CC2P); /* (2) */
TIMx->SMCR |= TIM_SMCR_SMS_0 | TIM_SMCR_SMS_1; /* (3) */
TIMx->CR1 |= TIM_CR1_CEN; /* (4) */

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Code examples

Reset mode code example
/* (1) Configure channel 1 to detect rising edges on the TI1 input
by writing CC1S = ‘01’,
and configure the input filter duration by writing the IC1F[3:0]
bits in the TIMx_CCMR1 register (if no filter is needed, keep
IC1F=0000).*/
/* (2) Select rising edge polarity by writing CC1P=0 in the TIMx_CCER
register
Not necessary as it keeps the reset value. */
/* (3) Configure the timer in reset mode by writing SMS=100
Select TI1 as the trigger input source by writing TS=101
in the TIMx_SMCR register.*/
/* (4) Set prescaler to 48000-1 in order to get an increment each 1ms */
/* (5) Enable the counter by writing CEN=1 in the TIMx_CR1 register. */
TIMx->CCMR1 |= TIM_CCMR1_CC1S_0; /* (1)*/
TIMx->CCER &= (uint16_t)(~TIM_CCER_CC1P); /* (2) */
TIMx->SMCR |= TIM_SMCR_SMS_2 | TIM_SMCR_TS_2 | TIM_SMCR_TS_0; /* (3) */
TIM1->PSC = 47999; /* (4) */
TIMx->CR1 |= TIM_CR1_CEN; /* (5) */

A.8.13

Gated mode code example
/* (1) Configure channel 1 to detect low level on the TI1 input
by writing CC1S = ‘01’,
and configure the input filter duration by writing the IC1F[3:0]
bits in the TIMx_CCMR1 register (if no filter is needed,
keep IC1F=0000). */
/* (2) Select polarity by writing CC1P=1 in the TIMx_CCER register */
/* (3) Configure the timer in gated mode by writing SMS=101
Select TI1 as the trigger input source by writing TS=101
in the TIMx_SMCR register. */
/* (4) Set prescaler to 12000-1 in order to get an increment each 250us */
/* (5) Enable the counter by writing CEN=1 in the TIMx_CR1 register. */
TIMx->CCMR1 |= TIM_CCMR1_CC1S_0; /* (1)*/
TIMx->CCER |= TIM_CCER_CC1P; /* (2) */
TIMx->SMCR |= TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0
| TIM_SMCR_TS_2 | TIM_SMCR_TS_0; /* (3) */
TIMx->PSC = 11999; /* (4) */
TIMx->CR1 |= TIM_CR1_CEN; /* (5) */

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Trigger mode code example
/* (1) Configure channel 2 to detect rising edge on the TI2 input
by writing CC2S = ‘01’,
and configure the input filter duration by writing the IC1F[3:0]
bits in the TIMx_CCMR1 register (if no filter is needed,
keep IC1F=0000). */
/* (2) Select polarity by writing CC2P=0 (reset value) in the TIMx_CCER
register */
/* (3) Configure the timer in trigger mode by writing SMS=110
Select TI2 as the trigger input source by writing TS=110
in the TIMx_SMCR register. */
/* (4) Set prescaler to 12000-1 in order to get an increment each 250us */
TIMx->CCMR1 |= TIM_CCMR1_CC2S_0; /* (1)*/
TIMx->CCER &= ~TIM_CCER_CC2P; /* (2) */
TIMx->SMCR |= TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1
| TIM_SMCR_TS_2 | TIM_SMCR_TS_1; /* (3) */
TIM1->PSC = 11999; /* (4) */

A.8.15

External clock mode 2 + trigger mode code example
/* (1) Configure no input filter (ETF=0000, reset value)
configure prescaler disabled (ETPS = 0, reset value)
select detection on rising edge on ETR (ETP = 0, reset value)
enable external clock mode 2 (ECE = 1) */
/* (2) Configure no input filter (IC1F=0000, reset value)
select input capture source on TI1 (CC1S = 01) */
/* (3) Select polarity by writing CC1P=0 (reset value) in the TIMx_CCER
register */
/* (4) Configure the timer in trigger mode by writing SMS=110
Select TI1 as the trigger input source by writing TS=101
in the TIMx_SMCR register. */
TIMx->SMCR |= TIM_SMCR_ECE; /* (1) */
TIMx->CCMR1 |= TIM_CCMR1_CC1S_0; /* (2)*/
TIMx->CCER &= ~TIM_CCER_CC1P; /* (3) */
TIMx->SMCR |= TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1
| TIM_SMCR_TS_2 | TIM_SMCR_TS_0; /* (4) */
/* Use TI2FP2 as trigger 1 */
/* (1) Map TI2FP2 on TI2 by writing CC2S=01 in the TIMx_CCMR1 register */
/* (2) TI2FP2 must detect a rising edge, write CC2P=0 and CC2NP=0
in the TIMx_CCER register (keep the reset value) */
/* (3) Configure TI2FP2 as trigger for the slave mode controller (TRGI)
by writing TS=110 in the TIMx_SMCR register,
TI2FP2 is used to start the counter by writing SMS to ‘110'
in the TIMx_SMCR register (trigger mode) */
TIMx->CCMR1 |= TIM_CCMR1_CC2S_0; /* (1) */
//TIMx->CCER &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); /* (2) */
TIMx->SMCR |= TIM_SMCR_TS_2 | TIM_SMCR_TS_1
| TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1; /* (3) */

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Code examples

One-Pulse mode code example
/*
/*
/*
/*
/*

OPM waveform is defined by writing the compare registers */
Set prescaler to 47, so APBCLK/48 i.e 1MHz */
Set ARR = 7, as timer clock is 1MHz the period is 8 us */
Set CCRx = 5, the burst will be delayed for 5 us (must be > 0) */
Select PWM mode 2 on OC1 (OC1M = 111),
enable preload register on OC1 (OC1PE = 1, reset value)
enable fast enable (no delay) if PULSE_WITHOUT_DELAY is set */
/* (5) Select active high polarity on OC1 (CC1P = 0, reset value),
enable the output on OC1 (CC1E = 1) */
/* (6) Enable output (MOE = 1) */
/* (7) Write '1 in the OPM bit in the TIMx_CR1 register to stop the counter
at the next update event (OPM = 1),
enable auto-reload register(ARPE = 1) */
TIMx->PSC = 47; /* (1) */
TIMx->ARR = 7; /* (2) */
TIMx->CCR1 = 5; /* (3) */
TIMx->CCMR1 |= TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0
| TIM_CCMR1_OC1PE
#if PULSE_WITHOUT_DELAY > 0
| TIM_CCMR1_OC1FE
#endif
; /* (4) */
TIMx->CCER |= TIM_CCER_CC1E; /* (5) */
TIMx->BDTR |= TIM_BDTR_MOE; /* (6) */
TIMx->CR1 |= TIM_CR1_OPM | TIM_CR1_ARPE; /* (7) */

A.8.17

The
(1)
(2)
(3)
(4)

Timer prescaling another timer code example
/* TIMy is slave of TIMx */
/* (1) Select Update Event as Trigger output (TRG0) by writing MMS = 010
in TIMx_CR2. */
/* (2) Configure TIMy in slave mode using ITR1 as internal trigger
by writing TS = 000 in TIMy_SMCR (reset value)
Configure TIMy in external clock mode 1, by writing SMS=111 in the
TIMy_SMCR register. */
/* (3) Set TIMx prescaler to 47999 in order to get an increment each 1ms */
/* (4) Set TIMx Autoreload to 999 in order to get an overflow (so an UEV)
each second */
/* (5) Set TIMx Autoreload to 24*3600-1 in order to get an overflow each 24hour */
/* (6) Enable the counter by writing CEN=1 in the TIMx_CR1 register. */
/* (7) Enable the counter by writing CEN=1 in the TIMy_CR1 register. */
TIMx->CR2 |= TIM_CR2_MMS_1; /* (1) */
TIMy->SMCR |= TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0; /* (2) */
TIMx->PSC = 47999; /* (3) */
TIMx->ARR = 999; /* (4) */
TIMy->ARR = (24 * 3600) - 1; /* (5) */
TIMx->CR1 |= TIM_CR1_CEN; /* (6) */
TIMy->CR1 |= TIM_CR1_CEN; /* (7) */

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RM0360

Timer enabling another timer code example
/* TIMy is slave of TIMx */
/* (1) Configure Timer x master mode to send its Output Compare 1 Reference
(OC1REF) signal as trigger output
(MMS=100 in the TIM1_CR2 register). */
/* (2) Configure the Timer x OC1REF waveform (TIM1_CCMR1 register)
Channel 1 is in PWM mode 1 when the counter is less than the
capture/compare register (write OC1M = 110) */
/* (3) Configure TIMy in slave mode using ITR1 as internal trigger
by writing TS = 000 in TIMy_SMCR (reset value)
Configure TIMy in gated mode, by writing SMS=101 in the
TIMy_SMCR register. */
/* (4) Set TIMx prescaler to 2 */
/* (5) Set TIMy prescaler to 2 */
/* (6) Set TIMx Autoreload to 999 in order to get an overflow (so an UEV)
each 100ms */
/* (7) Set capture compare register to a value between 0 and 999 */
TIMx->CR2 |= TIM_CR2_MMS_2; /* (1) */
TIMx->CCMR1 |= TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1; /* (2) */
TIMy->SMCR |= TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0; /* (3) */
TIMx->PSC = 2; /* (4) */
TIMy->PSC = 2; /* (5) */
TIMx->ARR = 999; /* (6) */
TIMx-> CCR1 = 700; /* (7) */
/* Configure the slave timer to generate toggling on each count */
/* (1) Configure the TIMy in PWM mode 1 (write OC1M = 110) */
/* (2) Set TIMy Autoreload to 1 */
/* (3) Set capture compare register to 1 */
TIMy->CCMR1 |= TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1; /* (1) */
TIMy->ARR = 1; /* (2) */
TIMy-> CCR1 = 1; /* (3) */
/* Enable the output of TIMx OC1 */
/* (1) Select active high polarity on OC1 (CC1P = 0, reset value),
enable the output on OC1 (CC1E = 1) */
/* (2) Enable output (MOE = 1) */
TIMx->CCER |= TIM_CCER_CC1E; /* (1) */
TIMx->BDTR |= TIM_BDTR_MOE; /* (2) */
/* Enable the output of TIMy OC1 */
/* (1) Select active high polarity on OC1 (CC1P = 0, reset value),
enable the output on OC1 (CC1E = 1) */
/* (2) Enable output (MOE = 1) */
TIMy->CCER |= TIM_CCER_CC1E; /* (1) */
TIMy->BDTR |= TIM_BDTR_MOE; /* (2) */
/* (1) Enable the slave counter first by writing CEN=1
in the TIMy_CR1 register. */
/* (2) Enable the master counter by writing CEN=1
in the TIMx_CR1 register. */
TIMy->CR1 |= TIM_CR1_CEN; /* (1) */
TIMx->CR1 |= TIM_CR1_CEN; /* (2) */

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Code examples

Master and slave synchronization code example
/* (1) Configure Timer x master mode to send its enable signal
as trigger output (MMS=001 in the TIM1_CR2 register). */
/* (2) Configure the Timer x Channel 1 waveform (TIM1_CCMR1 register)
is in PWM mode 1 (write OC1M = 110) */
/* (3) Configure TIMy in slave mode using ITR1 as internal trigger
by writing TS = 000 in TIMy_SMCR (reset value)
Configure TIMy in gated mode, by writing SMS=101 in the
TIMy_SMCR register. */
/* (4) Set TIMx prescaler to 2 */
/* (5) Set TIMy prescaler to 2 */
/* (6) Set TIMx Autoreload to 99 in order to get an overflow (so an UEV)
each 10ms */
/* (7) Set capture compare register to a value between 0 and 99 */
TIMx->CR2 |= TIM_CR2_MMS_0; /* (1) */
TIMx->CCMR1 |= TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1; /* (2) */
TIMy->SMCR |= TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0; /* (3) */
TIMx->PSC = 2; /* (4) */
TIMy->PSC = 2; /* (5) */
TIMx->ARR = 99; /* (6) */
TIMx-> CCR1 = 25; /* (7) */
/* Configure the slave timer Channel 1 as PWM as Timer
to show synchronicity */
/* (1) Configure the TIMy in PWM mode 1 (write OC1M = 110) */
/* (2) Set TIMy Autoreload to 99 */
/* (3) Set capture compare register to 25 */
TIMy->CCMR1 |= TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1; /* (1) */
TIMy->ARR = 99; /* (2) */
TIMy-> CCR1 = 25; /* (3) */
/* Enable the output of TIMx OC1 */
/* (1) Select active high polarity on OC1 (CC1P = 0, reset value),
enable the output on OC1 (CC1E = 1)*/
/* (2) Enable output (MOE = 1) */
TIMx->CCER |= TIM_CCER_CC1E; /* (1) */
TIMx->BDTR |= TIM_BDTR_MOE; /* (2) */
/* Enable the output of TIMy OC1 */
/* (1) Select active high polarity on OC1 (CC1P = 0, reset value),
enable the output on OC1 (CC1E = 1) */
/* (2) Enable output (MOE = 1) */
TIMy->CCER |= TIM_CCER_CC1E; /* (1) */
TIMy->BDTR |= TIM_BDTR_MOE; /* (2) */
/* (1) Reset Timer x by writing ‘1 in UG bit (TIMx_EGR register) */
/* (2) Reset Timer y by writing ‘1 in UG bit (TIMy_EGR register) */
TIMx->EGR |= TIM_EGR_UG; /* (1) */
TIMy->EGR |= TIM_EGR_UG; /* (2) */
/* (1) Enable the slave counter first by writing CEN=1 in the TIMy_CR1
register.
TIMy will start synchronously with the master timer */
/* (2) Start the master counter by writing CEN=1
in the TIMx_CR1 register. */
TIMy->CR1 |= TIM_CR1_CEN; /* (1) */
TIMx->CR1 |= TIM_CR1_CEN; /* (2) */

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RM0360

Two timers synchronized by an external trigger code example
/* (1) Configure TIMx master mode to send its enable signal
as trigger output (MMS=001 in the TIM1_CR2 register). */
/* (2) Configure TIMx in slave mode to get the input trigger from TI1
by writing TS = 100 in TIMx_SMCR
Configure TIMx in trigger mode, by writing SMS=110 in the
TIMx_SMCR register.
Configure TIMx in Master/Slave mode by writing MSM = 1
in TIMx_SMCR */
/* (3) Configure TIMy in slave mode to get the input trigger from Timer1
by writing TS = 000 in TIMy_SMCR (reset value)
Configure TIMy in trigger mode, by writing SMS=110 in the
TIMy_SMCR register. */
/* (4) Reset Timer x counter by writing ‘1 in UG bit (TIMx_EGR register) */
/* (5) Reset Timer y counter by writing ‘1 in UG bit (TIMy_EGR register) */
TIMx->CR2 |= TIM_CR2_MMS_0; /* (1)*/
TIMx->SMCR |= TIM_SMCR_TS_2 | TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1
| TIM_SMCR_MSM; /* (2) */
TIMy->SMCR |= TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1; /* (3) */
TIMx->EGR |= TIM_EGR_UG; /* (4) */
TIMy->EGR |= TIM_EGR_UG; /* (5) */
/* Configure the Timer Channel 2 as PWM */
/* (1) Configure the Timer x Channel 2 waveform (TIM1_CCMR1 register)
is in PWM mode 1 (write OC2M = 110) */
/* (2) Set TIMx prescaler to 2 */
/* (3) Set TIMx Autoreload to 99 in order to get an overflow (so an UEV)
each 10ms */
/* (4) Set capture compare register to a value between 0 and 99 */
TIMx->CCMR1 |= TIM_CCMR1_OC2M_2 | TIM_CCMR1_OC2M_1; /* (1) */
TIMx->PSC = 2; /* (2) */
TIMx->ARR = 99; /* (3) */
TIMx->CCR2 = 25; /* (4) */
/* Configure the slave timer Channel 1 as PWM as Timer
to show synchronicity */
/* (1) Configure the TIMy in PWM mode 1 (write OC1M = 110) */
/* (2) Set TIMy prescaler to 2 */
/* (3) Set TIMx Autoreload to 99 */
/* (4) Set capture compare register to 25 */
TIMy->CCMR1 |= TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1; /* (1) */
TIMy->PSC = 2; /* (2) */
TIMy->ARR = 99; /* (3) */
TIMy-> CCR1 = 25; /* (4) */
/* Enable the output of TIMx OC1 */
/* (1) Select active high polarity on OC1 (CC1P = 0, reset value),
enable the output on OC1 (CC1E = 1)*/
/* (2) Enable output (MOE = 1)*/
TIMx->CCER |= TIM_CCER_CC2E; /* (1) */
TIMx->BDTR |= TIM_BDTR_MOE; /* (2) */
/* Enable the output of TIMy OC1 */
/* (1) Select active high polarity on OC1 (CC1P = 0, reset value),
enable the output on OC1 (CC1E = 1)*/
/* (2) Enable output (MOE = 1)*/
TIMy->CCER |= TIM_CCER_CC1E; /* (1) */
TIMy->BDTR |= TIM_BDTR_MOE; /* (2) */

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Code examples

DMA burst feature code example
/* In this example TIMx has been previously configured
in PWM center-aligned */
/* Configure DMA Burst Feature */
/* Configure the corresponding DMA channel */
/* (1) Set DMA channel peripheral address is the DMAR register address */
/* (2) Set DMA channel memory address is the address of the buffer
in the RAM containing the data to be transferred by DMA
into CCRx registers */
/* (3) Set the number of data transfer to sizeof(Duty_Cycle_Table) */
/* (4) Configure DMA transfer in CCR register,
enable the circular mode by setting CIRC bit (optional),
set memory size to 16_bits MSIZE = 01,
set peripheral size to 32_bits PSIZE = 10,
enable memory increment mode by setting MINC,
set data transfer direction read from memory by setting DIR. */
/* (5) Configure TIMx_DCR register with DBL = 3 transfers
and DBA = (@TIMx->CCR2 - @TIMx->CR1) >> 2 = 0xE */
/* (6) Enable the TIMx update DMA request by setting UDE bit in DIER
register */
/* (7) Enable TIMx */
/* (8) Enable DMA channel */
DMA1_Channel2->CPAR = (uint32_t)(&(TIMx->DMAR)); /* (1) */
DMA1_Channel2->CMAR = (uint32_t)(Duty_Cycle_Table); /* (2) */
DMA1_Channel2->CNDTR = 10*3; /* (3) */
DMA1_Channel2->CCR |= DMA_CCR_CIRC | DMA_CCR_MSIZE_0 | DMA_CCR_PSIZE_1
| DMA_CCR_MINC | DMA_CCR_DIR; /* (4) */
TIMx->DCR = (3 << 8)
+ ((((uint32_t)(&TIMx->CCR2))
- ((uint32_t)(&TIMx->CR1))) >> 2); /* (5) */
TIMx->DIER |= TIM_DIER_UDE; /* (6) */
TIMx->CR1 |= TIM_CR1_CEN; /* (7) */
DMA1_Channel2->CCR |= DMA_CCR_EN; /* (8) */

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A.9

IRTIM code example

A.9.1

TIM16 and TIM17 configuration code example
/* The following configuration is for RC5 standard */
/* TIM16 is used for the enveloppe while TIM17 is used for the carrier */
#define TIM_ENV TIM16
#define TIM_CAR TIM17
/* (1) Enable the peripheral clocks of Timer 16 and 17 and SYSCFG */
/* (2) Enable the peripheral clock of GPIOB */
/* (3) Select alternate function mode on GPIOB pin 9 */
/* (4) Select AF0 on PB9 in AFRH for IR_OUT (reset value) */
/* (5) Enable the high sink driver capability by setting I2C_PB9_FM+ bit
in SYSCFG_CFGR1 */
RCC->APB2ENR |= RCC_APB2ENR_TIM16EN | RCC_APB2ENR_TIM17EN
| RCC_APB2ENR_SYSCFGCOMPEN; /* (1) */
RCC->AHBENR |= RCC_AHBENR_GPIOBEN; /* (2) */
GPIOB->MODER = (GPIOB->MODER & ~GPIO_MODER_MODER9)
| GPIO_MODER_MODER9_1; /* (3) */
GPIOB->AFR[1] &= ~(0x0F << ((9 - 8) * 4)); /* (4) */
SYSCFG->CFGR1 |= SYSCFG_CFGR1_I2C_FMP_PB9; /* (5) */
/* Configure TIM_CAR as carrier signal */
/* (1) Set prescaler to 1, so APBCLK i.e 48MHz */
/* (2) Set ARR = 1333, as timer clock is 48MHz the frequency is 36kHz */
/* (3) Set CCRx = 1333/4, , the signal will bhave a 25% duty cycle */
/* (4) Select PWM mode 1 on OC1 (OC1M = 110),
enable preload register on OC1 (OC1PE = 1) */
/* (5) Select active high polarity on OC1 (CC1P = 0, reset value),
enable the output on OC1 (CC1E = 1)*/
/* (6) Enable output (MOE = 1)*/
TIM_CAR->PSC = v; /* (1) */
TIM_CAR->ARR = 1333; /* (2) */
TIM_CAR->CCR1 = (uint16_t)(1333 / 4); /* (3) */
TIM_CAR->CCMR1 |= TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1
| TIM_CCMR1_OC1PE; /* (4) */
TIM_CAR->CCER |= TIM_CCER_CC1E; /* (5) */
TIM_CAR->BDTR |= TIM_BDTR_MOE; /* (6) */
/* Configure TIM_ENV is the modulation enveloppe */
/* (1) Set prescaler to 1, so APBCLK i.e 48MHz */
/* (2) Set ARR = 42627, as timer clock is 48MHz the period is 888 us */
/* (3) Select Forced inactive on OC1 (OC1M = 100) */
/* (4) Select active high polarity on OC1 (CC1P = 0, reset value),
enable the output on OC1 (CC1E = 1) */
/* (5) Enable output (MOE = 1) */
/* (6) Enable Update interrupt (UIE = 1) */
TIM_ENV->PSC = 0; /* (1) */
TIM_ENV->ARR = 42627; /* (2) */
TIM_ENV->CCMR1 |= TIM_CCMR1_OC1M_2; /* (3) */
TIM_ENV->CCER |= TIM_CCER_CC1E; /* (4) */
TIM_ENV->BDTR |= TIM_BDTR_MOE; /* (5) */
TIM_ENV->DIER |= TIM_DIER_UIE; /* (6) */
/* Enable and reset TIM_CAR only */
/* (1) Enable counter (CEN = 1),
select edge aligned mode (CMS = 00, reset value),
select direction as upcounter (DIR = 0, reset value) */

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/* (2) Force update generation (UG = 1) */
TIM_CAR->CR1 |= TIM_CR1_CEN; /* (1) */
TIM_CAR->EGR |= TIM_EGR_UG; /* (2) */
/* Configure TIM_ENV interrupt */
/* (1) Enable Interrupt on TIM_ENV */
/* (2) Set priority for TIM_ENV */
NVIC_EnableIRQ(TIM_ENV_IRQn); /* (1) */
NVIC_SetPriority(TIM_ENV_IRQn,0); /* (2) */

A.9.2

IRQHandler for IRTIM code example
/**
* Description: This function handles TIM_16 interrupt request.
*
This interrupt subroutine computes the laps between 2
*
rising edges on T1IC.
*
This laps is stored in the "Counter" variable.
*/
void TIM16_IRQHandler(void)
{
uint8_t bit_msg = 0;
if ((SendOperationReady == 1)
&& (BitsSentCounter < (RC5_GlobalFrameLength * 2)))
{
if (BitsSentCounter < 32)
{
SendOperationCompleted = 0x00;
bit_msg = (uint8_t)((ManchesterCodedMsg >> BitsSentCounter)& 1);
if (bit_msg== 1)
{
/* Force active level - OC1REF is forced high */
TIM_ENV->CCMR1 |= TIM_CCMR1_OC1M_0;
}
else
{
/* Force inactive level - OC1REF is forced low */
TIM_ENV->CCMR1 &= (uint16_t)(~TIM_CCMR1_OC1M_0);
}
}
BitsSentCounter++;
}
else
{
SendOperationCompleted = 0x01;
SendOperationReady = 0;
BitsSentCounter = 0;
}
/* Clear TIM_ENV update interrupt */
TIM_ENV->SR &= (uint16_t)(~TIM_SR_UIF);
}

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A.10

DBG code example

A.10.1

DBG read device ID code example
/* Read MCU Id, 32-bit access */
MCU_Id = DBGMCU->IDCODE;

A.10.2

DBG debug in Low-power mode code example
/* To be able to debug in stop mode */
DBGMCU->CR |= DBGMCU_CR_DBG_STOP;

A.11

I2C code example

A.11.1

I2C configured in master mode to receive code example
/* (1) Timing register value is computed with the AN4235 xls file,
fast Mode @400kHz with I2CCLK = 48MHz, rise time = 140ns,
fall time = 40ns */
/* (2) Periph enable, receive interrupt enable */
/* (3) Slave address = 0x5A, read transfer, 1 byte to receive, autoend */
I2C2->TIMINGR = (uint32_t)0x00B01A4B; /* (1) */
I2C2->CR1 = I2C_CR1_PE | I2C_CR1_RXIE; /* (2) */
I2C2->CR2 = I2C_CR2_AUTOEND | (1<<16) | I2C_CR2_RD_WRN
| (I2C1_OWN_ADDRESS << 1); /* (3) */

A.11.2

I2C configured in master mode to transmit code example
/* (1) Timing register value is computed with the AN4235 xls file,
fast Mode @400kHz with I2CCLK = 48MHz, rise time = 140ns,
fall time = 40ns */
/* (2) Periph enable */
/* (3) Slave address = 0x5A, write transfer, 1 byte to transmit, autoend */
I2C2->TIMINGR = (uint32_t)0x00B01A4B; /* (1) */
I2C2->CR1 = I2C_CR1_PE; /* (2) */
I2C2->CR2 = I2C_CR2_AUTOEND | (1 << 16) | (I2C1_OWN_ADDRESS << 1); /* (3) */

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A.11.3

Code examples

I2C configured in slave mode code example
/* (1) Timing register value is computed with the AN4235 xls file,
fast Mode @400kHz with I2CCLK = 48MHz, rise time = 140ns,
fall time = 40ns */
/* (2) Periph enable, address match interrupt enable */
/* (3) 7-bit address = 0x5A */
/* (4) Enable own address 1 */
I2C1->TIMINGR = (uint32_t)0x00B00000; /* (1) */
I2C1->CR1 = I2C_CR1_PE | I2C_CR1_ADDRIE; /* (2) */
I2C1->OAR1 |= (uint32_t)(I2C1_OWN_ADDRESS << 1); /* (3) */
I2C1->OAR1 |= I2C_OAR1_OA1EN; /* (4) */

A.11.4

I2C master transmitter code example
/* Check Tx empty */
if ((I2C2->ISR & I2C_ISR_TXE) == I2C_ISR_TXE)
{
I2C2->TXDR = I2C_BYTE_TO_SEND; /* Byte to send */
I2C2->CR2 |= I2C_CR2_START; /* Go */
}

A.11.5

I2C master receiver code example
if ((I2C2->ISR & I2C_ISR_RXNE) == I2C_ISR_RXNE)
{
/* Read receive register, will clear RXNE flag */
if (I2C2->RXDR == I2C_BYTE_TO_SEND)
{
/* Process */
}
}

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A.11.6

RM0360

I2C slave transmitter code example
uint32_t I2C_InterruptStatus = I2C1->ISR; /* Get interrupt status */
/* Check address match */
if ((I2C_InterruptStatus & I2C_ISR_ADDR) == I2C_ISR_ADDR)
{
I2C1->ICR |= I2C_ICR_ADDRCF; /* Clear address match flag */
/* Check if transfer direction is read (slave transmitter) */
if ((I2C1->ISR & I2C_ISR_DIR) == I2C_ISR_DIR)
{
I2C1->CR1 |= I2C_CR1_TXIE; /* Set transmit IT */
}
}
else if ((I2C_InterruptStatus & I2C_ISR_TXIS) == I2C_ISR_TXIS)
{
I2C1->CR1 &=~ I2C_CR1_TXIE; /* Disable transmit IT */
I2C1->TXDR = I2C_BYTE_TO_SEND; /* Byte to send */
}

A.11.7

I2C slave receiver code example
uint32_t I2C_InterruptStatus = I2C1->ISR; /* Get interrupt status */
if ((I2C_InterruptStatus & I2C_ISR_ADDR) == I2C_ISR_ADDR)
{
I2C1->ICR |= I2C_ICR_ADDRCF; /* Address match event */
}
else if ((I2C_InterruptStatus & I2C_ISR_RXNE) == I2C_ISR_RXNE)
{
/* Read receive register, will clear RXNE flag */
if (I2C1->RXDR == I2C_BYTE_TO_SEND)
{
/* Process */
}
}

A.11.8

I2C configured in master mode to transmit with DMA code example
/* (1) Timing register value is computed with the AN4235 xls file,
fast Mode @400kHz with I2CCLK = 48MHz, rise time = 140ns,
fall time = 40ns */
/* (2) Periph enable */
/* (3) Slave address = 0x5A, write transfer, 2 bytes to transmit,
autoend */
I2C2->TIMINGR = (uint32_t)0x00B01A4B; /* (1) */
I2C2->CR1 = I2C_CR1_PE | I2C_CR1_TXDMAEN; /* (2) */
I2C2->CR2 = I2C_CR2_AUTOEND | (SIZE_OF_DATA << 16)
| (I2C1_OWN_ADDRESS << 1); /* (3) */

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A.11.9

Code examples

I2C configured in slave mode to receive with DMA code example
/* (1) Timing register value is computed with the AN4235 xls file,
fast Mode @400kHz with I2CCLK = 48MHz, rise time = 140ns,
fall time = 40ns */
/* (2) Periph enable, receive DMA enable */
/* (3) 7-bit address = 0x5A */
/* (4) Enable own address 1 */
I2C1->TIMINGR = (uint32_t)0x00B00000; /* (1) */
I2C1->CR1 = I2C_CR1_PE | I2C_CR1_RXDMAEN | I2C_CR1_ADDRIE; /* (2) */
I2C1->OAR1 |= (uint32_t)(I2C1_OWN_ADDRESS << 1); /* (3) */
I2C1->OAR1 |= I2C_OAR1_OA1EN; /* (4) */

A.12

IWDG code example

A.12.1

IWDG configuration code example
/* (1) Activate IWDG (not needed if done in option bytes) */
/* (2) Enable write access to IWDG registers */
/* (3) Set prescaler by 8 */
/* (4) Set reload value to have a rollover each 100ms */
/* (5) Check if flags are reset */
/* (6) Refresh counter */
IWDG->KR = IWDG_START; /* (1) */
IWDG->KR = IWDG_WRITE_ACCESS; /* (2) */
IWDG->PR = IWDG_PR_PR_0; /* (3) */
IWDG->RLR = IWDG_RELOAD; /* (4) */
while (IWDG->SR) /* (5) */
{
/* add time out here for a robust application */
}
IWDG->KR = IWDG_REFRESH; /* (6) */

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RM0360

IWDG configuration with window code example
/* (1) Activate IWDG (not needed if done in option bytes) */
/* (2) Enable write access to IWDG registers */
/* (3) Set prescaler by 8 */
/* (4) Set reload value to have a rollover each 100ms */
/* (5) Check if flags are reset */
/* (6) Set a 50ms window, this will refresh the IWDG */
IWDG->KR = IWDG_START; /* (1) */
IWDG->KR = IWDG_WRITE_ACCESS; /* (2) */
IWDG->PR = IWDG_PR_PR_0; /* (3) */
IWDG->RLR = IWDG_RELOAD; /* (4) */
while (IWDG->SR) /* (5) */
{
/* add time out here for a robust application */
}
IWDG->WINR = IWDG_RELOAD >> 1; /* (6) */

A.13

RTC code example

A.13.1

RTC calendar configuration code example
/* (1) Write access for RTC registers */
/* (2) Enable init phase */
/* (3) Wait until it is allow to modify RTC register values */
/* (4) set prescaler, 40kHz/128 => 312 Hz, 312Hz/312 => 1Hz */
/* (5) New time in TR */
/* (6) Disable init phase */
/* (7) Disable write access for RTC registers */
RTC->WPR = 0xCA; /* (1) */
RTC->WPR = 0x53; /* (1) */
RTC->ISR |= RTC_ISR_INIT; /* (2) */
while ((RTC->ISR & RTC_ISR_INITF) != RTC_ISR_INITF) /* (3) */
{
/* add time out here for a robust application */
}
RTC->PRER = 0x007F0137; /* (4) */
RTC->TR = RTC_TR_PM | Time; /* (5) */
RTC->ISR &=~ RTC_ISR_INIT; /* (6) */
RTC->WPR = 0xFE; /* (7) */
RTC->WPR = 0x64; /* (7) */

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A.13.2

Code examples

RTC alarm configuration code example
/* (1) Write access for RTC registers */
/* (2) Disable alarm A to modify it */
/* (3) Wait until it is allow to modify alarm A value */
/* (4) Modify alarm A mask to have an interrupt each 1Hz */
/* (5) Enable alarm A and alarm A interrupt */
/* (6) Disable write access */
RTC->WPR = 0xCA; /* (1) */
RTC->WPR = 0x53; /* (1) */
RTC->CR &=~ RTC_CR_ALRAE; /* (2) */
while ((RTC->ISR & RTC_ISR_ALRAWF) != RTC_ISR_ALRAWF) /* (3) */
{
/* add time out here for a robust application */
}
RTC->ALRMAR = RTC_ALRMAR_MSK4 | RTC_ALRMAR_MSK3
| RTC_ALRMAR_MSK2 | RTC_ALRMAR_MSK1; /* (4) */
RTC->CR = RTC_CR_ALRAIE | RTC_CR_ALRAE; /* (5) */
RTC->WPR = 0xFE; /* (6) */
RTC->WPR = 0x64; /* (6) */

A.13.3

RTC WUT configuration code example
/* (1) Write access for RTC registers */
/* (2) Disable wake up timerto modify it */
/* (3) Wait until it is allow to modify wake up reload value */
/* (4) Modify wake upvalue reload counter to have a wake up each 1Hz */
/* (5) Enable wake up counter and wake up interrupt */
/* (6) Disable write access */
RTC->WPR = 0xCA; /* (1) */
RTC->WPR = 0x53; /* (1) */
RTC->CR &= ~RTC_CR_WUTE; /* (2) */
while ((RTC->ISR & RTC_ISR_WUTWF) != RTC_ISR_WUTWF) /* (3) */
{
/* add time out here for a robust application */
}
RTC->WUTR = 0x9C0; /* (4) */
RTC->CR = RTC_CR_WUTE | RTC_CR_WUTIE; /* (5) */
RTC->WPR = 0xFE; /* (6) */
RTC->WPR = 0x64; /* (6) */

A.13.4

RTC read calendar code example
if((RTC->ISR & RTC_ISR_RSF) == RTC_ISR_RSF)
{
TimeToCompute = RTC->TR; /* get time */
DateToCompute = RTC->DR; /* need to read date also */
}

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A.13.5

RM0360

RTC calibration code example
/* (1) Write access for RTC registers */
/* (2) Enable init phase */
/* (3) Wait until it is allow to modify RTC register values */
/* (4) set prescaler, 40kHz/125 => 320 Hz, 320Hz/320 => 1Hz */
/* (5) New time in TR */
/* (6) Disable init phase */
/* (7) Wait until it's allow to modify calibartion register */
/* (8) Set calibration to around +20ppm, which is a standard value @25°C */
/* Note: the calibration is relevant when LSE is selected for RTC clock */
/* (9) Disable write access for RTC registers */
RTC->WPR = 0xCA; /* (1) */
RTC->WPR = 0x53; /* (1) */
RTC->ISR |= RTC_ISR_INIT; /* (2) */
while ((RTC->ISR & RTC_ISR_INITF) != RTC_ISR_INITF) /* (3) */
{
/* add time out here for a robust application */
}
RTC->PRER = (124<<16) | 319; /* (4) */
RTC->TR = RTC_TR_PM | Time; /* (5) */
RTC->ISR &=~ RTC_ISR_INIT; /* (6) */
while((RTC->ISR & RTC_ISR_RECALPF) == RTC_ISR_RECALPF) /* (7) */
{
/* add time out here for a robust application */
}
RTC->CALR = RTC_CALR_CALP | 482; /* (8) */
RTC->WPR = 0xFE; /* (9) */
RTC->WPR = 0x64; /* (9) */

A.13.6

RTC tamper and time stamp configuration code example
/* Tamper configuration:
- Disable precharge (PU)
- RTCCLK/256 tamper sampling frequency
- Activate time stamp on tamper detection
- input rising edge trigger detection on RTC_TAMP2 (PA0)
- Tamper interrupt enable */
RTC->TAFCR = RTC_TAFCR_TAMPPUDIS | RTC_TAFCR_TAMPFREQ | RTC_TAFCR_TAMPTS
| RTC_TAFCR_TAMP2E | RTC_TAFCR_TAMPIE;

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A.13.7

Code examples

RTC tamper and time stamp code example
/* Check tamper and timestamp flag */
if (((RTC->ISR & (RTC_ISR_TAMP2F)) == (RTC_ISR_TAMP2F))
&& ((RTC->ISR & (RTC_ISR_TSF)) == (RTC_ISR_TSF)))
{
RTC->ISR &= ~RTC_ISR_TAMP2F; /* clear tamper flag */
EXTI->PR = EXTI_PR_PR19; /* clear exti line 19 flag */
TimeToCompute = RTC->TSTR; /* get tamper time in timestamp register */
RTC->ISR &= ~RTC_ISR_TSF; /* clear timestamp flag */
}

A.13.8

RTC clock output code example
/*
/*
/*
/*
/*

(1)
(2)
(3)
(4)
(5)

Write access for RTC registers */
Disable alarm A to modify it */
Wait until it is allow to modify alarm A value */
Modify alarm A mask to have an interrupt each 1Hz */
Enable alarm A and alarm A interrupt,
enable calibration output (1Hz) */
/* (6) Disable write access */
RTC->WPR = 0xCA; /* (1) */
RTC->WPR = 0x53; /* (1) */
RTC->CR &=~ RTC_CR_ALRAE; /* (2) */
while ((RTC->ISR & RTC_ISR_ALRAWF) != RTC_ISR_ALRAWF) /* (3) */
{
/* add time out here for a robust application */
}
RTC->ALRMAR = RTC_ALRMAR_MSK4 | RTC_ALRMAR_MSK3
| RTC_ALRMAR_MSK2 | RTC_ALRMAR_MSK1; /* (4) */
RTC->CR = RTC_CR_ALRAIE | RTC_CR_ALRAE | RTC_CR_COE
| RTC_CR_COSEL; /* (5) */
RTC->WPR = 0xFE; /* (6) */
RTC->WPR = 0x64; /* (6) */

A.14

SPI code example

A.14.1

SPI master configuration code example
/* (1) Master selection, BR: Fpclk/256 (due to C27 on the board, SPI_CLK is
set to the minimum) CPOL and CPHA at zero (rising first edge) */
/* (2) Slave select output enabled, RXNE IT, 8-bit Rx fifo */
/* (3) Enable SPI1 */
SPI1->CR1 = SPI_CR1_MSTR | SPI_CR1_BR; /* (1) */
SPI1->CR2 = SPI_CR2_SSOE | SPI_CR2_RXNEIE | SPI_CR2_FRXTH
| SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0; /* (2) */
SPI1->CR1 |= SPI_CR1_SPE; /* (3) */

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A.14.2

RM0360

SPI slave configuration code example
/* nSS hard, slave, CPOL and CPHA at zero (rising first edge) */
/* (1) RXNE IT, 8-bit Rx fifo */
/* (2) Enable SPI2 */
SPI2->CR2 = SPI_CR2_RXNEIE | SPI_CR2_FRXTH
| SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0; /* (1) */
SPI2->CR1 |= SPI_CR1_SPE; /* (2) */

A.14.3

SPI full duplex communication code example
if ((SPI1->SR & SPI_SR_TXE) == SPI_SR_TXE) /* Test Tx empty */
{
/* Will inititiate 8-bit transmission if TXE */
*(uint8_t *)&(SPI1->DR) = SPI1_DATA;
}

A.14.4

SPI interrupt code example
if ((SPI1->SR & SPI_SR_RXNE) == SPI_SR_RXNE)
{
SPI1_Data = (uint8_t)SPI1->DR; /* receive data, clear flag */
/* Process */
}

A.14.5

SPI master configuration with DMA code example
/* (1) Master selection, BR: Fpclk/256 (due to C27 on the board, SPI_CLK is
set to the minimum)
CPOL and CPHA at zero (rising first edge) */
/* (2) TX and RX with DMA,
enable slave select output,
enable RXNE interrupt,
select 8-bit Rx fifo */
/* (3) Enable SPI1 */
SPI1->CR1 = SPI_CR1_MSTR | SPI_CR1_BR; /* (1) */
SPI1->CR2 = SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN | SPI_CR2_SSOE
| SPI_CR2_RXNEIE | SPI_CR2_FRXTH
| SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0; /* (2) */
SPI1->CR1 |= SPI_CR1_SPE; /* (3) */

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A.14.6

Code examples

SPI slave configuration with DMA code example
/* nSS hard, slave, CPOL and CPHA at zero (rising first edge) */
/* (1) Select TX and RX with DMA,
enable RXNE interrupt,
select 8-bit Rx fifo */
/* (2) Enable SPI2 */
SPI2->CR2 = SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN
| SPI_CR2_RXNEIE | SPI_CR2_FRXTH
| SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0; /* (1) */
SPI2->CR1 |= SPI_CR1_SPE; /* (2) */

A.15

USART code example

A.15.1

USART transmitter configuration code example
/* (1) Oversampling by 16,
/* (2) 8 data bit, 1 start
USART1->BRR = 480000 / 96;
USART1->CR1 = USART_CR1_TE

A.15.2

9600 baud */
bit, 1 stop bit, no parity */
/* (1) */
| USART_CR1_UE; /* (2) */

USART transmit byte code example
/* Start USART transmission */
USART1->TDR = stringtosend[send++]; /* Will inititiate TC if TXE is set*/

A.15.3

USART transfer complete code example
if ((USART1->ISR & USART_ISR_TC) == USART_ISR_TC)
{
if (send == sizeof(stringtosend))
{
send=0;
USART1->ICR |= USART_ICR_TCCF; /* Clear transfer complete flag */
}
else
{
/* clear transfer complete flag and fill TDR with a new char */
USART1->TDR = stringtosend[send++];
}
}

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A.15.4

RM0360

USART receiver configuration code example
/* (1) oversampling by 16, 9600 baud */
/* (2) 8 data bit, 1 start bit, 1 stop bit, no parity, reception mode */
USART1->BRR = 480000 / 96; /* (1) */
USART1->CR1 = USART_CR1_RXNEIE | USART_CR1_RE | USART_CR1_UE; /* (2) */

A.15.5

USART receive byte code example
if ((USART1->ISR & USART_ISR_RXNE) == USART_ISR_RXNE)
{
chartoreceive = (uint8_t)(USART1->RDR); /* Receive data, clear flag */
}

A.15.6

USART synchronous mode code example
/* (1) Oversampling by 16, 9600 baud */
/* (2) Synchronous mode
CPOL and CPHA = 0 => rising first edge
Last bit clock pulse
Most significant bit first in transmit/receive */
/* (3) 8 data bit, 1 start bit, 1 stop bit, no parity
Transmission enabled, reception enabled */
USART1->BRR = 480000 / 96; /* (1) */
USART1->CR2 = USART_CR2_MSBFIRST | USART_CR2_CLKEN
| USART_CR2_LBCL; /* (2) */
USART1->CR1 = USART_CR1_TE | USART_CR1_RXNEIE
| USART_CR1_RE | USART_CR1_UE; /* (3) */
/* Polling idle frame Transmission w/o clock */
while ((USART1->ISR & USART_ISR_TC) != USART_ISR_TC)
{
/* add time out here for a robust application */
}
USART1->ICR |= USART_ICR_TCCF; /* Clear TC flag */
USART1->CR1 |= USART_CR1_TCIE; /* Enable TC interrupt */

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A.15.7

Code examples

USART DMA code example
/* (1) Oversampling by 16, 9600 baud */
/* (2) Enable DMA in reception and transmission */
/* (3) 8 data bit, 1 start bit, 1 stop bit, no parity, reception and
transmission enabled */
USART1->BRR = 480000 / 96; /* (1) */
USART1->CR3 = USART_CR3_DMAT | USART_CR3_DMAR; /* (2) */
USART1->CR1 = USART_CR1_TE | USART_CR1_RE | USART_CR1_UE; /* (3) */
/* Polling idle frame Transmission */
while ((USART1->ISR & USART_ISR_TC) != USART_ISR_TC)
{
/* add time out here for a robust application */
}
USART1->ICR |= USART_ICR_TCCF; /* Clear TC flag */
USART1->CR1 |= USART_CR1_TCIE; /* Enable TC interrupt */

A.15.8

USART hardware flow control code example
/* (1) oversampling by 16, 9600 baud */
/* (2) RTS and CTS enabled */
/* (3) 8 data bit, 1 start bit, 1 stop bit, no parity, reception and
transmission enabled */
USART1->BRR = 480000 / 96; /* (1) */
USART1->CR3 = USART_CR3_RTSE | USART_CR3_CTSE; /* (2) */
USART1->CR1 = USART_CR1_TE | USART_CR1_RXNEIE
| USART_CR1_RE | USART_CR1_UE; /* (3) */
/* Polling idle frame Transmission */
while ((USART1->ISR & USART_ISR_TC) != USART_ISR_TC)
{
/* add time out here for a robust application */
}
USART1->ICR |= USART_ICR_TCCF; /* Clear TC flag */
USART1->CR1 |= USART_CR1_TCIE; /* Enable TC interrupt */

A.16

WWDG code example

A.16.1

WWDG configuration code example
/* (1) Set prescaler to have a roll-over each about 5.5ms,
set window value (about 2.25ms) */
/* (2) Refresh WWDG before activate it */
/* (3) Activate WWDG */
WWDG->CFR = 0x60; /* (1) */
WWDG->CR = WWDG_REFRESH; /* (2) */
WWDG->CR |= WWDG_CR_WDGA; /* (3) */

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Revision history

RM0360

Revision history
Table 117. Document revision history
Date

Revision

23-Sep-2013

1

Initial release

2

Extended the applicability to STM32F070x6/xB and
STM32F030x4/x6/x8/xC.
Added Chapter 30: Universal serial bus full-speed
device interface (USB) and reviewed the content of most
chapters.

3

Renamed TIM16 and TIM17 in the table TIMx internal
trigger connection in the section General purpose timer
(TIM15/16/17).
Updated Table 85: STM32F0x0 USART implementation
for STM32F070xB.
Added Section Appendix A: Code examples.
Updated:
– Bit 8 (DBP) description of PWR_CR register in
Section 6.4.1: Power control register (PWR_CR),
– TIM1_ARR reset value in Section 16.4.12: TIM1 autoreload register (TIM1_ARR),
– Bit 3 (TE) description of USART_ISR and Bit 21
description of USARTx_ISR in Section 26.8.8:
Interrupt and status register (USART_ISR).
– Bit SMS description for encoder mode 1 and encoder
mode 2 and added the last note in SMS bit description
in Section 16.4.3: TIM1 slave mode control register
(TIM1_SMCR), Section 17.4.3: TIM2 and TIM3 slave
mode control register (TIM2_SMCR and
TIM3_SMCR) and Section 19.5.3: TIM15 slave mode
control register (TIM15_SMCR)
– the description of ETF bits in Section 16.4.3: TIM1
slave mode control register (TIM1_SMCR) and
Section 17.4.3: TIM2 and TIM3 slave mode control
register (TIM2_SMCR and TIM3_SMCR).
– the description of IC1F[3:0] bits in Section 16.4.7:
TIM1 capture/compare mode register 1
(TIM1_CCMR1), Section 17.4.7: TIM2 and TIM3
capture/compare mode register 1 (TIM2_CCMR1 and
TIM3_CCMR1) and Section 19.5.7: TIM15
capture/compare mode register 1 (TIM15_CCMR1).

13-Jan-2015

19-May-2015

772/779

Changes

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Revision history
Table 117. Document revision history
Date

24-Apr-2017

Revision

Changes

4

– Section 4: Option bytes - note and description
CRC
– Feature list
RCC
– Section 7.4.9: RTC domain control register
(RCC_BDCR) - bit field LSEDRV
GPIO
– Section 8.4.9: GPIO alternate function low register
(GPIOx_AFRL) (x = A..D, ) and other AF registers AFR renamed to AFSEL
DMA
Section 10.4.2: DMA interrupt flag clear register
(DMA_IFCR) - bit description
Interrupt
– Section Table 32.: Vector table - removed “(combined
with EXTI line 28)” from row position 29
– Section 11.2.5: External and internal interrupt/event
line mapping - line 23 reserved
– Section 11.3.1: Interrupt mask register (EXTI_IMR) MRx bits renamed to IMx
– Section 11.3.2: Event mask register (EXTI_EMR) MRx bits renamed to EMx
– Section 11.3.3: Rising trigger selection register
(EXTI_RTSR) - TRx renamed to RTx and FTx; RT31
added
– Section 11.3.5: Software interrupt event register
(EXTI_SWIER) - SWIERx renamed to SWIx; SWI31
added
– Section 11.3.6: Pending register (EXTI_PR) - PRx
renamed to PIFx; PIF31 added
ADC
– Section 12.4.1: Calibration (ADCAL) - calibration
software procedure
– Section 12.4.2: ADC on-off control (ADEN, ADDIS,
ADRDY) - modified
– Section 12.4.9: Starting conversions (ADSTART) and
corresponding bit description
– Section Reading the temperature - added paragraphs
TIM1
– Section 13.3.12: Using the break function
TIM3
– removed redundant table before Table 49: TIM3
internal trigger connection
– Section 14.4.12: TIM3 auto-reload register
(TIM3_ARR) reset value
– corrected Table 51: TIM3 register map and reset
values
TIM6/TIM7
– Section 15.4.7: TIM6/TIM7 auto-reload register
(TIMx_ARR) reset value

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Date

24-Apr-2017

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Revision

Changes

4

TIM15/16/17
– Section 17.4.12: Using the break function - break
function
– corrected Table 17.6.10: TIM16 and TIM17 autoreload register (TIM16_ARR and TIM17_ARR)
IWDG
– added Section 19.3.4: Behavior in Stop and Standby
modes
– Section 19.4.4: Status register (IWDG_SR)
RTC
– Section 21.4.1: RTC block diagram - figures
– Section Programming the wakeup timer
– Section 21.4.9: Resetting the RTC
– Section 21.4.15: Calibration clock output
– Section 21.6: RTC interrupts - EXTI replaced with
NVIC
– Section 21.7.3: RTC control register (RTC_CR) bits
SUB1H and ADD1H; added caution at the end
– Section 21.7.4: RTC initialization and status register
(RTC_ISR) bit WUTWF
I2C
– Table 69: STM32F0x0 I2C implementation
– Table 70: Comparison of analog vs. digital filters
– Figure 201: Slave initialization flowchart
– Section I2C timings - multiple additions
– Section 22.4.9: I2C master mode - information on
STM32CubeMX
– Section : Master communication initialization (address
phase) - information on 10-bit addressing mode
– Section 22.7.2: Control register 2 (I2C_CR2) - bit
START - information on 10-bit addressing mode, and
bit fields SADD and ADDRCF
USART
– Table 85: STM32F0x0 USART implementation
– Section 23.4: USART functional description - removed
1.5 stop bits
– Table 91: Effect of low-power modes on the USART
– Table 92: USART interrupt requests
– Figure 244: USART interrupt mapping diagram
– Section 23.7.1: Control register 1 (USART_CR1)
– Section 23.7.2: Control register 2 (USART_CR2)
– Section 23.7.3: Control register 3 (USART_CR3)
– Section 23.7.7: Interrupt and status register
(USART_ISR)
– Section “Guard time and prescale register” removed
– Table 93: USART register map and reset values
Section “USART smartcard code example” removed

DocID025023 Rev 4

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Revision history
Table 117. Document revision history
Date

24-Apr-2017

Revision

Changes

4

SPI
– Table 94: STM32F0x0 SPI implementation
– Section 24.4.2: Communications between one master
and one slave - NSS pin
– Section Half-duplex communication
– Section Simplex communications
– Section 24.4.4: Multi-master communication
– Section 24.4.7: Configuration of SPI - point 1b
– Section 24.4.14: CRC calculation
– Section 24.6.1: SPI control register 1 (SPIx_CR1) bit
MSTR
– Section 24.6.6: SPI Rx CRC register (SPIx_RXCRCR)
and Section 24.6.7: SPI Tx CRC register
(SPIx_TXCRCR) - bits 15:0
Debug
– Table 109: DEV_ID and REV_ID field values added
Appendix
– Section A.4.2: Alternate function selection sequence
code example
– Section A.7.1: ADC Calibration code example
– Section A.7.2: ADC enable sequence code example
– Section A.7.3: ADC disable sequence code example
– Section A.7.14: Analog watchdog code example
– Section A.7.16: Temperature computation code
example
– Section A.8.21: DMA burst feature code example
– Sections “USART smartcard mode code example”
and “USART IrDA mode code example” removed

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Index

RM0360

Index
A

FMPI2C_ISR . . . . . . . . . . . . . . . . . . . . . . . . . 588

ADC_CCR . . . . . . . . . . . . . . . . . . . . . . . . . . .219
ADC_CFGR1 . . . . . . . . . . . . . . . . . . . . . . . . .212
ADC_CFGR2 . . . . . . . . . . . . . . . . . . . . . . . . .216
ADC_CHSELR . . . . . . . . . . . . . . . . . . . . . . . .218
ADC_CR . . . . . . . . . . . . . . . . . . . . . . . . . . . .210
ADC_DR . . . . . . . . . . . . . . . . . . . . . . . . . . . .218
ADC_IER . . . . . . . . . . . . . . . . . . . . . . . . . . . .208
ADC_ISR . . . . . . . . . . . . . . . . . . . . . . . . . . . .207
ADC_SMPR . . . . . . . . . . . . . . . . . . . . . . . . . .216
ADC_TR . . . . . . . . . . . . . . . . . . . . . . . . . . . . .217

C
CRC_CR
CRC_DR
CRC_IDR
CRC_INIT

. . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .73

D
DBGMCU_APB1_FZ . . . . . . . . . . . . . . . . . . .722
DBGMCU_APB2_FZ . . . . . . . . . . . . . . . . . . .724
DBGMCU_CR . . . . . . . . . . . . . . . . . . . . . . . .721
DBGMCU_IDCODE . . . . . . . . . . . . . . . . . . . .713
DMA_CCRx . . . . . . . . . . . . . . . . . . . . . . . . . .163
DMA_CMARx . . . . . . . . . . . . . . . . . . . . . . . . .166
DMA_CNDTRx . . . . . . . . . . . . . . . . . . . . . . . .165
DMA_CPARx . . . . . . . . . . . . . . . . . . . . . . . . .165
DMA_CSELR . . . . . . . . . . . . . . . . . . . . . . . . .167
DMA_IFCR . . . . . . . . . . . . . . . . . . . . . . . . . . .162
DMA_ISR . . . . . . . . . . . . . . . . . . . . . . . . . . . .161

E
EXTI_EMR . . . . . . . . . . . . . . . . . . . . . . . . . . .176
EXTI_FTSR . . . . . . . . . . . . . . . . . . . . . . . . . .177
EXTI_IMR . . . . . . . . . . . . . . . . . . . . . . . . . . . .176
EXTI_PR . . . . . . . . . . . . . . . . . . . . . . . . . . . .178
EXTI_RTSR . . . . . . . . . . . . . . . . . . . . . . . . . .176
EXTI_SWIER . . . . . . . . . . . . . . . . . . . . . . . . .178

F
FLASH_ACR . . . . . . . . . . . . . . . . . . . . . . . . . .58
FLASH_CR . . . . . . . . . . . . . . . . . . . . . . . . . . .60
FLASH_KEYR . . . . . . . . . . . . . . . . . . . . . . . . .58
FLASH_OPTKEYR . . . . . . . . . . . . . . . . . . . . .59
FLASH_SR . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
776/779

G
GPIOx_AFRH . . . . . . . . . . . . . . . . . . . . . . . . 141
GPIOx_AFRL . . . . . . . . . . . . . . . . . . . . . . . . 140
GPIOx_BRR . . . . . . . . . . . . . . . . . . . . . . . . . 141
GPIOx_BSRR . . . . . . . . . . . . . . . . . . . . . . . . 138
GPIOx_IDR . . . . . . . . . . . . . . . . . . . . . . . . . . 138
GPIOx_LCKR . . . . . . . . . . . . . . . . . . . . . . . . 139
GPIOx_MODER . . . . . . . . . . . . . . . . . . . . . . 136
GPIOx_ODR . . . . . . . . . . . . . . . . . . . . . . . . . 138
GPIOx_OSPEEDR . . . . . . . . . . . . . . . . . . . . 137
GPIOx_OTYPER . . . . . . . . . . . . . . . . . . . . . . 136
GPIOx_PUPDR . . . . . . . . . . . . . . . . . . . . . . . 137

I
I2C_CR1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 578
I2C_CR2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 581
I2C_ICR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 590
I2C_ISR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 588
I2C_OAR1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 584
I2C_OAR2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 585
I2C_PECR . . . . . . . . . . . . . . . . . . . . . . . . . . . 591
I2C_RXDR . . . . . . . . . . . . . . . . . . . . . . . . . . . 592
I2C_TIMEOUTR . . . . . . . . . . . . . . . . . . . . . . 587
I2C_TIMINGR . . . . . . . . . . . . . . . . . . . . . . . . 586
I2C_TXDR . . . . . . . . . . . . . . . . . . . . . . . . . . . 592
I2Cx_CR2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 581
IWDG_KR . . . . . . . . . . . . . . . . . . . . . . . . . . . 474
IWDG_PR . . . . . . . . . . . . . . . . . . . . . . . . . . . 475
IWDG_RLR . . . . . . . . . . . . . . . . . . . . . . . . . . 476
IWDG_SR . . . . . . . . . . . . . . . . . . . . . . . . . . . 477
IWDG_WINR . . . . . . . . . . . . . . . . . . . . . . . . . 478

P
PWR_CR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
PWR_CSR . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

R
RCC_AHBENR . . . . . . . . . . . . . . . . . . . . . . . 111
RCC_AHBRSTR . . . . . . . . . . . . . . . . . . . . . . 120
RCC_APB1ENR . . . . . . . . . . . . . . . . . . . . . . 114
RCC_APB1RSTR . . . . . . . . . . . . . . . . . . . . . 108
RCC_APB2ENR . . . . . . . . . . . . . . . . . . . . . . 112
RCC_APB2RSTR . . . . . . . . . . . . . . . . . . . . . 106

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Index

RCC_BDCR . . . . . . . . . . . . . . . . . . . . . . . . . .117
RCC_CFGR . . . . . . . . . . . . . . . . . . . . . . . . . .101
RCC_CFGR2 . . . . . . . . . . . . . . . . . . . . . . . . .122
RCC_CFGR3 . . . . . . . . . . . . . . . . . . . . . . . . .123
RCC_CIR . . . . . . . . . . . . . . . . . . . . . . . . . . . .104
RCC_CR . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
RCC_CR2 . . . . . . . . . . . . . . . . . . . . . . . . . . .123
RCC_CSR . . . . . . . . . . . . . . . . . . . . . . . . . . .119
RTC_ALRMAR . . . . . . . . . . . . . . . . . . . . . . . .513
RTC_CALR . . . . . . . . . . . . . . . . . . . . . . . . . .519
RTC_CR . . . . . . . . . . . . . . . . . . . . . . . . . . . . .506
RTC_DR . . . . . . . . . . . . . . . . . . . . . . . . . . . . .504
RTC_ISR . . . . . . . . . . . . . . . . . . . . . . . . . . . .509
RTC_PRER . . . . . . . . . . . . . . . . . . . . . . . . . .511
RTC_SHIFTR . . . . . . . . . . . . . . . . . . . . . . . . .515
RTC_SSR . . . . . . . . . . . . . . . . . . . . . . . . . . .514
RTC_TAFCR . . . . . . . . . . . . . . . . . . . . . . . . .520
RTC_TR . . . . . . . . . . . . . . . . . . . . . . . . . . . . .503
RTC_TSDR . . . . . . . . . . . . . . . . . . . . . . . . . .517
RTC_TSSSR . . . . . . . . . . . . . . . . . . . . . . . . .518
RTC_TSTR . . . . . . . . . . . . . . . . . . . . . . . . . .516
RTC_WPR . . . . . . . . . . . . . . . . . . . . . . . . . . .514
RTC_WUTR . . . . . . . . . . . . . . . . . . . . . . . . . .512

S
SPIx_CR1 . . . . . . . . . . . . . . . . . . . . . . . . . . .668
SPIx_CR2 . . . . . . . . . . . . . . . . . . . . . . . . . . .670
SPIx_CRCPR . . . . . . . . . . . . . . . . . . . . . . . . .674
SPIx_DR . . . . . . . . . . . . . . . . . . . . . . . . . . . .674
SPIx_RXCRCR . . . . . . . . . . . . . . . . . . . . . . .675
SPIx_SR . . . . . . . . . . . . . . . . . . . . . . . . . . . . .673
SPIx_TXCRCR . . . . . . . . . . . . . . . . . . . . . . . .675
SYSCFG_CFGR1 . . . . . . . . . . . . . . . . . . . . .144
SYSCFG_CFGR2 . . . . . . . . . . . . . . . . . . . . .150
SYSCFG_EXTICR1 . . . . . . . . . . . . . . . . . . . .147
SYSCFG_EXTICR2 . . . . . . . . . . . . . . . . . . . .147
SYSCFG_EXTICR3 . . . . . . . . . . . . . . . . . . . .148
SYSCFG_EXTICR4 . . . . . . . . . . . . . . . . . . . .149

T
TIM15_ARR . . . . . . . . . . . . . . . . . . . . . . . . . .443
TIM15_BDTR . . . . . . . . . . . . . . . . . . . . . . . . .445
TIM15_CCER . . . . . . . . . . . . . . . . . . . . . . . . .440
TIM15_CCMR1 . . . . . . . . . . . . . . . . . . . . . . .437
TIM15_CCR1 . . . . . . . . . . . . . . . . . . . . . . . . .444
TIM15_CCR2 . . . . . . . . . . . . . . . . . . . . . . . . .445
TIM15_CNT . . . . . . . . . . . . . . . . . . . . . . . . . .443
TIM15_CR1 . . . . . . . . . . . . . . . . . . . . . . . . . .429
TIM15_CR2 . . . . . . . . . . . . . . . . . . . . . . . . . .430
TIM15_DCR . . . . . . . . . . . . . . . . . . . . . . . . . .448
TIM15_DIER . . . . . . . . . . . . . . . . . . . . . . . . .433

TIM15_DMAR . . . . . . . . . . . . . . . . . . . . . . . . 448
TIM15_EGR . . . . . . . . . . . . . . . . . . . . . . . . . 436
TIM15_PSC . . . . . . . . . . . . . . . . . . . . . . . . . . 443
TIM15_RCR . . . . . . . . . . . . . . . . . . . . . . . . . 444
TIM15_SMCR . . . . . . . . . . . . . . . . . . . . . . . . 432
TIM15_SR . . . . . . . . . . . . . . . . . . . . . . . . . . . 433
TIM5_OR . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394
TIMx_ARR . . . . . . . . . . .288, 354, 372, 393, 462
TIMx_BDTR . . . . . . . . . . . . . . . . . . . . . . 290, 464
TIMx_CCER . . . . . . . . . . . . . 284, 352, 392, 460
TIMx_CCMR1 . . . . . . . . . . . . 279, 348, 389, 456
TIMx_CCMR2 . . . . . . . . . . . . . . . . . . . . 282, 351
TIMx_CCR1 . . . . . . . . . . . . . . 288, 354, 394, 463
TIMx_CCR2 . . . . . . . . . . . . . . . . . . . . . . 289, 355
TIMx_CCR3 . . . . . . . . . . . . . . . . . . . . . . 289, 355
TIMx_CCR4 . . . . . . . . . . . . . . . . . . . . . . 290, 356
TIMx_CNT . . . . . . . . . . .287, 354, 371, 393, 462
TIMx_CR1 . . . . . . . . . . .268, 338, 369, 386, 451
TIMx_CR2 . . . . . . . . . . . . . . . . . . . 269, 340, 452
TIMx_DCR . . . . . . . . . . . . . . . . . . . 292, 356, 466
TIMx_DIER . . . . . . . . . .274, 343, 370, 387, 453
TIMx_DMAR . . . . . . . . . . . . . . . . . 293, 357, 466
TIMx_EGR . . . . . . . . . . .277, 347, 371, 388, 455
TIMx_PSC . . . . . . . . . . .287, 354, 372, 393, 462
TIMx_RCR . . . . . . . . . . . . . . . . . . . . . . . 288, 463
TIMx_SMCR . . . . . . . . . . . . . . . . . . . . . 271, 341
TIMx_SR . . . . . . . . . . . .276, 344, 371, 387, 454

U
USART_BRR . . . . . . . . . . . . . . . . . . . . . . . . . 633
USART_CR1 . . . . . . . . . . . . . . . . . . . . . . . . . 625
USART_CR2 . . . . . . . . . . . . . . . . . . . . . . . . . 628
USART_CR3 . . . . . . . . . . . . . . . . . . . . . . . . . 630
USART_ICR . . . . . . . . . . . . . . . . . . . . . . . . . 638
USART_ISR . . . . . . . . . . . . . . . . . . . . . . . . . 635
USART_RDR . . . . . . . . . . . . . . . . . . . . . . . . 639
USART_RQR . . . . . . . . . . . . . . . . . . . . . . . . 634
USART_RTOR . . . . . . . . . . . . . . . . . . . . . . . 633
USART_TDR . . . . . . . . . . . . . . . . . . . . . . . . . 640
USB_ADDRn_RX . . . . . . . . . . . . . . . . . . . . . 706
USB_ADDRn_TX . . . . . . . . . . . . . . . . . . . . . 705
USB_BCDR . . . . . . . . . . . . . . . . . . . . . . . . . . 699
USB_BTABLE . . . . . . . . . . . . . . . . . . . . . . . . 698
USB_CNTR . . . . . . . . . . . . . . . . . . . . . . . . . . 692
USB_COUNTn_RX . . . . . . . . . . . . . . . . . . . . 706
USB_COUNTn_TX . . . . . . . . . . . . . . . . . . . . 705
USB_DADDR . . . . . . . . . . . . . . . . . . . . . . . . 698
USB_EPnR . . . . . . . . . . . . . . . . . . . . . . . . . . 701
USB_FNR . . . . . . . . . . . . . . . . . . . . . . . . . . . 697
USB_ISTR . . . . . . . . . . . . . . . . . . . . . . . . . . . 694
USB_LPMCSR . . . . . . . . . . . . . . . . . . . . . . . 699

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RM0360

W
WWDG_CFR . . . . . . . . . . . . . . . . . . . . . . . . .484
WWDG_CR . . . . . . . . . . . . . . . . . . . . . . . . . .483
WWDG_SR . . . . . . . . . . . . . . . . . . . . . . . . . .484

778/779

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RM0360

IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and
improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on
ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order
acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or
the design of Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2017 STMicroelectronics – All rights reserved

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Keywords                        : Technical Literature, 025023, Product Development, Specification, Reference manual, STM32F030F4, STM32F030C6, STM32F030K6, STM32F030C8, STM32F030R8, STM32F030CC, STM32F030RC, STM32F070C6, STM32F070CB, STM32F070F6, STM32F070RB
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Revision                        : 4
Title                           : STM32F030x4/x6/x8/xC and STM32F070x6/xB advanced ARM®-based 32-bit MCUs
Alternate ID                    : 025023
Alternate Name                  : RM0360
Classification                  : Unclassified
Document Type                   : Reference manual
Author                          : STMICROELECTRONICS
Create Date                     : 2017:04:24 10:52:48Z

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