6430F SAM3U User Guide

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Features
1. ATSAM3U4/2/1 Description
- 1.1 Configuration Summary
2. ATSAM3U4/2/1 Block Diagram
3. Signal Description
- 3.1 Design Considerations
4. Package and Pinout
- 4.1 SAM3U4/2/1E Package and Pinout
- 4.2 SAM3U4/2/1C Package and Pinout
5. Power Considerations
- 5.1 Power Supplies
- 5.2 Voltage Regulator
- 5.3 Typical Powering Schematics
- 5.4 Active Mode
- 5.5 Low Power Modes
- 5.6 Wake-up Sources
- 5.7 Fast Start-Up
6. Input/Output Lines
- 6.1 General Purpose I/O Lines (GPIO)
- 6.2 System I/O Lines
- 6.3 Serial Wire JTAG Debug Port (SWJ-DP)
- 6.4 Test Pin
- 6.5 NRST Pin
- 6.6 NRSTB Pin
- 6.7 ERASE Pin
7. Processor and Architecture
- 7.1 ARM Cortex-M3 Processor
- 7.2 APB/AHB Bridges
- 7.3 Matrix Masters
- 7.4 Matrix Slaves
- 7.5 Master to Slave Access
- 7.6 DMA Controller
- 7.7 Peripheral DMA Controller
- 7.8 Debug and Test Features
8. Product Mapping
9. Memories
- 9.1 Embedded Memories
- 9.2 External Memories
10. System Controller
- 10.1 System Controller and Peripheral Mapping
- 10.2 Power-on-Reset, Brownout and Supply Monitor
- 10.3 Reset Controller
- 10.4 Supply Controller
- 10.5 Clock Generator
- 10.6 Power Management Controller
- 10.7 Watchdog Timer
- 10.8 SysTick Timer
- 10.9 Real-time Timer
- 10.10 Real-time Clock
- 10.11 General-Purpose Back-up Registers
- 10.12 Nested Vectored Interrupt Controller
- 10.13 Chip Identification
- 10.14 PIO Controllers
11. Peripherals
- 11.1 Peripheral Identifiers
- 11.2 Peripheral Signal Multiplexing on I/O Lines
12. Embedded Peripherals Overview
- 12.1 Serial Peripheral Interface (SPI)
- 12.2 Two Wire Interface (TWI)
- 12.3 Universal Asynchronous Receiver Transceiver (UART)
- 12.4 Universal Synchronous Asynchronous Receiver Transmitter (USART)
- 12.5 Serial Synchronous Controller (SSC)
- 12.6 Timer Counter (TC)
- 12.7 Pulse Width Modulation Controller (PWM)
- 12.8 High Speed Multimedia Card Interface (HSMCI)
- 12.9 USB High Speed Device Port (UDPHS)
- 12.10 Analog-to-Digital Converter (ADC)
  - 12.10.1 12-bit High Speed ADC
  - 12.10.2 10-bit Low Power ADC
13. ARM Cortex® M3 Processor
- 13.1 About this section
- 13.2 About the Cortex-M3 processor and core peripherals
  - 13.2.1 System level interface
  - 13.2.2 Integrated configurable debug
  - 13.2.3 Cortex-M3 processor features and benefits summary
  - 13.2.4 Cortex-M3 core peripherals
- 13.3 Programmers model
  - 13.3.1 Processor mode and privilege levels for software execution
  - 13.3.2 Stacks
  - 13.3.3 Core registers
  - 13.3.4 Exceptions and interrupts
  - 13.3.5 Data types
  - 13.3.6 The Cortex Microcontroller Software Interface Standard
- 13.4 Memory model
  - 13.4.1 Memory regions, types and attributes
  - 13.4.2 Memory system ordering of memory accesses
  - 13.4.3 Behavior of memory accesses
    - 13.4.3.1 Additional memory access constraints for shared memory
  - 13.4.4 Software ordering of memory accesses
  - 13.4.5 Bit-banding
    - 13.4.5.1 Directly accessing an alias region
    - 13.4.5.2 Directly accessing a bit-band region
  - 13.4.6 Memory endianness
    - 13.4.6.1 Little-endian format
  - 13.4.7 Synchronization primitives
    - 13.4.7.1 A Load-Exclusive instruction
    - 13.4.7.2 A Store-Exclusive instruction
  - 13.4.8 Programming hints for the synchronization primitives
- 13.5 Exception model
  - 13.5.1 Exception states
  - 13.5.2 Exception types
  - 13.5.3 Exception handlers
  - 13.5.4 Vector table
  - 13.5.5 Exception priorities
  - 13.5.6 Interrupt priority grouping
  - 13.5.7 Exception entry and return
- 13.6 Fault handling
  - 13.6.1 Fault types
  - 13.6.2 Fault escalation and hard faults
  - 13.6.3 Fault status registers and fault address registers
  - 13.6.4 Lockup
- 13.7 Power management
  - 13.7.1 Entering sleep mode
  - 13.7.2 Wakeup from sleep mode
    - 13.7.2.1 Wakeup from WFI or sleep-on-exit
    - 13.7.2.2 Wakeup from WFE
  - 13.7.3 Power management programming hints
- 13.8 Instruction set summary
- 13.9 Intrinsic functions
- 13.10 About the instruction descriptions
  - 13.10.1 Operands
  - 13.10.2 Restrictions when using PC or SP
  - 13.10.3 Flexible second operand
  - 13.10.4 Shift Operations
  - 13.10.5 Address alignment
  - 13.10.6 PC-relative expressions
  - 13.10.7 Conditional execution
  - 13.10.8 Instruction width selection
    - 13.10.8.1 Instruction width selection
- 13.11 Memory access instructions
  - 13.11.1 ADR
  - 13.11.2 LDR and STR, immediate offset
  - 13.11.3 LDR and STR, register offset
  - 13.11.4 LDR and STR, unprivileged
  - 13.11.5 LDR, PC-relative
  - 13.11.6 LDM and STM
  - 13.11.7 PUSH and POP
  - 13.11.8 LDREX and STREX
  - 13.11.9 CLREX
- 13.12 General data processing instructions
  - 13.12.1 ADD, ADC, SUB, SBC, and RSB
  - 13.12.2 AND, ORR, EOR, BIC, and ORN
  - 13.12.3 ASR, LSL, LSR, ROR, and RRX
  - 13.12.4 CLZ
  - 13.12.5 CMP and CMN
  - 13.12.6 MOV and MVN
  - 13.12.7 MOVT
  - 13.12.8 REV, REV16, REVSH, and RBIT
  - 13.12.9 TST and TEQ
- 13.13 Multiply and divide instructions
  - 13.13.1 MUL, MLA, and MLS
  - 13.13.2 UMULL, UMLAL, SMULL, and SMLAL
  - 13.13.3 SDIV and UDIV
- 13.14 Saturating instructions
  - 13.14.1 SSAT and USAT
- 13.15 Bitfield instructions
  - 13.15.1 BFC and BFI
  - 13.15.2 SBFX and UBFX
  - 13.15.3 SXT and UXT
- 13.16 Branch and control instructions
  - 13.16.1 B, BL, BX, and BLX
  - 13.16.2 CBZ and CBNZ
  - 13.16.3 IT
  - 13.16.4 TBB and TBH
- 13.17 Miscellaneous instructions
  - 13.17.1 BKPT
  - 13.17.2 CPS
  - 13.17.3 DMB
  - 13.17.4 DSB
  - 13.17.5 ISB
  - 13.17.6 MRS
  - 13.17.7 MSR
  - 13.17.8 NOP
  - 13.17.9 SEV
  - 13.17.10 SVC
  - 13.17.11 WFE
  - 13.17.12 WFI
- 13.18 About the Cortex-M3 peripherals
- 13.19 Nested Vectored Interrupt Controller
  - 13.19.1 The CMSIS mapping of the Cortex-M3 NVIC registers
  - 13.19.2 Interrupt Set-enable Registers
  - 13.19.3 Interrupt Clear-enable Registers
  - 13.19.4 Interrupt Set-pending Registers
  - 13.19.5 Interrupt Clear-pending Registers
  - 13.19.6 Interrupt Active Bit Registers
  - 13.19.7 Interrupt Priority Registers
  - 13.19.8 Software Trigger Interrupt Register
  - 13.19.9 Level-sensitive interrupts
    - 13.19.9.1 Hardware and software control of interrupts
  - 13.19.10 NVIC design hints and tips
    - 13.19.10.1 NVIC programming hints
- 13.20 System control block
  - 13.20.1 The CMSIS mapping of the Cortex-M3 SCB registers
  - 13.20.2 Auxiliary Control Register
    - 13.20.2.1 About IT folding
  - 13.20.3 CPUID Base Register
  - 13.20.4 Interrupt Control and State Register
  - 13.20.5 Vector Table Offset Register
  - 13.20.6 Application Interrupt and Reset Control Register
    - 13.20.6.1 Binary point
  - 13.20.7 System Control Register
  - 13.20.8 Configuration and Control Register
  - 13.20.9 System Handler Priority Registers
  - 13.20.10 System Handler Control and State Register
  - 13.20.11 Configurable Fault Status Register
  - 13.20.12 Hard Fault Status Register
  - 13.20.13 Memory Management Fault Address Register
  - 13.20.14 Bus Fault Address Register
  - 13.20.15 Auxiliary Fault Status Register
  - 13.20.16 System control block design hints and tips
- 13.21 System timer, SysTick
  - 13.21.1 SysTick Control and Status Register
  - 13.21.2 SysTick Reload Value Register
    - 13.21.2.1 Calculating the RELOAD value
  - 13.21.3 SysTick Current Value Register
  - 13.21.4 SysTick Calibration Value Register
  - 13.21.5 SysTick design hints and tips
- 13.22 Memory protection unit
  - 13.22.1 MPU Type Register
  - 13.22.2 MPU Control Register
  - 13.22.3 MPU Region Number Register
  - 13.22.4 MPU Region Base Address Register
    - 13.22.4.1 The ADDR field
  - 13.22.5 MPU Region Attribute and Size Register
    - 13.22.5.1 SIZE field values
  - 13.22.6 MPU access permission attributes
  - 13.22.7 MPU mismatch
  - 13.22.8 Updating an MPU region
  - 13.22.9 MPU design hints and tips
    - 13.22.9.1 MPU configuration for a microcontroller
- 13.23 Glossary
14. Debug and Test Features
- 14.1 Overview
- 14.2 Application Examples
  - 14.2.1 Debug Environment
  - 14.2.2 Test Environment
- 14.3 Debug and Test Pin Description
- 14.4 Functional Description
15. Watchdog Timer (WDT)
- 15.1 Description
- 15.2 Block Diagram
- 15.3 Functional Description
- 15.4 Watchdog Timer (WDT) User Interface
16. Reset Controller (RSTC)
- 16.1 Overview
- 16.2 Block Diagram
- 16.3 Functional Description
- 16.4 Reset Controller (RSTC) User Interface
17. Real-time Timer (RTT)
- 17.1 Description
- 17.2 Embedded Characteristics
- 17.3 Block Diagram
- 17.4 Functional Description
- 17.5 Real-time Timer (RTT) User Interface
18. Real Time Clock (RTC)
- 18.1 Description
- 18.2 Block Diagram
- 18.3 Product Dependencies
  - 18.3.1 Power Management
  - 18.3.2 Interrupt
- 18.4 Functional Description
- 18.5 Real Time Clock (RTC) User Interface
19. Supply Controller (SUPC)
- 19.1 Description
- 19.2 Embedded Characteristics
- 19.3 Block Diagram
- 19.4 Supply Controller Functional Description
- 19.5 Supply Controller (SUPC) User Interface
20. General Purpose Backup Registers (GPBR)
- 20.1 Embedded Characteristics
- 20.2 Description
  - 20.2.1 Power Management Controller (PMC) User Interface
    - 20.2.1.1 General Purpose Backup Register x
21. Enhanced Embedded Flash Controller (EEFC)
- 21.1 Description
- 21.2 Embedded Characteristics
- 21.3 Product Dependencies
  - 21.3.1 Power Management
  - 21.3.2 Interrupt Sources
- 21.4 Functional Description
- 21.5 Enhanced Embedded Flash Controller (EEFC) User Interface
22. Fast Flash Programming Interface (FFPI)
- 22.1 Overview
- 22.2 Parallel Fast Flash Programming
23. SAM3U4/2/1 Boot Program
- 23.1 Description
- 23.2 Flow Diagram
- 23.3 Device Initialization
- 23.4 SAM-BA Monitor
- 23.5 Hardware and Software Constraints
24. Bus Matrix (MATRIX)
- 24.1 Description
- 24.2 Memory Mapping
- 24.3 Special Bus Granting Techniques
- 24.4 Arbitration
- 24.5 Write Protect Registers
- 24.6 Bus Matrix (MATRIX) User Interface
25. Static Memory Controller (SMC)
- 25.1 Description
- 25.2 Embedded Characteristics
- 25.3 Block Diagram
- 25.4 I/O Lines Description
- 25.5 Multiplexed Signals
- 25.6 Application Example
  - 25.6.1 Implementation Examples
  - 25.6.2 Hardware Interface
- 25.7 Product Dependencies
- 25.8 External Memory Mapping
- 25.9 Connection to External Devices
  - 25.9.1 Data Bus Width
  - 25.9.2 Byte Write or Byte Select Access
- 25.10 Standard Read and Write Protocols
- 25.11 Scrambling/Unscrambling Function
- 25.12 Automatic Wait States
- 25.13 Data Float Wait States
- 25.14 External Wait
- 25.15 Slow Clock Mode
  - 25.15.1 Slow Clock Mode Waveforms
  - 25.15.2 Switching from (to) Slow Clock Mode to (from) Normal Mode
- 25.16 NAND Flash Controller Operations
- 25.17 SMC Error Correcting Code Functional Description
  - 25.17.1 Write Access
  - 25.17.2 Read Access
- 25.18 Power Management Controller (PMC) User Interface
26. Peripheral DMA Controller (PDC)
- 26.1 Description
- 26.2 Embedded Characteristics
- 26.3 Block Diagram
- 26.4 Functional Description
- 26.5 Peripheral DMA Controller (PDC) User Interface
27. Clock Generator
- 27.1 Description
- 27.2 Block Diagram
- 27.3 Slow Clock
  - 27.3.1 Slow Clock RC Oscillator
  - 27.3.2 Slow Clock Crystal Oscillator
- 27.4 Main Clock
- 27.5 Divider and PLLA Block
  - 27.5.1 Divider and Phase Lock Loop Programming
- 27.6 UTMI Phase Lock Loop Programming
28. Power Management Controller (PMC)
- 28.1 Description
- 28.2 Block Diagram
- 28.3 Master Clock Controller
- 28.4 Processor Clock Controller
- 28.5 SysTick Clock
- 28.6 Peripheral Clock Controller
- 28.7 Free Running Processor Clock
- 28.8 Programmable Clock Output Controller
- 28.9 Fast Startup
- 28.10 Clock Failure Detector
- 28.11 Programming Sequence
- 28.12 Clock Switching Details
  - 28.12.1 Master Clock Switching Timings
  - 28.12.2 Clock Switching Waveforms
- 28.13 Write Protection Registers
- 28.14 Power Management Controller (PMC) User Interface
29. Chip Identifier (CHIPID)
- 29.1 Description
- 29.2 Embedded Characteristics
- 29.3 Chip Identifier (CHIPID) User Interface
  - 29.3.1 Chip ID Register
  - 29.3.2 Chip ID Extension Register
30. Parallel Input/Output Controller (PIO)
- 30.1 Description
- 30.2 Embedded Characteristics
- 30.3 Block Diagram
- 30.4 Product Dependencies
- 30.5 Functional Description
- 30.6 I/O Lines Programming Example
  - 30.6.1 Write Protection Registers
- 30.7 Parallel Input/Output Controller (PIO) User Interface
31. Synchronous Serial Controller (SSC)
- 31.1 Description
- 31.2 Embedded Characteristics
- 31.3 Block Diagram
- 31.4 Application Block Diagram
- 31.5 Pin Name List
- 31.6 Product Dependencies
- 31.7 Functional Description
- 31.8 SSC Application Examples
  - 31.8.1 Write Protection Registers
- 31.9 Synchronous Serial Controller (SSC) User Interface
32. Serial Peripheral Interface (SPI) Programmer Datasheet
- 32.1 Description
- 32.2 Embedded Characteristics
- 32.3 Block Diagram
- 32.4 Application Block Diagram
- 32.5 Signal Description
- 32.6 Product Dependencies
- 32.7 Functional Description
- 32.8 Serial Peripheral Interface (SPI) User Interface
33. Two-wire Interface (TWI)
- 33.1 Description
- 33.2 Embedded Characteristics
- 33.3 List of Abbreviations
- 33.4 Block Diagram
- 33.5 Application Block Diagram
  - 33.5.1 I/O Lines Description
- 33.6 Product Dependencies
- 33.7 Functional Description
  - 33.7.1 Transfer Format
  - 33.7.2 Modes of Operation
- 33.8 Master Mode
- 33.9 Multi-master Mode
  - 33.9.1 Definition
  - 33.9.2 Different Multi-master Modes
    - 33.9.2.1 TWI as Master Only
    - 33.9.2.2 TWI as Master or Slave
- 33.10 Slave Mode
- 33.11 Two-wire Interface (TWI) User Interface
34. Universal Asynchronous Receiver Transceiver (UART)
- 34.1 Description
- 34.2 Embedded Characteristics
- 34.3 Block Diagram
- 34.4 Product Dependencies
- 34.5 UART Operations
- 34.6 Universal Asynchronous Receiver Transceiver (UART) User Interface
35. Universal Synchronous Asynchronous Receiver Transmitter (USART)
- 35.1 Description
- 35.2 Embedded Characteristics
- 35.3 Block Diagram
- 35.4 Application Block Diagram
- 35.5 I/O Lines Description
- 35.6 Product Dependencies
- 35.7 Functional Description
- 35.8 Universal Synchronous Asynchronous Receiver Transmitter (USART) User Interface
36. Timer Counter (TC)
- 36.1 Description
- 36.2 Embedded Characteristics
- 36.3 Block Diagram
- 36.4 Pin Name List
- 36.5 Product Dependencies
- 36.6 Functional Description
- 36.7 Timer Counter (TC) User Interface
37. High Speed Multimedia Card Interface (HSMCI)
- 37.1 Description
- 37.2 Embedded Characteristics
- 37.3 Block Diagram
- 37.4 Application Block Diagram
- 37.5 Pin Name List
- 37.6 Product Dependencies
- 37.7 Bus Topology
- 37.8 High Speed MultiMediaCard Operations
- 37.9 SD/SDIO Card Operation
  - 37.9.1 SDIO Data Transfer Type
  - 37.9.2 SDIO Interrupts
- 37.10 CE-ATA Operation
- 37.11 HSMCI Boot Operation Mode
  - 37.11.1 Boot Procedure, Processor Mode
  - 37.11.2 Boot Procedure DMA Mode
- 37.12 HSMCI Transfer Done Timings
- 37.13 Write Protection Registers
- 37.14 High Speed Multimedia Card Interface (HSMCI) User Interface
38. Pulse Width Modulation (PWM)
- 38.1 Description
- 38.2 Embedded Characteristics
- 38.3 Block Diagram
- 38.4 I/O Lines Description
- 38.5 Product Dependencies
- 38.6 Functional Description
- 38.7 Pulse Width Modulation (PWM) User Interface
39. USB High Speed Device Port (UDPHS)
- 39.1 Description
- 39.2 Embedded Characteristics
- 39.3 Block Diagram
- 39.4 Typical Connection
- 39.5 Product Dependencies
  - 39.5.1 Power Management
  - 39.5.2 Interrupt
- 39.6 Functional Description
- 39.7 USB High Speed Device Port (UDPHS) User Interface
40. DMA Controller (DMAC)
- 40.1 Description
- 40.2 Block Diagram
- 40.3 Functional Description
- 40.4 DMAC Software Requirements
- 40.5 DMA Controller (DMAC) User Interface
41. 12-bit Analog-to-Digital Converter (ADC12B)
- 41.1 Description
- 41.2 Block Diagram
- 41.3 Signal Description
- 41.4 Product Dependencies
- 41.5 Functional Description
- 41.6 12-bit Analog-to-Digital Converter (ADC12B) User Interface
42. Analog-to-Digital Converter (ADC)
- 42.1 Description
- 42.2 Block Diagram
- 42.3 Signal Description
- 42.4 Product Dependencies
- 42.5 Functional Description
- 42.6 Analog-to-Digital Converter (ADC) User Interface
43. SAM3U4/2/1 Electrical Characteristics
- 43.1 Absolute Maximum Ratings
- 43.2 DC Characteristics
- 43.3 Power Consumption
- 43.4 Crystal Oscillators Characteristics
- 43.5 UPLL, PLLA Characteristics
- 43.6 USB High Speed Port
- 43.7 12-Bit ADC Characteristics
  - 43.7.0.1 Static performance characteristics
- 43.8 AC Characteristics
44. SAM3U4/2/1 Mechanical Characteristics
- 44.1 100-lead LQFP Package
- 44.2 100-ball TFBGA Package
- 44.3 144-lead LQFP Package
- 44.4 144-ball LFBGA Package
- 44.5 Soldering Profile
- 44.6 Packaging Resources
45. Ordering Information
46. SAM3U Series Errata
- 46.1 Marking
- 46.2 SAM3U Errata - Rev. A Parts
- 46.3 SAM3U Errata - Rev. B Parts
47. Revision History

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