Sol PC Ation_Rev_D Ation Rev D

User Manual: Pdf Sol-PC-ation_Rev_D

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Dear Sol-PCB Customer:
The enclosed documentation on the Sol-PCB and PM-5204 printed circuit
boards includes the following information:
1)
2)
3)
4)
5)

five Sol schematic diagrams
complete revised parts list
assembly drawings for Sol & PM
S-IOO Bus specification
memory allocation table

6)
7)
8)

I/O port allocation
control and status bit
definition
user switch option
selection table

Many of the mechanical parts for the Sol Terminal Computer are
hard to obtain, so we have made available the following items:
Item No.
Sol-CONKIT

Price
$59.00

Sol-PRELIM

14.00

Sol-SS

40.00

Includes
Jl through Jll connectors, personality
module card guides, card guide brackets
and handle bracket.
Preliminary Sol manual describing
assembly and checkout procedures,
plus much additional information.
Very helpful when bringing up Sol.
IC socket kit

We have sent the source listing for the CONSOL tm Personality module
software to INTERFACE AGE magazine. This article is currently
expected to be published in the December 1976 issue but publication
schedules can vary. The CONSOL software allows the Sol to be used
as a stand-alone computer system or as a terminal. The following
commands are implemented:
BASIC (executes at zero)
ENTER (in hexidecimal)
EXEC (at hex address)

DUMP (in hexidecimal)
TERM (terminal mode)
TLOAD (load memory from cassette)

The Sol-PCB boards sold for $40 each are warranteed for thirty days
against defects in materials and workmanship. The warranty is void
if, in the opinion of PTC, the printed circuit board has been abused
during assembly. Warranty is limited in any case to replacement of
defective printed circuit boards.
Processor Technology can not provide direct support via telephone or
letter to Sol-PCB purchasers. The documentation provided should be
sufficient to easily build and debug a Sol unit. NOTE: please do
not make parts substitutions!
If you are in any way dissatisfied with your unassembled Sol-PCB
please feel free to return it to us postpaid for a full refund.
Have fun!

PROCESSOR TECHNOLOGY CORPORATION 6200 HOLLIS STREET EMERYVILLE CA 94608
CABLE ADDRESS "PROCTEC"
"Copyright

© by

Processor Technology Corporation 1976"

(415) 652-8080

PROCESSOR TECHNOLOGY CORPORATION
Sol-PC SINGLE BOARD TERMINAL COMPUTER™
Table

J

v

1

AM0026 or DM0026 (UI04)
1)'S cc) :U..
4N26 (U39) -- /

5

8T97 (U67,68,77,~ ,81)

/ 2/
1

Sol-PC Parts List.

~

INTEGRATED CIRCUITS

/1"

1.

v'

i/..r

-v

~y'" 74S04 (U92)
/>

.1/

..-Y
/.

2/

.... y

1489A (U38)

7 ".. --- 74LS86

(U~)

~~
(

4019 (Ulll)

/ 3

74LS138 (U34,35 .-36)J
v ./
74LS15? (U12, 30,3 2 ')

/

74L~}-63V'0r/ -GBLS163

(U~)
/

c;I ':

.

(U28, 3I, 3 3-,40)

oJ.

~2/

/'

~

4520 (Ul12)

W(

2-

/ a!
/

/.'1

74HOO (U91)

/.,/

,/

rrP
/7

~/

74LSOO (U4r<,48,55)

7
.

~./'

74LS02 or 9LS02 (U5 ~60)
74LS04 (U2~45, 4~54)

~

~~

~~

./

TRANSISTORS

/ /'

.,. . r.
/

1""9

2'" 2N2907 (Ql & 2)

Y

2N4360 (Q3)

CRYSTAL
. HC- 18/U Case
1 1' 14.318 MHz l.n
(XTAL)

t/'

74166 (U~) ./
74173 (U95, 96)

J

74LSa. 75 or/ 2 5LSl...7 5/ /
y
v
v
~ rr
(U 2,13,/ 26,27,42,76,90,93,
977,106~)
~
yo

74LS253

v"'"

(U6 3t,66,78,79)~/

f1'
v.( /
V.
74LS367 ( g.29 ~v~7 ,50,71,89,
94,107)
8080, 8080A or 9080A (UI05)

8836 or 8T380 (U46)
91L02APC or 2102LIPC
(U3 - 10, U14 - 21)
93L16 (U62) 11/0 g

?

DIODES

2N2222 (Q4 & 5)

1

(U~) V,/ _

~3

4029 (Ul,11,84)
v'".
9)
4030 ( U9
/
v
4046 (U85, 110) ,
4049 (U~ 1(59")

~3

y ,/./ ",.,G0

74LS136

v"

/

~~

(U74

4013 (UI0 0',113)

4027 (U; Ol ~

~
/"
r

74LS20 (U2~ 59, 83) ~

74LSI09 (Ufo 3 t,-52 ty 63, 64, 70,
72,73,75)

/

~t'
2

~8

MCM6574 or MCM6575 (U25)
4001

1/

¥.,.-/

;/3/

4023
/1'" 4024 (U86,') //l,tclL

1

/

7406 (U57, 58,87)

1458CP or ) -558CP (U ~6, 1~8)

/ 1"
/

3/

:I"/ ~5'/V 2/1 74LSI0 (U4~6 ~ v-

~2/ TMS6011NC (U51, 69)
1

SECTION I

/

lN4148 or IN914 (01,03 - 10)
lN5231B Zener Diode (011)

4 . . . IN4001 (02,12,13,14)
RELAYS
2

DIP Reed,

(Kl & 2)

Sigma 191-TEIA15S

PROCESSOR TECHNOLOGY CORPORATION
SECTION I

Sol-PC SINGLE BOARD TERMINAL COMPUTER™
Table
RESISTORS
47
. /2

/

75
100
/ Y "'/IOO
./

~r 200

A~30
~

-"",Y

330

~~ 470
2~

1.

Sol-PC Parts List (Continued).
CAPACITORS

ohm, ~ watt, 5%
ohm, ~ watt, 5%
ohm, ~ watt, 5%
ohm, ~ watt, 5%
ohm, ~ watt, 5%

,)~

ohm, ~ watt, 5%
ohm, ~ watt, 5%
ohm, ~ watt, 5%

/'/

\,/

y

15
39

' /2/
//
47
, /2
50
3
/ 3/ 100
/ 2 150
2/
1
/'
.....y....:

K ohm, ~
K ohm, ~
M ohm, ~
2.2M ohm, ~

.001 ufd, disc
.001 ufd, Mylar tubular
.01 ufd~ Mylar tubular

,./6

2/'"

~.

.047 ufd, disc
ufd, disc
.1

;37

M

ohm, ~ watt, 5%
ohm, ~ watt, 5%
f'cf 680
~ 1.5K ohm, ~ watt, 5%
3.3K ohm, ~ watt, 5%
/ y
~6~
5.6K ohm, ~ watt, 5%
K ohm, ~ watt, 5%
K ohm, ~ watt, 5%
K ohm, ~ watt, 5%
K ohm, ~ watt, 5%
K ohm, Potentiometer

pfd, disc
pfd, monolythic or
disc ceramic

1"'''

470

10

pfd, disc

10
Y"- 330
'3/ 680

~

.1
.68

\

/'

\

1

5/

15

/ l( 100

ufd, Mylar tubular
ufd, monolythic
ceramic
ufd, tantalum,
dipped
ufd, tantalum,
dipped
ufd, aluminum
electrolytic

watt, 5%
watt, 5%
watt, 5%
watt, 5%

3.3M ohm, ~ watt, 5%

CONNECTORS
1 25-pin Female, AMP206584-1 (Jl)
I
25-pin Male, AMP206604-1 (J2 )
1
2

20-pin Header, 3M3492-2002 (J3 & 4)
30-pin Right Angle Edge Connector, VIKING 3KH15/75KC15 (J5)
Miniature Phone Jack (J6 & 7)

2
1

Subminiature Phone Jack (J8 & 9)
7-pin Right Angle Molex (JIO)

1
1

100-pin Edge Connector, TI H322150-02-6A (Jll)
Molex-type DC Power Cable, Jll mating (prefabricated)

2

PROCESSOR TECHNOLOGY CORPORATION
Sol-PC SINGLE BOARD TERMINAL COMPUTER™
Table

1.

SECTION I

Sol-PC Parts List (Continued).

MISCELLANEOUS
1 Sol-PCB Circuit Board
2 8-pin DIP Socket
29 14-pin DIP Socket
74 16-pin DIP Socket
1 24-pin DIP Socket
3 40-pin DIP Socket
2 DIP Switch, 6 position (Sl&4)
2 DIP Switch, 8 position (S2&3)
1 Length 72-ohm Coaxial Cable
1 Tie Wrap
2 Mounting Bracket, Sol-1040

2
10
2
4
6
2
10
1
1
1

Card Guide, SAE1250F
#4 Lockwasher, internal tooth
#4 Insulating Washer, 0.05
4-40 x 1/4 Binder Head Screw
4-40 x 7/16 Binder Head Screw
4-40 x 5/8 Binder Head Screw
4-40 Hex Nut
Length Solder
Manual
Personality Module Kit
(contents listed below)

PERSONALITY MODULE KIT, PM5204
1 PM5204 PC Board
2/ 5204 EPROM (U1,U2)
/ 1 74LS155 (U5)
~~ 10K ohm, 1/4 watt, 5% Film Resistor
J~ .047 ufd Capacitor, Disc Ceramic
~2, 1 ufd Capacitor, Tantalum Dipped

1
1
1
2

16-pin DIP Socket
24-pin DIP Socket
Bracket, Sol-1045
2-56 Binder ~ead Screw

U2

U3

o

o

o
-I-o~o

!:01:10

I

oc

C

I"'"

0 ---+-0"'

ALL R'S VALUE

COMP

SIDE

C3 : 0.047

=10K

J3 Keyboard Connector (between U64 and U65)
pin no.
1
2

3
4
5
6

7
8
9

10

Signal name
ground
+5v
Kbd Data Ready
Break
Kbd Data 0 A
Kbd Data 1 E
Kbd Data 2 C
Kbd Data 3 1)
+5v
ground

I
12
13
14
15
16
17
18
19
20

no.

Sol-PC, Rev. 2,E
10/18/76
Signal name
ground
+5v
Restart
Local
KBd Data 4 r:
KBd Data 5
KBD Data 6
KBD Data 7
+5v
ground

J4 Display Expansion Connector (between U28, 29)
no.
2

3
4
5
6

7
8
9

10

Signal name
ground
N.C.
Char. addr. 4
Character clock
Char. addr. 0 IChar. addr. 1
Char. addr. 2
Char. addr. 3
N.C.
ground

1
12
13
14
15
16
17
18
19
20

no.

Signal name
ground
N.C.
Dot Clock, 14.318MHz
Composite sync. out
TTL Serial Data Out
Composite blanking out
Scan advance out
Char. addr. 5
N.C.
ground

J5 Personality Module Edge Connector
pin no.

Al

A2
A3
A4
AS
A6
A7
A8
A9
A10
All
A12
A13
A14
A15

Signal name
Ground
+5VDC
Addr. 9
Addr. 8
Addr. 7
INT Bus 0
INT Bus 1
INT Bus 2
INT Bus 3
INT Bus 4
INT Bus 5
Program 0
Program 1
Program 2
Program 3

pin no.

BI

B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15

Signal name
Ground
+5VDC
Addr. 0
Addr. 4
Addr. 3
Addr. 2
Addr. 1
Addr. 5
Addr. 6
C4

C0

INT Bus 6
INT Bus 7
-12VDC
+12VDC

J6

Audio Out forCUTS Cassette Interface:

J7

Ap~io

J8

Tape Motor Control 1:
panel

(See output port FA, bit 7) Sub-mini jack at rear

J9

Tape Motor Control 2:
panel

(See output port FA, bit 6) Sub-mini jack at rear

In forCUTS Cassette Interface:

Mini-phone jack at rear panel
Mini-phone jack at rear panel

J10

DC Power Connector, Sol-PC
0
0

Ground
+5VDC
-12 VDC
+12 VDC
-12 VDC
+5 VDC
Ground

0

0
0
0
0

S-100 Bus Definitions
PIN
NUMBER

NAME

FUNCTION
Unregulated voltage on bus, supplied
to PC boards and regulated to 5V
supplied by Sol-20 supply
-16 Volts
Positive unregulated voltage supplied by
Sol-20 power supply
EXTE~~AL READY External ready input to CPU ready
circuitry
Vectored Interrupt
Line 4f0
Vectored Interrupt
Line 4f1
Vectored Interrupt
Line 4f2
Vectored Interrupt
Line 4f3
Vectored Interrupt
Line #4
Vectored Interrupt
Line 4f5
Vectored Interrupt
Line 4f6
Vectored Interrupt
Line 4n
EXTERNAL READY 4f2
not used by Sol-PC

1

SYMBOL
+8V

2

-16V

3

X;RDY

4

VIO

5

VI1

6

VI2

7

VI3

8

VI4

9

VIS

10

VI6

11

VI7

12
13
to
17

XRDY2

TO BE DEFINED

18

STAT DSB

STATUS DISABLE

19

C/C DSB

COMMAND/CONTROL
DISABLE

20
21
22

UNPROT
SS
ADD DSB

UNPROTECT
SINGLE STEP
ADDRESS DISABLE

23

DO DSB

DATA OUT DISABLE

24
25
26

02
01

PHASE 2 CLOCK
PHASE 1 CLOCK
HOLD ACKNOWLEDGE

PHLDA

~olts

-Allows the buffers for the 8
status lines to be tri-stated
-Allows the buffers for the 6
output command/control lines
to be tri-stated
- not used by Sol-PC electronics
- not used by Sol-PC
- Allows the buffers for the 16
address lines to be tri-stated
-Allows the buffers for the 8
data output lines to be tri-stated
Processor command/control output
signal that appears in response to
the HOLD signal; indicates that the
data and address bus will go to the
high impedance state and processor
will enter HOLD state after
completion of the current machine
cycle.

S-IOO Bus Definitions-continued
PIN
NUMBER

27

SYMBOL
PWAIT

28

PINTE

29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44

AS
A4
A3
A15
A12
A9
DIOI
DI00
AlO
DI04
DI05
DI06
DI02
DI03
DI07
SMI

45

SOUT

..
46

SINP

47

SMEMR

48

SHLTA

49
50
51

CLOCK
GND
+8V

52

-16V

FUNCTION
-Processor command/control signal that
appears in response to the HOLD signal;
indicates that the data and address bus
will go to the high impedance state and
processor will enter HOLD state after
completion of the current machine cycle
INTERRUPT
-Processor command/control output signal;
ENABLE
indicates interrupts are enabled, as
determined by the contents of the CPU
internal interrupt flip-flop. When the
flip-flop is set (Enable Interrupt
instruction), interrupts are accepted by
the CPU; when it is reset (Disable
Interrupt instruction), interrupts are
inhibited.
Address Line If5
Address Line If4
Addre s s Line If3
Address Line #15 (MSB)
Address Line #12
Address Line If9
Data In/Out line #1
same as pin 94
Data In/Out line #0
same as pin 95
Address Line #10
Data In/Out Line #4
same as pin 91
Data In/Out Line #5
same as pin 92
same as pin 93
Data In/Out Line #6
Data In/Out Line #2
same as pin 88
Data In/Out Line #3
same as p~n 89
same as p1n 90
Data In/Out Line #7
MACHINE CYCLE 1
-Status output signal that indicates
that the processor is in the fetch
cycle for the first byte of an
instruction
-Status output signal that indicates
OUTPUT
the address bus contains the address
of an output device and t'he data bus
will cohtain the ouput data when PWR
is active
INPUT
-Status output signal that indicates
the address bus cont-ains the address
of an input device and the input data
should be placed on the data bus when
PDBIN is active
-Status output signal that indicates
MEMORY READ
the data bus will be used to read
memory data
HALT ACKNOlvLEDGE - Status output signal that acknowledges
a HALT instruction
Inverted output of the 02 CLOCK
CLOCK
GROUND
Unregulated input to 5 volt
+8 Volts
regulators supplied by Sol-20
power supply
Negative unregulated voltage s.upplied
-16 Volts
by Sol-20 power supply
NAME

WAIT

Pinouts: Parallel Data Interface (PDI) as
Sept. 30, 1976
used on Processor Tech. Sol System
MASTER UNIT-Male connector
J2 Pin 11 Signal
Signal
J2 pinll Signal
Signal name
nmemonic
name
nmemonic
1
CG
Chassis Ground
US
Unit Select
14
2

SG

Signal Ground

15

OE

Output Enable

3

IE

Input Enable

16

xrm:

eXternal I>evice Ready

4

rm:

Data Reaoy

17

nL

Output Loao

5

!AI{

18

OD7

Output Data,bit 7

6

ID7

Input Data, bit 7 19

OD6

Output Data, bit 6

7

ID6

Input Data, bit 6 20

ODS

Output Data, bit 5

8

IDS

Input Data, bit 5 21

OD4

Output Data, bit 4

9

ID4

Input Data, bit 4 22

OD3

Output Data. bit 3

10

ID3

Input Data, bit 3 23

OD2

Output Data, bit 2

11

ID2

Input Data, bit 2 24

ODI

Output Data, bit 1

12

IDI

Input Data. bit 1 25

ODO

Output Data, bit a

13

IDa

Input Data, bit a

Pinouts: Serial Data Interface (SCI) as
used on Processor Tech. Sol System
Female connector-DB25S
Signal name
Jl pin41 Signal
J1 pin41 Signal
Signal
nmemonic
nmemonic
name
1
CG
Chassis Grotmd
Carrier Detect
8
CD
2

TD

Transmit Data

11

CLO

Current Loop Output

3

RD

Receive Data

12

LR1

Loop Receiver 1

4

RTS

Request To Send

13

LR2

Loop Receiver 2

5

CTS

Clear To Send

20

DTR

Data Terminal Ready

6

DSR

Data Set Ready

23

LCS

Loop Current Source

7

SG

Signal Ground

Note 1:
Note 2:
Note 3:

I

Many pins not specified here are used in EIA RS-232C specification.
USE THEM WITH CAUTION.
Terminals output on pins 2,4 & 20 and input on pins 3,5 & 6 for EIA
type hookups. Modems and computer mainframes output on pins ~5 & 6
and input on pinsl'2,4 & 20.
Current loop hookups are the same for terminals, modems,mainframes.

STATUS PORT INPUT BIT ASSIGNMENTS
PORT F8 (STATUS, SERIAL COMM. CHANNEL)
FUNCTION
SIGNAL NAME

¢

SCD
SDSR
SPE
SFE
SOE
SCTS
SDR
STBE

1
2
3
4
5
6
7

Serial Carrier Detect (EIA)
Serial Data Set Ready (EIA)
Serial Parity Error
Serial Framing Error
Serial Overrun Error
Serial Clear to Send (EIA)
UART Serial Data Ready
UART Serial Transmit Buffer Empty

ACTIVE DIRECTION
1 carrier
¢ link ok
1 error
1 error
1 error
¢ clear
1 ready
1 empty

PORT FA (AUX. STATUS, CASSETTE TAPE INTERFACE, PARALLEL I/O, KEYBOARD INPUT)
ACTIVE DIRECTION
BIT
SIGNAL NAME
FUNCTION

¢

KDR
PDR
PXDR
TFE
TOE
not used
TDR
TTBE

1
2
3
4
5
6
7

Keyboard Data Ready
Parallel Data Ready
Parallel eXternal Device Ready
Tape Framing Error
Tape Overrun Error

¢

Tape Data Ready
Tape Transmitter Buffer Empty

1 ready
1 empty

PORT FE (DISPLAY STATUS)
BIT
SIGNAL NAME
¢
SOK
Scroll OK~
scroll

FUNCTION
~

sec timeout after

CONTROL PORT OUTPUT BIT ASSIGNMENTS
PORT F8 (CONTROL, SERIAL COMM. CHANNEL)
SIGNAL NAME
BIT
FUNCTION
4
SRTS
Serial Request to Send
PORT FA (CONTROL, PARALLEL I/O, CUTS CASSETTE I/O)
BIT
SIGNAL NAME
FUNCTION
PIE
3
Parallel Input Enable
4
PUS
Parallel Unit Select
TBR
5
Tape Baud Rate (300/1200)
6
TT2
Tape Transport 2
TTl
7
Tape Transport 1
PORT FE (SCROLL CONTROL, DISPLAY SECTION)
BIT
SIGNAL NAME
FUNCTION
¢ - 3
BDLA
Beginning Display Line Absolute
address
4 - 7
FDSP
First Displayed Line Screen
Position

Jl
J2
J3
J4
J5

CONNECTOR DESIGNATION
Serial data
J6
Parallel Data
J7
Keyboard
J8
J9
Display Expansion
JIO
ROM Personality Module
Jll

ready
¢ ready
¢ ready
1 error
1 error

ACTIVE DIRECTION
¢ time complete

ACTIVE DIRECTION
1 request
ACTIVE DIRECTION
1 pin 3 J2 low
o pin 14 J2 low
o 1200 Baud
o run tape
o run tape
ACTIVE DIRECTION
4-bit data nybble
4-bit data nybble

Cassette Tape Audio Out
Cassette Tape Audio In
Tape Motor 1
Tape Motor 2
PC Power
S-lOO Bus Expansion

S-100 Bus Definitions-continued
PIN
NUMBER
53
54
55
56
57

SYMBOL
SSWI
EXT CLR
RTC
STSTB

NAME

DiGf

SENSE SWITCH INPUT
EXTERNAL CLEAR
REAL TIME CLOCK
STATUS STROBE
DATA INPUT GATE #1

FRDY

FRONT PANEL READY

58
59
to
64
65

MREQ

MEMORY REQUEST

66

REF

REFRESH

67

PHANTOM

PHANTOM DISABLE

68

MWRITE

MEMORY WRITE

69
70
71
72

PS
PROT
RUN
PRDY

PROJECT STATUS
PROTECT
RUN
PROCESSOR READY

73

PINT

-

INTERRUPT REQUEST

74

PHOLD

75

PRESET

RESET

76

PSYNC

SYNC

77

PWR

WRITE

78

PDBIN

DATA BUS IN

FUNCTION
not used by Sol
not used by Sol-PC electronics
not used by Sol-PC electronics
not used by Sol
When low forces PDBINS low and
forces CPU input multiplexers to
the DIO bus. During CPU DBIN cycle,
disables CPU DIO bus drivers
-When low disables MWRITE driver

TO BE DEFINED
- Z 80 signal not used by Sol-PC
electronics
- Z 80 signal not used by Sol-PC
electronics
-Output from CPU section used to
disable RAM or ROM during power on
initialization program execution
-Indicates that the data present on
the Data Out Bus is to be written
into the memory location currently
on the address bus
-not used by Sol-PC electronics
-not used by Sol-PC electronics
- not used by Sol-PC electronics
- Memory and I/O input to the CPU
Board wait circuitry
- The processor recognizes an
interrupt request on this line at
the end of the current instruction
or while halted. If the processor
is in the HOLD state or the
Interrupt Enable flip-flop is reset,
it will not honor the request.
-Processor command/control input
signal that requests the processor
enter the HOLD state; allows an
external device to gain control of
address and data buses as soon as
the processor has completed its
use of these buses for the current
machine cycle
-Processor command/control input;
while activated, the content of the
program counter is cleared and the
instruction register is set to 0
-Processor command/control output;
provides a signal to indicate the
beginning of each machine cycle
-Processor command/control output;
used for memory write or I/O output control. Data on the data bus
is stable while the PWR is active
-Processor command/control output;
indicates to external circuits that
the data bus is in the input mode

S-IOO Bus Definitions-continued
PIN
NUMBER
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96

SYMBOL
AO
Al
A2
A6
A7
A8
A13
A14
All
DI02
DI03
DI07
DI04
DI05
DI06
DIOI
DI00
SINTA

97

SWO

98

SSTACK

99
100

POC
GND

NAME
FUNCTION
Address Line iFO
(LSB)
Address Line ill
Address Line 1,1:2
Addres s Line iF6
Address Line 417
Address Line iF8
Addres s Line ill3
Address Line 4114
Address Line 4111
Data In/Out Line 412
same as pin 41
Data In/Out Line 413
same as pin 42
Data In/Out Line 417
same as pin 43
Data In/Out Line 414
same as pin 38
Data In/Out Line 415
same as pin 39
Data In/Out Line 416
same as pin 40
Data In/Out Line 411
same as pin 35
Data In/Out Line 410
same as p~n 36
INTERRUPT ACKNOWLEDGE -Status output signal; acknowledges
signal for INTERRUPT request
WRITE OUT
-Status output signal; indicates
that the operation in the current
machine cycle will be a WRITE
memory or output function
STACK
-Status output signal indicates
that the address bus holds the
pushdown stack address from the
Stack Pointer
POWER-ON CLEAR
GROUND

SWITCH FUNCTION DEFINITION
Switch No.
Sl-l
Sl-2
Sl-3
Sl-4
Sl-5
Sl-6

Mnemonic
RST
not used
BLANK
Polarity
BLINK
SOLID

Display Ctrl---Schematic Drawing 414
Function
ON
OFF
Restart to Zero
RUN ( Dwg. 1Fl)
Blank Ctrl Characters Display Ctrl Char.
Blinking cursor
Solid cursor

*Solid or NO cursor
*Blinking or NO cursor

*NO cursor if Sl-5 and Sl-6 are off at same time.
Both switches should not be on at the same time.
Drawing 413 -- Sense Switch
Switch No.
Mnemonic
S2-1
ssw0
S2-2thruS2-7
S2-8
SSW7

Function
ON
LSB, data bit
etc.
MSB data bit 7

OFF
0-LO
LO
LO

HI
HI
HI

SERIAL I/O BAUD RATE SWITCH -- Schematic Drawing #3
Function
Mnemonic
ON
OFF
Switch No.
75
S3-1
75 BAUD
* Do not turn more than
110 BAUD
one switch on at a time
11
S3-2
150 BAUD
15
S3-3
300 BAUD
30
S3-4
600 BAUD
60
S3-s
12
1200 BAUD
S3-6
2400 or 4800(norma11y 2400 if not jumpered K to M)
24/48
S3-7
9600 BAUD
96
S3-8
Schematic Drawing #3
SERIAL I/O CONTROL
OFF
Mnemonic
ON
Switch No.
Parity odd (if s4-s on)
Parity even
PS
S4-l
Data word length 8bits 7bits 6bits sbitSJ
WLS 1
S4-2
ON
ON
OFF
OFF
WLS
2
S4-3
ON
OFF
ON
OFF
2 ston bits (1.5 if sbits/word)
1 stop bit
SBS
S4-4
No
parity
PI
Partty
S4-s
Full
duplex
Half duplex
F/R
S4-6

t

MEMORY ALLOCATION:
Hexidecima1
C000 C800 CC00 -

Address
C7FF
CBFF
CFFF

ON CARD
Function
Personality Module ROM or PROM (2048 words)
System RAM (1024 words)
Display RAM Memory (1024 characters)

ON CARD INPUT PORT ALLOCATION
Hexidecima1 Port
Address
F8
F9
FA
FB
FC
FD
FE
FF
OUTPUT PORTS
Hex Port Address
F8
F9
FA
FB
FC
FD
FE
FF

Function
Status, Serial Comm. channel
Serial Communication Channel Data
Aux. Status, Cassette tape interface, parallel
I/O, keyboard input
Audio Cassette (CUTS) Data
Keyboard Data (from J3)
Parallel Port Data (from J2)
Display Status
Sense Switch (S2-1 thru S2-8)
Function
Control, Serial Comm. Channel
Data, Serial Comm. Channel
Control, Parallel I/O, CUTS Cassette I/O
Data, CUTS audio cassette Interface
Alarm (optional)
Data, Parallel output Data channel
Scroll control,
Display Section
not usedin Sol-PC

PC

MUDIFICATION

REViSION

LI-~VEL

D

Due to layout errors connections to pins 28, 73 and 74 have been"
interchanged. These signals are used by DMA and interrupt devices.
Correction requires three cuts and installation of three jumpers.
Use 24 gauge wire supplied with the kit for these changes.
1. Cut trace on rear side of board connecting pin 1 of U45 with
feedthrough directly below. Install jumper wire on rear side of
board connecting pin 1 of U45 with pin 73 of Jll.

2. Cut trace connecting the feedthTough adjacent to pins 13 and 14
of U64 with the feedthrough directly above (on rear side of board).
Install jumper wire as shown on the rear side of the board.
3. Cut trace on front side of the board connecting the feedthrough
innnediately below and to the left of the "Jll" designation with
pin 73 of Jll. Install a jumper wire from this feedthrough to
pin 28 of Jll on the rear side of the board.

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