AMD64 Architecture Programmer’s Manual, Volume 3: General Purpose And System Instructions 3 &
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- AMD64 Architecture Programmer’s Manual Volume 3: General-Purpose and System Instructions
- Contents
- Figures
- Tables
- Revision History
- Preface
- 1 Instruction Encoding
- 2 Instruction Overview
- 3 General-Purpose Instruction Reference
- AAA
- AAD
- AAM
- AAS
- ADC
- ADCX
- ADD
- ADOX
- AND
- ANDN
- BEXTR (register form)
- BEXTR (immediate form)
- BLCFILL
- BLCI
- BLCIC
- BLCMSK
- BLCS
- BLSFILL
- BLSI
- BLSIC
- BLSMSK
- BLSR
- BOUND
- BSF
- BSR
- BSWAP
- BT
- BTC
- BTR
- BTS
- BZHI
- CALL (Near)
- CALL (Far)
- CBW CWDE CDQE
- CWD CDQ CQO
- CLC
- CLD
- CLFLUSH
- CLFLUSHOPT
- CLZERO
- CMC
- CMOVcc
- CMP
- CMPS CMPSB CMPSW CMPSD CMPSQ
- CMPXCHG
- CMPXCHG8B CMPXCHG16B
- CPUID
- CRC32
- DAA
- DAS
- DEC
- DIV
- ENTER
- IDIV
- IMUL
- IN
- INC
- INS INSB INSW INSD
- INT
- INTO
- Jcc
- JCXZ JECXZ JRCXZ
- JMP (Near)
- JMP (Far)
- LAHF
- LDS LES LFS LGS LSS
- LEA
- LEAVE
- LFENCE
- LLWPCB
- LODS LODSB LODSW LODSD LODSQ
- LOOP LOOPE LOOPNE LOOPNZ LOOPZ
- LWPINS
- LWPVAL
- LZCNT
- MFENCE
- MONITORX
- MOV
- MOVBE
- MOVD
- MOVMSKPD
- MOVMSKPS
- MOVNTI
- MOVS MOVSB MOVSW MOVSD MOVSQ
- MOVSX
- MOVSXD
- MOVZX
- MUL
- MULX
- MWAITX
- NEG
- NOP
- NOT
- OR
- OUT
- OUTS OUTSB OUTSW OUTSD
- PAUSE
- PDEP
- PEXT
- POP
- POPA POPAD
- POPCNT
- POPF POPFD POPFQ
- PREFETCH PREFETCHW
- PREFETCHlevel
- PUSH
- PUSHA PUSHAD
- PUSHF PUSHFD PUSHFQ
- RCL
- RCR
- RDFSBASE RDGSBASE
- RDRAND
- RDSEED
- RET (Near)
- RET (Far)
- ROL
- ROR
- RORX
- SAHF
- SAL SHL
- SAR
- SARX
- SBB
- SCAS SCASB SCASW SCASD SCASQ
- SETcc
- SFENCE
- SHL
- SHLD
- SHLX
- SHR
- SHRD
- SHRX
- SLWPCB
- STC
- STD
- STOS STOSB STOSW STOSD STOSQ
- SUB
- T1MSKC
- TEST
- TZCNT
- TZMSK
- UD0, UD1, UD2
- WRFSBASE WRGSBASE
- XADD
- XCHG
- XLAT
- XLATB
- XOR
- 4 System Instruction Reference
- Appendix A Opcode and Operand Encodings
- Appendix B General-Purpose Instructions in 64-Bit Mode
- B.1 General Rules for 64-Bit Mode
- B.2 Operation and Operand Size in 64-Bit Mode
- B.3 Invalid and Reassigned Instructions in 64-Bit Mode
- B.4 Instructions with 64-Bit Default Operand Size
- B.5 Single-Byte INC and DEC Instructions in 64-Bit Mode
- B.6 NOP in 64-Bit Mode
- B.7 Segment Override Prefixes in 64-Bit Mode
- Appendix C Differences Between Long Mode and Legacy Mode
- Appendix D Instruction Subsets and CPUID Feature Flags
- Appendix E Obtaining Processor Information Via the CPUID Instruction
- E.1 Special Notational Conventions
- E.2 Standard and Extended Function Numbers
- E.3 Standard Feature Function Numbers
- E.3.1 Function 0h—Maximum Standard Function Number and Vendor String
- E.3.2 Function 1h—Processor and Processor Feature Identifiers
- E.3.3 Functions 2h–4h—Reserved
- E.3.4 Function 5h—Monitor and MWait Features
- E.3.5 Function 6h—Power Management Related Features
- E.3.6 Function 7h—Structured Extended Feature Identifiers
- E.3.7 Functions 8h–Ch—Reserved
- E.3.8 Function Dh—Processor Extended State Enumeration
- E.3.9 Functions 4000_0000h–4000_FFh—Reserved for Hypervisor Use
- E.4 Extended Feature Function Numbers
- E.4.1 Function 8000_0000h—Maximum Extended Function Number and Vendor String
- E.4.2 Function 8000_0001h—Extended Processor and Processor Feature Identifiers
- E.4.3 Functions 8000_0002h–8000_0004h—Extended Processor Name String
- E.4.4 Function 8000_0005h—L1 Cache and TLB Information
- E.4.5 Function 8000_0006h—L2 Cache and TLB and L3 Cache Information
- E.4.6 Function 8000_0007h—Processor Power Management and RAS Capabilities
- E.4.7 Function 8000_0008h—Processor Capacity Parameters and Extended Feature Identification
- E.4.8 Function 8000_0009h—Reserved
- E.4.9 Function 8000_000Ah—SVM Features
- E.4.10 Functions 8000_000Bh–8000_0018h—Reserved
- E.4.11 Function 8000_0019h—TLB Characteristics for 1GB pages
- E.4.12 Function 8000_001Ah—Instruction Optimizations
- E.4.13 Function 8000_001Bh—Instruction-Based Sampling Capabilities
- E.4.14 Function 8000_001Ch—Lightweight Profiling Capabilities
- E.4.15 Function 8000_001Dh—Cache Topology Information
- E.4.16 Function 8000_001Eh—Processor Topology Information
- E.4.17 CPUID Fn8000_001f—Encrypted Memory Capabilities
- E.5 Multiple Core Calculation
- Appendix F Instruction Effects on RFLAGS
- Index