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Programming Environments Manual PowerPC RISC Microprocessor Family addx addx Add (x’7C00 0214’) add add. addo addo. rD,rA,rB rD,rA,rB rD,rA,rB rD,rA,rB (OE = 0 Rc = 0) (OE = 0 Rc = 1) (OE = 1 Rc = 0) (OE = 1 Rc = 1) [POWER mnemonics: cax, cax., caxo, caxo.] rD ← (rA) + (rB) The sum (rA) + (rB) is placed into rD. The add instruction is preferred for addition because it sets few status bits. Other registers altered: • Condition Register (CR0 field): Affected: LT, GT, EQ, SO (if Rc = 1) Note: CR0 field may not reflect the infinitely precise result if overflow occurs (see XER below). • XER: Affected: SO, OV (if OE = 1) Note: The setting of the affected bits in the XER is mode-dependent, and reflects overflow of the 64-bit result in 64-bit mode and overflow of the low-order 32-bit result in 32-bit mode. For further information about 64-bit mode and 32-bit mode in 64-bit implementations, see 4.1.2 , “Computation Modes.” PowerPC Architecture Level UISA pem8.fm.2.0 June 10, 2003 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form XO Instruction Set Page 377 of 785 Programming Environments Manual PowerPC RISC Microprocessor Family addcx addcx Add Carrying (x’7C00 0014’) addc addc. addco addco. rD,rA,rB rD,rA,rB rD,rA,rB rD,rA,rB (OE = 0 Rc = 0) (OE = 0 Rc = 1) (OE = 1 Rc = 0) (OE = 1 Rc = 1) [POWER mnemonics: a, a., ao, ao.] rD ← (rA) + (rB) The sum (rA) + (rB) is placed into rD. Other registers altered: • Condition Register (CR0 field): Affected: LT, GT, EQ, SO(if Rc = 1) Note: CR0 field may not reflect the infinitely precise result if overflow occurs (see XER below). • XER: Affected: CA Affected: SO, OV(if OE = 1) Note: The setting of the affected bits in the XER is mode-dependent, and reflects overflow of the 64-bit result in 64-bit mode and overflow of the low-order 32-bit result in 32-bit mode. For further information about 64-bit mode and 32-bit mode in 64-bit implementations, see 4.1.2 , “Computation Modes.” PowerPC Architecture Level UISA Instruction Set Page 378 of 785 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form XO pem8.fm.2.0 June 10, 2003 Programming Environments Manual PowerPC RISC Microprocessor Family addex addex Add Extended (x’7C00 0114’) adde adde. addeo addeo. rD,rA,rB rD,rA,rB rD,rA,rB rD,rA,rB (OE = 0 Rc = 0) (OE = 0 Rc = 1) (OE = 1 Rc = 0) (OE = 1 Rc = 1) [POWER mnemonics: ae, ae., aeo, aeo.] rD ← (rA) + (rB) + XER[CA] The sum (rA) + (rB) + XER[CA] is placed into rD. Other registers altered: • Condition Register (CR0 field): Affected: LT, GT, EQ, SO (if Rc = 1) Note: CR0 field may not reflect the infinitely precise result if overflow occurs (see XER below). • XER: Affected: CA Affected: SO, OV (if OE = 1) Note: The setting of the affected bits in the XER is mode-dependent, and reflects overflow of the 64-bit result in 64-bit mode and overflow of the low-order 32-bit result in 32-bit mode. For further information about 64-bit mode and 32-bit mode in 64-bit implementations, see 4.1.2 , “Computation Modes.” PowerPC Architecture Level UISA pem8.fm.2.0 June 10, 2003 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form XO Instruction Set Page 379 of 785 Programming Environments Manual PowerPC RISC Microprocessor Family addi addi Add Immediate (x’3800 0000’) addi rD,rA,SIMM [POWER mnemonic: cal] if rA = 0 then rD ← EXTS(SIMM) else rD ← rA + EXTS(SIMM) The sum (rA|0) + SIMM is placed into rD. The addi instruction is preferred for addition because it sets few status bits. Note that addi uses the value 0, not the contents of GPR0, if rA = 0. Other registers altered: • None Simplified mnemonics: li la subi rD,value rD,disp(rA) rD,rA,value PowerPC Architecture Level UISA Instruction Set Page 380 of 785 equivalent to equivalent to equivalent to Supervisor Level addi addi addi 32-Bit rD,0,value rD,rA,disp rD,rA,–value 64-Bit 64-Bit Bridge Optional Form D pem8.fm.2.0 June 10, 2003 Programming Environments Manual PowerPC RISC Microprocessor Family addic addic Add Immediate Carrying (x’3000 0000’) addic rD,rA,SIMM [POWER mnemonic: ai] rD ← (rA) + EXTS(SIMM) The sum (rA) + SIMM is placed into rD. Other registers altered: • XER: Affected: CA Note: The setting of the affected bits in the XER is mode-dependent, and reflects overflow of the 64-bit result in 64-bit mode and overflow of the low-order 32-bit result in 32-bit mode. For further information about 64-bit mode and 32-bit mode in 64-bit implementations, see 4.1.2 , “Computation Modes.” Simplified mnemonics: subic rD,rA,valueequivalent toaddicrD,rA,–value PowerPC Architecture Level UISA pem8.fm.2.0 June 10, 2003 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form D Instruction Set Page 381 of 785 Programming Environments Manual PowerPC RISC Microprocessor Family addic. addic. Add Immediate Carrying and Record (x’3400 0000’) addic. rD,rA,SIMM [POWER mnemonic: ai.] rD ← (rA) + EXTS(SIMM) The sum (rA) + SIMM is placed into rD. Other registers altered: • Condition Register (CR0 field): Affected: LT, GT, EQ, SO Note: CR0 field may not reflect the infinitely precise result if overflow occurs (see XER below). • XER: Affected: CA Note: The setting of the affected bits in the XER is mode-dependent, and reflects overflow of the 64-bit result in 64-bit mode and overflow of the low-order 32-bit result in 32-bit mode. For further information about 64-bit mode and 32-bit mode in 64-bit implementations, see 4.1.2 , “Computation Modes.” Simplified mnemonics: subic.rD,rA,valueequivalent toaddic.rD,rA,–value PowerPC Architecture Level UISA Instruction Set Page 382 of 785 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form D pem8.fm.2.0 June 10, 2003 Programming Environments Manual PowerPC RISC Microprocessor Family addis addis Add Immediate Shifted (x’3C00 0000’) addis rD,rA,SIMM [POWER mnemonic: cau] if rA = 0 then rD ← EXTS(SIMM || (16)0) else rD ← (rA) + EXTS(SIMM || (16)0) The sum (rA|0) + (SIMM || 0x0000) is placed into rD. The addis instruction is preferred for addition because it sets few status bits. Note that addis uses the value 0, not the contents of GPR0, if rA = 0. Other registers altered: • None Simplified mnemonics: lisrD,valueequivalent toaddisrD,0,value subisrD,rA,valueequivalent toaddisrD,rA,–value PowerPC Architecture Level UISA pem8.fm.2.0 June 10, 2003 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form D Instruction Set Page 383 of 785 Programming Environments Manual PowerPC RISC Microprocessor Family addmex addmex Add to Minus One Extended (x’7C00 01D4’) addme addme. addmeo addmeo. rD,rA rD,rA rD,rA rD,rA (OE = 0 Rc = 0) (OE = 0 Rc = 1) (OE = 1 Rc = 0) (OE = 1 Rc = 1) [POWER mnemonics: ame, ame., ameo, ameo.] rD ← (rA) + XER[CA] – 1 The sum (rA) + XER[CA] + 0xFFFF_FFFF_FFFF_FFFF is placed into rD. Other registers altered: • Condition Register (CR0 field): Affected: LT, GT, EQ, SO(if Rc = 1) Note: CR0 field may not reflect the infinitely precise result if overflow occurs (see XER below). • XER: Affected: CA Affected: SO, OV(if OE = 1) Note: The setting of the affected bits in the XER is mode-dependent, and reflects overflow of the 64-bit result in 64-bit mode and overflow of the low-order 32-bit result in 32-bit mode. For further information about 64-bit mode and 32-bit mode in 64-bit implementations, see 4.1.2 , “Computation Modes.” PowerPC Architecture Level UISA Instruction Set Page 384 of 785 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form XO pem8.fm.2.0 June 10, 2003 Programming Environments Manual PowerPC RISC Microprocessor Family addzex addzex Add to Zero Extended (x’7C00 0194’) addze addze. addzeo addzeo. rD,rA rD,rA rD,rA rD,rA (OE = 0 Rc = 0) (OE = 0 Rc = 1) (OE = 1 Rc = 0) (OE = 1 Rc = 1) [POWER mnemonics: aze, aze., azeo, azeo.] rD ← (rA) + XER[CA] The sum (rA) + XER[CA] is placed into rD. Other registers altered: • Condition Register (CR0 field): Affected: LT, GT, EQ, SO(if Rc = 1) Note: CR0 field may not reflect the infinitely precise result if overflow occurs (see XER below). • XER: Affected: CA Affected: SO, OV(if OE = 1) Note: The setting of the affected bits in the XER is mode-dependent, and reflects overflow of the 64-bit result in 64-bit mode and overflow of the low-order 32-bit result in 32-bit mode. For further information about 64-bit mode and 32-bit mode in 64-bit implementations, see 4.1.2 , “Computation Modes.” PowerPC Architecture Level UISA pem8.fm.2.0 June 10, 2003 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form XO Instruction Set Page 385 of 785 Programming Environments Manual PowerPC RISC Microprocessor Family andx andx AND (x’7C00 0038’) and and. rA,rS,rB rA,rS,rB (Rc = 0) (Rc = 1) rA ← (rS) & (rB) The contents of rS are ANDed with the contents of rB and the result is placed into rA. Other registers altered: • Condition Register (CR0 field): Affected: LT, GT, EQ, SO(if Rc = 1) PowerPC Architecture Level UISA Instruction Set Page 386 of 785 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form X pem8.fm.2.0 June 10, 2003 Programming Environments Manual PowerPC RISC Microprocessor Family andcx andcx AND with Complement (x’7C00 0078’) andc andc. rA,rS,rB rA,rS,rB (Rc = 0) (Rc = 1) rA ← (rS) + ¬ (rB) The contents of rS are ANDed with the one’s complement of the contents of rB and the result is placed into rA. Other registers altered: • Condition Register (CR0 field): Affected: LT, GT, EQ, SO(if Rc = 1) PowerPC Architecture Level UISA pem8.fm.2.0 June 10, 2003 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form X Instruction Set Page 387 of 785 Programming Environments Manual PowerPC RISC Microprocessor Family andi. andi. AND Immediate (x’7000 0000’) andi. rA,rS,UIMM [POWER mnemonic: andil.] rA ← (rS) & ((4816)0 || UIMM) The contents of rS are ANDed with 0x0000_0000_0000 || UIMM and the result is placed into rA. Other registers altered: • Condition Register (CR0 field): Affected: LT, GT, EQ, SO PowerPC Architecture Level UISA Instruction Set Page 388 of 785 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form D pem8.fm.2.0 June 10, 2003 Programming Environments Manual PowerPC RISC Microprocessor Family andis. andis. AND Immediate Shifted (x’7400 0000’) andis. rA,rS,UIMM [POWER mnemonic: andiu.] rA ← (rS) + ((32)0 || UIMM || (16)0) The contents of rS are ANDed with 0x0000_0000 || UIMM || 0x0000 and the result is placed into rA. Other registers altered: • Condition Register (CR0 field): Affected: LT, GT, EQ, SO PowerPC Architecture Level UISA pem8.fm.2.0 June 10, 2003 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form D Instruction Set Page 389 of 785 Programming Environments Manual PowerPC RISC Microprocessor Family bx bx Branch (x’4800 0000’) b ba bl bla target_addr target_addr target_addr target_addr (AA = 0 LK = 0) (AA = 1 LK = 0) (AA = 0 LK = 1) (AA = 1 LK = 1) if AA then NIA ←iea EXTS(LI || 0b00) else NIA ←iea CIA + EXTS(LI || 0b00) if LK then LR ←iea CIA + 4 target_addr specifies the branch target address. If AA = 0, then the branch target address is the sum of LI || 0b00 sign-extended and the address of this instruction, with the high-order 32 bits of the branch target address cleared in 32-bit mode of 64-bit implementations. If AA = 1, then the branch target address is the value LI || 0b00 sign-extended, with the high-order 32 bits of the branch target address cleared in 32-bit mode of 64-bit implementations. If LK = 1, then the effective address of the instruction following the branch instruction is placed into the link register. Other registers altered: Affected: Link Register (LR)(if LK = 1) PowerPC Architecture Level UISA Instruction Set Page 390 of 785 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form I pem8.fm.2.0 June 10, 2003 Programming Environments Manual PowerPC RISC Microprocessor Family bcx bcx Branch Conditional (x’4000 0000’) bc bca bcl bcla BO,BI,target_addr BO,BI,target_addr BO,BI,target_addr BO,BI,target_addr 16 0 BO 5 6 (AA = 0 LK = 0) (AA = 1 LK = 0) (AA = 0 LK = 1) (AA = 1 LK = 1) BI 10 11 BD 15 16 AA LK 29 30 31 if (64-bit implementation) & (64-bit mode) then m ← 0 else m ← 32 if ¬ BO[2] then CTR ← CTR – 1 ctr_ok ← BO[2] | ((CTR[m–63] ¦ 0) ⊕ BO[3]) cond_ok ← BO[0] | (CR[BI] ≡ BO[1]) if ctr_ok & cond_ok then if AA then NIA ←iea EXTS(BD || 0b00) else NIA ←iea CIA + EXTS(BD || 0b00) if LK then LR ←iea CIA + 4 The BI field specifies the bit in the condition register (CR) to be used as the condition of the branch. The BO field is encoded as described in . Additional information about BO field encoding is provided in Section 4.2.4.2 Conditional Branch Control. Table 8-6. BO Operand Encodings BO Description 0000y Decrement the CTR, then branch if the decremented CTR[M–63] ¦ 0 and the condition is FALSE. 0001y Decrement the CTR, then branch if the decremented CTR[M–63] = 0 and the condition is FALSE. 001zy Branch if the condition is FALSE. 0100y Decrement the CTR, then branch if the decremented CTR[M–63] ¦ 0 and the condition is TRUE. 0101y Decrement the CTR, then branch if the decremented CTR[M–63] = 0 and the condition is TRUE. 011zy Branch if the condition is TRUE. 1z00y Decrement the CTR, then branch if the decremented CTR[M–63] ¦ 0. 1z01y Decrement the CTR, then branch if the decremented CTR[M–63] = 0. 1z1zz Branch always. M = 32 in 32-bit mode, and M = 0 in the default 64-bit mode. If the BO field specifies that the CTR is to be decremented, the entire 64bit CTR is decremented regardless of the 32-bit mode or the default 64-bit mode. In this table, z indicates a bit that is ignored. Note that the z bits should be cleared, as they may be assigned a meaning in some future version of the PowerPC architecture. The y bit provides a hint about whether a conditional branch is likely to be taken, and may be used by some PowerPC implementations to improve performance. pem8.fm.2.0 June 10, 2003 Instruction Set Page 391 of 785 Programming Environments Manual PowerPC RISC Microprocessor Family target_addr specifies the branch target address. If AA = 0, the branch target address is the sum of BD || 0b00 sign-extended and the address of this instruction, with the high-order 32 bits of the branch target address cleared in 32-bit mode of 64-bit implementations. If AA = 1, the branch target address is the value BD || 0b00 sign-extended, with the high-order 32 bits of the branch target address cleared in 32-bit mode of 64-bit implementations. If LK = 1, the effective address of the instruction following the branch instruction is placed into the link register. Other registers altered: Affected: Count Register (CTR)(if BO[2] = 0) Affected: Link Register (LR)(if LK = 1) Simplified mnemonics: blt bne bdnz target cr2,target target PowerPC Architecture Level UISA Instruction Set Page 392 of 785 equivalent to equivalent to equivalent to Supervisor Level bc bc bc 12,0,target 4,10,target 16,0,target 32-Bit 64-Bit 64-Bit Bridge Optional Form B pem8.fm.2.0 June 10, 2003 Programming Environments Manual PowerPC RISC Microprocessor Family bcctrx bcctrx Branch Conditional to Count Register (x’4C00 0420’) bcctr bcctrl BO,BI BO,BI (LK = 0) (LK = 1) [POWER mnemonics: bcc, bccl] cond_ok ← BO[0] | (CR[BI] ≡ BO[1]) if cond_ok then NIA ←iea CTR[0–61] || 0b00 if LK then LR ←iea CIA + 4 The BI field specifies the bit in the condition register to be used as the condition of the branch. The BO field is encoded as described in . Additional information about BO field encoding is provided in Section 4.2.4.2 , “Conditional Branch Control.” . Table 8-7. BO Operand Encodings BO Description 0000y Decrement the CTR, then branch if the decremented CTR[M–63] ¦ 0 and the condition is FALSE. 0001y Decrement the CTR, then branch if the decremented CTR[M–63] = 0 and the condition is FALSE. 001zy Branch if the condition is FALSE. 0100y Decrement the CTR, then branch if the decremented CTR[M–63] ¦ 0 and the condition is TRUE. 0101y Decrement the CTR, then branch if the decremented CTR[M–63] = 0 and the condition is TRUE. 011zy Branch if the condition is TRUE. 1z00y Decrement the CTR, then branch if the decremented CTR[M–63] ¦ 0. 1z01y Decrement the CTR, then branch if the decremented CTR[M–63] = 0. 1z1zz Branch always. M = 32 in 32-bit mode, and M = 0 in the default 64-bit mode. If the BO field specifies that the CTR is to be decremented, the entire 64bit CTR is decremented regardless of the 32-bit mode or the default 64-bit mode. In this table, z indicates a bit that is ignored. Note that the z bits should be cleared, as they may be assigned a meaning in some future version of the PowerPC architecture. The y bit provides a hint about whether a conditional branch is likely to be taken, and may be used by some PowerPC implementations to improve performance. The branch target address is CTR[0–61] || 0b00, with the high-order 32 bits of the branch target address cleared in 32-bit mode of 64-bit implementations. If LK = 1, the effective address of the instruction following the branch instruction is placed into the link register. If the “decrement and test CTR” option is specified (BO[2] = 0), the instruction form is invalid. pem8.fm.2.0 June 10, 2003 Instruction Set Page 393 of 785 Programming Environments Manual PowerPC RISC Microprocessor Family Other registers altered: Affected: Link Register (LR)(if LK = 1) Simplified mnemonics: bltctr bnectr cr2 PowerPC Architecture Level UISA Instruction Set Page 394 of 785 equivalent to equivalent to Supervisor Level bcctr bcctr 32-Bit 12,0 4,10 64-Bit 64-Bit Bridge Optional Form XL pem8.fm.2.0 June 10, 2003 Programming Environments Manual PowerPC RISC Microprocessor Family bclrx bclrx Branch Conditional to Link Register (x’4C00 0020’) bclr bclrl BO,BI BO,BI (LK = 0) (LK = 1) [POWER mnemonics: bcr, bcrl] if (64-bit implementation) & (64-bit mode) then m ← 0 else m ← 32 if ¬ BO[2] then CTR ← CTR – 1 ctr_ok ← BO[2] | ((CTR[m–63] ¦ 0) ⊕ BO[3]) cond_ok ← BO[0] | (CR[BI] ≡ BO[1]) if ctr_ok & cond_ok then NIA ←iea LR[0–61] || 0b00 if LK then LR ←iea CIA + 4 The BI field specifies the bit in the condition register to be used as the condition of the branch. The BO field is encoded as described in Table 8-8. Additional information about BO field encoding is provided in Section 4.2.4.2 Conditional Branch Control. Table 8-8. BO Operand Encodings BO Description 0000y Decrement the CTR, then branch if the decremented CTR[M–63] ¦ 0 and the condition is FALSE. 0001y Decrement the CTR, then branch if the decremented CTR[M–63] = 0 and the condition is FALSE. 001zy Branch if the condition is FALSE. 0100y Decrement the CTR, then branch if the decremented CTR[M–63] ¦ 0 and the condition is TRUE. 0101y Decrement the CTR, then branch if the decremented CTR[M–63] = 0 and the condition is TRUE. 011zy Branch if the condition is TRUE. 1z00y Decrement the CTR, then branch if the decremented CTR[M–63] ¦ 0. 1z01y Decrement the CTR, then branch if the decremented CTR[M–63] = 0. 1z1zz Branch always. M = 32 in 32-bit mode, and M = 0 in the default 64-bit mode. If the BO field specifies that the CTR is to be decremented, the entire 64bit CTR is decremented regardless of the 32-bit mode or the default 64-bit mode. In this table, z indicates a bit that is ignored. Note that the z bits should be cleared, as they may be assigned a meaning in some future version of the PowerPC architecture. The y bit provides a hint about whether a conditional branch is likely to be taken, and may be used by some PowerPC implementations to improve performance. The branch target address is LR[0–61] || 0b00, with the high-order 32 bits of the branch target address cleared in 32-bit mode of 64-bit implementations. pem8.fm.2.0 June 10, 2003 Instruction Set Page 395 of 785 Programming Environments Manual PowerPC RISC Microprocessor Family If LK = 1, then the effective address of the instruction following the branch instruction is placed into the link register. Other registers altered: Affected: Count Register (CTR) (if BO[2] = 0) Affected: Link Register (LR) (if LK = 1) Simplified mnemonics: bltlr bnelr bdnzlr cr2 PowerPC Architecture Level UISA Instruction Set Page 396 of 785 equivalent to equivalent to equivalent to Supervisor Level bclr bclr bclr 12,0 4,10 16,0 32-Bit 64-Bit 64-Bit Bridge Optional Form XL pem8.fm.2.0 June 10, 2003 Programming Environments Manual PowerPC RISC Microprocessor Family cmp cmp Compare (x’7C00 0000’) cmp crfD,L,rA,rB if L = 0 then a ← EXTS(rA[32–63]) b ← EXTS(rB[32–63]) else a ← (rA) b ← (rB) if a < b then c ← 0b100 else if a > b then c ← 0b010 else c ← 0b001 CR[4 ∗ crfD–4 ∗ crfD + 3] ← c || XER[SO] The contents of rA (or the low-order 32 bits of rA if L = 0) are compared with the contents of rB (or the loworder 32 bits of rB if L = 0), treating the operands as signed integers. The result of the comparison is placed into CR field crfD. In 32-bit implementations, if L = 1 the instruction form is invalid. Other registers altered: • Condition Register (CR field specified by operand crfD): Affected: LT, GT, EQ, SO Simplified mnemonics: cmpd cmpw rA,rB cr3,rA,rB PowerPC Architecture Level UISA pem8.fm.2.0 June 10, 2003 equivalent to equivalent to Supervisor Level cmp cmp 32-Bit 0,1,rA,rB 3,0,rA,rB 64-Bit 64-Bit Bridge Optional Form X Instruction Set Page 397 of 785 Programming Environments Manual PowerPC RISC Microprocessor Family cmpi cmpi Compare Immediate (x’2C00 0000’) cmpi crfD,L,rA,SIMM if L = 0 then a ← EXTS(rA[32–63]) elsea ← (rA) if a < EXTS(SIMM) then c ← 0b100 else if a > EXTS(SIMM) then c ← 0b010 else c ← 0b001 CR[4 ∗ crfD–4 ∗ crfD + 3] ← c || XER[SO] The contents of rA (or the low-order 32 bits of rA sign-extended to 64 bits if L = 0) are compared with the signextended value of the SIMM field, treating the operands as signed integers. The result of the comparison is placed into CR field crfD. In 32-bit implementations, if L = 1 the instruction form is invalid. Other registers altered: • Condition Register (CR field specified by operand crfD): Affected: LT, GT, EQ, SO Simplified mnemonics: cmpdi cmpwi rA,value cr3,rA,value PowerPC Architecture Level UISA Instruction Set Page 398 of 785 equivalent to equivalent to Supervisor Level cmpi cmpi 32-Bit 0,1,rA,value 3,0,rA,value 64-Bit 64-Bit Bridge Optional Form D pem8.fm.2.0 June 10, 2003 Programming Environments Manual PowerPC RISC Microprocessor Family cmpl cmpl Compare Logical (x’7C00 0040’) cmpl crfD,L,rA,rB if L = 0 then a ← (32)0 || rA[32–63] b ← (32)0 || rB[32–63] elsea ← (rA) b ← (rB) if a U b then c ← 0b010 else c ← 0b001 CR[4 ∗ crfD–4 ∗ crfD + 3] ← c || XER[SO] The contents of rA (or the low-order 32 bits of rA if L = 0) are compared with the contents of rB (or the loworder 32 bits of rB if L = 0), treating the operands as unsigned integers. The result of the comparison is placed into CR field crfD. In 32-bit implementations, if L = 1 the instruction form is invalid. Other registers altered: • Condition Register (CR field specified by operand crfD): Affected: LT, GT, EQ, SO Simplified mnemonics: cmpld cmplw rA,rB cr3,rA,rB PowerPC Architecture Level UISA pem8.fm.2.0 June 10, 2003 equivalent to equivalent to Supervisor Level cmpl cmpl 32-Bit 0,1,rA,rB 3,0,rA,rB 64-Bit 64-Bit Bridge Optional Form X Instruction Set Page 399 of 785 Programming Environments Manual PowerPC RISC Microprocessor Family cmpli cmpli Compare Logical Immediate (x’2800 0000’) cmpli crfD,L,rA,UIMM 10 crfD 0 L A if L = 0 then a ← (32)0 || rA[32–63] else a ← (rA) if a U ((4816)0 || UIMM) then c ← 0b010 else c ← 0b001 CR[4 ∗ crfD–4 ∗ crfD + 3] ← c || XER[SO] The contents of rA (or the low-order 32 bits of rA zero-extended to 64-bits if L = 0) are compared with 0x0000_0000_0000 || UIMM, treating the operands as unsigned integers. The result of the comparison is placed into CR field crfD. In 32-bit implementations, if L = 1 the instruction form is invalid. Other registers altered: • Condition Register (CR field specified by operand crfD): Affected: LT, GT, EQ, SO Simplified mnemonics: cmpldi cmplwi r A,value cr3,rA,value PowerPC Architecture Level UISA Instruction Set Page 400 of 785 equivalent to equivalent to Supervisor Level cmpli cmpli 32-Bit 0,1,rA,value 3,0,rA,value 64-Bit 64-Bit Bridge Optional Form D pem8.fm.2.0 June 10, 2003 Programming Environments Manual PowerPC RISC Microprocessor Family cntlzdx 64-Bit Implementations Only cntlzdx Count Leading Zeros Double Word (x’7C00 0074’) cntlzd cntlzd. rA,rS rA,rS (Rc = 0) (Rc = 1) Reserved 31 0 S 5 6 A 10 11 0000 0 58 15 16 20 21 Rc 30 31 n ←0 do while n < 64 if rS[n] = 1 then leave n← n + 1 rA ← n A count of the number of consecutive zero bits starting at bit 0 of register rS is placed into rA. This number ranges from 0 to 64, inclusive. This instruction is defined only for 64-bit implementations. Using it on a 32-bit implementation will cause the system illegal instruction error handler to be invoked. Other registers altered: • Condition Register (CR0 field): Affected: LT, GT, EQ, SO(Rc = 1) Note: If Rc = 1, then LT is cleared in the CR0 field. PowerPC Architecture Level UISA pem8.fm.2.0 June 10, 2003 Supervisor Level 32-Bit 64-Bit Ð 64-Bit Bridge Optional Form X Instruction Set Page 401 of 785 Programming Environments Manual PowerPC RISC Microprocessor Family cntlzwx cntlzwx Count Leading Zeros Word (x’7C00 0034’) cntlzw cntlzw. rA,rS rA,rS (Rc = 0) (Rc = 1) [POWER mnemonics: cntlz, cntlz.] Reserved 31 0 S 5 6 A 10 11 0000 0 15 16 26 20 21 Rc 30 31 n ← 320 do while n < 6432 if rS[n] = 1 then leave n ← n + 1 rA ← n – 32 A count of the number of consecutive zero bits starting at bit 320 of rS (bit 0 in 32-bit implementations) is placed into rA. This number ranges from 0 to 32, inclusive. Other registers altered: • Condition Register (CR0 field): Affected: LT, GT, EQ, SO(if Rc = 1) Note: If Rc = 1, then LT is cleared in the CR0 field. PowerPC Architecture Level UISA Instruction Set Page 402 of 785 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form X pem8.fm.2.0 June 10, 2003 Programming Environments Manual PowerPC RISC Microprocessor Family crand crand Condition Register AND (x’4C00 0202’) crand crbD,crbA,crbB CR[crbD] ← CR[crbA] & CR[crbB] The bit in the condition register specified by crbA is ANDed with the bit in the condition register specified by crbB. The result is placed into the condition register bit specified by crbD. Other registers altered: • Condition Register: Affected: Bit specified by operand crbD PowerPC Architecture Level UISA pem8.fm.2.0 June 10, 2003 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form XL Instruction Set Page 403 of 785 Programming Environments Manual PowerPC RISC Microprocessor Family crandc crandc Condition Register AND with Complement (x’4C00 0102’) crandc crbD,crbA,crbB Reserved 19 0 crbD 5 6 crbA 10 11 crbB 15 16 129 20 21 0 30 31 CR[crbD] ← CR[crbA] & ¬ CR[crbB] The bit in the condition register specified by crbA is ANDed with the complement of the bit in the condition register specified by crbB and the result is placed into the condition register bit specified by crbD. Other registers altered: • Condition Register: Affected: Bit specified by operand crbD PowerPC Architecture Level UISA Instruction Set Page 404 of 785 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form XL pem8.fm.2.0 June 10, 2003 Programming Environments Manual PowerPC RISC Microprocessor Family creqv creqv Condition Register Equivalent (x’4C00 0242’) creqv crbD,crbA,crbB Reserved 19 0 crbD 5 6 crbA 10 11 crbB 15 16 289 20 21 0 30 31 CR[crbD] ← CR[crbA] ≡ CR[crbB] The bit in the condition register specified by crbA is XORed with the bit in the condition register specified by crbB and the complemented result is placed into the condition register bit specified by crbD. Other registers altered: • Condition Register: Affected: Bit specified by operand crbD Simplified mnemonics: crset crbD PowerPC Architecture Level UISA pem8.fm.2.0 June 10, 2003 equivalent to Supervisor Level creqv 32-Bit crbD,crbD,crbD 64-Bit 64-Bit Bridge Optional Form XL Instruction Set Page 405 of 785 Programming Environments Manual PowerPC RISC Microprocessor Family crnand crnand Condition Register NAND (x’4C00 01C2’) crnand crbD,crbA,crbB Reserved 19 0 crbD 5 6 crbA 10 11 crbB 15 16 225 20 21 0 30 31 CR[crbD] ← ¬ (CR[crbA] & CR[crbB]) The bit in the condition register specified by crbA is ANDed with the bit in the condition register specified by crbB and the complemented result is placed into the condition register bit specified by crbD. Other registers altered: • Condition Register: Affected: Bit specified by operand crbD PowerPC Architecture Level UISA Instruction Set Page 406 of 785 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form XL pem8.fm.2.0 June 10, 2003 Programming Environments Manual PowerPC RISC Microprocessor Family crnor crnor Condition Register NOR (x’4C00 0042’) crnor crbD,crbA,crbB Reserved 19 0 crbD 5 6 crbA 10 11 crbB 15 16 33 20 21 0 30 31 CR[crbD] ← ¬ (CR[crbA] | CR[crbB]) The bit in the condition register specified by crbA is ORed with the bit in the condition register specified by crbB and the complemented result is placed into the condition register bit specified by crbD. Other registers altered: • Condition Register: Affected: Bit specified by operand crbD Simplified mnemonics: crnot crbD,crbA PowerPC Architecture Level UISA pem8.fm.2.0 June 10, 2003 equivalent to Supervisor Level crnor 32-Bit crbD,crbA,crbA 64-Bit 64-Bit Bridge Optional Form XL Instruction Set Page 407 of 785 Programming Environments Manual PowerPC RISC Microprocessor Family cror cror Condition Register OR (x’4C00 0382’) cror crbD,crbA,crbB Reserved 19 0 crbD 5 6 crbA 10 11 crbB 15 16 449 20 21 0 30 31 CR[crbD] ← CR[crbA] | CR[crbB] The bit in the condition register specified by crbA is ORed with the bit in the condition register specified by crbB. The result is placed into the condition register bit specified by crbD. Other registers altered: • Condition Register: Affected: Bit specified by operand crbD Simplified mnemonics: crmove crbD,crbA PowerPC Architecture Level UISA Instruction Set Page 408 of 785 equivalent to Supervisor Level cror 32-Bit crbD,crbA,crbA 64-Bit 64-Bit Bridge Optional Form XL pem8.fm.2.0 June 10, 2003 Programming Environments Manual PowerPC RISC Microprocessor Family crorc crorc Condition Register OR with Complement (x’4C00 0342’) crorc crbD,crbA,crbB Reserved 19 0 crbD 5 6 crbA 10 11 crbB 15 16 417 20 21 0 30 31 CR[crbD] ← CR[crbA] | ¬ CR[crbB] The bit in the condition register specified by crbA is ORed with the complement of the condition register bit specified by crbB and the result is placed into the condition register bit specified by crbD. Other registers altered: • Condition Register: Affected: Bit specified by operand crbD PowerPC Architecture Level UISA pem8.fm.2.0 June 10, 2003 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form XL Instruction Set Page 409 of 785 Programming Environments Manual PowerPC RISC Microprocessor Family crxor crxor Condition Register XOR (x’4C00 0182’) crxor crbD,crbA,crbB Reserved 19 0 crbD 5 6 crbA 10 11 crbB 15 16 193 20 21 0 30 31 CR[crbD] ← CR[crbA] ⊕ CR[crbB] The bit in the condition register specified by crbA is XORed with the bit in the condition register specified by crbB and the result is placed into the condition register specified by crbD. Other registers altered: • Condition Register: Affected: Bit specified by crbD Simplified mnemonics: crclr crbD PowerPC Architecture Level UISA Instruction Set Page 410 of 785 equivalent to Supervisor Level crxor 32-Bit crbD,crbD,crbD 64-Bit 64-Bit Bridge Optional Form XL pem8.fm.2.0 June 10, 2003 Programming Environments Manual PowerPC RISC Microprocessor Family dcba dcba Data Cache Block Allocate (x’7C00 05EC’) dcba rA,rB Reserved 31 0 00 000 5 6 A 10 11 B 15 16 758 20 21 0 30 31 EA is the sum (rA|0) + (rB). The dcba instruction allocates the block in the data cache addressed by EA, by marking it valid without reading the contents of the block from memory; the data in the cache block is considered to be undefined after this instruction completes. This instruction is a hint that the program will probably soon store into a portion of the block, but the contents of the rest of the block are not meaningful to the program (eliminating the need to read the entire block from main memory), and can provide for improved performance in these code sequences. The dcba instruction executes as follows: • If the cache block containing the byte addressed by EA is in the data cache, the contents of all bytes are made undefined but the cache block is still considered valid. Note that programming errors can occur if the data in this cache block is subsequently read or used inadvertently. • If the cache block containing the byte addressed by EA is not in the data cache and the corresponding memory page or block is caching-allowed, the cache block is allocated (and made valid) in the data cache without fetching the block from main memory, and the value of all bytes is undefined. • If the addressed byte corresponds to a caching-inhibited page or block (i.e. if the I bit is set), this instruction is treated as a no-op. • If the cache block containing the byte addressed by EA is in coherency-required mode, and the cache block exists in the data cache(s) of any other processor(s), it is kept coherent in those caches (i.e. the processor performs the appropriate bus transactions to enforce this). This instruction is treated as a store to the addressed byte with respect to address translation, memory protection, referenced and changed recording and the ordering enforced by eieio or by the combination of caching-inhibited and guarded attributes for a page (or block). However, the DSI exception is not invoked for a translation or protection violation, and the referenced and changed bits need not be updated when the page or block is cache-inhibited (causing the instruction to be treated as a no-op). This instruction is optional in the PowerPC architecture. Other registers altered: • None In the PowerPC OEA, the dcba instruction is additionally defined to clear all bytes of a newly established block to zero in the case that the block did not already exist in the cache. pem8.fm.2.0 June 10, 2003 Instruction Set Page 411 of 785 Programming Environments Manual PowerPC RISC Microprocessor Family Additionally, as the dcba instruction may establish a block in the data cache without verifying that the associated physical address is valid, a delayed machine check exception is possible. See 6. , “Exceptions,” for a discussion about this type of machine check exception. PowerPC Architecture Level VEA Instruction Set Page 412 of 785 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form Ð X pem8.fm.2.0 June 10, 2003 Programming Environments Manual PowerPC RISC Microprocessor Family dcbf dcbf Data Cache Block Flush (x’7C00 00AC’) dcbf rA,rB Reserved 31 0 00 000 5 6 A 10 11 B 15 16 86 0 20 21 30 31 EA is the sum (rA|0) + (rB). The dcbf instruction invalidates the block in the data cache addressed by EA, copying the block to memory first, if there is any dirty data in it. If the processor is a multiprocessor implementation (for example, the 601, 604,and 604e and 620) and the block is marked coherency-required, the processor will, if necessary, send an address-only broadcast to other processors. The broadcast of the dcbf instruction causes another processor to copy the block to memory, if it has dirty data, and then invalidate the block from the cache. The action taken depends on the memory mode associated with the block containing the byte addressed by EA and on the state of that block. The list below describes the action taken for the various states of the memory coherency attribute (M bit). • Coherency required – Unmodified block—Invalidates copies of the block in the data caches of all processors. – Modified block—Copies the block to memory. Invalidates copies of the block in the data caches of all processors. – Absent block—If modified copies of the block are in the data caches of other processors, causes them to be copied to memory and invalidated in those data caches. If unmodified copies are in the data caches of other processors, causes those copies to be invalidated in those data caches. • Coherency not required – Unmodified block—Invalidates the block in the processor’s data cache. – Modified block—Copies the block to memory. Invalidates the block in the processor’s data cache. – Absent block (target block not in cache)—No action is taken. The function of this instruction is independent of the write-through, write-back and caching-inhibited/allowed modes of the block containing the byte addressed by EA. This instruction is treated as a load from the addressed byte with respect to address translation and memory protection. It is also treated as a load for referenced and changed bit recording except that referenced and changed bit recording may not occur. Other registers altered: • None PowerPC Architecture Level VEA pem8.fm.2.0 June 10, 2003 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form X Instruction Set Page 413 of 785 Programming Environments Manual PowerPC RISC Microprocessor Family dcbi dcbi Data Cache Block Invalidate (x’7C00 03AC’) dcbi rA,rB Reserved 31 0 00 000 5 6 A 10 11 B 15 16 470 20 21 0 30 31 EA is the sum (rA|0) + (rB). The action taken is dependent on the memory mode associated with the block containing the byte addressed by EA and on the state of that block. The list below describes the action taken if the block containing the byte addressed by EA is or is not in the cache. • Coherency required – Unmodified block—Invalidates copies of the block in the data caches of all processors. – Modified block—Invalidates copies of the block in the data caches of all processors. (Discards the modified contents.) – Absent block—If copies of the block are in the data caches of any other processor, causes the copies to be invalidated in those data caches. (Discards any modified contents.) • Coherency not required – Unmodified block—Invalidates the block in the processor’s data cache. – Modified block—Invalidates the block in the processor’s data cache. (Discards the modified contents.) – Absent block (target block not in cache)—No action is taken. When data address translation is enabled, MSR[DR] = 1, and the virtual address has no translation, a DSI exception occurs. The function of this instruction is independent of the write-through and caching-inhibited/allowed modes of the block containing the byte addressed by EA. This instruction operates as a store to the addressed byte with respect to address translation and protection. The referenced and changed bits are modified appropriately. This is a supervisor-level instruction. Other registers altered: • None PowerPC Architecture Level Supervisor Level OEA Ð Instruction Set Page 414 of 785 32-Bit 64-Bit 64-Bit Bridge Optional Form X pem8.fm.2.0 June 10, 2003 Programming Environments Manual PowerPC RISC Microprocessor Family dcbst dcbst Data Cache Block Store (x’7C00 006C’) dcbst rA,rB Reserved 31 0 00 000 5 6 A 10 11 B 15 16 54 20 21 0 30 31 EA is the sum (rA|0) + (rB). The dcbst instruction executes as follows: • If the block containing the byte addressed by EA is in coherency-required mode, and a block containing the byte addressed by EA is in the data cache of any processor and has been modified, the writing of it to main memory is initiated. • If the block containing the byte addressed by EA is in coherency-not-required mode, and a block containing the byte addressed by EA is in the data cache of this processor and has been modified, the writing of it to main memory is initiated. The function of this instruction is independent of the write-through and caching-inhibited/allowed modes of the block containing the byte addressed by EA. The processor treats this instruction as a load from the addressed byte with respect to address translation and memory protection. It is also treated as a load for referenced and changed bit recording except that referenced and changed bit recording may not occur. Other registers altered: • None PowerPC Architecture Level VEA pem8.fm.2.0 June 10, 2003 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form X Instruction Set Page 415 of 785 Programming Environments Manual PowerPC RISC Microprocessor Family dcbt dcbt Data Cache Block Touch (x’7C00 022C’) dcbt rA,rB Reserved 31 0 00 000 5 6 A 10 11 B 15 16 278 20 21 0 30 31 EA is the sum (rA|0) + (rB). This instruction is a hint that performance will possibly be improved if the block containing the byte addressed by EA is fetched into the data cache, because the program will probably soon load from the addressed byte. If the block is caching-inhibited, the hint is ignored and the instruction is treated as a no-op. Executing dcbt does not cause the system alignment error handler to be invoked. This instruction is treated as a load from the addressed byte with respect to address translation, memory protection, and reference and change recording except that referenced and changed bit recording may not occur. Additionally, no exception occurs in the case of a translation fault or protection violation. The program uses the dcbt instruction to request a cache block fetch before it is actually needed by the program. The program can later execute load instructions to put data into registers. However, the processor is not obliged to load the addressed block into the data cache. Note that this instruction is defined architecturally to perform the same functions as the dcbtst instruction. Both are defined in order to allow implementations to differentiate the bus actions when fetching into the cache for the case of a load and for a store. Other registers altered: • None PowerPC Architecture Level VEA Instruction Set Page 416 of 785 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form X pem8.fm.2.0 June 10, 2003 Programming Environments Manual PowerPC RISC Microprocessor Family dcbtst dcbtst Data Cache Block Touch for Store (x’7C00 01EC’) dcbtst rA,rB Reserved 31 0 00 000 5 6 A 10 11 B 15 16 246 20 21 0 30 31 EA is the sum (rA|0) + (rB). This instruction is a hint that performance will possibly be improved if the block containing the byte addressed by EA is fetched into the data cache, because the program will probably soon store from the addressed byte. If the block is caching-inhibited, the hint is ignored and the instruction is treated as a no-op. Executing dcbtst does not cause the system alignment error handler to be invoked. This instruction is treated as a load from the addressed byte with respect to address translation, memory protection, and reference and change recording except that referenced and changed bit recording may not occur. Additionally, no exception occurs in the case of a translation fault or protection violation. The program uses dcbtst to request a cache block fetch to potentially improve performance for a subsequent store to that EA, as that store would then be to a cached location. However, the processor is not obliged to load the addressed block into the data cache. Note that this instruction is defined architecturally to perform the same functions as the dcbt instruction. Both are defined in order to allow implementations to differentiate the bus actions when fetching into the cache for the case of a load and for a store. Other registers altered: • None PowerPC Architecture Level VEA pem8.fm.2.0 June 10, 2003 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form X Instruction Set Page 417 of 785 Programming Environments Manual PowerPC RISC Microprocessor Family dcbz dcbz Data Cache Block Clear to Zero (x’7C00 07EC’) dcbz rA,rB [POWER mnemonic: dclz] Reserved 31 0 00 000 5 6 A 10 11 B 15 16 1014 20 21 0 30 31 EA is the sum (rA|0) + (rB). The dcbz instruction executes as follows: • If the cache block containing the byte addressed by EA is in the data cache, all bytes are cleared. • If the cache block containing the byte addressed by EA is not in the data cache and the corresponding memory page or block is caching-allowed, the cache block is allocated (and made valid) in the data cache without fetching the block from main memory, and all bytes are cleared. • If the page containing the byte addressed by EA is in caching-inhibited or write-through mode, either all bytes of main memory that correspond to the addressed cache block are cleared or the alignment exception handler is invoked. The exception handler can then clear all bytes in main memory that correspond to the addressed cache block. • If the cache block containing the byte addressed by EA is in coherency-required mode, and the cache block exists in the data cache(s) of any other processor(s), it is kept coherent in those caches (i.e. the processor performs the appropriate bus transactions to enforce this). This instruction is treated as a store to the addressed byte with respect to address translation, memory protection, referenced and changed recording. It is also treated as a store with respect to the ordering enforced by eieio and the ordering enforced by the combination of caching-inhibited and guarded attributes for a page (or block). Other registers altered: • None The PowerPC OEA describes how the dcbz instruction may establish a block in the data cache without verifying that the associated physical address is valid. This scenario can cause a delayed machine check exception; see 6. , “Exceptions,” for a discussion about this type of machine check exception. PowerPC Architecture Level VEA Instruction Set Page 418 of 785 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form X pem8.fm.2.0 June 10, 2003 Programming Environments Manual PowerPC RISC Microprocessor Family divdx divdx 64-Bit Implementations Only Divide Double Word (x’7C00 03D2’) divd divd. divdo divdo. rD,rA,rB rD,rA,rB rD,rA,rB rD,rA,rB 31 0 D 5 6 (OE = 0 Rc = 0) (OE = 0 Rc = 1) (OE = 1 Rc = 0) (OE = 1 Rc = 1) A 10 11 B OE 15 16 489 20 21 22 Rc 30 31 dividend[0–63] ← (rA) divisor[0–63] ← (rB) rD ← dividend + divisor The 64-bit dividend is the contents of rA. The 64-bit divisor is the contents of rB. The 64-bit quotient is placed into rD. The remainder is not supplied as a result. Both the operands and the quotient are interpreted as signed integers. The quotient is the unique signed integer that satisfies the equation—dividend = (quotient ∗ divisor) + r—where 0 ð r < |divisor| if the dividend is non-negative, and –|divisor| < r ð 0 if the dividend is negative. If an attempt is made to perform the divisions—0x8000_0000_0000_0000 ÷ –1 or÷ 0—the contents of rD are undefined, as are the contents of the LT, GT, and EQ bits of the CR0 field (if Rc = 1). In this case, if OE = 1 then OV is set. This instruction is defined only for 64-bit implementations. Using it on a 32-bit implementation will cause the system illegal instruction error handler to be invoked. The 64-bit signed remainder of dividing (rA) by (rB) can be computed as follows, except in the case that (rA) = –263 and (rB) = –1: divd mulld subf rD,rA,rB rD,rD,rB rD,rD,rA # rD = quotient # rD = quotient * divisor # rD = remainder Other registers altered: • Condition Register (CR0 field): Affected: LT, GT, EQ, SO(if Rc = 1) • XER: Affected: SO, OV (if OE = 1) Note: The setting of the affected bits in the XER is mode-independent, and reflects overflow of the 64-bit result. PowerPC Architecture Level UISA pem8.fm.2.0 June 10, 2003 Supervisor Level 32-Bit 64-Bit Ð 64-Bit Bridge Optional Form XO Instruction Set Page 419 of 785 Programming Environments Manual PowerPC RISC Microprocessor Family divdux divdux 64-Bit Implementations Only Divide Double Word Unsigned (x’7C00 0392’) divdu divdu. divduo divduo. rD,rA,rB rD,rA,rB rD,rA,rB rD,rA,rB 31 0 D 5 6 (OE = 0 Rc = 0) (OE = 0 Rc = 1) (OE = 1 Rc = 0) (OE = 1 Rc = 1) A 10 11 B OE 15 16 457 20 21 22 Rc 30 31 dividend[0–63] ← (rA) divisor[0–63] ← (rB) rD ← dividend + divisor The 64-bit dividend is the contents of rA. The 64-bit divisor is the contents of rB. The 64-bit quotient of the dividend and divisor is placed into rD. The remainder is not supplied as a result. Both the operands and the quotient are interpreted as unsigned integers, except that if Rc is set to 1 the first three bits of CR0 field are set by signed comparison of the result to zero. The quotient is the unique unsigned integer that satisfies the equation—dividend = (quotient ∗ divisor) + r—where 0 ð r < divisor. If an attempt is made to perform the division— ÷ 0—the contents of rD are undefined as are the contents of the LT, GT, and EQ bits of the CR0 field (if Rc = 1). In this case, if OE = 1 then OV is set. This instruction is defined only for 64-bit implementations. Using it on a 32-bit implementation will cause the system illegal instruction error handler to be invoked. The 64-bit unsigned remainder of dividing (rA) by (rB) can be computed as follows: divdu mulld subf rD,rA,rB rD,rD,rB rD,rD,rA # rD = quotient # rD = quotient * divisor # rD = remainder Other registers altered: • Condition Register (CR0 field): Affected: LT, GT, EQ, SO(if Rc = 1) • XER: Affected: SO, OV(if OE = 1) Note: The setting of the affected bits in the XER is mode-independent, and reflects overflow of the 64-bit result. PowerPC Architecture Level UISA Instruction Set Page 420 of 785 Supervisor Level 32-Bit 64-Bit Ð 64-Bit Bridge Optional Form XO pem8.fm.2.0 June 10, 2003 Programming Environments Manual PowerPC RISC Microprocessor Family divwx divwx Divide Word (x’7C00 03D6’) divw divw. divwo divwo. rD,rA,rB rD,rA,rB rD,rA,rB rD,rA,rB 31 0 D 5 6 (OE = 0 Rc = 0) (OE = 0 Rc = 1) (OE = 1 Rc = 0) (OE = 1 Rc = 1) A 10 11 B 15 16 OE 491 20 21 22 Rc 30 31 dividend[0–63] ← EXTS(rA[32–63]) divisor[0–63] ← EXTS(rB[32–63]) rD[32–63] ← dividend ÷ divisor rD[0–31] ← undefined The 64-bit dividend is the sign-extended value of the contents of the low-order 32 bits of rA. The 64-bit divisor is the sign-extended value of the contents of the low-order 32 bits of rB. The 6432-bit quotient is formed and placed in rD. The low-order 32 bits of the 64-bit quotient are placed into the low-order 32 bits of rD. The contents of the high-order 32 bits of rD are undefined. The remainder is not supplied as a result. Both the operands and the quotient are interpreted as signed integers. The quotient is the unique signed integer that satisfies the equation—dividend = (quotient * divisor) + r where 0 ð r < |divisor| (if the dividend is non-negative), and –|divisor| < r ð 0 (if the dividend is negative). If an attempt is made to perform either of the divisions—0x8000_0000 ÷ –1 or ÷ 0, then the contents of rD are undefined, as are the contents of the LT, GT, and EQ bits of the CR0 field (if Rc = 1). In this case, if OE = 1 then OV is set. The 32-bit signed remainder of dividing the contents of the low-order 32 bits of rA by the contents of the loworder 32 bits of rB can be computed as follows, except in the case that the contents of the low-order 32 bits of rA = –231 and the contents of the low-order 32 bits of rB = –1. divw mullw subf rD,rA,rB rD,rD,rB rD,rD,rA # rD = quotient # rD = quotient ∗ divisor # rD = remainder Other registers altered: • Condition Register (CR0 field): Affected: LT, GT, EQ, SO(if Rc = 1) LT, GT, EQ undefined(if Rc =1 and 64-bit mode) • XER: Affected: SO, OV(if OE = 1) Note: The setting of the affected bits in the XER is mode-independent, and reflects overflow of the loworder 32-bit result. PowerPC Architecture Level UISA pem8.fm.2.0 June 10, 2003 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form XO Instruction Set Page 421 of 785 Programming Environments Manual PowerPC RISC Microprocessor Family divwux divwux Divide Word Unsigned (x’7C00 0396’) divwu divwu. divwuo divwuo. rD,rA,rB rD,rA,rB rD,rA,rB rD,rA,rB 31 0 D 5 6 (OE = 0 Rc = 0) (OE = 0 Rc = 1) (OE = 1 Rc = 0) (OE = 1 Rc = 1) A 10 11 B 15 16 OE 459 20 21 22 Rc 30 31 dividend[0–63] ← (32)0 || (rA)[32–63] divisor[0–63] ← (32)0 || (rB)[32–63] rD[32–63] ← dividend ÷ divisor rD[0–31] ← undefined The 64-bit dividend is the zero-extended value of the contents of the low-order 32 bits of rA. The 64-bit divisor is the zero-extended value the contents of the low-order 32 bits of rB. A 6432-bit quotient is formed. The loworder 32 bits of the 6432-bit quotient areis placed into the low-order 32 bits of rD. The contents of the highorder 32 bits of rD are undefined. The remainder is not supplied as a result. Both operands and the quotient are interpreted as unsigned integers, except that if Rc = 1 the first three bits of CR0 field are set by signed comparison of the result to zero. The quotient is the unique unsigned integer that satisfies the equation—dividend = (quotient ∗ divisor) + r (where 0 ð r < divisor). If an attempt is made to perform the division— ÷ 0—then the contents of rD are undefined as are the contents of the LT, GT, and EQ bits of the CR0 field (if Rc = 1). In this case, if OE = 1 then OV is set. The 32-bit unsigned remainder of dividing the contents of the low-order 32 bits of rA by the contents of the low-order 32 bits of rB can be computed as follows: divwurD,rA,rB# rD = quotient mullw rD,rD,rB# rD = quotient ∗ divisor subf rD,rD,rA # rD = remainder Other registers altered: • Condition Register (CR0 field): Affected: LT, GT, EQ, SO(if Rc = 1) LT, GT, EQ undefined(if Rc =1 and 64-bit mode) • XER: Affected: SO, OV(if OE = 1) Note: The setting of the affected bits in the XER is mode-independent, and reflects overflow of the loworder 32-bit result. PowerPC Architecture Level UISA Instruction Set Page 422 of 785 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form XO pem8.fm.2.0 June 10, 2003 Programming Environments Manual PowerPC RISC Microprocessor Family eciwx eciwx External Control In Word Indexed (x’7C00 026C’) eciwx rD,rA,rB Reserved 31 0 D 5 6 A 10 11 B 15 16 310 0 20 21 30 31 The eciwx instruction and the EAR register can be very efficient when mapping special devices such as graphics devices that use addresses as pointers. if rA = 0 then b ← 0 else b← (rA) EA ← b + (rB) paddr ← address translation of EA send load word request for paddr to device identified by EAR[RID] rD ← (32)0 || word from device EA is the sum (rA|0) + (rB). A load word request for the physical address (referred to as real address in the architecture specification) corresponding to EA is sent to the device identified by EAR[RID], bypassing the cache. The word returned by the device is placed in the low-order 32 bits of rD. The contents of the high-order 32 bits of rD are cleared. EAR[E] must be 1. If it is not, a DSI exception is generated. EA must be a multiple of four. If it is not, one of the following occurs: • A system alignment exception is generated. • A DSI exception is generated (possible only if EAR[E] = 0). • The results are boundedly undefined. The eciwx instruction is supported for EAs that reference memory segments in which SR[T] = 1 (or STE[T] = 1) and for EAs mapped by the DBAT registers. If the EA references a direct-store segment (SR[T] = 1 or STE[T] = 1), either a DSI exception occurs or the results are boundedly undefined. However, note that the direct-store facility is being phased out of the architecture and will not likely be supported in future devices. Thus, software should not depend on its effects. If this instruction is executed when MSR[DR] = 0 (real addressing mode), the results are boundedly undefined. This instruction is treated as a load from the addressed byte with respect to address translation, memory protection, referenced and changed bit recording, and the ordering performed by eieio. This instruction is optional in the PowerPC architecture. Other registers altered: • None PowerPC Architecture Level VEA pem8.fm.2.0 June 10, 2003 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form Ð X Instruction Set Page 423 of 785 Programming Environments Manual PowerPC RISC Microprocessor Family ecowx ecowx External Control Out Word Indexed (x’7C00 036C’) ecowx rS,rA,rB Reserved 31 0 S 5 6 A 10 11 B 15 16 438 0 20 21 30 31 The ecowx instruction and the EAR register can be very efficient when mapping special devices such as graphics devices that use addresses as pointers. if rA = 0 then b ← 0 else b ← (rA) EA ← b + (rB) paddr ← address translation of EA send store word request for paddr to device identified by EAR[RID] send rS[32–63] to device EA is the sum (rA|0) + (rB). A store word request for the physical address corresponding to EA and the contents of the low-order 32 bits of rS are sent to the device identified by EAR[RID], bypassing the cache. EAR[E] must be 1, if it is not, a DSI exception is generated. EA must be a multiple of four. If it is not, one of the following occurs: • A system alignment exception is generated. • A DSI exception is generated (possible only if EAR[E] = 0). • The results are boundedly undefined. The ecowx instruction is supported for effective addresses that reference memory segments in which SR[T] = 0 (or STE[T] = 0), and for EAs mapped by the DBAT registers. If the EA references a direct-store segment (SR[T] = 1 or STE[T] = 1), either a DSI exception occurs or the results are boundedly undefined. However, note that the direct-store facility is being phased out of the architecture and will not likely be supported in future devices. Thus, software should not depend on its effects. If this instruction is executed when MSR[DR] = 0 (real addressing mode), the results are boundedly undefined. This instruction is treated as a store from the addressed byte with respect to address translation, memory protection, and referenced and changed bit recording, and the ordering performed by eieio. Note that software synchronization is required in order to ensure that the data access is performed in program order with respect to data accesses caused by other store or ecowx instructions, even though the addressed byte is assumed to be caching-inhibited and guarded. This instruction is optional in the PowerPC architecture. Other registers altered: • None PowerPC Architecture Level VEA Instruction Set Page 424 of 785 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form Ð X pem8.fm.2.0 June 10, 2003 Programming Environments Manual PowerPC RISC Microprocessor Family eieio eieio Enforce In-Order Execution of I/O (x’7C00 06AC’) Reserved 31 0 00 000 5 6 0 0000 10 11 0000 0 15 16 854 20 21 0 30 31 The eieio instruction provides an ordering function for the effects of load and store instructions executed by a processor. These loads and stores are divided into two sets, which are ordered separately. The memory accesses caused by a dcbz or a dcba instruction are ordered like a store. The two sets follow: 1. Loads and stores to memory that is both caching-inhibited and guarded, and stores to memory that is write-through required. The eieio instruction controls the order in which the accesses are performed in main memory. It ensures that all applicable memory accesses caused by instructions preceding the eieio instruction have completed with respect to main memory before any applicable memory accesses caused by instructions following the eieio instruction access main memory. It acts like a barrier that flows through the memory queues and to main memory, preventing the reordering of memory accesses across the barrier. No ordering is performed for dcbz if the instruction causes the system alignment error handler to be invoked. All accesses in this set are ordered as a single set—that is, there is not one order for loads and stores to caching-inhibited and guarded memory and another order for stores to write-through required memory. • Stores to memory that have all of the following attributes—caching-allowed, write-through not required, and memory-coherency required. The eieio instruction controls the order in which the accesses are performed with respect to coherent memory. It ensures that all applicable stores caused by instructions preceding the eieio instruction have completed with respect to coherent memory before any applicable stores caused by instructions following the eieio instruction complete with respect to coherent memory. With the exception of dcbz and dcba, eieio does not affect the order of cache operations (whether caused explicitly by execution of a cache management instruction, or implicitly by the cache coherency mechanism). For more information, refer to 5. , “Cache Model and Memory Coherency.” The eieio instruction does not affect the order of accesses in one set with respect to accesses in the other set. The eieio instruction may complete before memory accesses caused by instructions preceding the eieio instruction have been performed with respect to main memory or coherent memory as appropriate. The eieio instruction is intended for use in managing shared data structures, in accessing memory-mapped I/O, and in preventing load/store combining operations in main memory. For the first use, the shared data structure and the lock that protects it must be altered only by stores that are in the same set (1 or 2; see previous discussion). For the second use, eieio can be thought of as placing a barrier into the stream of memory accesses issued by a processor, such that any given memory access appears to be on the same side of the barrier to both the processor and the I/O device. Because the processor performs store operations in order to memory that is designated as both cachinginhibited and guarded (refer to Section 5.1.1 , “Memory Access Ordering”), the eieio instruction is needed for such memory only when loads must be ordered with respect to stores or with respect to other loads. pem8.fm.2.0 June 10, 2003 Instruction Set Page 425 of 785 Programming Environments Manual PowerPC RISC Microprocessor Family Note that the eieio instruction does not connect hardware considerations to it such as multiprocessor implementations that send an eieio address-only broadcast (useful in some designs). For example, if a design has an external buffer that re-orders loads and stores for better bus efficiency, the eieio broadcast signals to that buffer that previous loads/stores (marked caching-inhibited, guarded, or write-through required) must complete before any following loads/stores (marked caching-inhibited, guarded, or write-through required). Other registers altered: • None PowerPC Architecture Level VEA Instruction Set Page 426 of 785 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form X pem8.fm.2.0 June 10, 2003 Programming Environments Manual PowerPC RISC Microprocessor Family eqvx eqvx Equivalent (x’7C00 0238’) eqv eqv. rA,rS,rB rA,rS,rB 31 0 S 5 6 (Rc = 0) (Rc = 1) B A 10 11 15 16 284 21 22 Rc 30 31 rA ← (rS) ≡ (rB) The contents of rS are XORed with the contents of rB and the complemented result is placed into rA. Other registers altered: • Condition Register (CR0 field): Affected: LT, GT, EQ, SO(if Rc = 1) PowerPC Architecture Level UISA pem8.fm.2.0 June 10, 2003 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form X Instruction Set Page 427 of 785 Programming Environments Manual PowerPC RISC Microprocessor Family extsbx extsbx Extend Sign Byte (x’7C00 0774’) extsb extsb. rA,rS rA,rS (Rc = 0) (Rc = 1) Reserved 31 0 S 5 6 A 10 11 0000 0 15 16 954 20 21 Rc 30 31 S ← rS[5624] rA[56–6324-31] ← rS[56–6324-31] rA[0–5523] ← (5624)S The contents of the low-order eight bits of rS[24-31] are placed into the low-order eight bits of rA[24-31]. Bit 5624 of rS is placed into the remaining bits of rA[0-23]. Other registers altered: • Condition Register (CR0 field): Affected: LT, GT, EQ, SO(if Rc = 1) PowerPC Architecture Level UISA Instruction Set Page 428 of 785 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form X pem8.fm.2.0 June 10, 2003 Programming Environments Manual PowerPC RISC Microprocessor Family extshx extshx Extend Sign Half Word (x’7C00 0734’) extsh extsh. rA,rS rA,rS (Rc = 0) (Rc = 1) [POWER mnemonics: exts, exts.] Reserved 31 0 S 5 6 A 10 11 0000 0 15 16 922 20 21 Rc 30 31 S ← rS[4816] rA[48–6316-31] ← rS[48–6316-31] rA[0–470-15] ← (4816)S The contents of the low-order 16 bits of rS[16-31] are placed into the low-order 16 bits of rA[16-31]. Bit 4816 of rS is placed into the remaining bits of rA[0–15]. Other registers altered: • Condition Register (CR0 field): Affected: LT, GT, EQ, SO(if Rc = 1) PowerPC Architecture Level UISA pem8.fm.2.0 June 10, 2003 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form X Instruction Set Page 429 of 785 Programming Environments Manual PowerPC RISC Microprocessor Family extswx 64-Bit Implementations Only extswx Extend Sign Word (x’7C00 07B4’) extsw extsw. rA,rS rA,rS (Rc = 0) (Rc = 1) Reserved 31 0 S 5 6 A 10 11 0000 0 986 15 16 20 21 Rc 30 31 S ← rS[32] rA[32–63] ← rS[32–63] rA[0–31] ← (32)S The contents of the low-order 32 bits of rS are placed into the low-order 32 bits of rA. Bit 32 of rS is placed into the high-order 32 bits of rA. This instruction is defined only for 64-bit implementations. Using it on a 32-bit implementation will cause the system illegal instruction error handler to be invoked. Other registers altered: • Condition Register (CR0 field): Affected: LT, GT, EQ, SO(if Rc = 1) PowerPC Architecture Level UISA Instruction Set Page 430 of 785 Supervisor Level 32-Bit 64-Bit Ð 64-Bit Bridge Optional Form X pem8.fm.2.0 June 10, 2003 Programming Environments Manual PowerPC RISC Microprocessor Family fabsx fabsx Floating Absolute Value (x’FC00 0210’) fabs fabs. frD,frB frD,frB (Rc = 0) (Rc = 1) Reserved 63 0 D 5 6 0 0000 10 11 B 15 16 264 20 21 Rc 30 31 The contents of frB with bit 0 cleared are placed into frD. Note that the fabs instruction treats NaNs just like any other kind of value. That is, the sign bit of a NaN may be altered by fabs. This instruction does not alter the FPSCR. Other registers altered: • Condition Register (CR1 field): Affected: FX, FEX, VX, OX(if Rc = 1) PowerPC Architecture Level UISA pem8.fm.2.0 June 10, 2003 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form X Instruction Set Page 431 of 785 Programming Environments Manual PowerPC RISC Microprocessor Family faddx faddx Floating Add (Double-Precision) (x’FC00 002A’) fadd fadd. frD,frA,frB frD,frA,frB (Rc = 0) (Rc = 1) [POWER mnemonics: fa, fa.] B 000 00 21 Rc The floating-point operand in frA is added to the floating-point operand in frB. If the most- significant bit of the resultant significand is not a one, the result is normalized. The result is rounded to double-precision under control of the floating-point rounding control field RN of the FPSCR and placed into frD. Floating-point addition is based on exponent comparison and addition of the two significands. The exponents of the two operands are compared, and the significand accompanying the smaller exponent is shifted right, with its exponent increased by one for each bit shifted, until the two exponents are equal. The two significands are then added or subtracted as appropriate, depending on the signs of the operands. All 53 bits in the significand as well as all three guard bits (G, R, and X) enter into the computation. If a carry occurs, the sum's significand is shifted right one bit position and the exponent is increased by one. FPSCR[FPRF] is set to the class and sign of the result, except for invalid operation exceptions when FPSCR[VE] = 1. Other registers altered: • Condition Register (CR1 field): Affected: FX, FEX, VX, OX (if Rc = 1) • Floating-Point Status and Control Register: Affected: FPRF, FR, FI, FX, OX, UX, XX,VXSNAN, VXISI PowerPC Architecture Level UISA Instruction Set Page 432 of 785 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form A pem8.fm.2.0 June 10, 2003 Programming Environments Manual PowerPC RISC Microprocessor Family faddsx faddsx Floating Add Single (x’EC00 002A’) fadds fadds. frD,frA,frB frD,frA,frB (Rc = 0) (Rc = 1) Reserved 59 0 D 5 6 B A 10 11 15 16 000 00 20 21 21 25 26 Rc 30 31 The floating-point operand in frA is added to the floating-point operand in frB. If the most-significant bit of the resultant significand is not a one, the result is normalized. The result is rounded to the single-precision under control of the floating-point rounding control field RN of the FPSCR and placed into frD. Floating-point addition is based on exponent comparison and addition of the two significands. The exponents of the two operands are compared, and the significand accompanying the smaller exponent is shifted right, with its exponent increased by one for each bit shifted, until the two exponents are equal. The two significands are then added or subtracted as appropriate, depending on the signs of the operands. All 53 bits in the significand as well as all three guard bits (G, R, and X) enter into the computation. If a carry occurs, the sum's significand is shifted right one bit position and the exponent is increased by one. FPSCR[FPRF] is set to the class and sign of the result, except for invalid operation exceptions when FPSCR[VE] = 1. Other registers altered: • Condition Register (CR1 field): Affected: FX, FEX, VX, OX (if Rc = 1) • Floating-Point Status and Control Register: Affected: FPRF, FR, FI, FX, OX, UX, XX,VXSNAN, VXISI PowerPC Architecture Level UISA pem8.fm.2.0 June 10, 2003 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form A Instruction Set Page 433 of 785 Programming Environments Manual PowerPC RISC Microprocessor Family fcfidx fcfidx 64-Bit Implementations Only Floating Convert from Integer Double Word (x’FC00 069C’) fcfid fcfid. frD,frB frD,frB (Rc = 0) (Rc = 1) Reserved 63 0 D 5 6 0 0000 10 11 B 846 15 16 20 21 Rc 30 31 The 64-bit signed fixed-point operand in register frB is converted to an infinitely precise floating-point integer. The result of the conversion is rounded to double-precision using the rounding mode specified by FPSCR[RN] and placed into register frD. FPSCR[FPRF] is set to the class and sign of the result. FPSCR[FR] is set if the result is incremented when rounded. FPSCR[FI] is set if the result is inexact. The conversion is described fully in Section D.4.3 , “Floating-Point Convert from Integer Model.” This instruction is defined only for 64-bit implementations. Using it on a 32-bit implementation will cause the system illegal instruction error handler to be invoked. Other registers altered: • Condition Register (CR1 field): Affected: FX, VX, FEX, OX(if Rc = 1) • Floating-point Status and Control Register: Affected: FPRF, FR, FI, FX, XX PowerPC Architecture Level UISA Instruction Set Page 434 of 785 Supervisor Level 32-Bit 64-Bit Ð 64-Bit Bridge Optional Form X pem8.fm.2.0 June 10, 2003 Programming Environments Manual PowerPC RISC Microprocessor Family fcmpo fcmpo Floating Compare Ordered (x’FC00 0040’) fcmpo crfD,frA,frB Reserved 63 0 crfD 5 6 00 8 A 9 10 11 if (frA) is a NaN or (frB) is a NaN then else if (frA)< (frB) then else if (frA)> (frB) then else B 15 16 32 20 21 0 30 31 c ← 0b0001 c ← 0b1000 c ← 0b0100 c ← 0b0010 FPCC ← c CR[4 ∗ crfD–4 ∗ crfD + 3] ← c if (frA) is an SNaN or (frB) is an SNaN then VXSNAN ← 1 if VE = 0 then VXVC ← 1 else if (frA) is a QNaN or (frB) is a QNaN then VXVC ← 1 The floating-point operand in frA is compared to the floating-point operand in frB. The result of the compare is placed into CR field crfD and the FPCC. If one of the operands is a NaN, either quiet or signaling, then CR field crfD and the FPCC are set to reflect unordered. If one of the operands is a signaling NaN, then VXSNAN is set, and if invalid operation is disabled (VE = 0) then VXVC is set. Otherwise, if one of the operands is a QNaN, then VXVC is set. Other registers altered: • Condition Register (CR field specified by operand crfD): Affected: LT, GT, EQ, UN • Floating-Point Status and Control Register: Affected: FPCC, FX, VXSNAN, VXVC PowerPC Architecture Level UISA pem8.fm.2.0 June 10, 2003 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form X Instruction Set Page 435 of 785 Programming Environments Manual PowerPC RISC Microprocessor Family fcmpu fcmpu Floating Compare Unordered (x’FC00 0000’) fcmpu crfD,frA,frB Reserved 63 0 crfD 5 6 00 8 A 9 10 11 B 15 16 0000000000 20 21 0 30 31 if (frA) is a NaN or (frB) is a NaN then c ← 0b0001 else if (frA) < (frB) then c ← 0b1000 else if (frA) > (frB) then c ← 0b0100 else c ← 0b0010 FPCC ← c CR[4 ∗ crfD–4 ∗ crfD + 3] ← c if (frA) is an SNaN or (frB) is an SNaN then VXSNAN ← 1 The floating-point operand in register frA is compared to the floating-point operand in register frB. The result of the compare is placed into CR field crfD and the FPCC. If one of the operands is a NaN, either quiet or signaling, then CR field crfD and the FPCC are set to reflect unordered. If one of the operands is a signaling NaN, then VXSNAN is set. Other registers altered: • Condition Register (CR field specified by operand crfD): Affected: LT, GT, EQ, UN • Floating-Point Status and Control Register: Affected: FPCC, FX, VXSNAN PowerPC Architecture Level UISA Instruction Set Page 436 of 785 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form X pem8.fm.2.0 June 10, 2003 Programming Environments Manual PowerPC RISC Microprocessor Family fctidx fctidx 64-Bit Implementations Only Floating Convert to Integer Double Word (x’FC00 065C’) fctid fctid. frD,frB frD,frB (Rc = 0) (Rc = 1) Reserved 63 0 D 5 6 0 0000 10 11 B 814 15 16 20 21 Rc 30 31 The floating-point operand in frB is converted to a 64-bit signed fixed-point integer, using the rounding mode specified by FPSCR[RN], and placed into frD. If the operand in frB is greater than 263– 1, then frD is set to 0x7FFF_FFFF_FFFF_FFFF. If the operand in frB is less than –263, then frD is set to 0x8000_0000_0000_0000. Except for enabled invalid operation exceptions, FPSCR[FPRF] is undefined. FPSCR[FR] is set if the result is incremented when rounded. FPSCR[FI] is set if the result is inexact. The conversion is described fully in Section D.4.2 , “Floating-Point Convert to Integer Model.” This instruction is defined only for 64-bit implementations. Using it on a 32-bit implementation will cause the system illegal instruction error handler to be invoked. Other registers altered: • Condition Register (CR1 field): Affected: FX, FEX, VX, OX(if Rc = 1) • Floating-Point Status and Control Register: Affected: FPRF (undefined), FR, FI, FX, XX, VXSNAN, VXCVI PowerPC Architecture Level UISA pem8.fm.2.0 June 10, 2003 Supervisor Level 32-Bit 64-Bit Ð 64-Bit Bridge Optional Form X Instruction Set Page 437 of 785 Programming Environments Manual PowerPC RISC Microprocessor Family fctidzx 64-Bit Implementations Only fctidzx Floating Convert to Integer Double Word with Round toward Zero (x’FC00 065E’) fctidz fctidz. frD,frB frD,frB (Rc = 0) (Rc = 1) Reserved 63 0 D 5 6 0 0000 10 11 B 815 15 16 20 21 Rc 30 31 The floating-point operand in frB is converted to a 64-bit signed fixed-point integer, using the rounding mode round toward zero, and placed into frD. If the operand in frB is greater than 263 – 1, then frD is set to 0x7FFF_FFFF_FFFF_FFFF. If the operand in frB is less than –263, then frD is set to 0x8000_0000_0000_0000. Except for enabled invalid operation exceptions, FPSCR[FPRF] is undefined. FPSCR[FR] is set if the result is incremented when rounded. FPSCR[FI] is set if the result is inexact. The conversion is described fully in Section D.4.2 , “Floating-Point Convert to Integer Model.” This instruction is defined only for 64-bit implementations. Using it on a 32-bit implementation will cause the system illegal instruction error handler to be invoked. Other registers altered: • Condition Register (CR1 field): Affected: FX, FEX, VX, OX(if Rc = 1) • Floating-Point Status and Control Register: Affected: FPRF (undefined), FR, FI, FX, XX, VXSNAN, VXCVI PowerPC Architecture Level UISA Instruction Set Page 438 of 785 Supervisor Level 32-Bit 64-Bit Ð 64-Bit Bridge Optional Form X pem8.fm.2.0 June 10, 2003 Programming Environments Manual PowerPC RISC Microprocessor Family fctiwx fctiwx Floating Convert to Integer Word (x’FC00 001C’) fctiw fctiw. frD,frB frD,frB (Rc = 0) (Rc = 1) Reserved 63 0 D 5 6 0 0000 10 11 B 14 15 16 20 21 Rc 30 31 The floating-point operand in register frB is converted to a 32-bit signed integer, using the rounding mode specified by FPSCR[RN], and placed in bits 32–63 of frD. Bits 0–31 of frD are undefined. If the operand in frB are greater than 231 – 1, bits 32–63 of frD are set to 0x7FFF_FFFF. If the operand in frB are less than –231, bits 32–63 of frD are set to 0x8000_0000. The conversion is described fully in Section D.4.2 , “Floating-Point Convert to Integer Model.” Except for trap-enabled invalid operation exceptions, FPSCR[FPRF] is undefined. FPSCR[FR] is set if the result is incremented when rounded. FPSCR[FI] is set if the result is inexact. Other registers altered: • Condition Register (CR1 field): Affected: FX, FEX, VX, OX (if Rc = 1) • Floating-Point Status and Control Register: Affected: FPRF (undefined), FR, FI, FX, XX, VXSNAN, VXCVI PowerPC Architecture Level UISA pem8.fm.2.0 June 10, 2003 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form X Instruction Set Page 439 of 785 Programming Environments Manual PowerPC RISC Microprocessor Family fctiwzx fctiwzx Floating Convert to Integer Word with Round toward Zero (x’FC00 001E’) fctiwz fctiwz. frD,frB frD,frB (Rc = 0) (Rc = 1) Reserved 63 0 D 5 6 0 0000 10 11 B 15 15 16 20 21 Rc 30 31 The floating-point operand in register frB is converted to a 32-bit signed integer, using the rounding mode round toward zero, and placed in bits 32–63 of frD. Bits 0–31 of frD are undefined. If the operand in frB is greater than 231 – 1, bits 32–63 of frD are set to 0x7FFF_FFFF. If the operand in frB is less than –231, bits 32–63 of frD are set to 0x 8000_0000. The conversion is described fully in Section D.4.2 , “Floating-Point Convert to Integer Model.” Except for trap-enabled invalid operation exceptions, FPSCR[FPRF] is undefined. FPSCR[FR] is set if the result is incremented when rounded. FPSCR[FI] is set if the result is inexact. Other registers altered: • Condition Register (CR1 field): Affected: FX, FEX, VX, OX(if Rc = 1) • Floating-Point Status and Control Register: Affected: FPRF (undefined), FR, FI, FX, XX, VXSNAN, VXCVI PowerPC Architecture Level UISA Instruction Set Page 440 of 785 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form X pem8.fm.2.0 June 10, 2003 Programming Environments Manual PowerPC RISC Microprocessor Family fdivx fdivx Floating Divide (Double-Precision) (x’FC00 0024’) fdiv fdiv. frD,frA,frB frD,frA,frB (Rc = 0) (Rc = 1) [POWER mnemonics: fd, fd.] Reserved 63 0 D 5 6 B A 10 11 15 16 000 00 20 21 18 Rc 25 26 30 31 The floating-point operand in register frA is divided by the floating-point operand in register frB. The remainder is not supplied as a result. If the most-significant bit of the resultant significand is not a one, the result is normalized. The result is rounded to double-precision under control of the floating-point rounding control field RN of the FPSCR and placed into frD. Floating-point division is based on exponent subtraction and division of the significands. FPSCR[FPRF] is set to the class and sign of the result, except for invalid operation exceptions when FPSCR[VE] = 1 and zero divide exceptions when FPSCR[ZE] = 1. Other registers altered: • Condition Register (CR1 field): Affected: FX, FEX, VX, OX(if Rc = 1) • Floating-Point Status and Control Register: Affected: FPRF, FR, FI, FX, OX, UX, ZX, XX, VXSNAN, VXIDI, VXZDZ PowerPC Architecture Level UISA pem8.fm.2.0 June 10, 2003 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form A Instruction Set Page 441 of 785 Programming Environments Manual PowerPC RISC Microprocessor Family fdivsx fdivsx Floating Divide Single (x’EC00 0024’) fdivs fdivs. frD,frA,frB frD,frA,frB (Rc = 0) (Rc = 1) Reserved 59 0 D 5 6 A 10 11 B 15 16 000 00 20 21 18 Rc 25 26 30 31 The floating-point operand in register frA is divided by the floating-point operand in register frB. The remainder is not supplied as a result. If the most-significant bit of the resultant significand is not a one, the result is normalized. The result is rounded to single-precision under control of the floating-point rounding control field RN of the FPSCR and placed into frD. Floating-point division is based on exponent subtraction and division of the significands. FPSCR[FPRF] is set to the class and sign of the result, except for invalid operation exceptions when FPSCR[VE] = 1 and zero divide exceptions when FPSCR[ZE] = 1. Other registers altered: • Condition Register (CR1 field): Affected: FX, FEX, VX, OX(if Rc = 1) • Floating-Point Status and Control Register: Affected: FPRF, FR, FI, FX, OX, UX, ZX, XX, VXSNAN, VXIDI, VXZDZ PowerPC Architecture Level UISA Instruction Set Page 442 of 785 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form A pem8.fm.2.0 June 10, 2003 Programming Environments Manual PowerPC RISC Microprocessor Family fmaddx fmaddx Floating Multiply-Add (Double-Precision) (x’FC00 003A’) fmadd fmadd. frD,frA,frC,frB frD,frA,frC,frB (Rc = 0) (Rc = 1) [POWER mnemonics: fma, fma.] 63 0 D 5 6 A 10 11 B 15 16 C 20 21 29 Rc 25 26 30 31 The following operation is performed: frD ← (frA ∗ frC) + frB The floating-point operand in register frA is multiplied by the floating-point operand in register frC. The floating-point operand in register frB is added to this intermediate result. If the most-significant bit of the resultant significand is not a one, the result is normalized. The result is rounded to double-precision under control of the floating-point rounding control field RN of the FPSCR and placed into frD. FPSCR[FPRF] is set to the class and sign of the result, except for invalid operation exceptions when FPSCR[VE] = 1. Other registers altered: • Condition Register (CR1 field): Affected: FX, FEX, VX, OX(if Rc = 1) • Floating-Point Status and Control Register: Affected: FPRF, FR, FI, FX, OX, UX, XX, VXSNAN, VXISI, VXIMZ PowerPC Architecture Level UISA pem8.fm.2.0 June 10, 2003 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form A Instruction Set Page 443 of 785 Programming Environments Manual PowerPC RISC Microprocessor Family fmaddsx fmaddsx Floating Multiply-Add Single (x’EC00 003A’) fmadds fmadds. frD,frA,frC,frB frD,frA,frC,frB 59 0 D 5 6 (Rc = 0) (Rc = 1) A 10 11 B 15 16 C 20 21 29 Rc 25 26 30 31 The following operation is performed: frD ← (frA ∗ frC) + frB The floating-point operand in register frA is multiplied by the floating-point operand in register frC. The floating-point operand in register frB is added to this intermediate result. If the most-significant bit of the resultant significand is not a one, the result is normalized. The result is rounded to single-precision under control of the floating-point rounding control field RN of the FPSCR and placed into frD. FPSCR[FPRF] is set to the class and sign of the result, except for invalid operation exceptions when FPSCR[VE] = 1. Other registers altered: • Condition Register (CR1 field): Affected: FX, FEX, VX, OX(if Rc = 1) • Floating-Point Status and Control Register: Affected: FPRF, FR, FI, FX, OX, UX, XX, VXSNAN, VXISI, VXIMZ PowerPC Architecture Level UISA Instruction Set Page 444 of 785 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form A pem8.fm.2.0 June 10, 2003 Programming Environments Manual PowerPC RISC Microprocessor Family fmrx fmrx Floating Move Register (Double-Precision) (x’FC00 0090’) fmr fmr. frD,frB frD,frB (Rc = 0) (Rc = 1) Reserved 63 0 D 5 6 0 0000 10 11 B 15 16 72 20 21 Rc 30 31 The following operation is performed: frD ← (frB) The contents of register frB are placed into frD. Other registers altered: • Condition Register (CR1 field): Affected: FX, FEX, VX, OX(if Rc = 1) PowerPC Architecture Level UISA pem8.fm.2.0 June 10, 2003 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form X Instruction Set Page 445 of 785 Programming Environments Manual PowerPC RISC Microprocessor Family fmsubx fmsubx Floating Multiply-Subtract (Double-Precision) x’FC00 0038’) fmsub fmsub. frD,frA,frC,frB frD,frA,frC,frB (Rc = 0) (Rc = 1) [POWER mnemonics: fms, fms.] 63 0 D 5 6 A 10 11 B 15 16 C 20 21 28 Rc 25 26 30 31 The following operation is performed: frD ← [frA ∗ frC] – frB The floating-point operand in register frA is multiplied by the floating-point operand in register frC. The floating-point operand in register frB is subtracted from this intermediate result. If the most-significant bit of the resultant significand is not a one, the result is normalized. The result is rounded to double-precision under control of the floating-point rounding control field RN of the FPSCR and placed into frD. FPSCR[FPRF] is set to the class and sign of the result, except for invalid operation exceptions when FPSCR[VE] = 1. Other registers altered: • Condition Register (CR1 field): Affected: FX, FEX, VX, OX(if Rc = 1) • Floating-Point Status and Control Register: Affected: FPRF, FR, FI, FX, OX, UX, XX, VXSNAN, VXISI, VXIMZ PowerPC Architecture Level UISA Instruction Set Page 446 of 785 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form A pem8.fm.2.0 June 10, 2003 Programming Environments Manual PowerPC RISC Microprocessor Family fmsubsx fmsubsx Floating Multiply-Subtract Single (x’EC00 0038’) fmsubs fmsubs. frD,frA,frC,frB frD,frA,frC,frB 59 0 D 5 6 (Rc = 0) (Rc = 1) A 10 11 B 15 16 C 20 21 28 Rc 25 26 30 31 The following operation is performed: frD ← [frA ∗ frC] – frB The floating-point operand in register frA is multiplied by the floating-point operand in register frC. The floating-point operand in register frB is subtracted from this intermediate result. If the most-significant bit of the resultant significand is not a one, the result is normalized. The result is rounded to single-precision under control of the floating-point rounding control field RN of the FPSCR and placed into frD. FPSCR[FPRF] is set to the class and sign of the result, except for invalid operation exceptions when FPSCR[VE] = 1. Other registers altered: • Condition Register (CR1 field): Affected: FX, FEX, VX, OX(if Rc = 1) • Floating-Point Status and Control Register: Affected: FPRF, FR, FI, FX, OX, UX, XX, VXSNAN, VXISI, VXIMZ PowerPC Architecture Level UISA pem8.fm.2.0 June 10, 2003 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form A Instruction Set Page 447 of 785 Programming Environments Manual PowerPC RISC Microprocessor Family fmulx fmulx Floating Multiply (Double-Precision) (x’FC00 0032’) fmul fmul. frD,frA,frC frD,frA,frC (Rc = 0) (Rc = 1) [POWER mnemonics: fm, fm.] Reserved 63 0 D 5 6 A 10 11 0000 0 15 16 C 20 21 25 Rc 25 26 30 31 The floating-point operand in register frA is multiplied by the floating-point operand in register frC. If the most-significant bit of the resultant significand is not a one, the result is normalized. The result is rounded to double-precision under control of the floating-point rounding control field RN of the FPSCR and placed into frD. Floating-point multiplication is based on exponent addition and multiplication of the significands. FPSCR[FPRF] is set to the class and sign of the result, except for invalid operation exceptions when FPSCR[VE] = 1. Other registers altered: • Condition Register (CR1 field): Affected: FX, FEX, VX, OX(if Rc = 1) • Floating-Point Status and Control Register: Affected: FPRF, FR, FI, FX, OX, UX, XX, VXSNAN, VXIMZ PowerPC Architecture Level UISA Instruction Set Page 448 of 785 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form A pem8.fm.2.0 June 10, 2003 Programming Environments Manual PowerPC RISC Microprocessor Family fmulsx fmulsx Floating Multiply Single (x’EC00 0032’) fmuls fmuls. frD,frA,frC frD,frA,frC (Rc = 0) (Rc = 1) Reserved 59 0 D 5 6 A 10 11 0000 0 15 16 C 20 21 25 Rc 25 26 30 31 The floating-point operand in register frA is multiplied by the floating-point operand in register frC. If the most-significant bit of the resultant significand is not a one, the result is normalized. The result is rounded to single-precision under control of the floating-point rounding control field RN of the FPSCR and placed into frD. Floating-point multiplication is based on exponent addition and multiplication of the significands. FPSCR[FPRF] is set to the class and sign of the result, except for invalid operation exceptions when FPSCR[VE] = 1. Other registers altered: • Condition Register (CR1 field): Affected: FX, FEX, VX, OX(if Rc = 1) • Floating-Point Status and Control Register: Affected: FPRF, FR, FI, FX, OX, UX, XX, VXSNAN, VXIMZ PowerPC Architecture Level UISA pem8.fm.2.0 June 10, 2003 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form A Instruction Set Page 449 of 785 Programming Environments Manual PowerPC RISC Microprocessor Family fnabsx fnabsx Floating Negative Absolute Value (x’FC00 0110’) fnabs fnabs. frD,frB frD,frB (Rc = 0) (Rc = 1) Reserved 63 0 D 5 6 0 0000 10 11 B 15 16 20 21 136 Rc 25 26 30 31 The contents of register frB with bit 0 set are placed into frD. Note that the fnabs instruction treats NaNs just like any other kind of value. That is, the sign bit of a NaN may be altered by fnabs. This instruction does not alter the FPSCR. Other registers altered: • Condition Register (CR1 field): Affected: FX, FEX, VX, OX(if Rc = 1) PowerPC Architecture Level UISA Instruction Set Page 450 of 785 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form X pem8.fm.2.0 June 10, 2003 Programming Environments Manual PowerPC RISC Microprocessor Family fnegx fnegx Floating Negate (x’FC00 0050’) fneg fneg. frD,frB frD,frB (Rc = 0) (Rc = 1) Reserved 63 0 D 5 6 0 0000 10 11 B 40 15 16 20 21 Rc 30 31 The contents of register frB with bit 0 inverted are placed into frD. Note that the fneg instruction treats NaNs just like any other kind of value. That is, the sign bit of a NaN may be altered by fneg. This instruction does not alter the FPSCR. Other registers altered: • Condition Register (CR1 field): Affected: FX, FEX, VX, OX(if Rc = 1) PowerPC Architecture Level UISA pem8.fm.2.0 June 10, 2003 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form X Instruction Set Page 451 of 785 Programming Environments Manual PowerPC RISC Microprocessor Family fnmaddx fnmaddx Floating Negative Multiply-Add (Double-Precision) (x’FC00 003E’) fnmadd fnmadd. frD,frA,frC,frB frD,frA,frC,frB (Rc = 0) (Rc = 1) [POWER mnemonics: fnma, fnma.] 63 0 D 5 6 A 10 11 B 15 16 C 20 21 31 Rc 25 26 30 31 The following operation is performed: frD ← – ([frA ∗ frC] + frB) The floating-point operand in register frA is multiplied by the floating-point operand in register frC. The floating-point operand in register frB is added to this intermediate result. If the most-significant bit of the resultant significand is not a one, the result is normalized. The result is rounded to double-precision under control of the floating-point rounding control field RN of the FPSCR, then negated and placed into frD. This instruction produces the same result as would be obtained by using the Floating Multiply-Add (fmaddx) instruction and then negating the result, with the following exceptions: • QNaNs propagate with no effect on their sign bit. • QNaNs that are generated as the result of a disabled invalid operation exception have a sign bit of zero. • SNaNs that are converted to QNaNs as the result of a disabled invalid operation exception retain the sign bit of the SNaN. FPSCR[FPRF] is set to the class and sign of the result, except for invalid operation exceptions when FPSCR[VE] = 1. Other registers altered: • Condition Register (CR1 field): Affected: FX, FEX, VX, OX(if Rc = 1) • Floating-Point Status and Control Register: Affected: FPRF, FR, FI, FX, OX, UX, XX, VXSNAN, VXISI, VXIMZ PowerPC Architecture Level UISA Instruction Set Page 452 of 785 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form A pem8.fm.2.0 June 10, 2003 Programming Environments Manual PowerPC RISC Microprocessor Family fnmaddsx fnmaddsx Floating Negative Multiply-Add Single (x’EC00 003E’) fnmadds fnmadds. frD,frA,frC,frB frD,frA,frC,frB 59 0 D 5 6 (Rc = 0) (Rc = 1) A 10 11 B 15 16 C 20 21 31 Rc 25 26 30 31 The following operation is performed: frD ← – ([frA ∗ frC] + frB) The floating-point operand in register frA is multiplied by the floating-point operand in register frC. The floating-point operand in register frB is added to this intermediate result. If the most-significant bit of the resultant significand is not a one, the result is normalized. The result is rounded to single-precision under control of the floating-point rounding control field RN of the FPSCR, then negated and placed into frD. This instruction produces the same result as would be obtained by using the Floating Multiply-Add Single (fmaddsx) instruction and then negating the result, with the following exceptions: • QNaNs propagate with no effect on their sign bit. • QNaNs that are generated as the result of a disabled invalid operation exception have a sign bit of zero. • SNaNs that are converted to QNaNs as the result of a disabled invalid operation exception retain the sign bit of the SNaN. FPSCR[FPRF] is set to the class and sign of the result, except for invalid operation exceptions when FPSCR[VE] = 1. Other registers altered: • Condition Register (CR1 field): Affected: FX, FEX, VX, OX(if Rc = 1) • Floating-Point Status and Control Register: Affected: FPRF, FR, FI, FX, OX, UX, XX, VXSNAN, VXISI, VXIMZ PowerPC Architecture Level UISA pem8.fm.2.0 June 10, 2003 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form A Instruction Set Page 453 of 785 Programming Environments Manual PowerPC RISC Microprocessor Family fnmsubx fnmsubx Floating Negative Multiply-Subtract (Double-Precision) (x’FC00 003C’) fnmsub fnmsub. frD,frA,frC,frB frD,frA,frC,frB (Rc = 0) (Rc = 1) [POWER mnemonics: fnms, fnms.] ] 63 0 D 5 6 A 10 11 B 15 16 C 20 21 30 Rc 25 26 30 31 The following operation is performed: frD ← – ([frA ∗ frC] – frB) The floating-point operand in register frA is multiplied by the floating-point operand in register frC. The floating-point operand in register frB is subtracted from this intermediate result. If the most-significant bit of the resultant significand is not one, the result is normalized. The result is rounded to double-precision under control of the floating-point rounding control field RN of the FPSCR, then negated and placed into frD. This instruction produces the same result obtained by negating the result of a Floating Multiply-Subtract (fmsubx) instruction with the following exceptions: • QNaNs propagate with no effect on their sign bit. • QNaNs that are generated as the result of a disabled invalid operation exception have a sign bit of zero. • SNaNs that are converted to QNaNs as the result of a disabled invalid operation exception retain the sign bit of the SNaN. FPSCR[FPRF] is set to the class and sign of the result, except for invalid operation exceptions when FPSCR[VE] = 1. Other registers altered: • Condition Register (CR1 field) Affected: FX, FEX, VX, OX(if Rc = 1) • Floating-Point Status and Control Register: Affected: FPRF, FR, FI, FX, OX, UX, XX, VXSNAN, VXISI, VXIMZ PowerPC Architecture Level UISA Instruction Set Page 454 of 785 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form A pem8.fm.2.0 June 10, 2003 Programming Environments Manual PowerPC RISC Microprocessor Family fnmsubsx fnmsubsx Floating Negative Multiply-Subtract Single (x’EC00 003C’) fnmsubs fnmsubs. frD,frA,frC,frB frD,frA,frC,frB (Rc = 0) (Rc = 1) ) 59 0 D 5 6 A 10 11 B 15 16 C 20 21 30 Rc 25 26 30 31 The following operation is performed: frD ← – ([frA ∗ frC] – frB) The floating-point operand in register frA is multiplied by the floating-point operand in register frC. The floating-point operand in register frB is subtracted from this intermediate result. If the most-significant bit of the resultant significand is not one, the result is normalized. The result is rounded to single-precision under control of the floating-point rounding control field RN of the FPSCR, then negated and placed into frD. This instruction produces the same result obtained by negating the result of a Floating Multiply-Subtract Single (fmsubsx) instruction with the following exceptions: • QNaNs propagate with no effect on their sign bit. • QNaNs that are generated as the result of a disabled invalid operation exception have a sign bit of zero. • SNaNs that are converted to QNaNs as the result of a disabled invalid operation exception retain the sign bit of the SNaN. FPSCR[FPRF] is set to the class and sign of the result, except for invalid operation exceptions when FPSCR[VE] = 1. Other registers altered: • Condition Register (CR1 field) Affected: FX, FEX, VX, OX(if Rc = 1) • Floating-Point Status and Control Register: Affected: FPRF, FR, FI, FX, OX, UX, XX, VXSNAN, VXISI, VXIMZ PowerPC Architecture Level UISA pem8.fm.2.0 June 10, 2003 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form A Instruction Set Page 455 of 785 Programming Environments Manual PowerPC RISC Microprocessor Family fresx fresx Floating Reciprocal Estimate Single (x’EC00 0030’) fres fres. frD,frB frD,frB (Rc = 0) (Rc = 1) Reserved 59 D 0 5 6 0 0000 10 11 B 000 00 15 16 20 21 24 Rc 25 26 30 31 A single-precision estimate of the reciprocal of the floating-point operand in register frB is placed into register frD. The estimate placed into register frD is correct to a precision of one part in 256 of the reciprocal of frB. That is, estimate – 1--- x 1 ABS ---------------------------------- ≤ -------- 256 1--- x where x is the initial value in frB. Note that the value placed into register frD may vary between implementations, and between different executions on the same implementation. Operation with various special values of the operand is summarized below: Operand Result Exception –× –0 None –0 –×* ZX +0 +×* ZX +× +0 None SNaN QNaN** VXSNAN QNaN QNaN None Notes: * No result if FPSCR[ZE] = 1 ** No result if FPSCR[VE] = 1 FPSCR[FPRF] is set to the class and sign of the result, except for invalid operation exceptions when FPSCR[VE] = 1 and zero divide exceptions when FPSCR[ZE] = 1. Note that the PowerPC architecture makes no provision for a double-precision version of the fresx instruction. This is because graphics applications are expected to need only the single-precision version, and no other important performance-critical applications are expected to require a double-precision version of the fresx instruction. This instruction is optional in the PowerPC architecture. Instruction Set Page 456 of 785 pem8.fm.2.0 June 10, 2003 Programming Environments Manual PowerPC RISC Microprocessor Family Other registers altered: • Condition Register (CR1 field): Affected: FX, FEX, VX, OX(if Rc = 1) • Floating-Point Status and Control Register: Affected: FPRF, FR (undefined), FI (undefined), FX, OX, UX, ZX, VXSNAN PowerPC Architecture Level UISA pem8.fm.2.0 June 10, 2003 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form Ð A Instruction Set Page 457 of 785 Programming Environments Manual PowerPC RISC Microprocessor Family frspx frspx Floating Round to Single (x’FC00 0018’) frsp frsp. frD,frB frD,frB (Rc = 0) (Rc = 1) Reserved 63 0 D 5 6 0 0000 10 11 B 15 16 12 Rc 20 21 30 31 The floating-point operand in register frB is rounded to single-precision using the rounding mode specified by FPSCR[RN] and placed into frD. The rounding is described fully in Section D.4.1 , “Floating-Point Round to Single-Precision Model.” FPSCR[FPRF] is set to the class and sign of the result, except for invalid operation exceptions when FPSCR[VE] = 1. Other registers altered: • Condition Register (CR1 field): Affected: FX, FEX, VX, OX(if Rc = 1) • Floating-Point Status and Control Register: Affected: FPRF, FR, FI, FX, OX, UX, XX, VXSNAN PowerPC Architecture Level UISA Instruction Set Page 458 of 785 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form X pem8.fm.2.0 June 10, 2003 Programming Environments Manual PowerPC RISC Microprocessor Family frsqrtex frsqrtex Floating Reciprocal Square Root Estimate (x’FC00 0034’) frsqrte frsqrte. frD,frB frD,frB (Rc = 0) (Rc = 1) Reserved 63 0 D 5 6 0 0000 10 11 B 000 00 15 16 20 21 26 Rc 25 26 30 31 A double-precision estimate of the reciprocal of the square root of the floating-point operand in register frB is placed into register frD. The estimate placed into register frD is correct to a precision of one part in 32 of the reciprocal of the square root of frB. That is, 1- estimate – ----- x 1 ABS -------------------------------------- ≤ -----1- ----- 32 x where x is the initial value in frB. Note that the value placed into register frD may vary between implementations, and between different executions on the same implementation. Operation with various special values of the operand is summarized below: Operand Result Exception –× QNaN** VXSQRT <0 QNaN** VXSQRT –0 –×* ZX +0 +×* ZX +× +0 None SNaN QNaN** VXSNAN QNaN QNaN None Notes: * No result if FPSCR[ZE] = 1 ** No result if FPSCR[VE] = 1 FPSCR[FPRF] is set to the class and sign of the result, except for invalid operation exceptions when FPSCR[VE] = 1 and zero divide exceptions when FPSCR[ZE] = 1. Note that no single-precision version of the frsqrte instruction is provided; however, both frB and frD are representable in single-precision format. This instruction is optional in the PowerPC architecture. pem8.fm.2.0 June 10, 2003 Instruction Set Page 459 of 785 Programming Environments Manual PowerPC RISC Microprocessor Family Other registers altered: • Condition Register (CR1 field): Affected: FX, FEX, VX, OX(if Rc = 1) • Floating-Point Status and Control Register: Affected: FPRF, FR (undefined), FI (undefined), FX, ZX, VXSNAN, VXSQRT PowerPC Architecture Level UISA Instruction Set Page 460 of 785 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form Ð A pem8.fm.2.0 June 10, 2003 Programming Environments Manual PowerPC RISC Microprocessor Family fselx fselx Floating Select (x’FC00 002E’) fsel fsel. frD,frA,frC,frB frD,frA,frC,frB 63 0 D 5 6 (Rc = 0) (Rc = 1) A 10 11 B 15 16 C 20 21 23 25 26 Rc 30 31 if (frA) Š 0.0 then frD ← (frC) else frD ← (frB) The floating-point operand in register frA is compared to the value zero. If the operand is greater than or equal to zero, register frD is set to the contents of register frC. If the operand is less than zero or is a NaN, register frD is set to the contents of register frB. The comparison ignores the sign of zero (that is, regards +0 as equal to –0). Care must be taken in using fsel if IEEE compatibility is required, or if the values being tested can be NaNs or infinities. For examples of uses of this instruction, see Section D.3 , “Floating-Point Conversions,” and Section D.5 , “Floating-Point Selection.” This instruction is optional in the PowerPC architecture. Other registers altered: • Condition Register (CR1 field): Affected: FX, FEX, VX, OX(if Rc = 1) PowerPC Architecture Level UISA pem8.fm.2.0 June 10, 2003 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form Ð A Instruction Set Page 461 of 785 Programming Environments Manual PowerPC RISC Microprocessor Family fsqrtx fsqrtx Floating Square Root (Double-Precision) (x’FC00 002C’) fsqrt fsqrt. frD,frB frD,frB (Rc = 0) (Rc = 1) Reserved 63 D 0 5 6 0 0000 10 11 B 15 16 000 00 20 21 22 Rc 25 26 30 31 The square root of the floating-point operand in register frB is placed into register frD. If the most-significant bit of the resultant significand is not a one the result is normalized. The result is rounded to the target precision under control of the floating-point rounding control field RN of the FPSCR and placed into register frD. Operation with various special values of the operand is summarized below: Operand Result Exception –× QNaN* VXSQRT <0 QNaN* VXSQRT –0 –0 None +× +× None SNaN QNaN* VXSNAN QNaN QNaN None Notes: * No result if FPSCR[VE] = 1 FPSCR[FPRF] is set to the class and sign of the result, except for invalid operation exceptions when FPSCR[VE] = 1. This instruction is optional in the PowerPC architecture. Other registers altered: • Condition Register (CR1 field): Affected: FX, FEX, VX, OX(if Rc = 1) • Floating-Point Status and Control Register: Affected: FPRF, FR, FI, FX, XX, VXSNAN, VXSQRT PowerPC Architecture Level UISA Instruction Set Page 462 of 785 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form Ð A pem8.fm.2.0 June 10, 2003 Programming Environments Manual PowerPC RISC Microprocessor Family fsqrtsx fsqrtsx Floating Square Root Single (x’EC00 002C’) fsqrts fsqrts. frD,frB frD,frB (Rc = 0) (Rc = 1) Reserved 59 0 D 5 6 0 0000 10 11 B 15 16 000 00 20 21 22 Rc 25 26 30 31 The square root of the floating-point operand in register frB is placed into register frD. If the most-significant bit of the resultant significand is not a one the result is normalized. The result is rounded to the target precision under control of the floating-point rounding control field RN of the FPSCR and placed into register frD. Operation with various special values of the operand is summarized below. Operand Result Exception –× QNaN* VXSQRT <0 QNaN* VXSQRT –0 –0 None +× +× None SNaN QNaN* VXSNAN QNaN QNaN None Notes: * No result if FPSCR[VE] = 1 FPSCR[FPRF] is set to the class and sign of the result, except for invalid operation exceptions when FPSCR[VE] = 1. This instruction is optional in the PowerPC architecture. Other registers altered: • Condition Register (CR1 field): Affected: FX, FEX, VX, OX(if Rc = 1) • Floating-Point Status and Control Register: Affected: FPRF, FR, FI, FX, XX, VXSNAN, VXSQRT PowerPC Architecture Level UISA pem8.fm.2.0 June 10, 2003 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form Ð A Instruction Set Page 463 of 785 Programming Environments Manual PowerPC RISC Microprocessor Family fsubx fsubx Floating Subtract (Double-Precision) (x’FC00 0028’) fsub fsub. frD,frA,frB frD,frA,frB (Rc = 0) (Rc = 1) [POWER mnemonics: fs, fs.] Reserved 63 0 D 5 6 A 10 11 B 15 16 000 00 20 21 20 Rc 25 26 30 31 The floating-point operand in register frB is subtracted from the floating-point operand in register frA. If the most-significant bit of the resultant significand is not a one, the result is normalized. The result is rounded to double-precision under control of the floating-point rounding control field RN of the FPSCR and placed into frD. The execution of the fsub instruction is identical to that of fadd, except that the contents of frB participate in the operation with its sign bit (bit 0) inverted. FPSCR[FPRF] is set to the class and sign of the result, except for invalid operation exceptions when FPSCR[VE] = 1. Other registers altered: • Condition Register (CR1 field): Affected: FX, FEX, VX, OX(if Rc = 1) • Floating-Point Status and Control Register: Affected: FPRF, FR, FI, FX, OX, UX, XX, VXSNAN, VXISI PowerPC Architecture Level UISA Instruction Set Page 464 of 785 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form A pem8.fm.2.0 June 10, 2003 Programming Environments Manual PowerPC RISC Microprocessor Family fsubsx fsubsx Floating Subtract Single (x’EC00 0028’) fsubs fsubs. frD,frA,frB frD,frA,frB (Rc = 0) (Rc = 1) Reserved 59 0 D 5 6 A 10 11 B 15 16 000 00 20 21 20 Rc 25 26 30 31 The floating-point operand in register frB is subtracted from the floating-point operand in register frA. If the most-significant bit of the resultant significand is not a one, the result is normalized. The result is rounded to single-precision under control of the floating-point rounding control field RN of the FPSCR and placed into frD. The execution of the fsubs instruction is identical to that of fadds, except that the contents of frB participate in the operation with its sign bit (bit 0) inverted. FPSCR[FPRF] is set to the class and sign of the result, except for invalid operation exceptions when FPSCR[VE] = 1. Other registers altered: • Condition Register (CR1 field): Affected: FX, FEX, VX, OX(if Rc = 1) • Floating-Point Status and Control Register: Affected: FPRF, FR, FI, FX, OX, UX, XX, VXSNAN, VXISI PowerPC Architecture Level UISA pem8.fm.2.0 June 10, 2003 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form A Instruction Set Page 465 of 785 Programming Environments Manual PowerPC RISC Microprocessor Family icbi icbi Instruction Cache Block Invalidate (x’7C00 07AC’) icbi rA,rB Reserved 31 0 00 000 5 6 A 10 11 B 15 16 982 20 21 0 30 31 EA is the sum (rA|0) + (rB). If the block containing the byte addressed by EA is in coherency-required mode, and a block containing the byte addressed by EA is in the instruction cache of any processor, the block is made invalid in all such instruction caches, so that subsequent references cause the block to be refetched. If the block containing the byte addressed by EA is in coherency-not-required mode, and a block containing the byte addressed by EA is in the instruction cache of this processor, the block is made invalid in that instruction cache, so that subsequent references cause the block to be refetched. The function of this instruction is independent of the write-through, write-back, and caching-inhibited/allowed modes of the block containing the byte addressed by EA. This instruction is treated as a load from the addressed byte with respect to address translation and memory protection. It may also be treated as a load for referenced and changed bit recording except that referenced and changed bit recording may not occur. Implementations with a combined data and instruction cache treat the icbi instruction as a no-op, except that they may invalidate the target block in the instruction caches of other processors if the block is in coherency-required mode. The icbi instruction invalidates the block at EA (rA|0 + rB). If the processor is a multiprocessor implementation (for example, the 601, 604, or 620) and the block is marked coherency-required, the processor will send an address-only broadcast to other processors causing those processors to invalidate the block from their instruction caches. For faster processing, many implementations will not compare the entire EA (rA|0 + rB) with the tag in the instruction cache. Instead, they will use the bits in the EA to locate the set that the block is in, and invalidate all blocks in that set. Other registers altered: • None PowerPC Architecture Level VEA Instruction Set Page 466 of 785 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form X pem8.fm.2.0 June 10, 2003 Programming Environments Manual PowerPC RISC Microprocessor Family isync isync Instruction Synchronize (x’4C00 012C’) isync [POWER mnemonic: ics] Reserved 19 0 00 000 5 6 0 0000 10 11 0000 0 15 16 150 20 21 0 30 31 The isync instruction provides an ordering function for the effects of all instructions executed by a processor. Executing an isync instruction ensures that all instructions preceding the isync instruction have completed before the isync instruction completes, except that memory accesses caused by those instructions need not have been performed with respect to other processors and mechanisms. It also ensures that no subsequent instructions are initiated by the processor until after the isync instruction completes. Finally, it causes the processor to discard any prefetched instructions, with the effect that subsequent instructions will be fetched and executed in the context established by the instructions preceding the isync instruction. The isync instruction has no effect on the other processors or on their caches. This instruction is context synchronizing. Context synchronization is necessary after certain code sequences that perform complex operations within the processor. These code sequences are usually operating system tasks that involve memory management. For example, if an instruction A changes the memory translation rules in the memory management unit (MMU), the isync instruction should be executed so that the instructions following instruction A will be discarded from the pipeline and refetched according to the new translation rules. Note that all exceptions and the rfi and rfid instructions are also context synchronizing. Other registers altered: • None PowerPC Architecture Level VEA pem8.fm.2.0 June 10, 2003 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form XL Instruction Set Page 467 of 785 Programming Environments Manual PowerPC RISC Microprocessor Family lbz lbz Load Byte and Zero (x’8800 0000’) lbz rD,d(rA) 34 0 D 5 6 A 10 11 d 15 16 31 if rA = 0 then b ← 0 else b ← (rA) EA ← b + EXTS(d) rD ← (5624)0 || MEM(EA, 1) EA is the sum (rA|0) + d. The byte in memory addressed by EA is loaded into the low-order eight bits of rD. The remaining bits in rD are cleared. Other registers altered: • None PowerPC Architecture Level UISA Instruction Set Page 468 of 785 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form D pem8.fm.2.0 June 10, 2003 Programming Environments Manual PowerPC RISC Microprocessor Family lbzu lbzu Load Byte and Zero with Update (x’8C00 0000’) lbzu rD,d(rA) 35 0 D 5 6 A 10 11 d 15 16 31 EA ← (rA) + EXTS(d) rD ← (5624)0 || MEM(EA, 1) rA ← EA EA is the sum (rA) + d. The byte in memory addressed by EA is loaded into the low-order eight bits of rD. The remaining bits in rD are cleared. EA is placed into rA. If rA = 0, or rA = rD, the instruction form is invalid. Other registers altered: • None PowerPC Architecture Level UISA pem8.fm.2.0 June 10, 2003 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form D Instruction Set Page 469 of 785 Programming Environments Manual PowerPC RISC Microprocessor Family lbzux lbzux Load Byte and Zero with Update Indexed (x’7C00 00EE’) lbzux rD,rA,rB Reserved 31 0 D 5 6 A 10 11 B 15 16 119 20 21 0 30 31 EA ← (rA) + (rB) rD ← (5624)0 || MEM(EA, 1) rA ← EA EA is the sum (rA) + (rB). The byte in memory addressed by EA is loaded into the low-order eight bits of rD. The remaining bits in rD are cleared. EA is placed into rA. If rA = 0 or rA = rD, the instruction form is invalid. Other registers altered: • None PowerPC Architecture Level UISA Instruction Set Page 470 of 785 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form X pem8.fm.2.0 June 10, 2003 Programming Environments Manual PowerPC RISC Microprocessor Family lbzx lbzx Load Byte and Zero Indexed (x’7C00 00AE’) lbzx rD,rA,rB Reserved 31 0 D 5 6 B A 10 11 15 16 87 20 21 0 30 31 if rA = 0 then b ← 0 else b ← (rA) EA ← b + (rB) rD ← (5624)0 || MEM(EA, 1) EA is the sum (rA|0) + (rB). The byte in memory addressed by EA is loaded into the low-order eight bits of rD. The remaining bits in rD are cleared. Other registers altered: • None PowerPC Architecture Level UISA pem8.fm.2.0 June 10, 2003 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form X Instruction Set Page 471 of 785 Programming Environments Manual PowerPC RISC Microprocessor Family ld ld 64-Bit Implementations Only Load Double Word (x’E800 0000’) ld rD,ds(rA) 58 0 D 5 6 A 10 11 ds 00 15 16 29 30 31 if rA = 0 then b ← 0 else b ← (rA) EA ← b + EXTS(ds || 0b00) rD ← MEM(EA, 8) EA is the sum (rA|0) + (ds || 0b00). The double word in memory addressed by EA is loaded into rD. This instruction is defined only for 64-bit implementations. Using it on a 32-bit implementation will cause the system illegal instruction error handler to be invoked. Other registers altered: • None PowerPC Architecture Level UISA Instruction Set Page 472 of 785 Supervisor Level 32-Bit 64-Bit Ð 64-Bit Bridge Optional Form DS pem8.fm.2.0 June 10, 2003 Programming Environments Manual PowerPC RISC Microprocessor Family ldarx ldarx 64-Bit Implementations Only Load Double Word and Reserve Indexed (x’7C00 00A8’) ldarx rD,rA,rB Reserved 31 0 D 5 6 A 10 11 B 84 15 16 20 21 0 30 31 if rA = 0 then b ← 0 else b ← (rA) EA ← b + (rB) RESERVE ← 1 RESERVE_ADDR ← physical_addr(EA) rD ← MEM(EA, 8) EA is the sum (rA|0) + (rB). The double word in memory addressed by EA is loaded into rD. This instruction creates a reservation for use by a Store Double Word Conditional Indexed (stdcx.) instruction. An address computed from the EA is associated with the reservation, and replaces any address previously associated with the reservation. EA must be a multiple of eight. If it is not, either the system alignment exception handler is invoked or the results are boundedly undefined. For additional information about alignment and DSI exceptions, see Section 6.4.3 , “DSI Exception (0x00300).” This instruction is defined only for 64-bit implementations. Using it on a 32-bit implementation will cause the system illegal instruction error handler to be invoked. Other registers altered: • None PowerPC Architecture Level UISA pem8.fm.2.0 June 10, 2003 Supervisor Level 32-Bit 64-Bit Ð 64-Bit Bridge Optional Form X Instruction Set Page 473 of 785 Programming Environments Manual PowerPC RISC Microprocessor Family ldu ldu 64-Bit Implementations Only Load Double Word with Update (x’E800 0001’) ldu rD,ds(rA) 58 0 D 5 6 A 10 11 ds 01 15 16 29 30 31 EA ← (rA) + EXTS(ds || 0b00) rD ← MEM(EA, 8) rA ← EA EA is the sum (rA) + (ds || 0b00). The double word in memory addressed by EA is loaded into rD. EA is placed into rA. If rA = 0 or rA = rD, the instruction form is invalid. This instruction is defined only for 64-bit implementations. Using it on a 32-bit implementation will cause the system illegal instruction error handler to be invoked. Other registers altered: • None PowerPC Architecture Level UISA Instruction Set Page 474 of 785 Supervisor Level 32-Bit 64-Bit Ð 64-Bit Bridge Optional Form DS pem8.fm.2.0 June 10, 2003 Programming Environments Manual PowerPC RISC Microprocessor Family ldux lduxx 64-Bit Implementations Only Load Double Word with Update Indexed (x’7C00 006A’) ldux rD,rA,rB Reserved 31 0 D 5 6 A 10 11 B 53 15 16 20 21 0 30 31 EA ← (rA) + (rB) rD ← MEM(EA, 8) rA ← EA EA is the sum (rA) + (rB). The double word in memory addressed by EA is loaded into rD. EA is placed into rA. If rA = 0 or rA = rD, the instruction form is invalid. This instruction is defined only for 64-bit implementations. Using it on a 32-bit implementation will cause the system illegal instruction to be invoked. Other registers altered: • None PowerPC Architecture Level UISA pem8.fm.2.0 June 10, 2003 Supervisor Level 32-Bit 64-Bit Ð 64-Bit Bridge Optional Form X Instruction Set Page 475 of 785 Programming Environments Manual PowerPC RISC Microprocessor Family ldx ldx 64-Bit Implementations Only Load Double Word Indexed (x’7C00 002A’) ldx rD,rA,rB Reserved 31 0 D 5 6 A 10 11 B 21 15 16 20 21 0 30 31 if rA = 0 then b ← 0 else b ← (rA) EA ← b + (rB) rD ← MEM(EA, 8) EA is the sum (rA|0) + (rB). The double word in memory addressed by EA is loaded into rD. This instruction is defined only for 64-bit implementations. Using it on a 32-bit implementation will cause the system illegal instruction error handler to be invoked. Other registers altered: • None PowerPC Architecture Level UISA Instruction Set Page 476 of 785 Supervisor Level 32-Bit 64-Bit Ð 64-Bit Bridge Optional Form X pem8.fm.2.0 June 10, 2003 Programming Environments Manual PowerPC RISC Microprocessor Family lfd lfd Load Floating-Point Double (x’C800 0000’) lfd frD,d(rA) 50 0 D 5 6 A 10 11 d 15 16 31 if rA = 0 then b ← 0 else b ← (rA) EA ← b + EXTS(d) frD ← MEM(EA, 8) EA is the sum (rA|0) + d. The double word in memory addressed by EA is placed into frD. Other registers altered: • None PowerPC Architecture Level UISA pem8.fm.2.0 June 10, 2003 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form D Instruction Set Page 477 of 785 Programming Environments Manual PowerPC RISC Microprocessor Family lfdu lfdu Load Floating-Point Double with Update (x’CC00 0000’) lfdu frD,d(rA) 51 0 D 5 6 A 10 11 d 15 16 31 EA ← (rA) + EXTS(d) frD ← MEM(EA, 8) rA ← EA EA is the sum (rA) + d. The double word in memory addressed by EA is placed into frD. EA is placed into rA. If rA = 0, the instruction form is invalid. Other registers altered: • None PowerPC Architecture Level UISA Instruction Set Page 478 of 785 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form D pem8.fm.2.0 June 10, 2003 Programming Environments Manual PowerPC RISC Microprocessor Family lfdux lfdux Load Floating-Point Double with Update Indexed (x’7C00 04EE’) lfdux frD,rA,rB Reserved 31 0 D 5 6 A 10 11 B 631 15 16 20 21 0 30 31 EA ← (rA) + (rB) frD ← MEM(EA, 8) rA ← EA EA is the sum (rA) + (rB). The double word in memory addressed by EA is placed into frD. EA is placed into rA. If rA = 0, the instruction form is invalid. Other registers altered: • None PowerPC Architecture Level UISA pem8.fm.2.0 June 10, 2003 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form X Instruction Set Page 479 of 785 Programming Environments Manual PowerPC RISC Microprocessor Family lfdx lfdx Load Floating-Point Double Indexed (x’7C00 04AE’) lfdx frD,rA,rB Reserved 31 0 D 5 6 A 10 11 B 599 15 16 20 21 0 30 31 if rA = 0 then b ← 0 else b ← (rA) EA ← b + (rB) frD ← MEM(EA, 8) EA is the sum (rA|0) + (rB). The double word in memory addressed by EA is placed into frD. Other registers altered: • None PowerPC Architecture Level UISA Instruction Set Page 480 of 785 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form X pem8.fm.2.0 June 10, 2003 Programming Environments Manual PowerPC RISC Microprocessor Family lfs lfs Load Floating-Point Single (x’C000 0000’) lfs frD,d(rA) 48 0 D 5 6 A 10 11 d 15 16 31 if rA = 0 then b ← 0 else b ← (rA) EA ← b + EXTS(d) frD ← DOUBLE(MEM(EA, 4)) EA is the sum (rA|0) + d. The word in memory addressed by EA is interpreted as a floating-point single-precision operand. This word is converted to floating-point double-precision (see Section D.6 , “Floating-Point Load Instructions”) and placed into frD. Other registers altered: • None PowerPC Architecture Level UISA pem8.fm.2.0 June 10, 2003 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form D Instruction Set Page 481 of 785 Programming Environments Manual PowerPC RISC Microprocessor Family lfsu lfsu Load Floating-Point Single with Update (x’C400 0000’) lfsu frD,d(rA) 49 0 D 5 6 A 10 11 d 15 16 31 EA ← (rA) + EXTS(d) frD ← DOUBLE(MEM(EA, 4)) rA ← EA EA is the sum (rA) + d. The word in memory addressed by EA is interpreted as a floating-point single-precision operand. This word is converted to floating-point double-precision (see Section D.6 , “Floating-Point Load Instructions”) and placed into frD. EA is placed into rA. If rA = 0, the instruction form is invalid. Other registers altered: • None PowerPC Architecture Level UISA Instruction Set Page 482 of 785 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form D pem8.fm.2.0 June 10, 2003 Programming Environments Manual PowerPC RISC Microprocessor Family lfsux lfsux Load Floating-Point Single with Update Indexed (x’7C00 046E’) lfsux frD,rA,rB Reserved 31 0 D 5 6 B A 10 11 15 16 567 20 21 0 30 31 EA ← (rA) + (rB) frD ← DOUBLE(MEM(EA, 4)) rA ← EA EA is the sum (rA) + (rB). The word in memory addressed by EA is interpreted as a floating-point single-precision operand. This word is converted to floating-point double-precision (see Section D.6 , “Floating-Point Load Instructions”) and placed into frD. EA is placed into rA. If rA = 0, the instruction form is invalid. Other registers altered: • None PowerPC Architecture Level UISA pem8.fm.2.0 June 10, 2003 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form X Instruction Set Page 483 of 785 Programming Environments Manual PowerPC RISC Microprocessor Family lfsx lfsx Load Floating-Point Single Indexed (x’7C00 042E’) lfsx frD,rA,rB Reserved 31 0 D 5 6 A 10 11 B 15 16 535 20 21 0 30 31 if rA = 0 then b ← 0 else b ← (rA) EA ← b + (rB) frD ← DOUBLE(MEM(EA, 4)) EA is the sum (rA|0) + (rB). The word in memory addressed by EA is interpreted as a floating-point single-precision operand. This word is converted to floating-point double-precision (see Section D.6 , “Floating-Point Load Instructions”) and placed into frD. Other registers altered: • None PowerPC Architecture Level UISA Instruction Set Page 484 of 785 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form X pem8.fm.2.0 June 10, 2003 Programming Environments Manual PowerPC RISC Microprocessor Family lha lha Load Half Word Algebraic (x’A800 0000’) lha rD,d(rA) 42 0 D 5 6 A 10 11 d 15 16 31 if rA = 0 then b ← 0 else b ← (rA) EA ← b + EXTS(d) rD ← EXTS(MEM(EA, 2)) EA is the sum (rA|0) + d. The half word in memory addressed by EA is loaded into the low-order 16 bits of rD. The remaining bits in rD are filled with a copy of the most-significant bit of the loaded half word. Other registers altered: • None PowerPC Architecture Level UISA pem8.fm.2.0 June 10, 2003 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form D Instruction Set Page 485 of 785 Programming Environments Manual PowerPC RISC Microprocessor Family lhau lhau Load Half Word Algebraic with Update (x’AC00 0000’) lhau rD,d(rA) 43 0 D 5 6 A 10 11 d 15 16 31 EA ← (rA) + EXTS(d) rD ← EXTS(MEM(EA, 2)) rA ← EA EA is the sum (rA) + d. The half word in memory addressed by EA is loaded into the low-order 16 bits of rD. The remaining bits in rD are filled with a copy of the most-significant bit of the loaded half word. EA is placed into rA. If rA = 0 or rA = rD, the instruction form is invalid. Other registers altered: • None PowerPC Architecture Level UISA Instruction Set Page 486 of 785 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form D pem8.fm.2.0 June 10, 2003 Programming Environments Manual PowerPC RISC Microprocessor Family lhaux lhaux Load Half Word Algebraic with Update Indexed (x’7C00 02EE’) lhaux rD,rA,rB Reserved 31 0 D 5 6 A 10 11 B 15 16 375 20 21 0 30 31 EA ← (rA) + (rB) rD ← EXTS(MEM(EA, 2)) rA ← EA EA is the sum (rA) + (rB). The half word in memory addressed by EA is loaded into the low-order 16 bits of rD. The remaining bits in rD are filled with a copy of the most-significant bit of the loaded half word. EA is placed into rA. If rA = 0 or rA = rD, the instruction form is invalid. Other registers altered: • None PowerPC Architecture Level UISA pem8.fm.2.0 June 10, 2003 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form X Instruction Set Page 487 of 785 Programming Environments Manual PowerPC RISC Microprocessor Family lhax lhax Load Half Word Algebraic Indexed (x’7C00 02AE’) lhax rD,rA,rB Reserved 31 0 D 5 6 A 10 11 B 15 16 343 20 21 0 30 31 if rA = 0 then b ← 0 else b ← (rA) EA ← b + (rB) rD ← EXTS(MEM(EA, 2)) EA is the sum (rA|0) + (rB). The half word in memory addressed by EA is loaded into the low-order 16 bits of rD. The remaining bits in rD are filled with a copy of the most-significant bit of the loaded half word. Other registers altered: • None PowerPC Architecture Level UISA Instruction Set Page 488 of 785 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form X pem8.fm.2.0 June 10, 2003 Programming Environments Manual PowerPC RISC Microprocessor Family lhbrx lhbrx Load Half Word Byte-Reverse Indexed (x’7C00 062C’) lhbrx rD,rA,rB Reserved 31 0 D 5 6 A 10 11 B 15 16 790 20 21 0 30 31 if rA = 0 then b ← 0 else b ← (rA) EA ← b + (rB) rD ← (4816)0 || MEM(EA + 1, 1) || MEM(EA, 1) EA is the sum (rA|0) + (rB). Bits 0–7 of the half word in memory addressed by EA are loaded into the loworder eight bits of rD. Bits 8–15 of the half word in memory addressed by EA are loaded into the subsequent low-order eight bits of rD. The remaining bits in rD are cleared. The PowerPC architecture cautions programmers that some implementations of the architecture may run the lhbrx instructions with greater latency than other types of load instructions. Other registers altered: • None PowerPC Architecture Level UISA pem8.fm.2.0 June 10, 2003 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form X Instruction Set Page 489 of 785 Programming Environments Manual PowerPC RISC Microprocessor Family lhz lhz Load Half Word and Zero (x’A000 0000’) lhz rD,d(rA) 40 0 D 5 6 A 10 11 d 15 16 31 if rA = 0 then b ← 0 else b ← (rA) EA ← b + EXTS(d) rD ← (4816)0 || MEM(EA, 2) EA is the sum (rA|0) + d. The half word in memory addressed by EA is loaded into the low-order 16 bits of rD. The remaining bits in rD are cleared. Other registers altered: • None PowerPC Architecture Level UISA Instruction Set Page 490 of 785 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form D pem8.fm.2.0 June 10, 2003 Programming Environments Manual PowerPC RISC Microprocessor Family lhzu lhzu Load Half Word and Zero with Update (x’A400 0000’) lhzu rD,d(rA) 41 0 D 5 6 A 10 11 d 15 16 31 EA ← rA + EXTS(d) rD ← (4816)0 || MEM(EA, 2) rA ← EA EA is the sum (rA) + d. The half word in memory addressed by EA is loaded into the low-order 16 bits of rD. The remaining bits in rD are cleared. EA is placed into rA. If rA = 0 or rA = rD, the instruction form is invalid. Other registers altered: • None PowerPC Architecture Level UISA pem8.fm.2.0 June 10, 2003 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form D Instruction Set Page 491 of 785 Programming Environments Manual PowerPC RISC Microprocessor Family lhzux lhzux Load Half Word and Zero with Update Indexed (x’7C00 026E’) lhzux rD,rA,rB Reserved 31 0 D 5 6 A 10 11 B 15 16 311 20 21 0 30 31 EA ← (rA) + (rB) rD ← (4816)0 || MEM(EA, 2) rA ← EA EA is the sum (rA) + (rB). The half word in memory addressed by EA is loaded into the low-order 16 bits of rD. The remaining bits in rD are cleared. EA is placed into rA. If rA = 0 or rA = rD, the instruction form is invalid. Other registers altered: • None PowerPC Architecture Level UISA Instruction Set Page 492 of 785 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form X pem8.fm.2.0 June 10, 2003 Programming Environments Manual PowerPC RISC Microprocessor Family lhzx lhzx Load Half Word and Zero Indexed (x’7C00 022E’) lhzx rD,rA,rB Reserved 31 0 D 5 6 A 10 11 B 15 16 279 20 21 0 30 31 if rA = 0 then b ← 0 else b ← (rA) EA ← b + (rB) rD ← (4816)0 || MEM(EA, 2) EA is the sum (rA|0) + (rB). The half word in memory addressed by EA is loaded into the low-order 16 bits of rD. The remaining bits in rD are cleared. Other registers altered: • None PowerPC Architecture Level UISA pem8.fm.2.0 June 10, 2003 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form X Instruction Set Page 493 of 785 Programming Environments Manual PowerPC RISC Microprocessor Family lmw lmw Load Multiple Word (x’B800 0000’) lmw rD,d(rA) [POWER mnemonic: lm] 46 0 D 5 6 A 10 11 d 15 16 31 if rA = 0 then b ← 0 else b ← (rA) EA ← b + EXTS(d) r ← rD do while r ð 31 GPR(r) ← (32)0 || MEM(EA, 4) r←r + 1 EA ← EA + 4 EA is the sum (rA|0) + d. n = (32 – rD). n consecutive words starting at EA are loaded into the low-order 32 bits of GPRs rD through r31. The highorder 32 bits of these GPRs are cleared. EA must be a multiple of four. If it is not, either the system alignment exception handler is invoked or the results are boundedly undefined. For additional information about alignment and DSI exceptions, see Section 6.4.3 , “DSI Exception (0x00300).” If rA is in the range of registers specified to be loaded, including the case in which rA = 0, the instruction form is invalid. Note that, in some implementations, this instruction is likely to have a greater latency and take longer to execute, perhaps much longer, than a sequence of individual load or store instructions that produce the same results. Other registers altered: • None PowerPC Architecture Level UISA Instruction Set Page 494 of 785 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form D pem8.fm.2.0 June 10, 2003 Programming Environments Manual PowerPC RISC Microprocessor Family lswi lswi Load String Word Immediate (x’7C00 04AA’) lswi rD,rA,NB [POWER mnemonic: lsi] if rA = 0 then EA ← 0 else EA ← (rA) if NB = 0 then n ← 32 elsen ← NB r ← rD – 1 i ← 320 do while n > 0 if i = 32 then r ← r + 1 (mod 32) GPR(r) ← 0 GPR(r)[i–i + 7] ← MEM(EA, 1) i← i + 8 if i = 6432 then i ← 320 EA ← EA + 1 n ← n – 1 EA is (rA|0). Let n = NB if NB ¦ 0, n = 32 if NB = 0; n is the number of bytes to load. Let nr = CEIL(n ÷ 4); nr is the number of registers to be loaded with data. n consecutive bytes starting at EA are loaded into GPRs rD through rD + nr – 1. Data is loaded into the loworder four bytes of each GPR; the high-order four bytes are cleared. Bytes are loaded left to right in each register. The sequence of registers wraps around to r0 if required. If the low-order 4 bytes of register rD + nr – 1 are only partially filled, the unfilled low-order byte(s) of that register are cleared. If rA is in the range of registers specified to be loaded, including the case in which rA = 0, the instruction form is invalid. Under certain conditions (for example, segment boundary crossing) the data alignment exception handler may be invoked. For additional information about data alignment exceptions, see Section 6.4.3 , “DSI Exception (0x00300).” Note that, in some implementations, this instruction is likely to have greater latency and take longer to execute, perhaps much longer, than a sequence of individual load or store instructions that produce the same results. pem8.fm.2.0 June 10, 2003 Instruction Set Page 495 of 785 Programming Environments Manual PowerPC RISC Microprocessor Family Other registers altered: • None PowerPC Architecture Level UISA Instruction Set Page 496 of 785 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form X pem8.fm.2.0 June 10, 2003 Programming Environments Manual PowerPC RISC Microprocessor Family lswx lswx Load String Word Indexed (x’7C00 042A’) lswx rD,rA,rB [POWER mnemonic: lsx] if rA = 0 then b ← 0 else b ← (rA) EA ← b + (rB) n ← XER[25–31] r ← rD – 1 i ← 32 rD ← undefined do while n > 0 if i = 32 then r ← r + 1 (mod 32) GPR(r) ← 0 GPR(r)[i–i + 7] ← MEM(EA, 1) i← i + 8 if i = 6432 then i ← 320 EA ← EA + 1 n ← n – 1 EA is the sum (rA|0) + (rB). Let n = XER[25–31]; n is the number of bytes to load. Let nr = CEIL(n ÷ 4); nr is the number of registers to receive data. If n > 0, n consecutive bytes starting at EA are loaded into GPRs rD through rD + nr – 1. Data is loaded into the low-order four bytes of each GPR; the highorder four bytes are cleared. Bytes are loaded left to right in each register. The sequence of registers wraps around through r0 if required. If the low-order four bytes of rD + nr – 1 are only partially filled, the unfilled low-order byte(s) of that register are cleared. If n = 0, the contents of rD are undefined. If rA or rB is in the range of registers specified to be loaded, including the case in which rA = 0, either the system illegal instruction error handler is invoked or the results are boundedly undefined. If rD = rA or rD = rB, the instruction form is invalid. If rD and rA both specify GPR0, the form is invalid. Under certain conditions (for example, segment boundary crossing) the data alignment exception handler may be invoked. For additional information about data alignment exceptions, see Section 6.4.3 , “DSI Exception (0x00300).” Note that, in some implementations, this instruction is likely to have a greater latency and take longer to execute, perhaps much longer, than a sequence of individual load or store instructions that produce the same results. pem8.fm.2.0 June 10, 2003 Instruction Set Page 497 of 785 Programming Environments Manual PowerPC RISC Microprocessor Family Other registers altered: • None PowerPC Architecture Level UISA Instruction Set Page 498 of 785 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form X pem8.fm.2.0 June 10, 2003 Programming Environments Manual PowerPC RISC Microprocessor Family lwa lwa 64-Bit Implementations Only Load Word Algebraic (x’E800 0002’) lwa rD,ds(rA) 58 0 D 5 6 A 10 11 ds 10 15 16 29 30 31 if rA = 0 then b ← 0 else b ← (rA) EA ← b + EXTS(ds || 0b00) rD ← EXTS(MEM(EA, 4)) EA is the sum (rA|0) + (ds || 0b00). The word in memory addressed by EA is loaded into the low-order 32 bits of rD. The contents of the high-order 32 bits of rD are filled with a copy of bit 0 of the loaded word. This instruction is defined only for 64-bit implementations. Using it on a 32-bit implementation will cause the system illegal instruction error handler to be invoked. Other registers altered: • None PowerPC Architecture Level UISA pem8.fm.2.0 June 10, 2003 Supervisor Level 32-Bit 64-Bit Ð 64-Bit Bridge Optional Form DS Instruction Set Page 499 of 785 Programming Environments Manual PowerPC RISC Microprocessor Family lwarx lwarx Load Word and Reserve Indexed (x’7C00 0028’) lwarx rD,rA,rB Reserved 31 0 D 5 6 A 10 11 B 15 16 20 20 21 0 30 31 if rA = 0 then b ← 0 else b ← (rA) EA ← b + (rB) RESERVE ← 1 RESERVE_ADDR ← physical_addr(EA) rD ← (32)0 || MEM(EA,4) EA is the sum (rA|0) + (rB). The word in memory addressed by EA is loaded into the low-order 32 bits of rD. The contents of the highorder 32 bits of rD are cleared. This instruction creates a reservation for use by a store word conditional indexed (stwcx.)instruction. The physical address computed from EA is associated with the reservation, and replaces any address previously associated with the reservation. EA must be a multiple of four. If it is not, either the system alignment exception handler is invoked or the results are boundedly undefined. For additional information about alignment and DSI exceptions, see Section 6.4.3 , “DSI Exception (0x00300).” When the RESERVE bit is set, the processor enables hardware snooping for the block of memory addressed by the RESERVE address. If the processor detects that another processor writes to the block of memory it has reserved, it clears the RESERVE bit. The stwcx. instruction will only do a store if the RESERVE bit is set. The stwcx. instruction sets the CR0[EQ] bit if the store was successful and clears it if it failed. The lwarx and stwcx. combination can be used for atomic read-modify-write sequences. Note that the atomic sequence is not guaranteed, but its failure can be detected if CR0[EQ] = 0 after the stwcx. instruction. Other registers altered: • None PowerPC Architecture Level UISA Instruction Set Page 500 of 785 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form X pem8.fm.2.0 June 10, 2003 Programming Environments Manual PowerPC RISC Microprocessor Family lwaux lwaux 64-Bit Implementations Only Load Word Algebraic with Update Indexed (x’7C00 02EA’) lwaux rD,rA,rB Reserved 31 0 D 5 6 B A 10 11 373 15 16 20 21 0 30 31 EA ← (rA) + (rB) rD ← EXTS(MEM(EA, 4)) rA ← EA EA is the sum (rA) + (rB). The word in memory addressed by EA is loaded into the low-order 32 bits of rD. The high-order 32 bits of rD are filled with a copy of bit 0 of the loaded word. EA is placed into rA. If rA = 0 or rA = rD, the instruction form is invalid. This instruction is defined only for 64-bit implementations. Using it on a 32-bit implementation will cause the system illegal instruction error handler to be invoked. Other registers altered: • None PowerPC Architecture Level UISA pem8.fm.2.0 June 10, 2003 Supervisor Level 32-Bit 64-Bit Ð 64-Bit Bridge Optional Form X Instruction Set Page 501 of 785 Programming Environments Manual PowerPC RISC Microprocessor Family lwax lwax 64-Bit Implementations Only Load Word Algebraic Indexed (x’7C00 02AA’) lwax rD,rA,rB Reserved 31 0 D 5 6 A 10 11 B 341 15 16 20 21 0 30 31 if rA = 0 then b ← 0 else b ← (rA) EA ← b + (rB) rD ← EXTS(MEM(EA, 4)) EA is the sum (rA|0) + (rB). The word in memory addressed by EA is loaded into the low-order 32 bits of rD. The high-order 32 bits of rD are filled with a copy of bit 0 of the loaded word. This instruction is defined only for 64-bit implementations. Using it on a 32-bit implementation will cause the system illegal instruction error handler to be invoked. Other registers altered: • None PowerPC Architecture Level UISA Instruction Set Page 502 of 785 Supervisor Level 32-Bit 64-Bit Ð 64-Bit Bridge Optional Form X pem8.fm.2.0 June 10, 2003 Programming Environments Manual PowerPC RISC Microprocessor Family lwbrx lwbrx Load Word Byte-Reverse Indexed (x’7C00 042C’) lwbrx rD,rA,rB [POWER mnemonic: lbrx] Reserved 31 0 D 5 6 A 10 11 B 15 16 534 20 21 0 30 31 if rA = 0 then b ← 0 else b ← (rA) EA ← b + (rB) rD ← (32)0 || MEM(EA + 3, 1) || MEM(EA + 2, 1) || MEM(EA + 1, 1) || MEM(EA, 1) EA is the sum (rA|0) + rB. Bits 0–7 of the word in memory addressed by EA are loaded into the low-order 8 bits of rD. Bits 8–15 of the word in memory addressed by EA are loaded into the subsequent low-order 8 bits of rD. Bits 16–23 of the word in memory addressed by EA are loaded into the subsequent low-order eight bits of rD. Bits 24–31 of the word in memory addressed by EA are loaded into the subsequent low-order 8 bits of rD. The high-order 32 bits of rD are cleared. The PowerPC architecture cautions programmers that some implementations of the architecture may run the lwbrx instructions with greater latency than other types of load instructions. Other registers altered: • None PowerPC Architecture Level UISA pem8.fm.2.0 June 10, 2003 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form X Instruction Set Page 503 of 785 Programming Environments Manual PowerPC RISC Microprocessor Family lwz lwz Load Word and Zero (x’8000 0000’) lwz rD,d(rA) [POWER mnemonic: l] 32 0 D 5 6 A 10 11 d 15 16 31 if rA = 0 then b ← 0 else b ← (rA) EA ← b + EXTS(d) rD ← (32)0 || MEM(EA, 4) EA is the sum (rA|0) + d. The word in memory addressed by EA is loaded into the low-order 32 bits of rD. The high-order 32 bits of rD are cleared. Other registers altered: • None PowerPC Architecture Level UISA Instruction Set Page 504 of 785 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form D pem8.fm.2.0 June 10, 2003 Programming Environments Manual PowerPC RISC Microprocessor Family lwzu lwzu Load Word and Zero with Update (x’8400 0000’) lwzu rD,d(rA) [POWER mnemonic: lu] 33 0 D 5 6 A 10 11 d 15 16 31 EA ← rA + EXTS(d) rD ← (32)0 || MEM(EA, 4) rA ← EA EA is the sum (rA) + d. The word in memory addressed by EA is loaded into the low-order 32 bits of rD. The high-order 32 bits of rD are cleared. EA is placed into rA. If rA = 0, or rA = rD, the instruction form is invalid. Other registers altered: • None PowerPC Architecture Level UISA pem8.fm.2.0 June 10, 2003 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form D Instruction Set Page 505 of 785 Programming Environments Manual PowerPC RISC Microprocessor Family lwzux lwzux Load Word and Zero with Update Indexed (x’7C00 006E’) lwzux rD,rA,rB [POWER mnemonic: lux] Reserved 31 0 D 5 6 A 10 11 B 15 16 55 20 21 0 30 31 EA ← (rA) + (rB) rD ← (32)0 || MEM(EA, 4) rA ← EA EA is the sum (rA) + (rB). The word in memory addressed by EA is loaded into the low-order 32 bits of rD. The high-order 32 bits of rD are cleared. EA is placed into rA. If rA = 0, or rA = rD, the instruction form is invalid. Other registers altered: • None PowerPC Architecture Level UISA Instruction Set Page 506 of 785 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form X pem8.fm.2.0 June 10, 2003 Programming Environments Manual PowerPC RISC Microprocessor Family lwzx lwzx Load Word and Zero Indexed (x’7C00 002E’) lwzx rD,rA,rB [POWER mnemonic: lx] Reserved 31 0 D 5 6 A 10 11 B 15 16 23 20 21 0 30 31 if rA = 0 then b ← 0 else b ← (rA) EA ← b + rB rD ← (32)0 || MEM(EA, 4) EA is the sum (rA|0) + (rB). The word in memory addressed by EA is loaded into the low-order 32 bits of rD. The high-order 32 bits of rD are cleared. Other registers altered: • None PowerPC Architecture Level UISA pem8.fm.2.0 June 10, 2003 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form X Instruction Set Page 507 of 785 Programming Environments Manual PowerPC RISC Microprocessor Family mcrf mcrf Move Condition Register Field (x’4C00 0000’) mcrf crfD,crfS CR[4 ∗ crfD–4 ∗ crfD + 3] ← CR[4 ∗ crfS–4 ∗ crfS + 3] The contents of condition register field crfS are copied into condition register field crfD. All other condition register fields remain unchanged. Other registers altered: • Condition Register (CR field specified by operand crfD): Affected: LT, GT, EQ, SO PowerPC Architecture Level UISA Instruction Set Page 508 of 785 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form XL pem8.fm.2.0 June 10, 2003 Programming Environments Manual PowerPC RISC Microprocessor Family mcrfs mcrfs Move to Condition Register from FPSCR (x’FC00 0080’) mcrfs crfD,crfS Reserved 63 0 crfD 5 6 00 8 crfS 9 10 11 00 0000 0 13 14 15 16 64 20 21 0 30 31 The contents of FPSCR field crfS are copied to CR field crfD. All exception bits copied (except FEX and VX) are cleared in the FPSCR. Other registers altered: • Condition Register (CR field specified by operand crfD): Affected: FX, FEX, VX, OX • Floating-Point Status and Control Register: Affected: FX, OX (if crfS = 0) Affected: UX, ZX, XX, VXSNAN (if crfS = 1) Affected: VXISI, VXIDI, VXZDZ, VXIMZ (if crfS = 2) Affected: VXVC (if crfS = 3) Affected: VXSOFT, VXSQRT, VXCVI (if crfS = 5) PowerPC Architecture Level UISA pem8.fm.2.0 June 10, 2003 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form X Instruction Set Page 509 of 785 Programming Environments Manual PowerPC RISC Microprocessor Family mcrxr mcrxr Move to Condition Register from XER (x’7C00 0400’) mcrxr crfD Reserved 31 0 crfD 5 6 00 8 00000 9 10 11 0000 0 16 512 20 21 0 30 31 CR[* crfD-4 * crfD +3] The contents of XER[0-3] are copied into the condition register field designated by crfD. All other fields of the condition register remain unchanged. XER[0-3] is cleared. Other registers altered: • Condition Register (CR field specified by operand crfD): Affected: LT, GT, EQ, SO • XER[0-3] PowerPC Architecture Level UISA Instruction Set Page 510 of 785 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form X pem8.fm.2.0 June 10, 2003 Programming Environments Manual PowerPC RISC Microprocessor Family mfcr mfcr Move from Condition Register (x’7C00 0026’) mfcr rD Reserved 31 0 D 5 6 00000 10 11 0000 0 15 16 19 0 20 21 30 31 rD ← (32)0 || CR The contents of the condition register (CR) are placed into the low-order 32 bits of rD. The high-order 32 bits of rD are cleared. Other registers altered: • None PowerPC Architecture Level UISA pem8b.fm.2.0 June 10, 2003 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form X Page 511 of 785 Programming Environments Manual PowerPC RISC Microprocessor Family mffsx mffsx Move from FPSCR (x’FC00 048E’) mffs mffs. frD frD (Rc = 0) (Rc = 1) Reserved 63 0 D 5 6 00000 0 10 11 0000 0 15 16 583 Rc 20 21 30 31 frD[32-63] ← FPSCR The contents of the floating-point status and control register (FPSCR) are placed into the low-order bits of register frD. The high-order bits of register frD are undefined. Other registers altered: • Condition Register (CR1 field): Affected: FX, FEX, VX, OX(if Rc = 1) PowerPC Architecture Level UISA Page 512 of 785 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form X pem8b.fm.2.0 June 10, 2003 Programming Environments Manual PowerPC RISC Microprocessor Family mfmsr mfmsr Move from Machine State Register (x’7C00 00A6’) mfmsr rD Reserved 31 D 0 5 6 0 0000 10 11 0000 0 15 16 83 20 21 0 30 31 rD ← MSR The contents of the MSR are placed into rD. This is a supervisor-level instruction. Other registers altered: • None PowerPC Architecture Level Supervisor Level OEA Ð pem8b.fm.2.0 June 10, 2003 32-Bit 64-Bit 64-Bit Bridge Optional Form X Page 513 of 785 Programming Environments Manual PowerPC RISC Microprocessor Family mfspr mfspr Move from Special-Purpose Register (x’7C00 02A6’) mfspr rD,SPR Reserved 31 D 0 5 6 spr* 339 10 11 20 21 0 30 31 *Note: This is a split field. n ← spr[5–9] || spr[0–4] if length (SPR(n)) = 64 then rD ← SPR(n) else rD ← (32)0 || SPR(n) In the PowerPC UISA, the SPR field denotes a special-purpose register, encoded as shown in Table 8-9. . The contents of the designated special-purpose register are placed into rD. For special-purpose registers that are 32 bits long, the low-order 32 bits of rD receive the contents of the special-purpose register and the high-order 32 bits of rD are cleared. Table 8-9. PowerPC UISA SPR Encodings for mfspr SPR** Register Name Decimal spr[5–9] spr[0–4] 1 00000 00001 XER 8 00000 01000 LR 9 00000 01001 CTR Note: ** The order of the two 5-bit halves of the SPR number is reversed compared with the actual instruction coding. If the SPR field contains any value other than one of the values shown in Table 8-9. (and the processor is in user mode), one of the following occurs: • The system illegal instruction error handler is invoked. • The system supervisor-level instruction error handler is invoked. • The results are boundedly undefined. Other registers altered: • None Simplified mnemonics: mfxer mflr mfctr Page 514 of 785 rD rD rD equivalent to equivalent to equivalent to mfspr mfspr mfspr rD,1 rD,8 rD,9 pem8b.fm.2.0 June 10, 2003 Programming Environments Manual PowerPC RISC Microprocessor Family In the PowerPC OEA, the SPR field denotes a special-purpose register, encoded as shown in Table 8-10. . The contents of the designated SPR are placed into rD. For SPRs that are 32 bits long, the low-order 32 bits of rD receive the contents of the SPR and the high-order 32 bits of rD are cleared. SPR[0] = 1 if and only if reading the register is supervisor-level. Execution of this instruction specifying a defined and supervisor-level register when MSR[PR] = 1 will result in a privileged instruction type program exception. If MSR[PR] = 1, the only effect of executing an instruction with an SPR number that is not shown in Table 8-10. and has SPR[0] = 1 is to cause a supervisor-level instruction type program exception or an illegal instruction type program exception. For all other cases, MSR[PR] = 0 or SPR[0] = 0. If the SPR field contains any value that is not shown in Table 8-10. , either an illegal instruction type program exception occurs or the results are boundedly undefined. Other registers altered: • None Table 8-10. PowerPC OEA SPR Encodings for mfspr 1 SPR Register Name Access 00001 XER User 00000 01000 LR User 9 00000 01001 CTR User 18 00000 10010 DSISR Supervisor 19 00000 10011 DAR Supervisor 22 00000 10110 DEC Supervisor 25 00000 11001 SDR1 Supervisor 26 00000 11010 SRR0 Supervisor 27 00000 11011 SRR1 Supervisor 272 01000 10000 SPRG0 Supervisor 273 01000 10001 SPRG1 Supervisor 274 01000 10010 SPRG2 Supervisor 275 01000 10011 SPRG3 Supervisor Supervisor Decimal spr[5–9] spr[0–4] 1 00000 8 280 01000 11000 ASR2 282 01000 11010 EAR Supervisor 287 01000 11111 PVR Supervisor 528 10000 10000 IBAT0U Supervisor 529 10000 10001 IBAT0L Supervisor 530 10000 10010 IBAT1U Supervisor 531 10000 10011 IBAT1L Supervisor 532 10000 10100 IBAT2U Supervisor 533 10000 10101 IBAT2L Supervisor 534 10000 10110 IBAT3U Supervisor pem8b.fm.2.0 June 10, 2003 Page 515 of 785 Programming Environments Manual PowerPC RISC Microprocessor Family Table 8-10. PowerPC OEA SPR Encodings for mfspr (Continued) 1 SPR Register Name Access 10111 IBAT3L Supervisor 10000 11000 DBAT0U Supervisor 537 10000 11001 DBAT0L Supervisor 538 10000 11010 DBAT1U Supervisor 539 10000 11011 DBAT1L Supervisor 540 10000 11100 DBAT2U Supervisor 541 10000 11101 DBAT2L Supervisor 542 10000 11110 DBAT3U Supervisor 543 10000 11111 DBAT3L Supervisor 1013 11111 10101 DABR Supervisor Decimal spr[5–9] spr[0–4] 535 10000 536 1Note that the order of the two 5-bit halves of the SPR number is reversed compared with actual instruction coding. For mtspr and mfspr instructions, the SPR number coded in assembly language does not appear directly as a 10-bit binary number in the instruction. The number coded is split into two 5-bit halves that are reversed in the instruction, with the high-order five bits appearing in bits 16–20 of the instruction and the low-order five bits in bits 11–15. 264-bit implementations only. PowerPC Architecture Level Supervisor Level UISA/OEA Ð* 32-Bit 64-Bit 64-Bit Bridge Optional Form XFX * Note that mfspr is supervisor level only if SPR[0] = 1 Page 516 of 785 pem8b.fm.2.0 June 10, 2003 Programming Environments Manual PowerPC RISC Microprocessor Family mfsr mfsr Move from Segment Register (x’7C00 04A6’) mfsr rD,SR Reserved 31 D 0 5 6 0 SR 10 11 12 0000 0 15 16 595 20 21 0 30 31 rD ← SEGREG(SR) The contents of segment register SR are placed into rD. This is a supervisor-level instruction. This instruction is defined only for 32-bit implementations; using it on a 64-bit implementation causes an illegal instruction type program exception. Other registers altered: • None T EMPORARY 64-B IT BRIDGE rD ← SLB(SR) The contents of the SLB entry selected by SR are placed into rD; the contents of rD correspond to a segment table entry containing values as shown in Table 8-11. Table 8-11. GPR Content Format Following mfsr SLB Double Word Bit(s) Contents Description 0–31 0x0000_0000 ESID[0–31] 32–35 SR ESID[32–35] 57–59 rD[32–34] T, Ks, Kp 60–61 rD[35–36] N, reserved bit, or b0 0–24 rD[7–31] VSID[0–24] or reserved 25–51 rD[37–63] VSID[25–51], or b1, CNTLR_SPEC — rD[0–6] 0b0000_000 0 1 None pem8b.fm.2.0 June 10, 2003 Page 517 of 785 Programming Environments Manual PowerPC RISC Microprocessor Family If the SLB entry selected by SR was not created by an mtsr, mtsrd, or mtsrdin instruction, the contents of rD are undefined. This is a supervisor-level instruction. Other registers altered: • None PowerPC Architecture Level Supervisor Level 32-Bit OEA Ð Ð Page 518 of 785 64-Bit 64-Bit Bridge Ð Optional Form X pem8b.fm.2.0 June 10, 2003 Programming Environments Manual PowerPC RISC Microprocessor Family mfsrin mfsrin Move from Segment Register Indirect (x’7C00 0526’) mfsrin rD,rB Reserved 31 0 D 5 6 0 0000 10 11 B 15 16 659 20 21 0 30 31 rD ← SEGREG(rB[0–3]) The contents of the segment register selected by bits 0–3 of rB are copied into rD. This is a supervisor-level instruction. This instruction is defined only for 32-bit implementations. Using it on a 64-bit implementation causes an illegal instruction type program exception. Note that the rA field is not defined for the mfsrin instruction in the PowerPC architecture. However, mfsrin performs the same function in the PowerPC architecture as does the mfsri instruction in the POWER architecture (if rA = 0). Other registers altered: • None pem8b.fm.2.0 June 10, 2003 Page 519 of 785 Programming Environments Manual PowerPC RISC Microprocessor Family T EMPORARY 64-B IT BRIDGE rD ← SLB(rB[32-35]) The contents of the SLB entry selected by rB[32–35] are placed into rD; the contents of rD correspond to a segment table entry containing values as shown in Table 8-12 : Table 8-12. GPR Content Format Following mfsrin Doubleword Bit(s) Contents Description 0-31 0x0000_0000 ESID[0–31] 32-35 rB[32–35] ESID[32–35] 57-59 rD[32–34] T, Ks, Kp 60-61 rD[35–36] N, reserved bit, or b0 0-24 rD[7–31] VSID[0–24] or reserved 25-51 rD[37–63] VSID[25–51], or b1, CNTLR_SPEC 70 rD[0–6] 0b0000_000 0 1 none If the SLB entry selected by rB[32–35] was not created by an mtsr, mtsrd, or mtsrdin instruction, the contents of rD are undefined. This is a supervisor-level instruction. Other registers altered: • None PowerPC Architecture Level Supervisor Level 32-Bit OEA Ð Ð Page 520 of 785 64-Bit 64-Bit Bridge Ð Optional Form X pem8b.fm.2.0 June 10, 2003 Programming Environments Manual PowerPC RISC Microprocessor Family mftb mftb Move from Time Base (x’7C00 02E6’) mftb rD,TBR Reserved 31 0 D 5 6 tbr* 10 11 371 0 20 21 30 31 *Note: This is a split field. n ← tbr[5–9] || tbr[0–4] if n = 268 then if (64-bit implementation) then rD ← TB else rD ← TBL else if n = 269 then if (64-bit implementation) then rD ← (32)0 || TBU else rD ← TBU When reading the time base lower (TBL) on a 64-bit implementation, the contents of the entire time base (TBU || TBL) is copied into rD. Note that when reading time base upper (TBU) on a 64-bit implementation the high-order 32 bits of rD are cleared. The contents of TBL or TBU are copied into rD, as designated by the value in TBR, encoded as shown in The TBR field denotes either the TBL or TBU, encoded as shown in Table 8-13. . Table 8-13. TBR Encodings for mftb TBR* tbr[5–9] tbr[0–4] Register Name Access Decimal 268 01000 01100 TBL User 269 01000 01101 TBU User Note: *The order of the two 5-bit halves of the TBR number is reversed. If the TBR field contains any value other than one of the values shown in Table 8-13. , then one of the following occurs: • The system illegal instruction error handler is invoked. • The system supervisor-level instruction error handler is invoked. • The results are boundedly undefined. It is important to note that some implementations may implement mftb and mfspr identically, therefore, a TBR number must not match an SPR number. For more information on the time base refer to Section 2.2 , “PowerPC VEA Register Set—Time Base.” Other registers altered: pem8b.fm.2.0 June 10, 2003 Page 521 of 785 Programming Environments Manual PowerPC RISC Microprocessor Family • None Simplified mnemonics: mftb mftbu rD rD PowerPC Architecture Level VEA Page 522 of 785 equivalent to equivalent to mftb mftb Supervisor Level 32-Bit rD,268 rD,269 64-Bit 64-Bit Bridge Optional Form XFX pem8b.fm.2.0 June 10, 2003 Programming Environments Manual PowerPC RISC Microprocessor Family mtcrf mtcrf Move to Condition Register Fields (x’7C00 0120’) mtcrf CRM,rS Reserved 31 0 S 5 6 0 CRM 10 11 12 0 144 19 20 21 0 30 31 mask ← (4)(CRM[0]) || (4)(CRM[1]) ||... (4)(CRM[7]) CR ← (rS[32–63] & mask) | (CR & ¬ mask) The contents of the low-order 32 bits of rS are placed into the condition register under control of the field mask specified by CRM. The field mask identifies the 4-bit fields affected. Let i be an integer in the range 0– 7. If CRM(i) = 1, CR field i (CR bits 4 ∗ i through 4 ∗ i + 3) is set to the contents of the corresponding field of the low-order 32 bits of rS. Note that updating a subset of the eight fields of the condition register may have substantially poorer performance on some implementations than updating all of the fields. Other registers altered: • CR fields selected by mask Simplified mnemonics: mtcr rS PowerPC Architecture Level UISA pem8b.fm.2.0 June 10, 2003 equivalent to mtcrf Supervisor Level 32-Bit 0xFF,rS 64-Bit 64-Bit Bridge Optional Form XFX Page 523 of 785 Programming Environments Manual PowerPC RISC Microprocessor Family mtfsb0x mtfsb0x Move to FPSCR Bit 0 (x’FC00 008C’) mtfsb0 mtfsb0. crbD crbD (Rc = 0) (Rc = 1) Reserved 63 0 crbD 5 6 0 0000 10 11 0000 0 15 16 70 20 21 Rc 30 31 Bit crbD of the FPSCR is cleared. Other registers altered: • Condition Register (CR1 field): Affected: FX, FEX, VX, OX(if Rc = 1) • Floating-Point Status and Control Register: Affected: FPSCR bit crbD Note: Bits 1 and 2 (FEX and VX) cannot be explicitly cleared. PowerPC Architecture Level UISA Page 524 of 785 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form X pem8b.fm.2.0 June 10, 2003 Programming Environments Manual PowerPC RISC Microprocessor Family mtfsb1x mtfsb1x Move to FPSCR Bit 1 (x’FC00 004C’) mtfsb1 mtfsb1. crbD crbD (Rc = 0) (Rc = 1) Reserved 63 0 crbD 5 6 0 0000 10 11 0000 0 15 16 38 20 21 Rc 30 31 Bit crbD of the FPSCR is set. Other registers altered: • Condition Register (CR1 field): Affected: FX, FEX, VX, OX(if Rc = 1) • Floating-Point Status and Control Register: Affected: FPSCR bit crbD and FX Note: Bits 1 and 2 (FEX and VX) cannot be explicitly set. PowerPC Architecture Level UISA pem8b.fm.2.0 June 10, 2003 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form X Page 525 of 785 Programming Environments Manual PowerPC RISC Microprocessor Family mtfsfx mtfsfx Move to FPSCR Fields (x’FC00 058E’) mtfsf mtfsf. FM,frB FM,frB (Rc = 0) (Rc = 1) Reserved 63 0 0 5 6 FM 7 0 B 14 15 16 711 20 21 Rc 30 31 The low-order 32 bits of frB are placed into the FPSCR under control of the field mask specified by FM. The field mask identifies the 4-bit fields affected. Let i be an integer in the range 0–7. If FM[i] = 1, FPSCR field i (FPSCR bits 4 * i through 4 * i + 3) is set to the contents of the corresponding field of the low-order 32 bits of register frB. FPSCR[FX] is altered only if FM[0] = 1. Updating fewer than all eight fields of the FPSCR may have substantially poorer performance on some implementations than updating all the fields. When FPSCR[0–3] is specified, bits 0 (FX) and 3 (OX) are set to the values of frB[32] and frB[35] (that is, even if this instruction causes OX to change from 0 to 1, FX is set from frB[32] and not by the usual rule that FX is set when an exception bit changes from 0 to 1). Bits 1 and 2 (FEX and VX) are set according to the usual rule and not from frB[33–34]. Other registers altered: • Condition Register (CR1 field): Affected: FX, FEX, VX, OX(if Rc = 1) • Floating-Point Status and Control Register: Affected: FPSCR fields selected by mask PowerPC Architecture Level UISA Page 526 of 785 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form XFL pem8b.fm.2.0 June 10, 2003 Programming Environments Manual PowerPC RISC Microprocessor Family mtfsfix mtfsfix Move to FPSCR Field Immediate (x’FC00 010C’) mtfsfi mtfsfi. crfD,IMM crfD,IMM (Rc = 0) (Rc = 1) Reserved 63 0 crfD 5 6 00 8 0 0000 9 10 11 12 IMM 15 16 0 134 19 20 21 Rc 30 31 FPSCR[crfD] ← IMM The value of the IMM field is placed into FPSCR field crfD. FPSCR[FX] is altered only if crfD = 0. When FPSCR[0–3] is specified, bits 0 (FX) and 3 (OX) are set to the values of IMM[0] and IMM[3] (that is, even if this instruction causes OX to change from 0 to 1, FX is set from IMM[0] and not by the usual rule that FX is set when an exception bit changes from 0 to 1). Bits 1 and 2 (FEX and VX) are set according to the usual rule and not from IMM[1–2]. Other registers altered: • Condition Register (CR1 field): Affected: FX, FEX, VX, OX(if Rc = 1) • Floating-Point Status and Control Register: Affected: FPSCR field crfD PowerPC Architecture Level UISA pem8b.fm.2.0 June 10, 2003 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form X Page 527 of 785 Programming Environments Manual PowerPC RISC Microprocessor Family mtmsr mtmsr Move to Machine State Register (x’7C00 0124’) mtmsr rS Reserved 31 0 S 5 6 0 0000 10 11 0000 0 15 16 146 20 21 0 30 31 MSR ← (rS) The contents of rS are placed into the MSR. This is a supervisor-level instruction. It is also an execution synchronizing instruction except with respect to alterations to the POW and LE bits. Refer to Section 2.3.18 , “Synchronization Requirements for Special Registers and for Lookaside Buffers,” for more information. In addition, alterations to the MSR[EE] and MSR[RI] bits are effective as soon as the instruction completes. Thus if MSR[EE] = 0 and an external or decrementer exception is pending, executing an mtmsr instruction that sets MSR[EE] = 1 will cause the external or decrementer exception to be taken before the next instruction is executed, if no higher priority exception exists. This instruction is defined only for 32-bit implementations. Using it on a 64-bit implementation causes an illegal instruction type program exception. Other registers altered: • MSR T EMPORARY 64-B IT BRIDGE The mtmsr instruction may optionally be provided by a 64-bit implementation. The operation of the mtmsr instruction in a 64-bit implementation is identical to operation in a 32-bit implementation, except as described below: • Bits 32–63 of rS are placed into the corresponding bits of the MSR. The high-order 32 bits of the MSR are unchanged. Note that there is no need for an optional version of the mfmsr instruction, as the existing instruction copies the entire contents of the MSR to the selected GPR. When the optional mtmsr instruction is provided in a 64-bit implementation, the optional rfi instruction is also provided. Refer to the rfi instruction description for additional detail about the operation of the rfi instruction in 64-bit implementations. PowerPC Architecture Level Supervisor Level 32-Bit OEA Ð Ð Page 528 of 785 64-Bit 64-Bit Bridge Ð Optional Form X pem8b.fm.2.0 June 10, 2003 Programming Environments Manual PowerPC RISC Microprocessor Family mtmsrd 64-Bit Implementations Only mtmsrd Move to Machine State Register Double Word (x’7C00 0164’) mtmsrd rS Reserved 31 0 S 5 6 0 0000 10 11 0000 0 15 16 178 20 21 0 30 31 MSR ← (rS) The contents of rS are placed into the MSR. This is a supervisor-level instruction. It is also an execution synchronizing instruction except with respect to alterations to the POW and LE bits. Refer to Section 2.3.18 , “Synchronization Requirements for Special Registers and for Lookaside Buffers,” for more information. In addition, alterations to the MSR[EE] and MSR[RI] bits are effective as soon as the instruction completes. Thus if MSR[EE] = 0 and an external or decrementer exception is pending, executing an mtmsrd instruction that sets MSR[EE] = 1 will cause the external or decrementer exception to be taken before the next instruction is executed, if no higher priority exception exists. This instruction is defined only for 64-bit implementations. Using it on a 32-bit implementation causes an illegal instruction type program exception. Other registers altered: • MSR PowerPC Architecture Level Supervisor Level OEA Ð pem8b.fm.2.0 June 10, 2003 32-Bit 64-Bit Ð 64-Bit Bridge Optional Form X Page 529 of 785 Programming Environments Manual PowerPC RISC Microprocessor Family mtspr mtspr Move to Special-Purpose Register (x’7C00 03A6’) mtspr SPR,rS Reserved 31 S 0 5 6 spr* 10 11 467 20 21 0 30 31 *Note: This is a split field. n ← spr[5–9] || spr[0–4] if length (SPR(n)) = 64 then SPR(n) ← (rS) else SPR(n) ← rS[32–63] In the PowerPC UISA, the SPR field denotes a special-purpose register, encoded as shown in Table 8-14. . The contents of rS are placed into the designated special-purpose register. For special-purpose registers that are 32 bits long, the low-order 32 bits of rS are placed into the SPR. Table 8-14. PowerPC UISA SPR Encodings for mtspr SPR** Register Name Decimal spr[5–9] spr[0–4] 1 00000 00001 XER 8 00000 01000 LR 9 00000 01001 CTR Note: ** The order of the two 5-bit halves of the SPR number is reversed compared with actual instruction coding. If the SPR field contains any value other than one of the values shown in Table 8-14. , and the processor is operating in user mode, one of the following occurs: • The system illegal instruction error handler is invoked. • The system supervisor instruction error handler is invoked. • The results are boundedly undefined. Other registers altered: • See Table 8-14. . Simplified mnemonics: mtxer mtlr mtctr rD rD rD equivalent to equivalent to equivalent to mtspr mtspr mtspr 1,rD 8,rD 9,rD In the PowerPC OEA, the SPR field denotes a special-purpose register, encoded as shown in Table 8-15. . The contents of rS are placed into the designated special-purpose register. For special-purpose registers that are 32 bits long, the low-order 32 bits of rS are placed into the SPR. Page 530 of 785 pem8b.fm.2.0 June 10, 2003 Programming Environments Manual PowerPC RISC Microprocessor Family For this instruction, SPRs TBL and TBU are treated as separate 32-bit registers; setting one leaves the other unaltered. The value of SPR[0] = 1 if and only if writing the register is a supervisor-level operation. Execution of this instruction specifying a defined and supervisor-level register when MSR[PR] = 1 results in a privileged instruction type program exception. If MSR[PR] = 1 then the only effect of executing an instruction with an SPR number that is not shown in Table 8-15. and has SPR[0] = 1 is to cause a privileged instruction type program exception or an illegal instruction type program exception. For all other cases, MSR[PR] = 0 or SPR[0] = 0, if the SPR field contains any value that is not shown in Table 8-15. , either an illegal instruction type program exception occurs or the results are boundedly undefined. Other registers altered: • See Table 8-15. . Table 8-15. PowerPC OEA SPR Encodings for mtspr SPR 1 Register Name Access 00001 XER User 00000 01000 LR User 9 00000 01001 CTR User 18 00000 10010 DSISR Supervisor 19 00000 10011 DAR Supervisor 22 00000 10110 DEC Supervisor 25 00000 11001 SDR1 Supervisor 26 00000 11010 SRR0 Supervisor 27 00000 11011 SRR1 Supervisor 272 01000 10000 SPRG0 Supervisor 273 01000 10001 SPRG1 Supervisor 274 01000 10010 SPRG2 Supervisor 275 01000 10011 SPRG3 Supervisor Supervisor Decimal spr[5–9] spr[0–4] 1 00000 8 280 01000 11000 ASR2 282 01000 11010 EAR Supervisor 284 01000 11100 TBL Supervisor 285 01000 11101 TBU Supervisor 528 10000 10000 IBAT0U Supervisor 529 10000 10001 IBAT0L Supervisor 530 10000 10010 IBAT1U Supervisor 531 10000 10011 IBAT1L Supervisor 532 10000 10100 IBAT2U Supervisor 533 10000 10101 IBAT2L Supervisor 534 10000 10110 IBAT3U Supervisor pem8b.fm.2.0 June 10, 2003 Page 531 of 785 Programming Environments Manual PowerPC RISC Microprocessor Family Table 8-15. PowerPC OEA SPR Encodings for mtspr (Continued) SPR 1 Register Name Access 10111 IBAT3L Supervisor 10000 11000 DBAT0U Supervisor 537 10000 11001 DBAT0L Supervisor 538 10000 11010 DBAT1U Supervisor 539 10000 11011 DBAT1L Supervisor 540 10000 11100 DBAT2U Supervisor 541 10000 11101 DBAT2L Supervisor 542 10000 11110 DBAT3U Supervisor 543 10000 11111 DBAT3L Supervisor 1013 11111 10101 DABR Supervisor Decimal spr[5–9] spr[0–4] 535 10000 536 1Note that the order of the two 5-bit halves of the SPR number is reversed. For mtspr and mfspr instructions, the SPR number coded in assembly language does not appear directly as a 10-bit binary number in the instruction. The number coded is split into two 5-bit halves that are reversed in the instruction, with the high-order five bits appearing in bits 16– 20 of the instruction and the low-order five bits in bits 11–15. 264-bit implementations only. PowerPC Architecture Level Supervisor Level UISA/OEA Ð* 32-Bit 64-Bit 64-Bit Bridge Optional Form XFX * Note that mtspr is supervisor level only if SPR[0] = 1 Page 532 of 785 pem8b.fm.2.0 June 10, 2003 Programming Environments Manual PowerPC RISC Microprocessor Family mtsr mtsr Move to Segment Register (x’7C00 01A4’) mtsr SR,rS Reserved 31 0 S 0 5 6 SR 10 11 12 0000 0 15 16 210 20 21 0 30 31 SEGREG(SR) ← (rS) The contents of rS are placed into SR. This is a supervisor-level instruction. This instruction is defined only for 32-bit implementations. Using it on a 64-bit implementation causes an illegal instruction type program exception. Other registers altered: • None T EMPORARY 64-B IT BRIDGE SLB(SR) ← (rS[32-63]) The SLB entry selected by SR is set as though it were loaded from a segment table entry, as shown in Table 8-16. Table 8-16. SLB Entry Following mtsr Double Word 0 Bit(s) Contents Description 0–31 0x0000_0000 ESID[0–31] 32–35 SR ESID[32–35] 56 0b1 V 57–59 rS[32-34] T, Ks, Kp 60–61 rS[35-36] N, reserved bit, or b0 0–24 0x0000_00||0b0 VSID[0–24] or reserved 25–51 rS[37-63] VSID[25–51], or b1, CNTLR_SPEC 1 pem8b.fm.2.0 June 10, 2003 Page 533 of 785 Programming Environments Manual PowerPC RISC Microprocessor Family This is a supervisor-level instruction. Note that when creating an ordinary segment (T = 0) using the mtsr instruction, rS[36–39] should be set to 0x0, as these bits correspond to the reserved bits in the T = 0 format for a segment register. Other registers altered: • None PowerPC Architecture Level Supervisor Level 32-Bit OEA Ð Ð Page 534 of 785 64-Bit 64-Bit Bridge Ð Optional Form X pem8b.fm.2.0 June 10, 2003 Programming Environments Manual PowerPC RISC Microprocessor Family mtsrd mtsrd 64-Bit Implementations Only Move to Segment Register Double Word (x’7C00 00A4’) T EMPORARY 64-B IT BRIDGE mtsrd SR,rS Reserved 31 S 0 5 6 0 SR 10 11 12 0000 0 15 16 82 0 20 21 30 31 SLB(SR) ← (rS) The contents of rS are placed into the SLB selected by SR. The SLB entry is set as though it were loaded from an STE, as shown in Table 8-17. Table 8-17. SLB Entry Following mtsrd Double Word 0 Bit(s) Contents Description 0–31 0x0000_0000 ESID[0–31] 32–35 SR ESID[32–35] 56 0b1 V 57–59 rS[32–34] T, Ks, Kp 60–61 rS[35–36] N, reserved bit, or b0 0–24 rS[7–31] VSID[0–24] or reserved 25–51 rS[37–63] VSID[25–51], or b1, CNTLR_SPEC 1 This is a supervisor-level instruction. This instruction is optional, and is defined only for 64-bit implementations. If the mtsrd instruction is implemented, the mtsrdin instruction will also be implemented. Using it on a 32-bit implementation causes an illegal instruction type program exception. Other registers altered: • None PowerPC Architecture Level Supervisor Level OEA Ð pem8b.fm.2.0 June 10, 2003 32-Bit 64-Bit 64-Bit Bridge Optional Form Ð Ð Ð X Page 535 of 785 Programming Environments Manual PowerPC RISC Microprocessor Family mtsrdin 64-Bit Implementations Only mtsrdin Move to Segment Register Double Word Indirect (x’7C00 00E4’) T EMPORARY 64-B IT BRIDGE mtsrdin rS,rB Reserved 31 0 S 5 6 0 0000 10 11 B 114 15 16 20 21 0 30 31 SLB(rB[32-35]) ← (rS) The contents of rS are copied to the SLB selected by bits 32–35 of rB. The SLB entry is set as though it were loaded from an STE, as shown in Table 8-18. Table 8-18. SLB Entry following mtsrdin Double Word 0 Bit(s) Contents Description 0–31 0x0000_0000 ESID[0–31] 32–35 rB[32–35] ESID[32–35] 56 0b1 V 57–59 rS[32–34] T, Ks, Kp 60–61 rS[35–36] N, reserved bit, or b0 0–24 rS[7–31] VSID[0-24] or reserved 25–51 rS[37–63] VSID[25–51], or b1, CNTLR_SPEC 1 This is a supervisor-level instruction. This instruction is optional, and defined only for 64-bit implementations. If the mtsrdin instruction is implemented, the mtsrd instruction will also be implemented. Using it on a 32-bit implementation causes an illegal instruction exception. Other registers altered: • None PowerPC Architecture Level Supervisor Level OEA Ð Page 536 of 785 32-Bit 64-Bit 64-Bit Bridge Optional Form Ð Ð Ð X pem8b.fm.2.0 June 10, 2003 Programming Environments Manual PowerPC RISC Microprocessor Family mtsrin mtsrin Move to Segment Register Indirect (x’7C00 01E4’) mtsrin rS,rB [POWER mnemonic: mtsri] Reserved 31 0 S 5 6 0 0000 10 11 B 15 16 242 20 21 0 30 31 SEGREG(rB[0–3]) ← (rS) The contents of rS are copied to the segment register selected by bits 0–3 of rB. This is a supervisor-level instruction. This instruction is defined only for 32-bit implementations. Using it on a 64-bit implementation causes an illegal instruction type program exception. Note that the PowerPC architecture does not define the rA field for the mtsrin instruction. However, mtsrin performs the same function in the PowerPC architecture as does the mtsri instruction in the POWER architecture (if rA = 0). Other registers altered: • None pem8b.fm.2.0 June 10, 2003 Page 537 of 785 Programming Environments Manual PowerPC RISC Microprocessor Family T EMPORARY 64-B IT BRIDGE SLB(rB[32-35]) ← (rS[32-63]) The SLB entry selected by bits 32-35 of rB is set as though it were loaded from a segment table entry, as shown in Table 8-19. Table 8-19. SLB Entry Following mtsrin Double Word 0 Bit(s) Contents Description 0–31 0x0000_0000 ESID[0–31] 32–35 rB[32–35] ESID[32–35] 56 0b1 V 57–59 rS[32–34] T, Ks, Kp 60–61 rS[35–36] N, reserved bit, or b0 0–24 0x0000_00||0b0 VSID[0–24] or reserved 25–51 rS[37–63] VSID[25–51], or b1, CNTLR_SPEC 1 This is a supervisor-level instruction. Note that when creating an ordinary segment (T = 0) using the mtsrin instruction, rS[36–39] should be set to 0x0, as these bits correspond to the reserved bits in the T = 0 format for a segment register. Other registers altered: • None PowerPC Architecture Level Supervisor Level 32-Bit OEA Ð Ð Page 538 of 785 64-Bit 64-Bit Bridge Ð Optional Form X pem8b.fm.2.0 June 10, 2003 Programming Environments Manual PowerPC RISC Microprocessor Family mulhdx 64-Bit Implementations Only mulhdx Multiply High Double Word (x’7C00 0092’) mulhd mulhd. rD,rA,rB rD,rA,rB 31 0 D 5 6 (Rc = 0) (Rc = 1) A 10 11 B 0 15 16 73 20 21 22 Rc 30 31 prod[0–127] ← (rA) ∗ (rB) rD ← prod[0–63] The 64-bit operands are (rA) and (rB). The high-order 64 bits of the 128-bit product of the operands are placed into rD. Both the operands and the product are interpreted as signed integers. This instruction is defined only for 64-bit implementations. Using it on a 32-bit implementation will cause the system illegal instruction error handler to be invoked. This instruction may execute faster on some implementations if rB contains the operand having the smaller absolute value. Other registers altered: • Condition Register (CR0 field): Affected: LT, GT, EQ, SO(if Rc = 1) Note: The setting of CR0 bits LT, GT, and EQ is mode-dependent, and reflects overflow of the 64-bit result. PowerPC Architecture Level UISA pem8b.fm.2.0 June 10, 2003 Supervisor Level 32-Bit 64-Bit Ð 64-Bit Bridge Optional Form XO Page 539 of 785 Programming Environments Manual PowerPC RISC Microprocessor Family mulhdux 64-Bit Implementations Only mulhdux Multiply High Double Word Unsigned (x’7C00 0012’) mulhdu mulhdu. rD,rA,rB rD,rA,rB 31 0 D 5 6 prod[0–127] ← (rA) rD ← prod[0–63] (Rc = 0) (Rc = 1) A 10 11 B 0 15 16 9 20 21 22 Rc 30 31 ∗ (rB) The 64-bit operands are (rA) and (rB). The high-order 64 bits of the 128-bit product of the operands are placed into rD. Both the operands and the product are interpreted as unsigned integers, except that if Rc = 1 the first three bits of CR0 field are set by signed comparison of the result to zero. This instruction is defined only for 64-bit implementations. Using it on a 32-bit implementation will cause the system illegal instruction error handler to be invoked. This instruction may execute faster on some implementations if rB contains the operand having the smaller absolute value. Other registers altered: • Condition Register (CR0 field): Affected: LT, GT, EQ, SO(if Rc = 1) Note: The setting of CR0 bits LT, GT, and EQ is mode-dependent, and reflects overflow of the 64-bit result. PowerPC Architecture Level UISA Page 540 of 785 Supervisor Level 32-Bit 64-Bit Ð 64-Bit Bridge Optional Form XO pem8b.fm.2.0 June 10, 2003 Programming Environments Manual PowerPC RISC Microprocessor Family mulhwx mulhwx Multiply High Word (x’7C00 0096’) mulhw mulhw. rD,rA,rB rD,rA,rB (Rc = 0) (Rc = 1) Reserved 31 0 D 5 6 A 10 11 B 15 16 0 75 20 21 22 Rc 30 31 prod[0–63] ← rA[32–63] ∗ rB[32–63] rD[32–63] ← prod[0–31] rD[0–31] ← undefined The 6432-bit product is formed from the contents of the low-order 32 bits of rA and rB. The high-order 32 bits of the 64-bit product of the operands are placed into the low-order 32 bits of rD. The high-order 32 bits of rD are undefined. Both the operands and the product are interpreted as signed integers. This instruction may execute faster on some implementations if rB contains the operand having the smaller absolute value. Other registers altered: • Condition Register (CR0 field): Affected: LT, GT, EQ, SO (if Rc = 1) LT, GT, EQ undefined(if Rc =1 and 64-bit mode) Note: The setting of CR0 bits LT, GT, and EQ is mode-dependent, and reflects overflow of the 32-bit result. PowerPC Architecture Level UISA pem8b.fm.2.0 June 10, 2003 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form XO Page 541 of 785 Programming Environments Manual PowerPC RISC Microprocessor Family mulhwux mulhwux Multiply High Word Unsigned (x’7C00 0016’) mulhwu mulhwu. rD,rA,rB rD,rA,rB (Rc = 0) (Rc = 1) Reserved 31 0 D 5 6 A 10 11 B 15 16 0 11 20 21 22 Rc 30 31 prod[0–63] ← rA[32–63] ∗ rB[32–63] rD[32–63] ← prod[0–31] rD[0–31] ← undefined The 32-bit operands are the contents of the low-order 32 bits of rA and rB. The high-order 32 bits of the 64-bit product of the operands are placed into the low-order 32 bits of rD. The high-order 32 bits of rD are undefined. Both the operands and the product are interpreted as unsigned integers, except that if Rc = 1 the first three bits of CR0 field are set by signed comparison of the result to zero. This instruction may execute faster on some implementations if rB contains the operand having the smaller absolute value. Other registers altered: • Condition Register (CR0 field): Affected: LT, GT, EQ, SO(if Rc = 1) LT, GT, EQ undefined(if Rc =1 and 64-bit mode) Note: The setting of CR0 bits LT, GT, and EQ is mode-dependent, and reflects overflow of the 32-bit result. PowerPC Architecture Level UISA Page 542 of 785 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form XO pem8b.fm.2.0 June 10, 2003 Programming Environments Manual PowerPC RISC Microprocessor Family mulldx 64-Bit Implementations Only mulldx Multiply Low Double Word (x’7C00 01D2’) mulld mulld. mulldo mulldo. rD,rA,rB rD,rA,rB rD,rA,rB rD,rA,rB 31 0 D 5 6 (OE = 0 Rc = 0) (OE = 0 Rc = 1) (OE = 1 Rc = 0) (OE = 1 Rc = 1) A 10 11 B OE 15 16 233 Rc 20 21 22 30 31 prod[0–127] ← (rA) ∗ (rB) rD ← prod[64–127] The 64-bit operands are the contents of rA and rB. The low-order 64 bits of the 128-bit product of the operands are placed into rD. Both the operands and the product are interpreted as signed integers. The low-order 64 bits of the product are independent of whether the operands are regarded as signed or unsigned 64-bit integers. If OE = 1, then OV is set if the product cannot be represented in 64 bits. This instruction is defined only for 64-bit implementations. Using it on a 32-bit implementation will cause the system illegal instruction error handler to be invoked. This instruction may execute faster on some implementations if rB contains the operand having the smaller absolute value. Other registers altered: • Condition Register (CR0 field): Affected: LT, GT, EQ, SO(if Rc = 1) Note: CR0 field may not reflect the infinitely precise result if overflow occurs (see XER below). • XER: Affected: SO, OV(if OE = 1) Note: The setting of the affected bits in the XER is mode-independent, and reflects overflow of the 64-bit result. PowerPC Architecture Level UISA pem8b.fm.2.0 June 10, 2003 Supervisor Level 32-Bit 64-Bit Ð 64-Bit Bridge Optional Form XO Page 543 of 785 Programming Environments Manual PowerPC RISC Microprocessor Family mulli mulli Multiply Low Immediate (x’1C00 0000’) mulli rD,rA,SIMM [POWER mnemonic: muli] 07 0 D 5 6 A 10 11 SIMM 15 16 31 prod[0–12748] ← (rA) ∗ EXTS(SIMM) rD ← prod[64–12716-48] The 6432-bit first operand is (rA). The 6416-bit second operand is the sign-extended value of the SIMM field. The low-order 6432-bits of the 12848-bit product of the operands are placed into rD. Both the operands and the product are interpreted as signed integers. The low-order 64 bits (or 32 bits) of the product are calculated independently of whether the operands are treated as signed or unsigned 64-bit (or 32-bit) integers. This instruction can be used with mulhdx or mulhwx to calculate a full 128-bit (or 64-bit) product. The low-order 32 bits of the product are the correct 32-bit product for 32-bit implementations and for 32-bit mode in 64-bit implementations. Other registers altered: • None PowerPC Architecture Level UISA Page 544 of 785 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form D pem8b.fm.2.0 June 10, 2003 Programming Environments Manual PowerPC RISC Microprocessor Family mullwx mullwx Multiply Low Word (x’7C00 01D6’) mullw mullw. mullwo mullwo. rD,rA,rB rD,rA,rB rD,rA,rB rD,rA,rB (OE = 0 Rc = 0) (OE = 0 Rc = 1) (OE = 1 Rc = 0) (OE = 1 Rc = 1) [POWER mnemonics: muls, muls., mulso, mulso.] 31 0 D 5 6 A 10 11 B 15 16 OE 235 Rc 20 21 22 30 31 rD ← rA[32–63] ∗ rB[32–63] The 32-bit operands are the contents of the low-order 32 bits of rA and rB. The low-order 32 bits of the 64-bit product (rA) * (rB) are placed into rD. The low-order 32 bits of the product are the correct 32-bit product for 32-bit mode of 64-bit implementations and for 32-bit implementations. The low-order 32-bits of the product are independent of whether the operands are regarded as signed or unsigned 32-bit integers. If OE = 1, then OV is set if the product cannot be represented in 32 bits. Both the operands and the product are interpreted as signed integers. This instruction can be used with mulhwx to calculate a full 64-bit product. Note that this instruction may execute faster on some implementations if rB contains the operand having the smaller absolute value. Other registers altered: • Condition Register (CR0 field): Affected: LT, GT, EQ, SO(if Rc = 1) Note: CR0 field may not reflect the infinitely precise result if overflow occurs (see XER below). • XER: Affected: SO, OV(if OE = 1) Note: The setting of the affected bits in the XER is mode-independent, and reflects overflow of the loworder 32-bit result. PowerPC Architecture Level UISA pem8b.fm.2.0 June 10, 2003 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form XO Page 545 of 785 Programming Environments Manual PowerPC RISC Microprocessor Family nandx nandx NAND (x’7C00 03B8’) nand nand. rA,rS,rB rA,rS,rB 31 0 S 5 6 (Rc = 0) (Rc = 1) A 10 11 B 476 15 16 20 21 Rc 30 31 rA ← ¬ ((rS) & (rB)) The contents of rS are ANDed with the contents of rB and the complemented result is placed into rA. nand with rS = rB can be used to obtain the one's complement. Other registers altered: • Condition Register (CR0 field): Affected: LT, GT, EQ, SO(if Rc = 1) PowerPC Architecture Level UISA Page 546 of 785 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form X pem8b.fm.2.0 June 10, 2003 Programming Environments Manual PowerPC RISC Microprocessor Family negx negx Negate (x’7C00 00D0’) neg neg. nego nego. rD,rA rD,rA rD,rA rD,rA (OE = 0 Rc = 0) (OE = 0 Rc = 1) (OE = 1 Rc = 0) (OE = 1 Rc = 1) Reserved 31 0 D 5 6 A 10 11 0000 0 15 16 OE 104 20 21 22 Rc 30 31 rD ← ¬ (rA) + 1 The value 1 is added to the complement of the value in rA, and the resulting two’s complement is placed into rD. If executing in the default 64-bit mode and rA contains the most negative 6432-bit number (0x8000_0000_0000_0000), the result is the most negative number and, if OE = 1, OV is set. Similarly, if executing in 32-bit mode of a 64-bit implementation (or on a 32-bit implementation) and the low-order 32 bits of rA contains the most negative 32-bit number (0x8000_0000), the low-order 32 bits of the result contain the most negative 32-bit number and, if OE = 1, OV is set. Other registers altered: • Condition Register (CR0 field): Affected: LT, GT, EQ, SO(if Rc = 1) • XER: Affected: SO OV(if OE = 1) PowerPC Architecture Level UISA pem8b.fm.2.0 June 10, 2003 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form XO Page 547 of 785 Programming Environments Manual PowerPC RISC Microprocessor Family norx norx NOR (x’7C00 00F8’) nor nor. rA,rS,rB rA,rS,rB 31 0 S 5 6 (Rc = 0) (Rc = 1) A B 10 11 15 16 124 Rc 20 21 30 31 rA ← ¬ ((rS) | (rB)) The contents of rS are ORed with the contents of rB and the complemented result is placed into rA. nor with rS = rB can be used to obtain the one’s complement. Other registers altered: • Condition Register (CR0 field): Affected: LT, GT, EQ, SO(if Rc = 1) Simplified mnemonics: not rD,rS PowerPC Architecture Level UISA Page 548 of 785 equivalent to nor Supervisor Level rA,rS,rS 32-Bit 64-Bit 64-Bit Bridge Optional Form X pem8b.fm.2.0 June 10, 2003 Programming Environments Manual PowerPC RISC Microprocessor Family orx orx OR (x’7C00 0378’) or or. rA,rS,rB rA,rS,rB 31 0 S 5 6 (Rc = 0) (Rc = 1) A B 10 11 15 16 444 20 21 Rc 30 31 rA ← (rS) | (rB) The contents of rS are ORed with the contents of rB and the result is placed into rA. The simplified mnemonic mr (shown below) demonstrates the use of the or instruction to move register contents. Other registers altered: • Condition Register (CR0 field): Affected: LT, GT, EQ, SO(if Rc = 1) Simplified mnemonics: mr rA,rS PowerPC Architecture Level UISA pem8b.fm.2.0 June 10, 2003 equivalent to or Supervisor Level rA,rS,rS 32-Bit 64-Bit 64-Bit Bridge Optional Form X Page 549 of 785 Programming Environments Manual PowerPC RISC Microprocessor Family orcx orcx OR with Complement (x’7C00 0338’) orc orc. rA,rS,rB rA,rS,rB 31 0 S 5 6 (Rc = 0) (Rc = 1) A 10 11 B 15 16 412 20 21 Rc 30 31 rA ← (rS) | ¬ (rB) The contents of rS are ORed with the complement of the contents of rB and the result is placed into rA. Other registers altered: • Condition Register (CR0 field): Affected: LT, GT, EQ, SO(if Rc = 1) PowerPC Architecture Level UISA Page 550 of 785 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form X pem8b.fm.2.0 June 10, 2003 Programming Environments Manual PowerPC RISC Microprocessor Family ori ori OR Immediate (x’6000 0000’) ori rA,rS,UIMM [POWER mnemonic: oril] 24 0 S 5 6 A UIMM 10 11 15 16 31 rA ← (rS) | ((4816)0 || UIMM) The contents of rS are ORed with 0x0000_0000_0000 || UIMM and the result is placed into rA. The preferred no-op (an instruction that does nothing) is ori 0,0,0. Other registers altered: • None Simplified mnemonics: nop equivalent to PowerPC Architecture Level UISA pem8b.fm.2.0 June 10, 2003 ori Supervisor Level 0,0,0 32-Bit 64-Bit 64-Bit Bridge Optional Form D Page 551 of 785 Programming Environments Manual PowerPC RISC Microprocessor Family oris oris OR Immediate Shifted (x’6400 0000’) oris rA,rS,UIMM [POWER mnemonic: oriu] 25 0 S 5 6 A 10 11 UIMM 15 16 31 rA ← (rS) | ((32)0 || UIMM || (16)0) The contents of rS are ORed with 0x0000_0000 || UIMM || 0x0000 and the result is placed into rA. Other registers altered: • None PowerPC Architecture Level UISA Page 552 of 785 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form D pem8b.fm.2.0 June 10, 2003 Programming Environments Manual PowerPC RISC Microprocessor Family rfi rfi Return from Interrupt (x’4C00 0064’) Reserved 19 0 00 000 5 6 0000 0 0 0000 10 11 15 16 50 20 21 0 30 31 MSR[16–23, 25–27, 30–31] ← SRR1[16–23, 25–27, 30–31] NIA ←iea SRR0[0–29] || 0b00 Bits SRR1[16–23, 25–27, 30–31] are placed into the corresponding bits of the MSR. If the new MSR value does not enable any pending exceptions, then the next instruction is fetched, under control of the new MSR value, from the address SRR0[0–29] || 0b00. If the new MSR value enables one or more pending exceptions, the exception associated with the highest priority pending exception is generated; in this case the value placed into SRR0 by the exception processing mechanism is the address of the instruction that would have been executed next had the exception not occurred. Note that an implementation may define additional MSR bits, and in this case, may also cause them to be saved to SRR1 from MSR on an exception and restored to MSR from SRR1 on an rfid (or rfi). This is a supervisor-level, context synchronizing instruction. This instruction is defined only for 32-bit implementations. Using it on a 64-bit implementation causes an illegal instruction type program exception. Other registers altered: • MSR T EMPORARY 64-B IT BRIDGE The rfi instruction may optionally be provided by a 64-bit implementation. The operation of the rfi instruction in a 64-bit implementation is identical to the operation in a 32-bit implementation, except as described below: • The SRR1 bits that are copied to the corresponding bits of the MSR are bits 48–55, 57–59 and 62– 63 of SRR1. Note that depending on the implementation, additional bits from SRR1 may be restored to the MSR. The remaining bits of the MSR, including the high-order bits, are unchanged. • If the new MSR value does not enable any pending exceptions, then the next instruction is fetched under control of the new MSR value from the address SRR0[0–61 || 0b00 (when SF = 1 in the new MSR value), or from 0x0000_0000 || SRR[32–61] ||0b00 (when SF = 0 in the new MSR value). When the optional rfi instruction is provided in a 64-bit implementation, the optional mtmsr instruction is also provided. Refer to the mtmsr instruction description for additional detail about the operation of the mtmsr instruction in 64-bit implementations. PowerPC Architecture Level Supervisor Level 32-Bit OEA Ð Ð pem8b.fm.2.0 June 10, 2003 64-Bit 64-Bit Bridge Ð Optional Form XL Page 553 of 785 Programming Environments Manual PowerPC RISC Microprocessor Family rfid rfid 64-Bit Implementations Only Return from Interrupt Double Word (x’4C00 0024’) Reserved 19 0 00 000 5 6 0 0000 10 11 0000 0 15 16 18 20 21 0 30 31 MSR[0, 48–55, 57–59, 62–63] ← SRR1[0, 48–55, 57–59, 62–63] NIA ←iea SRR0[0–61] || 0b00 Bits SRR1[0, 48–55, 57–59, 62–63] are placed into the corresponding bits of the MSR. If the new MSR value does not enable any pending exceptions, then the next instruction is fetched, under control of the new MSR value, from the address SRR0[0–61] || 0b00 (when MSR[SF] = 1) or 0x0000_0000 || SRR0[32–61] || 0b00 (when MSR[SF] = 0). If the new MSR value enables one or more pending exceptions, the exception associated with the highest priority pending exception is generated; in this case the value placed into SRR0 by the exception processing mechanism is the address of the instruction that would have been executed next had the exception not occurred. Note that an implementation may define additional MSR bits, and in this case, may also cause them to be saved to SRR1 from MSR on an exception and restored to MSR from SRR1 on an rfid. This is a supervisor-level, context synchronizing instruction. This instruction is defined only for 64-bit implementations. Using it on a 32-bit implementation causes an illegal instruction type program exception. Other registers altered: • MSR PowerPC Architecture Level Supervisor Level OEA Ð Page 554 of 785 32-Bit 64-Bit Ð 64-Bit Bridge Optional Form XL pem8b.fm.2.0 June 10, 2003 Programming Environments Manual PowerPC RISC Microprocessor Family rldclx rldclx 64-Bit Implementations Only Rotate Left Double Word then Clear Left (x’7800 0010’) rldcl rldcl. rA,rS,rB,MB rA,rS,rB,MB 30 0 S 5 6 (Rc = 0) (Rc = 1) A B 10 11 mb* 15 16 20 21 8 26 27 Rc 30 31 *Note: This is a split field. n ← rB[58–63] r ← ROTL[64](rS, n) b ← mb[5] || mb[0–4] m ← MASK(b, 63) rA ← r & m The contents of rS are rotated left the number of bits specified by operand in the low-order six bits of rB. A mask is generated having 1 bits from bit MB through bit 63 and 0 bits elsewhere. The rotated data is ANDed with the generated mask and the result is placed into rA. This instruction is defined only for 64-bit implementations. Using it on a 32-bit implementation will cause the system illegal instruction error handler to be invoked. Note that the rldcl instruction can be used to extract and rotate bit fields using the methods shown below: • To extract an n-bit field, that starts at variable bit position b in register rS, right-justified into rA (clearing the remaining 64 – n bits of rA), set the low-order six bits of rB to b + n and MB = 64 – n. • To rotate the contents of a register left by variable n bits, set the low-order six bits of rB to n and MB = 0, and to shift the contents of a register right, set the low-order six bits of rB to(64 – n), and MB = 0. Other registers altered: • Condition Register (CR0 field): Affected: LT, GT, EQ, SO(if Rc = 1) Simplified mnemonics: rotld rA,rS,rB PowerPC Architecture Level UISA pem8b.fm.2.0 June 10, 2003 equivalent to rldcl Supervisor Level 32-Bit rA,rS,rB,0 64-Bit Ð 64-Bit Bridge Optional Form MDS Page 555 of 785 Programming Environments Manual PowerPC RISC Microprocessor Family rldcrx rldcrx 64-Bit Implementations Only Rotate Left Double Word then Clear Right (x’7800 0012’) rldcr rldcr. rA,rS,rB,ME rA,rS,rB,ME 30 0 S 5 6 (Rc = 0) (Rc = 1) A 10 11 B me* 15 16 20 21 9 Rc 26 27 30 31 *Note: This is a split field. n ← rB[58–63] r ← ROTL[64](rS, n) e ← me[5] || me[0–4] m ← MASK(0, e) rA ← r & m The contents of rS are rotated left the number of bits specified by the low-order six bits of rB. A mask is generated having 1 bits from bit 0 through bit ME and 0 bits elsewhere. The rotated data is ANDed with the generated mask and the result is placed into rA. This instruction is defined only for 64-bit implementations. Using it on a 32-bit implementation will cause the system illegal instruction error handler to be invoked. Note that rldcr can be used to extract and rotate bit fields using the methods shown below: • To extract an n-bit field, that starts at variable bit position b in register rS, left-justified into rA (clearing the remaining 64 – n bits of rA), set the low-order six bits of rB to b and ME = n – 1. • To rotate the contents of a register left by variable n bits, set the low-order six bits of rB to n and ME = 63, and to shift the contents of a register right, set the low-order six bits of rB to(64 – n), and ME = 63. Other registers altered: • Condition Register (CR0 field): Affected: LT, GT, EQ, SO(if Rc = 1) For a detailed list of simplified mnemonics for the rldcr instruction, refer to Appendix F. , “Simplified Mnemonics.” PowerPC Architecture Level UISA Page 556 of 785 Supervisor Level 32-Bit 64-Bit Ð 64-Bit Bridge Optional Form MDS pem8b.fm.2.0 June 10, 2003 Programming Environments Manual PowerPC RISC Microprocessor Family rldicx rldicx 64-Bit Implementations Only Rotate Left Double Word Immediate then Clear (x’7800 0008’) rldic rldic. rA,rS,SH,MB rA,rS,SH,MB 30 0 S 5 6 (Rc = 0) (Rc = 1) A 10 11 sh* mb* 15 16 20 21 2 26 27 sh* Rc 29 30 31 *Note: This is a split field. n ← sh[5] || sh[0–4] r ← ROTL[64](rS, n) b ← mb[5] || mb[0–4] m ← MASK(b, ¬ n) rA ← r & m The contents of rS are rotated left the number of bits specified by operand SH. A mask is generated having 1 bits from bit MB through bit 63 – SH and 0 bits elsewhere. The rotated data is ANDed with the generated mask and the result is placed into rA. This instruction is defined only for 64-bit implementations. Using it on a 32-bit implementation will cause the system illegal instruction error handler to be invoked. Note that rldic can be used to clear and shift bit fields using the methods shown below: • To clear the high-order b bits of the contents of a register and then shift the result left by n bits, set SH = n and MB = b – n. • To clear the high-order n bits of a register, set SH = 0 and MB = n. Other registers altered: • Condition Register (CR0 field): Affected: LT, GT, EQ, SO(if Rc = 1) Simplified mnemonics: clrlsldi rA,rS,b,nequivalent torldicrA,rS,n,b – n For a more detailed list of simplified mnemonics for the rldic instruction, refer to Appendix F. , “Simplified Mnemonics.” PowerPC Architecture Level UISA pem8b.fm.2.0 June 10, 2003 Supervisor Level 32-Bit 64-Bit Ð 64-Bit Bridge Optional Form MD Page 557 of 785 Programming Environments Manual PowerPC RISC Microprocessor Family rldiclx rldiclx 64-Bit Implementations Only Rotate Left Double Word Immediate then Clear Left (x’7800 0000’) rldicl rldicl. rA,rS,SH,MB rA,rS,SH,MB 30 0 S 5 6 (Rc = 0) (Rc = 1) A sh* 10 11 mb* 15 16 20 21 0 26 27 sh* Rc 29 30 31 *Note: This is a split field. n ← sh[5] || sh[0–4] r ← ROTL[64](rS, n) b ← mb[5] || mb[0–4] m ← MASK(b, 63) rA ← r & m The contents of rS are rotated left the number of bits specified by operand SH. A mask is generated having 1 bits from bit MB through bit 63 and 0 bits elsewhere. The rotated data is ANDed with the generated mask and the result is placed into rA. This instruction is defined only for 64-bit implementations. Using it on a 32-bit implementation will cause the system illegal instruction error handler to be invoked. Note that rldicl can be used to extract, rotate, shift, and clear bit fields using the methods shown below: • To extract an n-bit field, that starts at bit position b in rS, right-justified into rA (clearing the remaining 64 – n bits of rA), set SH = b + n and MB = 64 – n. • To rotate the contents of a register left by n bits, set SH = n and MB = 0; to rotate the contents of a register right by n bits, set SH = (64 – n), and MB = 0. • To shift the contents of a register right by n bits, set SH = 64 – n and MB = n. • To clear the high-order n bits of a register, set SH = 0 and MB = n. Other registers altered: • Condition Register (CR0 field): Affected: LT, GT, EQ, SO(if Rc = 1) Simplified mnemonics: extrdi rA,rS,n,b (n > 0) rotldi rA,rS,n rotrdi rA,rS,n srdi rA,rS,n (n < 64) clrldi rA,rS,n (n < 64) PowerPC Architecture Level UISA Page 558 of 785 equivalent to equivalent to equivalent to equivalent to equivalent to rldicl rA,rS,b + n,64 – n rldicl rA,rS,n,0 rldicl rA,rS,64 – n,0 rldicl rA,rS,64 – n,n rldicl rA,rS,0,n Supervisor Level 32-Bit 64-Bit Ð 64-Bit Bridge Optional Form MD pem8b.fm.2.0 June 10, 2003 Programming Environments Manual PowerPC RISC Microprocessor Family rldicrx rldicrx 64-Bit Implementations Only Rotate Left Double Word Immediate then Clear Right (x’7800 0004’) rldicr rldicr. rA,rS,SH,ME rA,rS,SH,ME 30 0 S 5 6 (Rc = 0) (Rc = 1) A sh* 10 11 me* 15 16 20 21 1 26 27 sh* Rc 29 30 31 *Note: This is a split field. n ← sh[5] || sh[0–4] r ← ROTL[64](rS, n) e ← me[5] || me[0–4] m ← MASK(0, e) rA ← r & m The contents of rS are rotated left the number of bits specified by operand SH. A mask is generated having 1 bits from bit 0 through bit ME and 0 bits elsewhere. The rotated data is ANDed with the generated mask and the result is placed into rA. This instruction is defined only for 64-bit implementations. Using it on a 32-bit implementation will cause the system illegal instruction error handler to be invoked. Note that rldicr can be used to extract, rotate, shift, and clear bit fields using the methods shown below: • To extract an n-bit field, that starts at bit position b in rS, left-justified into rA (clearing the remaining 64 – n bits of rA), set SH = b and ME = n – 1. • To rotate the contents of a register left (right) by n bits, set SH = n (64 – n) and ME = 63. • To shift the contents of a register left by n bits, by setting SH = n and ME = 63 – n. • To clear the low-order n bits of a register, by setting SH = 0 and ME = 63 – n. Other registers altered: • Condition Register (CR0 field): Affected: LT, GT, EQ, SO(if Rc = 1) Simplified mnemonics: extldi sldi clrrdi rA,rS,n,b rA,rS,n rA,rS,n PowerPC Architecture Level UISA pem8b.fm.2.0 June 10, 2003 equivalent to equivalent to equivalent to rldicr rldicr rldicr Supervisor Level 32-Bit rA,rS,b,n – 1 rA,rS,n,63 – n rA,rS,0,63 – n 64-Bit Ð 64-Bit Bridge Optional Form MD Page 559 of 785 Programming Environments Manual PowerPC RISC Microprocessor Family rldimix rldimix 64-Bit Implementations Only Rotate Left Double Word Immediate then Mask Insert (x’7800 000C’) rldimi rldimi. rA,rS,SH,MB rA,rS,SH,MB 30 0 S 5 6 (Rc = 0) (Rc = 1) A sh* 10 11 mb* 15 16 20 21 3 26 27 sh* Rc 29 30 31 *Note: This is a split field. n ← sh[5] || sh[0–4] r ← ROTL[64](rS, n) b ← mb[5] || mb[0–4] m ← MASK(b, ¬ n) rA ← (r & m) | (rA & ¬ m) The contents of rS are rotated left the number of bits specified by operand SH. A mask is generated having 1 bits from bit MB through bit 63 – SH and 0 bits elsewhere. The rotated data is inserted into rA under control of the generated mask. This instruction is defined only for 64-bit implementations. Using it on a 32-bit implementation will cause the system illegal instruction error handler to be invoked. Note that rldimi can be used to insert an n-bit field, that is right-justified in rS, into rA starting at bit position b, by setting SH = 64 – (b + n) and MB = b. Other registers altered: • Condition Register (CR0 field): Affected: LT, GT, EQ, SO(if Rc = 1) Simplified mnemonics: insrdi rA,rS,n,b equivalent to rldimi rA,rS,64 – (b + n),b For a more detailed list of simplified mnemonics for the rldimi instruction, refer to Appendix F. , “Simplified Mnemonics.” PowerPC Architecture Level UISA Page 560 of 785 Supervisor Level 32-Bit 64-Bit Ð 64-Bit Bridge Optional Form MD pem8b.fm.2.0 June 10, 2003 Programming Environments Manual PowerPC RISC Microprocessor Family rlwimix rlwimix Rotate Left Word Immediate then Mask Insert (x’5000 0000’) rlwimi rlwimi. rA,rS,SH,MB,ME rA,rS,SH,MB,ME (Rc = 0) (Rc = 1) [POWER mnemonics: rlimi, rlimi.] 20 0 S 5 6 A 10 11 SH 15 16 MB 20 21 ME 25 26 Rc 30 31 n ← SH r ← ROTL[32](rS[32–63], n) m ← MASK(MB + 32, ME + 32) rA ← (r & m) | (rA & ¬ m) The contents of rS are rotated left the number of bits specified by operand SH. A mask is generated having 1 bits from bit MB + 32 through bit ME + 32 and 0 bits elsewhere. The rotated data is inserted into rA under control of the generated mask. Note that rlwimi can be used to insert a bit field into the contents of rA using the methods shown below: • To insert an n-bit field, that is left-justified in the low-order 32 bits of rS, into the high-order 32 bits of rA starting at bit position b, set SH = 32 – b, MB = b, and ME = (b + n) – 1. • To insert an n-bit field, that is right-justified in the low-order 32 bits of rS, into the high-order 32 bits of rA starting at bit position b, set SH = 32 – (b + n), MB = b, and ME = (b + n) – 1. Other registers altered: • Condition Register (CR0 field): Affected: LT, GT, EQ, SO(if Rc = 1) Simplified mnemonics: inslwi rA,rS,n,b equivalent to rlwimirA,rS,32 – b,b,b + n – 1 insrwi rA,rS,n,b (n > 0)equivalent to rlwimi rA,rS,32 – (b + n),b,(b + n) – 1 PowerPC Architecture Level UISA pem8b.fm.2.0 June 10, 2003 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form M Page 561 of 785 Programming Environments Manual PowerPC RISC Microprocessor Family rlwinmx rlwinmx Rotate Left Word Immediate then AND with Mask (x’5400 0000’) rlwinm rlwinm. rA,rS,SH,MB,ME rA,rS,SH,MB,ME (Rc = 0) (Rc = 1) [POWER mnemonics: rlinm, rlinm.] 21 0 S 5 6 A 10 11 SH 15 16 MB 20 21 ME 25 26 Rc 30 31 n ← SH r ← ROTL[32](rS[32–63], n) m ← MASK(MB + 32, ME + 32) rA ← r & m The contents of rS[32-63] are rotated left the number of bits specified by operand SH. A mask is generated having 1 bits from bit MB + 32 through bit ME + 32 and 0 bits elsewhere. The rotated data is ANDed with the generated mask and the result is placed into rA. The upper 32 bits of rA are cleared. Note that rlwinm can be used to extract, rotate, shift, and clear bit fields using the methods shown below: • To extract an n-bit field, that starts at bit position b in the high-order 32 bits of rS, right-justified into rA (clearing the remaining 32 – n bits of rA), set SH = b + n, MB = 32 – n, and ME = 31. • To extract an n-bit field, that starts at bit position b in the high-order 32 bits of rS, left-justified into rA (clearing the remaining 32 – n bits of rA), set SH = b, MB = 0, and ME = n – 1. • To rotate the contents of a register left (or right) by n bits, set SH = n (32 – n), MB = 0, and ME = 31. • To shift the contents of a register right by n bits, by setting SH = 32 – n, MB = n, and ME = 31. It can be used to clear the high-order b bits of a register and then shift the result left by n bits by setting SH = n, MB = b – n and ME = 31 – n. • To clear the low-order n bits of a register, by setting SH = 0, MB = 0, and ME = 31 – n. For all uses mentioned, the high-order 32 bits of rA are cleared. Other registers altered: • Condition Register (CR0 field): Affected: LT, GT, EQ, SO(if Rc = 1) Simplified mnemonics: extlwi rA,rS,n,b (n > 0) equivalent torlwinm rA,rS,b,0,n – 1 extrwi rA,rS,n,b (n > 0) equivalent torlwinm rA,rS,b + n,32 – n,31 rotlwi rA,rS,n equivalent to rlwinm rA,rS,n,0,31 rotrwi rA,rS,n equivalent to rlwinm rA,rS,32 – n,0,31 slwi rA,rS,n (n < 32) equivalent torlwinm rA,rS,n,0,31–n srwi rA,rS,n (n < 32) equivalent torlwinm rA,rS,32 – n,n,31 Page 562 of 785 pem8b.fm.2.0 June 10, 2003 Programming Environments Manual PowerPC RISC Microprocessor Family clrlwi rA,rS,n (n < 32) equivalent torlwinm rA,rS,0,n,31 clrrwi rA,rS,n (n < 32) equivalent torlwinm rA,rS,0,0,31 – n clrlslwi rA,rS,b,n (n ð b < 32) equivalent torlwinm rA,rS,n,b – n,31 – n PowerPC Architecture Level UISA pem8b.fm.2.0 June 10, 2003 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form M Page 563 of 785 Programming Environments Manual PowerPC RISC Microprocessor Family rlwnmx rlwnmx Rotate Left Word then AND with Mask (x’5C00 0000’) rlwnm rlwnm. rA,rS,rB,MB,ME rA,rS,rB,MB,ME (Rc = 0) (Rc = 1) [POWER mnemonics: rlnm, rlnm.] 23 0 S 5 6 A 10 11 B MB 15 16 20 21 ME 25 26 Rc 30 31 n ← rB[59–6327-31] r ← ROTL[32](rS[32–63], n) m ← MASK(MB + 32, ME + 32) rA ← r & m The contents of rS are rotated left the number of bits specified by the low-order five bits of rB. A mask is generated having 1 bits from bit MB + 32 through bit ME + 32 and 0 bits elsewhere. The rotated data is ANDed with the generated mask and the result is placed into rA. Note that rlwnm can be used to extract and rotate bit fields using the methods shown as follows: • To extract an n-bit field, that starts at variable bit position b in the high-order 32 bits of rS, right-justified into rA (clearing the remaining 32 – n bits of rA), by setting the low-order five bits of rB to b + n, MB = 32 – n, and ME = 31. • To extract an n-bit field, that starts at variable bit position b in the high-order 32 bits of rS, left-justified into rA (clearing the remaining 32 – n bits of rA), by setting the low-order five bits of rB to b, MB = 0, and ME = n – 1. • To rotate the contents of a register left (or right) by n bits, by setting the low-order five bits of rB to n (32 – n), MB = 0, and ME = 31. For all uses mentioned, the high-order 32 bits of rA are cleared. Other registers altered: • Condition Register (CR0 field): Affected: LT, GT, EQ, SO(if Rc = 1) Simplified mnemonics: rotlw rA,rS,rB PowerPC Architecture Level UISA Page 564 of 785 equivalent to rlwnm Supervisor Level 32-Bit rA,rS,rB,0,31 64-Bit 64-Bit Bridge Optional Form M pem8b.fm.2.0 June 10, 2003 Programming Environments Manual PowerPC RISC Microprocessor Family sc sc System Call (x’4400 0002’) [POWER mnemonic: svca] Reserved 17 0 00 000 5 6 0 0000 10 11 0000 0000 0000 00 15 16 1 0 29 30 31 In the PowerPC UISA, the sc instruction calls the operating system to perform a service. When control is returned to the program that executed the system call, the content of the registers depends on the register conventions used by the program providing the system service. This instruction is context synchronizing, as described in Section 4.1.5.1 , “Context Synchronizing Instructions.” Other registers altered: • Dependent on the system service In PowerPC OEA, the sc instruction does the following: SRR0 ←iea CIA + 4 SRR1[33–361-4, 42–4710-15] ← 0 SRR1[0, 48–5516–23, 57–5925–27, 62–6330–31] ← MSR[0, 48–5516–23, 57–5925–27, 62–6330– 31] MSR ← new_value (see below) NIA ←iea base_ea + 0xC00 (see below) The EA of the instruction following the sc instruction is placed into SRR0. Bits 0, 48–5516–23, 57–5925–27, and 62–6330–31 of the MSR are placed into the corresponding bits of SRR1, and bits 33–361-4 and 42– 4710-15 of SRR1 are set to undefined values. Note that an implementation may define additional MSR bits, and in this case, may also cause them to be saved to SRR1 from MSR on an exception and restored to MSR from SRR1 on an rfid (or rfi). Then a system call exception is generated. The exception causes the MSR to be altered as described in Section 6.4 , “Exception Definitions.” The exception causes the next instruction to be fetched from offset 0xC00 from the physical base address determined by the new setting of MSR[IP]. Other registers altered: • SRR0 • SRR1 • MSR PowerPC Architecture Level UISA/OEA pem8b.fm.2.0 June 10, 2003 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form SC Page 565 of 785 Programming Environments Manual PowerPC RISC Microprocessor Family slbia slbia 64-Bit Implementations Only SLB Invalidate All (x’7C00 03E4’) Reserved 31 0 00 000 5 6 0 0000 10 11 0000 0 498 15 16 0 20 21 30 31 All SLB entries ← invalid The entire segment lookaside buffer (SLB) is made invalid (that is, all entries are removed). The SLB is invalidated regardless of the settings of MSR[IR] and MSR[DR]. This instruction is supervisor-level. This instruction is optional in the PowerPC architecture. This instruction is defined only for 64-bit implementations. Using it on a 32-bit implementation will cause an illegal instruction type program exception. It is not necessary that the ASR point to a valid segment table when issuing slbia. Other registers altered: • None PowerPC Architecture Level Supervisor Level OEA Ð Page 566 of 785 32-Bit 64-Bit Ð 64-Bit Bridge Optional Form Ð X pem8b.fm.2.0 June 10, 2003 Programming Environments Manual PowerPC RISC Microprocessor Family slbie slbie 64-Bit Implementations Only SLB Invalidate Entry (x’7C00 0364’) slbie rB Reserved 31 0 00 000 5 6 0 0000 10 11 B 434 15 16 0 20 21 30 31 EA ← (rB) if SLB entry exists for EA, then SLB entry ← invalid EA is the contents of rB. If the segment lookaside buffer (SLB) contains an entry corresponding to EA, that entry is made invalid (that is, removed from the SLB). The SLB search is done regardless of the settings of MSR[IR] and MSR[DR]. Block address translation for EA, if any, is ignored. This instruction is supervisor-level and optional in the PowerPC architecture. This instruction is defined only for 64-bit implementations. Using it on a 32-bit implementation will cause an illegal instruction type program exception. It is not necessary that the ASR point to a valid segment table when issuing slbie. Note that bits 11–15 of this instruction (ordinarily the position of an rA field) must be zero. This provides implementations the option of using (rA|0) + rB address arithmetic for this instruction. Other registers altered: • None PowerPC Architecture Level Supervisor Level OEA Ð pem8b.fm.2.0 June 10, 2003 32-Bit 64-Bit Ð 64-Bit Bridge Optional Form Ð X Page 567 of 785 Programming Environments Manual PowerPC RISC Microprocessor Family sldx sldx 64-Bit Implementations Only Shift Left Double Word (x’7C00 0036’) sld sld. rA,rS,rB rA,rS,rB 31 0 S 5 6 (Rc = 0) (Rc = 1) A 10 11 B 27 15 16 20 21 Rc 30 31 n ← rB[58–63] r ← ROTL[64](rS, n) if rB[57] = 0 then m ← MASK(0, 63 – n) else m ← (64)0 rA ← r & m The contents of rS are shifted left the number of bits specified by the low-order seven bits of rB. Bits shifted out of position 0 are lost. Zeros are supplied to the vacated positions on the right. The result is placed into rA. Shift amounts from 64 to 127 give a zero result. This instruction is defined only for 64-bit implementations. Using it on a 32-bit implementation will cause the system illegal instruction error handler to be invoked. Other registers altered: • Condition Register (CR0 field): Affected: LT, GT, EQ, SO(if Rc = 1) PowerPC Architecture Level UISA Page 568 of 785 Supervisor Level 32-Bit 64-Bit Ð 64-Bit Bridge Optional Form X pem8b.fm.2.0 June 10, 2003 Programming Environments Manual PowerPC RISC Microprocessor Family slwx slwx Shift Left Word (x’7C00 0030’) slw slw. rA,rS,rB rA,rS,rB (Rc = 0) (Rc = 1) [POWER mnemonics: sl, sl.] 31 0 S 5 6 A 10 11 B 15 16 24 20 21 Rc 30 31 n ← rB[59–6327-31] r ← ROTL[32](rS[32–63], n) if rB[58] = 0 then m ← MASK(32, 63 – n) else m ← (64)0 rA ← r & m The contents of the low-order 32 bits of rS are shifted left the number of bits specified by the low-order six bits of rB. Bits shifted out of position 32 are lost. Zeros are supplied to the vacated positions on the right. The 32bit result is placed into the low-order 32 bits of rA. The high-order 32 bits of rA are cleared. Shift amounts from 32 to 63 give a zero result. If bit 26 of rB = 0, the contents of rS are shifted left the number of bits specified by rB[27–31]. Bits shifted out of position 0 are lost. Zeros are supplied to the vacated positions on the right. The 32-bit result is placed into rA. If bit 26 of rB = 1, 32 zeros are placed into rA. Other registers altered: • Condition Register (CR0 field): Affected: LT, GT, EQ, SO(if Rc = 1) PowerPC Architecture Level UISA pem8b.fm.2.0 June 10, 2003 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form X Page 569 of 785 Programming Environments Manual PowerPC RISC Microprocessor Family sradx sradx 64-Bit Implementations Only Shift Right Algebraic Double Word (x’7C00 0634’) srad srad. rA,rS,rB rA,rS,rB 31 0 S 5 6 (Rc = 0) (Rc = 1) A 10 11 B 794 15 16 20 21 Rc 30 31 n ← rB[58–63] r ← ROTL[64](rS, 64 – n) if rB[57] = 0 then m ← MASK(n, 63) else m ← (64)0 S ← rS[0] rA ← (r & m) | (((64)S) & ¬ m) XER[CA] ← S & ((r & ¬ m) ¦ 0) The contents of rS are shifted right the number of bits specified by the low-order seven bits of rB. Bits shifted out of position 63 are lost. Bit 0 of rS is replicated to fill the vacated positions on the left. The result is placed into rA. XER[CA] is set if rS is negative and any 1 bits are shifted out of position 63; otherwise XER[CA] is cleared. A shift amount of zero causes rA to be set equal to rS, and XER[CA] to be cleared. Shift amounts from 64 to 127 give a result of 64 sign bits in rA, and cause XER[CA] to receive the sign bit of rS. Note that the srad instruction, followed by addze, can by used to divide quickly by 2n. The setting of the CA bit, by srad, is independent of mode. This instruction is defined only for 64-bit implementations. Using it on a 32-bit implementation will cause the system illegal instruction error handler to be invoked. Other registers altered: • Condition Register (CR0 field): Affected: LT, GT, EQ, SO(if Rc = 1) • XER: Affected: CA PowerPC Architecture Level UISA Page 570 of 785 Supervisor Level 32-Bit 64-Bit Ð 64-Bit Bridge Optional Form X pem8b.fm.2.0 June 10, 2003 Programming Environments Manual PowerPC RISC Microprocessor Family sradix sradix 64-Bit Implementations Only Shift Right Algebraic Double Word Immediate (x’7C00 0674’) sradi sradi. rA,rS,SH rA,rS,SH 31 0 S 5 6 (Rc = 0) (Rc = 1) A 10 11 sh* 413 15 16 20 21 sh* Rc 30 31 *Note: This is a split field. n ← sh[5] || sh[0–4] r ← ROTL[64](rS, 64 – n) m ← MASK(n, 63) S ← rS[0] rA ← (r & m) | (((64)S) & ¬ m) XER[CA] ← S & ((r & ¬ m) ¦ 0) The contents of rS are shifted right SH bits. Bits shifted out of position 63 are lost. Bit 0 of rS is replicated to fill the vacated positions on the left. The result is placed into rA. XER[CA] is set if rS is negative and any 1 bits are shifted out of position 63; otherwise XER[CA] is cleared. A shift amount of zero causes rA to be set equal to rS, and XER[CA] to be cleared. Note that the sradi instruction, followed by addze, can by used to divide quickly by 2n. The setting of the XER[CA] bit, by sradi, is independent of mode. This instruction is defined only for 64-bit implementations. Using it on a 32-bit implementation will cause the system illegal instruction error handler to be invoked. Other registers altered: • Condition Register (CR0 field): Affected: LT, GT, EQ, SO(if Rc = 1) • XER: Affected: CA PowerPC Architecture Level UISA pem8b.fm.2.0 June 10, 2003 Supervisor Level 32-Bit 64-Bit Ð 64-Bit Bridge Optional Form XS Page 571 of 785 Programming Environments Manual PowerPC RISC Microprocessor Family srawx srawx Shift Right Algebraic Word (x’7C00 0630’) sraw sraw. rA,rS,rB rA,rS,rB (Rc = 0) (Rc = 1) [POWER mnemonics: sra, sra.] 31 0 S 5 6 A 10 11 B 15 16 792 20 21 Rc 30 31 n ← rB[59–6327-31] r ← ROTL[32](rS[32–63], 64 – n) if rB[5826] = 0 then m ← MASK(n + 32, 63) else m ← (6432)0 S ← rS[32] rA ← r & m | (64)S & ¬ m XER[CA] ← S & (r & ¬ m[32–63] ¦ 0 The contents of the low-order 32 bits of rS are shifted right the number of bits specified by the low-order six bits of rB. Bits shifted out of position 63 are lost. Bit 32 of rS is replicated to fill the vacated positions on the left. The 32-bit result is placed into the low-order 32 bits of rA. Bit 32 of rS is replicated to fill the high-order 32 bits of rA. XER[CA] is set if the low-order 32 bits of rS contain a negative number and any 1 bits are shifted out of position 63; otherwise XER[CA] is cleared. A shift amount of zero causes rA to receive the signextended value of the low-order 32 bits of rS, and XER[CA] to be cleared. Shift amounts from 32 to 63 give a result of 64 sign bits, and cause XER[CA] to receive the sign bit of the low-order 32 bits of rS.If rB[26] = 0,then the contents of rS are shifted right the number of bits specified by rB[27–31]. Bits shifted out of position 31 are lost. The result is padded on the left with sign bits before being placed into rA. If rB[26] = 1, then rA is filled with 32 sign bits (bit 0) from rS. CR0 is set based on the value written into rA. XER[CA] is set if rS contains a negative number and any 1 bits are shifted out of position 31; otherwise XER[CA] is cleared. A shift amount of zero causes XER[CA] to be cleared. Note that the sraw instruction, followed by addze, can by used to divide quickly by 2n. The setting of the XER[CA] bit, by sraw, is independent of mode. Other registers altered: • Condition Register (CR0 field): Affected: LT, GT, EQ, SO(if Rc = 1) • XER: Affected: CA PowerPC Architecture Level UISA Page 572 of 785 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form X pem8b.fm.2.0 June 10, 2003 Programming Environments Manual PowerPC RISC Microprocessor Family srawix srawix Shift Right Algebraic Word Immediate (x’7C00 0670’) srawi srawi. rA,rS,SH rA,rS,SH (Rc = 0) (Rc = 1) [POWER mnemonics: srai, srai.] 31 0 S 5 6 A 10 11 SH 15 16 824 20 21 Rc 30 31 n ← SH r ← ROTL[32](rS[32–63], 6432 – n) m← MASK(n + 32, 63) S ← rS[32] rA ← r & m | (64)S & ¬ m XER[CA] ← S & ((r & ¬ m)[32–63] ¦ 0) The contents of the low-order 32 bits of rS are shifted right SH bits. Bits shifted out of position 63 are lost. Bit 32 of rS is replicated to fill the vacated positions on the left. The 32-bit result is placed into the low-order 32 bits of rA. Bit 32 of rS is replicated to fill the high-order 32 bits of rA. XER[CA] is set if the low-order 32 bits of rS contain a negative number and any 1 bits are shifted out of position 63; otherwise XER[CA] is cleared. A shift amount of zero causes rA to receive the sign-extended value of the low-order 32 bits of rS, and XER[CA] to be cleared.The contents of rS are shifted right the number of bits specified by operand SH. Bits shifted out of position 31 are lost. The shifted value is sign-extended before being placed in rA. The 32-bit result is placed into rA. XER[CA] is set if rS contains a negative number and any 1 bits are shifted out of position 31; otherwise XER[CA] is cleared. A shift amount of zero causes XER[CA] to be cleared. Note that the srawi instruction, followed by addze, can be used to divide quickly by 2n. The setting of the CA bit, by srawi, is independent of mode. Other registers altered: • Condition Register (CR0 field): Affected: LT, GT, EQ, SO (if Rc = 1) • XER: Affected: CA PowerPC Architecture Level UISA pem8b.fm.2.0 June 10, 2003 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form X Page 573 of 785 Programming Environments Manual PowerPC RISC Microprocessor Family srdx srdx 64-Bit Implementations Only Shift Right Double Word (x’7C00 0436’) srd srd. rA,rS,rB rA,rS,rB 31 0 S 5 6 (Rc = 0) (Rc = 1) A 10 11 B 15 16 539 20 21 Rc 30 31 n ← rB[58–63] r ← ROTL[64](rS, 64 – n) if rB[57] = 0 then m ← MASK(n, 63) else m ← (64)0 rA ← r & m The contents of rS are shifted right the number of bits specified by the low-order seven bits of rB. Bits shifted out of position 63 are lost. Zeros are supplied to the vacated positions on the left. The result is placed into rA. Shift amounts from 64 to 127 give a zero result. This instruction is defined only for 64-bit implementations. Using it on a 32-bit implementation will cause the system illegal instruction error handler to be invoked. Other registers altered: • Condition Register (CR0 field): Affected: LT, GT, EQ, SO(if Rc = 1) PowerPC Architecture Level UISA Page 574 of 785 Supervisor Level 32-Bit 64-Bit Ð 64-Bit Bridge Optional Form X pem8b.fm.2.0 June 10, 2003 Programming Environments Manual PowerPC RISC Microprocessor Family srwx srwx Shift Right Word (x’7C00 0430’) srw srw. rA,rS,rB rA,rS,rB (Rc = 0) (Rc = 1) [POWER mnemonics: sr, sr.] 31 0 S 5 6 A 10 11 B 15 16 536 20 21 Rc 30 31 n ← rB[58–6327-31] r ← ROTL[32](rS[32–63], 6432 – n) if rB[58] = 0 then m ← MASK(n + 32, 63) else m ← (64)0 rA ← r & m The contents of the low-order 32 bits of rS are shifted right the number of bits specified by the low-order six bits of rB. Bits shifted out of position 6331 are lost. Zeros are supplied to the vacated positions on the left. The 32-bit result is placed into the low-order 32 bits of rA. The high-order 32 bits of rA are cleared. Shift amounts from 32 to 63 give a zero result. Other registers altered: • Condition Register (CR0 field): Affected: LT, GT, EQ, SO(if Rc = 1) PowerPC Architecture Level UISA pem8b.fm.2.0 June 10, 2003 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form X Page 575 of 785 Programming Environments Manual PowerPC RISC Microprocessor Family stb stb Store Byte (x’9800 0000’) stb rS,d(rA) 38 0 S 5 6 A 10 11 d 15 16 31 if rA = 0 then b ← 0 else b ← (rA) EA ← b + EXTS(d) MEM(EA, 1) ← rS[56–6324-31] EA is the sum (rA|0) + d. The contents of the low-order eight bits of rS are stored into the byte in memory addressed by EA. Other registers altered: • None PowerPC Architecture Level UISA Page 576 of 785 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form D pem8b.fm.2.0 June 10, 2003 Programming Environments Manual PowerPC RISC Microprocessor Family stbu stbu Store Byte with Update (x’9C00 0000’) stbu rS,d(rA) 39 0 S 5 6 A 10 11 d 15 16 31 EA ← (rA) + EXTS(d) MEM(EA, 1) ← rS[56–6324-31] rA ← EA EA is the sum (rA) + d. The contents of the low-order eight bits of rS are stored into the byte in memory addressed by EA. EA is placed into rA. If rA = 0, the instruction form is invalid. Other registers altered: • None PowerPC Architecture Level UISA pem8b.fm.2.0 June 10, 2003 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form D Page 577 of 785 Programming Environments Manual PowerPC RISC Microprocessor Family stbux stbux Store Byte with Update Indexed (x’7C00 01EE’) stbux rS,rA,rB Reserved 31 0 S 5 6 A 10 11 B 15 16 247 21 22 0 30 31 EA ← (rA) + (rB) MEM(EA, 1) ← rS[56–6324-31] rA ← EA EA is the sum (rA) + (rB). The contents of the low-order eight bits of rS are stored into the byte in memory addressed by EA. EA is placed into rA. If rA = 0, the instruction form is invalid. Other registers altered: • None PowerPC Architecture Level UISA Page 578 of 785 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form X pem8b.fm.2.0 June 10, 2003 Programming Environments Manual PowerPC RISC Microprocessor Family stbx stbx Store Byte Indexed (x’7C00 01AE’) stbx rS,rA,rB Reserved 31 0 S 5 6 A 10 11 B 15 16 215 21 22 0 30 31 if rA = 0 then b ← 0 else b ← (rA) EA ← b + (rB) MEM(EA, 1) ← rS[56–6324-31] EA is the sum (rA|0) + (rB). The contents of the low-order eight bits of rS are stored into the byte in memory addressed by EA. Other registers altered: • None PowerPC Architecture Level UISA pem8b.fm.2.0 June 10, 2003 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form X Page 579 of 785 Programming Environments Manual PowerPC RISC Microprocessor Family std std 64-Bit Implementations Only Store Double Word (x’F800 0000’) std rS,ds(rA) 62 0 S 5 6 A 10 11 ds 00 15 16 29 30 31 if rA = 0 then b ← 0 else b ← (rA) EA ← b + EXTS(ds || 0b00) (MEM(EA, 8)) ← (rS) EA is the sum (rA|0) + (ds || 0b00). The contents of rS are stored into the double word in memory addressed by EA. This instruction is defined only for 64-bit implementations. Using it on a 32-bit implementation will cause the system illegal instruction error handler to be invoked. Other registers altered: • None PowerPC Architecture Level UISA Page 580 of 785 Supervisor Level 32-Bit 64-Bit Ð 64-Bit Bridge Optional Form DS pem8b.fm.2.0 June 10, 2003 Programming Environments Manual PowerPC RISC Microprocessor Family stdcx. stdcx. 64-Bit Implementations Only Store Double Word Conditional Indexed (x’7C00 01AD’) stdcx. rS,rA,rB 31 0 S 5 6 A 10 11 B 15 16 214 20 21 1 30 31 if rA = 0 then b ← 0 else b ← (rA) EA ← b + (rB) if RESERVE then if RESERVE_ADDR = physical_addr(EA) MEM(EA, 8) ← (rS) CR0 ← 0b00 || 0b1 || XER[SO] else u ← undefined 1-bit value if u then MEM(EA, 8) ← (rS) CR0 ← 0b00 || u || XER[SO] RESERVE ← 0 else CR0 ← 0b00 || 0b0 || XER[SO] EA is the sum (rA|0) + (rB). If a reservation exists, and the memory address specified by the stdcx. instruction is the same as that specified by the load and reserve instruction that established the reservation, the contents of rS are stored into the double word in memory addressed by EA and the reservation is cleared. If a reservation exists, but the memory address specified by the stdcx. instruction is not the same as that specified by the load and reserve instruction that established the reservation, the reservation is cleared, and it is undefined whether the contents of rS are stored into the double word in memory addressed by EA. If no reservation exists, the instruction completes without altering memory. CR0 field is set to reflect whether the store operation was performed as follows. CR0[LT GT EQ S0] = 0b00 || store_performed || XER[SO] EA must be a multiple of eight. If it is not, either the system alignment exception handler is invoked or the results are boundedly undefined. For additional information about alignment and DSI exceptions, see Section 6.4.3 , “DSI Exception (0x00300).” Note that, when used correctly, the load and reserve and store conditional instructions can provide an atomic update function for a single aligned word (load word and reserve and store word conditional) or double word (load double word and reserve and store double word conditional) of memory. In general, correct use requires that load word and reserve be paired with store word conditional, and load double word and reserve with store double word conditional, with the same memory address specified by both instructions of the pair. The only exception is that an unpaired store word conditional or store double word conditional instruction to any (scratch) EA can be used to clear any reservation held by the processor. Examples of correct uses of these instructions, to emulate primitives such as fetch and add, test and set, and compare and swap can be found in Appendix E. , “Synchronization Programming Examples.” pem8b.fm.2.0 June 10, 2003 Page 581 of 785 Programming Environments Manual PowerPC RISC Microprocessor Family A reservation is cleared if any of the following events occurs: • The processor holding the reservation executes another load and reserve instruction; this clears the first reservation and establishes a new one. • The processor holding the reservation executes a store conditional instruction to any address. • Another processor executes any store instruction to the address associated with the reservation.] • Any mechanism, other than the processor holding the reservation, stores to the address associated with the reservation. This instruction is defined only for 64-bit implementations. Using it on a 32-bit implementation will cause the system illegal instruction error handler to be invoked. Other registers altered: • Condition Register (CR0 field): Affected: LT, GT, EQ, SO PowerPC Architecture Level UISA Page 582 of 785 Supervisor Level 32-Bit 64-Bit Ð 64-Bit Bridge Optional Form X pem8b.fm.2.0 June 10, 2003 Programming Environments Manual PowerPC RISC Microprocessor Family stdu stdu 64-Bit Implementations Only Store Double Word with Update (x’F800 0001’) stdu rS,ds(rA) 62 0 S 5 6 A 10 11 ds 01 15 16 29 30 31 EA ← (rA) + EXTS(ds || 0b00) (MEM(EA, 8)) ← (rS) rA ← EA EA is the sum (rA) + (ds || 0b00). The contents of rS are stored into the double word in memory addressed by EA. EA is placed into rA. If rA = 0, the instruction form is invalid. This instruction is defined only for 64-bit implementations. Using it on a 32-bit implementation will cause the system illegal instruction error handler to be invoked. Other registers altered: • None PowerPC Architecture Level UISA pem8b.fm.2.0 June 10, 2003 Supervisor Level 32-Bit 64-Bit Ð 64-Bit Bridge Optional Form DS Page 583 of 785 Programming Environments Manual PowerPC RISC Microprocessor Family stdux stdux 64-Bit Implementations Only Store Double Word with Update Indexed (x’7C00 016A’) stdux rS,rA,rB Reserved 31 0 S 5 6 A 10 11 B 181 15 16 20 21 0 30 31 EA ← (rA) + (rB) MEM(EA, 8) ← (rS) rA ← EA EA is the sum (rA) + (rB). The contents of rS are stored into the double word in memory addressed by EA. EA is placed into rA. If rA = 0, the instruction form is invalid. This instruction is defined only for 64-bit implementations. Using it on a 32-bit implementation will cause the system illegal instruction error handler to be invoked. Other registers altered: • None PowerPC Architecture Level UISA Page 584 of 785 Supervisor Level 32-Bit 64-Bit Ð 64-Bit Bridge Optional Form X pem8b.fm.2.0 June 10, 2003 Programming Environments Manual PowerPC RISC Microprocessor Family stdx stdx 64-Bit Implementations Only Store Double Word Indexed (x’7C00 012A’) stdx rS,rA,rB Reserved 31 0 S 5 6 A 10 11 B 149 15 16 20 21 0 30 31 if rA = 0 then b ← 0 else b ← (rA) EA ← b + (rB) (MEM(EA, 8)) ← (rS) EA is the sum (rA|0) + (rB). The contents of rS are stored into the double word in memory addressed by EA. This instruction is defined only for 64-bit implementations. Using it on a 32-bit implementation will cause the system illegal instruction error handler to be invoked. Other registers altered: • None PowerPC Architecture Level UISA pem8b.fm.2.0 June 10, 2003 Supervisor Level 32-Bit 64-Bit Ð 64-Bit Bridge Optional Form X Page 585 of 785 Programming Environments Manual PowerPC RISC Microprocessor Family stfd stfd Store Floating-Point Double (x’D800 0000’) stfd frS,d(rA) 54 0 S 5 6 A 10 11 d 15 16 30 31 if rA = 0 then b ← 0 else b ← (rA) EA ← b + EXTS(d) MEM(EA, 8) ← (frS) EA is the sum (rA|0) + d. The contents of register frS are stored into the double word in memory addressed by EA. Other registers altered: • None PowerPC Architecture Level UISA Page 586 of 785 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form D pem8b.fm.2.0 June 10, 2003 Programming Environments Manual PowerPC RISC Microprocessor Family stfdu stfdu Store Floating-Point Double with Update (x’DC00 0000’) stfdu frS,d(rA) 55 0 S 5 6 A 10 11 d 15 16 31 EA ← (rA) + EXTS(d) MEM(EA, 8) ← (frS) rA ← EA EA is the sum (rA) + d. The contents of register frS are stored into the double word in memory addressed by EA. EA is placed into rA. If rA = 0, the instruction form is invalid. Other registers altered: • None PowerPC Architecture Level UISA pem8b.fm.2.0 June 10, 2003 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form D Page 587 of 785 Programming Environments Manual PowerPC RISC Microprocessor Family stfdux stfdux Store Floating-Point Double with Update Indexed (x’7C00 05EE’) stfdux frS,rA,rB Reserved 31 0 S 5 6 A 10 11 B 15 16 759 20 21 0 30 31 EA ← (rA) + (rB) MEM(EA, 8) ← (frS) rA ← EA EA is the sum (rA) + (rB). The contents of register frS are stored into the double word in memory addressed by EA. EA is placed into rA. If rA = 0, the instruction form is invalid. Other registers altered: • None PowerPC Architecture Level UISA Page 588 of 785 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form X pem8b.fm.2.0 June 10, 2003 Programming Environments Manual PowerPC RISC Microprocessor Family stfdx stfdx Store Floating-Point Double Indexed (x’7C00 05AE’) stfdx frS,rA,rB Reserved 31 0 S 5 6 A 10 11 B 15 16 727 20 21 0 30 31 if rA = 0 then b ← 0 else b ← (rA) EA ← b + (rB) MEM(EA, 8) ← (frS) EA is the sum (rA|0) + rB. The contents of register frS are stored into the double word in memory addressed by EA. Other registers altered: • None PowerPC Architecture Level UISA pem8b.fm.2.0 June 10, 2003 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form X Page 589 of 785 Programming Environments Manual PowerPC RISC Microprocessor Family stfiwx stfiwx Store Floating-Point as Integer Word Indexed (x’7C00 07AE’) stfiwx frS,rA,rB Reserved 31 0 S 5 6 A 10 11 B 15 16 983 20 21 0 30 31 if rA = 0 then b ← 0 else b ← (rA) EA ← b + (rB) MEM(EA, 4) ← frS[32–63] EA is the sum (rA|0) + (rB). The contents of the low-order 32 bits of register frS are stored, without conversion, into the word in memory addressed by EA. If the contents of register frS were produced, either directly or indirectly, by an lfs instruction, a single-precision arithmetic instruction, or frsp, then the value stored is undefined. The contents of frS are produced directly by such an instruction if frS is the target register for the instruction. The contents of frS are produced indirectly by such an instruction if frS is the final target register of a sequence of one or more floating-point move instructions, with the input to the sequence having been produced directly by such an instruction. This instruction is defined as optional by the PowerPC architecture to ensure backwards compatibility with earlier processors; however, it will likely be required for subsequent PowerPC processors. Other registers altered: • None PowerPC Architecture Level UISA Page 590 of 785 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form Ð X pem8b.fm.2.0 June 10, 2003 Programming Environments Manual PowerPC RISC Microprocessor Family stfs stfs Store Floating-Point Single (x’D000 0000’) stfs frS,d(rA) 52 0 S 5 6 A 10 11 d 15 16 31 if rA = 0 then b ← 0 else b ← (rA) EA ← b + EXTS(d) MEM(EA, 4) ← SINGLE(frS) EA is the sum (rA|0) + d. The contents of register frS are converted to single-precision and stored into the word in memory addressed by EA. Note that the value to be stored should be in single-precision format prior to the execution of the stfs instruction. For a discussion on floating-point store conversions, see Section D.7 , “Floating-Point Store Instructions.” Other registers altered: • None PowerPC Architecture Level UISA pem8b.fm.2.0 June 10, 2003 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form D Page 591 of 785 Programming Environments Manual PowerPC RISC Microprocessor Family stfsu stfsu Store Floating-Point Single with Update (x’D400 0000’) stfsu frS,d(rA) 53 0 S 5 6 A 10 11 d 15 16 31 EA ← (rA) + EXTS(d) MEM(EA, 4) ← SINGLE(frS) rA ← EA EA is the sum (rA) + d. The contents of frS are converted to single-precision and stored into the word in memory addressed by EA. Note that the value to be stored should be in single-precision format prior to the execution of the stfsu instruction. For a discussion on floating-point store conversions, see Section D.7 , “Floating-Point Store Instructions.” EA is placed into rA. If rA = 0, the instruction form is invalid. Other registers altered: • None PowerPC Architecture Level UISA Page 592 of 785 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form D pem8b.fm.2.0 June 10, 2003 Programming Environments Manual PowerPC RISC Microprocessor Family stfsux stfsux Store Floating-Point Single with Update Indexed (x’7C00 056E’) stfsux frS,rA,rB Reserved 31 0 S 5 6 A 10 11 B 15 16 695 20 21 0 30 31 EA ← (rA) + (rB) MEM(EA, 4) ← SINGLE(frS) rA ← EA EA is the sum (rA) + (rB). The contents of frS are converted to single-precision and stored into the word in memory addressed by EA. For a discussion on floating-point store conversions, see Section D.7 , “Floating-Point Store Instructions.” EA is placed into rA. If rA = 0, the instruction form is invalid. Other registers altered: • None PowerPC Architecture Level UISA pem8b.fm.2.0 June 10, 2003 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form X Page 593 of 785 Programming Environments Manual PowerPC RISC Microprocessor Family stfsx stfsx Store Floating-Point Single Indexed (x’7C00 052E’) stfsx frS,rA,rB Reserved 31 0 S 5 6 A 10 11 B 15 16 663 20 21 0 30 31 if rA = 0 then b ← 0 else b ← (rA) EA ← b + (rB) MEM(EA, 4) ← SINGLE(frS) EA is the sum (rA|0) + (rB). The contents of register frS are converted to single-precision and stored into the word in memory addressed by EA. For a discussion on floating-point store conversions, see Section D.7 , “Floating-Point Store Instructions.” Other registers altered: • None PowerPC Architecture Level UISA Page 594 of 785 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form X pem8b.fm.2.0 June 10, 2003 Programming Environments Manual PowerPC RISC Microprocessor Family sth sth Store Half Word (x’B000 0000’) sth rS,d(rA) 44 0 S 5 6 A 10 11 d 15 16 31 if rA = 0 then b ← 0 else b ← (rA) EA ← b + EXTS(d) MEM(EA, 2) ← rS[48–6316-31] EA is the sum (rA|0) + d. The contents of the low-order 16 bits of rS are stored into the half word in memory addressed by EA. Other registers altered: • None PowerPC Architecture Level UISA pem8b.fm.2.0 June 10, 2003 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form D Page 595 of 785 Programming Environments Manual PowerPC RISC Microprocessor Family sthbrx sthbrx Store Half Word Byte-Reverse Indexed (x’7C00 072C’) sthbrx rS,rA,rB Reserved 31 0 S 5 6 A 10 11 B 918 15 16 20 21 0 30 31 if rA = 0 then b ← 0 else b ← (rA) EA ← b + (rB) MEM(EA, 2) ← rS[56–6324-31] || rS[48–5516-23] EA is the sum (rA|0) + (rB). The contents of the low-order eight bits of rS are stored into bits 0–7 of the half word in memory addressed by EA. The contents of the subsequent low-order eight bits of rS are stored into bits 8–15 of the half word in memory addressed by EA. Other registers altered: • None PowerPC Architecture Level UISA Page 596 of 785 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form X pem8b.fm.2.0 June 10, 2003 Programming Environments Manual PowerPC RISC Microprocessor Family sthu sthu Store Half Word with Update (x’B400 0000’) sthu rS,d(rA) 45 0 S 5 6 d A 10 11 15 16 31 EA ← (rA) + EXTS(d) MEM(EA, 2) ← rS[48–6316-31] rA ← EA EA is the sum (rA) + d. The contents of the low-order 16 bits of rS are stored into the half word in memory addressed by EA. EA is placed into rA. If rA = 0, the instruction form is invalid. Other registers altered: • None PowerPC Architecture Level UISA pem8b.fm.2.0 June 10, 2003 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form D Page 597 of 785 Programming Environments Manual PowerPC RISC Microprocessor Family sthux sthux Store Half Word with Update Indexed (x’7C00 036E’) sthux rS,rA,rB Reserved 31 0 S 5 6 A 10 11 B 15 16 439 20 21 0 30 31 EA ← (rA) + (rB) MEM(EA, 2) ← rS[48–6316-31] rA ← EA EA is the sum (rA) + (rB). The contents of the low-order 16 bits of rS are stored into the half word in memory addressed by EA. EA is placed into rA. If rA = 0, the instruction form is invalid. Other registers altered: • None PowerPC Architecture Level UISA Page 598 of 785 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form X pem8b.fm.2.0 June 10, 2003 Programming Environments Manual PowerPC RISC Microprocessor Family sthx sthx Store Half Word Indexed (x’7C00 032E’) sthx rS,rA,rB Reserved 31 0 S 5 6 A 10 11 B 15 16 407 20 21 0 30 31 if rA = 0 then b ← 0 else b ← (rA) EA ← b + (rB) MEM(EA, 2) ← rS[48–6316-31] EA is the sum (rA|0) + (rB). The contents of the low-order 16 bits of rS are stored into the half word in memory addressed by EA. Other registers altered: • None PowerPC Architecture Level UISA pem8b.fm.2.0 June 10, 2003 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form X Page 599 of 785 Programming Environments Manual PowerPC RISC Microprocessor Family stmw stmw Store Multiple Word (x’BC00 0000’) stmw rS,d(rA) [POWER mnemonic: stm] 47 0 S 5 6 A 10 11 d 15 16 31 if rA = 0 then b ← 0 else b ← (rA) EA ← b + EXTS(d) r ← rS do while r ð 31 MEM(EA, 4) ← GPR(r)[32–63] r← r + 1 EA ← EA + 4 EA is the sum (rA|0) + d. n = (32 – rS). n consecutive words starting at EA are stored from the low-order 32 bits of GPRs rS through r31. For example, if rS = 30, 2 words are stored. EA must be a multiple of four. If it is not, either the system alignment exception handler is invoked or the results are boundedly undefined. For additional information about alignment and DSI exceptions, see Section 6.4.3 , “DSI Exception (0x00300).” Note that, in some implementations, this instruction is likely to have a greater latency and take longer to execute, perhaps much longer, than a sequence of individual load or store instructions that produce the same results. Other registers altered: • None PowerPC Architecture Level UISA Page 600 of 785 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form D pem8b.fm.2.0 June 10, 2003 Programming Environments Manual PowerPC RISC Microprocessor Family stswi stswi Store String Word Immediate (x’7C00 05AA’) stswi rS,rA,NB [POWER mnemonic: stsi] Reserved 31 0 S 5 6 A 10 11 NB 15 16 725 20 21 0 30 31 if rA = 0 then EA ← 0 else EA ← (rA) if NB = 0 then n ← 32 else n ← NB r ← rS – 1 i ← 32 do while n > 0 if i = 32 then r ← r + 1 (mod 32) MEM(EA, 1) ← GPR(r)[i–i + 7] i← i + 8 if i = 64 then i ← 32 EA ← EA + 1 n ← n– 1 EA is (rA|0). Let n = NB if NB ¦ 0, n = 32 if NB = 0; n is the number of bytes to store. Let nr = CEIL(n ÷ 4); nr is the number of registers to supply data. n consecutive bytes starting at EA are stored from GPRs rS through rS + nr – 1. Data is stored from the loworder four bytes of each GPR. Bytes are stored left to right from each register. The sequence of registers wraps around through r0 if required. Under certain conditions (for example, segment boundary crossing) the data alignment exception handler may be invoked. For additional information about data alignment exceptions, see Section 6.4.3 , “DSI Exception (0x00300).” Note that, in some implementations, this instruction is likely to have a greater latency and take longer to execute, perhaps much longer, than a sequence of individual load or store instructions that produce the same results. Other registers altered: • None PowerPC Architecture Level UISA pem8b.fm.2.0 June 10, 2003 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form X Page 601 of 785 Programming Environments Manual PowerPC RISC Microprocessor Family stswx stswx Store String Word Indexed (x’7C00 052A’) stswx rS,rA,rB [POWER mnemonic: stsx] Reserved 31 0 S 5 6 A 10 11 B 15 16 661 20 21 0 30 31 if rA = 0 then b ← 0 else b ← (rA) EA ← b + (rB) n ← XER[25–31] r ← rS – 1 i ← 32 do while n > 0 if i = 32 then r ← r + 1 (mod 32) MEM(EA, 1) ← GPR(r)[i–i + 7] i← i + 8 if i = 64 then i ← 32 EA ← EA + 1 n ←n– 1 EA is the sum (rA|0) + (rB). Let n = XER[25–31]; n is the number of bytes to store. Let nr = CEIL(n ÷ 4); nr is the number of registers to supply data. n consecutive bytes starting at EA are stored from GPRs rS through rS + nr – 1. Data is stored from the loworder four bytes of each GPR. Bytes are stored left to right from each register. The sequence of registers wraps around through r0 if required. If n = 0, no bytes are stored. Under certain conditions (for example, segment boundary crossing) the data alignment exception handler may be invoked. For additional information about data alignment exceptions, see Section 6.4.3 , “DSI Exception (0x00300).” Note that, in some implementations, this instruction is likely to have a greater latency and take longer to execute, perhaps much longer, than a sequence of individual load or store instructions that produce the same results. Other registers altered: • None PowerPC Architecture Level UISA Page 602 of 785 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form X pem8b.fm.2.0 June 10, 2003 Programming Environments Manual PowerPC RISC Microprocessor Family stw stw Store Word (x’9000 0000’) stw rS,d(rA) [POWER mnemonic: st] 36 0 S 5 6 A 10 11 d 15 16 31 if rA = 0 then b ← 0 else b ← (rA) EA ← b + EXTS(d) MEM(EA, 4) ← rS[32–63] EA is the sum (rA|0) + d. The contents of the low-order 32 bits of rS are stored into the word in memory addressed by EA. Other registers altered: • None PowerPC Architecture Level UISA pem8b.fm.2.0 June 10, 2003 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form D Page 603 of 785 Programming Environments Manual PowerPC RISC Microprocessor Family stwbrx stwbrx Store Word Byte-Reverse Indexed (x’7C00 052C’) stwbrx rS,rA,rB [POWER mnemonic: stbrx] Reserved 31 0 S 5 6 A 10 11 B 15 16 662 20 21 0 30 31 if rA = 0 then b ← 0 else b ← (rA) EA ← b + (rB) MEM(EA, 4) ← rS[56–6324-31] || rS[48–5516-23] || rS[40–478-15] || rS[32–390-7] EA is the sum (rA|0) + (rB). The contents of the low-order eight bits of rS are stored into bits 0–7 of the word in memory addressed by EA. The contents of the subsequent eight low-order bits of rS are stored into bits 8– 15 of the word in memory addressed by EA. The contents of the subsequent eight low-order bits of rS are stored into bits 16–23 of the word in memory addressed by EA. The contents of the subsequent eight loworder bits of rS are stored into bits 24–31 of the word in memory addressed by EA. Other registers altered: • None PowerPC Architecture Level UISA Page 604 of 785 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form X pem8b.fm.2.0 June 10, 2003 Programming Environments Manual PowerPC RISC Microprocessor Family stwcx. stwcx. Store Word Conditional Indexed (x’7C00 012D’) stwcx. rS,rA,rB 31 0 S 5 6 A 10 11 B 15 16 150 20 21 1 30 31 if rA = 0 then b ← 0 else b ← (rA) EA ← b + (rB) if RESERVE then if RESERVE_ADDR = physical_addr(EA) MEM(EA, 4) ← rS[32–63] CR0 ← 0b00 || 0b1 || XER[SO] else u ← undefined 1-bit value if u then MEM(EA, 4) ← rS[32–63] CR0 ← 0b00 || u || XER[SO] RESERVE ← 0 else CR0 ← 0b00 || 0b0 || XER[SO] EA is the sum (rA|0) + (rB). If the reserved bit is set, the stwcx. instruction stores rS to effective address (rA + rB), clears the reserved bit, and sets CR0[EQ]. If the reserved bit is not set, the stwcx. instruction does not do a store; it leaves the reserved bit cleared and clears CR0[EQ]. Software must look at CR0[EQ] to see if the stwcx. was successful. The reserved bit is set by the lwarx instruction. The reserved bit is cleared by any stwcx. instruction to any address, and also by snooping logic if it detects that another processor does any kind of store to the block indicated in the reservation buffer when reserved is set. If a reservation exists, and the memory address specified by the stwcx. instruction is the same as that specified by the load and reserve instruction that established the reservation, the contents of the low-order 32 bits of rS are stored into the word in memory addressed by EA and the reservation is cleared. If a reservation exists, but the memory address specified by the stwcx. instruction is not the same as that specified by the load and reserve instruction that established the reservation, the reservation is cleared, and it is undefined whether the contents of the low-order 32 bits of rS are stored into the word in memory addressed by EA. If no reservation exists, the instruction completes without altering memory. CR0 field is set to reflect whether the store operation was performed as follows. CR0[LT GT EQ S0] = 0b00 || store_performed || XER[SO] EA must be a multiple of four. If it is not, either the system alignment exception handler is invoked or the results are boundedly undefined. For additional information about alignment and DSI exceptions, see Section 6.4.3 , “DSI Exception (0x00300).” pem8b.fm.2.0 June 10, 2003 Page 605 of 785 Programming Environments Manual PowerPC RISC Microprocessor Family The granularity with which reservations are managed is implementation-dependent. Therefore, the memory to be accessed by the load and reserve and store conditional instructions should be allocated by a system library program. Other registers altered: • Condition Register (CR0 field): Affected: LT, GT, EQ, SO PowerPC Architecture Level UISA Page 606 of 785 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form X pem8b.fm.2.0 June 10, 2003 Programming Environments Manual PowerPC RISC Microprocessor Family stwu stwu Store Word with Update (x’9400 0000’) stwu rS,d(rA) [POWER mnemonic: stu] 37 0 S 5 6 d A 10 11 15 16 31 EA ← (rA) + EXTS(d) MEM(EA, 4) ← rS[32–63] rA ← EA EA is the sum (rA) + d. The contents of the low-order 32 bits of rS are stored into the word in memory addressed by EA. EA is placed into rA. If rA = 0, the instruction form is invalid. Other registers altered: • None PowerPC Architecture Level UISA pem8b.fm.2.0 June 10, 2003 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form D Page 607 of 785 Programming Environments Manual PowerPC RISC Microprocessor Family stwux stwux Store Word with Update Indexed (x’7C00 016E’) stwux rS,rA,rB [POWER mnemonic: stux] Reserved 31 0 S 5 6 A 10 11 B 15 16 183 20 21 0 30 31 EA ← (rA) + (rB) MEM(EA, 4) ← rS[32–63] rA ← EA EA is the sum (rA) + (rB). The contents of the low-order 32 bits of rS are stored into the word in memory addressed by EA. EA is placed into rA. If rA = 0, the instruction form is invalid. Other registers altered: • None PowerPC Architecture Level UISA Page 608 of 785 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form X pem8b.fm.2.0 June 10, 2003 Programming Environments Manual PowerPC RISC Microprocessor Family stwx stwx Store Word Indexed (x’7C00 012E’) stwx rS,rA,rB [POWER mnemonic: stx] Reserved 31 0 S 5 6 A 10 11 B 15 16 151 20 21 0 30 31 if rA = 0 then b ← 0 else b ← (rA) EA ← b + (rB) MEM(EA, 4) ← rS[32–63] EA is the sum (rA|0) + (rB). The contents of the low-order 32 bits of rS are is stored into the word in memory addressed by EA. Other registers altered: • None PowerPC Architecture Level UISA pem8b.fm.2.0 June 10, 2003 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form X Page 609 of 785 Programming Environments Manual PowerPC RISC Microprocessor Family subfx subfx Subtract From (x’7C00 0050’) subf subf. subfo subfo. rD,rA,rB rD,rA,rB rD,rA,rB rD,rA,rB 31 0 D 5 6 (OE = 0 Rc = 0) (OE = 0 Rc = 1) (OE = 1 Rc = 0) (OE = 1 Rc = 1) A B 10 11 15 16 OE 40 20 21 22 Rc 30 31 rD ← ¬ (rA) + (rB) + 1 The sum ¬ (rA) + (rB) + 1 is placed into rD. The subf instruction is preferred for subtraction because it sets few status bits. Other registers altered: • Condition Register (CR0 field): Affected: LT, GT, EQ, SO(if Rc = 1) • XER: Affected: SO, OV(if OE = 1) Simplified mnemonics: sub rD,rA,rB PowerPC Architecture Level UISA Page 610 of 785 equivalent to subf Supervisor Level 32-Bit rD,rB,rA 64-Bit 64-Bit Bridge Optional Form XO pem8b.fm.2.0 June 10, 2003 Programming Environments Manual PowerPC RISC Microprocessor Family subfcx subfcx Subtract from Carrying (x’7C00 0010’) subfc subfc. subfco subfco. rD,rA,rB rD,rA,rB rD,rA,rB rD,rA,rB (OE = 0 Rc = 0) (OE = 0 Rc = 1) (OE = 1 Rc = 0) (OE = 1 Rc = 1) [POWER mnemonics: sf, sf., sfo, sfo.] 31 0 D 5 6 A B 10 11 15 16 OE 8 Rc 20 21 22 30 31 rD ← ¬ (rA) + (rB) + 1 The sum ¬ (rA) + (rB) + 1 is placed into rD. Other registers altered: • Condition Register (CR0 field): Affected: LT, GT, EQ, SO (if Rc = 1) Note: CR0 field may not reflect the infinitely precise result if overflow occurs (see XER below). • XER: Affected: CA Affected: SO, OV (if OE = 1) Note: The setting of the affected bits in the XER is mode-dependent, and reflects overflow of the 64-bit result in 64-bit mode and overflow of the low-order 32-bit result in 32-bit mode. For further information about 64-bit mode and 32-bit mode in 64-bit implementations, see 3. , “Operand Conventions.” Simplified mnemonics: subc rD,rA,rB PowerPC Architecture Level UISA pem8b.fm.2.0 June 10, 2003 equivalent to subfc Supervisor Level 32-Bit rD,rB,rA 64-Bit 64-Bit Bridge Optional Form XO Page 611 of 785 Programming Environments Manual PowerPC RISC Microprocessor Family subfex subfex Subtract from Extended (x’7C00 0110’) subfe subfe. subfeo subfeo. rD,rA,rB rD,rA,rB rD,rA,rB rD,rA,rB (OE = 0 Rc = 0) (OE = 0 Rc = 1) (OE = 1 Rc = 0) (OE = 1 Rc = 1) [POWER mnemonics: sfe, sfe., sfeo, sfeo.] 31 0 D 5 6 A 10 11 B 15 16 OE 136 Rc 20 21 22 30 31 rD ← ¬ (rA) + (rB) + XER[CA] The sum ¬ (rA) + (rB) + XER[CA] is placed into rD. Other registers altered: • Condition Register (CR0 field): Affected: LT, GT, EQ, SO(if Rc = 1) Note: CR0 field may not reflect the infinitely precise result if overflow occurs (see XER below). • XER: Affected: CA Affected: SO, OV(if OE = 1) Note: The setting of the affected bits in the XER is mode-dependent, and reflects overflow of the 64-bit result in 64-bit mode and overflow of the low-order 32-bit result in 32-bit mode. For further information about 64-bit mode and 32-bit mode in 64-bit implementations, see 3. , “Operand Conventions.” PowerPC Architecture Level UISA Page 612 of 785 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form XO pem8b.fm.2.0 June 10, 2003 Programming Environments Manual PowerPC RISC Microprocessor Family subfic subfic Subtract from Immediate Carrying (x’2000 0000’) subfic rD,rA,SIMM [POWER mnemonic: sfi] 08 0 D 5 6 A 10 11 SIMM 15 16 31 rD ← ¬ (rA) + EXTS(SIMM) + 1 The sum ¬ (rA) + EXTS(SIMM) + 1 is placed into rD. Other registers altered: • XER: Affected: CA Note: The setting of the affected bits in the XER is mode-dependent, and reflects overflow of the 64-bit result in 64-bit mode and overflow of the low-order 32-bit result in 32-bit mode. For further information about 64-bit mode and 32-bit mode in 64-bit implementations, see 3. , “Operand Conventions.” PowerPC Architecture Level UISA pem8b.fm.2.0 June 10, 2003 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form D Page 613 of 785 Programming Environments Manual PowerPC RISC Microprocessor Family subfmex subfmex Subtract from Minus One Extended (x’7C00 01D0’) subfme subfme. subfmeo subfmeo. rD,rA rD,rA rD,rA rD,rA (OE = 0 Rc = 0) (OE = 0 Rc = 1) (OE = 1 Rc = 0) (OE = 1 Rc = 1) [POWER mnemonics: sfme, sfme., sfmeo, sfmeo.] Reserved 31 0 D 5 6 A 10 11 0000 0 15 16 OE 232 Rc 20 21 22 30 31 rD ← ¬ (rA) + XER[CA] – 1 The sum ¬ (rA) + XER[CA] + (6432)1 is placed into rD. Other registers altered: • Condition Register (CR0 field): Affected: LT, GT, EQ, SO(if Rc = 1) Note: CR0 field may not reflect the infinitely precise result if overflow occurs (see XER below). • XER: Affected: CA Affected: SO, OV(if OE = 1) Note: The setting of the affected bits in the XER is mode-dependent, and reflects overflow of the 64-bit result in 64-bit mode and overflow of the low-order 32-bit result in 32-bit mode. For further information about 64-bit mode and 32-bit mode in 64-bit implementations, see 3. , “Operand Conventions.” PowerPC Architecture Level UISA Page 614 of 785 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form XO pem8b.fm.2.0 June 10, 2003 Programming Environments Manual PowerPC RISC Microprocessor Family subfzex subfzex Subtract from Zero Extended (x’7C00 0190’) subfze subfze. subfzeo subfzeo. rD,rA rD,rA rD,rA rD,rA (OE = 0 Rc = 0) (OE = 0 Rc = 1) (OE = 1 Rc = 0) (OE = 1 Rc = 1) [POWER mnemonics: sfze, sfze., sfzeo, sfzeo.] Reserved 31 0 D 5 6 A 10 11 0000 0 15 16 OE 200 Rc 20 21 22 30 31 rD ← ¬ (rA) + XER[CA] The sum ¬ (rA) + XER[CA] is placed into rD. Other registers altered: • Condition Register (CR0 field): Affected: LT, GT, EQ, SO(if Rc = 1) Note: CR0 field may not reflect the infinitely precise result if overflow occurs (see XER below). • XER: Affected: CA Affected: SO, OV(if OE = 1) Note: The setting of the affected bits in the XER is mode-dependent, and reflects overflow of the 64-bit result in 64-bit mode and overflow of the low-order 32-bit result in 32-bit mode. For further information about 64-bit mode and 32-bit mode in 64-bit implementations, see 3. , “Operand Conventions.” PowerPC Architecture Level UISA pem8b.fm.2.0 June 10, 2003 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form XO Page 615 of 785 Programming Environments Manual PowerPC RISC Microprocessor Family sync sync Synchronize (x’7C00 04AC’) [POWER mnemonic: dcs] Reserved 31 0 00 000 5 6 0 0000 10 11 0000 0 15 16 598 0 20 21 30 31 The sync instruction provides an ordering function for the effects of all instructions executed by a given processor. Executing a sync instruction ensures that all instructions preceding the sync instruction appear to have completed before the sync instruction completes, and that no subsequent instructions are initiated by the processor until after the sync instruction completes. When the sync instruction completes, all external accesses caused by instructions preceding the sync instruction will have been performed with respect to all other mechanisms that access memory. For more information on how the sync instruction affects the VEA, refer to 5. , “Cache Model and Memory Coherency.” Multiprocessor implementations also send a sync address-only broadcast that is useful in some designs. For example, if a design has an external buffer that re-orders loads and stores for better bus efficiency, the sync broadcast signals to that buffer that previous loads/stores must be completed before any following loads/stores. The sync instruction can be used to ensure that the results of all stores into a data structure, caused by store instructions executed in a “critical section” of a program, are seen by other processors before the data structure is seen as unlocked. The functions performed by the sync instruction will normally take a significant amount of time to complete, so indiscriminate use of this instruction may adversely affect performance. In addition, the time required to execute sync may vary from one execution to another. The eieio instruction may be more appropriate than sync for many cases. This instruction is execution synchronizing. For more information on execution synchronization, see Section 4.1.5 , “Synchronizing Instructions.” Other registers altered: • None PowerPC Architecture Level UISA Page 616 of 785 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form X pem8b.fm.2.0 June 10, 2003 Programming Environments Manual PowerPC RISC Microprocessor Family td td 64-Bit Implementations Only Trap Double Word (x’7C00 0088’) td TO,rA,rB Reserved 31 0 TO 5 6 A B 10 11 68 15 16 20 21 0 30 31 a ← (rA) b ← (rB) if (a < b) & TO[0] then TRAP if (a > b) & TO[1] then TRAP if (a = b) & TO[2] then TRAP if (a U b) & TO[4] then TRAP The contents of rA are compared with the contents of rB. If any bit in the TO field is set and its corresponding condition is met by the result of the comparison, then the system trap handler is invoked. This instruction is defined only for 64-bit implementations. Using it on a 32-bit implementation will cause the system illegal instruction error handler to be invoked. Other registers altered: • None Simplified mnemonics: tdge tdlnl rA,rB rA,rB PowerPC Architecture Level UISA pem8b.fm.2.0 June 10, 2003 equivalent to equivalent to td td Supervisor Level 12,rA,rB 5,rA,rB 32-Bit 64-Bit Ð 64-Bit Bridge Optional Form X Page 617 of 785 Programming Environments Manual PowerPC RISC Microprocessor Family tdi tdi 64-Bit Implementations Only Trap Double Word Immediate (x’0800 0000’) tdi TO,rA,SIMM 02 0 TO 5 6 A SIMM 10 11 15 16 31 a ← (rA) if (a < EXTS(SIMM)) & TO[0] then TRAP if (a > EXTS(SIMM)) & TO[1] then TRAP if (a = EXTS(SIMM)) & TO[2] then TRAP if (a U EXTS(SIMM)) & TO[4] then TRAP The contents of rA are compared with the sign-extended value of the SIMM field. If any bit in the TO field is set and its corresponding condition is met by the result of the comparison, then the system trap handler is invoked. This instruction is defined only for 64-bit implementations. Using it on a 32-bit implementation will cause the system illegal instruction error handler to be invoked. Other registers altered: • None Simplified mnemonics: tdlti tdnei rA,value rA,value PowerPC Architecture Level UISA Page 618 of 785 equivalent to equivalent to tdi tdi Supervisor Level 16,rA,value 24,rA,value 32-Bit 64-Bit Ð 64-Bit Bridge Optional Form D pem8b.fm.2.0 June 10, 2003 Programming Environments Manual PowerPC RISC Microprocessor Family tlbia tlbia Translation Lookaside Buffer Invalidate All (x’7C00 02E4’) Reserved 31 0 00 000 5 6 0 0000 10 11 0000 0 15 16 370 20 21 0 30 31 All TLB entries ← invalid The entire translation lookaside buffer (TLB) is invalidated (that is, all entries are removed). The TLB is invalidated regardless of the settings of MSR[IR] and MSR[DR]. The invalidation is done without reference to the SLB, segment table, or segment registers. This instruction does not cause the entries to be invalidated in other processors. This is a supervisor-level instruction and optional in the PowerPC architecture. Other registers altered: • None PowerPC Architecture Level Supervisor Level OEA Ð pem8b.fm.2.0 June 10, 2003 32-Bit 64-Bit 64-Bit Bridge Optional Form Ð X Page 619 of 785 Programming Environments Manual PowerPC RISC Microprocessor Family tlbie tlbie Translation Lookaside Buffer Invalidate Entry (x’7C00 0264’) tlbie rB [POWER mnemonic: tlbi] Reserved 31 0 00 000 5 6 0 0000 10 11 B 30k6 15 16 20 21 0 30 31 VPS ← rB[36–514-19] Identify TLB entries corresponding to VPS Each such TLB entry ← invalid EA is the contents of rB. If the translation lookaside buffer (TLB) contains an entry corresponding to EA, that entry is made invalid (that is, removed from the TLB). Multiprocessing implementations (for example, the 601, and 604) send a tlbie address-only broadcast over the address bus to tell other processors to invalidate the same TLB entry in their TLBs. The TLB search is done regardless of the settings of MSR[IR] and MSR[DR]. The search is done based on a portion of the logical page number within a segment, without reference to the SLB, segment table, or segment registers. All entries matching the search criteria are invalidated. Block address translation for EA, if any, is ignored. Refer to Section 7.5.3.4 , “Synchronization of Memory Accesses and Referenced and Changed Bit Updates,” and Section 7.6.3 , “Page Table Updates,” for other requirements associated with the use of this instruction. This is a supervisor-level instruction and optional in the PowerPC architecture. Other registers altered: • None PowerPC Architecture Level Supervisor Level OEA Ð Page 620 of 785 32-Bit 64-Bit 64-Bit Bridge Optional Form Ð X pem8b.fm.2.0 June 10, 2003 Programming Environments Manual PowerPC RISC Microprocessor Family tlbsync tlbsync TLB Synchronize (x’7C00 046C’) Reserved 31 0 00 000 5 6 0 0000 10 11 0000 0 15 16 566 0 20 21 30 31 If an implementation sends a broadcast for tlbie then it will also send a broadcast for tlbsync. Executing a tlbsync instruction ensures that all tlbie instructions previously executed by the processor executing the tlbsync instruction have completed on all other processors. The operation performed by this instruction is treated as a caching-inhibited and guarded data access with respect to the ordering done by eieio. Note that the 601 expands the use of the sync instruction to cover tlbsync functionality. Refer to Section 7.5.3.4 , “Synchronization of Memory Accesses and Referenced and Changed Bit Updates,” and Section 7.6.3 , “Page Table Updates,” for other requirements associated with the use of this instruction. This instruction is supervisor-level and optional in the PowerPC architecture. Other registers altered: • None PowerPC Architecture Level Supervisor Level OEA Ð pem8b.fm.2.0 June 10, 2003 32-Bit 64-Bit 64-Bit Bridge Optional Form Ð X Page 621 of 785 Programming Environments Manual PowerPC RISC Microprocessor Family tw tw Trap Word (x’7C00 0008’) tw TO,rA,rB [POWER mnemonic: t] Reserved 31 0 TO 5 6 A B 10 11 15 16 4 20 21 0 30 31 a ← EXTS(rA[32–63]) b ← EXTS(rB[32–63]) if (a < b) & TO[0] then TRAP if (a > b) & TO[1] then TRAP if (a = b) & TO[2] then TRAP if (a U b) & TO[4] then TRAP The contents of the low-order 32 bits of rA are compared with the contents of the low-order 32 bits of rB. If any bit in the TO field is set and its corresponding condition is met by the result of the comparison, then the system trap handler is invoked. Other registers altered: • None Simplified mnemonics: tweq twlge trap rA,rB rA,rB PowerPC Architecture Level UISA Page 622 of 785 equivalent to equivalent to equivalent to tw tw tw Supervisor Level 4,rA,rB 5,rA,rB 31,0,0 32-Bit 64-Bit 64-Bit Bridge Optional Form X pem8b.fm.2.0 June 10, 2003 Programming Environments Manual PowerPC RISC Microprocessor Family twi twi Trap Word Immediate (x’0C00 0000’) twi TO,rA,SIMM [POWER mnemonic: ti] 03 0 TO 5 6 A SIMM 10 11 15 16 31 a ← EXTS(rA[32–63]) if (a < EXTS(SIMM)) & TO[0] then TRAP if (a > EXTS(SIMM)) & TO[1] then TRAP if (a = EXTS(SIMM)) & TO[2] then TRAP if (a U EXTS(SIMM)) & TO[4] then TRAP The contents of the low-order 32 bits of rA are compared with the sign-extended value of the SIMM field. If any bit in the TO field is set and its corresponding condition is met by the result of the comparison, then the system trap handler is invoked. Other registers altered: • None Simplified mnemonics: twgti twllei rA,value rA,value PowerPC Architecture Level UISA pem8b.fm.2.0 June 10, 2003 equivalent to equivalent to twi twi Supervisor Level 8,rA,value 6,rA,value 32-Bit 64-Bit 64-Bit Bridge Optional Form D Page 623 of 785 Programming Environments Manual PowerPC RISC Microprocessor Family xorx xorx XOR (x’7C00 0278’) xor xor. rA,rS,rB rA,rS,rB 31 0 S 5 rA ← (rS) 6 (Rc = 0) (Rc = 1) A 10 11 B 15 16 316 20 21 Rc 30 31 ⊕ (rB) The contents of rS is XORed with the contents of rB and the result is placed into rA. Other registers altered: • Condition Register (CR0 field): Affected: LT, GT, EQ, SO(if Rc = 1) PowerPC Architecture Level UISA Page 624 of 785 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form X pem8b.fm.2.0 June 10, 2003 Programming Environments Manual PowerPC RISC Microprocessor Family xori xori XOR Immediate (x’6800 0000’) xori rA,rS,UIMM [POWER mnemonic: xoril] 26 0 S 5 rA ← (rS) 6 A 10 11 UIMM 15 16 31 ⊕ ((4816)0 || UIMM) The contents of rS are XORed with 0x0000_0000_0000 || UIMM and the result is placed into rA. Other registers altered: • None PowerPC Architecture Level UISA pem8b.fm.2.0 June 10, 2003 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form D Page 625 of 785 Programming Environments Manual PowerPC RISC Microprocessor Family xoris xoris XOR Immediate Shifted (x’6C00 0000’) xoris rA,rS,UIMM [POWER mnemonic: xoriu] 27 0 S 5 rA ← (rS) 6 A 10 11 UIMM 15 16 31 ⊕ ((32)0 || UIMM || (16)0) The contents of rS are XORed with 0x0000_0000 || UIMM || 0x0000 and the result is placed into rA. Other registers altered: • None PowerPC Architecture Level UISA Page 626 of 785 Supervisor Level 32-Bit 64-Bit 64-Bit Bridge Optional Form D pem8b.fm.2.0 June 10, 2003
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