Jetson TX2 OEM Product Design Guide
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OEM PRODUCT DESIGN GUIDE NVIDIA Jetson TX2 Abstract This document contains recommendations and guidelines for Engineers to follow to create a product that is optimized to achieve the best performance from the common interfaces supported by the NVIDIA® Jetson™ TX2 System-onModule (SOM). Note: Jetson TX2 utilizes Tegra X2 which is a Parker series SoC. JETSON TX2 OEM PRODUCT | DESIGN GUIDE | 20170912 1 NVIDIA Jetson TX2 OEM Product Design Guide Document Change History Date Description MAY, 2017 Initial Release SEP, 2017 Power Added pull-up mention for CARRIER_PWR_ON and updated for RESET_OUT# & SLEEP# in Power & - System Pin Descriptions (Table 5 & Table 90 in Appendix) Updated Power Block diagram to show pull-ups on CARRIER_PWR_ON, POWER_BTN# & SLEEP# and added Auto-power-on block & pull-up for CHARGER_PRSNT# Added Deep Sleep (SC7) sequence USB 3.0 Added Electrical Spec section Updated impedance Added Trace Spacing for TX/RX non-interleaving section PCIe Removed note under routing guidelines table related to max trace length as this was intended for chi-down designs, not module based designs. PCIe/SATA/HDMI Removed min spacing between turn requirement from Serpentine section DSI/CSI guidelines Updated max frequency to include separate max speeds for DSI & CSI Updated reference plane Updated breakout impedance Updated main impedance Updated max trace delay to include different lengths for 1.0, 1.5 & 2.5 Gbps HDMI Added pre HDMI 1.4b max length/delay requirements I2C Updated notes under I2C signal Connections table to use E_IO_HV, not E_OD_HV. UART Updated UART Connections figure to add strapping information and added caution note below figure Debug Removed external pull-up on JTAG_GP0 (JTAG_TRST_N) Strapping Updated figure, table & notes to remove mention of RAM_CODE[3:2] straps. Pads Updated Schmitt Trigger Usage section to add caution when considering changing settings Checklist Corrected on-module termination for CHARGER_PRSNT# & added RESET_OUT# Added check for using pins associated with Tegra straps JETSON TX2 OEM PRODUCT | DESIGN GUIDE | 20170912 2 NVIDIA Jetson TX2 OEM Product Design Guide Table of Contents 1.0 INTRODUCTION ....................................................................................................................................................................5 1.1 References.......................................................................................................................................................................5 1.2 Abbreviations and Definitions .......................................................................................................................................5 2.0 JETSON TX2 ..........................................................................................................................................................................6 2.1 Overview ..........................................................................................................................................................................6 3.0 POWER ..................................................................................................................................................................................8 3.1 Supply Allocation ............................................................................................................................................................9 3.2 Main Power Sources/Supplies .....................................................................................................................................10 3.3 Power Sequencing ........................................................................................................................................................10 3.4 Power Discharge ...........................................................................................................................................................13 3.5 Power & Voltage Monitoring ........................................................................................................................................14 3.6 Deep Sleep (SC7) ..........................................................................................................................................................15 3.7 Optional Auto-Power-On Support................................................................................................................................16 4.0 GENERAL ROUTING GUIDELINES ....................................................................................................................................18 5.0 USB, PCIE & SATA .............................................................................................................................................................20 5.1 USB ................................................................................................................................................................................22 5.2 PCIe ................................................................................................................................................................................26 5.3 SATA ..............................................................................................................................................................................30 6.0 GIGABIT ETHERNET ..........................................................................................................................................................33 7.0 DISPLAY ..............................................................................................................................................................................35 7.1 MIPI DSI..........................................................................................................................................................................35 7.2 eDP / DP / HDMI .............................................................................................................................................................38 8.0 MIPI CSI (VIDEO INPUT) .....................................................................................................................................................48 9.0 SDIO/SDCARD/EMMC .........................................................................................................................................................52 9.1 SD Card ..........................................................................................................................................................................52 10.0 AUDIO ................................................................................................................................................................................55 11.0 WLAN / BT (INTEGRATED)...............................................................................................................................................57 12.0 MISCELLANEOUS INTERFACES .....................................................................................................................................58 12.1 I2C ................................................................................................................................................................................58 12.2 SPI ................................................................................................................................................................................60 12.3 UART ............................................................................................................................................................................62 12.4 Fan................................................................................................................................................................................63 12.5 CAN ..............................................................................................................................................................................64 12.6 Debug ...........................................................................................................................................................................66 12.7 Strapping Pins .............................................................................................................................................................68 13.0 PADS ..................................................................................................................................................................................70 13.1 MPIO Pad Behavior when Associated Power Rail is Enabled .................................................................................70 13.2 Internal Pull-ups for CZ Type Pins at Power-on .......................................................................................................70 13.3 Schmitt Trigger Usage ................................................................................................................................................70 13.4 Pins Pulled/Driven High During Power-on ................................................................................................................70 13.5 Pad Drive Strength ......................................................................................................................................................71 14.0 UNUSED INTERFACE TERMINATIONS ...........................................................................................................................72 JETSON TX2 OEM PRODUCT | DESIGN GUIDE | 20170912 3 NVIDIA Jetson TX2 OEM Product Design Guide 14.1 Unused MPIO Interfaces .............................................................................................................................................72 14.2 Unused SFIO Interface Pins .......................................................................................................................................72 15.0 DESIGN CHECKLIST ........................................................................................................................................................73 16.0 APPENDIX A: GENERAL LAYOUT GUIDELINES ...........................................................................................................81 16.1 Overview ......................................................................................................................................................................81 16.2 Via Guidelines .............................................................................................................................................................81 16.3 Connecting Vias ..........................................................................................................................................................82 16.4 Trace Guidelines .........................................................................................................................................................82 17.0 APPENDIX B: STACK-UPS ..............................................................................................................................................84 17.1 Reference Design Stack-Ups .....................................................................................................................................84 18.0 APPENDIX C: TRANSMISSION LINE PRIMER ................................................................................................................85 18.1 Background .................................................................................................................................................................85 18.2 Physical Transmission Line Types ...........................................................................................................................85 18.3 Driver Characteristics .................................................................................................................................................86 18.4 Receiver Characteristics ............................................................................................................................................86 18.5 Transmission Lines & Reference Planes ..................................................................................................................86 19.0 APPENDIX D: DESIGN GUIDELINE GLOSSARY ...........................................................................................................89 20.0 APPENDIX E: JETSON TX2 PIN DESCRIPTIONS ..........................................................................................................90 JETSON TX2 OEM PRODUCT | DESIGN GUIDE | 20170912 4 NVIDIA Jetson TX2 OEM Product Design Guide 1.0 INTRODUCTION 1.1 References Refer to the documents or models listed in Table 1 for more information. Use the latest revision of all documents at all times. Table 1. List of Related Documents Document Jetson TX2 Module Data Sheet Parker Series SoC Technical Reference Manual Jetson TX1/TX2 Developer Kit Carrier Board Specification Jetson TX2 Module Pinmux Jetson TX2 Thermal Design Guide Jetson TX1/TX2 Developer Kit Carrier Board Design Files Jetson TX1/TX2 Developer Kit Carrier Board BOM Jetson TX1/TX2 Developer Kit Camera Module Design Files Jetson TX1/TX2 Supported Component List 1.2 Abbreviations and Definitions Table 2 lists abbreviations that may be used throughout this document and their definitions. Table 2. Abbreviations and Definitions Abbreviation BT CEC CAN DP eDP eMMC GPS HDMI I2C I2S LCD LDO LPDDR4 PCIe (PEX) PCM PHY PMC PMIC RF RTC SATA SDIO SPI UART USB WLAN Definition Bluetooth Consumer Electronic Control Controller Area Network Display Port Embedded Display Port Embedded MMC Global Positioning System High Definition Multimedia Interface Inter IC Inter IC Sound Interface Liquid Crystal Display Low Dropout (voltage regulator) Low Power Double Data Rate DRAM, Fourth-generation Peripheral Component Interconnect Express interface Pulse Code Modulation Physical Interface (i.e. USB PHY) Power Management Controller Power Management IC Radio Frequency Real Time Clock Serial “AT” Attachment interface Secure Digital I/O Interface Serial Peripheral Interface Universal Asynchronous Receiver-Transmitter Universal Serial Bus Wireless Local Area Network JETSON TX2 OEM PRODUCT | DESIGN GUIDE | 20170912 5 NVIDIA Jetson TX2 OEM Product Design Guide 2.0 JETSON TX2 2.1 Overview The Jetson TX2 resides at the center of the embedded system solution and includes: 1. 3. 5. 7. Power (PMIC/Regulators, etc.) DRAM (LPDDR4) eMMC Connects to WLAN and Bluetooth enabled devices 2. 4. 6. Ethernet PHY Power & Voltage Monitors Thermal Sensor In addition, a range of interfaces are available at the main connector for use on the carrier board as shown in the following table. Table 3. Jetson TX2 Interfaces Catagory USB PCIe SATA Camera Display Audio SD Card LAN Note: Function Catagory Function USB 2.0 (3x) USB 3.0 (up to 3x) see note Control [x3] (shared Wake) PCIe (3 root ports - See note) SATA & Device Sleep control CSI (6 x2 or 3 x4), Control, Clock 2x eDP/DP/HDMI DSI (2 x4), Display/Backlight Control I2S (4x), Control & Clock Digital Mic & Speaker SD Card or SDIO Gigabit Ethernet CAN I2C UART SPI WLAN/BT/Modem Touch Sensor Fan Debug System Power 2x 8x 5x 3x PEX/UART/I2S, Control/handshake Touch Clock, Interrupt & Reset Control & Interrupt FAN PWM & Tach Input JTAG, UART Power Control, Reset, Alerts Main Input Some USB 3.0 or PCIe instances are shared. Refer to Chapter 5.0 USB, PCIe & SATA for details. Table 4. Jetson TX2 Connector (8x50) Pin Out Matrix 1 2 3 4 5 6 7 A VDD_IN VDD_IN GND GND RSVD I2C_PM_CLK CHARGING# 8 GPIO14_AP_WAKE_MDM B VDD_IN VDD_IN GND GND RSVD I2C_PM_DAT CARRIER_STBY# C VDD_IN VDD_IN GND GND RSVD I2C_CAM_CLK BATLOW# GPIO1_CAM1_PWR# GPIO4_CAM_STROBE H I2S0_LRCLK I2S0_SDOUT GPIO20_AUD_INT DSPK_OUT_DAT I2S2_LRCLK I2S2_SDOUT GPIO3_CAM1_RST# VIN_PWR_BAD# GPIO15_AP2MDM_ GPIO17_MDM2AP_ 9 READY READY GPIO16_MDM_ GPIO18_MDM_COL 10 WAKE_AP DBOOT 11 JTAG_GP1 JTAG_TCK BATT_OC UART7_TX CAM_VSYNC CAM1_MCLK GPIO0_CAM0_PWR# GPIO2_CAM0_RST# WDT_TIME_OUT# UART1_TX UART1_RTS# CAM0_MCLK UART3_CTS# UART3_RX I2C_GP2_DAT UART1_RX UART1_CTS# UART3_RTS# UART3_TX I2C_GP2_CLK RSVD RSVD GND RSVD UART0_RTS# UART0_CTS# 12 JTAG_TMS JTAG_TDI I2C_GP3_CLK RSVD RSVD RSVD UART0_RX UART0_TX 13 JTAG_TDO JTAG_GP0 I2C_GP3_DAT I2S1_LRCLK RSVD SPI1_MOSI SPI1_CLK GPIO8_ALS_PROX_INT 14 JTAG_RTCK I2S1_SDIN I2S1_SDOUT SPI1_CS0# SPI1_MISO GPIO9_MOTION_INT SPI2_CLK 15 UART2_CTS# GND UART2_RX I2S1_CLK I2C_GP0_DAT I2C_GP0_CLK SPI2_MOSI SPI2_MISO 16 UART2_RTS# UART2_TX FAN_PWM AO_DMIC_IN_DAT AO_DMIC_IN_CLK GND SPI2_CS1# SPI2_CS0# SDCARD_PWR_EN 17 USB0_EN_OC# FAN_TACH CAN1_STBY CAN1_RX RSVD SDCARD_CD# SDCARD_D1 18 USB1_EN_OC# RSVD CAN1_TX CAN0_RX CAN0_ERR SDCARD_D3 GND SDCARD_CLK 19 RSVD GPIO11_AP_WAKE_BT CAN1_ERR CAN0_TX SDCARD_D2 SDCARD_CMD 20 I2C_GP1_DAT 21 I2C_GP1_CLK GPIO10_WIFI_WAKE_AP CAN_WAKE GND CSI5_CLK- GND CSI5_D1- SDCARD_WP GND CSI4_D1- CSI5_D1+ 22 GPIO_EXP1_INT 23 GPIO_EXP0_INT 24 LCD1_BKLT_PWM GPIO13_BT_WAKE_AP GND CSI4_D0CSI4_D0+ GND GND CSI4_CLK- GPIO12_BT_EN GND CSI5_D0GPIO7_TOUCH_RST CSI5_D0+ TOUCH_CLK GND JETSON TX2 OEM PRODUCT | DESIGN GUIDE | 20170912 D E FORCE_RECOV# SLEEP# SPI0_CLK SPI0_MISO UART7_RX I2S3_SDIN I2C_CAM_DAT I2S3_CLK GPIO5_CAM_FLASH_EN CAM2_MCLK RSVD RSVD RSVD RSVD CSI5_CLK+ GND CSI3_CLK- GND CSI3_D1CSI3_D1+ F AUDIO_MCLK GPIO19_AUD_RST SPI0_CS0# SPI0_MOSI I2S3_LRCLK I2S3_SDOUT G I2S0_SDIN I2S0_CLK GND DSPK_OUT_CLK I2S2_CLK I2S2_SDIN CSI4_CLK+ GND CSI2_CLK- SDCARD_D0 CSI4_D1+ GND CSI2_D1CSI2_D1+ 6 NVIDIA Jetson TX2 OEM Product Design Guide 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 A LCD_TE GSYNC_HSYNC GSYNC_VSYNC GND SDIO_RST# RSVD RSVD RSVD DP1_HPD DP1_AUX_CHDP1_AUX_CH+ USB0_OTG_ID GND USB1_D+ USB1_D– GND PEX2_REFCLK+ PEX2_REFCLK– GND PEX0_REFCLK+ PEX0_REFCLK– RESET_OUT# RESET_IN# CARRIER_PWR_ON CHARGER_PRSNT# VDD_RTC Ground Legend Notes: B GPIO6_TOUCH_INT LCD_VDD_EN LCD0_BKLT_PWM LCD_BKLT_EN RSVD RSVD GND RSVD HDMI_CEC DP0_AUX_CHDP0_AUX_CH+ DP0_HPD USB0_VBUS_DET GND USB0_D+ USB0_DGND USB2_D+ USB2_DGND PEX1_REFCLK+ PEX1_REFCLKGND RSVD RSVD POWER_BTN# 1. 2. C CSI3_D0CSI3_D0+ GND CSI1_D0CSI1_D0+ GND DSI3_D0+ DSI3_D0GND DSI1_D0+ DSI1_D0GND DP1_TX1DP1_TX1+ GND PEX2_TX+ PEX2_TXGND USB_SS0_TX+ USB_SS0_TXGND PEX2_CLKREQ# PEX1_CLKREQ# PEX0_CLKREQ# PEX0_RST# RSVD Power D CSI3_CLK+ GND CSI1_CLKCSI1_CLK+ GND DSI3_CLK+ DSI3_CLK– GND DSI1_CLK+ DSI1_CLK– GND DP1_TX2DP1_TX2+ GND PEX_RFU_TX+ PEX_RFU_TXGND USB_SS1_TX+ USB_SS1_TXGND SATA_TX+ SATA_TXSATA_DEV_SLP PEX_WAKE# PEX2_RST# RSVD Not available on Jetson TX1 E GND CSI1_D1CSI1_D1+ GND DSI3_D1+ DSI3_D1GND DSI1_D1+ DSI1_D1GND DP1_TX3DP1_TX3+ GND DP1_TX0DP1_TX0+ GND PEX1_TX+ PEX1_TXGND PEX0_TX+ PEX0_TXGND GBE_LINK_ACT# GBE_MDI0+ GBE_MDI0PEX1_RST# Reserved F CSI2_D0CSI2_D0+ GND CSI0_D0CSI0_D0+ GND DSI2_D0+ DSI2_D0GND DSI0_D0+ DSI0_D0GND DP0_TX1DP0_TX1+ GND PEX2_RX+ PEX2_RXGND USB_SS0_RX+ USB_SS0_RXGND GBE_LINK1000# GBE_MDI1+ GBE_MDI1GND GBE_LINK100# G CSI2_CLK+ GND CSI0_CLKCSI0_CLK+ GND DSI2_CLK+ DSI2_CLKGND DSI0_CLK+ DSI0_CLKGND DP0_TX2DP0_TX2+ GND PEX_RFU_RX+ PEX_RFU_RXGND USB_SS1_RX+ USB_SS1_RXGND SATA_RX+ SATA_RXGND GBE_MDI2+ GBE_MDI2GND H GND CSI0_D1CSI0_D1+ GND DSI2_D1+ DSI2_D1GND DSI0_D1+ DSI0_D1GND DP0_TX3DP0_TX3+ GND DP0_TX0DP0_TX0+ GND PEX1_RX+ PEX1_RXGND PEX0_RX+ PEX0_RXGND GBE_MDI3+ GBE_MDI3GND RSVD Unassigned on carrier board RSVD (Reserved) pins on Jetson TX2 must be left unconnected. Signals starting with “GPIO_” are standard GPIOs that have been assigned recommended usage. If the assigned usage is required in a design it is recommended the matching GPIO be used. If the assigned usage is not required, the pins may be used as GPIOs for other purposes. JETSON TX2 OEM PRODUCT | DESIGN GUIDE | 20170912 7 NVIDIA Jetson TX2 OEM Product Design Guide 3.0 POWER Caution Jetson TX2 is not hot-pluggable. Before installing or removing the module, the main power supply (to VDD_IN pins) must be disconnected and adequate time (recommended > 1 minute) must be allowed for the various power rails to fully discharge. Table 5. Jetson TX2 Power & System Pin Descriptions Tegra Signal Usage/Description Usage on the Carrier Board Direction Pin Type − Main power – Supplies PMIC & external supplies Main DC input Input 5.5V-19.6V (PMIC_GPIO6) Battery Low (PMIC GPIO) Carrier Power On. Used as part of the power up sequence. The module asserts this signal when it is safe for the carrier board to power up. A 10kΩ pull-up to VDD_3V3_SYS is present on the module. Carrier Board Standby: The module drives this signal low when it is in the standby power state. System Charger Present. Connected on module to PMIC ACOK through FET & 4.7kΩ resistor. PMIC ACOK has 100kΩ pull-up internally to MBATT (VDD_5V0_SYS). Can optionally be used to support auto-power-on where the module platform will power-on when the main power source is connected instead of waiting for a power button press. Charger Interrupt Fan PWM Fan Fan Tachometer Force Recovery strap pin Power Button. Used to initiate a system power-on. Connected to PMIC EN0 which has internal 10KΩ Pull-up to VDD_5V0_SYS. Also connected to Tegra POWER_ON pin through Diode with 100kΩ pull-up to VDD_1V8_AP near Tegra. Reset In. System Reset driven from PMIC to carrier board for devices requiring full system reset. Also driven from carrier board to initiate full system reset (i.e. RESET button). A pull- System up is present on module. Reset Out. Reset from PMIC (through diodes) to Tegra & eMMC reset pins. Driven from carrier board to force reset of Tegra & eMMC (not PMIC). An external 100kΩ pull-up to Input CMOS – 1.8V Output Open-Collector – 3.3V Output CMOS – 1.8V Input MBATT level – 5.0V (see note 2) Input Output Input Input CMOS – 1.8V CMOS – 1.8V CMOS – 1.8V CMOS – 1.8V Input CMOS – 5.0V (see note 2) Bidir Open Drain, 1.8V Bidir CMOS – 1.8V Input CMOS – 1.8V (see note 2) Input CMOS – 5.0V Input CMOS – 1.8V Bidir 1.65V-5.5V Bidir CMOS – 1.8V Pin # Jetson TX2 Pin Name A1 A2 B1 B2 C1 C2 C7 VDD_IN VDD_IN VDD_IN VDD_IN VDD_IN VDD_IN BATLOW# A48 CARRIER_PWR_ON − B7 CARRIER_STBY# SOC_PWR_REQ A49 CHARGER_PRSNT# (PMIC ACOK) A7 C16 B17 E1 CHARGING# FAN_PWM FAN_TACH FORCE_RECOV# (PMIC GPIO5) GPIO_SEN6 UART5_TX GPIO_SW1 B50 POWER_BTN# POWER_ON / (PMIC EN0) A47 RESET_IN# (PMIC NRST_IO) A46 RESET_OUT# SYS_RESET_N E2 SLEEP# GPIO_SW2 B8 VIN_PWR_BAD# − C9 WDT_TIME_OUT# GPIO_SEN7 A50 VDD_RTC (PMIC BBATT) C8 BATT_OC BATT_OC Note: 1. 2. 1.8V near Tegra (module pin side) & external 10kΩ pull-up to 1.8V on the other side of a diode (PMIC side). Sleep Request to the module from the carrier board. An internal Tegra pull-up is present on the signal. VDD_IN Power Bad. Carrier board indication to the module that the VDD_IN power is not valid. Carrier board should deassert this (drive high) only when VDD_IN has reached its required voltage level and is stable. This prevents Tegra from powering up until the VDD_IN power is stable. Watchdog Timeout Real-Time-Clock. Optionally used to provide back-up power for RTC. Connects to Lithium Cell or super capacitor on Carrier Board. PMIC is supply when charging cap or coin cell. Super cap or coin cell is source when system is disconnected from power. Battery Over-current (& Thermal) warning Sleep (VOL DOWN) button System Battery Back-up using Supercapacitor Power efficiency is higher when the input voltage is lower, such as 9V or 12V. At very low voltages (close to the 5.5V minimum), the power supported by some of the supplies may be reduced. These pins are handled as Open-Drain on the carrier board. JETSON TX2 OEM PRODUCT | DESIGN GUIDE | 20170912 8 NVIDIA Jetson TX2 OEM Product Design Guide Figure 1. Power Block Diagram Jetson TX2 PU B8 From Carrier Board main power input & discharge circuit CARRIER_PWR_ ON A48 To Carrier Board power subsystem RESET_IN# A47 System Reset to/from Carrier Board RESET_O UT# A46 Tegra Force Reset from Carrier Board VIN_PWR_BAD# PU Power Subsystem DC Jack A1 A2 B1 B2 C1 C2 Super Cap or Li Cell (Optional) A50 PU VDD_IN 5V/3.3V Pre-Regs PMU Switchers/LDOs CPU/GPU Regs Ext. LDOs Load Switches PU PU VDD_RTC Tegra POWER PU POWE R_BTN# Optional Power Button B50 ACO K SLEEP PU SLEEP # PU Memory/Peripherals LPDDR4, eMMC, Ethernet, WiFi / BT Auto-poweron Circuit CARRIER_STBY # CHARGER_P RS NT# Optional Sleep Button E2 B7 To Carrier Board to disable devices/ rails to be off in sleep mode A49 Optional signal from Carrier Board to support Auto-Power-On 3.1 Supply Allocation Table 6 Jetson TX2 Internal Power Subsystem Allocation Power Rails VDD_5V0_SYS VDD_CPU VDD_GPU & VDD_SRAM VDD_SOC (CORE) VDD_DDR_1V1_PMIC AVDD_DSI_CSI_1V2 VDD_1V8 VDD_3V3_SYS VDDIO_3V3_AOHV VDDIO_SDMMC1_AP VDD_RTC (See note) VDDIO_SDMMC3_AP VDD_HDMI_1V05 VDD_PEX_1V05 VDD_1V8_AP (& VDD_1V8_AP_PLL) Note: Usage Supplies various switchers & load switches that power the various circuits & peripherals on Jetson TX2. Tegra MCPU/BCPU Tegra GPU & SRAM Tegra Core LPDDR4 Source for some DSI/CSI blocks Tegra, eMMC, WLAN Supplies various LDOs & load switches that in turn power the various circuits & peripherals on Jetson TX2. Tegra VDDIO_AO_HV rail Tegra SD Card I/O rail Tegra Real Time Clock/Always-on Rail Tegra SDIO rail Tegra HDMI / DP rail Tegra PCIe / USB 3.0 / SATA rail Main 1.8V Tegra rail (V) 5.0 Power Supply 5V DC-DC Source VDD_IN 1.0 (Var) 1.0 (Var) 1.0 (Var) 1.125 1.2 1.8 3.3 OpenVREG (uP1666QQKF) OpenVREG (uP1666QQKF) OpenVREG (uP1666QQKF) PMIC Switcher SD0 PMIC Switcher SD1 PMIC Switcher SD2 PMIC Switcher SD3 VDD_5V0_SYS VDD_5V0_SYS VDD_5V0_SYS VDD_5V0_SYS VDD_5V0_SYS VDD_5V0_SYS VDD_5V0_SYS 3.3 1.8/3.3 1.0 (Var) 1.8/3.3 1.0 1.0 1.8 PMIC LDO 2 PMIC LDO 3 PMIC LDO 4 PMIC LDO 5 PMIC LDO 7 PMIC LDO 8 Load Switch VDD_5V0_SYS VDD_5V0_SYS VDD_1V8 VDD_5V0_SYS AVDD_DSI_CSI_1V2 AVDD_DSI_CSI_1V2 VDD_1V8 This is the Tegra supply, and should not be confused with Jetson TX2 VDD_RTC pin which is the supply that connects to the PMIC BBATT pin to keep the Real-Time Clock powered. JETSON TX2 OEM PRODUCT | DESIGN GUIDE | 20170912 9 NVIDIA Jetson TX2 OEM Product Design Guide 3.2 Main Power Sources/Supplies The figure below shows the power connections used on the carrier board, including the DC Jack which connects to the 5.5V19.6V AC/DC adapter, and the main 5.0V, 3.3V and 1.8V supplies. Also shown are the power control signals that are used to enable these supplies, or are used to communicate power sequence information to Jetson TX2 or other circuitry on the carrier board (i.e. discharge circuits). Figure 2. Main Power Source/Supply Connections DC Jack VDD_19V_IN (5.5V-19.6V) S PWR G FET D G S FET D VIN_PWR_BAD# VDD_MOD To Jetson TX2 & Power Discharge Circuitry To Jetson TX2 VDD_IN U31 TPS53015 DC-DC From CARRIER_PWR_ON Jetson TX2 VIN SW EN PG VDD_5V0_IO_SYS Main Carrier Board 5V Supply 3V3_SYS_BUCK_EN U16 TPS53015 DC-DC VDD_3V3_SYS VIN SW EN PG Main Carrier Board 3.3V Supply L7 VDD_3V3_SYS_PG Main 3.3V Power Good – Routed to Power LED on Carrier board 1V8_IO_VREG_EN U9 From Main VDD_5V0_IO_SYS 5V supply VDD_1V8 APW8805 OpenVReg VIN SW L6 VCC EN/FS PGOOD 1V8_IO_PG RESET_OUT# Note Main Carrier Board 1.8V Supply Main 3.3V Power Good – Routed to Power LED on Carrier board To Jetson TX2 (RESET_OUT#) to keep Tegra in Reset until 1.8V rail Valid The figure above is a high-level representation of the connections involved. Refer to the Jetson TX1/TX2 carrier board reference design for details. 3.3 Power Sequencing In order to ensure reliable and consistent power up sequencing, the pins VIN_PWR_BAD#, CARRIER_PWR_ON, and RESET_OUT# on Jetson TX2 connector should be connected and used as described below: VIN_PWR_BAD# signal is generated by the Carrier Board and passed to Jetson TX2 to keep the Tegra processor powered off until the VDD_IN supply is stable and it is possible to power up any standby circuits on Jetson TX2. This signal prevents the Tegra processor from powering up prematurely before the Carrier Board has charged up its decoupling capacitors and power to Jetson TX2 is stable CARRIER_PWR_ON signal is generated by Jetson TX2 and passed to the Carrier Board to indicate that Jetson TX2 is powered up and that the power up sequence for the Carrier Board circuits can begin. RESET_OUT# is de-asserted by the Carrier Board after a period sufficient to allow the Carrier Board circuits to power up. JETSON TX2 OEM PRODUCT | DESIGN GUIDE | 20170912 10 NVIDIA Jetson TX2 OEM Product Design Guide Figure 3. Power Up Sequence 1 2 3 4 5 6 7 8 VDD_IN VIN_PWR_BAD# POWER_BTN# Jetson TX2 System Power (Main 1.8V rail most IF pins are associated with) CARRIER_PWR_ON Carrier Board VDD_1V8 (note 1) RESET_OUT# (note 2) Note: 1. 2. 3. The 1.8V supply on the carrier board associated with MPIO pins common to Jetson TX2 must not be enabled unless the Jetson TX2 main 1.8V rail is on. In addition, the carrier board should keep RESET_OUT# low until this 1.8V supply is valid. On the P2597, this is accomplished by connecting the VDD_1V8 supply PGOOD signal to RESET_OUT#. Inactive when both PMIC Reset is inactive (high) & VDD_1V8 PGOOD is active (high) During run time if any Jetson TX2 I/O rail is switched OFF or ON, the following sequences should be performed. Violating these sequences will result in extra in-rush current during the rail transition. OFF Sequence: The associated NO_IOPOWER bit in the PMC APBDEV_PMC_NO_IOPOWER_0 register must be enabled before the - I/O Rail is powered OFF ON Sequence. After an I/O Rail is powered ON, the associated NO_IOPOWER bit in the PMC APBDEV_PMC_NO_IOPOWER_0 register needs to be cleared to the “disable” state Table 7. Power Up Sequence Timing Relationships Timing t1-2 t2-3 t3-4 t4-5 t4-6 t5-6 t6-7 t6-8 Note: Parameter VDD_IN On to POWER_BTN# Pull-up (PMIC) active VDD_IN On to VIN_PWR_BAD# inactive VIN_PWR_BAD# inactive to POWER_BTN# active POWER_BTN# active time POWER_BTN# active to CARRIER_PWR_ON active Jetson TX2 System Power On to CARRIER_PWR_ON CARRIER_PWR_ON active to Carrier Board System Power Enabled CARRIER_PWR_ON to On-Module PMIC Reset Inactive RESET_IN# active time 1. 2. 3. 4. 5. 6. Min 0 50 0 50 Typ 8.8 54 See Notes 38.6 8 6.6 77.4 Max Units ms ms ms ms ms ms ms ms ms Notes 1 2 3 3 4 5 6 Measured from VDD_IN ramp start to POWER_BTN# ramp start. Carrier board dependent. Typical value using NVIDIA P2597, measured from VDD_IN ramp start to VIN_PWR_BAD# inactive start. Carrier board dependent. User Dependent if POWER_BTN# connected to button. Otherwise, carrier board dependent. Typical value measured using NVIDIA P2597. Carrier board dependent Typical value using P2597. Carrier board dependent. User Dependent if RESET_IN# connected to button. Otherwise, carrier board dependent. Not shown in Power up sequence figure. JETSON TX2 OEM PRODUCT | DESIGN GUIDE | 20170912 11 NVIDIA Jetson TX2 OEM Product Design Guide Figure 4. Power Down Sequence (Controlled Case) 1 2 3 4 5 6 7 8 9 RESET_OUT# CARRIER_PWR_ON Carrier Board System Power (1.8V used for pins shared w/Jetson TX2) Jetson TX2 System Power (Main 1.8V rail most IF pins are associated with) VIN_PWR_BAD# VDD_IN Table 8. Power Down Sequence Timing Relationships (Controlled Case) Table 9. Power Down Sequence Timing Relationships (Controlled Case) Timing t1-2 t2-3 t2-4 Note: Parameter RESET_OUT# active to CARRIER_PWR_ON inactive CARRIER_PWR_ON inactive to carrier board system power off CARRIER_PWR_ON inactive to Jetson TX2 System Power (main 1.8V rail) Off 1. 2. 3. Min Typ 3.76 0.46 1.24 Max Units mS ms mS Notes 1 2 3 Measured from RESET_OUT# active to CARRIER_PWR_ON to inactive ramp down start. Typical value measured using NVIDIA P2597. Measured from CARRIER_PWR_ON to carrier board VDD_1V8 ramp down start. Carrier board dependent. Typical value measured using NVIDIA P2597. Measured from CARRIER_PWR_ON ramp down start to Jetson TX2 main 1.8V ramp down start. Figure 5. Power Down Sequence (Uncontrolled Power Removal Case) 1 2 3 4 5 6 7 8 9 VDD_IN VIN_PWR_BAD# RESET_OUT# CARRIER_PWR_ON Carrier Board System Power Jetson TX2 System Power Table 10. Power Down Sequence Timing Relationships (Uncontrolled Power Removal Case) Timing t1 t2 Parameter VDD_IN Removed in uncontrolled manner VIN_PWR_BAD detection “sees” drop in VDD_IN & is asserted to start uncontrolled power-down sequence. RESET_OUT# & CARRIER_PWR_ON are driven low via PMIC sequence soon after. Carrier board power & Jetson TX2 power begin to ramp down. Min Typ Max Units Notes Carrier board power (mainly 1.8V rail associated with interface pins connected to Jetson TX2) should ramp down faster so it is off before the Jetson TX2 main 1.8V rail is off. Removal of the VDD_IN/VDD_MUX supply causes VIN_PWR_BAD# to go active which causes Jetson TX2 to initiate a controlled shut down. The controlled shut down takes ~20ms to complete so the internal PMIC supply needs to stay above ~2.9v for >~20ms. The USB0_OTG_ID pin is a pin which can be monitored to see the state of the internal PMIC supply level. JETSON TX2 OEM PRODUCT | DESIGN GUIDE | 20170912 12 NVIDIA Jetson TX2 OEM Product Design Guide Figure 6. VIN_PWR_BAD# Detection Test Circuit for Uncontrolled Power-down Case ~20% droop VDD_IN VIN_PWR_BAD# Voltage measured at USB0_OTG_ID pin 2.9V >20ms 3.4 Power Discharge In order to meet the Power Down requirements, discharge circuitry is required. In the figure below the DISCHARGE signal is generated, based on a transition of the CARRIER_POWER_ON signal or the removal of the main supply (VDD_MUX/VDD_IN). When DISCHARGE is asserted, VDD_5V0_IO_SYS, VDD_3V3_SYS, VDD_1V8 and VDD_3V3_SLP are forced to GND in a controlled manner. Removal of the VDD_MUX supply also causes VIN_PWR_BAD# to go active which causes Jetson TX2 to initiate a controlled shut down. Figure 7. Power Discharge VDD_5V0_IO_SYS VIN_PWR_BAD# (Jetson TX2 Pin B8) 100Ω VDD_MUX D 10kΩ C MMBT 4403 NTR4003 NT1G G VDD_3V3_SYS 47Ω S D 10MΩ 0Ω E B 0.05Ω Tol. 10kΩ BAT54ALT1 10uF 10uF D NTR4001 NT1G G NTR4003 NT1G G S D DISCHARGE VDD_MUX NTR4003 NT1G NTR4003 NT1G G VDD_5V0_IO_SYS VDD_3V3_SLP 47Ω S D VDD_12V_SLP D 470Ω G 470Ω S S D 75kΩ CARRIER_PWR_ON (Jetson TX2 pin A48) NTR4003 NT1G G 100kΩ,1% 1uF 47kΩ 100kΩ,1% 100kΩ,1% BAT54CW 4.7uF VDD_1V8 36Ω S BAT54CW NTR4003 NT1G G VDD_5V0_IO_SLP 100Ω S FDV301N D VDD_3V3_SLP G S JETSON TX2 OEM PRODUCT | DESIGN GUIDE | 20170912 D NTR4003 NT1G G S 13 NVIDIA Jetson TX2 OEM Product Design Guide 3.5 Power & Voltage Monitoring 3.5.1 Power Monitor Power monitors are provided on Jetson TX2. These monitor the main DC, CPU, GPU/SRAM, SOC (CORE) & DDR Supplies. The monitors will toggle a WARN (warning) output, or a CRIT (critical) output, depending on the power “seen” at the sense resistors and the thresholds set for each supply. Figure 8. Power Monitor (GPU/SRAM, SOC & WLAN) INA3221AIRGVR Power Monitor VDD_3V3_SYS GPU Supply Monitor 1uF VS GEN1_I2C (PU to 3.3V) GPU_INA_P VIN1P 0.1uF GEN1_I2C_SCL GEN1_I2C_SDA 10Ω VIN1N SCL SDA AO VIN2P PV TC VPU VIN2N GND PAD VIN3P 10Ω GPU_INA_M 10Ω SOC_INA_P SOC Supply Monitor 1uF 10Ω SOC_INA_M 10Ω WIFI_INA_P 10Ω WIFI_INA_M Wi-Fi Supply Monitor 1uF VIN3N Sense Resistors VDD_IN 0.01Ω, 1% 0805 VDD_SYS_GPU_IN (GPU supply input) VDD_IN 0.01Ω, 1% 0805 VDD_SYS_SOC_IN (SOC supply input) VDD_5V0_SYS 0.01Ω, 1% 0603 VDD_3V8_WIFI_SENSE VDD_1V8 100kΩ WARN INA_WIFI_THERM_WARN_L CRIT Tegra GPIO_MDM6 Figure 9. Power Monitor (VDD_IN, CPU & DDR) INA3221AIRGVR Power Monitor VDD_3V3_SYS VDD_IN Supply Monitor 1uF VS GEN1_I2C_SCL GEN1_I2C_SDA VDD_IN_SENSE VIN1P 0.1uF GEN1_I2C (PU to 3.3V) 10Ω 10Ω VIN1N SCL SDA AO 10Ω VIN2P VIN2N GND PAD VIN3P 10Ω CPU_INA_M 10Ω SRAM_INA_P DDR Supply Monitor 1uF VIN3N 10Ω SRAM_INA_M VDD_IN_RS 0.02Ω, 1% 3012 VDD_IN CPU_INA_P CPU Supply Monitor 1uF PV TC VPU VDD_IN_PREREG_SENSE Sense Resistors VDD_IN 0.01Ω, 1% 0805 VDD_SYS_CPU_IN (CPU supply input) VDD_5V0_SYS 0.01Ω, 1% 0603 VDD_5V0_SD0 (DDR supply input) VDD_1V8 WARN CRIT 100kΩ INA_PREREG_THERM_WARN_L Tegra BATT_OC 3.5.2 Voltage Monitor A voltage monitor circuit is implemented on Jetson TX2 to indicate if the main DC input rail, VDD_IN, “droops” below an acceptable level. The device used will react quickly and generate an alert to one of the Tegra SOC_THERM capable pins (VCOMP_ALERT). The voltage monitor circuit is implemented with a fast voltage comparator supplied by VDD_IN with a 1.8V (VDD_1V8) reference common with the Tegra IO domain that receives the output signal. This device has an open drain active low output which is pulled low when the VDD_IN voltage drops below the selected threshold. JETSON TX2 OEM PRODUCT | DESIGN GUIDE | 20170912 14 NVIDIA Jetson TX2 OEM Product Design Guide Figure 10. Voltage Monitor Connections VDD_5V0_SYS 1.8V 100kΩ VDD_IN VDD_1V8 Note: 110kΩ,1% IN_POS 49.9kΩ, 1% IN_NEG + – VCC VOUT COMP_SOC_THERM* (Tegra VCOMP_ALERT) VEE 34kΩ,1% The threshold for VDD_IN, determined by the voltage divider components used in the circuit above is 5.75V. 3.6 Deep Sleep (SC7) Jetson TX2 supports a low power state called Deep Sleep or SC7. This can be entered under software control, and exited using various mechanisms, including wake capable pins that are listed in the table below. Table 11. Jetson TX2 Signal Wake Events Potential Wake Event (Reference Design Signal) PCIe Wake Request (PEX_WAKE#) Bluetooth Wake AP (BT2_WAKE_AP – Secondary) WLAN Wake AP (WIFI_WAKE_AP - Secondary) Thermal/Over-current Warning Audio Codec Interrupt (AUD_INT_L) DP 0 Hot Plug Detect (DP_AUX_CH0_HPD) HDMI Consumer Electronic Control (HDMI_CEC) DP 1 Hot Plug Detect (DP_AUX_CH1_HPD) Camera Vertical Sync (CAM_VSYNC) POWER_BTN# Motion Interrupt (MOTION_INT) CAN 1 Error (CAN1_ERR) CAN Wake (CAN_WAKE) CAN 0 Error (CAN0_ERR) Touch Interrupt (TOUCH_INT) USB VBUS Detect (USB_VBUS_DET) GPIO Expansion 0 Interrupt (GPIO_EXP0_INT) Modem Wake AP (MDM_WAKE_AP) Battery Low (BATLOW#) GPIO Expansion 1 Interrupt (GPIO_EXP1_INT) USB Vbus Enable 0 (USB_VBUS_EN0) USB Vbus Enable 1 (USB_VBUS_EN1) Ambient Light Proximity Interrupt (ALS_PROX_INT) Modem Coldboot (MDM_COLDBOOT) Force Recovery (FORCE_RECOV#) Sleep (SLEEP_L) JETSON TX2 OEM PRODUCT | DESIGN GUIDE | 20170912 Jetson TX2 Pin Assigned PEX_WAKE# GPIO13_BT_WAKE_AP GPIO10_WIFI_WAKE_AP BATT_OC GPIO20_AUD_INT DP0_HPD HDMI_CEC DP1_HPD CAM_VSYNC POWER_BTN# GPIO9_MOTION_INT CAN1_ERR CAN_WAKE CAN0_ERR GPIO6_TOUCH_INT USB0_VBUS_DET GPIO_EXP0_INT GPIO16_MDM_WAKE_AP BATLOW# GPIO_EXP1_INT USB_VBUS_EN0 USB_VBUS_EN1 GPIO8_ALS_PROX_INT GPIO18_MDM_COLDBOOT FORCE_RECOV# SLEEP# Wake # 1 8 9 10 12 19 20 21 23 29 46 47 48 49 51 53 54 55 56 58 61 62 63 64 67 68 15 NVIDIA Jetson TX2 OEM Product Design Guide Figure 11. Deep Sleep (SC7) Entry/Exit Sequence SC7 Entry SC7 Exit SC7 Entry/Exit Trigger VDD_IN VIN_PWR_BAD# CARRIER_PWR_ON Carrier Board VDD_1V8 RESET_OUT# CARRIER_STBY# (Tegra X2 SOC_PWR_REQ) VDD_3V3_SLP VDD_5V0_SLP VDD_12V_SLP VDD_5V0_HDMI_CON 3.7 Optional Auto-Power-On Support Jetson TX2 includes circuitry on the module to support Auto-Power-On. This allows the platform to power on when VDD_IN is first powered, instead of waiting for a power button press. In order to enable this feature, the CHARGER_PRSNT# pin should be tied to GND. This section provides guidance for modifying a carrier board design to power the platform on when VDD_IN is first powered, instead of waiting for a power button press. In order to power the system on without a power button, a specific sequence is required between the time the VDD_IN power (5.5V-19.6V) is connected and the CHARGER_PRSNT# pin on Jetson TX2 is driven low. The CHARGER_PRSNT# pin connects to the Jetson TX2 PMIC and requires a minimum delay of 300ms from the point VDD_IN reaches its minimum level (5.5V) before it can be driven low. Four options to meet this requirement and allow Auto-Power-On are described: ▪ ▪ ▪ ▪ Built-in Auto-Power-On circuit: Not available on Jetson TX1. Microcontroller: Recommended if a microcontroller is already being used to control power-on. Supervisor IC: Using a supervisor IC and related discrete devices to meet the sequencing requirements. Discrete Circuit: Circuit using only discrete devices to meet the sequencing requirements Built-in Auto-Power-On circuit Jetson TX2 includes circuitry on the module to support Auto-Power-On. In order to enable this feature, the CHARGER_PRSNT# pin should be tied to GND. This option is not compatible with Jetson TX1 which does not have this circuitry. Microcontroller If a microcontroller is already present on the carrier board and is used to power the system on when the main power source is connected, then it can be used to support Auto-Power-On with the following conditions: ▪ ▪ ▪ After the microcontroller is out of reset wait 300ms before driving CHARGER_PRSNT# low or pulsing POWER_BTN# low If the POWER_BTN# pin is used, it should be held low for a time period between 50ms & 5sec. If the CHARGER_PRSNT# pin is used, it should be held low for >200us JETSON TX2 OEM PRODUCT | DESIGN GUIDE | 20170912 16 NVIDIA Jetson TX2 OEM Product Design Guide Supervisor IC 90.9kΩ,1% The figure below shows a circuit that includes a supervisor IC. This circuit meets the sequence requirement to leave CHARGER_PRSNT# floating until VDD_IN is on plus the delay mentioned above (>300ms) then driving the signal low. The circuit works across the full range of VDD_IN (5.5V to 19.6V). Supervisor MAX16053AUT VIN_PWR_BAD# IN GND OUT EN 2N7002W SOT323 G CDELAY 22nF 0.1uF CHARGER_PRSNT# D 10nF 100kΩ,1% 0.1uF VCC 10kΩ,1% 5.5V-19.6V Input Supply S Discrete Circuit The figure below shows a circuit using only discrete components. This circuit also meets the sequence requirement to keep CHARGER_PRSNT# floating until VDD_IN is on plus the delay mentioned above (>300ms) before driving it low. The circuit assumes the VDD_IN ramp slew rate is faster than 7 V/S. In order to meet the full supported range for VDD_IN (5.5V to 19.6V), the turn-on delay can be as long as 4sec. For a narrower VDD_IN range, the delay can be optimized (reduced). 5.5V-19.6V Input Supply 10kΩ NTS4001 NT1G SOT323 4.7uF D 4.7uF G NTS4001 NT1G SOT323 JETSON TX2 OEM PRODUCT | DESIGN GUIDE | 20170912 CHARGER_PRSNT# G S RB521S30 T1G, 30V SOD523 470kΩ RB521S30 T1G, 30V SOD523 470kΩ S D 17 NVIDIA Jetson TX2 OEM Product Design Guide 4.0 GENERAL ROUTING GUIDELINES Signal Name Conventions The following conventions are used in describing the signals for Jetson TX2: ▪ ▪ Signal names use a mnemonic to represent the function of the signal. For example, Secure Digital Interface #3 Command signal is represented as SDCARD_CMD, written in bold to distinguish it from other text. All active low signals are identified by a # or an underscore followed by capital N (_N) after the signal name. For example, RESET_IN# indicates an active low signal. Active high signals do not have the underscore-N (_N) after the signal names. For example, SDCARD_CMD indicates an active high signal. Differential signals are identified as a pair with the same names that end with _P & _N, just P & N or + & - (for positive and negative, respectively). For example, USB1_DP and USB1_DN indicate a differential signal pair. I/O Type The signal I/O type is represented as a code to indicate the operational characteristics of the signal. The table below lists the I/O codes used in the signal description tables. Table 12. Signal Type Codes Code A DIFF I/O DIFF IN DIFF OUT I/O I O OD I/OD P Definition Analog Bidirectional Differential Input/Output Differential Input Differential Output Bidirectional Input/Output Input Output Open Drain Output Bidirectional Input / Open Drain Output Power Routing Guideline Format The routing guidelines have the following format to specify how a signal should be routed. ▪ ▪ ▪ Breakout traces are traces routed from a BGA or other pin array, either to a point beyond the array, or to another layer where full normal spacing guidelines can be met. Breakout trace delay limited to 500 mils unless otherwise specified. After breakout, signal should be routed according to specified impedance for differential, single-ended, or both (for example: HDMI). Trace spacing to other signals also specified. Follow max & min trace delays where specified. Trace delays are typically shown in mm or in terms of signal delay in pico-seconds (ps) or both. For differential signals, trace spacing to other signals must be larger of specified × dielectric height or interpair spacing Spacing to other signals/pairs cannot be smaller than spacing between complementary signals (intra-pair). Total trace delay depends on signal velocity which is different between outer (microstrip) & inner (stripline) layers of a PCB. JETSON TX2 OEM PRODUCT | DESIGN GUIDE | 20170912 18 NVIDIA Jetson TX2 OEM Product Design Guide Signal Routing Conventions Throughout this document, the following signal routing conventions are used: SE Impedance (/ Diff Impedance) at x Dielectric Height Spacing ▪ Note: Single-ended (SE) impedance of trace (along with differential impedance for diff pairs) is achieved by spacing requirement. Spacing is multiple of dielectric height. Dielectric height is typically different for microstrip & stripline. Note: 1 mil = 1/1000th of an inch. Trace spacing requirement applies to SE traces or differential pairs to other SE traces or differential pairs. It does not apply to traces making up a differential pair. For this case, spacing/trace widths are chosen to meet differential impedance requirement. General Routing Guidelines Pay close attention when routing high speed interfaces, such as HDMI/DP, USB 3.0, PCIe or DSI/CSI. Each of these interfaces has strict routing rules for the trace impedance, width, spacing, total delay, and delay/flight time matching. The following guidelines provide an overview of the routing guidelines and notations used in this document. ▪ ▪ ▪ Controlled Impedance Each interface has different trace impedance requirements & spacing to other traces. It is up to designer to calculate trace width & spacing required to achieve specified single-ended (SE) & differential (Diff) impedances. Unless otherwise noted, trace impedance values are ±15%. Max Trace Lengths/Delays Trace lengths/delays should include main PCB routing and any additional routing on a Flex/ secondary PCB segment connected to main PCB. The max length/delay should be from Jetson TX2 to the actual connector (i.e. USB, HDMI, SD Card, etc.) or device (i.e. onboard USB device, Display driver IC, camera imager IC, etc.) Trace Delay/Flight Time Matching Signal flight time is the time it takes for a signal to propagate from one end (driver) to other end (receiver). One way to get same flight time for signal within signal group is to match trace lengths within specified delay in the signal group. Total trace delay = Carrier PCB trace delay only. Do not exceed maximum trace delay specified. For six layers or more, it is recommended to match trace delays based on flight time of signals. For example, outer-layer signal velocity could be 150psi (ps/inch) & inner-layer 180psi. If one signal is routed 10 inches on outer layer & second signal is routed 10 inches in inner layer, difference in flight time between two signals will be 300ps! That is a big difference if required matching is 15ps (trace delay matching). To fix this, inner trace needs to be 1.7 inches shorter or outer trace needs to be 2 inches longer. In this design guide, terms such as intra-pair & inter-pair are used when describing differential pair delay. Intra-pair refers to matching traces within differential pair (for example, true to complement trace matching). Inter-pair matching refers to matching differential pairs average delays to other differential pairs average delays. General PCB Routing Guidelines For GSSG stack-up to minimize crosstalk, signal should be routed in such a way that they are not on top of each other in two routing layers (see diagram to right) G S S G Do not route other signals or power traces/areas directly under or over critical high-speed interface signals. Note: The requiements detailed in the Interface Signal Routing Requirements tables must be met for all interfaces implemented or proper operation cannot be guaranteed. JETSON TX2 OEM PRODUCT | DESIGN GUIDE | 20170912 19 NVIDIA Jetson TX2 OEM Product Design Guide 5.0 USB, PCIE & SATA The Jetson TX2 allows multiple USB 3.0 & PCIe interfaces, and a single SATA interface to be brought out on the module. In some cases, these interfaces are multiplexed on some of the module pins. The tables below show several ways to bring out as many of the USB 3.0 or PCIe interfaces as possible to meet different design requirements. The first table covers many of the combinations possible on designs built around Jetson TX2 only. The second table covers the combinations possible for both Jetson TX2 and previous/future pin compatible modules. Table 13. Jetson TX2 USB 2.0 Pin Descriptions Pin # Jetson TX2 Pin Name Tegra Signal Usage/Description B40 B39 A17 A36 B37 A39 A38 A18 B43 B42 USB0_D– USB0_D+ USB0_EN_OC# USB0_OTG_ID USB0_VBUS_DET USB1_D– USB1_D+ USB1_EN_OC# USB2_D– USB2_D+ USB0_DN USB0_DP USB_VBUS_EN0 (PMIC GPIO0) UART5_CTS USB1_DN USB1_DP USB_VBUS_EN1 USB2_DN USB2_DP USB 2.0 Port 0 Data– USB 2.0 Port 0 Data+ USB VBUS Enable/Overcurrent 0 USB 0 ID USB 0 VBUS Detect USB 2.0, Port 1 Data– USB 2.0, Port 1 Data+ USB VBUS Enable/Overcurrent 1 USB 2.0, Port 2 Data– USB 2.0, Port 2 Data+ Usage on Carrier Board USB 2.0 Micro AB USB 3.0 Type A M.2 Key E Direction Pin Type Bidir Bidir Bidir Input Input Bidir Bidir Bidir Bidir Bidir USB PHY Open Drain – 3.3V Analog USB VBUS, 5V USB PHY Open Drain – 3.3V USB PHY Table 14. Jetson TX2 USB 3.0, PCIe & SATA Pin Descriptions Pin # Jetson TX2 Pin Name Tegra Signal Usage/Description A44 PEX0_REFCLK+ PEX_CLK1P A45 PEX0_REFCLK– PEX_CLK1N C48 PEX0_CLKREQ# PEX_L0_CLKREQ_N C49 PEX0_RST# PEX_L0_RST_N H44 PEX0_RX+ PEX_RX4P H45 PEX0_RX– PEX_RX4N E44 PEX0_TX+ PEX_TX4P E45 PEX0_TX– PEX_TX4N G42 USB_SS1_RX+ PEX_RX2P G43 USB_SS1_RX– PEX_RX2N D42 USB_SS1_TX+ PEX_TX2P D43 USB_SS1_TX– PEX_TX2N PCIe 0 Reference Clock+ (PCIe IF #0) PCIe 0 Reference Clock – (PCIe IF #0) PCIe 0 Clock Request (PCIe IF #0) PCIe 0 Reset (PCIe IF #0) PCIe 0 Lane 0 Receive+ (PCIe IF #0) PCIe 0 Lane 0 Receive– (PCIe IF #0) PCIe 0 Lane 0 Transmit+ (PCIe IF #0) PCIe 0 Lane 0 Transmit– (PCIe IF #0) USB SS 1 Receive+ (USB 3.0 Port #2 or PCIe IF #0 Lane 1) USB SS 1 Receive– (USB 3.0 Port #2 or PCIe #0 Lane 1) USB SS 1 Transmit+ (USB 3.0 Port #2 or PCIe IF #0 Lane 1) USB SS 1 Transmit– (USB 3.0 Port #2 or PCIe #0 Lane 1) PCIe 2 Receive+ (PCIe IF #0 Lane 2 or PCIe IF #1 Lane 0) PCIe 2 Receive– (PCIe IF #0 Lane 2 or PCIe IF #1 Lane 0) PCIe 2 Transmit+ (PCIe IF #0 Lane 2 or PCIe IF #1 Lane 0) PCIe 2 Transmit– (PCIe IF #0 Lane 2 or PCIe IF #1 Lane 0) PCIe RFU Receive+ (PCIe IF #0 Lane 3 or USB 3.0 Port #1) PCIe RFU Receive– (PCIe IF #0 Lane 3 or USB 3.0 Port #1) PCIe RFU Transmit+ (PCIe IF #0 Lane 3 or USB 3.0 Port #1) PCIe RFU Transmit – (PCIe IF #0 Lane 3 or USB 3.0 Port #1) PCIe Wake F40 PEX2_RX+ PEX_RX3P F41 PEX2_RX– PEX_RX3N C40 PEX2_TX+ PEX_TX3P C41 PEX2_TX– PEX_TX3N G39 PEX_RFU_RX+ PEX_RX1P G40 PEX_RFU_RX– PEX_RX1N D39 PEX_RFU_TX+ PEX_TX1P D40 PEX_RFU_TX– PEX_TX1N D48 PEX_WAKE# PEX_WAKE_N JETSON TX2 OEM PRODUCT | DESIGN GUIDE | 20170912 Usage on the Carrier Board Direction Output Output Bidir Output Pin Type PCIe PHY Open Drain 3.3V, Pull-up on the module Input Input Output Output Input Input Output Output PCIe x4 Connector Input PCIe PHY, AC-Coupled on carrier board Input Output Output Input Input Output Output PCIe x4 conn & M.2 Input Open Drain 3.3V, Pull-up on the module 20 NVIDIA Jetson TX2 OEM Product Design Guide Usage on the Carrier Board Pin # Jetson TX2 Pin Name Tegra Signal Usage/Description B45 PEX1_REFCLK+ PEX_CLK3P B46 PEX1_REFCLK– PEX_CLK3N C47 PEX1_CLKREQ# PEX_L2_CLKREQ_N E50 PEX1_RST# PEX_L2_RST_N H41 PEX1_RX+ PEX_RX0P H42 PEX1_RX– PEX_RX0N E41 PEX1_TX+ PEX_TX0P E42 PEX1_TX– PEX_TX0N A41 PEX2_REFCLK+ PEX_CLK2P A42 PEX2_REFCLK– PEX_CLK2N C46 PEX2_CLKREQ# PEX_L1_CLKREQ_N D49 PEX2_RST# PEX_L1_RST_N F43 USB_SS0_RX+ PEX_RX0P F44 USB_SS0_RX– PEX_RX0N PCIe Reference Clock 1+ (PCIe IF #2) PCIe Reference Clock 1– (PCIe IF #2) PCIE 1 Clock Request (mux option - PCIe IF #2) PCIe 1 Reset (PCIe IF #2) PCIe 1 Receive+ (PCIe #2 Lane 0 muxed w/USB 3.0 Port #0) PCIe 1 Receive– (PCIe #2 Lane 0 muxed w/USB 3.0 Port #0) PCIe 1 Transmit+ (PCIe #2 Lane 0 muxed w/USB 3.0 Port #0) PCIe 1 Transmit– (PCIe #2 Lane 0 muxed w/USB 3.0 Port #0) PCIe 2 Reference Clock+ (PCIe IF #1) PCIe 2 Reference Clock– (PCIe IF #1) PCIE 2 Clock Request (PCIe IF #1) PCIe 2 Reset (PCIe IF #1) USB SS 0 Receive+ (USB 3.0 Port #0 muxed w/PCIe #2 Lane 0) USB SS 0 Receive– (USB 3.0 Port #0 muxed w/PCIe #2 Lane 0) USB SS 0 Transmit+ (USB 3.0 Port #0 muxed w/PCIe #2 Lane 0) USB SS 0 Transmit– (USB 3.0 Port #0 muxed w/PCIe #2 Lane 0) SATA Receive+ SATA Receive– SATA Transmit+ SATA Transmit– SATA Device Sleep or PEX1_CLKREQ# (PCIe IF #2) depending on Mux setting C43 USB_SS0_TX+ PEX_TX0P C44 USB_SS0_TX– PEX_TX0N G45 SATA_RX+ PEX_RX5P G46 SATA_RX– PEX_RX5N D45 SATA_TX+ PEX_TX5P D46 SATA_TX– PEX_TX5N D47 SATA_DEV_SLP PEX_L2_CLKREQ_N Direction Pin Type Output PCIe PHY Output M.2 Key E Bidir Output Open Drain 3.3V, Pull-up on the module Input USB 3.0 Type A (Default) or M.2 Key E Input Output PCIe PHY, AC-Coupled on carrier board Output Output PCIe PHY Output Unassigned Bidir Output Open Drain 3.3V, Pull-up on the module Input USB SS PHY, AC-Coupled (off the module) Input USB 3.0 Type A Output Output USB SS PHY, AC-Coupled on carrier board Input Input SATA Connector Output SATA PHY, AC-Coupled on carrier board Output Input Open Drain 3.3V, Pull-up on the module Table 15. Jetson TX2 USB 3.0, PCIe & SATA Lane Mapping Configurations Jetson TX2 Pin Names Configs 1 Tegra Lanes Avail. Outputs from Jetson TX2 USB 3.0 PCIe SATA 2 (CB Default) 3 4 5 6 1. 2. 3. PEX_RFU PEX2 USB_SS1 PEX0 Lane 0 Lane 1 Lane 3 Lane 2 Lane 4 PCIe#0_3 PCIe#0_3 PCIe#0_2 PCIe#0_2 PCIe#0_1 PCIe#0_1 PCIe#0_0 PCIe#0_0 USB_SS#1 USB_SS#1 USB_SS#1 USB_SS#1 PCIe#1_0 USB_SS#2 PCIe#1_0 USB_SS#2 PCIe#1_0 PCIe#0_1 PCIe#1_0 PCIe#0_1 X4 PCIe Connector PCIe#0_0 PCIe#0_0 PCIe#0_0 PCIe#0_0 0 1 1x1 + 1x4 1x4 1 1 PCIe#2_0 2 3 1 2 3x1 2x1 2x1 + 1x2 1x1 + 1x2 1 1 1 1 PCIe#2_0 Default Usage on CB (carrier board) Note: PEX1 PCIe#2_0 Unused USB_SS0 (see note 1) SATA Lane 5 USB_SS#0 USB_SS#0 USB_SS#0 USB 3 Type A SATA SATA SATA SATA SATA SATA SATA PCIe interface #2 can be brought to the PEX1 pins, or USB 3.0 port #1 to the USB_SS0 pins on Jetson TX2 depending on the setting of a multiplexor on the module. The selection is controlled by QSPI_IO2 configured as a GPIO. Jetson TX2 has been designed to enable use cases listed in the table above. However, released Software may not support all configurations, nor has every configuration been validated. o Configuration #1 & 2 represent the supported and validated Jetson TX2 Developer Kit configurations. These configurations are supported by the released Software, and the PCIe, USB 3.0, and SATA interfaces have been verified on the carrier board. The cell colors highlight the different PCIe interfaces and USB 3.0 ports. Three shades of green are used for PCIe interfaces #[2:0]. Three shades of blue are used for USB 3.0 ports #[2:0]. SATA is highlighted in orange. JETSON TX2 OEM PRODUCT | DESIGN GUIDE | 20170912 21 NVIDIA Jetson TX2 OEM Product Design Guide 4. Any x4 configuration can be used as a single x2 using only lanes 0 & 1 or a single x1 using only lane 0. Any x2 configuration can be used as a single x1 using only lane 0. 5. In order to ease routing, the order of lanes for PCIe #0 can either be as shown above, or the reverse (i.e., PCIE#0_3 on PEX0, PCIE#0_2 on USB_SS1, PCIE#0_1 on PEX2 & PCIE#0_0 on PEX_RFU). Table 16. Backward Compatible USB 3.0, PCIe & SATA Lane Mapping Configurations Configs A Module Pin Names Avail. Outputs from Module USB 3.0 PCIe SATA B (CB Default) C D PEX_RFU PEX2 USB_SS1 PEX0 USB_SS0 SATA PCIe x4 L3 PCIe x4 L3 PCIex4 L2 PCIex4 L2 PCIex4 L1 PCIex4 L1 PCIex4 L0 PCIex4 L0 USB_SS (1) SATA SATA USB_SS (2) USB_SS (2) X4 PCIe Connector PCIex4 L0 PCIex4 L0 USB_SS (1) 0 1 1x1 + 1x4 1x4 1 1 PCIe x1 1 2 2x1 1x1 1 1 PCIe x1 Default Usage on CB (carrier board) Note: PEX1 Unused SATA SATA SATA USB 3 Type A See notes under Table 15 related to color coding, PCIe x2/x1 support & lane reversal. 5.1 USB Jetson TX2 Tegra UARTCAM VDD_5V0_IO_SYS To PMIC GPIO0 (on Module) UART5_CTS_N Gate/LS USB0_OTG_ID USB0_VBUS_DET A36 USB_VBUS_EN0 Load Switch IN OUT EN OC 100kΩ Figure 12 USB Connection Example 100Ω B37 VBUS VDD_3V3_SYS USB2_EN_OC# USB_VBUS_EN0 USB0_EN_OC# USB_VBUS_EN1 USB 2.0 USB1_EN_OC# USB0_DP USB0_DN USB0_D+ USB1_DP USB1_DN USB1_D+ USB2_DP USB2_DN USB2_D+ USB0_D– USB1_D– USB2_D– USB_SS0_TX+ USB 3.0 & PEX Default USB_SS0_TX– USB_SS0_RX+ PEX_TX0_P PEX_TX0_N PEX_RX0_P PEX_RX0_N USB_SS0_RX– Mux PEX1_TX+ PEX1_TX– PEX1_RX+ PEX1_RX– Note: 1. 2. 3. 4. A19 A17 A18 VDD_5V0_IO_SYS B39 B40 USB_VBUS_EN1 ID Load Switch IN OUT EN OC ESD 100Ω A38 A39 B42 B43 VBUS To M.2 Module on Carrier Board 0.1uF 0.1uF C43 C44 F43 F44 E41 E42 H41 USB 2.0 Micro AB D+ D– Common Mode Choke PCIe#2 (x1) Common Mode Choke D+ D– Common Mode Choke TX+ TX– Common Mode Choke RX+ RX– USB 3.0 Type A ESD H42 Common mode filters on USB[2:0]_DP/DN (USB 2.0 interfaces) are optional. Place only as needed if EMI is an issue. Common mode filters on USB3_TX/RX_P/N signals are not recommended. If common mode devices are placed, they must be selected to minimize the impact to signal quality, which must meet the USB spec. signal requirements. See the Common Mode Choke requirements in the USB 3.0 Interface Signal Routing Requirements table. If USB 3.0 is routed to a connector, only AC caps on Jetson TX2 TX lines are required. If routed directly to a peripheral, AC caps are needed for both Jetson TX2 TX lines (connected to device RX) & Device TX lines (connected to Jetson TX2 RX). USB0 must be available to use as USB Device for USB Recovery Mode. Connector used must be USB-IF certified if USB 3.0 implemented. JETSON TX2 OEM PRODUCT | DESIGN GUIDE | 20170912 22 NVIDIA Jetson TX2 OEM Product Design Guide USB 2.0 Design Guidelines These requirements apply to the USB 2.0 controller PHY interfaces: USB[2:0]_D–/D+ Table 17. USB 2.0 Interface Signal Routing Requirements Parameter Max Frequency (High Speed) Bit Rate/UI period/Frequency Max Loading High Speed / Full Speed / Low Speed Reference plane Trace Impedance Diff pair / Single Ended Via proximity (Signal to reference) Max Trace Delay With CMC or SW (Microstrip / Stripline) Without CMC or SW (Microstrip / Stripline) Requirement 480/2.083/240 10 / 150 / 600 GND 90 / 50 < 3.8 (24) 900/1050 (6) 1350/1575 (9) Max Intra-Pair Skew between USBx_D+ & USBx_D– 7.5 Note: 1. 2. 3. 4. Units Mbps/ns/MHz pF Ω mm (ps) ps (in) Notes ±15% See Note 2 Prop delay assumption: 175ps/in. for stripline, 150ps/in. for microstrip). See Note 3 ps If portion of route is over a flex cable this length should be included in the Max Trace Delay/Length calculation & 85Ω Differential pair trace impedance is recommended. Up to 4 signal Vias can share a single GND return Via. CMC = Common-Mode-Choke. SW = Analog Switch Adjustments to the USB drive strength, slew rate, termination value settings should not be necessary, but if any are made, they MUST be done as an offset to default values instead of overwriting those values. USB 3.0 Design Guidelines The following requirements apply to the USB 3.0 PHY interfaces Table 18. USB 3.0 Interface Signal Routing Requirements Parameter Specification Data Rate / UI period Max Number of Loads Termination Reference plane Electrical Specification Insertion Loss @ 2.5GHz Type-C Type A Resonance dip frequency TDR dip Near-end Crosstalk (NEXT) @ DC to 5GHz IL/NEXT plot Trace Impedance Trace Impedance Reference plane Diff pair / Single Ended JETSON TX2 OEM PRODUCT | DESIGN GUIDE | 20170912 Requirement Units 5.0 / 200 1 90 differential GND Gbps / ps load Ω <=2 <=7 >8 >= 75 <=-45 85-90 / 45-55 GND dB dB GHz Ω dB Ω Notes On-die termination at TX & RX Only PCB with add-on components (connector excluded) is considered Using TDR pulse with Tr (10%-90%) = 200ps For each TX-RX NEXT ±15% 23 NVIDIA Jetson TX2 OEM Product Design Guide Trace Length/Skew Trace loss characteristic @ 2.5GHz Breakout Region Max Trace Length < 0.7 Max trace length/delay dB/in 11 (73) 152.3 (1014) mm (ps) mm (ps) The following max length is derived based on this characteristic. See Note 1. Trace with minimum width and spacing Max length assume USB3 Tx voltage swing set at 0.8V MIN, length can increase if Tx swing increase. Do trace length matching before hitting discontinuities 0.15 (1) mm (ps) Max Within Pair (Intra-Pair) Skew Differential pair uncoupled length 6.29 (41.9) mm (ps) Trace Spacing – for TX/RX non-interleaving TX-RX Xtalk is very critical in PCB trace routing. The ideal solution is to route TX and RX on different layers. If routing on the same layer, strongly recommend not interleaving TX and RX lanes If it is necessary to have interleaved routing in breakout, all the inter-pair spacing should follow the rule of inter-SNEXT The breakout trace width is suggested to be the minimum to increase inter-pair spacing Do not perform serpentine routing for intra-pair skew compensation in the breakout region Min Inter-SNEXT Breakout (between TX/RX) Main-route Min Inter-SFEXT Breakout (between TX/TX or RX/RX) Main-route Max length Breakout Main-route Trace Spacing – for TX/RX interleaving Trace Spacing Pair-Pair (inter-pair) Microstrip / Stripline To plane & capacitor pad Microstrip / Stripline To unrelated high-speed signals Microstrip / Stripline Via Topology 4.85x 3x 1x 1x 11 Max trace length - LBRK Dielectric height Inter-pair spacing mm 4x / 3x 4x / 3x 4x / 3x dielectric - GND via - - Max # of Vias Max Via Stub Length Serpentine Min bend angle Dimension PTH vias Micro Vias Min A Spacing Min B, C Length Min Jog Width - This is the recommended dimension for meeting NEXT requirement Stripline structure in a GSSG structure is assumed; it holds in broadside-coupled stripline structure All values are in terms of minimum dielectric height Y-pattern is recommended Keep symmetry Y-pattern helps with Xtalk suppression. It can also reduce the limit of pair-pair distance. Need review (NEXT/FEXT check) if via placement is not Ypattern. Place ground vias as symmetrically as possible to data pair vias up to 4 signal vias (2 diff pairs) can share a single GND return via GND via is used to maintain return path, while its Xtalk suppression is limited 4 Not limited as long as total channel loss meets IL spec 0.4 mm long via stub requires review (IL & resonance dip check) 135 4x 1.5x 3x deg (α) Trace width S1 must be taken care in order to consider Xtalk to adjacent pair Added-on Components JETSON TX2 OEM PRODUCT | DESIGN GUIDE | 20170912 24 NVIDIA Jetson TX2 OEM Product Design Guide Placement Order AC Cap Value Min/Max Location (max length to adjacent discontinuity) Voiding Chip ̶ AC capacitor (TX only) ̶ common mode choke ̶ ESD ̶ Connector uF mm GND/PWR void under/above cap is preferred 0.1 / 0.2 8 Only required for TX pair when routed to connector Discontinuity is connector, via, or component pad Voiding is required if AC cap size is 0603 or larger ESD (the usage of ESD is optional. A design should include the footprint for ESD as a stuffing option) e.g. SEMTECH RClamp0524p Preferred device pF Max Junction capacitance (IO to GND) 0.8 Footprint Pad should be on the net – not trace stub Location (max length to adjacent discontinuity) Common-mode Choke (Only if needed. Place near connector.) Common-mode impedance @100MHz Min/Max Max Rdc Differential TDR impedance @TR-200ps (10%-90%) Min Sdd21 @ 2.5GHz Max Scc21 @ 2.5GHz Routing length reduction 8 (53) mm (ps) 65/90 0.3 90 2.22 19.2 <= 3 Ω Ω Ω 1. 2. 3. TDK ACM2012D-900-2P dB dB in FPC (Additional length of Flexible Printed Circuit Board) The FPC routing should be included for PCB trace calculations (max length, etc.) Characteristic Impedance Same as PCB Loss characteristic Strongly recommend to be the same as PCB or better Connector Connector used must be USB-IF certified Note: Discontinuity is connector, via, or component pad If worse than PCB, the PCB & FPC length must be reestimated Longer trace lengths may be possible if the total trace loss is equal to or better than the target. If the loss is greater, the max trace lengths will need to be reduced. Recommend trace length matching to <1ps before Vias or any discontinuity to minimize common mode conversion. Place GND Vias as symmetrically as possible to data pair Vias. Common USB Routing Guidelines Guideline If routing to USB device or USB connector includes a flex or 2nd PCB, the total routing including all PCBs/flexes must be used for the max trace & skew calculations. Keep critical USB related traces away from other signal traces or unrelated power traces/areas or power supply components JETSON TX2 OEM PRODUCT | DESIGN GUIDE | 20170912 25 NVIDIA Jetson TX2 OEM Product Design Guide Table 19. Jetson TX2 USB 2.0 Signal Connections Jetson TX2 Ball Name USB[2:0]_D+ USB[2:0]_D– Type Termination Description DIFF I/O 90Ω common-mode chokes close to connector. ESD Protection between choke & connector on each line to GND USB Differential Data Pair: Connect to USB connector, Mini-Card Socket, Hub or other device on the PCB. Table 20. Miscellaneous USB 2.0 Signal Connections Jetson TX2 Pin Name USB0_VBUS_DET USB0_OTG_ID Type A Termination Description 100kΩ resistor to GND. See reference design for VBUS power filtering. USB0 VBus Detect: Connect to VBUS pin of USB connector receiving USB0_+/– interface. Also connects to VBUS power supply if host mode supported. USB Identification: Connect to ID pin of USB OTG connector receiving USB0_P/M interface. A Table 21. Jetson TX2 USB 3.0 Signal Connections Jetson TX2 Pin Name USB_SS0_TX+/– (USB 3.0 Port #0) PEX_RFU_TX+/– (USB 3.0 Port #1) USB_SS1_TX+/– (USB 3.0 Port #2) USB_SS0_RX+/– (USB 3.0 Port #0) PEX_RFU_RX+/– (USB 3.0 Port #1) USB_SS1_RX+/– (USB 3.0 Port #2) Type DIFF Out Termination Series 0.1uF caps. Common-mode chokes & ESD protection if these are used. DIFF In If routed directly to a peripheral on the board, AC caps are needed for the peripheral TX lines. Common-mode chokes & ESD protection, if these are used. Description USB 3.0 Differential Transmit Data Pairs: Connect to USB 3.0 connectors, hubs or other devices on the PCB. USB 3.0 Differential Receive Data Pairs: Connect to USB 3.0 connectors, hubs or other devices on the PCB. Table 22. Recommended USB observation (test) points for initial boards Test Points Recommended One for each of the USB 2.0 data lines (D+/-) One for each of the USB 3.0 output lines used (TXn_+/-) One for each of the USB 3.0 input lines (RX_+/-) Location Near Jetson TX2 connector & USB device. USB connector pins can serve as test points. Near USB device. USB connector pins can serve as test points Near Jetson TX2 connector. 5.2 PCIe Jetson TX2 contains a PCIe (PEX) controller that supports up to 5 lanes, and 3 separate interfaces. This narrow, high-speed interface can be used to connect to a variety of high bandwidth devices. JETSON TX2 OEM PRODUCT | DESIGN GUIDE | 20170912 26 NVIDIA Jetson TX2 OEM Product Design Guide Figure 13. PCIe Connection Example Jetson TX2 Tegra - PCIe PEX PEX1_REFCLK+ PEX_CLK3_P PEX_CLK3_N PEX1_REFCLK– PEX1_TX+ PEX1_TX– PEX1_RX+ PEX_TX0P PEX_TX0N PEX_RX0P PEX_RX0N PEX1_RX– Mux Tegra QSPI_IO2 LS SEL USB_SS0_TX+ (Default) USB_SS0_TX– USB_SS0_RX+ B4 5 B4 6 E41 E42 H41 H42 C43 C44 F43 USB_SS0_RX– PEX_CLK1_P PEX_CLK1_N PEX0_REFCLK+ PEX_TX1P PEX_TX1N PEX_RX1P PEX_RX1N PEX_RFU_T X+ PEX0_REFCLK– PEX_RFU_T X– PEX_RFU_RX+ PEX_RFU_RX– USB_SS1_TX+ PEX_TX2P PEX_TX2N PEX_RX2P PEX_RX2N USB_SS1_TX– USB_SS1_RX+ USB_SS1_RX– PEX2_TX+ PEX_TX3P PEX_TX3N PEX_RX3P PEX_RX3N PEX2_TX– PEX2_RX+ PEX2_RX– PEX0_TX+ PEX_TX4P PEX_TX4N PEX_RX4P PEX_RX4N PEX0_TX– PEX0_RX+ PEX0_RX– PEX2_REFCLK+ PEX_CLK2_P PEX_CLK2_N PEX2_REFCLK– PCIe – Single Lane (IF #2) or (USB 3.0 Port #0). Used for M.2 Connector on Carrier Board 0.1uF 0.1uF USB 3.0 (Port #1) F44 A44 A45 D39 D40 G39 G40 D42 D43 G42 G43 C40 C41 F40 F41 E44 E45 H44 H45 0.1uF 0.1uF PCIe IF #0 Lane 3 Default: PCIe x1 (only PEX2_TX/RX lane used) 0.1uF 0.1uF PCIe IF #0 Lane 1 Alternate: PCIe x4 (Routed to PCIe Connector on Carrier Board) 0.1uF 0.1uF PCIe IF #0 Lane 2 0.1uF 0.1uF PCIe IF #0 Lane 0 Optionally used with PCIe IF x1 on PEX2_TX/RX (PCIe IF #1). A41 A42 VDD_3V3_SYS PEX Control PEX_L0_CLKREQ_N PEX_L0_RST_N PEX0_CLKREQ# PEX_L1_CLKREQ_N PEX_L1_RST_N PEX2_CLKREQ# PEX_L2_CLKREQ_N PEX_L2_RST_N PEX0_RST# PEX2_RST# Mux PMIC GPIO7 SEL SATA_DEV_SLP PEX1_CLKREQ# PEX1_RST# PEX_WAKE# PEX_WAKE_N C48 C49 Control for PCIe IF #0 Lanes C46 Control for PCIe IF #1 Lane D49 D47 Control for PCIe IF #2 Lane C47 E50 Shared D48 PCIE Design Guidelines Table 23. PCIE Interface Signal Routing Requirements Parameter Specification Data Rate / UI Period Configuration / Device Organization Topology Termination Impedance Trace Impedance differential / Single Ended Reference plane Spacing Trace Spacing (Stripline/Microstrip) Pair – Pair To plane & capacitor pad JETSON TX2 OEM PRODUCT | DESIGN GUIDE | 20170912 Requirement 5.0 / 200 1 Point-point 50 Units Gbps / ps Load Notes 2.5GHz, half-rate architecture Ω Unidirectional, differential To GND Single Ended for P & N 85 / 50 GND Ω ±15%. See note 1 3x / 4x 3x / 4x Dielectric 27 NVIDIA Jetson TX2 OEM Product Design Guide To unrelated high-speed signals Length/Skew Trace loss characteristic @ 2.5GHz 3x / 4x < 0.7 dB/in Breakout region (Max Length) 41.9 ps Max trace length Max PCB via distance from the BGA PCB within pair (intra-pair) skew 5.5 (880) 41.9 0.15 (0.5) in (ps) ps mm (ps) 0.15 (0.5) mm (ps) Within pair (intra-pair) matching between subsequent discontinuities Differential pair uncoupled length Via Via placement Max # of Vias PTH Vias Micro-Vias Max Via stub length Routing signals over antipads AC Cap Value Min/Max Location (max length to adjacent discontinuity) Voiding Serpentine Min bend angle Dimension Min A Spacing Min B, C Length Min Jog Width MIsc. Routing signals over antipads Routing over voids Connector Voiding 41.9 The following max length is derived based on this characteristic. See note 3 Minimum width and spacing. 4x or wider dielectric height spacing is preferred Max distance from BGA ball to first PCB via. Do trace length matching before hitting discontinuities ps Place GND vias as symmetrically as possible to data pair vias. GND via distance should be placed less than 1x the diff pair via pitch 2 for TX traces & 2 for RX trace No requirement 0.4 mm Longer via stubs would require review Not allowed uF 0.075 / 0.2 mm 8 Voiding the plane directly under the pad 3-4 mils larger than the pad size is recommended. Only required for TX pair when routed to connector Discontinuity such as edge finger, component pad 135 4x 1.5x 3x S1 must be taken care in order to consider Xtalk to adjacent pair deg (a) Trace width Not allowed When signal pair approaches Vias, the maximal trace length across the void on the plane is 50mil. Voiding the plane directly under the pad 5.7 mils larger than the pad size is recommended. Keep critical PCIe traces such as PEX_TX/RX, TERMP etc. away from other signal traces or unrelated power traces/areas or power supply components Note: 1. 2. 3. 4. The PCIe spec. has 40-60Ω absolute min/max trace impedance, which can be used instead of the 50Ω, ± 15%. If routing in the same layer is necessary, route group TX & RX separately without mixing RX/TX routes & keep distance between nearest TX/RX trace & RX to other signals 3x RX-RX separation. Longer trace lengths may be possible if the total trace loss is equal to or better than the target. If the loss is greater, the max trace lengths will need to be reduced. Do length matching before Via transitions to different layers or any discontinuity to minimize common mode conversion. JETSON TX2 OEM PRODUCT | DESIGN GUIDE | 20170912 28 NVIDIA Jetson TX2 OEM Product Design Guide Table 24. PCIE Signal Connections Jetson TX2 Pin Name Type Termination Description PCIe Interface #0 (x1 default configuration – x4 optional. PEX0_TX+/– USB_SS1_TX+/– PEX2_TX+/– PEX_RFU_TX+/– PEX0_RX_+/– USB_SS1_RX+/– PEX2_RX+/– PEX_RFU_RX+/– PEX0_REFCLK+/– PEX0_CLKREQ# PEX0_RST# (Lane 0) (Lane 1) (Lane 2) (Lane 3) (Lane 0) (Lane 1) (Lane 2) (Lane 3) DIFF OUT DIFF IN Series 0.1uF Capacitor Differential Transmit Data Pairs: Connect to TX_P/N pins of PCIe connector or RX_P/N pin of PCIe device through AC cap according to supported configuration. Default configuration (x1) uses only Lane 0. Series 0.1uF capacitors if device on main PCB. Differential Receive Data Pairs: Connect to RX_P/N pins of PCIe connector or TX_P/N pin of PCIe device through AC cap according to supported configuration. Default configuration (x1) uses only Lane 0. DIFF OUT I/O O 56KΩ pullup to VDD_3V3_SYS on each line (exists on Jetson TX2) Differential Reference Clock Output: Connect to REFCLK_P/N pins of PCIe device/connector PEX Clock Request for PEX0_REFCLK: Connect to CLKREQ pin on device/connector. PEX Reset: Connect to PERST pin on device/connector. PCIe Interface #1 (x1) – (Shared with PCIe Interface #0 lane 2) PEX2_TX+/– DIFF OUT PEX2_RX+/– DIFF IN PEX2_REFCLK+/– PEX2_CLKREQ# PEX2_RST# Series 0.1uF Capacitor Series 0.1uF capacitors if device on main PCB. DIFF OUT I/O O 56KΩ pullup to VDD_3V3_SYS on each line (exists on Jetson TX2) Differential Transmit Data Pairs: Connect to TX+/– pins of PCIe connector or RX_+/– pin of PCIe device through AC cap according to supported configuration. Differential Receive Data Pairs: Connect to RX_+/– pins of PCIe connector or TX_+/– pin of PCIe device through AC cap according to supported configuration. Differential Reference Clock Output: Connect to REFCLK_+/– pins of PCIe device/connector. PEX Clock Request for PEX2_REFCLK: Connect to CLKREQ pin on device/connector(s) PEX Reset: Connect to PERST pin on device/connector. PCIe Interface #2 (x1) – Muxed with USB 3.0 Port #0 on USB_SS0 PEX1_TX+/– DIFF OUT PEX1_RX+/– DIFF IN PEX1_REFCLK+/– PEX1_CLKREQ# PEX1_RST# PEX_WAKE# Note: Series 0.1uF Capacitor Series 0.1uF capacitors if device on main PCB. DIFF OUT I/O O I 56KΩ pullup to VDD_3V3_SYS on each line (exists on Jetson TX2) 56KΩ pullup to VDD_3V3_SYS (exists on Jetson TX2) Differential Transmit Data Pairs: Connect to TX+/– pins of PCIe connector or RX_+/– pin of PCIe device through AC cap according to supported configuration. Differential Receive Data Pairs: Connect to RX_+/– pins of PCIe connector or TX_+/– pin of PCIe device through AC cap according to supported configuration. Differential Reference Clock Output: Connect to REFCLK_+/– pins of PCIe device/connector PEX Clock Request for PEX1_REFCLK: Connect to CLKREQ pin on device/connector(s) PEX Reset: Connect to PERST pin on device/connector(s) PEX Wake: Connect to WAKE pins on devices or connectors Check “Supported USB 3.0, PEX & SATA Interface Mappings” tables earlier in this section for PCIE IF mapping options. Table 25. Recommended PCIe observation (test) points for initial boards Test Points Recommended One for each of the PCIe TX_+/– output lines used. One for each of the PCIe RX_+/– input lines used. JETSON TX2 OEM PRODUCT | DESIGN GUIDE | 20170912 Location Near PCIe device. Connector pins may serve as test points if accessible. Near Jetson TX2 connector. 29 NVIDIA Jetson TX2 OEM Product Design Guide 5.3 SATA A Gen 2 SATA controller is implemented on Jetson TX2. The interface is brought to Jetson TX2 edge connector as shown in the figure below. Figure 14. SATA Connection Example Jetson TX2 1 Tegra PEX, USB 3.0 & SATA 2 SATA_TX+ PEX_TX5P PEX_TX5N PEX_RX5P PEX_RX5N SATA_TX– SATA_RX+ SATA_RX– PEXCTL D45 D46 PEX1_CLKREQ# Mux SEL PMIC SATA_DEV_SLP 4 0.01uF 0.01uF G45 5 6 G46 7 VDD_1V8 PEX_L2_CLKREQ_N 3 0.01uF 0.01uF VDD_3V3_SLP 8 C47 9 Level Shifter D47 10 11 12 13 GPIO7 14 15 VDD_5V0_IO_SLP 16 17 18 19 VDD_12V_SLP 20 21 22 SATA Design Guidelines Table 26. SATA Signal Routing Requirements Parameter Specification Max Frequency Bit Rate / UI Topology Configuration / Device Organization Max Load (per pin) Termination Impedance Reference plane Trace Impedance Differential Pair / Single Ended Spacing Trace Spacing Pair-to-pair (inter-pair) Stripline / Microstrip To plane & capacitor pad Stripline / Microstrip To unrelated high-speed signals Stripline / Microstrip Length/Skew Breakout region Max Length Spacing Max Trace Length/Delay Max PCB Via distance from pin Max Within Pair (Intra-Pair) Skew Intra-pair matching between subsequent discontinuities Requirement Units Notes 3.0 / 333.3 Point to point 1 0.5 100 Gbps / ps 1.5GHz Unidirectional, differential Differential pair uncoupled length AC Cap AC Cap Value typical (max) AC Cap Location (max distance from adjacent discontinuities) GND 95 / 45-55 load pf Ω On die termination Ω ±15% 3x / 4x 3x / 4x 3x / 4x Dielectric 41.9 Min width/spacing 76.2 (480) 6.29 (41.9) 0.15 (0.5) 0.15 (0.5) ps 6.29 (41.9) mm (ps) 0.01 (0.012) 8 (53.22) uF mm (ps) Mm (ps) mm (ps) mm (ps) mm (ps) 4x or wider dielectric height spacing is preferred Do trace length matching before hitting discontinuities The AC cap location should be located as close as possible to nearby discontinuities. Via JETSON TX2 OEM PRODUCT | DESIGN GUIDE | 20170912 30 NVIDIA Jetson TX2 OEM Product Design Guide Parameter GND Via Placement Requirement Units Notes Place ground vias as symmetrically as possible to data pair vias GND via distance should be placed less than 1x the diff pair via pitch 3 If all are through-hole < 0.4 mm Max # of vias Via stub length Voiding AC cap pad voiding Voiding the plane directly under the pad 3-4 mils larger than the pad size is recommended The size of voiding can be same as the size of pin pad Connector voiding (Required) ESD ESD protection device (Optional) Type: SEMTECH RClamp0524p. Place ESD component near connector. A design may include the footprints for ESD as a stuffing option. The junction capacitance in ESD may cause effect on signal integrity, so it’s important to choose an ESD component with low capacitance and whose package design is optimized for high speed links. The SEMTECH ESD Rclamp0524p has been well verified with its 0.3pF capacitance. 8 (53) mm (ps) Max distance from ESD Device to Connector Recommended ESD layout Choke Preferred device Type: TDK ACM2012D-900-2P. Only if needed. Place near connector. Refer to Common Mode Choke Requirement section. Location - Max distance from to adjacent discontinuities – ex, connector, AC cap) Common-mode impedance @ 100MHz Min/Max Max Rdc Differential TDR impedance 8 (53) mm (ps) 65/90 0.3 90 Ω Ω Ω @TR200ps (10%90%) Min Sdd21 @ 2.5GHz Max Scc21 @ 2.5GHz 2.22 19.2 Serpentine Min bend angle Dimension Min A Spacing Min B, C Length Min Jog Width TDK ACM2012D-900-2P dB dB 135 4x 1.5x 3x deg (a) Trace width S1 must be taken care in order to consider Xtalk to adjacent pair MIsc. Routing over voids Noise Coupling Note: Where signal 1.27mm Keep critical SATA related traces such as SATA_TX/RX, SATA_TERM etc. away from other signal traces or unrelated power traces/areas or power supply components If routing to SATA device or SATA connector includes a flex or 2nd PCB, the total routing including all PCBs/flexes must be used for the max trace & skew calculations JETSON TX2 OEM PRODUCT | DESIGN GUIDE | 20170912 31 NVIDIA Jetson TX2 OEM Product Design Guide Table 27. SATA Signal Connections Jetson TX2 Pin Name SATA_TX+/– SATA_RX+/– SATA_DEV_SLP Type DIFF OUT Termination Series 0.01uF Capacitor DIFF IN Series 0.01uF Capacitor O 1.8V to 3.3V level shifter Description Differential Transmit Data Pair: Connect to SATA+/– pins of SATA device/connector through termination (capacitor) Differential Receive Data Pair: Connect to SATA+/– pins of SATA device/connector through termination (capacitor) SATA Device Sleep: Connect through level shifter to matching pin on device or connector (pin 10 of Connector show in example). Table 28. Recommended SATA observation (test) points for initial boards Test Points Recommended One for each of the SATA_TX_+/– output lines. One for each of the SATA_RX_+/– input lines. JETSON TX2 OEM PRODUCT | DESIGN GUIDE | 20170912 Location Near SATA device. Connector pins may serve as test points if accessible. Near Jetson TX2 connector. 32 NVIDIA Jetson TX2 OEM Product Design Guide 6.0 GIGABIT ETHERNET Jetson TX2 integrates a BCM54610C1IMLG Ethernet PHY. The magnetics & RJ45 connector are implemented on the Carrier board. Contact Broadcom for the Carrier board placement/routing guidelines. Table 29. Jetson TX2 Gigabit Ethernet Pin Descriptions Usage on Carrier Board Pin # Jetson TX2 Pin Name Tegra Signal Usage/Description E47 F50 F46 E49 E48 F48 F47 G49 G48 H48 H47 GBE_LINK_ACT# GBE_LINK100# GBE_LINK1000# GBE_MDI0– GBE_MDI0+ GBE_MDI1– GBE_MDI1+ GBE_MDI2– GBE_MDI2+ GBE_MDI3– GBE_MDI3+ − − − − − − − − − − − GbE RJ45 connector Link ACT (LED0) GbE RJ45 connector Link 100 (LED1) GbE RJ45 connector Link 1000 (LED2) GbE Transformer Data 0– GbE Transformer Data 0+ GbE Transformer Data 1– GbE Transformer Data 1+ GbE Transformer Data 2– GbE Transformer Data 2+ GbE Transformer Data 3– GbE Transformer Data 3+ Direction Output Output Output Bidir Bidir Bidir Bidir Bidir Bidir Bidir Bidir LAN Pin Type CMOS – 3.3V tolerant MDI Figure 15. Ethernet Connections Jetson TX2 Tegra SDMMC2_HV GbE Tranceiver EQOS_TXC EQOS_TD0 EQOS_TD1 EQOS_TD2 EQOS_TD3 EQOS_TX_CTL GBE_MDI1– GBE_MDI2+ GBE_MDI2– GBE_MDI3+ GBE_MDI3– GBE_LINK_ACT GBE_LINK_100 GBE_LINK_1000 VDD_3V3_SYS EQOS_MDC EQOS_MDIO 1.8V DMIC4_DAT DMIC4_CLK GBE_MDI0– GBE_MDI1+ EQOS_RXC EQOS_RD0 EQOS_RD1 EQOS_RD2 EQOS_RD3 EQOS_RX_CTL AUDIO_HV GBE_MDI0+ ENETPHY_RST GBE_CTREF E48 E49 F47 F48 G48 G49 To Magnetics / RJ45 Connector H47 H48 E47 F50 F46 H50 3.3V LS ENETPHY_INT VDD_1V8 Figure 16. Gigabit Ethernet Magnetics & RJ45 Connections Magnetics GBE_MDI0+ + CT – + CT – + CT – + CT – GBE_MDI0– GBE_MDI1+ GBE_MDI1– GBE_MDI2+ GBE_MDI2– GBE_MDI3+ GBE_MDI3– VDD_3V3_SLP + CT – + CT – + CT – + CT – VDD_3V3_SLP TDP 75Ω 0.1uF TDN RDP RJ45 14 9 10 75Ω 1 RDN TDP1 3 5 75Ω 7 TDN1 RDP1 11 4 6 8 12 13 75Ω RDN1 ESD 10nF 2 100pF 1nF 0.1uF GBE_LINK_ACT GBE_LED0_SPICSB GBE_LINK_100 GBE_LED1_SPISCK 681Ω,1% 0.1uF 681Ω,1% Note: The connections above match those used on the carrier board and are shown for reference. JETSON TX2 OEM PRODUCT | DESIGN GUIDE | 20170912 33 NVIDIA Jetson TX2 OEM Product Design Guide Table 30. Ethernet MDI Interface Signal Routing Requirements Parameter Reference plane Trace Impedance Diff pair / Single Ended Min Trace Spacing (Pair-Pair) Max Trace Length Max Within Pair (Intra-Pair) Skew Number of Vias Requirement GND 100 / 50 0.763 109 (690) 0.15 (1) minimum Units Notes Ω ±15%. Differential impedance target is 100Ω. 90Ω can be used if 100Ω is not achievable mm mm (ps) mm (ps) Ideally there should be no vias, but if required for breakout to Ethernet controller or magnetics, keep very close to either device. Table 31. Ethernet Signal Connections Jetson TX2 Pin Name GBE_MDI[3:0]+/– Type Termination Description ESD device to GND per signal Gigabit Ethernet MDI IF Pairs: Connect to Magnetics +/– pins GBE_LINK_ACT GBE_LINK100 DIFF I/O O O GBE_LINK1000 GBE_CTREF O na 681Ω series resistor & 0.1uF capacitor to GND 681Ω series resistor & 0.1uF capacitor to GND. 10kΩ Pull-down to GND (exists on Jetson TX2) 681Ω series resistor & 0.1uF capacitor to GND Gigabit Ethernet ACT : Connect to LED1C on Ethernet connector. Gigabit Ethernet Link 100 : Connect to LED2C on Ethernet connector. Pulldown part of strapping to use 3.3V PHY mode. Gigabit Ethernet Link 1000 : Connect to Link 1000 LED on conn. Not used Table 32. Recommended Gigabit Ethernet observation (test) points for initial boards Test Points Recommended One for each of the MDI[3:0]+/– lines. JETSON TX2 OEM PRODUCT | DESIGN GUIDE | 20170912 Location Near Jetson TX2 connector & Magnetics device. 34 NVIDIA Jetson TX2 OEM Product Design Guide 7.0 DISPLAY Jetson TX2 designs can select from several display options including MIPI DSI & eDP for embedded displays, and HDMI or DP for external displays. Three display controllers are available, so the possible display combinations are: ▪ ▪ ▪ DP/HDMI + eDP + single/dual-link-DSI DP/HDMI + single-link-DSI + single-link-DSI DP/HDMI + DP/HDMI + single/dual-link-DSI Table 33. Jetson TX2 Display General Pin Descriptions Pin # A26 A27 A25 B26 B28 B27 A24 Jetson TX2 Pin Name GSYNC_HSYNC GSYNC_VSYNC LCD_TE LCD_VDD_EN LCD_BKLT_EN LCD0_BKLT_PWM LCD1_BKLT_PWM Tegra Signal GPIO_DIS4 GPIO_DIS2 GPIO_DIS1 GPIO_EDP0 GPIO_DIS3 GPIO_DIS0 GPIO_DIS5 Usage/Description GSYNC Horizontal Sync GSYNC Vertical Sync Display Tearing Effect Display VDD Enable Display Backlight Enable Display Backlight PWM 0 Display Backlight PWM 1 Usage on Carrier Board Display Connector Direction Output Output Input Output Output Output Output Pin Type CMOS – 1.8V CMOS – 1.8V CMOS – 1.8V CMOS – 1.8V CMOS – 1.8V CMOS – 1.8V CMOS – 1.8V 7.1 MIPI DSI Jetson TX2 supports eight total MIPI DSI data lanes. Each data lane has a peak bandwidth up to 1.5Gbps. The lanes can be configured in Dual Link & Split Link modes. The following configurations are possible: Dual Link Mode (Up to 8 PHY lanes): ▪ DSI-A (1x4) + DSI-C (1x4) to single display ▪ DSI-A (1x4) to one display, DSI-C (1x4) to a second display Split Link Mode (Up to 8 PHY lanes): ▪ Two Links with 1-lane each: DSI-A(1x1) + DSI-B (1x1) or DSI-C (1x1) + DSI-D (1x1) ▪ Two Links with 2-lane each: DSI-A(1x2) + DSI-B (1x2) or DSI-C (1x2) + DSI-D (1x2) ▪ Four Links with 1-lane each: DSI-A(1x1) + DSI-B (1x1) + DSI-C (1x1) + DSI-D (1x1) ▪ Four Links with 2-lane each: DSI-A(1x2) + DSI-B (1x2) + DSI-C (1x2) + DSI-D (1x2) Table 34. Jetson TX2 DSI Pin Descriptions Pin # G34 G33 F35 F34 H33 H32 D34 D33 C35 C34 E33 E32 G31 G30 F32 F31 H30 H29 D31 D30 C32 C31 E30 E29 Jetson TX2 Pin Name DSI0_CLK– DSI0_CLK+ DSI0_D0– DSI0_D0+ DSI0_D1– DSI0_D1+ DSI1_CLK– DSI1_CLK+ DSI1_D0– DSI1_D0+ DSI1_D1– DSI1_D1+ DSI2_CLK– DSI2_CLK+ DSI2_D0– DSI2_D0+ DSI2_D1– DSI2_D1+ DSI3_CLK– DSI3_CLK+ DSI3_D0– DSI3_D0+ DSI3_D1– DSI3_D1+ Tegra Signal DSI_A_CLK_N DSI_A_CLK_P DSI_A_D0_N DSI_A_D0_P DSI_A_D1_N DSI_A_D1_P DSI_B_CLK_N DSI_B_CLK_P DSI_B_D0_N DSI_B_D0_P DSI_B_D1_N DSI_B_D1_P DSI_C_CLK_N DSI_C_CLK_P DSI_C_D0_N DSI_C_D0_P DSI_C_D1_N DSI_C_D1_P DSI_D_CLK_N DSI_D_CLK_P DSI_D_D0_N DSI_D_D0_P DSI_D_D1_N DSI_D_D1_P JETSON TX2 OEM PRODUCT | DESIGN GUIDE | 20170912 Usage/Description Display, DSI 0 Clock– Display, DSI 0 Clock+ Display, DSI 0 Data 0– Display, DSI 0 Data 0+ Display, DSI 0 Data 1– Display, DSI 0 Data 1+ Display DSI 1 Clock– Display DSI 1 Clock+ Display, DSI 1 Data 0– Display, DSI 1 Data 0+ Display, DSI 1 Data 1– Display, DSI 1 Data 1+ Display DSI 2 Clock– Display DSI 2 Clock+ Display, DSI 2 Data 0– Display, DSI 2 Data 0+ Display, DSI 2 Data 1– Display, DSI 2 Data 1+ Display DSI 3 Clock– Display DSI 3 Clock+ Display, DSI 3 Data 0– Display, DSI 3 Data 0+ Display, DSI 3 Data 1– Display, DSI 3 Data 1+ Usage on Carrier Board Display Connector Direction Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Pin Type MIPI D-PHY 35 NVIDIA Jetson TX2 OEM Product Design Guide Figure 17: DSI Dual Link Connections Jetson TX2 Display Connector (DSI) Tegra DSI/CSI Note: DSI_A_CLK_P DSI_A_CLK_N DSI_A_D0_P DSI_A_D0_N DSI_A_D1_P DSI_A_D1_N DSI0_CK+ DSI_B_CLK_P DSI_B_CLK_N DSI_B_D0_P DSI_B_D0_N DSI_B_D1_P DSI_B_D1_N DSI1_CK+ DSI_C_CLK_P DSI_C_CLK_N DSI_C_D0_P DSI_C_D0_N DSI_C_D1_P DSI_C_D1_N DSI2_CK+ DSI_D_CLK_P DSI_D_CLK_N DSI_D_D0_P DSI_D_D0_N DSI_D_D1_P DSI_D_D1_N DSI3_CK+ DSI0_CK– DSI0_D0+ DSI0_D0– DSI0_D1+ DSI0_D1– DSI1_CK– DSI1_D0+ DSI1_D0– DSI1_D1+ DSI1_D1– DSI2_CK– DSI2_D0+ DSI2_D0– DSI2_D1+ DSI2_D1– DSI3_CK– DSI3_D0+ DSI3_D0– DSI3_D1+ DSI3_D1– A_CLKP A_CLKN A_D0P A_D0N A_D1P A_D1N G33 G34 F34 F35 H32 H33 4-Lane D33 D34 C34 C35 E32 E33 G30 EMI/ESD G31 F31 F32 H29 H30 A_D2P A_D2N A_D3P A_D3N B_CLKP B_CLKN B_D0P B_D0N B_D1P B_D1N Each 4-lane interface can go to a separate display, or both can go to a single display. 4-Lane D30 D31 B_D2P B_D2N B_D3P B_D3N C31 C32 E29 E30 If EMI/ESD devices are necessary, they must be tuned to minimize impact to signal quality, which must meet the DSI spec. requirements for the frequencies supported by the design. Figure 18: DSI Split Link Connections Jetson TX2 Display Connector (DSI) Tegra DSI/CSI DSI_A_CLK_P DSI_A_CLK_N DSI_A_D0_P DSI_A_D0_N DSI_A_D1_P DSI_A_D1_N DSI0_CK+ DSI_B_CLK_P DSI_B_CLK_N DSI_B_D0_P DSI_B_D0_N DSI_B_D1_P DSI_B_D1_N DSI1_CK+ DSI_C_CLK_P DSI_C_CLK_N DSI_C_D0_P DSI_C_D0_N DSI_C_D1_P DSI_C_D1_N DSI2_CK+ DSI_D_CLK_P DSI_D_CLK_N DSI_D_D0_P DSI_D_D0_N DSI_D_D1_P DSI_D_D1_N DSI3_CK+ DSI0_CK– DSI0_D0+ DSI0_D0– DSI0_D1+ DSI0_D1– DSI1_CK– DSI1_D0+ DSI1_D0– DSI1_D1+ DSI1_D1– DSI2_CK– DSI2_D0+ DSI2_D0– DSI2_D1+ DSI2_D1– DSI3_CK– JETSON TX2 OEM PRODUCT | DESIGN GUIDE | 20170912 DSI3_D0+ DSI3_D0– DSI3_D1+ DSI3_D1– G33 G34 F34 F35 H32 H33 D33 D34 C34 C35 E32 E33 G30 G31 F31 F32 H29 H30 D30 D31 C31 C32 E29 E30 EMI/ESD CLK_P CLK_N D0_P D0_N D1_P D1_N 1-2 Lanes CLK_P CLK_N D0_P D0_N D1_P D1_N 1-2 Lanes CLK_P CLK_N D0_P D0_N D1_P D1_N 1-2 Lanes CLK_P CLK_N D0_P D0_N D1_P D1_N 1-2 Lanes 36 NVIDIA Jetson TX2 OEM Product Design Guide Figure 19: Display Backlight/Control Connections Jetson TX2 Tegra SYS LCD_BKLT_EN GPIO_DIS3 GPIO_DIS0 GPIO_DIS5 GPIO_DIS1 eDP LCD0_BKLT_PWM LCD1_BKLT_PWM LCD_TE LCD_VDD_EN GPIO_EDP0 B28 B27 A24 Backlight Control A25 Tearing Effect B26 Display Power Enable MIPI DSI / CSI Design Guidelines Table 35. MIPI DSI & CSI Interface Signal Routing Requirements Parameter Max Frequency/Data Rate (per data lane) HS (DSI) HS (CSI) LP Requirement 0.75 / 1.5 1.25 / 2.5 10 1 10 GND 45-50 48 90-100 / 45-50 < 3.8 (24) 2x / 2x 1100 800 350 Units GHz/Gbps MHz Notes Number of Loads load Max Loading (per pin) pF Reference plane See Note 1 Breakout Region Impedance (Single Ended) Ω ±15% Max PCB breakout delay ps Trace Impedance Diff pair / Single Ended Ω Via proximity (Signal to reference) mm (ps) See Note 2 Trace spacing Microstrip / Stripline dielectric mm (ps) Max Trace Delay 1 Gbps See Note 3 1.5 Gbps 2.5 Gbps 1 ps Max Intra-pair Skew See Note 3 5 ps Max Trace Delay Skew between DQ & CLK See Note 3 Keep critical DSI/CSI related traces including DSI/CSI clock/data traces & RDN/RUP traces away from other signal traces or unrelated power traces/areas or power supply components Note: 1. 2. 3. If PWR, 0.01uF decoupling cap required for return current Up to 4 signal Vias can share a single GND return Via If routing to device includes a flex or 2nd PCB, the max trace & skew calculations must include all the PCBs/flex routing MIPI DSI / CSI Connection Guidelines Table 36. MIPI DSI Signal Connections Jetson TX2 Pin Name DSI[3:0]_CK+/– Type DIFF OUT DSI[3:0]_D[1:0]+/– DIFF OUT LCD_TE LCD_BL_EN LCD[1:0]_BKLT_PWM I O O LCD_VDD_EN O Termination Description DSI Differential Clocks: Connect to CLKn & CLKp pins of receiver. See connection diagrams for Dual & Split Link Mode configurations. DSI Differential Data Lanes: Connect to Dn & Dp pins of DSI display. See connection diagrams for Dual & Split Link Mode configurations. LCD Tearing Effect: Connect to LCD Tearing Effect pin if supported LCD Backlight Enable: Connect to LCD backlight solution enable if supported LCD Backlight Pulse Width Modulation: Connect to LCD backlight solution PWM input if supported LCD Power Enable: Connect as necessary to enable appropriate Display power supply(ies). Table 37. Recommended DSI observation (test) points for initial boards Test Points Recommended One for each signal line. Note: Location Near display. Panel connector pins can be used if accessible. Test points must be done carefully to minimize signal integrity impact. Avoid stubs & keep pads small & near signal traces JETSON TX2 OEM PRODUCT | DESIGN GUIDE | 20170912 37 NVIDIA Jetson TX2 OEM Product Design Guide 7.2 eDP / DP / HDMI Jetson TX2 includes two interfaces (DP0 & DP1). Both support eDP / DP or HDMI. See Jetson TX2 Data Sheet for the maximum resolution supported. Table 38. Jetson TX2 HDMI / eDP / DP Pin Descriptions Pin # Jetson TX2 Pin Name Tegra Signal Usage/Description B34 DP0_AUX_CH– DP_AUX_CH0_N B35 DP0_AUX_CH+ H38 H39 F37 F38 G36 G37 H35 H36 B36 A34 Usage on the Carrier Board Direction Pin Type Display Port 0 Aux– or HDMI DDC SDA Bidir DP_AUX_CH0_P Display Port 0 Aux+ or HDMI DDC SCL Bidir AC-Coupled on Carrier Board (eDP/DP) or OpenDrain, 1.8V (3.3V tolerant DDC/I2C) DP0_TX0– DP0_TX0+ DP0_TX1– DP0_TX1+ DP0_TX2– DP0_TX2+ DP0_TX3– DP0_TX3+ DP0_HPD DP1_AUX_CH– HDMI_DP0_TXDN2 HDMI_DP0_TXDP2 HDMI_DP0_TXDN1 HDMI_DP0_TXDP1 HDMI_DP0_TXDN0 HDMI_DP0_TXDP0 HDMI_DP0_TXDN3 HDMI_DP0_TXDP3 DP_AUX_CH0_HPD DP_AUX_CH1_N DisplayPort 0 Lane 0– or HDMI Lane 2– DisplayPort 0 Lane 0+ or HDMI Lane 2+ DisplayPort 0 Lane 1– or HDMI Lane 1– DisplayPort 0 Lane 1+or HDMI Lane 1+ DisplayPort 0 Lane 2– or HDMI Lane 0– DisplayPort 0 Lane 2+ or HDMI Lane 0+ DisplayPort 0 Lane 3– or HDMI Clk Lane– DisplayPort 0 Lane 3+ or HDMI Clk Lane+ Display Port 0 Hot Plug Detect Display Port 1 Aux– or HDMI DDC SDA A35 DP1_AUX_CH+ DP_AUX_CH1_P Display Port 1 Aux+ or HDMI DDC SCL E38 E39 C37 C38 D36 D37 E35 E36 A33 B33 DP1_TX0– DP1_TX0+ DP1_TX1– DP1_TX1+ DP1_TX2– DP1_TX2+ DP1_TX3– DP1_TX3+ DP1_HPD HDMI_CEC HDMI_DP1_TXDN2 HDMI_DP1_TXDP2 HDMI_DP1_TXDN1 HDMI_DP1_TXDP1 HDMI_DP1_TXDN0 HDMI_DP1_TXDP0 HDMI_DP1_TXDN3 HDMI_DP1_TXDP3 DP_AUX_CH1_HPD HDMI_CEC DisplayPort 1 Lane 0– or HDMI Lane 2– DisplayPort 1 Lane 0+ or HDMI Lane 2+ DisplayPort 1 Lane 1– or HDMI Lane 1– DisplayPort 1 Lane 1+ or HDMI Lane 1+ DisplayPort 1 Lane 2– or HDMI Lane 0– DisplayPort 1 Lane 2+ or HDMI Lane 0+ DisplayPort 1 Lane 3– or HDMI Clk Lane– DisplayPort 1 Lane 3+ or HDMI Clk Lane+ Display Port 1 Hot Plug Detect HDMI CEC Note: Output Output Output Output Output Output Output Output Input Bidir Display Connector Bidir Output Output Output Output Output Output Output Output Input Bidir HDMI Type A Conn. AC-Coupled on carrier board CMOS – 1.8V AC-Coupled on Carrier Board (eDP/DP) or OpenDrain, 1.8V (3.3V tolerant DDC/I2C) AC-Coupled on carrier board CMOS – 1.8V Open Drain, 3.3V In the Connection figures & tables, the “x” in the signal/power rail names indicates that the interface can come from either HDMI_DP0 or HDMI_DP1. The interface must include only signals from one or the other (not mixed). Table 39. DP/HDMI Pin Mapping Jetson TX2 Pin Name Jetson TX2 Pin #s Tegra Pin Name Tegra Pin #s HDMI DP H39 H38 F38 F37 G37 G36 H36 H35 HDMI_DP0_TXDP2 HDMI_DP0_TXDN2 HDMI_DP0_TXDP1 HDMI_DP0_TXDN1 HDMI_DP0_TXDP0 HDMI_DP0_TXDN0 HDMI_DP0_TXDP3 HDMI_DP0_TXDN3 E4 E5 C3 B3 A3 B4 C1 C2 TX2+ TX2– TX1+ TX1– TX0+ TX0– TXC+ TXC– TX0+ TX0– TX1+ TX1– TX2+ TX2– TX3+ TX3– E39 E38 C38 C37 D37 D36 E36 E35 HDMI_DP1_TXDP2 HDMI_DP1_TXDN2 HDMI_DP1_TXDP1 HDMI_DP1_TXDN1 HDMI_DP1_TXDP0 HDMI_DP1_TXDN0 HDMI_DP1_TXDP3 HDMI_DP1_TXDN3 A5 A6 C5 B5 D5 D6 C6 B6 TX2+ TX2– TX1+ TX1– TX0+ TX0– TXC+ TXC– TX0+ TX0– TX1+ TX1– TX2+ TX2– TX3+ TX3– DP0 DP0_TX0+ DP0_TX0– DP0_TX1+ DP0_TX1– DP0_TX2+ DP0_TX2– DP0_TX3+ DP0_TX3– DP1 DP1_TX0+ DP1_TX0– DP1_TX1+ DP1_TX1– DP1_TX2+ DP1_TX2– DP1_TX3+ DP1_TX3– JETSON TX2 OEM PRODUCT | DESIGN GUIDE | 20170912 38 NVIDIA Jetson TX2 OEM Product Design Guide 7.2.1 EDP/DP Figure 20: eDP / DP Connection Example See Note 2 3.3V Jetson TX2 DP0/DP1 DP[1:0] 1. Note: 2. 3. DP_AUX_CHx_P DP_AUX_CHx_N DPx_AUX_CH+ DP_AUX_CHx_HPD DPx_HPD DPx_AUX_CH– HDMI_DPx_TXDP0 HDMI_DPx_TXDN0 TXD2_P DPx_TX2/HDMIx_TX0_P TXD2_N DPx_TX2/HDMIx_TX0_N HDMI_DPx_TXDP1 HDMI_DPx_TXDN1 TXD1_P DPx_TX1 / HDMIx_TX1_P TXD1_N DPx_TX1 / HDMIx_TX1_N HDMI_DPx_TXDP2 HDMI_DPx_TXDN2 TXD0_P DPx_TX0 / HDMIx_TX2_P TXD0_N DPx_TX0 / HDMIx_TX2_N HDMI_DPx_TXDP3 HDMI_DPx_TXDN3 TXD3_P DPx_TX3 / HDMIx_TXC_P TXD3_N DPx_TX3 / HDMIx_TXC_N 0.1uF B35/A35 B34/A34 B36/A33 G37/D37 G36/D36 F38/C38 F37/C37 H39/E39 H38/E38 H36/E36 H35/E35 100kΩ Tegra EDP eDP / DP Connector +3.3V 0.1uF 10uF 0.1uF See Note 1 Level Shifter 100kΩ 1kΩ EMI/ ESD AUX+ AUX– HPD EDP_TX2+ 0.1uF EDP_TX1+ 0.1uF 0.1uF EDP_TX1– EDP_TX0+ 0.1uF EMI/ESD 0.1uF EDP_TX0– EDP_TX3+ LN2+ LN2– 0.1uF EDP_TX2– 0.1uF LN0+ LN0– 2-lane 4-lane LN3+ LN3– 0.1uF EDP_TX3– LN1+ LN1– A Level shifter is required on HPD to avoid the pin from being driven when Jetson TX2 is off. The level shifter must be noninverting (preserve the polarity of the HPD signal from the display). Pull-up/down only required for DP – not for eDP. If EMI devices are necessary, they must be tuned to minimize the impact to signal quality, which must meet the timing & electrical requirements of the DisplayPort specification for the modes to be supported. Any ESD solution must also maintain signal integrity & meet the DisplayPort requirements for the modes to be supported. eDP Routing Guidelines Figure 21: eDP / DP (Differential Main Link) Topology Jetson TX2 Common Mode Chokes & ESD Tegra DP Driver P eDP Conn Pkg N Table 40. eDP / DP Main Link Signal Routing Requirements (Including DP_AUX) Parameter Specification Max Data Rate / Min UI Requirement HBR2 HBR RBR Number of Loads / Topology Termination Electrical Spec Insertion Loss E-HBR @ 0.675GHz PBR 0.68GHz HBR 1.35GHz HBR2 @ 2.7GHz Resonance dip frequency TDR dip FEXT @ DC @ 2.7GHz JETSON TX2 OEM PRODUCT | DESIGN GUIDE | 20170912 5.4 / 185 2.7 / 370 1.62 / 617 1 100 <=0.7 <=0.7 <=1.2 <=2.4 >8 >85 <= -40dB <= -30dB Units Gbps / ps load Ω Notes Per data lane Point-Point, Differential, Unidirectional On die at TX/RX dB dB dB dB GHz Ω @ Tr-200ps (10%-90%) IL/FEXT plot – up to HBR2 39 NVIDIA Jetson TX2 OEM Product Design Guide Parameter Impedance Trace Impedance Requirement Diff pair 100 90 85 Units Ω (±10%) Notes - Reference Plane Trace Length, Spacing & Skew Trace loss characteristic @ 2.7GHz GND < 0.81 Max PCB Via dist. from module conn. RBR/HBR HBR2 Max trace length from module to connector RBR/HBR (Stripline / Microstrip) HBR2 (Stripline) HBR2 (Microstrip, 5x / 7x) Trace spacing (Pair-Pair) Stripline Microstrip (HBR/RBR) Microstrip (HBR2) Trace spacing Stripline/Microstrip (Main Link to AUX) Max Intra-pair (within pair) Skew No requirement 7.63 (0.3) 165 (1137.5)/(975) 101.6 (700) 89 (525) / 101.6 (600) 3x 4x 5x to 7x 3x / 5x 0.15 (1) dB/in The following max length is derived based on this characteristic. See note 2. mm (in) mm (ps) 175ps/inch assumption for Stripline, 150ps/inch for Microstrip. dielectric dielectric mm (ps) - Max Inter-pair (pair-pair) Skew Via Max GND transition Via distance Via Structure Impedance dip Recommended via dimension for impedance control 100Ω is the spec. target. 95/85Ω are implementation options (Zdiff does not account for trace coupling) 95Ω should be used to support DP-HDMI colayout as HDMI 2.0 requires 100Ω impedance (see HDMI section for addition of series resistor RS). 85Ω can be used if eDP/DP only & is preferable as it can provide better trace loss characteristic performance. See Note 1. Drill/Pad Antipad Via pitch JETSON TX2 OEM PRODUCT | DESIGN GUIDE | 20170912 Do not perform length matching within breakout region Do trace length matching before hitting discontinuity (i.e. matching to <1ps before the vias or any discontinuity to minimize common mode conversion). 150 ps < 1x diff pair pitch For signals switching reference layers, add symmetrical GND stitching Via near signal Vias. ≥97 ≥92 Ω @ 200ps Ω @ 35ps The via dimension must be required for the HDMIDP co-layout condition. 200/400 >840 ≥880 um um um 40 NVIDIA Jetson TX2 OEM Product Design Guide Parameter Topology Requirement Units Y-pattern is recommended keep symmetry Notes Xtalk suppression is best using the Y-pattern. It can also reduce the limit of pair-pair distance. For in-line via, the distance from a via of one lane to the adjacent via from other lane >= 1.2mm center-center. GND via Max # of Vias PTH vias Micro Vias Max Via Stub Length Serpentine Min bend angle Dimension AC Cap Value Max Dist. from AC cap to connector Voiding Connector Voiding Min A Spacing Min B, C Length Min Jog Width Place GND via as symmetrically as possible to data pair vias. Up to 4 signal vias (2 diff pairs) can share a single GND return via 4 if all vias are PTH via Not limited as long as total channel loss meets IL spec 0.4 mm GND via is used to maintain return path, while its Xtalk suppression is limited 135 4x 1.5x 3x S1 must be taken care in order to consider Xtalk to adjacent pair RBR/HBR HBR2 RBR/HBR HBR2 0.1 No requirement 0.5 No requirement Voiding required RBR/HBR HBR2 No requirement Voiding required deg (a) Trace width uF Discrete 0402 in HBR2: Voiding the plane directly under the pad 34 mils larger than the pad size is recommended. HBR2: Standard DP Connector: Voiding requirement is stack-up dependent. For typical stack-ups, voiding on the layer under the connector pad is required to be 5.7mil larger than the connector pad. Keep critical eDP related traces including differential clock/data traces & RSET trace away from other signal traces or unrelated power traces/areas or power supply components Notes: 1. 2. 3. 4. For eDP/DP, the spec puts a higher priority on the trace loss characteristic than on the impedance. However, before selecting 85Ω for impedance, it is important to make sure the selected stack-up, material & trace dimension can achieve the needed low loss characteristic. Longer trace lengths may be possible if the total trace loss is equal to or better than the target. If the loss is greater, the max trace lengths will need to be reduced. The average of the differential signals is used for length matching. Do not perform length matching within breakout region. Recommend doing trace length matching to <1ps before Vias or any discontinuity to minimize common mode conversion JETSON TX2 OEM PRODUCT | DESIGN GUIDE | 20170912 41 NVIDIA Jetson TX2 OEM Product Design Guide Table 41. eDP Signal Connections Jetson TX2 Pin Name DPx_TX[3:0]+/– Type DPx_AUX+/– DPx_HPD I/OD I O Termination Description Series 0.1uF capacitors on all lines eDP/DP Differential CLK/Data Lanes: Connect to matching pins on display connector. See DP/HDMI Pin Mapping & connection diagram for details. eDP/DP: Auxiliary Channels: Connect to AUX_CH+/– on display connector. eDP/DP: Hot Plug Detect: Connect to HPD pin on display connector. Series 0.1uF capacitors Table 42. Recommended eDP/DP observation (test) points for initial boards Test Points Recommended One for each signal line. Note: Location Near display connector. Connector pins can be used if accessible. Test points must be done carefully to minimize signal integrity impact. Avoid stubs & keep pads small & near signal traces 7.2.2 HDMI A standard DP 1.2a or HDMI V2.0 interface is supported. These share the same set of interface pins, so either Display Port or HDMI can be supported natively. Dual-Mode DisplayPort(DP++ ) can be supported, in which the DisplayPort connector logically outputs TMDS signaling to a DP-to-HDMI dongle. 7.2.3 HDMI Figure 22: HDMI Connection Example Jetson TX2 VDD_1V8 VDD_3V3_SYS HDMI Connector VDD_5V0_HDMI eDP DP_AUX_CH1_P DP_AUX_CH1_N DPx_AUX_CH+ HDMI_CEC HDMI_CEC 10kΩ 10kΩ DP0/DP1 B3 6/A33 0.1uF 1.8kΩ DPx_HPD See Note 1 Level Shifter 1.8kΩ DP_AUX_CH1_HPD 10kΩ +5V Tegra - HDMI 10uF 100kΩ HPD EMI HDMI_DPx HDMI_DPx_TXDP0 HDMI_DPx_TXDN0 TXD0_P TXD0_N DPx_TX2/HDMIx_TX0_N HDMI_DPx_TXDP1 HDMI_DPx_TXDN1 TXD1_P TXD1_N DPx_TX1 / HDMIx_TX1_N HDMI_DPx_TXDP2 HDMI_DPx_TXDN2 TXD2_P DPx_TX0 / HDMIx_TX2_P TXD2_N DPx_TX0 / HDMIx_TX2_N HDMI_DPx_TXDP3 HDMI_DPx_TXDN3 TXC_P TXC_N DPx_TX3 / HDMIx_TXC_N DPx_TX2/HDMIx_TX0_P DPx_TX1 / HDMIx_TX1_P DPx_TX3 / HDMIx_TXC_P B3 3 G37/D37 G36/D36 SCL SDA Level Shifter B3 5/A35 B3 4/A34 CEC Gating Circuitry 100kΩ DPx_AUX_CH– CEC See Note 2 ESD RS 0.1uF 0.1uF RS RS 0.1uF F38/C3 8 F37/C3 7 0.1uF H39/E3 9 H38/E3 8 0.1uF RS H36/E3 6 0.1uF 0.1uF RS H35/E3 5 RS CMC 0.1uF RS RS See Note 3 See Note 2 , 1% ESD See Note 4 CK+ CKD0+ D0D1+ D1D2+ D2- 00 @100MHz 5V0_HDMI_EN Note: 1. 2. 3. 4. Enable FET Level shifters required on DDC/HPD. Jetson TX2 pads are not 5V tolerant & cannot directly meet HDMI VIL/VIH requirements. HPD level shifter can be non-inverting or inverting. If EMI/ESD devices are necessary, they must be tuned to minimize the impact to signal quality, which must meet the timing & electrical requirements of the HDMI specification for the modes to be supported. See requirements & recommendations in the related sections of the HDMI Interface Signal Routing Requirements table. The HDMI_DP_TXx pads are native DP pads & require series AC capacitors (ACCAP) & pull-downs (RPD) to be HDMI compliant. The 499Ω, 1% pull-downs must be disabled when Tegra is off to meet the HDMI VOFF requirement. The enable to the FET, enables the pull-downs when the HDMI interface is to be used. Chokes between pull-downs & FET are required for Standard Technology designs and recommended for HDI designs. Series resistors RS are required. See the RS section of the HDMI Interface Signal Routing Requirements table for details. JETSON TX2 OEM PRODUCT | DESIGN GUIDE | 20170912 42 NVIDIA Jetson TX2 OEM Product Design Guide Figure 23: HDMI Clk/Data Topology Common Mode Chokes & ESD AC CAP Jetson TX2 Main Route – Seg A 95-100Ω Tegra 0.1uF 0.1uF RS (See note 4) Seg B 100Ω * Note 3 Seg D 100Ω * Note 3 Seg E 100Ω * Note 3 Seg F 100Ω * Note 3 100Ω 100Ω 100Ω 100Ω 95-100Ω Seg C HDMI Conn See Note 1 PCB Vias RPD 499Ω, 1% 499Ω, 1% PCB Vias 3.3V Note: Choke or Trace See Note 2 RPD pad must be on the main trace. RPD & ACCAP must be on same layer. Chokes (600Ω@100MHz) or narrow traces (1uH@DC-100MHz) between pull-downs & FET are required for Standard Technology (through-hole) designs and recommended for HDI designs. The trace after the main-route via should be routed on the Top or Bottom layer of the PCB, and either with 100ohm differential impedance, or as uncoupled 50ohm Single Ended traces. RS series resistor is required. See the RS section of the HDMI Interface Signal Routing Requirements table for details. 1. 2. 3. 4. Table 43. HDMI Interface Signal Routing Requirements Parameter Specification Max Frequency / UI Topology Termination Requirement Units 5.94 / 168 Point to point At Receiver 100 On-board 500 Gbps / ps Ω Electrical Specification IL TDR dip <= 1.7 <= 2 <= 3 <6 resonance dip frequency > 12 >= 85 FEXT (PSFEXT) dB @ 1GHz dB @ 1.5GHz dB @ 3GHz dB @ 6GHz GHz Ω @ Tr=200ps <= -50 <= -40 <= -40 dB at DC dB at 3GHz dB at 6GHz IL/FEXT plot Impedance Trace Impedance Reference plane Trace spacing/Length/Skew Trace loss characteristic: Diff pair 100 Notes Per lane – not total link bandwidth Unidirectional, Differential Differential To 3.3V at receiver To GND near connector 10%-90%. If TDR dip is 75~85ohm that dip width should < 250ps PSNEXT is derived from an algebraic summation of the individual NEXT effects on each pair by the other pairs TDR plot Ω ±10%. Target is 100Ω. 95Ω for the breakout & main route is an implementation option. GND < 0.8 < 0.4 JETSON TX2 OEM PRODUCT | DESIGN GUIDE | 20170912 dB/in. @ 3GHz dB/in. @ 1.5GHz The max length is derived based on this characteristic. See note 1. 43 NVIDIA Jetson TX2 OEM Product Design Guide Parameter Trace spacing (Pair-Pair) Requirement Stripline Microstrip: pre 1.4b Microstrip: 1.4b/2.0 Trace spacing Stripline (Main Link to DDC) Microstrip Max Total Delay (1.4b/2.0 - up to 5.94Gbps) Stripline Microstrip (5x spacing) Microstrip (7x spacing) Max Total Delay (Pre-1.4b) (up to 165Mhz) Microstrip Stripline Max Intra-Pair (within pair) Skew Max Inter-Pair (pair to pair) Skew Max GND transition Via distance Via Topology 3x 4x 5x to 7x 3x 5x 63.5/2.5 (437) 50.8/2.0 (300) 63.5/2.5 (375) 254/10 (1500) 225/8.5 (1500) 0.15 (1) 150 1x 8. Y-pattern is recommended 9. keep symmetry 97 92 Minimum Impedance Dip Recommended Via Dimension drill/pad Antipad Via pitch GND via Connector pin via - Max Via Stub Length Serpentine Min bend angle PTH via u-via dielectric dielectric Notes For Stripline, this is 3x of the thinner of above and below. For Stripline, this is 3x of the thinner of above and below. Propagation delay: 175ps/in. for stripline, 150ps/in. for microstrip). mm/in (ps) mm/in (ps) Propagation delay: 175ps/in. for stripline, 150ps/in. for microstrip). Mm (ps) ps Diff pair via pitch See Notes 2, 3 & 4 See Notes 2, 3 & 4 For signals switching reference layers, add one or two ground stitching vias. It is recommended they be symmetrical to signal vias. Ω@200ps Ω@35ps 200/400 uM 840 880 Place GND via as symmetrically as possible to data pair vias. Up to 4 signal vias (2 diff pairs) can share a single GND return via The break-in trace to the connector pin via should - Max # of Vias Units Xtalk suppression is the best by Y-pattern. Also it can reduce the limit of pair-pair distance. Need review (NEXT/FEXT check) if via placement is not Ypattern. GND via is used to maintain return path, while its Xtalk suppression is limited be routed on the BOTTOM in order to avoid via stub effect Equal spacing (0.8mm) between adjacent signal vias. The x-axis distance between signal and GND via should be > 0.6mm 4 if all vias are PTH via Not limited as long as total channel loss meets IL spec. No breakout: ≤ 3 vias 0.4 mm 135 deg (a) JETSON TX2 OEM PRODUCT | DESIGN GUIDE | 20170912 breakout on the same layer as main trunk: ≤ 4 vias long via stub requires review (IL & resonance dip check) 44 NVIDIA Jetson TX2 OEM Product Design Guide Parameter Dimension Min A Spacing Min B, C Length Min Jog Width Requirement 4x 1.5x 3x Units Trace width Topology The main-route via dimensions should comply with the via structure rules (See Via section) For the connector pin vias, follow the rules for the connector pin vias (See Via section) The traces after main-route via should be routed as 100Ω differential or as uncoupled 50ohm Single-ended traces on PCB Top or Bottom. 1 mm Max distance from RPD to main trace (seg B) Max distance from AC cap to RPD ~0 mm stubbing point (seg A) Max distance between ESD and 3 mm signal via Add-on Components Example of a case where space is Top limited for placing components. AC Cap Value Max via distance from BGA Location 0.1 uF 7.62 (52.5) mm (ps) must be placed before pull-down resistor Notes S1 must be taken care in order to consider Xtalk to adjacent pair See topology figure above table Bottom The distance between the AC cap and the HDMI connector is not restricted. Placement PTH design Place cap on bottom layer if main-route above core Place cap on top layer if main-route below core Micro-Via design Not Restricted Void GND (or PWR) void under/above the cap is needed. Void size = SMT area + 1x dielectric height keepout distance Pull-down Resistor (RPD), choke/FET Value 500 Ω Location. Must be placed after AC cap Layer of placement Same layer as AC cap. The FET & choke can be placed on the opposite layer thru a PTH via Choke between RPD & FET Choke 600 or Ω@100MHz 1 uH@DC-100MHz Max Trace Rdc ≤20 mΩ Max Trace length 4 mm Void GND/PWR void under/above cap is preferred Common-Mode Choke (Stuffing option – not added unless EMI issue is seen) Common-mode Min 65 Ω impedance @ 100MHz Max 90 RDC <=0.3ohm Differential TDR impedance 90ohm +/-15% @ Tr=200ps (10%-90%) JETSON TX2 OEM PRODUCT | DESIGN GUIDE | 20170912 Can be choke or Trace. Recommended option for HDMI2.0 HF1-9 improvement. TDK ACM2012D-900-2P 45 NVIDIA Jetson TX2 OEM Product Design Guide Parameter Min Sdd21 @ 2.5GHz Max Scc21 @ 2.5GHz Location Requirement Units 2.22 dB 19.2 dB Close to any adjacent discontinuity (< 8mm) – such as connector, via, etc. Notes ESD (On-chip protection diode is able to withstand 2kV HMM. External ESD is optional. Designs should include ESD footprint as a stuffing option) Max junction capacitance 0.35 pF e.g. ON-semiconductor ESD8040 (IO to GND) Footprint Pad right on the net instead of trace stub Location Void After pull-down resistor/CMC and before RS GND/PWR void under/above the cap is needed. Void size = 1mm x 2mm for 1 pair Series Resistor (RS) – Series resistor on P/N path for HDMI 2.0 (Mandatory) Value ≤6 Location Void ± 10%. 0ohm is acceptable if the design passes the HDMI2.0 HF1-9 test. Otherwise, adjust the RS value to ensure the HDMI2.0 tests pass: Eye diagram, Vlow test and HF1-9 TDR test After all components and before HDMI connector GND/PWR void under/above the RS device is needed. Void size = SMT area + 1x dielectric height keepout distance. Trace at Component Region Value Location Trace entering the SMT pad Trace between components HDMI Connector Connector Voiding General Routing over Voids Noise Coupling Note: Ω 1. 2. 3. 4. 100 At component region (Microstrip) One 45° Ω ± 10% Uncoupled structure Voiding the ground below the signal lanes 0.1448(5.7mil) larger than the pin itself Routing over voids not allowed except void around device ball/pin the signal is routed to. Keep critical HDMI related traces including differential clock/data traces & RSET trace away from other signal traces or unrelated power traces/areas or power supply components Longer trace lengths may be possible if the total trace loss is equal to or better than the target. If the loss is greater, the max trace lengths will need to be reduced. The average of the differential signals is used for length matching. Do not perform length matching within breakout region. Recommend doing trace length matching to <1ps before vias or any discontinuity to minimize common mode conversion If routing includes a flex or 2nd PCB, the max trace delay & skew calculations must include all the PCBs/flex routing. Solutions with flex/2nd PCB may not achieve maximum frequency operation. JETSON TX2 OEM PRODUCT | DESIGN GUIDE | 20170912 46 NVIDIA Jetson TX2 OEM Product Design Guide Table 44. HDMI Signal Connections Jetson TX2 Pin Name DPx_TX3+/– DPx_HPD Type DIFF OUT DIFF OUT I HDMI_CEC I/OD DPx_AUX_CH+/– I/OD HDMI 5V Supply P DPx_TX[2:0] +/– Note: Termination (see note on ESD) 0.1uF series ACCAP → 500Ω RPD (controlled by FET) → EMI/ESD (if required),.≤6Ω RS (series resistor) Jetson TX2 to Connector: 10kΩ PU to 1.8V → level shifter → 100kΩ series resistor. 100kΩ to GND on connector side. Gating circuitry, See connection figure or reference schematics for details. From Jetson TX2 to Connector: 10kΩ PU to 3.3V → level shifter → 1.8kΩ PU to 5V → connector pin Adequate decoupling (0.1uF & 10uF recommended) on supply near connector. Description HDMI Differential Clock: Connect to C–/C+ & pins on HDMI Connector HDMI Differential Data: Connect to D[2:0]+/– pins. See DP/HDMI Pin Mapping table and connection diagram. HDMI Hot Plug Detect: Connect to HPD pin on HDMI Connector HDMI Consumer Electronics Control: Connect to CEC on HDMI Connector through circuitry. HDMI: DDC Interface – Clock and Data: Connect DP1_AUX_CH+ to SCL & DP1_AUX_CH– to SDA on HDMI Connector HDMI 5V supply to connector: Connect to +5V on HDMI Connector. Any ESD and/or EMI solutions must support targeted modes (frequencies). Table 45. Recommended HDMI / DP observation (test) points for initial boards Test Points Recommended One for each signal line. Note: Location Near display connector. Connector pins can be used if accessible. Test points must be done carefully to minimize signal integrity impact. Avoid stubs & keep pads small & near signal traces Figure 24: Optional Dual-Mode (DP/HDMI) Connections 5.0V 10kΩ 10kΩ DP_MODE* 10kΩ 10nF DP_AUX_CHx_P DP_AUX 100kΩ 0.1uF To Jetson TX2 CONFIG1 10kΩ To DP Connector Gated 100kΩ 3.3V DP_MODE* 100kΩ DP_AUX_CHx_N DP_AUX* 100kΩ 0.1uF DP Interface Signal Routing Requirements See eDP/DP Signal Routing Requirements. JETSON TX2 OEM PRODUCT | DESIGN GUIDE | 20170912 47 NVIDIA Jetson TX2 OEM Product Design Guide 8.0 MIPI CSI (VIDEO INPUT) Jetson TX2 supports three MIPI CSI x4 bricks, allowing a variety of device types and combinations to be supported. Up to three quad lane stereo cameras or 6 dual lane camera streams are available. Each data lane has a peak bandwidth of up to 2.5Gbps. Note: Maximum data rate may be limited by use case / memory bandwidth. Table 46. Jetson TX2 CSI Pin Descriptions Pin # Jetson TX2 Pin Name Tegra Signal Usage/Description G27 G28 F28 F29 H26 H27 D27 D28 C28 C29 E26 E27 G24 G25 F25 F26 H23 H24 D24 D25 C25 C26 E23 E24 G21 G22 F22 F23 H20 H21 D21 D22 C22 C23 E20 E21 CSI0_CLK– CSI0_CLK+ CSI0_D0– CSI0_D0+ CSI0_D1– CSI0_D1+ CSI1_CLK– CSI1_CLK+ CSI1_D0– CSI1_D0+ CSI1_D1– CSI1_D1+ CSI2_CLK– CSI2_CLK+ CSI2_D0– CSI2_D0+ CSI2_D1– CSI2_D1+ CSI3_CLK– CSI3_CLK+ CSI3_D0– CSI3_D0+ CSI3_D1– CSI3_D1+ CSI4_CLK– CSI4_CLK+ CSI4_D0– CSI4_D0+ CSI4_D1– CSI4_D1+ CSI5_CLK– CSI5_CLK+ CSI5_D0– CSI5_D0+ CSI5_D1– CSI5_D1+ CSI_A_CLK_N CSI_A_CLK_P CSI_A_D0_N CSI_A_D0_P CSI_A_D1_N CSI_A_D1_P CSI_B_CLK_N CSI_B_CLK_P CSI_B_D0_N CSI_B_D0_P CSI_B_D1_N CSI_B_D1_P CSI_C_CLK_N CSI_C_CLK_P CSI_C_D0_N CSI_C_D0_P CSI_C_D1_N CSI_C_D1_P CSI_D_CLK_N CSI_D_CLK_P CSI_D_D0_N CSI_D_D0_P CSI_D_D1_N CSI_D_D1_P CSI_E_CLK_N CSI_E_CLK_P CSI_E_D0_N CSI_E_D0_P CSI_E_D1_N CSI_E_D1_P CSI_F_CLK_N CSI_F_CLK_P CSI_F_D0_N CSI_F_D0_P CSI_F_D1_N CSI_F_D1_P Camera, CSI 0 Clock– Camera, CSI 0 Clock+ Camera, CSI 0 Data 0– Camera, CSI 0 Data 0+ Camera, CSI 0 Data 1– Camera, CSI 0 Data 1+ Camera, CSI 1 Clock– Camera, CSI 1 Clock+ Camera, CSI 1 Data 0– Camera, CSI 1 Data 0+ Camera, CSI 1 Data 1– Camera, CSI 1 Data 1+ Camera, CSI 2 Clock– Camera, CSI 2 Clock+ Camera, CSI 2 Data 0– Camera, CSI 2 Data 0+ Camera, CSI 2 Data 1– Camera, CSI 2 Data 1+ Camera, CSI 3 Clock– Camera, CSI 3 Clock+ Camera, CSI 3 Data 0– Camera, CSI 3 Data 0+ Camera, CSI 3 Data 1– Camera, CSI 3 Data 1+ Camera, CSI 4 Clock– Camera CSI 4 Clock+ Camera, CSI 4 Data 0– Camera, CSI 4 Data 0+ Camera, CSI 4 Data 1– Camera, CSI 4 Data 1+ Camera, CSI 5 Clock– Camera, CSI 5 Clock+ Camera, CSI 5 Data 0– Camera, CSI 5 Data 0+ Camera, CSI 5 Data 1– Camera, CSI 5 Data 1+ Usage on the Carrier Board Camera Connector Direction Pin Type Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input MIPI D-PHY Direction Pin Type Output Output Output Output Output Output Output Output Output Output CMOS – 1.8V CMOS – 1.8V CMOS – 1.8V CMOS – 1.8V CMOS – 1.8V CMOS – 1.8V CMOS – 1.8V CMOS – 1.8V CMOS – 1.8V CMOS – 1.8V Table 47. Jetson TX2 Camera Miscellaneous Pin Descriptions Pin # Jetson TX2 Pin Name Tegra Signal Usage/Description F9 F8 E7 G8 F7 H8 H7 G7 D7 E8 CAM0_MCLK CAM1_MCLK CAM2_MCLK GPIO0_CAM0_PWR# GPIO1_CAM1_PWR# GPIO2_CAM0_RST# GPIO3_CAM1_RST# GPIO4_CAM_STROBE GPIO5_CAM_FLASH_EN CAM_VSYNC EXTPERIPH1_CLK EXTPERIPH2_CLK GPIO_CAM2 QSPI_SCK GPIO_CAM3 QSPI_CS_N QSPI_IO0 GPIO_SEN5 UART5_RTS_N QSPI_IO1 Camera 0 Reference Clock Camera 1 Reference Clock Camera 2 Master Clock Camera 0 Powerdown or GPIO Camera 1 Powerdown or GPIO Camera 0 Reset or GPIO Camera 1 Reset or GPIO Camera Strobe or GPIO Camera Flash Enable or GPIO Camera Vertical Sync JETSON TX2 OEM PRODUCT | DESIGN GUIDE | 20170912 Usage on the Carrier Board Camera Connector 48 NVIDIA Jetson TX2 OEM Product Design Guide Table 48. CSI Configurations Camera # CSI Lanes CSI_0_CLK CSI_0_D[1:0] CSI_1_CLK CSI_1_D[1:0] CSI_2_CLK CSI_2_D[1:0] CSI_3_CLK CSI_3_D[1:0] CSI_4_CLK CSI_4_D[1:0] CSI_5_CLK CSI_5_D[1:0] Note: 1. 2. #1 2-Lane Configurations #3 #4 #2 #5 #6 √ √ #1 4-Lane Configurations #2 #3 √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ Each 2-lane options shown above can also be used for one single lane camera as well Combinations of 1, 2 & 4-lane cameras are supported, as long as any 4-lane cameras match one of the three configurations above Figure 25: Camera Control Connections Jetson TX2 Tegra 1kΩ VDD_1V8 1kΩ UART/CAM I2C_CAM_CLK CAM_I2C_SCL CAM_I2C_SDA EXTPERIPH1_CLK EXTPERIPH2_CLK GPIO_CAM2 GPIO_CAM3 UART5_RTS I2C_CAM_DAT 120Ω CAM0_MCLK 120Ω GPIO0_CAM0_PWR# 120Ω GPIO2_CAM0_RST# CAM1_MCLK GPIO1_CAM1_PWR# GPIO3_CAM1_RST# QSPI_SCK QSPI_CS QSPI_IO1 QSPI_IO0 SPI CAM2_MCLK CAM_VSYNC GPIO4_CAM_STROBE GPIO5_CAM_FLASH_EN AO Note: Camera I2C C6 D6 F9 Camera 0 Clock/Control G8 H8 EMI F8 & F7 H7 CAM_AF_EN ESD Camera 1 Clock/Control E7 Camera 2 Clock E8 Misc. Camera Strobe/Flash G7 D7 GPIO_SEN5 1. 2. If Jetson TX2 is providing flash control (as shown), GPIO5_CAM_FLASH_EN & GPIO4_CAM_STROBE must be used. Any EMI/ESD devices must be tuned to minimize impact to signal quality and meet the timing & Vil/Vih requirements at the receiver & maintain signal quality and meet requirements for the frequencies supported by the design. JETSON TX2 OEM PRODUCT | DESIGN GUIDE | 20170912 49 NVIDIA Jetson TX2 OEM Product Design Guide Figure 26: Camera CSI Connections Jetson TX2 Tegra DSI/CSI Note: CSI_A_CLK_P CSI_A_CLK_N CSI_A_D0_P CSI_A_D0_N CSI_A_D1_P CSI_A_D1_N CSI0_CK+ CSI_B_CLK_P CSI_B_CLK_N CSI_B_D0_P CSI_B_D0_N CSI_B_D1_P CSI_B_D1_N CSI1_CK+ CSI_C_CLK_P CSI_C_CLK_N CSI_C_D0_P CSI_C_D0_N CSI_C_D1_P CSI_C_D1_N CSI2_CK+ CSI_D_CLK_P CSI_D_CLK_N CSI_D_D0_P CSI_D_D0_N CSI_D_D1_P CSI_D_D1_N CSI3_CK+ CSI_E_CLK_P CSI_E_CLK_N CSI_E_D0_P CSI_E_D0_N CSI_E_D1_P CSI_E_D1_N CSI4_CK+ CSI_F_CLK_P CSI_F_CLK_N CSI_F_D0_P CSI_F_D0_N CSI_F_D1_P CSI_F_D1_N CSI5_CK+ CSI0_CK– CSI0_D0+ CSI0_D0– CSI0_D1+ CSI0_D1– CSI1_CK– CSI1_D0+ CSI1_D0– CSI1_D1+ CSI1_D1– CSI2_CK– CSI2_D0+ CSI2_D0– CSI2_D1+ CSI2_D1– CSI3_CK– CSI3_D0+ CSI3_D0– CSI3_D1+ CSI3_D1– CSI4_CK– CSI4_D0+ CSI4_D0– CSI4_D1+ CSI4_D1– CSI5_CK– CSI5_D0+ CSI5_D0– CSI5_D1+ CSI5_D1– G28 G27 F29 2-Lane F28 H27 4-Lane (B_CLK not used) H26 D28 D27 C29 2-Lane C28 E27 E26 G25 G24 F26 F25 H24 H23 D25 EMI 2-Lane & 4-Lane (D_CLK not used) ESD D24 C26 C25 2-Lane E24 E23 G22 G21 F23 F22 2-Lane H21 4-Lane (F_CLK not used) H20 D22 D21 C23 C22 2-Lane E21 E20 Any EMI/ESD devices must be tuned to minimize impact to signal quality and meet the timing & Vil/Vih requirements at the receiver & maintain signal quality and meet requirements for the frequencies supported by the design. CSI Design Guidelines CSI & DSI use the MIPI D-PHY for the physical interface. The routing & connection requirements are found in the DSI section. Table 49. MIPI CSI Signal Connections Jetson TX2 Pin Name CSI[5:0]_CLK+/– CSI[5:0]_D[1:0]+/– Note: Type Termination Description I See note I/O See note CSI Differential Clocks: Connect to clock pins of camera. See the CSI Configurations tables for details CSI Differential Data Lanes: Connect to data pins of camera. See the CSI Configurations tables for details Depending on the mechanical design of the platform and camera modules, ESD protection may be necessary. In addition, EMI control may be needed. Both are shown in the Camera Connection Example diagram. Any EMI/ESD solution must be compatible with the frequency required by the design. JETSON TX2 OEM PRODUCT | DESIGN GUIDE | 20170912 50 NVIDIA Jetson TX2 OEM Product Design Guide Table 50. Miscellaneous Camera Connections Jetson TX2 Pin Name I2C_CAM_CLK I2C_CAM_DAT CAM[2:0]_MCLK GPIO1_CAM1_PWR# GPIO0_CAM0_PWR# GPIO4_CAM_STROBE Type O I/O O Termination 1kΩ Pull-ups VDD_1V8 (on Jetson TX2). See note related to EMI/ESD under MIPI CSI Signal Connections tables. 120Ω Bead in series (on Jetson TX2) See note related to EMI/ESD under MIPI CSI Signal Connections tables. I/O GPIO5_CAM_FLASH_EN GPIO3_CAM1_RST# GPIO2_CAM0_RST# O O CAM_VSYNC O See note related to ESD under MIPI CSI Signal Connections tables. Description Camera I2C Interface: Connect to I2C SCL & SDA pins of imager Camera Master Clocks: Connect to Camera reference clock inputs. Camera Power Control signals (or GPIOs [1:0]): Connect to powerdown pins on camera(s). Camera Strobe Enable (or GPIO 4): Connect to camera strobe circuit unless strobe control comes from camera module. Camera Flash Enable: Connect to enable of flash circuit Camera Resets (or GPIO [3:2]): Connect to reset pin on any cameras with this function. If AutoFocus Enable is required, connect GPIO3_CAM1_RST# to AF_EN pin on camera module & use GPIO2_CAM0_RST# as common reset line. Camera Vertical Sync Table 51. Recommended CSI observation (test) points for initial boards Test Points Recommended One per signal line. Note: Location Near Jetson TX2 pins Test points must be done carefully to minimize signal integrity impact. Avoid stubs & keep pads small & near signal traces JETSON TX2 OEM PRODUCT | DESIGN GUIDE | 20170912 51 NVIDIA Jetson TX2 OEM Product Design Guide 9.0 SDIO/SDCARD/EMMC Jetson TX2 has four SD/MMC interfaces. Three are used on Jetson TX2 for eMMC, WLAN/BT & Ethernet. One is brought to the connector pins for SD Card or SDIO use. Table 52. Jetson TX2 SDMMC Pin Descriptions Usage on the Carrier Board Pin # Jetson TX2 Pin Name Tegra Signal Usage/Description G18 G19 H18 H17 F19 F18 F17 H16 F20 SDCARD_CLK SDCARD_CMD SDCARD_D0 SDCARD_D1 SDCARD_D2 SDCARD_D3 SDCARD_CD# SDCARD_PWR_EN SDCARD_WP SDMMC1_CLK SDMMC1_CMD SDMMC1_DAT0 SDMMC1_DAT1 SDMMC1_DAT2 SDMMC1_DAT3 GPIO_EDP2 GPIO_EDP3 GPIO_EDP1 SD Card (or SDIO) Clock SD Card (or SDIO) Command SD Card (or SDIO) Data 0 SD Card (or SDIO) Data 1 SD Card (or SDIO) Data 2 SD Card (or SDIO) Data 3 SD Card Card Detect SD Card power switch Enable SD Card Write Protect SD Card Direction Pin Type Output Bidir Bidir Bidir Bidir Bidir Input Output Input CMOS – 3.3/1.8V CMOS – 3.3/1.8V CMOS – 3.3V/1.8V CMOS – 3.3V/1.8V CMOS – 3.3/1.8V CMOS – 3.3/1.8V CMOS – 1.8V CMOS – 1.8V CMOS – 1.8V Table 53. SDIO / SD Card / eMMC Interface Mapping Jetson TX2 Pins SDCARD Tegra Interface SDMMC1 Width 4-bit N/A N/A N/A SDMMC2 SDMMC3 SDMMC4 4-bit 4-bit 8-bit Usage SD (Primary SD Card). Can be used instead for SDIO interface. Pins used for EQOS for Ethernet on Jetson TX2 Used on Jetson TX2 for WLAN/BT Used on Jetson TX2 - eMMC 9.1 SD Card The Figure shows a standard SD socket. Internal pull-up resistors are used for SDCARD Data/CMD lines, so external pull-ups are not required. Figure 27. SD Card Socket Connection Example VDD_3V3_SYS 4.7kΩ D Jetson TX2 G S Tegra SDMMC1 SDMMC1_CLK SDMMC1_CMD SDMMC1_DAT0 SDMMC1_DAT1 SDMMC1_DAT2 SDMMC1_DAT3 EDP SDCARD_CLK 120Ω@100MHz SDCARD_CMD SDCARD_D0 SDCARD_D1 SDCARD_D2 SDCARD_D3 GPIO_EDP3 SDCARD_PWR_EN GPIO_EDP2 SDCARD_CD# G18 Load Switch VIN VOUT ON 10Ω DATA2 10Ω DATA3 10Ω CMD GND G19 VDD H18 H17 CLK 0Ω F19 GND F18 H16 F17 SDMMC_VDD_EN 10Ω DATA0 10Ω DATA1 SDMMC1_ CD* C_DETECT COMMON C_WR_PROTECT ESD GPIO_EDP1 Notes: 1. 2. SDCARD_WP F20 SDMMC1_ WP If EMI and/or ESD devices are necessary, they must be tuned to minimize the impact to signal quality, which must meet the timing & Vil/Vih requirements at the receiver & maintain signal quality and meet requirements for the frequencies supported by the design. Supply (load switch, etc) used to provide power to the SD Card must be current limited if the supply is shorted to GND. JETSON TX2 OEM PRODUCT | DESIGN GUIDE | 20170912 52 NVIDIA Jetson TX2 OEM Product Design Guide Table 54. SDCARD Interface Signal Routing Requirements Parameter Max Frequency 3.3V Signaling DS HS SDR12 SDR25 SDR50 SDR104 DDR50 1.8V Signaling Topology Reference plane Trace Impedance Max Via Count Via proximity (Signal to reference) Trace spacing Trace length SDR50 / SDR25 / SDR12 / HS / DS PTH HDI Microstrip / Stripline Min Max Min Max SDR104 / DDR50 Requirement 25 (12.5) 50 (25) 25 (12.5) 50 (25) 100 (50) 208 (104) 50 (50) Point to point GND or PWR 50 4 10 < 3.8 (24) 4x / 3x Units MHz (MB/s) Ω mm (ps) dielectric 16 (100) 139 (876) 16 (100) 83 (521) Notes See Note 1 See Note 2 ±15%. 45Ω optional depending on stack-up Independand of stackup layers Depends on stackup layers Up to 4 signal Vias can share 1 GND return Via mm (ps) See Note 3 Max Trace Delay Skew in/between CLK & CMD/DAT Mm (ps) SDR50 / SDR25 / SDR12 / HS / DS 14 (87.5) SDR104 / DDR50 2 (12.5) Keep CLK, CMD & DATA traces away from other signal traces or unrelated power traces/areas or power supply components Note: 1. 2. 3. Actual frequencies may be lower due to clock source/divider limitations. If PWR, 0.01uF decoupling cap required for return current. If routing to SD Card socket includes a flex or 2nd PCB, max trace & skew calculations must include PCB & flex routing. Table 55. SD Card Loading vs Drive Type General SD Card Compliance CCARD (CDIE+CPKG) Drive Type FMAX (CLK base frequency) CLOAD (CCARD+CEQ) (CLK freq = 208MHz) CLOAD (CCARD+CEQ) (CLK freq = 100/50/25MHz) Parameter Min Max A B C D SDR104 DDR50 SDR50 SDR25 SDR12 HS DS Drive Type = A Drive Type = B Drive Type = C Drive Type = D Drive Type = A Drive Type = B Drive Type = C Drive Type = D JETSON TX2 OEM PRODUCT | DESIGN GUIDE | 20170912 Value 5 10 33 50 66 100 208 50 100 50 25 50 25 21 15 11 22 43 30 23 22 Units pF pF Ω Ω Ω Ω MHz MHz MHz MHz MHz MHz MHz pF pF pF pF pF pF pF pF Notes Spec best case value Spec worst case value UHS50 Card = optional, UHS104 Card = mandatory UHS50 Card = mandatory, UHS104 Card = mandatory UHS50 Card = optional, UHS104 Card = mandatory UHS50 Card = optional, UHS104 Card = mandatory Single data rate up to 104MB/sec Double data rate up to 50MB/sec Single data rate up to 50MB/sec Single data rate up to 25MB/sec Single data rate up to 12.5MB/sec Single data rate up to 25MB/sec Single data rate up to 12.5MB/sec Total load capacitance supported Total load capacitance supported Total load capacitance supported Possibly 22pF+ depending on host system Total load capacitance supported Total load capacitance supported Total load capacitance supported Possibly 22pF+ depending on host system 53 NVIDIA Jetson TX2 OEM Product Design Guide Table 56. SDCARD Signal Connections Function Signal Name SDCARD_CLK SDCARD_CMD SDCARD_D[3:0] SDCARD_CD# SDCARD_WP SDIO_RST# SDCARD_PWR_EN Note: Type O I/O I/O Termination 120 Ω bead on module for SDCARD_CLK. 0Ω series resistor on carrier board as placeholder. See note for EMI/ESD 10Ω series resistors for SDCARD CMD/D[3:0]. See note for EMI/ESD I I O O Description SDIO/SD Card Clock: Connect to CLK pin of device or socket SDIO/SDMMC Command: Connect to CMD pin of device/socket SDIO/SDMMC Data: Connect to Data pins of device or socket SDIO Card Detect: Connect to CD/C_DETECT pin on socket if required. SDIO Write Protect: Connect to WP/WR_PROTECT pin on socket if required. SDIO Reset: Connect to reset line on SDIO peripheral/connector. SDIO Supply/Load Switch Enable: Connect to enable of supply/load switch supplying VDD on SD Card socket. EMI/ESD may be required for SDIO when used as the SD Card socket interface. Any EMI/ESD device used must be able to meet signal timing/quality requirements. The Carrier Board implements 10Ω series resistors on the SDCARD data lines and a 0Ω series resistor on the clock line (for possible tuning if required). Table 57. Recommended SDCARD observation (test) points for initial boards Test Points Recommended One for SDCARD_CLK line. One SDCARD_DATx line & one for SDCARD_CMD. JETSON TX2 OEM PRODUCT | DESIGN GUIDE | 20170912 Location Near Device/Connector pin. SD connector pin can be used for device end if accessible. Near Jetson TX2 & Device pins. SD connector pin can be used for device end if accessible. 54 NVIDIA Jetson TX2 OEM Product Design Guide 10.0 AUDIO Jetson TX2 brings four PCM/I2S audio interfaces to the module pins & includes a flexible audio-port switching architecture. In addition, digital microphone & speaker interfaces are provided. Table 58. Jetson TX2 Audio Pin Descriptions Pin # Jetson TX2 Pin Name Tegra Signal Usage/Description F1 G2 H1 G1 H2 C15 D13 C14 D14 G5 H5 G6 H6 E6 F5 E5 F6 E16 D16 G4 H4 F2 H3 AUDIO_MCLK I2S0_CLK I2S0_LRCLK I2S0_SDIN I2S0_SDOUT I2S1_CLK I2S1_LRCLK I2S1_SDIN I2S1_SDOUT I2S2_CLK I2S2_LRCLK I2S2_SDIN I2S2_SDOUT I2S3_CLK I2S3_LRCLK I2S3_SDIN I2S3_SDOUT AO_DMIC_IN_CLK AO_DMIC_IN_DAT DSPK_OUT_CLK DSPK_OUT_DAT GPIO19_AUD_RST GPIO20_AUD_INT AUD_MCLK DAP1_SCLK DAP1_FS DAP1_DIN DAP1_DOUT DAP2_SCLK DAP2_FS DAP2_DIN DAP2_DOUT DMIC2_DAT DMIC1_CLK DMIC1_DAT DMIC2_CLK DAP4_SCLK DAP4_FS DAP4_DIN DAP4_DOUT CAN_GPIO1 CAN_GPIO0 GPIO_AUD3 GPIO_AUD2 GPIO_AUD1 GPIO_AUD0 Audio Codec Master Clock I2S Audio Port 0 Clock I2S Audio Port 0 Left/Right Clock I2S Audio Port 0 Data In I2S Audio Port 0 Data Out I2S Audio Port 1 Clock I2S Audio Port 1 Left/Right Clock I2S Audio Port 1 Data In I2S Audio Port 1 Data Out I2S Audio Port 2 Clock I2S Audio Port 2 Left/Right Clock I2S Audio Port 2 Data In I2S Audio Port 2 Data Out I2S Audio Port 3 Clock I2S Audio Port 3 Left/Right Clock I2S Audio Port 3 Data In I2S Audio Port 3 Data Out Digital Mic Input Clock Digital Mic Input Data Digital Speaker Output Clock Digital Speaker Output Data Audio Codec Reset or GPIO Audio Codec Interrupt or GPIO Usage on the Carrier Board Direction Pin Type Output Bidir Bidir Input Bidir Bidir Bidir Input Bidir Bidir Bidir Input Bidir Bidir Bidir Input Bidir Output Input Output Output Output Input CMOS – 1.8V CMOS – 1.8V CMOS – 1.8V CMOS – 1.8V CMOS – 1.8V CMOS – 1.8V CMOS – 1.8V CMOS – 1.8V CMOS – 1.8V CMOS – 1.8V CMOS – 1.8V CMOS – 1.8V CMOS – 1.8V CMOS – 1.8V CMOS – 1.8V CMOS – 1.8V CMOS – 1.8V CMOS – 1.8V CMOS – 1.8V CMOS – 1.8V CMOS – 1.8V CMOS – 1.8V CMOS – 1.8V Expansion Header GPIO Expansion Header M.2 Key E Camera Connector Expansion Header GPIO Expansion Header Expansion Header When possible, the following assignments should be used for the I2Sx interfaces. Table 59. I2S Interface Mapping Jetson TX2 Pins (Tegra Functions) I2S0 (I2S1) I2S1 (I2S2) I2S2 (I2S3) I2S3 (I2S4) NA (I2S6) JETSON TX2 OEM PRODUCT | DESIGN GUIDE | 20170912 I/O Block AUDIO CONN AUDIO_HV AUDIO_HV DMIC_HV Typical Usage Available (Codec) Available (Misc) Available (WLAN / BT, Modem) Available (Misc) Used for on-module WLAN / BT 55 NVIDIA Jetson TX2 OEM Product Design Guide Figure 28. Audio Device Connections Jetson TX2 Tegra AUDIO AUD_MCLK GPIO_AUD1 DAP1_SCLK DAP1_FS DAP1_DOUT DAP1_DIN AUDIO_HV GPIO_AUD0 DMIC2_DAT DMIC1_CLK DMIC2_CLK DMIC1_DAT Note: - 75Ω AUDIO_MCLK GPIO19_AUD_RST I2S1_CLK 75Ω I2S1_LRCK I2S0_CLK I2S0_LRCK I2S1_SDOUT I2S0_SDOUT I2S1_SDIN I2S0_SDIN GPIO20_AUD_INT I2S3_CLK 75Ω I2S3_LRCK I2S2_CLK I2S2_LRCK I2S3_SDOUT I2S2_SDOUT I2S3_SDIN DAP4_SCLK DAP4_FS DAP4_DOUT DAP4_DIN I2S4_CLK GPIO_PQ0 GPIO_PQ3 GPIO_PQ1 GPIO_PQ2 I2S6_CLK DAP2_SCLK DAP2_FS DAP2_DOUT DAP2_DIN I2S2_CLK DMIC_HV CONN Nvidia Carrier Board Net Name Tegra Function I2S2_SDIN 120Ω@ I2S4_LRCK I2S3_CLK I2S3_LRCK I2S4_SDOUT I2S3_SDOUT I2S4_SDIN I2S3_SDIN F1 F2 G2 H1 H2 G1 H3 G5 H5 H6 G6 E6 F5 F6 E5 Audio Codec AUDIO_I2S_MCLK GPIO_X1_AUD DAP1_SCLK_AP DAP1_FS_AP DAP1_DOUT_AP DAP1_DIN_AP AUD_INT DAP3_SCLK_AP 2nd WiFi/BT, Modem DAP3_FS_AP DAP3_DOUT_AP DAP3_DIN_AP DAP4_SCLK_AP Misc DAP4_FS_AP DAP4_DOUT_AP DAP4_DIN_AP 120Ω@ Primary WiFi/BT I2S6_LRCK I2S6_SDOUT I2S6_SDIN I2S2_LRCK I2S2_SDOUT I2S1_CLK I2S1_LRCK I2S1_SDOUT I2S2_SDIN I2S1_SDIN C15 D13 D14 C14 DAP2_SCLK_AP Misc DAP2_FS_AP DAP2_DOUT_AP DAP2_DIN_AP The I2S interfaces can be used in either Master or Slave mode. A capacitor from DAPn_FS to GND is recommended if Tegra an I2S slave & the edge_cntrl configuration = 1 (SDATA driven on positive edge of SCLK). The value of the capacitor should be chosen to provide a minimum of 2ns hold time for the DAPn_FS edge after the rising edge of DAPn_SCLK. I2S Design Guidelines Table 60. I2S Interface Signal Routing Requirements Parameter Configuration / Device Organization Max Loading Reference plane Breakout Region Impedance Trace Impedance Via proximity (Signal to reference) Trace spacing Microstrip or Stripline Max Trace Delay Max Trace Delay Skew between SCLK & SDATA_OUT/IN Note: Requirement 1 8 GND Min width/spacing 50 < 3.8 (24) 2x 3600 (~22) 250 (~1.6”) Units load pF Ω mm (ps) dielectric Notes ±20% See Note 1 ps (in) ps (in) Up to 4 signal Vias can share a single GND return Via Table 61. Audio Signal Connections Jetson TX2 Pin Name I2S[3:0]_SCLK Type I/O I2S[3:0]_LRCK I2S[3:0]_SDATA_OUT I2S[3:0]_SDATA_IN AUD_MCLK GPIO19_AUD_RST GPIO20_AUD_INT I/O Termination I2S[2,0]_CLK have 75Ω beads & I2S3_CLK has a 120Ω Bead in series (on Jetson TX2). I/O I O O I 75Ω Beads in series (on Jetson TX2). JETSON TX2 OEM PRODUCT | DESIGN GUIDE | 20170912 Description I2S Serial Clock: Connect to I2S/PCM CLK pin of audio device. I2S Left/Right Clock: Connect to Left/Right Clock pin of audio device. I2S Data Output: Connect to Data Input pin of audio device. I2S Data Input: Connect to Data Output pin of audio device. Audio Codec Master Clock: Connect to clock pin of Audio Codec. Audio Reset: Connect to reset pin of Audio Codec. Audio Interrupt: Connect to interrupt pin of Audio Codec. 56 NVIDIA Jetson TX2 OEM Product Design Guide 11.0 WLAN / BT (INTEGRATED) Jetson TX2 integrates a Broadcom BCM4354 WLAN / BT solution. Two Dual-band antenna connectors are located on the module. The requirements are in the Antenna Requirements table below. The UART interface is multiplexed and either route these to the WLAN/BT device or to the connector pins for use on the carrier board. The default selection for the multiplexers is to the WLAN/BT device. Figure 29. Integrated WLAN / BT Jetson TX2 Tegra SDMMC3_CLK SDMMC3_CMD SDMMC3_DAT0 SDMMC3_DAT1 SDMMC3_DAT2 SDMMC3_DAT3 SDMMC3 SPI QSPI_IO3 CAM GPIO_CAM1 SYS UART Load Switch WIFI_EN GPIO_SW3 WIFI_WAKE_AP GPIO_SW4 BT2_WAKE_AP GP_PWM7 BT_EN GPIO_MDM5 VDD_3V3_SYS MUX_SEL RF VDD_1V8 Antenna Connector #1 RF Antenna Connector #2 WiFi / BT AP2_WAKE_BT UART3_TX UART3_RX UART4_TX UART4_RX UART4_RTS_N UART4_CTS_N CONN DMIC_HV GPIO_PQ0 GPIO_PQ1 GPIO_PQ2 GPIO_PQ3 SEL UART3_RTS# UART3_CTS# Mux H10 H9 G10 G9 (Default) DAP6_SCLK DAP6_DOUT DAP6_DIN DAP6_FS Table 62. Antenna Requirements Parameter Type Frequency Band(s) Impedance Mating Connector Note: 1. 2. 3. Requirement Dual-Band (x2) Dipole 2.4 & 5.0 50 Plug: I-PEX U.FL series Units Notes GHz Ω See note 1 Receptacles on Jetson TX2 are from Hirose Electric (U.S.A). Part # is U.FL-R-SMT-1(10). Antenna Manufacturer: Pulse, Part Number: W1043 Cable manufacturer: Pulse, part number: W9009 JETSON TX2 OEM PRODUCT | DESIGN GUIDE | 20170912 57 NVIDIA Jetson TX2 OEM Product Design Guide 12.0 MISCELLANEOUS INTERFACES 12.1 I2C Tegra has nine I2C controllers. Jetson TX2 brings eight of the I2C interfaces out, which are shown in the tables below. The assignments in Table 64 should be used for the I2C interfaces: Table 63. Jetson TX2 I2C Pin Descriptions Pin # Jetson TX2 Pin Name Tegra Signal Usage/Description C6 D6 E15 D15 A21 A20 C11 C10 C12 C13 A6 B6 A34 A35 B34 B35 I2C_CAM_CLK I2C_CAM_DAT I2C_GP0_CLK I2C_GP0_DAT I2C_GP1_CLK I2C_GP1_DAT I2C_GP2_CLK I2C_GP2_DAT I2C_GP3_CLK I2C_GP3_DAT I2C_PM_CLK I2C_PM_DAT DP1_AUX_CH– DP1_AUX_CH+ DP0_AUX_CH– DP0_AUX_CH+ CAM_I2C_SCL CAM_I2C_SDA GPIO_SEN8 GPIO_SEN9 GEN1_I2C_SCL GEN1_I2C_SDA GEN7_I2C_SCL GEN7_I2C_SDA GEN9_I2C_SCL GEN9_I2C_SDA GEN8_I2C_SCL GEN8_I2C_SDA DP_AUX_CH1_N DP_AUX_CH1_P DP_AUX_CH0_N DP_AUX_CH0_P Camera I2C Clock Camera I2C Data General I2C 0 Clock General I2C 0 Data General I2C 1 Clock General I2C 1 Data General I2C 2 Clock General I2C 2 Data General I2C 3 Clock General I2C 3 Data PM I2C Clock PM I2C Data Display Port 1 Aux– or HDMI DDC SDA Display Port 1 Aux+ or HDMI DDC SCL Display Port 0 Aux– or HDMI DDC SDA Display Port 0 Aux+ or HDMI DDC SCL Usage on the Carrier Board Camera Connector I2C (General) HDMI Type A Conn. Display Connector Direction Pin Type Bidir Bidir Bidir Bidir Bidir Bidir Bidir Bidir Bidir Bidir Bidir Bidir Bidir Bidir Bidir Bidir Open Drain – 1.8V Open Drain – 1.8V Open Drain – 1.8V Open Drain – 1.8V Open Drain – 3.3V Open Drain – 3.3V Open Drain – 1.8V Open Drain – 1.8V Open Drain – 1.8V Open Drain – 1.8V Open Drain – 1.8V Open Drain – 1.8V AC-Coupled on Carrier Board (eDP/DP) or OpenDrain, 1.8V (3.3V tolerant DDC/I2C) Table 64. I2C Interface Mapping Ctrlr Usage on Jetson TX2 Power monitors Typcial usage on Carrier board On-Jetson TX2 Pull-up/voltage I2C1 I2C2 I2C3 I2C4 Jetson TX2 Pins Names I2C_GP1_CLK/DAT I2C_GP0_CLK/DAT I2C_CAM_CLK/DAT DP1_AUX_CH_P/N General I2C bus usage. 3.3V devices supported Audio Codec, general I2C. 1.8V devices supported Cameras & related functions. 1.8V devices supported HDMI / DP / I2C. 1.8V / 3.3V devices supported. I2C5 I2C6 na DP0_AUX_CH_P/N Power control On-Jetson TX2 use only HDMI / DP / I2C. 1.8V / 3.3V devices supported. I2C7 I2C8 I2C9 I2C_GP2_CLK/DAT I2C_PM_CLK/DAT I2C_GP3_CLK/DAT 1KΩ on Jetson TX2 to 3.3V 1KΩ on Jetson TX2 to 1.8V 1KΩ on Jetson TX2 to 1.8V None on Jetson TX2. I/F supports pull-up to 1.8V or 3.3V (3.3V in Open-drain mode only) 1KΩ on Jetson TX2 to 1.8V None on Jetson TX2. I/F supports pull-up to 1.8V or 3.3V (3.3V in Open-drain mode only) 1KΩ on Jetson TX2 to 1.8V 1KΩ on Jetson TX2 to 1.8V 1KΩ on Jetson TX2 to 1.8V Thermal Sensor JETSON TX2 OEM PRODUCT | DESIGN GUIDE | 20170912 General I2C bus. 1.8V devices supported General I2C bus. Only 1.8V devices supported General I2C bus. Only 1.8V devices supported 58 NVIDIA Jetson TX2 OEM Product Design Guide Figure 30. I2C Connections Jetson TX2 1kΩ Tegra – I2C SYS I2C5 VDD_1V8 1kΩ PWR_I2C_SCL PWR_I2C_SDA On-Module Usage Only 1kΩ VDD_3V3_SYS 1kΩ I2C1 I2C_GP1_CLK GEN1_I2C_SCL GEN1_I2C_SDA I2C_GP1_DAT 1kΩ A21 A20 Used on-module for power monitors, & typically offmodule for GPIO expansion or other misc 3.3V I2C usage VDD_1V8 1kΩ CAM I2C3 I2C_CAM_CLK CAM_I2C_SCL CAM_I2C_SDA I2C_CAM_DAT 1kΩ UART C6 D6 Used as camera module control interface VDD_1V8 1kΩ I2C7 I2C_GP2_CLK GEN7_I2C_SCL GEN7_I2C_SDA I2C_GP2_DAT 1kΩ C11 C10 Available for misc. 1.8V I2C devices VDD_1V8 1kΩ I2C9 I2C_GP3_CLK GEN9_I2C_SCL GEN9_I2C_SDA I2C_GP3_DAT 1kΩ C12 C13 Available for misc. 1.8V I2C devices VDD_1V8 1kΩ AO I2C2 I2C_GP0_CLK GPIO_SEN8 GPIO_SEN9 I2C_GP0_DAT 1kΩ E15 D15 Available for misc. 1.8V I2C devices VDD_1V8 1kΩ DP GEN8_I2C_SCL GEN8_I2C_SDA I2C_PM_CLK I2C8 DP_AUX_CH0_P DP_AUX_CH0_N DP0_AUX_CH+ I2C6 DP_AUX_CH1_P DP_AUX_CH1_N DP1_AUX_CH+ I2C4 I2C_PM_DAT DP0_AUX_CH– DP1_AUX_CH– A6 B6 B35 B34 A35 A34 Available for misc. 1.8V I2C devices Typically used for eDP. Otherwise available for Misc 1.8V/3.3V I2C usage. Typically used for HDMI or DP. Otherwise available for Misc 1.8V/3.3V I2C usage. I2C Design Guidelines Care must be taken to ensure I2C peripherals on same I2C bus connected to Jetson TX2 do not have duplicate addresses. Addresses can be in two forms: 7-bit, with the Read/Write bit removed or 8-bit including the Read/Write bit. Be sure to compare I2C device addresses using the same form (all 7-bit or all 8-bit format). Table 65. I2C Interface Signal Routing Requirements Parameter Max Frequency Topology Max Loading Reference plane Trace Impedance Trace Spacing Max Trace Delay Note: 1. 2. 3. Standard-mode / Fm / Fm+ Standard-mode / Fm / Fm+ Standard Mode Fm & Fm+ Requirement Units Notes 100 / 400 / 1000 kHz See Note 1 Single ended, bi-directional, multiple masters/slaves 400 pF Total of all loads GND or PWR 50 – 60 Ω ±15% 1x dielectric ps (in) 3400 (~20) 1700 (~10) Fm = Fast-mode, Fm+ = Fast-mode Plus Avoid routing I2C signals near noisy traces, supplies or components such as a switching power regulator. No requirement for decoupling caps for PWR reference JETSON TX2 OEM PRODUCT | DESIGN GUIDE | 20170912 59 NVIDIA Jetson TX2 OEM Product Design Guide Table 66. I2C Signal Connections Jetson TX2 Pin Name I2C_GP0_CLK/DAT I2C_GP1_CLK/DAT I2C_GP2_CLK/DAT I2C_GP3_CLK/DAT I2C_PM_CLK/DAT Type Termination Description I/OD I/OD I/OD I/OD I/OD 1kΩ pull-ups to VDD_1V8 on Jetson TX2 1kΩ pull-ups to VDD_3V3_SYS on Jetson TX2 1kΩ pull-ups to VDD_1V8 on Jetson TX2 1kΩ pull-ups to VDD_1V8 on Jetson TX2 1kΩ pull-ups to VDD_1V8 on Jetson TX2 I2C_CAM_CLK/DAT DP0_AUX_CH+/– I/OD I/OD DP1_AUX_CH+/– I/OD 1kΩ pull-ups to VDD_1V8 on Jetson TX2 See eDP/HDMI/DP sections for correct termination See eDP/HDMI/DP sections for correct termination General I2C 0 Clock\Data. Connect to CLK/Data pins of 1.8V devices General I2C 1 Clock\Data. Connect to CLK/Data pins of 3.3V devices. General I2C 2 Clock\Data. Connect to CLK/Data pins of 1.8V devices General I2C 3 Clock\Data. Connect to CLK/Data pins of 1.8V devices. Power Mon. I2C Clock\Data. Connect to CLK/Data pins of 1.8V devices Camera I2C Clock\Data. Connect to CLK/Data pins of any 1.8V devices DP_AUX Channel (eDP/DP) or DDC I2C 2 Clock & Data (HDMI). Connect to AUX_CH+/– (DP) or SCL/SDA (HDMI) DP_AUX Channel (eDP/DP) or DDC I2C 2 Clock & Data (HDMI). Connect to AUX_CH+/– (DP) or SCL/SDA (HDMI) Note: 1. 2. If some devices require a different voltage level than others connected to the same I2C bus, level shifters are required. For I2C interfaces that are pulled up to 1.8V, disable the E_IO_HV option for these pads. For I2C interfaces that are pulled up to 3.3V, enable the E_IO_HV option. The E_IO_HV option is selected in the Pinmux registers. De-bounce The tables below contain the allowable De-bounce settings for the various I2C Modes. Table 67. De-bounce Settings (Fast Mode Plus, Fast Mode & Standard Mode) I2C Mode Clock Source Source Clock Freq I2C Source Divisor Sm/Fm Divisor Fm+ PLLP_OUT0 408MHz 5 (0x04) 10 (0x9) Fm PLLP_OUT0 408MHz 5 (0x4) Sm PLLP_OUT0 408MHz 20 (0x13) Note: De-bounce Value 0 5:1 7:6 I2C SCL Freq 1016KHz 905.8KHz 816KHz 26 (0x19) 7:0 392KHz 26 (0x19) 7:0 98KHz Sm = Standard Mode. 12.2 SPI Jetson TX2 brings out three of the Tegra SPI interfaces. Table 68. Jetson TX2 SPI Pin Descriptions Pin # Jetson TX2 Pin Name Tegra Signal Usage/Description E3 F3 E4 F4 G13 E14 F14 F13 H14 G16 F16 H15 G15 SPI0_CLK SPI0_CS0# SPI0_MISO SPI0_MOSI SPI1_CLK SPI1_CS0# SPI1_MISO SPI1_MOSI SPI2_CLK SPI2_CS0# SPI2_CS1# SPI2_MISO SPI2_MOSI GPIO_SEN1 GPIO_SEN4 GPIO_SEN2 GPIO_SEN3 GPIO_CAM4 GPIO_CAM7 GPIO_CAM5 GPIO_CAM6 GPIO_WAN5 GPIO_WAN8 GPIO_MDM4 GPIO_WAN6 GPIO_WAN7 SPI 0 Clock SPI 0 Chip Select 0 SPI 0 Master In / Slave Out SPI 0 Master Out / Slave In SPI 1 Clock SPI 1 Chip Select 0 SPI 1 Master In / Slave Out SPI 1 Master Out / Slave In SPI 2 Clock SPI 2 Chip Select 0 SPI 2 Chip Select 1 SPI 2 Master In / Slave Out SPI 2 Master Out / Slave In JETSON TX2 OEM PRODUCT | DESIGN GUIDE | 20170912 Usage on the Carrier Board Display Connector Expansion Header Display/Camera Conns. Direction Pin Type Bidir Bidir Bidir Bidir Bidir Bidir Bidir Bidir Bidir Bidir Bidir Bidir Bidir CMOS – 1.8V CMOS – 1.8V CMOS – 1.8V CMOS – 1.8V CMOS – 1.8V CMOS – 1.8V CMOS – 1.8V CMOS – 1.8V CMOS – 1.8V CMOS – 1.8V CMOS – 1.8V CMOS – 1.8V CMOS – 1.8V 60 NVIDIA Jetson TX2 OEM Product Design Guide Figure 31. SPI Connections Jetson TX2 Tegra – SPI AO 120Ω@100MHz GPIO_SEN1 GPIO_SEN2 GPIO_SEN3 GPIO_SEN4 CAM SPI0_CLK SPI0_MISO SPI0_MOSI SPI0_CS0# SPI1_CLK GPIO_CAM4 GPIO_CAM5 GPIO_CAM6 GPIO_CAM7 SPI1_MISO SPI1_MOSI SPI1_CS0# SPI1_CS1# UART SPI2_CLK GPIO_WAN5 GPIO_WAN6 GPIO_WAN7 GPIO_WAN8 GPIO_MDM4 SPI2_MISO SPI2_MOSI SPI2_CS0# SPI2_CS1# E3 E4 F4 Touch F3 G13 F14 F13 Expansion E14 E13 H14 H15 G15 G16 Display (CS0) Camera (CS1) F16 The figure below shows the basic connections used. Figure 32. Basic SPI Master/Slave Connections Jetson TX2 Master SPI Slave Device SPIn_CSx# CS (Chip Select) SPIn_SCK Jetson TX2 Slave SPIn_CSx# CLK (Clock) SPIn_SCK SPI Master Device CS (Chip Select) CLK (Clock) SPIn_MOSI MOSI (Master out, Slave in) SPIn_MOSI MOSI (Master out, Slave in) SPIn_MISO MISO (Master in, Slave out) SPIn_MISO MISO (Master in, Slave out) SPI Design Guidelines Figure 33. SPI Point-Point Topology Jetson TX2 Die PKG Main trunk SPI Device Figure 34. SPI Star Topologies Jetson TX2 Die Branch-A SPI Device #1 Branch-B SPI Device #2 PKG Main trunk Figure 35. SPI Daisy Topologies Branch-A SPI Device #1 Jetson TX2 Die PKG Main trunk JETSON TX2 OEM PRODUCT | DESIGN GUIDE | 20170912 Branch-B SPI Device #2 61 NVIDIA Jetson TX2 OEM Product Design Guide Table 69. SPI Interface Signal Routing Requirements Parameter Max Frequency Configuration / Device Organization Max Loading (total of all loads) Reference plane Breakout Region Impedance Max PCB breakout delay Trace Impedance Via proximity (Signal to reference) Trace spacing Microstrip / Stripline Max Trace Length/Delay (PCB Main Trunk) Point-Point For MOSI, MISO, SCK & CS 2x-Load Star/Daisy Max Trace Length/Delay (Branch-A) 2x-Load Star/Daisy for MOSI, MISO, SCK & CS Max Trace Length/Delay (Branch-B) 2x-Load Star/Daisy for MOSI, MISO, SCK & CS Max Trace Length/Delay Skew from MOSI, MISO & CS to SCK Note: Requirement 65 3 15 GND Minimum width & spacing 75 50 – 60 < 3.8 (24) 4x / 3x 195 (1228) 120 (756) 75 (472) Units MHz load pF ps Ω mm (ps) dielectric Notes ±15% See Note 1 mm (ps) mm (ps) 75 (472) mm (ps) 16 (100) mm (ps) At any point Up to 4 signal Vias can share a single GND return Via Table 70. SPI Signal Connections Jetson TX2 Pin Names SPI[2:0]_CLK SPI[2:0]_MOSI SPI[2:0]_MISO SPI[2:1]_CS[1:0]# SPI0_CS0# Type I/O Termination SPI0_CLK has 120Ω Bead in series (on Jetson TX2). I/O I/O I/O Description SPI Clock.: Connect to Peripheral CLK pin(s) SPI Data Output: Connect to Slave Peripheral MOSI pin(s) SPI Data Input: Connect to Slave Peripheral MISO pin(s) SPI Chip Selects.: Connect one CS_N pin per SPI IF to each Slave Peripheral CS pin on the interface Table 71. Recommended SPI observation (test) points for initial boards Test Points Recommended One for each SPI signal line used Location Near Jetson TX2 & Device pins. 12.3 UART Jetson TX2 brings five UARTs out to the main connector. One of the UARTs is used for the WLAN/BT on Jetson TX2 or as UART3 at the connector depending on the setting of a multiplexor. See Table 73 for typical assignments of the UARTs. Table 72. Jetson TX2 UART Pin Descriptions Pin # Jetson TX2 Pin Name Tegra Signal Usage/Description H11 G11 G12 H12 E10 E9 D10 D9 A15 A16 B15 B16 UART0_CTS# UART0_RTS# UART0_RX UART0_TX UART1_CTS# UART1_RTS# UART1_RX UART1_TX UART2_CTS# UART2_RTS# UART2_RX UART2_TX UART 0 Clear to Send UART 0 Request to Send UART 0 Receive UART 0 Transmit UART 1 Clear to Send UART 1 Request to Send UART 1 Receive UART 1 Transmit UART 2 Clear to Send UART 2 Request to Send UART 2 Receive UART 2 Transmit G9 UART3_CTS# UART1_CTS UART1_RTS UART1_RX UART1_TX UART3_CTS UART3_RTS UART3_RX UART3_TX UART2_CTS UART2_RTS UART2_RX UART2_TX UART4_CTS_N (via mux) UART4_RTS_N (via mux) UART4_RX (via mux) UART4_TX (via mux) G10 UART3_RTS# H9 H10 UART3_RX UART3_TX JETSON TX2 OEM PRODUCT | DESIGN GUIDE | 20170912 Usage on the Carrier Board Debug Header Serial Port Header M.2 Key E UART 3 Clear to Send Direction Pin Type Input Output Input Output Input Output Input Output Input Output Input Output CMOS – 1.8V CMOS – 1.8V CMOS – 1.8V CMOS – 1.8V CMOS – 1.8V CMOS – 1.8V CMOS – 1.8V CMOS – 1.8V CMOS – 1.8V CMOS – 1.8V CMOS – 1.8V CMOS – 1.8V Input CMOS – 1.8V Output CMOS – 1.8V Input Output CMOS – 1.8V CMOS – 1.8V Not assigned UART 3 Request to Send UART 3 Receive UART 3 Transmit Optional source of UART on Exp. Header 62 NVIDIA Jetson TX2 OEM Product Design Guide Pin # Jetson TX2 Pin Name Tegra Signal Usage/Description D5 D8 UART7_RX UART7_TX UART7_RX UART7_TX UART 7 Receive UART 7 Transmit Usage on the Carrier Board Not Assigned Direction Pin Type Input Output CMOS – 1.8V CMOS – 1.8V Table 73. UART Interface Mapping Jetson TX2 Pins (Tegra Functions) UART0 (UART1) UART1 (UART3) UART2 (UART2) UART3 (UART4) I/O Block DEBUG AO UART CONN UART7 (UART7) AO Typical Usage Debug Serial Port M.2 socket for external WLAN / BT Misc. Available if not used for on-module WLAN / BT (selected by on-module multiplexor) 2nd Debug/Misc. Figure 36. Jetson TX2 UART Connections Jetson TX2 Tegra – UART AO UART3_TX UART3_RX UART3_RTS_N UART3_CTS_N (RAM_CODE1 Strap) UART 1_TX UART7_TX UART7_RX (RAM_CODE1 Strap) RSVD UART 1_RX UART 1_RTS# UART 1_CTS# RSVD UART3_TX CONN UART3_RX UART4_TX UART4_RX UART4_RTS_N UART4_CTS_N DEBUG UART1_TX UART1_RX UART1_RTS_N UART1_CTS_N Mux UART3_CTS# D8 D5 Serial Port, etc. UART 7_TX_AP UART 7_RX_AP Misc. H10 H9 G10 Misc. G9 WiFi / BT on Jetson TX2 UART 0_TX UART 0_RX (RAM_CODE0 Strap) UART 0_RTS# UART 0_CTS# UART2_TX UART2_TX UART2_RX UART2_RTS_N UART2_CTS_N UART Note: UART3_RTS# D9 D10 E9 E10 UART2_RX UART2_RTS# UART2_CTS# H12 G12 G11 H11 Used for Debug, etc. B1 6 B1 5 A16 M.2 Conn. (2nd WiFi/Bt) A15 Care should be taken when using UART pins that are associated with Tegra straps. See Strapping Pins section for details. Table 74. UART Signal Connections Ball Name UART[7,3:0]_TX UART[7,3:0]_RX UART[3:0]_CTS# UART[3:0]_RTS# Type O I I O Termination Description UART Transmit: Connect to Peripheral RXD pin of device UART Receive: Connect to Peripheral TXD pin of device UART Clear to Send: Connect to Peripheral RTS_N pin of device UART Request to Send: Connect to Peripheral CTS pin of device 12.4 Fan Jetson TX2 provides PWM and Tachometer functionality for controlling a fan as part of the thermal solution. Information on the PWM and Tachometer pins/functions can be found in the following locations: Jetson TX2 Module Pin Mux: ▪ This is used to configure the FAN_PWM & FAN_TACH pins. The FAN_PWM pin is configured as GP_PWM4. The FAN_TACH pin is configured as NV_THERM_FAN_TACH. JETSON TX2 OEM PRODUCT | DESIGN GUIDE | 20170912 63 NVIDIA Jetson TX2 OEM Product Design Guide Tegra X2 Technical Reference Manual: ▪ Functional descriptions and related registers can be found in the TRM for the FAN_PWM (PWM chapter) & FAN_TACH (Tachometer chapter) functions. Jetson Developer Kit Carrier Board Specification: ▪ The document contains the maximum current capability of the VDD_5V0_IO_SYS supply in the Interface Power chapter (VDDIO_5V0_IO_SLP comes from that supply). The fan is powered by this supply on the Jetson TX2 Developer Kit carrier board. Table 75. Jetson TX2 Fan Pin Descriptions Pin # Jetson TX2 Pin Name Tegra Signal Usage/Description Usage on the Carrier Board C16 B17 FAN_PWM FAN_TACH GPIO_SEN6 UART5_TX Fan PWM Fan Tach Fan Direction Pin Type Output Input CMOS – 1.8V CMOS – 1.8V Figure 37. Jetson TX2 Fan Connection Example VDD_1V8 VDD_5V0_IO_SLP AO UART GPIO_SEN6 FAN_PWM UART5_TX FAN_TACH D 100Ω G C16 10kΩ Tegra – Fan 100kΩ 4.7kΩ Jetson TX2 10uF 0.1uF Fan Header 4 S 3 2 B17 VDD_5V0_IO_SYS 100kΩ D 10pF G PS_VDD_FAN_DISABLE (GPIO Expander P04) 1 10pF S Table 76. Fan Signal Connections Ball Name FAN_PWM Type O FAN_TACH I Termination ESD diode to GND Description Fan Pulse Width Modulation: Connect through FET as shown in the Jetson TX2 Fan Connections figure. Fan Tachometer: Connect to TACH pin on fan connector. 12.5 CAN Jetson TX2 brings two CAN (Controller Area Network) interfaces out to the main connector. Table 77. Jetson TX2 CAN Pin Descriptions Pin # Jetson TX2 Pin Name Tegra Signal Usage/Description C20 E18 D18 D19 C19 D17 C17 C18 CAN_WAKE CAN0_ERR CAN0_RX CAN0_TX CAN1_ERR CAN1_RX CAN1_STBY CAN1_TX CAN_GPIO4 CAN_GPIO5 CAN0_DIN CAN0_DOUT CAN_GPIO3 CAN1_DIN CAN_GPIO6 CAN1_DOUT CAN Wake CAN #0 Error CAN #0 Receive CAN #0 Transmit CAN #1 Error CAN #1 Receive CAN #1 Standby CAN #1 Transmit JETSON TX2 OEM PRODUCT | DESIGN GUIDE | 20170912 Usage on the Carrier Board GPIO Expansion Header Direction Pin Type Input Input Input Output Input Input Output Output CMOS 3.3V CMOS 3.3V CMOS 3.3V CMOS 3.3V CMOS 3.3V CMOS 3.3V CMOS 3.3V CMOS 3.3V 64 NVIDIA Jetson TX2 OEM Product Design Guide Figure 38. Jetson TX2 CAN Connections Jetson TX2 Tegra - CAN AO_HV CAN #1 CAN1_DOUT CAN1_DIN CAN1_TX CAN1_RX CAN0_DOUT CAN0_DIN CAN0_TX CAN0_RX CAN1_ERR CAN_GPIO3 CAN_GPIO4 CAN_GPIO5 CAN_GPIO6 CAN_WAKE CAN0_ERR CAN1_STBY C18 D17 D19 CAN #0 D18 C19 C20 E18 CAN Wake C17 Table 78. CAN Interface Signal Routing Requirements Parameter Max Data Rate / Frequency Configuration / Device Organization Reference plane Trace Impedance Via proximity (Signal via to GND return via) Trace spacing Microstrip / Stripline Max Trace Length (for RX & TX only) Max Trace Length/Delay Skew from RX to TX Requirement 1 1 GND 50 < 3.8 (24) 4x / 3x 223 (1360) 8 (50) Units Mbps / MHz load Notes Ω mm (ps) dielectric ±15% See Note 1 mm (ps) mm (ps) See Note 2 See Note 2 Table 79. CAN Signal Connections Ball Name CAN[1:0]_TX CAN[1:0]_RX CAN[1:0]_ERR CAN1_STBY CAN_WAKE Type O I I O I Termination JETSON TX2 OEM PRODUCT | DESIGN GUIDE | 20170912 Description CAN Transmit: Connect to matching pin of device CAN Receive: Connect to Peripheral pin of device CAN Error: Connect to matching pin of device CAN Standby: Connect to matching pin of device CAN Wake: Connect to matching pin of device 65 NVIDIA Jetson TX2 OEM Product Design Guide 12.6 Debug Figure 39. Debug Connections Jetson TX2 JTAG_RTCK JTAG_T MS JTAG_TMS JTAG_TDI JTAG_TCK JTAG_TDO JTAG_TRST_N NVJTAG_SEL JTAG_T DI JTAG_TCK JTAG_TDO JTAG_GP0 100kΩ 100kΩ 100kΩ JTAG_GP1 0.1uF To PMIC RESET_IN A13 B1 3 A11 A47 0Ω See Note 1 VDD_1V8 UART0_TX UART1_TXD UART1_RXD UART1_RTS_N UART1_CTS_N A14 A12 B1 2 B1 1 UART 0_RX UART 0_RTS# UART0_CTS# VDD_3V3_SYS H12 G12 G11 100kΩ DEBUG Optional JTAG connections RTCK TMS TDI TCLK TDO TRST_N RST VDD_1V8 100kΩ Tegra Level Shifter For Debug Use H11 See Note 2 DP RSVD UART7_TX UART7_RX Notes: 1. 2. 3. RSVD D8 D5 JTAG_GP1 (Tegra NVJTAG_SEL) is left unconnected (pulled down on module) for normal operation and pulled to 1.8V for Boundary Scan Mode. If level shifter is implemented, pull-ups are required the RX & CTS lines on the non-Tegra side of the level shifter. This is required to keep the inputs from floating and toggling when no device is connected to the debug UART. Check preferred JTAG debugger documentation for JTAG PU/PD recommendations. 12.6.1 JTAG JTAG is not required, but may be useful for new design bring-up or for Boundary Scan. Table 80. Jetson TX2 JTAG Pin Descriptions Pin # Jetson TX2 Pin Name Tegra Signal Usage/Description B13 JTAG_GP0 JTAG_TRST_N JTAG Test Reset A11 JTAG_GP1 NVJTAG_SEL A14 B11 B12 A13 A12 JTAG_RTCK JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS − JTAG_TCK JTAG_TDI JTAG_TD0 JTAG_TMS JETSON TX2 OEM PRODUCT | DESIGN GUIDE | 20170912 JTAG General Purpose 1. Pulled low on module for normal operation & pulled high by test device for Boundary Scan test mode. JTAG Return Clock JTAG Test Clock JTAG Test Data In JTAG Test Data Out JTAG Test Mode Select Usage on the Carrier Board JTAG Header & Debug Connector JTAG JTAG Header & Debug Connector Direction Pin Type Input CMOS – 1.8V Input CMOS – 1.8V Input Input Input Output Input CMOS – 1.8V CMOS – 1.8V CMOS – 1.8V CMOS – 1.8V CMOS – 1.8V 66 NVIDIA Jetson TX2 OEM Product Design Guide Table 81. JTAG Signal Connections Jetson TX2 Pin (function) Name JTAG_TMS JTAG_TCK JTAG_TDO JTAG_TDI JTAG_RTCK JTAG_GP0# (JTAG_TRST_N) JTAG_GP1 Type I I O I I I Termination Description JTAG Mode Select: Connect to TMS pin of connector JTAG Clock: Connect to TCK pin of connector JTAG Data Out: Connect to TDO pin of connector JTAG Data In: Connect to TDI pin of connector JTAG Return Clock: Connect to RTCK pin of connector JTAG General Purpose Pin #0: Connect to TRST pin of connector 100kΩ to GND (on Jetson TX2) 100kΩ to GND & 0.1uF to GND (on Jetson TX2) 100kΩ to GND (on Jetson TX2) JTAG General Purpose Pin #1: Used as select Normal operation: Leave series resistor from NVJTAG_SEL not stuffed. Scan test mode: Connect NVJTAG_SEL to VDD_1V8 (install 0Ω resistor as shown). 12.6.2 Debug UART Jetson TX2 provides UART0 for debug purposes. The connections are shown in Figure 39 and described in the table below. Table 82. Debug UART Connections Jetson TX2 Pin Name UART0_TXD UART0_RXD Type O I UART0_RTS# O UART0_CTS# I Termination Description If level shifter implemented, 100kΩ to supply on the non-Jetson TX2 side of the device. 4.7kΩ to GND or VDD_1V8 on Jetson TX2 for RAM Code strapping If level shifter implemented, 100kΩ to supply on the non-Jetson TX2 side of the device. UART #0 Transmit: Connect to RX pin of serial device UART #0 Receive: Connect to TX pin of serial device UART #0 Request to Send: Connect to CTS pin of serial device UART #0 Clear to Send: Connect to RTS pin of serial device 12.6.3 Boundary Scan Test Mode To support Boundary Scan Test mode, the Tegra NVJTAG_SEL pin must be pulled high and Tegra must be held in reset without resetting the PMIC. The figure below illustrates this. Other requirements related to supporting Boundary Scan Test mode are described in the “Tegra X2 Boundary Scan Requirements & Usage” document. Figure 40. Boundary Scan Connections Jetson TX2 Tegra NVJTAG_SEL JTAG_GP0 100kΩ 100kΩ JTAG_GP1 VDD_1V8 SYS_RESET_N eMMC RESET_OUT# RESET* PMIC RST I/O RESET_IN# 10kΩ B1 3 A11 100kΩ JTAG_TRST_N A46 A47 TRST on JTAG Connector R1 - 0 Ω VDD_1V8 Leave Resistors R1 & R2 uninstalled for normal operation. Install both for boundary scan test mode. R2 - 0Ω Devices requiring system reset & System Reset Sources 1.8V JETSON TX2 OEM PRODUCT | DESIGN GUIDE | 20170912 67 NVIDIA Jetson TX2 OEM Product Design Guide 12.7 Strapping Pins Jetson TX2 has one strap (FORCE_RECOV#) that is intended to be used on the carrier board. That strap is used to enter Force Recovery mode. The other straps mentioned in this section are for use on the module by Nvidia only. They are included here as their state at power-on must be kept at the level selected on the module. Figure 41. Jetson TX2 Strap Connections Tegra Jetson TX2 ~100kΩ 1.8V ~100kΩ ~100kΩ RECOVERY SYS RCM0 Strap GPIO_SW1 GPIO_SW2 GPIO_SW4 FORCE_RECOV# RCM1 Strap SLEEP# RCM2 Strap E2 BT Wake AP (On-Module Bt/Wi-Fi) 1.8V DEBUG E1 VO L DN / SLEEP (See Note) RAM_CODE1 Strap UART3_TX UART7_TX BOOT_SELECT2 Strap 4.7kΩ AO 4.7kΩ RAM_CODE0 Strap UART1_RTS_N UART 0_RTS G11 ~100kΩ UART 1_TX ~100kΩ D9 ~100kΩ UART7_TX UART4_TX UART4_RTS_N UART3_TX SPI ~100kΩ UART 3_RTS Mux 4.7kΩ BOOT_SELECT0 Strap 4.7kΩ ~100kΩ BOOT_SELECT1 Strap 4.7kΩ CONN SEL D8 H10 G10 UART (On-Module Bt/Wi-Fi) QSPI_IO2 Table 83. Power-on Strapping Breakdown Jetson TX2 Pin Name Tegra Ball Name Strap Options FORCE_RECOV# SLEEP# GPIO_SW1 GPIO_SW2 UART1_TX UART0_RTS RSVD-D8 NA (see note 5) NA (see note 5) Note: 1. 2. Jetson TX2 PU/PD RCM0 RCM1 Tegra Internal PU/PD ~100kΩ PU ~100kΩ PU UART3_TX RAM_CODE1 ~100kΩ PD 4.7KΩ PU UART1_RTS_N UART7_TX UART4_TX UART4_RTS_N RAM_CODE0 BOOT_SELECT2 BOOT_SELECT1 BOOT_SELECT0 ~100kΩ PD ~100kΩ PD ~100kΩ PD ~100kΩ PD 4.7KΩ PU 4.7kΩ PD 4.7kΩ PD 4.7kΩ PD Description Recovery Mode [1:0] x1: Normal boot from secondary device 10: Forced Recovery Mode 00: Reserved See critical warning in note 1 [3:2] Selects secondary boot device configuration set within the BCT. For Nvidia use only. [1:0] Selects DRAM configuration set within the BCT. For Nvidia use only. See critical warning in Note 2. Software reads value and determines Boot device to be configured and used 000 = eMMC x8 BootModeOFF, 512-byte page. Maps to SDMMC w/config=0x0001 size. 26MHz 001 – 111 Reserved See Note 3 & 5. See critical warning in Note 4. If the SLEEP# pin is used in a design, it must not be driven or pulled low during power-on at the same time as FORCE_RECOV# is pulled low for Recovery Mode as this would change the strapping and select a reserved mode. Violating this requirement will prevent the system from entering Recovery Mode. If UART1_TX or UART0_RTS are used in a design, they must not be driven or pulled high or low during power-on. Violating this requirement can change the RAM_CODE strapping & result in functional failures. JETSON TX2 OEM PRODUCT | DESIGN GUIDE | 20170912 68 NVIDIA Jetson TX2 OEM Product Design Guide 3. 4. 5. 6. The above BOOT_SELECT option is only in effect in "regular boot" conditions i.e. coldboot. If "Forced Recovery" mode is detected (FORCE_RECOV# low at boot), that mode take precedence over the eMMC boot device choice. If UART7_TX (on RSVD pin) is used in a design, it must not be driven or pulled high during power-on as this would affect the BOOT_SELECT strapping. Violating this requirement will likely prevent the system from booting. eMMC boot does not use either the normal boot mode or alternate boot mode supported by the eMMC spec. The Tegra BootROM uses the Card Identification mode for booting from eMMC. Tegra UART4_TX & UART4_RTS_N are routed to a mux on Jetson TX2 and directed to either UART3_TX/RTS or On-module WLAN/BT. Since these pins are outputs, and the mux is in the path, Jetson TX2 UART3 pins will not affect the Boot Select [1:0] strapping. JETSON TX2 OEM PRODUCT | DESIGN GUIDE | 20170912 69 NVIDIA Jetson TX2 OEM Product Design Guide 13.0 PADS 13.1 MPIO Pad Behavior when Associated Power Rail is Enabled Jetson TX2 CZ (see note) type MPIOs pins may glitch when the associated power rail is enabled or disabled. Designers should take this into account. MPIOs of this type that must maintain a low state even while the power rail is being ramped up or down may require special handling. The CZ type pins are used on the following Jetson TX2 pins: - I2S[3:2]_x SDCARD_x - AO_DMIC_IN_x GPIO[18,17,11,9,8,6]/x CANx Note: The Pin Descriptions section of Jetson TX2 Data Sheet includes the pin type information. 13.2 Internal Pull-ups for CZ Type Pins at Power-on The MPIO pads of type CZ (see note) are on blocks that can be powered at 1.8V or 3.3V. If the associated block is powered at 1.8V, the internal pull-up at initial power-on is not effective. The signal may only be pulled up a fraction of the 1.8V rail. Once the system boots, software can configure the pins for 1.8V operation and the internal pull-ups will work correctly. Signals that need the pull-ups during power-on should have external pull-up resistors added. If the associated block is powered at 3.3V by default, the pull-ups work correctly. The affected pins listed below. These are the Jetson TX2 CZ Type Pins on blocks powered at 1.8V with Power-on-Reset Default of Internal Pull-up Enabled. The SD_CARD pins are CZ type, but the associated power rail is not enabled at power-on – software enables this at a later time. As long as the software configures the pins appropriately for the voltage, the issue will not affect the SD_CARD pins. - CAN1_DOUT CAN1_DIN CAN0_DOUT CAN0_DIN Note: The Pin Descriptions section of Jetson TX2 Data Sheet includes the pin type information. 13.3 Schmitt Trigger Usage The MPIO pins have an option to enable or disable Schmitt Trigger mode on a per-pin basis. This mode is recommended for pins used for edge-sensitive functions such as input clocks, or other functions where each edge detected will affect the operation of a device. Schmitt Trigger mode provides better noise immunity, and can help avoid extra edges from being “seen” by the Tegra inputs. Input clocks include the I2S & SPI clocks (I2Sx_SCLK & SPIx_SCK) when Tegra is in slave mode. The FAN_TACH pin is another input that could be affected by noise on the signal edges. The SD_CARD pin (Tegra SDMMC1_CLK function), while used to output the SD clock, also samples the clock at the input to help with read timing. Therefore, the SD_CARD_CLK pin may benefit from enabling Schmitt Trigger mode. Care should be taken if the Schmitt Trigger mode setting is changed from the default initialization mode as this can have an effect on interface timing. 13.4 Pins Pulled/Driven High During Power-on The Jetson TX2 is powered up before the carrier board (See Power Sequencing section). The table below lists the pins on Jetson TX2 that default to being pulled or driven high. Care must be taken on the carrier board design to ensure that any of these pins that connect to devices on the carrier board (or devices connected to the carrier board) do not cause damage or excessive leakage to those devices. The SD_CARD pins are not included because the associated power rail is not enabled at power-on – software enables this at a later time. Some of the ways to avoid issues with sensitive devices are: ▪ External pull-downs on the carrier board that are strong enough to keep the signals low are one solution, given that this does not affect the function of the pin. This will not work with RESET_IN# which is actively driven high. JETSON TX2 OEM PRODUCT | DESIGN GUIDE | 20170912 70 NVIDIA Jetson TX2 OEM Product Design Guide ▪ Buffers or level shifters can be used to separate the signals from devices that may be affected. The buffer/shifter should be disabled until the device power is enabled. Table 84. Jetson TX2 Pins Pulled/Driven High by Tegra Prior to CARRIER_PWR_ON Active Jetson TX2 Pin DSPK_OUT_CLK SPI1_CS0# RESET_IN# FORCE_RECOV# SLEEP# GPIO7_TOUCH_RST CARRIER_STBY# GPIO5/CAM_FLASH_EN USB0_VBUS_DET SPI2_CS1# SPI2_CS0# UART0_TX UART0_RX WDT_TIME_OUT# Power-on Reset Default Internal Pull-up Internal Pull-up Driven High Internal Pull-up Internal Pull-up Driven High Driven High Internal Pull-up Internal Pull-up Internal Pull-up Internal Pull-up Internal Pull-up Internal Pull-up Driven High Pull-up Strength (kΩ) ~100 ~100 na ~100 ~100 na na ~100 ~100 ~100 ~100 ~100 ~100 na Jetson TX2 Pin JTAG_TMS JTAG_TDI UART1_RX SPI0_MISO SPI0_MOSI CAN1_TX CAN1_RX CAN0_TX CAN0_RX GPIO6_TOUCH_INT GPIO3_CAM1_RST# CAM_VSYNC GPIO2_CAM0_RST# Power-on Reset Default Internal Pull-up Internal Pull-up Internal Pull-up Internal Pull-up Internal Pull-up Internal Pull-up Internal Pull-up Internal Pull-up Internal Pull-up Driven High Internal Pull-up Internal Pull-up Internal Pull-up Pull-up Strength (kΩ) ~100 ~100 ~100 ~100 ~100 ~20 ~20 ~20 ~20 na ~18 ~18 ~18 Table 85. Jetson TX2 Pins Pulled High on the Module Prior to CARRIER_PWR_ON Active Jetson TX2 Pin VIN_PWR_BAD# RESET_OUT# I2C_GP0_CLK/DAT I2C_GP1_CLK/DAT I2C_GP2_CLK/DAT I2C_GP3_CLK/DAT I2C_PM_CLK/DAT I2C_CAM_CLK/DAT Pull-up Supply Voltage (V) 5.0 1.8 1.8 3.3 1.8 1.8 1.8 1.8 External Pull-up (kΩ) 10 4.7 1.0 1.0 1.0 1.0 1.0 1.0 Jetson TX2 Pin USB0_EN_OC# USB1_EN_OC# PEX0_CLKREQ# PEX0_RST# PEX1_CLKREQ# PEX1_RST# PEX2_CLKREQ# PEX2_RST# PEX_WAKE# Pull-up Supply Voltage (V) 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 External Pull-up (kΩ) 100 100 56 56 56 56 56 56 56 13.5 Pad Drive Strength The table below provides the maximum MPIO pad output drive current when the pad is configured for the maximum DRVUP/DRVDN values (11111b). The MPIO pad types include the ST, DD, CZ and LV_CZ type pads. The pad types can be found in the Jetson TX2 Module Data Sheet. Table 86. MPIO Maximum Output Drive Current IOL/IOH +/- 1mA +/- 1mA +/- 1mA +/- 1mA +/- 1mA Pad Type ST DD CZ (1.8V mode) CZ (3.3V mode) LV_CZ VOL 0.15*VDD 0.15*VDD 0.15*VDD 0.15*VDD 0.15*VDD VOH 0.825*VDD 0.8*VDD 0.85*VDD 0.85*VDD 0.85*VDD +/- 2mA +/- 2mA +/- 2mA +/- 2mA +/- 2mA ST DD CZ (1.8V mode) CZ (3.3V mode) LV_CZ 0.15*VDD 0.175*VDD 0.25*VDD 0.15*VDD 0.25*VDD 0.7*VDD 0.7*VDD 0.75*VDD 0.75*VDD 0.75*VDD JETSON TX2 OEM PRODUCT | DESIGN GUIDE | 20170912 71 NVIDIA Jetson TX2 OEM Product Design Guide 14.0 UNUSED INTERFACE TERMINATIONS 14.1 Unused MPIO Interfaces The following Jetson TX2 pins (& groups of pins) are Jetson TX2 MPIO (Multi-purpose Standard CMOS Pad) pins that support either special function IOs (SFIO) and/or GPIO capabilities. Any unused pins or portions of pin groups listed below that are not used can be left unconnected. Table 87. Unused MPIO pins / Pin Groups Jetson TX2 Pins / Pin Groups SLEEP# BATLOW# FORCE_RECOV# RESET_OUT# WDT_TIME_OUT# CARRIER_STBY# CHARGER_PRSNT# CHARGING# USBx_EN_OC# PEXx_REFCLK/RST/CLKREQ/WAKE LCD0_BKLT_PWM, FAN_PWM CAN LCD_x DP0_HPD, DP1_HPD, HDMI_CEC CAM Control, Clock Jetson TX2 Pins / Pin Groups SDIO, SDMMC AUDIO_x I2S DMIC DSPK UART I2C SPI TOUCH_x WIFI_WAKE_x MODEM_x, MDM2AP_x, AP2MDM_x GPIO_EXP[1:0]_INT ALS_PROX_INT, MOTION_INT JTAG 14.2 Unused SFIO Interface Pins See the Unused SFIO (Special Function I/O) interface pins section in the Checklist at the end of this document. JETSON TX2 OEM PRODUCT | DESIGN GUIDE | 20170912 72 NVIDIA Jetson TX2 OEM Product Design Guide 15.0 DESIGN CHECKLIST The checklist below is intended to help ensure that the correct connections have been made in a design. The check items describe connections for the various interfaces and the “Same/Diff/NA” column is intended to be used to indicate whether the design matches the check item description, is different, or is not applicable to the design. Table 88. Checklist Same/Diff/NA Check Item Description Jetson TX2 Signal Terminations (Present on the module - shown for reference only) Note: Internal refers to Tegra internal Pull-up/down resistors. External refers to resistors added on the module. Parallel Termination Series Termination USB0_EN_OC# USB1_EN_OC# USB0_VBUS_DET External 100KΩ pull-up to 3.3V External 100KΩ pull-up to 3.3V PEX0_CLKREQ# PEX0_RST# PEX1_CLKREQ# PEX1_RST# PEX2_CLKREQ# PEX2_RST# PEX_WAKE# External 56KΩ pull-up to 3.3V External 56KΩ pull-up to 3.3V External 56KΩ pull-up to 3.3V External 56KΩ pull-up to 3.3V External 56KΩ pull-up to 3.3V External 56KΩ pull-up to 3.3V External 56KΩ pull-up to 3.3V – – Level shifter between Tegra & Jetson TX2 USB0_VBUS_DET pin – – – – – – – Internal pull-down Internal pull-down – – External 1KΩ pull-up to 1.8V External 1KΩ pull-up to 3.3V External 1KΩ pull-up to 1.8V External 1KΩ pull-up to 1.8V External 1KΩ pull-up to 1.8V External 1KΩ Pull Up to 1.8V – – – – – – Internal pull-down Internal pull-down Internal pull-down Internal pull-up to 1.8V Internal pull-down Internal pull-down Internal pull-down Internal pull-up to 1.8V Internal pull-up to 1.8V Internal Pull Down Internal Pull Down Internal Pull Down Internal pull-up to 1.8V Internal pull-up to 1.8V – – – – – – – – – – – – – – Internal pull-up to 1.8V/3.3V Internal pull-up to 1.8V/3.3V Internal pull-up to 1.8V Internal pull-up to 1.8V – – – – Internal pull-down – Internal pull-down to GND Internal pull-down to GND – – USB/PCIe HDMI/DP/eDP DP0_HPD DP1_HPD I2C I2C_GP0_CLK/DAT I2C_GP1_CLK/DAT I2C_GP2_CLK/DAT I2C_GP3_CLK/DAT I2C_PM_CLK/DAT I2C_CAM_CLK/DAT SPI SPI0_MOSI SPI0_MISO SPI0_CLK SPI0_CS0# SPI1_MOSI SPI1_MISO SPI1_CLK SPI1_CS0# SPI1_CS1# SPI2_MOSI SPI2_MISO SPI2_CLK SPI2_CS0# SPI2_CS1# SD Card SDCARD_CMD SDCARD_D[3:0] SDCARD_CD# SDCARD_WP Embedded Display LCD_TE GPIO GPIO0_CAM0_PWR GPIO1_CAM1_PWR JETSON TX2 OEM PRODUCT | DESIGN GUIDE | 20170912 73 NVIDIA Jetson TX2 OEM Product Design Guide GPIO2_CAM0_RST GPIO3_CAM1_RST GPIO4_CAM_STROBE GPIO5_CAM_FLASH_EN GPIO6/TOUCH_INT GPIO7/TOUCH_RST GPIO8/ALS_PROX_INT GPIO9/MOTION_INT GPIO10/WIFI_WAKE_AP GPIO11_AP_WAKE_BT GPIO12_BT_EN GPIO13/BT_WAKE_AP GPIO14_AP_WAKE_MDM GPIO15_AP2MDM_READY GPIO16/MDM_WAKE_AP GPIO17/MDM2AP_READY GPIO18/MDM_COLDBOOT GPIO19/AUD_RST GPIO20/AUD_INT GPIO_EXP0_INT GPIO_EXP1_INT Internal pull-up to 1.8V Internal pull-up to 1.8V Internal pull-down to GND Internal pull-up to 1.8V Internal pull-up to 1.8V (Driven high) Internal pull-up to 1.8V Internal pull-up to 1.8V Internal pull-up to 1.8V Internal pull-down to GND Internal pull-down to GND Internal pull-up to 1.8V (Driven low) (Driven low) Internal pull-up to 1.8V Internal pull-up to 1.8V Internal pull-up to 1.8V Internal pull-up to 1.8V Internal pull-up to 1.8V Internal pull-up to 1.8V Internal pull-up to 1.8V – – – – – – – – – – – – – – – – – – – – – External 10kΩ pull-up to 3.8V External 10kΩ pull-up to 3.3V Internal pull-up to 1.8V Internal pull-up to 1.8V Internal Pull Up to 1.8V near Tegra & PMIC internal Pull-up to 5.0V on other side of diodes (module pin side) External 10kΩ pull-up to 1.8V External 100kΩ pull-up to 1.8V near Tegra (module pin side) & external 10kΩ pull-up to 1.8V on the other side of a diode Internal pull-up to 1.8V – System Control VIN_PWR_BAD# CARRIER_PWR_ON FORCE_RECOV# SLEEP# POWER_BTN# RESET_IN# RESET_OUT# FAN_TACH – – BAT54CW Schottky barrier diodes – Charging CHARGER_PRSNT# CHARGING# BATLOW# External 4.7kΩ pull-up to 5V & Internal – PMIC pull-up to 5.0V once FET is enabled by VDD_IN on & VIN_PWR_BAD# inactive. Internal pull-up to 1.8V – Internal pull-up to 1.8V – JTAG JTAG_TCK JTAG_GP0 JTAG_GP1 External 100KΩ pull-down to GND – External 100KΩ pull-down to GND & 0.1uF – capacitor to GND External 100KΩ pull-down to GND Carrier Board Signal Terminations (To be implemented on the carrier board for interfaces that are used) Parallel Termination Series Termination – – – – – – – – – – – – 0.1uF capacitors 0.1uF capacitors 0.1uF capacitors if directly connected 0.1uF capacitors directly connected 0.1uF capacitors 0.1uF capacitors 0.1uF capacitors 0.1uF capacitors 0.1uF capacitors if directly connected 0.1uF capacitors if directly connected 0.1uF capacitors if directly connected 0.1uF capacitors USB/PCIe/SATA USB_SS0_TX+/USB_SS1_TX+/USB_SS0_RX+/USB_SS1_RX+/PEX0_TX+/PEX1_TX+/PEX2_TX+/PEX_RFU_TX+/PEX0_RX+/PEX1_RX+/PEX2_RX+/PEX_RFU_RX+/- JETSON TX2 OEM PRODUCT | DESIGN GUIDE | 20170912 74 NVIDIA Jetson TX2 OEM Product Design Guide SATA_TX+/SATA_RX+/SATA_DEV_SLP – – – 0.01uF capacitors 0.01uF capacitors 1.8V to 3.3V Level Shifter – – – – – – – Magnetics near RJ45 connector Magnetics near RJ45 connector Magnetics near RJ45 connector Magnetics near RJ45 connector LED and pull-up Current Limiting Circuit LED and pull-up Current Limiting Circuit LED and pull-up Current Limiting Circuit – – – – 100kΩ Pull-down to GND near connector (DP only) 100kΩ Pull-up to 3.3V near connector (DP only) 10kΩ Pull-up to 1.8V near main conn. & 100kΩ Pull-down to GND on DP side of level shifter. 0.1uF capacitors 0.1uF capacitors 0.1uF capacitors 0.1uF capacitors 0.1uF capacitor 499Ω, 1% resistor to 600Ω bead to GND 499Ω, 1% resistor to 600Ω bead to GND 499Ω, 1% resistor to 600Ω bead to GND 499Ω, 1% resistor to 600Ω bead to GND 10kΩ Pull-up to 3.3V near main conn. & 1.8kΩ Pull-up to 5V near HDMI conn. 10kΩ Pull-up to 1.8V near main conn. & 100kΩ Pull-down to GND near HDMI conn. 0.1uF capacitors 0.1uF capacitors 0.1uF capacitors 0.1uF capacitors Bidirectional level shifter between Pull-ups in Parallel Termination column Level shifter (w/output toward main connector) between Pull-up & Pull-down in Parallel Termination column. Level shifter can be inverting or non-inverting. 100kΩ series resistor between pull-down & HDMI connector. Ethernet GBE_MDI0+/GBE_MDI1+/GBE_MDI2+/GBE_MDI3+/GBE_LINK100# GBE_LINK1000# GBE_LINK_ACT# DP[1:0] for eDP/DP DPx_TX3+/DPx_TX2+/DPx_TX1+/DPx_TX0+/DPx_AUX_CH+ DPx_AUX_CHDPx_HPD 0.1uF capacitor Level Shifter (w/output toward main connector) near main connector & 100kΩ resistor to DP connector. Level shifter must be non-inverting. DP[1:0] for HDMI DPx_TX3+/DPx_TX2+/DPx_TX1+/DPx_TX0+/DPx_AUX_CH+/DPx_HPD Power Jetson TX2 Power Supplies Supply (Carrier Board) VDD_IN Usage Main Supply from Adapter (V) 5.519.6 1.655.5 Supply Type Adapter Source na Enable na VDD_RTC Real-time clock supply PMIC is supply when charging cap or coin cell Super cap or coin cell is source when system power removed na Main power input from DC Adapter Main 5V supply Main 3.3V supply Main 1.8V supply 5.519.6 5.0 3.3 1.8 FETs DC Adapter DC/DC DC/DC DC/DC VDD_MUX VDD_MUX VDD_5V0_IO_SYS 3.3V rail, off in Sleep (various) 5V rail, off in Sleep (SATA/FAN) PCIe & SATA connectors VBUS (USB 2.0 Type AB conn) VBUS (USB 3.0 Type A conn) SD Card power rail 5V rail for HDMI connector 1.8V rail for touch screen 3.3 FETs/Load Switch FETs/Load Switch Boost Load Switch Load Switch Load Switch Load Switch Load Switch VDD_3V3_SYS CARRIER_PWR_ON 3V3_SYS_BUCK_EN 1V8_IO_VREG_EN (VDD_3V3_SYS_PG) SOC_PWR_REQ VDD_5V0_IO_SYS VDD_3V3_SLP VDD_5V0_IO_SYS VDD_5V0_IO_SYS VDD_5V0_IO_SYS VDD_3V3_SYS VDD_5V0_IO_SYS VDD_1V8 VDD_3V3_SLP USB_VBUS_EN0 USB_VBUS_EN1 SDCARD_VDD_EN GPIO Expander U29, P14 GPIO Expander U29, P01 Carrier Board Supplies VDD_MUX VDD_5V0_IO_SYS VDD_3V3_SYS VDD_1V8 VDD_3V3_SLP VDD_5V0_IO_SLP VDD_12V_SLP VDD_VBUS_CON USB_VBUS SD_CARD_SW_PWR VDD_5V0_HDMI_CON VDD_TS_1V8 JETSON TX2 OEM PRODUCT | DESIGN GUIDE | 20170912 5 12 5.0 5.0 3.3 5.0 1.8 75 NVIDIA Jetson TX2 OEM Product Design Guide AVDD_TS_DIS VDD_LCD_1V8_DIS VDD_DIS_3V3_LCD VDD_1V2 DVDD_CAM_IO_1V8 AVDD_CAM DVDD_CAM_IO_1V2 High voltage rail for touch screen 1.8V rail for panel High voltage rail for panel Generic 1.2V display rail 1.8V rail for camera I/O High voltage rail for cameras 1.2V rail for camera Core 3.3 Load Switch VDD_3V3_SLP 1.8 3.3 1.2 1.8 2.8 1.2 Load Switch Load Switch LDO Load Switch Load Switch LDO VDD_1V8 VDD_3V3_SYS VDD_1V8 VDD_1V8 VDD_3V3_SLP VDD_1V8 GPIO Expander U29, P02 GPIO Expander U29, P11 GPIO Expander U29, P03 GPIO Expander U29, P12 GPIO Expander U28, P11 GPIO Expander U29, P15 GPIO Expander U28, P12 Power Control VIN_PWR_BAD# connects to Carrier Board main power input & discharge circuit. Inactive when main supply is stable CARRIER_PWR_ON used as enable for Carrier Board main 5V supply & discharge circuit RESET_IN# to/from carrier board connects to devices requiring full system reset, and to system reset sources (reset button, etc.) RESET_OUT# to Jetson TX2 from Carrier Board when a force reset is required (as for Boundary Scan test mode) POWER_BTN# connects to button or similar to pull POWER_BTN# to GND when pressed/asserted to power system ON/OFF SLEEP# connects to button or similar to pull SLEEP# to GND when pressed/asserted to put system in sleep mode CARRIER_STBY# connects to enable of supplies that should be off in Sleep mode such as VDD_3V3_SLP Power Discharge VIN_PWR_BAD# connects to Carrier Board main power input & discharge circuit. Inactive when main supply is stable VDD_5V0_IO_SYS Discharge implemented: FET enabled by DISCHARGE w/Source GND'd & 100Ω to VDD_5V0_IO_SYS VDD_3V3_SYS Discharge implemented: FET enabled by DISCHARGE w/Source GND'd & 47Ω to VDD_3V3_SYS VDD_1V8 Discharge implemented: FET enabled by DISCHARGE w/Source GND'd & 36Ω to VDD_1V8 VDD_3V3_SLP Discharge implemented: FET enabled by DISCHARGE w/Source GND'd & 47Ω to VDD_3V3_SLP VDD_12V_SLP Discharge implemented: FET enabled by DISCHARGE & VDD_3V3_SLP w/Source GND'd & 2x470Ω to VDD_12V_SLP VDD_5V0_IO_SLP Discharge implemented: FET enabled by DISCHARGE & VDD_3V3_SLP w/Source GND'd & 100Ω to VDD_5V0_IO_SLP Wake Event Pins If Audio Interrupt required, GPIO20_AUD_INT pin is used If External BT Wake Request to AP required, GPIO13_BT_WAKE_AP pin is used If External WLAN Wake Request to AP required, GPIO10_WIFI_WAKE_AP pin is used If Modem to AP Ready required, GPIO17_MDM2AP_READY pin is used If Modem Coldboot Alert required, GPIO18_MDM_COLDBOOT pin is used If HDMI CEC required, HDMI_CEC pin is used If GPIO Exapander 0 Interrupt required, GPIO_EXP0_INT pin is used If Power Button On required, POWER_BTN# pin is used If Charging Interrupt required, CHARGING# pin is used If Sleep Request from Carrier Board required, SLEEP# pin is used If Ambient/Proximity Interrupt required, GPIO8_ALS_PROX_INT pin is used If HDMI Hot Plug Detect required, DP1_HPD pin is used If Battery Low Warning required, BATLOW# pin is used If Primary Modem Wake Request to AP required, GPIO16_MDM_WAKE_AP pin is used If Touch Controller Interrupt required, GPIO6_TOUCH_INT pin is used If Motion Sensor Interrupt required, GPIO9_MOTION_INT pin is used USB/PEX/SATA Connections USB 2.0 USB0 available to be used as device for USB recovery at a minimum USB ID from connector, if used, connects to Jetson TX2 USB0_OTG_ID pin VBUS from connector connects to load switch (if host supported) and USB0_VBUS_DET pin on Jetson TX2 (100kΩ resistor to GND required) USB[2:0]_DP/DN connected to D+/D- pins on USB 2.0 connector/device. Any EMI/ESD devices used are suitable for USB High-speed USB 3.0 USB_SS0_RX+/– connected to RX+/- pins on USB 3.0 connector, Device, Hub, etc. (muxed w/PCIe #2 on module) USB_SS0_TX+/– connected to TX+/- pins on USB 3.0 conn., Device, Hub, etc. (muxed w/PCIe #2 on module - See Signal Terminations) Additional USB 3.0 interfaces taken from USB_SS1 or PEX_RFU (See Signal Terminations) See USB 3.0 section for Common Mode Choke requirements if this is required. TDK ACM2012D-900-2P device is recommended See USB 3.0 section for ESD requirements. SEMTECH ESD Rclamp0524p device is recommended PCIe PCIe Controller #0 (x1 by default – supports up to x4. Lanes [2:1] of x4 configuration shared w/USB_SS#[2:1] PEX0 used for 3.3V single-lane device/connector (lane 0 of PCIe x1 connector on reference Carrier Board) PEX0 & USB_SS1 used for 3.3V 2-lane device/connector PEX0, USB_SS1, PEX2 & PEX_RFU used for 3.3V 4-lane device/connector TX+/– connected to corresponding pins on connector, or RX+/– on device on the carrier board (See Signal Terminations) JETSON TX2 OEM PRODUCT | DESIGN GUIDE | 20170912 76 NVIDIA Jetson TX2 OEM Product Design Guide RX+/– connected to corresponding pins on connector, or TX+/– on device on the carrier board AC caps are provided for device TX pins (those connected to Jetson TX2 RX+/–) if device is on the carrier board (See Signal Terminations) Reference clock used for PCIe Controller #0 (Up to x4 lane PCIe interface) is PEX0_REFCLK+/– Clock Request & Reset for PCIe Controller #0 are PEX0_CLKREQ# & PEX0_RST# PCIe Controller #1 (x1 – Shared with PCIe Controller #0 lane 2) PEX2 used for 3.3V single-lane device/connector TX+/– connected to corresponding pins on connector, or RX+/– on device on the carrier board (See Signal Terminations) RX+/– connected to corresponding pins on connector, or TX+/– on device on the carrier board AC caps are provided for device TX pins (those connected to Jetson TX2 RX+/–) if device is on the carrier board (See Signal Terminations) Reference clock used for PCIe Controller #1 (single-lane PCIe interface) is PEX2_REFCLK+/– Clock Request & Reset for PCIe Controller #1 are PEX2_CLKREQ# & PEX2_RST# (See Signal Terminations) PCIe Controller #2 (x1) PEX1 used for 3.3V single-lane device/connector (M.2 connector on Jetson carrier board) or USB_SS#0 (controlled by on module mux) TX+/– connected to corresponding pins on connector, or RX+/– on device on the carrier board (See Signal Terminations) RX+/– connected to corresponding pins on connector, or TX+/– on device on the carrier board AC caps are provided for device TX pins (those connected to Jetson TX2 RX+/–) if device is on the carrier board (See Signal Terminations) Reference clock used for PCIe Controller #2 (single-lane PCIe interface) is PEX1_REFCLK+/– Clock Request & Reset for PCIe Controller #1 are PEX1_CLKREQ# & PEX1_RST# (PEX1_CLKREQ# muxed with SATA_DEV_SLP on module See Signal Terminations) Common PEX_WAKE# connected to WAKE pins on devices/connectors (See Signal Terminations) SATA SATA_TX+/– connected to TX_P/N pins of SATA connector (or RX+/– pins of onboard device) (See Signal Terminations) SATA_RX+/– connected to RX_P/N pins of SATA connector (or TX+/– pins of onboard device) (See Signal Terminations) See SATA section for Common Mode Choke requirements if they are required. TDK ACM2012D-900-2P device is recommended See SATA section for ESD requirements. SEMTECH ESD Rclamp0524p device is recommended SATA_DEV_SLP connected to matching pin on device or connector (pin 10 on conn. shown in SATA section – See Signal Terminations) Ethernet GBE_MDI[3:0]+/ – connected to equivalent pins on magnetics device (See Signal Terminations) GBE_LINK_ACT, GBE_LINK100 & GBE_LINK1000 connected to LED pins on connector (See Signal Terminations) GBE_CTVREF – Not used. Leave NC. SDMMC Connections SD Card SDCARD_CLK connected to CLK pin of socket/device SDCARD_CMD connected to CMD pin of socket/device. (See Signal Terminations) SDCARD_D[3:0] connected to DATA[3:0] pins of socket/device. (See Signal Terminations) SDCARD_CD connected to the SD Card Detect pin on socket SDCARD_WP connected to the SD Card Write Protect pin on socket (if supported) SDCARD_PWR_EN connected to SD Card VDD supply/load switch enable pin Adequate bypass caps provided on SD Card VDD rail Any EMI/ESD devices used are suitable for highest frequencies supported (low capacitive load: <1pf recommended). Display Connections DSI DSI Dual Link Configurations DSI0_CK+/– connected to CLKp/n pins of the lower x4 DSI interface of display DSI0_D[1:0] +/– connected to lower 2 data lanes of the lower x4 DSI interface of display DSI1_D[1:0] +/– connected to upper 2 data lanes of the lower x4 DSI interface of display DSI2_CK+/– connected to CLKp/n pins of the upper x4 DSI interface of display or a x4 DSI interface of secondary display DSI2_D[1:0] +/– connected to lower 2 data lanes of the upper x4 DSI interface of display or lower 2 lanes of secondary display DSI3_D[1:0] +/– connected to upper 2 data lanes of the upper x4 DSI interface of display or upper 2 lanes of secondary display Any EMI/ESD devices used on DSI signals are suitable for highest frequencies supported (low capacitive load: <1pf recommended) DSI Split Link Configurations DSI0_CK+/– connected to CLKp/n pins of the 1st x2 DSI interface of split link display DSI0_D[1:0] +/– connected to up to 2 data lanes of the 1st x1/x2 DSI interface of split link display DSI1_CK+/– connected to CLKp/n pins of the 2nd x2 DSI interface of split link display DSI1_D[1:0] +/– connected to up to 2 data lanes of the 2nd x1/x2 DSI interface of split link display DSI2_CK+/– connected to CLKp/n pins of the 3rd x2 DSI interface of split link display DSI2_D[1:0] +/– connected to up to 2 data lanes of the 3rd x1/x2 DSI interface of split link display DSI3_CK+/– connected to CLKp/n pins of the 4th x2 DSI interface of split link display DSI3_D[1:0] +/– connected to up to 2 data lanes of the 4th x1/x2 DSI interface of split link display Any EMI/ESD devices used on DSI signals are suitable for highest frequencies supported (low capacitive load: <1pf recommended) JETSON TX2 OEM PRODUCT | DESIGN GUIDE | 20170912 77 NVIDIA Jetson TX2 OEM Product Design Guide Display Control Connections LCD_TE (used for Tearing Effect signal from display) connected to matching pin on display connector if supported LCD_VDD_EN connected to enable of embedded display related power supply/load switch LCD_BKLT_EN connected to enable of backlight solution(s) LCD[1:0]_BKLT_PWM connected to PWM input(s) of backlight solution(s) eDP / DP DPx_TX[3:0]+/– connected to D[3:0]+/– pins on eDP/DP connector (See DP/HDMI Pin Mapping table & Signal Terminations) DPx_AUX_CH+/– connected to Aux Lane of panel/connector (See Signal Terminations) DPx_HPD connected to HPD pin of panel/connector Any EMI/ESD devices used are suitable for highest frequencies supported (low capacitive load: <1pf recommended) HDMI DPx_TX3+/– connected to C–/C+ & pins on HDMI Connector (See Signal Terminations) DPx_TX[2:0]+/– connected to D[0:2]+/– pins (See DP/HDMI Pin Mapping table) (See Signal Terminations) DPx_HPD connected to HPD pin on HDMI Connector (See Signal Terminations) HDMI_CEC connected to CEC on HDMI Connector through gating circuitry. DPx_AUX_CH+ connected to SCL & DPx_AUX_CH– to SDA on HDMI Connector (See Signal Terminations) HDMI 5V Supply connected to +5V on HDMI Connector. See HDMI section for Common Mode Choke requirements if this is required (not recommended unless EMI issues seen) See HDMI section for ESD requirements. ON-Semiconductor ESD8040 device is recommended Video Input Camera (CSI) CSI[5:0]_CLK+/– connected to clock pins of camera. See CSI D-PHY Configurations table for details CSI[5:0]_D[1:0]+/– connected to data pins of camera. See CSI D-PHY Configurations table for details Any EMI/ESD devices used are suitable for highest frequencies supported (low capacitive load: <1pf recommended) Control I2C_CAM_CK/DAT connected to I2C SCL & SDA pins of imager (See Signal Terminations). CAM[1:0]_MCLK connected to Camera reference clock inputs. GPIO1_CAM1_PWR# / GPIO0_CAM0_PWR# connected to powerdown pins on camera(s). GPIO4_CAM_STROBE connected to camera strobe circuit unless strobe control comes from camera module. CAM_FLASH_EN connected to enable of flash circuit If a Jetson TX2 GPIO is used for flash control, CAM_FLASH_EN and/or CAMR_STROBE pins are used GPIO3_CAM1_RST# / GPIO2_CAM0_RST# connected to reset pin on any cameras with this function. If AutoFocus Enable is required, GPIO3_CAM1_RST# connected to AF_EN pin on camera module & GPIO2_CAM0_RST# used as common reset line. Audio Codec/I2S/DMIC/DSPK I2S0 used for Audio Codec if present in design I2S2 used for BT if present in design I2S[3:0]_SCLK Connect to I2S/PCM CLK pin of audio device. I2S[3:0]_LRCK Connect to Left/Right Clock pin of audio device. I2S[3:0]_SDATA_OUT Connect to Data Input pin of audio device. I2S[3:0]_SDATA_IN Connect to Data Output pin of audio device. AUD_MCLK Connect to clock pin of Audio Codec. GPIO8_AUD_RST Connect to reset pin of Audio Codec. GPIO9_AUD_INT Connect to interrupt pin of Audio Codec. AO_DMIC_IN_CLK/DAT connect to CLK/DAT pins of digital mic DSPK_OUT_CLK/DAT connect to CLK/DAT pins of digital speaker driver I2C/SPI/UART I2C I2C devices on same I2C interface do not have address conflicts (comparisons are done 7-bit to 7-bit format or 8-bit to 8-bit format) I2C_CAM, I2C_GP0, I2C_GP2, I2C_GP3 & I2C_PM (See Signal Terminations). Additional external pull-ups are not added unless stronger pull-up than on module required. Devices on bus are 1.8V or level shifter is used. I2C_GP1 (See Signal Terminations). Additional external pull-ups are not added unless stronger pull-up than on module required & devices on bus are 3.3V or level shifter is used. Pull-up resistors are provided on the non-Jetson TX2 side of any level shifters. Pull-up resistor values based on frequency/load (check I2C Spec) I2C_CAM_CK/DAT, I2C_GP[3:0]_CK/DAT & I2C_PM_CK/DAT connect to SCL/SDA pins of devices SPI SPI[2:0]_CLK connected to Peripheral CLK pin(s) SPI[2:0]_MOSI connected to Slave Peripheral MOSI pin(s) JETSON TX2 OEM PRODUCT | DESIGN GUIDE | 20170912 78 NVIDIA Jetson TX2 OEM Product Design Guide SPI[2:0]_MISO connected to Slave Peripheral MISO pin(s) SPI[2:1]_CS[1:0]# / SPI0_CS0# connected one CS# pin per SPI IF to each Slave Peripheral CS pin on the interface CAN CAN[1:0]_TX connected to input data (RX) pins of respective CAN device CAN[1:0]_RX connected to output data (TX) pin of respective CAN device CAN1_STBY connected to Standby pin of respective CAN device CAN[1:0]_ERR connected to Error pin of respective CAN device CAN_WAKE connected to Wake pin of CAN devices UART UARTx_TX connects to Peripheral RX pin of device UARTx_RX connects to Peripheral TX pin of device UARTx_CTS# connects to Peripheral RTS# pin of device UARTx_RTS# connects to Peripheral CTS# pin of device Miscellaneous JTAG JTAG_TMS Connect to TMS pin of connector JTAG_TCK Connect to TCK pin of connector (See Signal Terminations). JTAG_TDO Connect to TDO pin of connector JTAG_TDI Connect to TDI pin of connector JTAG_RTCLK Connect to RTCK pin of connector JTAG_GP0 (JTAG_TRST#): Connect to TRST pin of connector JTAG_GP1 (NVJTAG_SEL): For Boundary Scan test mode, NVJTAG_SEL is connected to VDD_1V8. (See Signal Terminations). JTAG_GP1 (NVJTAG_SEL): For normal operation, NVJTAG_SEL is pullled down. (See Signal Terminations). Strapping FORCE_RECOV#: To enter Forced Recovery mode, pin is connected to GND when system is powered on. All other module pins associated with strapping on Tegra X2: Ensure any devices connected to module pins associated with Tegra X2 straps do not affect the level of the straps at power-on. Module pins affected are: SLEEP#, UART1_TX, UART0_RTS, RSVD-D8 (UART7_TX) Pin Selection Pinmux completed including GPIO usage (direction, initial state, Ext. PU/PD resistors, Deep Sleep state). SFIO usage matches reference platform where possible. Each SFIO function assigned to only one pin, even if function selected in Pinmux registers is not used or pin used as GPIO GPIO usage matches reference platform where possible. Unused SFIO (Special Function I/O) Interface Pins Ball Name USB 2.0 Termination USB[2:1]+/– Leave NC any unused pins *USB 3.0 / PCIe PEX_[2:0]_TX+/–, USB_SS[1:0]_TX+/–, PEX_RFU_TX+/– PEX_[2:0]_RX+/–, USB_SS[1:0]_RX+/–, PEX_RFU_RX+/– PEX_[2:0]_REFCLK+/– Leave NC any unused TX lines Connect to GND any unused RX lines Leave NC if not used SATA SATA_TX+/– SATA_RX+/– Leave NC if not used. Connect to GND if SATA IF not used DSI DSI[3:0]_CK+/– DSI[3:0]_D[1:0]+/– Leave NC any Clock lane not used. Leave NC any unused DSI Data lanes CSI CSI[5:0]_CK+/– CSI[5:0]_D[1:0] +/– Leave NC any unused CSI Clock lanes Leave NC any unused CSI Data lanes eDP/DP DPx_TX[3:0] +/– DPx_AUX_CH+/– DPx_HPD Leave NC any unused lanes Leave NC if not used Leave NC if not used HDMI DPx_TX[3:0] +/– Leave NC if lanes not used for HDMI or DP JETSON TX2 OEM PRODUCT | DESIGN GUIDE | 20170912 79 NVIDIA Jetson TX2 OEM Product Design Guide DPx_AUX_CH+/– DPx_HPD HDMI_CEC Leave NC if not used Leave NC if not used Leave NC if not used JETSON TX2 OEM PRODUCT | DESIGN GUIDE | 20170912 80 NVIDIA Jetson TX2 OEM Product Design Guide 16.0 APPENDIX A: GENERAL LAYOUT GUIDELINES 16.1 Overview Trace and via characteristics play an important role in signal integrity and power distribution on Jetson TX2. Vias can have a strong impact on power distribution and signal noise, so careful planning must take place to ensure designs meet NVIDIA’s via requirements. Trace length and impedance determine signal propagation time and reflections, both of which can greatly improve or reduce the performance of Jetson TX2. Trace and via requirements for each signal type can be found in the corresponding chapter; this appendix provides general guidelines for via and trace placement. 16.2 Via Guidelines The number of vias in the path of a given signal, power supply line, or ground line can greatly affect the performance of the trace. Via placement can make differences in current carrying capability, signal integrity (due to reflections and attenuation), and noise generation, all of which can impact the overall performance of the trace. The following guidelines provide basic advice for proper use of vias. 16.2.1 Via Count and Trace Width As a general rule, each ampere of current requires at least two micro-vias. 16.2.2 Via Placement If vias are not placed carefully, they can severely degrade the robustness of a board’s power plane. In standard deigns that don’t use blind or buried vias, construction of a via entails drilling a hole that cuts into the power and ground planes. Thus, incorrect via placement affects the amount of copper available to carry current to the power balls of the IC. 16.2.3 Via Placement and Power/Ground Corridors Vias should be placed so that sufficiently wide power corridors are created for good power distribution, as show in Figure 42. Figure 42. Via Placement for Good Power Distribution Care should also be taken to avoid use of “thermal spokes” (also referred to as “thermal relief”) on power and ground vias. Thermal spokes are not necessary for surface-mount components, and the narrow spoke widths contribute to increased inductance. The metal on the inner layers between vias may not be flooded with copper if sufficient spacing is not provided. The diminished spacing creates a blockage and forces the current to find another path due to lack of copper, as shown in Figure 43 and Figure 44. This leads to power delivery issues and impedance discontinuities when traces are routed over these plane voids. JETSON TX2 OEM PRODUCT | DESIGN GUIDE | 20170912 81 NVIDIA Jetson TX2 OEM Product Design Guide Figure 43. Good Current Flow Resulting from Correct Via Placement Current Flow Current Flow With sufficient via spacing Correct via implementation Figure 44. Poor Current Flow Resulting from Incorrect via Placement Current Flow Current Flow With insufficient via spacing Incorrect via implementation In general, a dense via population should be avoided and good PCB design principles and analysis should be applied. 16.3 Connecting Vias To be effective, vias must be connected properly to the signal and power planes. Poor via connections make the capacitor and power planes less effective, leading to increased cost due to the need for additional capacitors to achieve equivalent performance. This not only impacts the BOM (Bill of Material) cost of the design, but it can greatly impact quality and reliability of the design. 16.4 Trace Guidelines Trace length and impedance play a critical role in signal integrity between the driver and the receiver on Jetson TX2. Signal trace requirements are determined by the driver characteristics, source characteristics, and signal frequency of the propagating signal. 16.4.1 Layer Stack-Up The number of layers required is determined by the number of memory signal layers needed to achieve the desired performance, and the number of power rails required to achieve the optimum power delivery/noise floor. For example, highperformance boards require four memory signal routing layers, with at least two GND planes for reference. This comes to six layers; add another two for power, which gives eight layers minimum. Reduction from eight to six layers starts the trade-off of cost versus performance. Power and GND planes usually serve two purposes in PCB design: power distribution and providing a signal reference for highspeed signals. Either the power or the ground planes can be used for high-speed signal reference; this is particularly common for low-cost designs with a low layer count. When both power and GND are used for signal reference, make sure you minimize the reference plane transition for all high-speed signals. Decoupling caps or transition vias should be added close to the reference plane transitions. JETSON TX2 OEM PRODUCT | DESIGN GUIDE | 20170912 82 NVIDIA Jetson TX2 OEM Product Design Guide 16.4.2 Trace Length The maximum trace length for a given signal is determined by the maximum allowable propagation delay and impedance for the signal. Higher frequency signals must be treated as transmission lines (see “Appendix C – Transmission Line Primer”) to determine proper trace characteristics for a signal. All signals on the graphics card maintain different trace guidelines; please refer to the corresponding signal chapter in the Design Guide to determine the guidelines for the signal. JETSON TX2 OEM PRODUCT | DESIGN GUIDE | 20170912 83 NVIDIA Jetson TX2 OEM Product Design Guide 17.0 APPENDIX B: STACK-UPS 17.1 Reference Design Stack-Ups 17.1.1 Importance of Stack-Up Definition Stack-ups define the number and order of Board layers. Stack-up definition is critical to the following design: ▪ ▪ ▪ Circuit routability Signal quality Cost 17.1.2 Impact of Stack-Up Definition on Design Stack-Up Impact on Circuit Routability If there are insufficient layers to maintain proper signal spacing, prevent discontinuities in reference planes, obstruct flow of sufficient current, or avoid extra vias, circuit routing can become unnecessarily complex. Layer count must be minimally appropriate for the circuit. Stack-Up Impact on Signal Quality Both layer count and layer order impact signal integrity. Proper inter-signal spacing must be achievable. Via count for critical signals must be minimized. Current commensurate with the performance of the board must be carried. Critical signals must be adjacent to major and minor reference planes, and adhere to proximity constraints with respect to those planes. The recommended NVIDIA stack-ups achieve these requirements for the signal speeds supported by the board. Stack-Up Impact on Cost While defining extra layers can facilitate excellent signal integrity, current handling capability and routability, extra layers can impede the goal of hitting cost targets. The art of stack-up definition is achieving all technical and reliability circuit requirements in a cost efficient manner. The recommended NVIDIA stack-ups achieve these requirements with efficient use of board layers. JETSON TX2 OEM PRODUCT | DESIGN GUIDE | 20170912 84 NVIDIA Jetson TX2 OEM Product Design Guide 18.0 APPENDIX C: TRANSMISSION LINE PRIMER 18.1 Background NVIDIA maintains strict guidelines for high-frequency PCB transmission lines to ensure optimal signal integrity for data transmission. This section provides a brief primer into basic board-level transmission line theory. Characteristics The most important PCB transmission line characteristics are listed in the following bullets: ▪ Trace width/height, PCB height and dielectric constant, and layer stack-up affect the characteristic trace impedance of a transmission line. Z0 =˜ ▪ L 1/2 C Signal rise time is proportional to the transmission line impedance and load capacitance. RiseTime = ˜ ▪ Z0 * RTerm Z0 + RTerm * CLoad Real transmission lines (Figure 45) have non-zero resistances that lead to attenuation and distortion, creating signal integrity issues. Figure 45. Typical Transmission Line Circuit Source ZS Transmission Line Z0 Load ZL Transmission lines are used to “transmit” the source signal to the load or destination with as little signal degradation or reflection as possible. For this reason it is important to design the high-speed signal transmission line to fall within characteristic guidelines based on the signal speed and type. 18.2 Physical Transmission Line Types The two primary transmission line types often used for Jetson TX2 board designs are: ▪ ▪ Microstrip transmission line (Figure 46) Stripline transmission line (Figure 47) The following sections describe each type of transmission. Microstrip Transmission Line Figure 46. Microstrip Transmission Line W H Dielectric ▪ ▪ ▪ ▪ ▪ T Z0 = 87 Er + 1.414 ln 5.98H 0.8W + T Z0: Impedance W: Trace width (inches) T: Trace thickness (inches) Er: Dielectric constant of substrate H: Distance between signal and reference plane Stripline Transmission Line JETSON TX2 OEM PRODUCT | DESIGN GUIDE | 20170912 85 NVIDIA Jetson TX2 OEM Product Design Guide Figure 47. Stripline Transmission Line W T B H ▪ ▪ ▪ ▪ ▪ Z0 = 60 Er 4H ln 0.67πW 0.8 + T W Z0: Impedance W: Trace width (inches) T: Trace thickness (inches) Er: Dielectric constant of substrate H: Distance between signal and reference plane 18.3 Driver Characteristics Driver characteristics are important to the integrity and maximum speed of the signal. The following points identify key driver equations and concepts used to improve signal integrity and transmission speed. ▪ The driver (source) has resistive output impedance ZS, which causes only a fraction of the signal voltage to propagate down the transmission line to the receiver (load). • Transfer function at source: T1 = ▪ Z0 ZS+ Z0 • Driver strength is inversely proportional to the source impedance, Z S. ZS also acts as the source termination, which helps dampen reflection. Source reflection coefficient: R1 = (ZS– Z0) (ZS+ Z0) 18.4 Receiver Characteristics Receiver characteristics are important to the integrity and detectability of the signal. The following points identify key receiver concepts and equations for optimum signal integrity at the final destination. ▪ ▪ The receiver acts as a capacitive load and often has a high load impedance, Z L. Unterminated transmission lines cause overshoot and reflection at the receiver, which can cause data corruption. Output transfer function at load: T2 = - ▪ 2 * ZL ZL + Z0 Load reflection coefficient: (Z – Z ) R2 = L 0 (ZL + Z0) Load impedance can be lowered with a termination resistor (R Term) placed at the end of the transmission line. Reflection is minimized when ZL matches Z0 18.5 Transmission Lines & Reference Planes Defining an appropriate reference plane is vital to transmission line performance due to crosstalk and EMI issues. The following points explore appropriate reference plane identification and characteristics for optimal signal integrity: ▪ Transmission line return current (Figure 48) High-speed return current follows the path of least inductance. The lowest inductance path for a transmission line is right underneath the transmission line; i(D) is proportional to: JETSON TX2 OEM PRODUCT | DESIGN GUIDE | 20170912 86 NVIDIA Jetson TX2 OEM Product Design Guide Figure 48. Transmission Line Height ▪ Transmission line return current: High-speed return current follows the path of least inductance. The lowest inductance path for a transmission line is the portion of the line closest to the dielectric surface; i(D) is proportional to 1 D (1 + ▪ 2 H ) Crosstalk on solid reference plane (Figure 49): Crosstalk is caused by the mutual inductance of two parallel traces. Crosstalk at the second trace is proportional to 1 (1 + - D H 2 ) The signals need to be properly spaced to minimize crosstalk. Figure 49. Crosstalk on Reference Plane ▪ ▪ Reference plane selection Solid ground is preferred as reference plane. Solid power can be used as reference plane with decoupling capacitors near driver and receiver. Reference plane cuts and layer changes need to be avoided. Power plane cut example (Figure 50) Power plane cuts will cause EMI issues. Power plane cuts also induce crosstalk to adjacent signals. Figure 50. Example of Power Plane Cuts ▪ When cut is unavoidable: • Place decoupling capacitors near transition. • Place transition near source or receiver when decoupling capacitors are abundant (Figure 51). JETSON TX2 OEM PRODUCT | DESIGN GUIDE | 20170912 87 NVIDIA Jetson TX2 OEM Product Design Guide Figure 51. Another Example of Power Plane Cuts ▪ When signal changes plane: Try not to change the reference plane, if possible. When a reference plane switches to different power rail, a stitching capacitor is required (Figure 52). Figure 52. Switching Reference Planes - When the same ground/power reference plane changes to a different layer, a stitching via is required (Figure 53). Figure 53. Reference Plane Switch Using VIA JETSON TX2 OEM PRODUCT | DESIGN GUIDE | 20170912 88 NVIDIA Jetson TX2 OEM Product Design Guide 19.0 APPENDIX D: DESIGN GUIDELINE GLOSSARY The Design Guidelines include various terms. The descriptions in the table below are intended to show what these terms mean and how they should be applied to a design. Table 89 Layout Guideline Tutorial Trace Delays Max Breakout Delay Routing on Component layer: Maximum Trace Delay from module connector pin to point beyond pin array where normal trace spacing/impedance can be met. Routing passes to layer other than Component layer: Beyond this, normal trace spacing/impedance must be met. Max Total Trace Delay Trace from module connector pin to Device pin. This must include routing on the main PCB & any other Flex or secondary PCB. Delay is from Module connector to the final connector/device. Intra/Inter Pair Skews Intra Pair Skew (within pair) Difference in delay between two traces in differential pair: Shorter routes may require indirect path to equalize delays Inter Pair Skew (pair to pair) Difference between two (or possibly more) differential pairs Impedance/Spacing Microstrip vs Stripline Microstrip: Traces next to single ref. plane. Stripline: Traces between two ref planes Trace Impedance Impedance of trace determined by width & height of trace, distance from ref. plane & dielectric constant of PCB material. For differential traces, space between pair of traces is also a factor Board trace spacing / Spacing to other nets Minimum distance between two traces. Usually specified in terms of dielectric height which is distance from trace to reference layers. Pair to pair spacing Spacing between differential traces Breakout spacing Possible exception to board trace spacing where different spacing rules are allowed under module connector pin in order to escape from the pin array. Outside device boundary, normal spacing rules apply Reference Return Ground Reference Return Via & Via proximity (signal to reference) Signals changing layers & reference GND planes need similar return current path Accomplished by adding via, tying both GND layers together Via proximity (sig to ref) is distance between signal & reference return vias GND reference via for Differential Pair Where a differential pair changes GND reference layers, return via should be placed close to & between signal vias (example to right) Signal to return via ratio Number of Ground Return vias per Signal vias. For critical IFs, ratio is usually 1:1. For less critical IFs, several trace vias can share fewer return vias (i.e. 3:2 – 3 trace vias & 2 return vias). Slots in Ground Reference Layer When traces cross slots in adjacent power or ground plane Return current has longer path around slot Longer slots result in larger loop areas Avoid slots in GND planes or do not route across them Routing over Split Power Layer Reference Layers When traces cross different power areas on power plane - - Return current must find longer path - usually a distant bypass cap - Placing one cap across two PWR areas near where traces cross area boundaries provides high-frequency path for return current If possible, route traces w/solid plane (GND or PWR) or keep routes across single area If traces must cross two or more power areas, use stitching capacitors Cap value typically 0.1uF & should ideally be within 0.1" of crossing JETSON TX2 OEM PRODUCT | DESIGN GUIDE | 20170912 89 NVIDIA Jetson TX2 OEM Product Design Guide 20.0 APPENDIX E: JETSON TX2 PIN DESCRIPTIONS Table 90. Jetson TX2 Connector (8x50) Pin Descriptions Tegra Signal Usage/Description Usage on the Carrier Board Main power – Supplies PMIC & external supplies Main DC input Pin # Jetson TX2 Pin Name A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 VDD_IN VDD_IN GND GND RSVD I2C_PM_CLK CHARGING# GPIO14_AP_WAKE_MDM GPIO15_AP2MDM_READY GPIO16_MDM_WAKE_AP − − − GEN8_I2C_SCL (PMIC GPIO5) UFS0_RST UFS0_REF_CLK GPIO_MDM2 A11 JTAG_GP1 NVJTAG_SEL A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 JTAG_TMS JTAG_TDO JTAG_RTCK UART2_CTS# UART2_RTS# USB0_EN_OC# USB1_EN_OC# RSVD I2C_GP1_DAT I2C_GP1_CLK GPIO_EXP1_INT GPIO_EXP0_INT LCD1_BKLT_PWM LCD_TE GSYNC_HSYNC GSYNC_VSYNC GND SDIO_RST# RSVD RSVD RSVD DP1_HPD DP1_AUX_CH– JTAG_TMS JTAG_TD0 − UART2_CTS UART2_RTS USB_VBUS_EN0 USB_VBUS_EN1 − GEN1_I2C_SDA GEN1_I2C_SCL GPIO_MDM7 GPIO_MDM1 GPIO_DIS5 GPIO_DIS1 GPIO_DIS4 GPIO_DIS2 − GPIO_WAN3 − − − DP_AUX_CH1_HPD DP_AUX_CH1_N GND GND Not used PM I2C Clock Charger Interrupt AP (Tegra) Wake Modem or GPIO AP (Tegra) to Modem Ready or GPIO Modem Wake AP (Tegra) or GPIO JTAG General Purpose 1. Pulled low on module for normal operation & pulled high by test device for Boundary Scan test mode. JTAG Test Mode Select JTAG Test Data Out JTAG Return Clock UART 2 Clear to Send UART 2 Request to Send USB VBUS Enable/Overcurrent 0 USB VBUS Enable/Overcurrent 1 Not used General I2C 1 Data General I2C 1 Clock GPIO Expander 1 Interrupt or GPIO GPIO expander 0 Interrupt or GPIO Display Backlight PWM 1 Display Tearing Effect GSYNC Horizontal Sync GSYNC Vertical Sync GND Secondary WLAN Enable Not used Not used Not used Display Port 1 Hot Plug Detect Display Port 1 Aux– or HDMI DDC SDA A35 DP1_AUX_CH+ DP_AUX_CH1_P Display Port 1 Aux+ or HDMI DDC SCL A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 USB0_OTG_ID GND USB1_D+ USB1_D– GND PEX2_REFCLK+ PEX2_REFCLK– GND PEX0_REFCLK+ PEX0_REFCLK– (PMIC GPIO0) − USB1_DP USB1_DN − PEX_CLK2P PEX_CLK2N − PEX_CLK1P PEX_CLK1N A46 RESET_OUT# SYS_RESET_N USB 0 ID / VBUS EN GND USB 2.0, Port 1 Data+ USB 2.0, Port 1 Data– GND PCIe 2 Reference Clock+ (PCIe IF #1) PCIe 2 Reference Clock– (PCIe IF #1) GND PCIe 0 Reference Clock+ (PCIe IF #0) PCIe 0 Reference Clock – (PCIe IF #0) Reset Out. Reset from PMIC (through diodes) to Tegra & eMMC reset pins. Driven from carrier board to force reset of Tegra & eMMC (not PMIC). An external 100kΩ pull-up to 1.8V near − GND GND − I2C (General) System M.2 Key E JTAG JTAG Header & Debug Connector M.2 Key E USB 2.0 Micro AB USB 3.0 Type A − I2C (General) GPIO Expander Display Connector GND M.2 Key E − − − Direction Pin Type Input 5.5V-19.6V − − − Bidir Input Output Output Input GND GND − Open Drain – 1.8V CMOS – 1.8V CMOS – 1.8V CMOS – 1.8V CMOS – 1.8V Input CMOS – 1.8V Input Output Input Input Output Bidir Bidir − Bidir Bidir Input Input Output Input Output Output − Output − − − Input Bidir CMOS – 1.8V CMOS – 1.8V CMOS – 1.8V CMOS – 1.8V CMOS – 1.8V Open Drain – 3.3V Open Drain – 3.3V − Open Drain – 3.3V Open Drain – 3.3V CMOS – 1.8V CMOS – 1.8V CMOS – 1.8V CMOS – 1.8V CMOS – 1.8V CMOS – 1.8V GND CMOS – 1.8V − − − CMOS – 1.8V AC-Coupled on Carrier Board (eDP/DP) or OpenDrain, 1.8V (3.3V tolerant DDC/I2C) Analog GND HDMI Type A Conn. Bidir USB 2.0 Micro AB GND USB 3.0 Type A GND Unassigned GND PCIe x4 Connector System Input − Bidir Bidir − Output Output − Output Output Bidir USB PHY GND PCIe PHY GND PCIe PHY CMOS – 1.8V Tegra (module pin side) & external 10kΩ pull-up to 1.8V on the other side of a diode (PMIC side). JETSON TX2 OEM PRODUCT | DESIGN GUIDE | 20170912 90 NVIDIA Jetson TX2 OEM Product Design Guide Pin # Jetson TX2 Pin Name Tegra Signal A47 RESET_IN# A48 CARRIER_PWR_ON − A49 CHARGER_PRSNT# (PMIC ACOK) A50 VDD_RTC (PMIC BBATT) B1 B2 B3 B4 B5 B6 VDD_IN VDD_IN GND GND RSVD I2C_PM_DAT − − − GEN8_I2C_SDA B7 CARRIER_STBY# SOC_PWR_REQ B8 VIN_PWR_BAD# B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 GPIO17_MDM2AP_READY GPIO18_MDM_COLDBOOT JTAG_TCK JTAG_TDI JTAG_GP0 GND UART2_RX UART2_TX FAN_TACH RSVD GPIO11_AP_WAKE_BT GPIO10_WIFI_WAKE_AP GPIO12_BT_EN GPIO13_BT_WAKE_AP GPIO7_TOUCH_RST TOUCH_CLK GPIO6_TOUCH_INT LCD_VDD_EN LCD0_BKLT_PWM LCD_BKLT_EN RSVD RSVD GND (PMIC NRST_IO) − − GPIO_PQ7 GPIO_PQ6 JTAG_TCK JTAG_TDI JTAG_TRST_N − UART2_RX UART2_TX UART5_TX − GPIO_PQ5 GPIO_WAN4 MCU_PWR_REQ GPIO_WAN2 SAFE_STATE TOUCH_CLK CAN_GPIO7 GPIO_EDP0 GPIO_DIS0 GPIO_DIS3 − − − JETSON TX2 OEM PRODUCT | DESIGN GUIDE | 20170912 Usage/Description Usage on the Carrier Board Direction Pin Type Bidir Open Drain, 1.8V Output Open-Collector – 3.3V Input MBATT level – 5.0V (see note 3) Bidir 1.65V-5.5V Main DC input Input 5.5V-19.6V GND GND − − − Bidir GND GND − Open Drain – 1.8V Output CMOS – 1.8V Input CMOS – 5.0V Input Input Input Input Input − Input Output Input − Output Input Output Input Output Output Input Output Output Output − − − CMOS – 1.8V CMOS – 1.8V CMOS – 1.8V CMOS – 1.8V CMOS – 1.8V GND CMOS – 1.8V CMOS – 1.8V CMOS – 1.8V − CMOS – 1.8V CMOS – 1.8V CMOS – 1.8V CMOS – 1.8V CMOS – 1.8V CMOS – 1.8V CMOS – 1.8V CMOS – 1.8V CMOS – 1.8V CMOS – 1.8V − − GND Reset In. System Reset driven from PMIC to carrier board for devices requiring full system reset. Also driven from carrier board to initiate full system reset (i.e. RESET button). A pull-up is present on module. Carrier Power On. Used as part of the power up sequence. The module asserts this signal when it is safe for the carrier board to power up. A 10kΩ pull-up to VDD_3V3_SYS is present on the module. Charger Present. Connected on module to PMIC ACOK through FET & 4.7kΩ resistor. PMIC ACOK has 100kΩ pull-up internally to MBATT (VDD_5V0_SYS). Can optionally be used to support autopower-on where the module platform will power-on when the main power source is connected instead of waiting for a power button press. Real-Time-Clock. Optionally used to provide back-up power for RTC. Connects to Lithium Cell or super Battery Back-up using capacitor on Carrier Board. PMIC is Super-capacitor supply when charging cap or coin cell. Super cap or coin cell is source when system is disconnected from power. Main power – Supplies PMIC & external supplies GND GND Not used PM I2C Data Carrier Board Standby: The module drives this signal low when it is in the standby power state. VDD_IN Power Bad. Carrier board indication to the module that the VDD_IN power is not valid. Carrier board should de-assert this (drive high) only when VDD_IN has reached its required voltage level and is stable. This prevents Tegra from powering up until the VDD_IN power is stable. Modem to AP (Tegra) Ready or GPIO Modem Coldboot or GPIO JTAG Test Clock JTAG Test Data In JTAG General Purpose 0 (Test Reset) GND UART 2 Receive UART 2 Transmit Fan Tachometer Not used AP (Tegra) Wake Bluetooth or GPIO WLAN 2 Wake AP (Tegra) or GPIO BT 2 Enable or GPIO BT 2 Wake AP (Tegra) or GPIO Touch Reset or GPIO Touch Clock Touch Interrupt or GPIO Display VDD Enable Display Backlight PWM 0 Display Backlight Enable Not used Not used GND − I2C (General) System M.2 Key E JTAG Header & Debug Connector GND M.2 Key E Fan − Display Connector M.2 Key E Display Connector − − GND 91 NVIDIA Jetson TX2 OEM Product Design Guide Pin # Jetson TX2 Pin Name Tegra Signal Usage/Description B32 B33 B34 RSVD HDMI_CEC DP0_AUX_CH– − HDMI_CEC DP_AUX_CH0_N Not used HDMI CEC Display Port 0 Aux– or HDMI DDC SDA B35 DP0_AUX_CH+ DP_AUX_CH0_P Display Port 0 Aux+ or HDMI DDC SCL B36 B37 B38 B39 B40 B41 B42 B43 B44 B45 B46 B47 B48 B49 DP0_HPD USB0_VBUS_DET GND USB0_D+ USB0_D– GND USB2_D+ USB2_D– GND PEX1_REFCLK+ PEX1_REFCLK– GND RSVD RSVD DP_AUX_CH0_HPD UART5_CTS − USB0_DP USB0_DN − USB2_DP USB2_DN − PEX_CLK3P PEX_CLK3N − − − B50 POWER_BTN# POWER_ON / (PMIC EN0) Display Port 0 Hot Plug Detect USB 0 VBUS Detect GND USB 2.0 Port 0 Data+ USB 2.0 Port 0 Data– GND USB 2.0, Port 2 Data+ USB 2.0, Port 2 Data– GND PCIe 1 Reference Clock+ (PCIe IF #2) PCIe 1 Reference Clock– (PCIe IF #2) GND Not used Not used Power Button. Used to initiate a system power-on. Connected to PMIC EN0 which has internal 10KΩ Pull-up to VDD_5V0_SYS. Also connected to Tegra POWER_ON pin through Diode with 100kΩ pull-up to VDD_1V8_AP near Tegra. C1 C2 C3 C4 C5 C6 C7 VDD_IN VDD_IN GND GND RSVD I2C_CAM_CLK BATLOW# − − − CAM_I2C_SCL (PMIC_GPIO6) C8 BATT_OC BATT_OC C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 C33 C34 C35 C36 WDT_TIME_OUT# I2C_GP2_DAT I2C_GP2_CLK I2C_GP3_CLK I2C_GP3_DAT I2S1_SDIN I2S1_CLK FAN_PWM CAN1_STBY CAN1_TX CAN1_ERR CAN_WAKE GND CSI5_D0– CSI5_D0+ GND CSI3_D0– CSI3_D0+ GND CSI1_D0– CSI1_D0+ GND DSI3_D0+ DSI3_D0– GND DSI1_D0+ DSI1_D0– GND GPIO_SEN7 GEN7_I2C_SDA GEN7_I2C_SCL GEN9_I2C_SCL GEN9_I2C_SDA DAP2_DIN DAP2_SCLK GPIO_SEN6 CAN_GPIO6 CAN1_DOUT CAN_GPIO3 CAN_GPIO4 − CSI_F_D0_N CSI_F_D0_P − CSI_D_D0_N CSI_D_D0_P − CSI_B_D0_N CSI_B_D0_P − DSI_D_D0_P DSI_D_D0_N − DSI_B_D0_P DSI_B_D0_N − − − JETSON TX2 OEM PRODUCT | DESIGN GUIDE | 20170912 Main power – Supplies PMIC & external supplies GND GND Not used Camera I2C Clock Battery Low (PMIC GPIO) Battery Over-current (& Thermal) warning Watchdog Timeout General I2C 2 Data General I2C 2 Clock General I2C 3 Clock General I2C 3 Data I2S Audio Port 1 Data In I2S Audio Port 1 Clock Fan PWM CAN 1 Standby CAN 1 Transmit CAN 1 Error CAN Wake GND Camera, CSI 5 Data 0– Camera, CSI 5 Data 0+ GND Camera, CSI 3 Data 0– Camera, CSI 3 Data 0+ GND Camera, CSI 1 Data 0– Camera, CSI 1 Data 0+ GND Display, DSI 3 Data 0+ Display, DSI 3 Data 0– GND Display, DSI 1 Data 0+ Display, DSI 1 Data 0– GND Usage on the Carrier Board − HDMI Type A Conn. Display Connector USB 2.0 Micro AB GND USB 2.0 Micro AB GND M.2 Key E GND M.2 Key E GND − − Direction − Bidir Bidir Bidir Input Input − Bidir Bidir − Bidir Bidir − Output Output − − − Pin Type − Open Drain, 3.3V AC-Coupled on Carrier Board (eDP/DP) or OpenDrain, 1.8V (3.3V tolerant DDC/I2C) CMOS – 1.8V USB VBUS, 5V GND USB PHY GND USB PHY GND PCIe PHY GND − − System Input CMOS – 5.0V (see note 3) Main DC input Input 5.5V-19.6V GND GND − − − Bidir Input GND GND − Open Drain – 1.8V CMOS – 1.8V Bidir CMOS – 1.8V Input Bidir Bidir Bidir Bidir Input Bidir Output Output Output Input Input − Input Input − Input Input − Input Input − Output Output − Output Output − CMOS – 1.8V Open Drain – 1.8V Open Drain – 1.8V Open Drain – 1.8V Open Drain – 1.8V CMOS – 1.8V CMOS – 1.8V CMOS – 1.8V CMOS 3.3V CMOS 3.3V CMOS 3.3V CMOS 3.3V GND − Camera Connector System I2C (General) GPIO Expansion Header Fan GPIO Expansion Header GND Camera Connector GND Camera Connector GND Camera Connector GND Display Connector GND Display Connector GND MIPI D-PHY GND MIPI D-PHY GND MIPI D-PHY GND MIPI D-PHY GND MIPI D-PHY GND 92 NVIDIA Jetson TX2 OEM Product Design Guide Pin # Jetson TX2 Pin Name Tegra Signal Usage/Description C37 C38 C39 DP1_TX1– DP1_TX1+ GND HDMI_DP1_TXDN1 HDMI_DP1_TXDP1 − C40 PEX2_TX+ PEX_TX3P DisplayPort 1 Lane 1– or HDMI Lane 1– DisplayPort 1 Lane 1+ or HDMI Lane 1+ GND PCIe 2 Transmit+ (PCIe IF #0 Lane 2 or PCIe IF #1 Lane 0) PCIe 2 Transmit– (PCIe IF #0 Lane 2 or PCIe IF #1 Lane 0) GND USB SS 0 Transmit+ (USB 3.0 Port #0 muxed w/PCIe #2 Lane 0) USB SS 0 Transmit– (USB 3.0 Port #0 muxed w/PCIe #2 Lane 0) GND PCIE 2 Clock Request (PCIe IF #1) PCIE 1 Clock Request (mux option - PCIe IF #2) PCIE 0 Clock Request (PCIe IF #0) PCIe 0 Reset (PCIe IF #0) Not used Not used Not used Not used Not used UART 7 Receive Camera I2C Data Camera Flash Enable or GPIO UART 7 Transmit UART 1 Transmit UART 1 Receive Not used Not used I2S Audio Port 1 Left/Right Clock I2S Audio Port 1 Data Out General I2C 0 Data Digital Mic Input Data CAN 1 Receive CAN 0 Receive CAN 0 Transmit GND Camera, CSI 5 Clock– Camera, CSI 5 Clock+ GND Camera, CSI 3 Clock– Camera, CSI 3 Clock+ GND Camera, CSI 1 Clock– Camera, CSI 1 Clock+ GND Display DSI 3 Clock+ Display DSI 3 Clock– GND Display DSI 1 Clock+ Display DSI 1 Clock– GND DisplayPort 1 Lane 2– or HDMI Lane 0– DisplayPort 1 Lane 2+ or HDMI Lane 0+ GND PCIe RFU Transmit+ (PCIe IF #0 Lane 3 or USB 3.0 Port #1) PCIe RFU Transmit – (PCIe IF #0 Lane 3 or USB 3.0 Port #1) GND C41 PEX2_TX– C42 GND C43 USB_SS0_TX+ PEX_TX3N − PEX_TX0P C44 USB_SS0_TX– PEX_TX0N C45 C46 GND PEX2_CLKREQ# − PEX_L1_CLKREQ_N C47 PEX1_CLKREQ# PEX_L2_CLKREQ_N C48 C49 C50 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 D32 D33 D34 D35 D36 D37 D38 PEX0_CLKREQ# PEX0_RST# RSVD RSVD RSVD RSVD RSVD UART7_RX I2C_CAM_DAT GPIO5_CAM_FLASH_EN UART7_TX UART1_TX UART1_RX RSVD RSVD I2S1_LRCLK I2S1_SDOUT I2C_GP0_DAT AO_DMIC_IN_DAT CAN1_RX CAN0_RX CAN0_TX GND CSI5_CLK– CSI5_CLK+ GND CSI3_CLK– CSI3_CLK+ GND CSI1_CLK– CSI1_CLK+ GND DSI3_CLK+ DSI3_CLK– GND DSI1_CLK+ DSI1_CLK– GND DP1_TX2– DP1_TX2+ GND PEX_L0_CLKREQ_N PEX_L0_RST_N − − − − − UART7_RX CAM_I2C_SDA UART5_RTS_N UART7_TX UART3_TX UART3_RX − − DAP2_FS DAP2_DOUT GPIO_SEN9 CAN_GPIO0 CAN1_DIN CAN0_DIN CAN0_DOUT − CSI_F_CLK_N CSI_F_CLK_P − CSI_D_CLK_N CSI_D_CLK_P − CSI_B_CLK_N CSI_B_CLK_P − DSI_D_CLK_P DSI_D_CLK_N − DSI_B_CLK_P DSI_B_CLK_N − HDMI_DP1_TXDN0 HDMI_DP1_TXDP0 − D39 PEX_RFU_TX+ PEX_TX1P D40 PEX_RFU_TX– D41 GND PEX_TX1N − JETSON TX2 OEM PRODUCT | DESIGN GUIDE | 20170912 Usage on the Carrier Board HDMI Type A Conn. GND Direction Pin Type Output Output − AC-Coupled on carrier board Output PCIe x4 Connector Output GND − Output USB 3.0 Type A Output GND PCIe PHY, AC-Coupled on carrier board GND USB SS PHY, AC-Coupled on carrier board GND Unassigned − Bidir GND M.2 Key E Bidir Open Drain 3.3V, Pull-up on the module PCIe x4 Connector − − − − − Not Assigned Camera Connector Not Assigned Serial Port Header − − GPIO Expansion Header I2C (General) GPIO Expansion Header GND Camera Connector GND Camera Connector GND Camera Connector GND Display Connector GND Display Connector GND HDMI Type A Conn. GND Bidir Output − − − − − Input Bidir Output Output Output Input − − Bidir Bidir Bidir Input Input Input Output − Input Input − Input Input − Input Input − Output Output − Output Output − Output Output − Output PCIe x4 Connector Output GND − − − − − − CMOS – 1.8V Open Drain – 1.8V CMOS – 1.8V CMOS – 1.8V CMOS – 1.8V CMOS – 1.8V − − CMOS – 1.8V CMOS – 1.8V Open Drain – 1.8V CMOS – 1.8V CMOS 3.3V CMOS 3.3V CMOS 3.3V GND MIPI D-PHY GND MIPI D-PHY GND MIPI D-PHY GND MIPI D-PHY GND MIPI D-PHY GND AC-Coupled on carrier board GND PCIe PHY, AC-Coupled on carrier board GND 93 NVIDIA Jetson TX2 OEM Product Design Guide Pin # Jetson TX2 Pin Name Tegra Signal Usage/Description D43 USB_SS1_TX– PEX_TX2N D44 D45 D46 GND SATA_TX+ SATA_TX– PEX_TX5P PEX_TX5N D47 SATA_DEV_SLP PEX_L2_CLKREQ_N D48 D49 D50 E1 PEX_WAKE# PEX2_RST# RSVD FORCE_RECOV# PEX_WAKE_N PEX_L1_RST_N − GPIO_SW1 E2 SLEEP# GPIO_SW2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 SPI0_CLK SPI0_MISO I2S3_SDIN I2S3_CLK CAM2_MCLK CAM_VSYNC UART1_RTS# UART1_CTS# RSVD RSVD RSVD SPI1_CS0# I2C_GP0_CLK AO_DMIC_IN_CLK RSVD GPIO_SEN1 GPIO_SEN2 DAP4_DIN DAP4_SCLK GPIO_CAM2 QSPI_IO1 UART3_RTS UART3_CTS − − − GPIO_CAM7 GPIO_SEN8 CAN_GPIO1 − USB SS 1 Transmit+ (USB 3.0 Port #2 or PCIe IF #0 Lane 1) USB SS 1 Transmit– (USB 3.0 Port #2 or PCIe #0 Lane 1) GND SATA Transmit+ SATA Transmit– SATA Device Sleep or PEX1_CLKREQ# (PCIe IF #2) depending on Mux setting PCIe Wake PCIe 2 Reset (PCIe IF #1) Not used Force Recovery strap pin Sleep Request to the module from the carrier board. An internal Tegra pull-up is present on the signal. SPI 0 Clock SPI 0 Master In / Slave Out I2S Audio Port 3 Data In I2S Audio Port 3 Clock Camera 2 Master Clock Camera Vertical Sync UART 1 Request to Send UART 1 Clear to Send Not used Not used Not used SPI 1 Chip Select 0 General I2C 0 Clock Digital Mic Input Clock Not used E18 CAN0_ERR CAN_GPIO5 CAN 0 Error E19 E20 E21 E22 E23 E24 E25 E26 E27 E28 E29 E30 E31 E32 E33 E34 E35 E36 E37 E38 E39 E40 GND CSI5_D1– CSI5_D1+ GND CSI3_D1– CSI3_D1+ GND CSI1_D1– CSI1_D1+ GND DSI3_D1+ DSI3_D1– GND DSI1_D1+ DSI1_D1– GND DP1_TX3– DP1_TX3+ GND DP1_TX0– DP1_TX0+ GND − CSI_F_D1_N CSI_F_D1_P − CSI_D_D1_N CSI_D_D1_P − CSI_B_D1_N CSI_B_D1_P − DSI_D_D1_P DSI_D_D1_N − DSI_B_D1_P DSI_B_D1_N − HDMI_DP1_TXDN3 HDMI_DP1_TXDP3 − HDMI_DP1_TXDN2 HDMI_DP1_TXDP2 − E41 PEX1_TX+ PEX_TX0P E42 PEX1_TX– PEX_TX0N E43 E44 E45 E46 GND PEX0_TX+ PEX0_TX– GND GND Camera, CSI 5 Data 1– Camera, CSI 5 Data 1+ GND Camera, CSI 3 Data 1– Camera, CSI 3 Data 1+ GND Camera, CSI 1 Data 1– Camera, CSI 1 Data 1+ GND Display, DSI 3 Data 1+ Display, DSI 3 Data 1– GND Display, DSI 1 Data 1+ Display, DSI 1 Data 1– GND DisplayPort 1 Lane 3– or HDMI Clk Lane– DisplayPort 1 Lane 3+ or HDMI Clk Lane+ GND DisplayPort 1 Lane 0– or HDMI Lane 2– DisplayPort 1 Lane 0+ or HDMI Lane 2+ GND PCIe 1 Transmit+ (PCIe #2 Lane 0 muxed w/USB 3.0 Port #0) PCIe 1 Transmit– (PCIe #2 Lane 0 muxed w/USB 3.0 Port #0) GND PCIe 0 Transmit+ (PCIe IF #0 Lane 0) PCIe 0 Transmit– (PCIe IF #0 Lane 0) GND D42 USB_SS1_TX+ PEX_TX2P − − PEX_TX4P PEX_TX4N − JETSON TX2 OEM PRODUCT | DESIGN GUIDE | 20170912 Usage on the Carrier Board Direction Output PCIe x4 Connector Output GND SATA Connector − Output Output Input Pin Type USB SS PHY, AC-Coupled on carrier board GND SATA PHY, AC-Coupled on carrier board Open Drain 3.3V, Pull-up on the module PCIe x4 conn & M.2 Unassigned − System Input Output − Input Open Drain 3.3V, Pull-up on the module Sleep (VOL DOWN) button Input CMOS – 1.8V (see note 3) Bidir Bidir Input Bidir Output Output Output Input − − − Bidir Bidir Output − CMOS – 1.8V CMOS – 1.8V CMOS – 1.8V CMOS – 1.8V CMOS – 1.8V CMOS – 1.8V CMOS – 1.8V CMOS – 1.8V − − − CMOS – 1.8V Open Drain – 1.8V CMOS – 1.8V − Input CMOS 3.3V − Input Input − Input Input − Input Input − Output Output − Output Output − Output Output − Output Output − GND Display Connector Camera Connector Serial Port Header − − − Expansion Header I2C (General) Expansion Header − GPIO Expansion Header GND Camera Connector GND Camera Connector GND Camera Connector GND Display Connector GND Display Connector GND HDMI Type A Conn. GND HDMI Type A Conn. GND USB 3.0 Type A (Default) or M.2 Key E GND PCIe x4 Connector GND Output Output − Output Output − − CMOS – 1.8V MIPI D-PHY GND MIPI D-PHY GND MIPI D-PHY GND MIPI D-PHY GND MIPI D-PHY GND AC-Coupled on carrier board GND AC-Coupled on carrier board GND PCIe PHY, AC-Coupled on carrier board GND PCIe PHY, AC-Coupled on carrier board GND 94 NVIDIA Jetson TX2 OEM Product Design Guide Pin # Jetson TX2 Pin Name E47 E48 E49 GBE_LINK_ACT# GBE_MDI0+ GBE_MDI0– E50 PEX1_RST# F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 F32 F33 F34 F35 F36 F37 F38 F39 Tegra Signal Pin Type CMOS – 3.3V tolerant LAN Output Bidir Bidir PCIe 1 Reset (PCIe IF #2) M.2 Key E Output Audio Codec Master Clock Audio Codec Reset or GPIO SPI 0 Chip Select 0 SPI 0 Master Out / Slave In I2S Audio Port 3 Left/Right Clock I2S Audio Port 3 Data Out Camera 1 Powerdown or GPIO Camera 1 Reference Clock Camera 0 Reference Clock GND Not used Not used SPI 1 Master Out / Slave In SPI 1 Master In / Slave Out GND SPI 2 Chip Select 1 SD Card Card Detect SD Card (or SDIO) Data 3 SD Card (or SDIO) Data 2 SD Card Write Protect GND Camera, CSI 4 Data 0– Camera, CSI 4 Data 0+ GND Camera, CSI 2 Data 0– Camera, CSI 2 Data 0+ GND Camera, CSI 0 Data 0– Camera, CSI 0 Data 0+ GND Display, DSI 2 Data 0+ Display, DSI 2 Data 0– GND Display, DSI 0 Data 0+ Display, DSI 0 Data 0– GND DisplayPort 0 Lane 1– or HDMI Lane 1– DisplayPort 0 Lane 1+or HDMI Lane 1+ GND PCIe 2 Receive+ (PCIe IF #0 Lane 2 or PCIe IF #1 Lane 0) PCIe 2 Receive– (PCIe IF #0 Lane 2 or PCIe IF #1 Lane 0) GND USB SS 0 Receive+ (USB 3.0 Port #0 muxed w/PCIe #2 Lane 0) USB SS 0 Receive– (USB 3.0 Port #0 muxed w/PCIe #2 Lane 0) GND GbE RJ45 connector Link 1000 (LED2) GbE Transformer Data 1+ GbE Transformer Data 1– GND GbE RJ45 connector Link 100 (LED1) I2S Audio Port 0 Data In I2S Audio Port 0 Clock GND Expansion Header Output Output Bidir Bidir Bidir Bidir Output Output Output − − − Bidir Bidir − Bidir Input Bidir Bidir Input − Input Input − Input Input − Input Input − Output Output − Output Output − Output Output − PEX_L2_RST_N AUDIO_MCLK GPIO19_AUD_RST SPI0_CS0# SPI0_MOSI I2S3_LRCLK I2S3_SDOUT GPIO1_CAM1_PWR# CAM1_MCLK CAM0_MCLK GND RSVD RSVD SPI1_MOSI SPI1_MISO GND SPI2_CS1# SDCARD_CD# SDCARD_D3 SDCARD_D2 SDCARD_WP GND CSI4_D0– CSI4_D0+ GND CSI2_D0– CSI2_D0+ GND CSI0_D0– CSI0_D0+ GND DSI2_D0+ DSI2_D0– GND DSI0_D0+ DSI0_D0– GND DP0_TX1– DP0_TX1+ GND AUD_MCLK GPIO_AUD1 GPIO_SEN4 GPIO_SEN3 DAP4_FS DAP4_DOUT GPIO_CAM3 EXTPERIPH2_CLK EXTPERIPH1_CLK − − − GPIO_CAM6 GPIO_CAM5 − GPIO_MDM4 GPIO_EDP2 SDMMC1_DAT3 SDMMC1_DAT2 GPIO_EDP1 − CSI_E_D0_N CSI_E_D0_P − CSI_C_D0_N CSI_C_D0_P − CSI_A_D0_N CSI_A_D0_P − DSI_C_D0_P DSI_C_D0_N − DSI_A_D0_P DSI_A_D0_N − HDMI_DP0_TXDN1 HDMI_DP0_TXDP1 − F40 PEX2_RX+ PEX_RX3P F41 PEX2_RX– PEX_RX3N F42 GND F43 USB_SS0_RX+ USB_SS0_RX– F45 F46 F47 F48 F49 F50 G1 G2 G3 GND GBE_LINK1000# GBE_MDI1+ GBE_MDI1– GND GBE_LINK100# I2S0_SDIN I2S0_CLK GND − PEX_RX0P PEX_RX0N − − − − − − DAP1_DIN DAP1_SCLK − JETSON TX2 OEM PRODUCT | DESIGN GUIDE | 20170912 Usage on the Carrier Board Direction GbE RJ45 connector Link ACT (LED0) GbE Transformer Data 0+ GbE Transformer Data 0– F44 − − − Usage/Description Display Connector Camera Connector GND − − Expansion Header GND Display/Camera Conns. SD Card GND Camera Connector GND Camera Connector GND Camera Connector GND Display Connector GND Display Connector GND Display Connector GND Input PCIe x4 Connector Input GND − Input USB 3.0 Type A Input GND LAN GND LAN Expansion Header GND − Output Bidir Bidir − Output Input Bidir − MDI Open Drain 3.3V, Pull-up on the module CMOS – 1.8V CMOS – 1.8V CMOS – 1.8V CMOS – 1.8V CMOS – 1.8V CMOS – 1.8V CMOS – 1.8V CMOS – 1.8V CMOS – 1.8V GND − − CMOS – 1.8V CMOS – 1.8V GND CMOS – 1.8V CMOS – 1.8V CMOS – 3.3/1.8V CMOS – 3.3/1.8V CMOS – 1.8V GND MIPI D-PHY GND MIPI D-PHY GND MIPI D-PHY GND MIPI D-PHY GND MIPI D-PHY GND AC-Coupled on carrier board GND PCIe PHY, AC-Coupled on carrier board GND USB SS PHY, AC-Coupled (off the module) GND CMOS – 3.3V Tolerant MDI GND CMOS – 3.3V Tolerant CMOS – 1.8V CMOS – 1.8V GND 95 NVIDIA Jetson TX2 OEM Product Design Guide Pin # Jetson TX2 Pin Name Tegra Signal Usage/Description G4 DSPK_OUT_CLK GPIO_AUD3 Digital Speaker Output Clock G5 G6 G7 G8 I2S2_CLK I2S2_SDIN GPIO4_CAM_STROBE GPIO0_CAM0_PWR# I2S Audio Port 2 Clock I2S Audio Port 2 Data In Camera Strobe or GPIO Camera 0 Powerdown or GPIO G9 UART3_CTS# Direction Pin Type Output CMOS – 1.8V Bidir Input Output Output CMOS – 1.8V CMOS – 1.8V CMOS – 1.8V CMOS – 1.8V Input CMOS – 1.8V UART 3 Request to Send Output CMOS – 1.8V UART 0 Request to Send UART 0 Receive SPI 1 Clock Output Input Bidir CMOS – 1.8V CMOS – 1.8V CMOS – 1.8V Input CMOS – 1.8V Bidir Bidir − Output Bidir − Input Input − Input Input − Input Input − Output Output − Output Output − Output Output − CMOS – 1.8V CMOS – 1.8V GND CMOS – 3.3/1.8V CMOS – 3.3/1.8V GND G10 UART3_RTS# G11 G12 G13 UART0_RTS# UART0_RX SPI1_CLK DMIC2_DAT DMIC1_DAT GPIO_SEN5 QSPI_SCK UART4_CTS_N (via mux) UART4_RTS_N (via mux) UART1_RTS UART1_RX GPIO_CAM4 G14 GPIO9_MOTION_INT CAN_GPIO2 Motion Interrupt or GPIO G15 G16 G17 G18 G19 G20 G21 G22 G23 G24 G25 G26 G27 G28 G29 G30 G31 G32 G33 G34 G35 G36 G37 G38 SPI2_MOSI SPI2_CS0# GND SDCARD_CLK SDCARD_CMD GND CSI4_CLK– CSI4_CLK+ GND CSI2_CLK– CSI2_CLK+ GND CSI0_CLK– CSI0_CLK+ GND DSI2_CLK+ DSI2_CLK– GND DSI0_CLK+ DSI0_CLK– GND DP0_TX2– DP0_TX2+ GND GPIO_WAN7 GPIO_WAN8 − SDMMC1_CLK SDMMC1_CMD − CSI_E_CLK_N CSI_E_CLK_P − CSI_C_CLK_N CSI_C_CLK_P − CSI_A_CLK_N CSI_A_CLK_P − DSI_C_CLK_P DSI_C_CLK_N − DSI_A_CLK_P DSI_A_CLK_N − HDMI_DP0_TXDN0 HDMI_DP0_TXDP0 − G39 PEX_RFU_RX+ PEX_RX1P DAP1_FS DAP1_DOUT GPIO_AUD0 SPI 2 Master Out / Slave In SPI 2 Chip Select 0 GND SD Card (or SDIO) Clock SD Card (or SDIO) Command GND Camera, CSI 4 Clock– Camera CSI 4 Clock+ GND Camera, CSI 2 Clock– Camera, CSI 2 Clock+ GND Camera, CSI 0 Clock– Camera, CSI 0 Clock+ GND Display DSI 2 Clock+ Display DSI 2 Clock– GND Display, DSI 0 Clock+ Display, DSI 0 Clock– GND DisplayPort 0 Lane 2– or HDMI Lane 0– DisplayPort 0 Lane 2+ or HDMI Lane 0+ GND PCIe RFU Receive+ (PCIe IF #0 Lane 3 or USB 3.0 Port #1) PCIe RFU Receive– (PCIe IF #0 Lane 3 or USB 3.0 Port #1) GND USB SS 1 Receive+ (USB 3.0 Port #2 or PCIe IF #0 Lane 1) USB SS 1 Receive– (USB 3.0 Port #2 or PCIe #0 Lane 1) GND SATA Receive+ SATA Receive– GND GbE Transformer Data 2+ GbE Transformer Data 2– GND I2S Audio Port 0 Left/Right Clock I2S Audio Port 0 Data Out Audio Codec Interrupt or GPIO PEX_RX1N G41 GND G42 USB_SS1_RX+ PEX_RX2P G43 USB_SS1_RX– PEX_RX2N G44 G45 G46 G47 G48 G49 G50 H1 H2 H3 GND SATA_RX+ SATA_RX– GND GBE_MDI2+ GBE_MDI2– GND I2S0_LRCLK I2S0_SDOUT GPIO20_AUD_INT H4 DSPK_OUT_DAT GPIO_AUD2 Digital Speaker Output Data H5 H6 H7 I2S2_LRCLK I2S2_SDOUT GPIO3_CAM1_RST# DMIC1_CLK DMIC2_CLK QSPI_IO0 I2S Audio Port 2 Left/Right Clock I2S Audio Port 2 Data Out Camera 1 Reset or GPIO − − − − − JETSON TX2 OEM PRODUCT | DESIGN GUIDE | 20170912 Camera Connector Not assigned PEX_RFU_RX– PEX_RX5P PEX_RX5N M.2 Key E UART 3 Clear to Send G40 − Usage on the Carrier Board GPIO Expansion Header Debug Header Expansion Header Camera Conn & Exp. Hdr. Display/Camera Conns. GND SD Card GND Camera Connector GND Camera Connector GND Camera Connector GND Display Connector GND Display Connector GND Display Connector GND Input PCIe x4 Connector Input GND − Input PCIe x4 Connector Input GND SATA Connector GND LAN GND Expansion Header GPIO Expansion Header M.2 Key E Camera Connector − Input Input − Bidir Bidir − Bidir Bidir Input MIPI D-PHY GND MIPI D-PHY GND MIPI D-PHY GND MIPI D-PHY GND MIPI D-PHY GND AC-Coupled on carrier board GND PCIe PHY, AC-Coupled on carrier board GND USB SS PHY, AC-Coupled (off the module) GND SATA PHY, AC-Coupled on carrier board GND MDI GND CMOS – 1.8V CMOS – 1.8V CMOS – 1.8V Output CMOS – 1.8V Bidir Bidir Output CMOS – 1.8V CMOS – 1.8V CMOS – 1.8V 96 NVIDIA Jetson TX2 OEM Product Design Guide Usage on the Carrier Board Pin # Jetson TX2 Pin Name Tegra Signal Usage/Description H8 H9 H10 H11 H12 H13 H14 H15 H16 H17 H18 H19 H20 H21 H22 H23 H24 H25 H26 H27 H28 H29 H30 H31 H32 H33 H34 H35 H36 H37 H38 H39 H40 GPIO2_CAM0_RST# UART3_RX UART3_TX UART0_CTS# UART0_TX GPIO8_ALS_PROX_INT SPI2_CLK SPI2_MISO SDCARD_PWR_EN SDCARD_D1 SDCARD_D0 GND CSI4_D1– CSI4_D1+ GND CSI2_D1– CSI2_D1+ GND CSI0_D1– CSI0_D1+ GND DSI2_D1+ DSI2_D1– GND DSI0_D1+ DSI0_D1– GND DP0_TX3– DP0_TX3+ GND DP0_TX0– DP0_TX0+ GND QSPI_CS_N UART4_RX (via mux) UART4_TX (via mux) UART1_CTS UART1_TX GPIO_PQ4 GPIO_WAN5 GPIO_WAN6 GPIO_EDP3 SDMMC1_DAT1 SDMMC1_DAT0 − CSI_E_D1_N CSI_E_D1_P − CSI_C_D1_N CSI_C_D1_P − CSI_A_D1_N CSI_A_D1_P − DSI_C_D1_P DSI_C_D1_N − DSI_A_D1_P DSI_A_D1_N − HDMI_DP0_TXDN3 HDMI_DP0_TXDP3 − HDMI_DP0_TXDN2 HDMI_DP0_TXDP2 − H41 PEX1_RX+ PEX_RX0P H42 PEX1_RX– PEX_RX0N H43 H44 H45 H46 H47 H48 H49 H50 GND PEX0_RX+ PEX0_RX– GND GBE_MDI3+ GBE_MDI3– GND RSVD Camera 0 Reset or GPIO UART 3 Receive UART 3 Transmit UART 0 Clear to Send UART 0 Transmit Proximity sensor Interrupt or GPIO SPI 2 Clock SPI 2 Master In / Slave Out SD Card power switch Enable SD Card (or SDIO) Data 1 SD Card (or SDIO) Data 0 GND Camera, CSI 4 Data 1– Camera, CSI 4 Data 1+ GND Camera, CSI 2 Data 1– Camera, CSI 2 Data 1+ GND Camera, CSI 0 Data 1– Camera, CSI 0 Data 1+ GND Display, DSI 2 Data 1+ Display, DSI 2 Data 1– GND Display, DSI 0 Data 1+ Display, DSI 0 Data 1– GND DisplayPort 0 Lane 3– or HDMI Clk Lane– DisplayPort 0 Lane 3+ or HDMI Clk Lane+ GND DisplayPort 0 Lane 0– or HDMI Lane 2– DisplayPort 0 Lane 0+ or HDMI Lane 2+ GND PCIe 1 Receive+ (PCIe #2 Lane 0 muxed w/USB 3.0 Port #0) PCIe 1 Receive– (PCIe #2 Lane 0 muxed w/USB 3.0 Port #0) GND PCIe 0 Receive+ (PCIe IF #0 Lane 0) PCIe 0 Receive– (PCIe IF #0 Lane 0) GND GbE Transformer Data 3+ GbE Transformer Data 3– GND Not used PEX_RX4P PEX_RX4N − − − − − Ground Legend Notes: − 1. 2. 3. Power Not available on Jetson TX1 Reserved Optional source of UART on Exp. Header Debug Header Sensor Display/Camera Conns. SD Card GND Camera Connector GND Camera Connector GND Camera Connector GND Display Connector GND Display Connector GND Display Connector GND Display Connector GND Direction Pin Type Output Input Output Input Output Input Bidir Bidir Output Bidir Bidir − Input Input − Input Input − Input Input − Output Output − Output Output − Output Output − Output Output − CMOS – 1.8V CMOS – 1.8V CMOS – 1.8V CMOS – 1.8V CMOS – 1.8V CMOS – 1.8V CMOS – 1.8V CMOS – 1.8V CMOS – 1.8V CMOS – 3.3V/1.8V CMOS – 3.3V/1.8V GND USB 3.0 Type A (Default) or M.2 Key E GND PCIe x4 Connector GND LAN GND − Input Input − Input Input − Bidir Bidir − − MIPI D-PHY GND MIPI D-PHY GND MIPI D-PHY GND MIPI D-PHY GND MIPI D-PHY GND AC-Coupled on carrier board GND AC-Coupled on carrier board GND PCIe PHY, AC-Coupled on carrier board GND PCIe PHY, AC-Coupled on carrier board GND MDI GND − Unassigned on Carrier The Usage/Description column uses the Jetson TX2 port/lane/interface references. In the Type/Dir column, Output is from Jetson TX2. Input is to Jetson TX2. Bidir is for Bidirectional signals. These pins are handled as Open-Drain on the carrier board JETSON TX2 OEM PRODUCT | DESIGN GUIDE | 20170912 97 Notice The information provided in this specification is believed to be accurate and reliable as of the date provided. However, NVIDIA Corporation ("NVIDIA") does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information. NVIDIA shall have no liability for the consequences or use of such information or for any infringement of patents or other rights of third parties that may result from its use. This publication supersedes and replaces all other specifications for the product that may have been previously supplied. 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