MCS 4 Msc4 Manual
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"1
Features
. Microprogrammable
PROMs
Directly
4004
. Interface 1702A
Completely
--
CPU
4004
to
46
With
CPU
Parallel
4-Bit
.
CPU
. Directly CompatibleWith
General Purpose Computer
Set
Execute MCS-4 Programs from
any Mix of Standard Intel PROMs,
ROMs
.
Input
4-bit
16
to
Up
--
Ports and 16 4-bit Output Ports
.
Lines
Compatible
TTL
are
I/O Ports and Control
Compatible
.
and
ROMs
Directly
MCS-4
CPU
With
in
Number
of I/O Ports is
CPU
-
the
(Write
WPM
New
Instruction
Memory)
is
Used
RAM
of
. Packagedin 16-PinDual
Configuration
Alterable
(RAM)
Unlimited Number
Output Lines
Loading
Storage
of
Bits
5120
Program
In-Line
Memory
up
and
ROM
of
Bits
32,768
Program
Drive up to
.
can Directly
One
RAMs
Independent of the Size of
. Easy Expansion
to
Storage
Each Port May be Both Input and
Output
.
2-PhaseDynamicOperation
. 10.8 Microsecond
Instruction Cycle
.
Program
Memory
. Expanded1/0 Port Capability
in 850
Microseconds
.
Interface
.
8-Digit
Two
of
Numbers
.
Permits
Alterable
Modes
Addition
.
Arithmetic
.
RAMs
Conditional Branching,
Jump to Subroutine and
Indirect Fetching
. Binary and Decimal
and
. InstructionSet Includes
TTL
Eliminates
Instructions
Program
for
.
~
4004 PhotomicrographWith Pin Designations
SYSTEMS
lOGIC
RANDOM
TO
ALTERNATIVE
THE
-
General Discussion
inception,
digital
usage.
In particular,
cations
has
effect
have found
having
is
dedicated
appli-
a minicomputer
at
the heart
of a
random
logic.
systems
NOW
being
implemented
with
has
complicated
MCS-4
smaller
INTEL
THE
many
pur-
general
a
of
power
the
makes
technology
in
concept
SET.
new
COMPUTER
This
in
design.
.
in
logic.
MICRO
with
OFFERS
its
random
on systems
the size and cost of even the smallest
minicomputer
use to relatively
large and costly
systems.
This has
Unfortunately,
resulted
from
significant
advantages.
Minicomputer
systems
are
can be easily
personalized
for a particular
customer's
and can be more easily
changed or updated
than fixedsystems.
For most designers,
the programming of a minia much easier and more straightforward
procedure
than
a controller
limited
evolved
control.
The developthe scope of computer
.
computer
designing
have
and into
increased
the use of minicomputers
had a profound
engineers
system offers
more flexible,
requirements,
logic
design
applications
processing
has vastly
LSI
Many
computer
through
data
minicomputer
ALTERNATIVE.
its
calculation
ment of the
ANOTHER
Since
pose computer available
to alDK>st every logic designer
and represents
a strong attack on the dependency of systems manufacturers
on complicated
random
logic
systems.
This
component
computer
from
Intel
can
provide the same arithmetic,
control
and computing functions
minicomputer
in as few as two 16 pin DIP's and costs nearly
of magnitude less.
implemented
with
a
totally
of a
2 orders
self-contained
system
built
be.
now
can
TTL
MSI
and
the minicomputer,
but rather
new ranges of applications.
55I
of
built
now
systems
many
example,
For
The set is not designed to compete with
to extend the power of the concept into
around
this
set of devices.
the
I/O
and
the
The
the
RAM's
can
tables;
Auxiliary
MCS-4
family
(CPU)
which
data
functions.
and
system.
outside
unit
Registers
Shift
and
of
devices
processor
processing
central
microprograms
data
store
which
capacity
circuits
chip
and
a single
instructions.
ROM's
and
data
are
CPU
store
the
to
which
expand
with
is
control
system
all
each
performs
of
which
Heart
system
through
communicates
"ports"
provided
With
these
computers,
combinations
and with
you
build
computers
microprogramming.
microprogramming
of
requirements.
1
SR's.
CPU,
ROM.
of
one
of
one
and
number
consist
CPU
one
arbitrary
usually
distributed
computers,
dedicated
and utilize
the
infinite
The
the
an
just
and
will
with
can
personalized
of
RAM's
16
devices
designed
to
of
components,
or
be
up
set
this
ROM's,
could
16
using
to
system
one
system
minimum
from
A
on each RAMand ROM.
A
A.
INTRODUCTION
designer
ROM fulfills
buys
his
almost
standard
own unique
devices,
circuit
~
system
or
circuit
cally
the
parts
boards.
and
checkout
erasable
prevent
economies
insertion,
changes,
size
come
is
easier
Switches,
power.
using
ROM's,
and
system
obsolescence.
from
simple
ability
lower labor costs,
displays,
etc.
are
also
electri-
to
insert
package
lower
design,
inventory
When designing
with
random logic
(logic
gates,
flip
the designer
will
usually
start
with
a description
function
and attempt
to wire
counters,
gates,
etc.
function.
ability
and low
ROM
programming
is easierthan
helps
automatic
program
and small
system
and
microprograms
Manufacturing
easy
system,
design,
programmable
new
microcomputers:
with
shrink
of
random
Intel
flexibility,
expand
Expediency
to
of
design,
Qreat
advantages
DIP
major
because
The three
of
flops,
etc.),
of the desired
to achieve
this
connected
to
the
logic
To correct
errors
or make changes in a design
usually
requires
significant
changes in wiring,
often
requiring
that
circuit
boards
be
scrapped
and replaced
by new ones.
of
the
system
via
the
input
or binary
Switches,
designer
etc.
ROM.
variety
in
implements
arithmetic,
displays,
and output
the
he
a
of
and
sequences
decimal
etc.
Set,
However,
complete
quite
suitable
is
to be performed:
table-lookup,
Computer
description.
wide
HCS-4 Micro
instructions
the
functional
set
by
functions
decisions,
to
with
the
instruction
MCS-4
The
functions
with
allows
same design
starts
these
again
encoding
To do the
counting,
are
connected
ports.
As a result
of this
organization.
almost
the entire
logic.
the entire
I'-personality"
of the machine
is determined
by the instructions
in ROM.
Very significant
modifications
of machine
characteristics
can be made
by changing
or adding
ROM's without
making any changes in wiring
or
circuit
boards.
Thus
the
set
offers
tremendous
flexibility
of
design
and
allows
the
high
market
to
asso-
cycle.
insurance
provides
response
flexibility
development
thus
rapid
and
long
cycle
more
and
much
computer
designing
custom
computers
2
set
is
instruction
arithmetic,
the
in
stored
of
Set
with
the 4004 CPU. This device
set which allows
the system
control
and decision
functions
standard
components.
the
Computer
designer
of the MCS-4 micro
microprograms
The
design
of
Micro
the
MCS-4
give
the
has a powerful
and versatile
to perform
a wide variety
of
power
LSI
custom
with
allows
short
disadvantages
The
the
of
possible
programming
etc.
none
for
devices
Applications
Heart
is
obsolescence.
ROM
against
B.
ROM
than
with
costs.
have
yet
demands
ciated
development
and
user to have many of the desirable
features
of a custom MaS LSI design-small
package count.
a set of components
which
is uniquely
his own
(for
each user's
program
routines
are his proprietary
property)--
You
can
- Because
of
programming,
the
in
systems
as those
and
in
highway
the
controls,
low
initial
cost
and
can be used in place of random logic
MCS-4
microprograms
ROM
ing
such
of
flexibility
Functions
elevator
Here are a few examples:
anywhere.
process
control,
numeric
and rail
traffic
controls.
can
be
controls,
By changmodified
Control
almost
easily
MCS-4
system
the
whole
use
updated.
Computer
Peripherals
peripheral
-
equipment
readers,
plotters
The
to
and to
system
can
be
control
displays,
give
intelligence
conveniently
used
keyboards,
to
in
printers,
terminals.
,puter
test
system
c.
com-
central
decentralize
to
functions.
Other Applications
tions
used
efficiently
be
can
MCS-4
the
Computing
Systems - The MCS-4 system is ideally
suited for such
devices as billing
machines, cash registers,
point of sale terminals and accounting machines.
For example, the adding of two
8-digit
numbers can be done in 850 microseconds.
In addition,
within
- The elements
transportation,
systems.
where
of the
automotive,
inexpensive
dedicated
MCS-4
medical
have
many
applica-
electronics
computers
can
and
improve
performance.
Features of the MCS-4
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
4-bit
parallel
CPU with
45 instructions
Decimal
and binary
arithmetic
modes
10.8 ~ instruction
cycle
Addition
of TWo 8-digit
numbers in 850 psec.
Sixteen
4-bit
general
purpose
registers
Nesting
of sUbroutines
up to 3 levels
Instruction
Set includes
conditional
branching,
and indirect
fetching
2-phase
dynamic
jump
operation
Synchronous
operation
wi th memories
Direct
compatibility
with
4001,4002
and 4003
No interface
circuitry
to memory and I/O required
Directly
drives
up to:
4K by 8 ROM (16 4001's)
1280 by 4 RAM (16
4002's)
128 I/O lines
(without
4003)
Unlimited
I/O (with
4003's)
Memory capacity
expandable
through
bank switching
16-pin
DIP
package
P-channe1
Silicon
Minimum system:
Gate MaS
CPU and one ROM
3
to
subroutine,
MCS-4 SYSTEM DESCRIPTION
General Description
Each
MCS-4
circuit
constitues
a basic
allows the design of many different
fabricated
using the same parts.
standard
building
by
The MCS-4 micro
computer
set consists
packaged
in a 16 pin DIP package:
following
A
A
A
A
(1)
(2)
(3)
(4)
block
which
types of systems which can be
The only custom part is the ROM
chip which will
store
a microprogram
defined
a metal mask option
for each new program.
of
the
the
user
and requires
4 chips,
each
Central Processor Unit Chip -CPU - 4004
Read Only Memory Chip - ROM - 4001
Random Access Memory Chip - RAM - 4002
Shift Register
Chip - SR - 4003
The CPU contains
the control
unit and the arithmetic
unit of a general
purpose microprogrammable
computer.
The ROM stores microprograms
and
data tables,
the RAM stores data and instructions,
and the Shift
Regis-
mation
flow
be~ee~
for
control
signals
data
infor-
all
for
used
is
bus
data
single
except
the
4-line
interfaceability;
chips
increase
a
optimum
of
for
the
effectively
means
designed
by
to
ROM's
devices
and
I/O
the
D).
,
D
Dl'
with
has been
communicates
(DO'
bus
CPU
The MCS-4 set
with
RAM's
is used in conjunction
number of I/O lines.
This
ter
the
Which
are
One.CPU controls
custom
be
can
lines
I/O
192
and
lines.
combined
4002
and
functions,
RAM
4001
and
Each
ROM
the
capability
for
the
MCS-4
providing
ROM
devices.
programmable
I/O
mask
metal
Bit
microprogramming
chips.
from
RAM
and
ROM
different
with
2048
a
communication
is
4001
for
the
in
although
CPU.
located
The
lines
-
I/O
RAMS
additional
5
&
over
ROMS
48
ROM
one
function,
I/O
4
4001-ROM
has
by
physically
is
The
controlled
to
and
up
RAM
gates
to
few
of
sent
up
to 16 ROM's (4K x 8 words),
16 RAM's (1280 x 4 words), and 128 I/O
lines without
requiring
any interface
circuit.
With the addit,ion
micro
320
stores
it
RAM
a
As
functions.
two
performs
4002
The
converters,
etc.
4
A-D
readers,
switches,
te1etypewriters~
printers,
bits arranged as 4 registers
of twenty 4-bit
characters
each.
As a vehicle
of communication with peripheral
devices,it
is provided with 4 output lines and associated
contro110gic
to perform output operations.
- The 4003 is a 10 bit Seria1-in/paralle1-out,
serial-out
shift
register.
Its function
is to increase
the number of
output lines to interface
with I/O devices such as keyboards,
displays,
4003-SR
-
computer
set.
Each chip is organized
as 256 x 8 bit
words
which can be used for storing
programs
or data tables.
Each
chip also has a 4 bit input-output
(I/O)
port which
is used
to route
information
to and from the data bus lines
in and
out of the system.
4002-RAM
A.
II,
processor
unit
designed
to work
other
members of the MCS-4 micro
SYNC
L I
RESET
set
16 ROM's.
,.
1.
CM.ROM
1/0
4001
I
,-
I
RESET
SYNC
~
I
.r-r
=0
I/O
CL
RESET
SYNC
-1~
4001
=1
Figure 1. MCS-4 System Interconnection
a synchronizing
signal (SYNC), indicating
cycle,
and sends it
to the ROM's (4001)
5
the start
and RAM's
generates
(4004)
CPU
The
cycle.
instruction
~sec
10.8
a
Operation
uses
System
MCS-4
Basic
The
B.
of an instruction
(4002).
to
RAM
4
one
to
and
up
RAM's)
up to
con-
chip
devices
the
of
CPU
The
the
members
peripheral
used
':M-RAMo
1
are
control
of
in
system.
which
16
can
of
line
capacity
a bank
1
I
I
4004
of
.,
control
with
and
ports.
bus
data
SR
I/O
four
(each
system
to
lines,
1
used
or
line
total
chips
control
GNO
is
self-contained
~D
which
ROM
RAM,
four
the
for
chips
control
command
RAM
5
tains
completely
other
a
with
form
communicates
to
the
through
a
CPU
set
through
The
computer
a central
with
the
the
- The 4004 is
conjunction
a
4004-CPU
Basic
clock.
instruction
execution
requires
8 or 16 cycles of a 750 kHz
In a typical
sequence, the CPU sends 12 bits of address (in
three
4 bit
bytes
on the
data
bus)
to
the
ROM's
in
the
first
three
cycles (A , A ,A3).
This address selects
lout
of 16 chips and 1
out of 256 8-~it words in that chip.
The selected
ROM chip sends
in
bus
data
executed
line
4
two
X2
transferred
during
lines
is
2)
data
r/o
ROM,
the
Figure
ROM
four
from
next
and
the
over
the
interpreted
sent
is
CPU in
(See
the
on
received
~,X3).
accumulator
CPU
the
then
is
instruction
OPA) to
instruction
(Xl'
is
cycles
instruction
the
r/o
three
from
or
to
an
final
(OPR,
This
The
bit~ytes.
4
two
the
When
in
instruction
~).
of
(ML'
8 bits
cycles
back
the
CPU
the
the
of
lines.
content
When
to
character
control
transferred
and
command
is
executed.
the
CPU,
output
RAM
the
is
and
register
four
of
chip,
CPU
RAM
one
four
by
instruction
the
a
by
of
RAM
the
to
received
a
in
address
controlled
transferred
is
when
registers
The
is
time
X3
index
CPU.
RAM's
two
is
instruction
X2'
in
the
four
of
output
during
stored
from
set
CM-
and
flip-flops
0
and
address
from
registers
the
of
start
will
CPU
contents
the
the
RESET,
activated
After
is
selected.
cleared.
is
RAM
are
RESET
CPU.
RAM's
andROM's
canbe controlledby an externalRESET
line.
While
The
.
accumulator
RAM
RAM
is
lines
A
time.
c.
MCS-4
Logic
shown.
The
minimum
system
and
one
ROM
(4001).
An
configuration
Definitions
The MCS-4 devices operate with negative Logic.
Logic
as the low voltage
(negative
voltage)
Level and Logic
as the high voltage Level (Vss>. This definition
will
throughout
the manual.
D.
1.
Figure
in
shown
is
system
MCS-4
is
(4004)
CPU
one
configureation
of
consists
expanded
the
of
interconnection
The
0
"1" is defined
ItO" is- defined
be used
Basic System Timing
For the correct
operation
of the system two non-overlapping
clock
- '1' ~2 - must be externally
supplied
to the 4001,4002
and
phases
4004.(1)
(I)
The 4004 will
generate
and will
beginning
send it to'the
400l's
of each instruction
generate
internal
The 4003 is a static
for its
operation.
timing
using
shift
sn~c
register
6
a SYNC signal
every
8
clock
and 4002's.
The SYNC signal
cycle.
The 400l's
and 4002's
and ~1'
and does
periods
marks the
will
then
Q2.
not
use
these
two
clocks
c~
~~,...
Figure2. MCS-4&.ic InstructionCycle
data
data
condition
data at
4004
-
(CPU)
UNIT
PROCESSOR
CENTRAL
BIT
A.
III
4
line,
therefore
all the other buffers
must be in a floating
However, more than 1 input buffer
per data line can receive
the same time.
a
drive
"0" and floating.
"1",
allowed
states:
and what
Each
subdivided
period.
is
clock
each
cycle
is
possible
buffer
three
output
only
has
bus
during
on the data
buffer
time,
given
output
a
At
bus
is
1
the activity
to
Figure 2 shows how a basic instruction
Description
The 4004 block
functional
(1)
(2)
(3)
(4)
(5)
diagram
blocks:
shown in Figure
3 contains
the following
Address
register
(program counter and stack organizaed as 4
words of 12 bits each) and address incrementer.
Index register
(64 bits organized
as 16 words of 4 bits each.
4-bit
adder.
Instruction
register
(8 bits wide),
decoder and control.
Peripheral
circuitry.
Ihe functional
blocks communicate internally
through a 4-line
bus
and are shown in Figure 3. The function
and composition
of each
block is as follOws:
7
Stack
&
counter
ram
R
Address
.1.
& Address
Incrementer
address
register
is a dynamic RAM cell array of 4 x 12 bits.
It contains one level used to store the instruction
address
(program counter)
and 3 levels
used as a stack for subroutine
calls.
The stack address is provided by the effective
address
counter and by the refresh
counter,
and it is multiplexed
to the
decoder.
The
4-
three
in
AJ
and is
and
A2'
,
A
during
bus
internal
the
to
demultiplexed
The address when read is stored in an address buffer
bit slices
(see Figure 2 for basic instruc!ion
cycle).
The address
is incremented by a 4-bit
carry look-ahead
circuit
(address incrementer) after each 4-bit
slice
is sent out on the data bus.
The
incremented
address is transferred
back to the address buffer
and
finally
written
back into the address register.
v. v.
..
..
SYNC
OOTPVT
INTERNAl
RAMJ
RAM,
RAM,
RAMo
CM CM CM CM
RESET
TOT
SYNC
RElET
eufflR
'IF
---T-
r I
CM-RAM
OUTPUT BUFFERS
TIMING
ADORE.
CM
INCREMENTER
LOG~
~
a-
MULTIPLEXER
~
AW\.I..
'IF
.
'IP
REGISTER
BUFFER
CC*TROL
~=
h~
~
~~~
CYCLE
ICX*TROL
FOR
~ER
~IVER
~RE8
(PROGRAM
~ER
lr
C<*TROl
~
THE
REGISTER
:;rtiR
.-CIAL
ADORE.
STACK'
.
.
MUX
CMRYFIF
IMJeX
4 .
12 BIT
DYNAMIC
REGISTER
~
~A
~
MUX
#2
~
.
. "IFTER
I~UCTION
~R
MJFFER
r-
REGISTER
r8"t
~
.
REFRE84
---I
j
.3
EFFECTIVE
A(X)RE8
IEGI~R
~I
I*TR~
I
~ER
~
.~R
OONTROt.
~
ADGER
RAM
DlmDER
DECOOER
.,
~
MOISTER
.
IN-OUT
8UFFE~
ACC~AT~
~
~R
AW\.I.
~
orA
REG.
.MUX
,REGISTER
REGIsnR
ADa
INDEX
lIT
',.4
REGISTER
~
IW
DATA
Figure 3. 4004 CPU Block Diagram
8
RAM
DYNAMIC
MUX
.
I
COUNTIR
DRIVER
REFRE"
DECOOER
--L-
INTERNAl.
BUffER
~
..
bits
the
4
addressable
storstoring
of
loca-
In the second
for
RAM
8 pairs
x
16
of
operation
of
array
cell
RAM
one
mode
storage
bus
index
the
internal
to
the
by
multiplexed
is
provided
is
and
address
ROM.
addressing
provides
counter
refresh
the
register
from
for
register
locations
fetched
by
index
data
The
and
addressable
and control.
as
index
directly
well
the
16
computation
as
mode,
In
provides
ROM
intermediate
and
for
decoder.
4-Bit
a
into
bus
internal
the
register.
of
index
the
to
then
and
content
register
is transferred
to the internal
Writing
into the register
is accom-
transferring
register
by
temporary
plished
of the index
a multiplexer.
the
register
dynamic
a
is
operation.
register
age
index
tions
The content
bus through
3
of
register
modes
two
has
and
index
Index Register
The
2.
Adder
The 4-bit
adder is of the ripple-through
carry type.
One term of
the addition
comes from the "ADB" register
which
coanunicates
with
the internal
bus on one side
and can transfer
data or QiEi
to the adder.
The other
term of the addition
comes from the
accumulator
and carry
flip-flop.
Both data and data
can be
Process)
transferred
is provided
also
for
internal
conver-
used
(Keyboard
KBP
a
code
3-bit
perform
a
ROM's
a
control
and
command
and
special
accumulator)
special
the
with
instructions.
flip-flop
the
holds
the
The
adjust
The
left
to
the
is
with
register
ROM's,
control
(decimal
instructions.
the internal
bus.
ACC - 0 conditions,
an external
signal
and ISZ (increment
adder
code
the
The accumulator
right
and rotate
communicates
switching.
command
DAA
for
line
The
bus.
CM-RAM
sion
of
FF.
rotate
also
special
accumulator
register,
The
output
and carry
implement
ROI~'s
The
accumulator
shifter
to
condition
transferred.
communicate
with
The condition
logic
senses ADD - 0 and
the state
of the carry
FF, and the state
(TEST) to implement
JCN (jump on condition)
index
register
skip
if zero)
instructions.
of
4.
the
and
contents
fetched
instruction
the
in
t~e
OPR Register
with
of
cycle)
the
from
of
loaded
the
~
is
hol&s
and
wide)
And
(at
bus
(consisting
4 bits
multiplexer
a
internal
through
the
each
instruction
register
OPA Register
~
The instruction
(instead
of
8
bits)and
that
require
two
cycles
(16
wide
bits
16
Double-
system
is
OP-code
instructions.
whose
double-length
5
instructions
of
are
anyone
from
set
instructions
is
length
FF
ROll.
The instructions
are decoded in the instruction
decoder
and appropriately
gated with
timing
signals
to provide
the control
signals
for the various
functional
blocks.
A doUble cycle
clock
cycles)
for their
execution.
Double length
instructions
are
in two successive
locations
in ROl.I. A condition
FF controls
and ISZ instructions
and is set by the condition
logic.
The
of an external
pin "test"
can control
one of the conditions
JCN instruction.
9
stored
JCN
state
in the
Peripheral
Circuitry
This includes:
a. The data bus input-output
buffers
data pads and internal
bus.
all
start
from
all
registers
for
at
index
(256
"0"
step
and
control
command
RAM
RAM's and static
After
"0".
CM-RAM
is
selected.
in
the
and RAM locationi
least
8 full
instruction
register
refresh
clock
cycles
for
.Instruction
To
CPU the
cycles
counter
the
4002
FF's
to scan
RAM).
are
completely
reset
(6-4
clock
all
locations
clear
signal
cycles)
must
to
in
instruction
repertoire
a.
16 machine
b.
14 accumulator
c.
15 in~ut/outP.ut
of
instructions
The instruction
the next section.
memory.
the
4004
consists
(5 of which
group
are
of:
doUble
length)
instructions
and RAM instructions
set
and its
format
Section
VII will
will
be briefly
then describe
described
in
each instruction
and Operation
Organization,
Register
Index
Format,
Set
Instruction
detail.
of 'the Address Register and Command
Instruction
Set
a.
Instructions
Machine
Lines
Format
ROM
in
location
wide and requiring
cycle)
one
occupies
2-word instructions
-16 bits wide and requiriag
16 clock periods (2 instruction
cycles) for
execution
truction
instructions
- 8 bits
periods
(1 instruction
ins
.
l-word
l-word
8 clock
A
.
address
(3) 4 bits of data
(4) An instruction
modifier
10
load.
things:
into
4
the
divided
modifier.
operation
that
the
operation
the
of
of
lower
called
is
the
The
is
word
bits
code.
contains
and
code
the
one
subtract.
address
register
pair
register
A
instruction
(add.
contains
be performed
4
upper
instruction
operation
OPA
the
the
The
Esch
machine
contains
word
(OPA)
to
modifier
(1)
(2)
ROM.
contains
called
is
(OPR)
a single
code
For
is
fields.
in
4-bit
and
bits
OPR
two
tions
(each location
can hold one 8-bit
word)
and s
2-word
instruction
occupies
two successive
loca-
A
CPU
allow
Repertoire
The
1.
cleared,
will
low),
control
pin
program
(Reset
reset,
reset
and
thedata
bus
is setto
in
4
Reset flip-flop.
During
B.
the
and
(CM-ROM)
buffers.
control
output
command
ROM
1
(C~RAMi)
d.
6
between
Timing and SYNC generator.
c.
b.
communicating
4
5.
etc.).
The
be applied
the
a 2-word
one of
A register
A register
The upper
A condition
ONE WORD INSTRUCTIONS
ROM address
Xl
I
X
I
X
I
X
I
X
I
X
I
X
I
X
I
~l
I
X
~A
~
~A
~
I
~IFIER
I
CODE
OP
I
MOOIFIERI
I
~COOI
I
I
I
AJ
AJ
ADORE.
AJ
~R
A,
I
X
I
v
I
I
w
X
I
I
w
OR
I
C.
CJ
CONDITION I
C.
I
X
I
X
,
v
c,
I
v
I
I
X
x
I
v
I
I
PAIR
REGISTER
I
ADORE8
A,
A,
A,
A,
A,
A,
UPPER
DATA I
LOWER
DATA I
I
D,
D,
D,
D,
I
OJ
DZ
OJ
DZ
I
R
ADDRESS
PA:IINDEX
IIN~XA~~rs\R
x
X
I
x
X
I
x
X
I
x
X
l
OR
A,
R
A,
R
LOWER
ADDRESS
MIDOLE
1"1"1"1"100001
ADDRESS
I
x
X
R
I
x
X
REGISTER
I
x
X
~NDE:'l.~~~;ER
X
INDEX
1
DATA
OR
X
R
R
X
I
I
I
w
v
,X
P:R
PAIR
REGISTER
X
INo
R
ADDRESS
I
OR
1
field
the
and
of
OPR)
bits
MI
fetched
OPA).
the contents
and
8
be
in
during
always
I illustrates
machine
(in
or
portion
will
lower
4 bits
(OPA)
Table
in
address
middle
the
instruction
of
(OPR)
and
ROM
the
another
OPR
in
of
either
instruction
bits
4
of
bits
OPA)
contains
respectively.
4-bit
of
instructions.
Group
&RAM
Instructions
andAccumulator
Input/Output
b.
bits
lower
4
the
before
M2 times
each
4
upper
upper
(the
The
data
(in
word
portion
2nd
lower
The
T8bIo1- M8d1ineInstructionF~
Instructions
In these instructions
(which are all
contains
a 4-bit
code which identifies
instruction
or the accumulator
group
contains
a 4-bit
code which identifies
performed.
Table
0,
0,
II
illustrates
Dt Dt
Dt 0,
the
Dt
Dt
I
I
I
-
I
I
x
x
I
x
x
I
I
I
~
x
I
I
I
x
x
I
I
I
a
.
1
I
I
I
.
1
1
I
I
I
~
.
1
1
I
.
I
1
I
1
I
.
."'I'I'IAIAIAIAI
GA~
I
.
IWVY.QJTPUT
INIT"~'OM
~ULATO"
RAMIN8TR~~
--AI X. EITHB
A
Table II
-1/0 and Accumulltor
~ A..,-.
Group Instruction
11
single word) the OPR
either
the I/O
instruction
and the OPA
the operation
to be
contents
Lxlxlxlxlx!xlx!xl
x
X
I
X
X
I
R
R
R
R
,
~
IIN:Ex.~~~S:S:R
X
I
X
X
X
X
I
1
X
I
De
REGISTER
AO~ESS
I
x
INDEX
I
~NO~~A~E;;ERR
x
X
I
X
I
X
I
X
X
1
similar
(OPA)
.J
MODIFIER
I
~
x
X
I
X
x
X
l
OP
(
is
DrA
~
I
Ix/xlxlxJxlx/xlxl
I
D,
X
0.
I
0,
word
modifier
4 things:
X
0,
I
0,
1st
the
address
pair
address
portion
of another
for jumping
X
0.
I
0,
0,
the
however,
nW> M>RD INSTRUCTIONS
lit INSTRtx:TION
CYCLE
2oIdINSTRtx:T1ON
CYCLE
DJ D, De D, DJ D, De
D, D, D, De D, DJ D,
X
0,
instruction
instruction,
X
contains
(1)
(2)
(3)
(4)
machine
l-word
I
a
X
to
I
For
Formats
of each 4-bit
field.
modes
two
in
addressed
a.
By specifying
lout
of 16 possible
locations
code of the form RRRR(l) (See Table III).
b.
By specifying
lower
data
fetched
as
fetched
the
from
the
location
from
the
of
ROM, the
the
even
the
middle
of
register,
pair
location
a
as
as
used
used
data
used
an OPA code of the
odd nwmer
lower
address
RO~.
AOORESING
'AIR
N~ER
PAIR
REGISTER
NU_ER
REGISTER
REGISTER
ADORE_NO
the
is
with
art OPA
III).
is
upper
(RRRl)
REGISTER
SINOLE
the
is
register
or
register
or
Table
(RRRO)
index
register
address
of 8 pairs
(See
the
lout
RRRX{2)
the
number
When
form
with
the
can
Oraanization
register
index
The
Index Register
be
2.
Teble
3.
III
. Index Register Organization
Operation of the Address
Register
(Proaram
Counter
and Stack)
The address register
contains four 12-bit registers;
one register
is used as the program counter and stores the instruction
address.
the other 3 registers
make up the push down stack.
address
effective
the
becomes
then
address
new
This
out.
sent
is
Initially
anyone of the 4 registers
can be used as the program
counter to store the instruction
address.
In a typical
sequence
the program counter is incremented
by 1 after
the last address
If a JMS (Jump to Subroutine)
instruction
is received by the CPUt
the program control
is transferred
to the address called out in
JMS instruction.
This address is stored in the register
just
above the old program counter which now saves the address of
the next instruction
to be executed following
the last ~ffi.(3)
This return
address becomes the effective
address following
the BBL(Branch back and load) instruction
at the end of the
subroutine.
(-1)
In
by
In
by
this
case the instruction
RRRR.
this
case the instruction
RRRX, where X iR specified
Since
address
instruction
the
JNS
is
instruction
incremented
to
be
is
is
on the
4-bit
content
addressed
is executed
on the
for e~~
instruction.
a-bit
content
addressed
a
by 2 to
execute"d
executed
2-word
instruction
correctly
after
12
the
give
return
the
the
from
old
address
J~fS.
effective
of
the
next
(1)
~
-.
.
is
always
the number of ROM's in the system needs to be more than 16, external
can
be
used
to
route
CM-ROMto two ROMbanks.
The same comment
applies
to the ~RAMi
lines if more than 16 RAM's need to be used.
circuitry
If
13
to
up
control
can
instruction.
chip
RAM
and
well
as
chip,
bank,
RAM
of
ROM's and RAM'. by indicating
to them how to interpret
bus content at any given time.
DCL
the
of
ROM
addressing,
Conma!}.!!
SRC
stack.
address
counter
program
the
pushes the program
however,
line,
line
group
each
chip
CM-RAMi)
control
can
RAM
in
pushes
instruction
~ROH
the
It.-ruction
Subroutine
to
llVll
~
~
~
ax*TaR
-
CM-ROM
line
ROM
the
of
~~
~~R
--. ~ICIIVIO
-
and
I/O
and
.hAmp
n
~E8
RmMN
~~IR
.,
~..
AlTUM
.1
~E8
R~
n
~E8
AIT\MN
.~
ADORa8
RmMN
PMJORAM
~R
~
.J
~
~ETUM
- -
execution
4002'8.
.
on
~~R
COt*TIR
'ROGRAM
-
the
the
control
instruction
..
-£8
R~
~~~R
~1CafYaO
-
by
an
Lines
RET\MN
~
. L~
~RAMi
implementation
(~ROH.
ReIiIt8r
Ad*-.
the
of
~.afi
IV.
- ~.1
The
can
each
the
BBL
a
J}fS
selected
addressing,
operation
the
a
instruction.
receives
Co~d
and
then,
b.
configuration
allow
linea
The
level
one
up
MT~ ACORE8
.2
and
instruction
the
character
linea
of
shows
IV
Table
sununary,
CPU
the
and
command
~ration
PROGRAM
~I~
s
4001'
systea
time
CPU
The
~..
--
Line)
Each
line
four
sixteen
command
The
In
typical
register
nIE~ ,
CM-RAMi
activating
as
RlcalVEO
-
the
at
"-2-
a
In
EF,eCTlve
to
up
T...
AOOR"
RIcaIWD
Command
(Designate
4.
~IVED
RIG~R
~
RIG~R
~-
:~
~~_., --=:W~ Law..
'-83
~ICIIVID
R~~.J
~~.2
counter
down one level.
Since there are J registers
in the push down
stack,
J return
addresses may be saved.
If a fourth
JMS occurs,
the deepest return
address (the first
one stored)
is lost.
are used to control
the data
the
.
enabled.(l)
14
convenient
affect
executing
of
executed
be
bank)
RAM
One
CPU.
the
example
(for
desired
the
uCM.AAM,ISACTIVATED
u
CM-RAMo.
after
until
register
SRC.
one
10PAI
MODIFIER
THE
'-'
SRC
new
a
an
RAM
AND
0
If
THE
OF
~
WRR,
RDM.
(WRM.
fetched
be
must
instruction
Control)
Register
(Send
SRC
the
and character
(by
This
bank.
RAM
same
the
time
RECEIVED
IS
INSTRUCTION
U
the
instruction
In
time.)
by
not
to
be
RAM',
AND
ROM's
BY
~C
instruction
using
selected
selected
omitted).
selected
is
it
control
DCL the CM-RAMicode is transferred
are
controlled
2
on
in
accumulator
instruction
FETCHED
11--'
does
would
the
ADDRESS
TO
RAM
and
I/O
be
be
start-up
Each
command
register
CPU
THE
I.BIT
THE
'
necessity
operate
(selecting
in
DCL
BY
BY
SENT
Aa
.)
.
An
register
&
automatically
DCL
the
which
RAM',
AND
RECEIVED
IS
J
I
A21
A,I
I
.
.
must
system,
time.
the
in
the
of
explanation
a
in
instructions
received.
stored
be
ROM',
REGISTER
_I
Xa1-J
line
at
a bank
will
control
instruction).
must
-I
~
X,I
and RAM group
1
in
without
it
activated
then
command
U
TRANSFERRED
IS
CODE
\
command
Step
because CM-RAMo is
1/0
instruction
is
LDM
CONTROL
COMMAND
I
and RAM chiP.
(usually
each
is
remains
next
execution
to
Prior
a detailed
used
are
and
executed
code
code
~RAMi
_1-
the execution
of an I/O
steps
are necessary:
and
them
bank
RAM
instruction
an
through
-,-
appropriate
RESET
one
arrange
RAM
is
During
~
chips
all
the
to
lator
~-
unnecessary
same
line
CM-RAMi
CM.RAM,
1-
DCL
The ROM chip
is
instruction
the
during
,
least
RAM
DCL
CM~RAMi
The
is
at
the
new
a
Following
4
DCL
instruction
F.".
DCL
to
allows
This
THE
r
FETCHED
SYNC
'U
to
within
CM.ROM
The
of
another
CM.RAMo
(3)
up
If
CM-RAM1
(1)
(2)
case
cation
DATA
Xsi..1 AaI AJI-,!..,
this
(1)
BUS
For
ing
follow-
DCL)
must
I M,I ~ I X,IX2/XI! A,IAtI A,1-,1-2!X,IX21
XJI A,IAaI AJI M,I~:
- I 110ANDRAM
INSTRUCTION
FETCHED
'-'
CM.RAMO
ISDEACTIVATED
u
t
4. Operationof the Comm.ndControl:Lines
of each step.
from the accumu-
CM-ROM.Only the RAM on the designatedcommandline will latch the SRC.
the appli-
is
.,
respond
8-bit
is
a)
that
on
the
the
ROM
a
and
to
logic
a
are
ROMS
in
the
X2
and
now
in
time
during
character
are
X2
bus
is
interpreted
and
RAMS
line
At
data
and
address
address
of
bank
CM-RAKi
cycle.
the
register
to
chip,
sent
which
th~
The 8-bit
selected
instruction
the
SRC
is
RAM
a
to
indicate
to
and
the
address
select
of
state
line
time
This
used
true
CM-ROK
X3
chip.
to
The SRC instruction
specified
an index
register
pair
in
the CPU, whose content
is an 8-bit
address
(this
8-bit
address
has previously
been stored
in the register
pair)
(3)
data
following
bus.
way:
The first
4-bits
(X2 time)
select
one chip out of 16; a flip-flop
is
set in the selected
chip.
The second 4-bits
(X3 time)
are
by the ROM's
b)
ignored.
The
a)
first
select
of
four
bits
bits
sent
of four
registers.
(D),
out
at
chips
X2 time
and one out
The two higher
D2) select
lower
order
register.
by the RAM'.
bit.
the chip
(Dl,
no)
order
and the
select
two
the
The second 4-bits
(XJ time)
select
one
4-bit
character
out of 16;
The address
is stored
in the address
register
of
RAM
the
of
description
detailed
a
for
~
chi~.
Section
selected
(See
the
chip)
b)
equals
however,
were controlled
This
receive
time.
to
M2
at
RAM's
any
~RAMf
of
tiae
selected
AJ
the
at
and
state
true
~ROM
the
logical
a
allows
the
to
expand
the
their
that
within
ROM's
ROM
to
user
a
of
indicates
number
ti~
chip
AJ
at
the
feature
than
the
system.
16 ROM chips.
at AJti~ hasnomeanins
for the RAM
"I"
This
more
is
"1"
time
AJ
equals
at
code
bank.
chips,
The selected
ROM and
(as well
88 the CPU) and
the execution
time of the
cycle.
~ROK
instruction
to
that
in
added
be
always
are
should
lines
It
the modifier
of the instruction.'
RAM will
decode the instruction
appropriately
execute
it during
same instruction
cycle.
and
true
ROM's
logical
be
to
selected
line
previously
CM-RAMi
the
all0W8
selected
At this
time one ROM chip and one RAM chip,
register
and
character,have
been selected.
If the CPU fetches
an I/O
and RAM in8truction,
it will
cause the CM-ROH and the
Cli-RAMt
(4)
four
one out
it
could be meaningful
by a c)1-RAHi
line.
Figure
4 summarizes
the
the various
instruction
15
operation
cycles.
of
if
the
ROM's an4 RAM's
command lines
in
Vshows
c~
Basic I nstruction Set
Table
the
Section
VII
basic
will
instruction
set
describe
each
of
the
instruction
4004
in
(CPU)
detail.
[Those instructions precededby an asterisk (.) are 2 word instructions that occupy 2 successivelocations in ROM]
MACHINE
INSTRUCTIONS (Logic 1 = Low Voltage= NegativeVoltage;Logic0 & Hi~ Voltage. Ground)
the
(within
A1
A1
0-
~n
~j.lr
"..
of
8d«...
en
out..
RRR
pair
re9iater
Indirect.
Jump
1
A
A1
A2.
A30
-»-
ROM
to
unmnditional
Ju~
A1
A1
~
R
R
18
borrow.
with
8CCUmul8ror
fO
R
.
~mu"tor
to
DODO
I.oed
Basic
registerRRRRand8CCUmllator.
1IewIlnlt8Ck)~ 1O8d
~. DDDDto ~mul.tor
Set
A
0
D
V.
R
RRRR to 8CCUmulator.
Excn.,. contentS
of ~x
a-IdI beckI~
R
R
r8gi1-
contents
LO8d~n18nt. of ~r
d8t8
R
A
A
0
D
Table
of
R
R
R
R
A
R
0
A
A
0
, , 0(
, , 0,
D
, 0, ,
-r--Ffldlliidr"8ct-fromROM~n..nts
0
R
R
R
R
SubtrKt
1
0
0
1
Addmntentl of regilt. RRRRto ~mulator with carry.
0
0
0
1
R
~~~~
A, A1 A1 A,
1011)
(Up 1 level
Iftcr!nwntcontentl of_r8tI8t- RRRR. 131
lna-_t
COi1ten..of r8jst., RRRR. Go ro ROM8dfk- A2. A,
(within rN .me ROMthet contain. chi. ISZ in.tructlon) If r..ult ~ 0
ot'--.
.klp (~to tN next Instruction In 8qU8'-~.
Instruction
1
II pIKed IntO regll.., pelr l0C8tlon RRR.
In_k.1
R
1
R
1
A
0
R
1 0
~
1
8ddreA. 0818fet~
Jump to wbroutlne ROMaddI'HI AJ. A2. A1. 8V8 old 8dd,
~A3~~
"
INC
-ISZ
ADD
StM
LD
XCH
IlL
LDM
out.l.n
A1 A1 A1 A1
0
A1
0,
1
°1
--
1
In ~encel.
RRR.12)
CPU
1 0
(go to the next InltrUctlon
.t A1 end A? tln8 In the Instruction Cycle.
A
-J"
0
A2~~~
Ikip
Sendregister~trol. SendN .td,-. (contwntl of index r",ater peir RRRI
to ROM Ind RAM 8t X2 and X3 dIM in the Inttruction Cyde.
A3A3A3A3
D
'JUN
0 1 0 0
A2 A2 A2 A2
A
0 0 1 1
A
JIN
A1
00, ,
A1
FIN
-
A1
Ju~
0
R
R
~
°1
R
SRC
II true, otherwi.
l0C8tion
0 0 1 0
-
Fetch Immedle.. Idlrect) from ROM 0818~. D1 to Index registerpelr
A
"FIM
Dz~Dz~
°1
-JCN
C1 ~C3C4
A1 A, A1 A~
~~A2~
0 0 1 0
-
ROM that contalnl thll JCN Inltructlonl If condition C1 C2 C3 C4111
A2.
1
-
0
Nooperadon
-
0
A2
0
0
A2
0
0
A2
0
-
0
8dfkeSI
0
ROM
0
DESCRIPTIONDF OPERATION
to
0
.
NOF
MA
DJ~o,~
R
MNEMONIC
OPR
~DzD'De
,.,
INPUT/OUTPUT
AND RAM INSTRUCTIONS
RAM'I8nd ROM', ~8t8d on in the 1/0 8nd RAM inltructionl h_!.en
OF~R.T~
CWA
~
(The
~8VlousiVlelect8dby the 181SAC instruetlo..8x8CUttd.1
DEKRIPTION
o,~Dt~
1
0
0
1
~
---
Pl'8ViOuliV
tM
inlO
__1M
-
Into
of the KCUn-.18tor
the
8I8cted
prwiOullV
the
-
Of*vl
-.,-.
with
'*
IfM
Kcumu18tM
Into the pr8¥iOu"v
-.ct8d
Into
8I8cted
1.
cont.nts
of the
acwmulatM
the
Pl'8ViouslV
RAM Iiatul ch8r8ct...2.
of the _n-.I8tM
IntO the D'eYlouIIy
cI\8I'-
from
bof'row.
R.~ the ptevfously1818ct8d A
into
lhe
~
the ~8VIou"V -lee.-
8I8cted
..-vIo\Aly
~~ the KCUmu4ator.
-~~u-~i
meln ff8fr*Y ~
Into
I
8I8ct8d
'
POI't
, 00 ,
, 0t .
, 01,
with
Input
(
aeeurnulalor
ROM
t
RAM statUIcI\8I'3.
SubtrKt the D'eYIouIlV8lect8d RAM ~in -V
.
0
1
t
me~y
of the
Write lhe conten..
.
lhe
~..~
of
h8lf
byte
contents
-the
0
0
, , 0
, , 0
, 10
, , 0
1 10
-..
PIWioUllv
1
1
\
ADM
ADA
ADM
IBM
Write
t
,
,
,
,
,
WA3141
the
RAM ltatul char-
0
, 1, 0
intO the
RAM Itatul characterO.
tOt
WAr41
of the -_tor
Write lhe contents
1 0
1
1 1
1
WR1141
Write
0 t 0 4
.
t 1 , 0
the con18fttl
rNd'-i.
0
0
0
0
WPM
W~141
of
Wrlle
0
0
0
0
0
0
,
0
0
,
,
,
,
WMP
WRR
,
RAM au t
t. IOu t LInes!
Write the contentsof the Kcumu tM nto t
ROMoutPUIport. 11/0Llnnl
Wri.
t t t 0
~tenll
Wrile Ihe conlenll of lhe Kcumu18tMInlo I e D'eY1ouVRAM ~n memoty cl\8l'Kter.
0
,
,
I
WRM
,
OJ~ D",Do
lhe
MNEMONIC
accumUIe\or.II/O.Unell_-
_rnulatM
with
RAM m81nn.mory clw-
to
~y.
R.-j thepnviouliV_lectedRAMstatusc_-
AD114)
.
1 1 0
1 1 0 1
RNd the pr8¥I~"V 8tect8d RAM statUIC'-Kt8l' 1 into 8CCU~I.tor.
1 , 10
t , , 0
1 1 1 0
RMdtN prwiouslyselected
RAMstatusctwKt8f 2 into -~a.-.
AD~4J
0 Into_n-.18t0l'.
Readthe ~lViOUsty.18ct8d RAM statUIc'-Kter
.
ADr4)
1
1 1 0 0
1
1 1 1 0
~
A~141
3 Into 8«u".,I8tor.
ACCUMULATOR GROUP INSTRUCTIONS
bodt. IAccumul8tOl"'-rv1
0-
-rv.
0 0 1 0
I
0 1 0 1
t t t t
0 1 1 0
, . . 1
0 1 1 1
~
nd C8Ty1
IAccu-'-..
,...t.
~
Aoy.. left. IA~mu
Tr8ftfmltC8rryto _mu18tor 8ndct.- ~.
C
D8Cr8n8nt
-mul8tOl'.
--~.
8M
Iubtr8Ct
~
-rv.
Set
0
1
0
I
D8d"-,
8djust KaI
--
1
1
0
1
t
t
1
t
DAA
1
1
.,
1
1
STC
T~1fer
1
0
0
1
~
1
.
t
TQ
-
1
0 0
0
t
~I
t
f
-~.
0.1
t
-,
t
t t t t
. t -.mII'-'.
;;-~t~.
0 0 1 1
, , 1,
DAC
0-
0 0 0 1
0
T~
RAR
RAL
CMA
0 0 0 0
~
~
CMC
1
lAC
,
CLC
,
, , , ,
, , , ,
, , , ,
CL8
lhe mftUn"
of lhe Kaln-.I8tor
fr-
.
--
~.
bln.-y
.
10
~
line
~
17
TableV - BasicCPUInstructionSet (Continued)
0
.
II
~.
""11...
.18C18d
Ch8"Kt.,18nd
CItatul ch.,act.,l.
the
F~
Instructl_.
SAC
8ft
by
8dtke.-d
tOPAI.
code
ch.8C1.,..
Instruction
the
by
~~v
me.n
and
-18C18d
'89IIt.,
IoC8tionl..
RAM
numt.,.
cwect.,
Chip
Iign8I
Jumpif c.-rv/llnk II a 1
(2IRRRII the~..
of 1 of 8 In~. '89111..
~ In the CPU.
t3lRRRRII the ~
of 1 of 16 lna. r8III1W1lnthe CPU.
(CIEech
RAMchiph. C '89IIt.,l. eachwith t-tv 4-bit ch.'Kte'IIU~lvldld Into 18 main~~
IUtUI
t8l1
If
Jump
1
.
Cc
r-
Is
If
~
1
~ . 1
and
Not Inwn jumpcondition
.
~
concItlon
jump
follows:
chip
C, .0
Inwn
t
.
~
NOTES: (11Th. condItion codellasI9n8d.
f-
of
~I
018
0..,.-
1
0
1 1
1
DCL
1 i
1
I
0
0
1
1
K8P
KeybO8'd prOC88. Co_"
likely
tion
in
at the start-up
Section
VII.
time).
18
See detailed
definition
data
receiving
for
it
following
upon.
port8
1/0
the
a
desig-
will
X3
at
chips)
4
of
out
the
of
case
the
In
that
the
to be activated
time
instruction
with
data
in-
is
CM-ROK,
of
CM-RAM(l)
one
and
CM-ROM
will
out
the
1/0
in
1/0
to be operated
code
the
M2,
presence
it
RAM)
and
ROM
to
addresa
conjunc-
in
used
instructions
basic
two
review
first
mode
I/O
the
into
going
Before
M2'
at
ends
mode
ROM
the
in
4001
the
activity
The
H2.
and
HI
cycles:
two
following
the
during
out
data
send
(CSE
AJ
is
8 bits
should
no
If
by
after
a
is
of
ignored.
nU8ber of the unit
to
pina
SIC)
(one
number
send
activated
acccupli8hed
execute
to
ready
activate
instruction
SRC
an
(Send
must
we
operation
"1")
(most
be
executed.
is
an
communicate
to
ia
X3
at
will
and
X3
executes
Instruction.
SR~
whose
chip
the
only
present,
18
CM-ROM
When
time.
optioo
~tal
CK-ROM
with
together
number,
chip
a
and
2)
Figure
(see
time
A2
and
Al
AJ
during
-
System
the
I/O
receives
16)
(by
during
line
chip
the
simultaneous
with
X2,
at
and
the
to
i8
allowed
(OPA)
part
regi8ters);
4
of
Data
operation.
X2
during
data
during
its
4001
instruction
be
will
of
automatically
is
1/0
CPU
the
out
(one
designate
will
Data
X2.
at
line
sent
once
lines
CPU
the
allow
at
selected
CM-RAK
4002
one
and
out
instruction
preaent
second
When
4O02's.
number
X2
by the 4001 as the chip
will
at X2If the instruction
data bus at X2 -~2 will
be
the
of
one
and
CM-ROM
(one
8Witcbing)
bank
the
the
receive
to
4001
I/O
an
perform
n\DDber code
l...t
at
(DCL)
line"
portion
OPA
Instructions
character
~RAKo
the
information
operation.
instructions
at
data
4002,
Whenthe CPU
applied
(RAM
out of four
SRC.
the
and
register
the
and
to
chip
was
I/O
CM-RAK
the
couaand
the
4-bit
to
The
4002'8
the
of
mode
one
only
SRC
terpreted
selection
Only one
the
RESET
-RAM
and
I/O
of
matches
prior
time.
that
with
RAM
and
1/0
I/O
line
bus
the
4001'8
the
of
nate
transfer
activate
will
with
"designate
and
4001'8
tion
I/O
the
instruction.
2.
will
In
1.
CM-RAM
RDR
of
code
a
when
CPU
during
address
8-bit
an
receive
will
4001
the
operation
of
mode
ROM
the
In
The 4001 performs tWo
functions:
stores
256 x 8 words of program or data table.;
as a vehicle of communication
with peripheral
devices it i. provided with 4 I/O pins and associated
control
logic
to perform input and output operations.
(The block diagraa is shown
in Figure 5.)
it
ROM
a
As
distinct
and
basic
PORT
I/O
BIT
4
AND
ROM
PROGRAMMABLE
MASK
8
x
256
-
executed
is
DCL
IV.
4001
provided
X2
at
m
~
allCNed
it.
of
later
After
instruction.
8pecifying
which 1/0 operation
should
be performed;
There are
15 different
operations
pos8ible.
The only ones affecting
the
4001 operation
are RDR - read ROM port,
and WRR - write
ROM port.
received
waa WRR. the data pre8ent
on
latched
on the output
flip-flop8
associated
liMa.
at any given
of system instruc-
~
dynamic
mode
of
operation
~nd
is
divided
into
two
cells each.
Multiplexing
is needed for both
and data to data bus output buffer
operations.
blocks
of
address
16
x
to address
a
has
array
ROM
The
4001.
the
of
organization
block
shows
the
5
Figure
64
register
~e HTC flip-~lop
controls
the outputting
of data.
It is set at A3'
(see Figure
2). if CM-ROM and CSE (chip
select)
are "1".
CSE is a single
4-input
AND gate of the 4 data bus lines,
using
Di or 151 according
to
the chip number that
the user wants to assign
to the chip.
This
is accomplished
by metal
mask option.
TIMING
control
generates
all
internal
timing
silnals
using
SYNC. ~l and G2.
A RESET(l)
flip-flops
and
The output
usine
~R
r-
will
flip-flops
external
for
inhibit
data
X2' (see
input
or
for
signal
Figure
output
2),
and
operation.
the ROM and
will
clear
I/O
all
static
out.
associated
with
I/O
pins
can
a180 be
CL pin.
the start-u?
of the system.
. 1- r
MlFFEAI
I
Ct»ITROL
~~
110
..,
t--
CKmUT
DATA
!4L-.
IK
,.
~~
Fi~r. 5. 4001ROMBlockDi..m
19
CLQ8T
~
~
~
'--
M~
~FEM
IWVT
I
an
i~ed
~'ARTIAL
-(l~T
is set by CM-ROM and CSE at
control
logic
for a following
cleared
The SRC flip-flop
presets
the I/O
Of
0,
o.
Da
f.
instruction.
20
88 the
the I/O
ac-
execution
"DCL"
a
of
main
diagram
the
for
associated
stores
X2
index
and
lines
output
(16
at
line
block
the
(0 through
3) as well
by the OPA portion
of
DCL
(The
designated
the
of
each
CM-RAM
CM-RAM
one
4
with
As a RAIl it
next
to
in
below:
content
as follows:
of
the
During
DO
01
activate
in 4 registers
of twenty 4-bit
characters
and
4 status characters).
As a vehicle
the
to
Prior
No.
Ch8f8ct8r
shown
the
operations.
stored
receiving
161
02
~~~;~~~
th,~
M8mory
-
been
instruction.
after
CO
will
provided
two
functions.
with
starting
has
as
is
accumulato~
I
03
out
In the RAM mode. the operation
CPU
M8In
and
X3
send
will
output
instruction.)
location
selected
code
command line)
is
the
selected
RAM
and
it
it
the
by
interpreted
is
X2
7).
perform
LDM
an
character
on it are
from
~
Do
X3
performs
4002
The
distinct
selected
~°No.1
~RAM
No.
I ::='-
3)
ChipNo.
RIgis18I'
°3 °2
through
devices,
then
through
31
10
(1)
is
accomplished
previously
desired
(designate
to
transferred
during
peripheral
bank
the
The status
performed
and
Figure
in
shown
lo~ic
is
10 rhro.q.
is
instruction
SRC
an
control
example
pair
register
with
X2
the
at
data
~1e
chRracters
RAM
.~
arranged
code
switching
Bank
PORT
OUTPUT
BIT
4
AND
RAM
BIT
320
4002
The
(for
instruction
DCL
v.
~RAM
cumulator
(1)
the
appendix.
the
is
table
this
of
copy
A
Intel.
upon
available
is
table
truth
customer
blank
A
256
register.
from
request
the
of
stored-'ineach
be
to
pattern
ROM
3.
pin
1/0
each
for
options
metal
the
All
2.
number
Chip
1.
specified:
be
must
tion
1/0
in
shown
each
for
options
available
the
shows
6
Figure
VSS.
or
VDD
either
to
connected
resistor
chip
uniquely
be
can
ROM
each
on
pin
1/0
Each
ROM Options and Ordenn! the ROM
chosento be either an input or output line
by metal option. Also eachinput or output
can either be inverted or direct. Whenthe
pin is chosenasan input it may havean on.
When ordering a 4001 the following informapin.
locations.
320 bits
communication
memory
is
When the CPU receives
bank.
-
operation
to be
and RAM instructions.
.,
The chip
number is
assigned
4002-1
selection.
chip
optiona,
for
two metal
available
in
also
is
available
PO.
pin.
the 4002 is
external
An
selection.
4002-2.
and
For chip
as follows:
~ICHAAGI
MIMORY
~
CI~
~
ITATW
~EGI8TIR
~R
~ACTER
X.ADOAE8
TIMING
M~Y
,..-:
CHARACTER
'-J
STAT\8
.
MAIN
.I~Y
~R
0UTP\n
M~Y
RAMAIC
MAIN
..,...CELLS
H
Y~IGI8TIR
Mo--'"
~O--
!~
t
MUioTIPLExaR
I~
~EF~IIM
~IFIEM
~IR
CX*T~
REFRE8f
...«If.
.
v.
--0
--0
~
o~
'UP"L~
~
.
J
RI8T
--0
"1
0.
1
0.
1
0,
l'
0,
Fi.,re 7. 4002RAMBlockDi...m
The twenty
4-bit
characters
Four
registers
the
are arranged as
constitute
memry.
21
the
Four 16-
in8truction:
I/O
an
of
SRC
instruction:
the !'main" .mory
OPA
an
the
by
con8titute
addressable
4-character
by
addressable
registers
characters
4
2.
16 characters
character
the
only
for
D3J
ready
D2be
on
X2
will
at
state
data
Po
and
for each 4002 register
follCNs:
1.
was
follows.
option
of
4002~8 that an SRCinstruction
combination
that
metal
given
a
proper
For
the
operation
RAM
with
or
I/O
chip
received.
Presence
of ~RAM during X2 tells
"status
character"
~
Two separate
X decoders
switch
between
main
and status
characcer
(lOR)
if
operations
determine
Buff...
Enebled
Output
following
Bus
the
0 for
0..
in
4002Del. BI8 Dutput
8&8 Output
CPU
4002's
the
the
CPU,
for
the
time
will
lOR, DJ.
IIIc).
88 shown
8uff.EMbled
Op.
in
'
into
is
1 for
Section
En-..
~
state
action
4001 0-.
1100..
~
divided
the
Shown below
x
WRM
11O0P8W.
a write.
DJ.
Set, shown in
will
which
Buff..
instruction
4m2
I
I/O
RAM
I ~.,
-..
I
ADM
S8M
WA3
WR2
WA'
WAf
.
ADA
.
~
.
.
~
.
.
will
decode
the
4002 Chip (by
after
M2).
at
SRC),
activated
(CM-RAM
instruction
the selected
1/0
an
of
OPA
the
1/0 mode of operation.
receiving
In the
instruction.
will
RESET
me~
the
scan
(256 clock
inhibited
to
are
counter
cycles
buffers
ou~put
refresh
and
memory.
the
flip-flops
clear
completely
bus
chiP.
the
to
applied
when
-
data
the
static
32 instruction
leaat
internal
at
the
and control
To
array.
RAK
allow
for
the content of either
ter into the decoder.
22
counter
portion
RAM
and'the
of the sysloading
array
be periodically
ailows
memory
The
4002.
the
of
address
An
the refresh
must
an idle
multiplexer
during
the
it
scans
therefore
refreshed
M2).
is
and
cell.
counter
refresh
A
content
(HI
cycle
organization
block
the
shows
7
URes a dynamic
memory
tem
output
condition).
Figure
(floating
array
all
RESET
During
ory.
to
be applied
periods)
must
of
the
a clear
clear
will
cause
RESET
-
If the instruction
is WMP. the data present on the data bus during
x2.82
will
set the outpu~ flip-flops
aasociated
with the 1/0
pins.
That information
will
be available
until
next WMPfor
peripheral
devices control.
An external
signal
refreshed.
r
~
11.cr.
I
For each
table:
or
instruction),
to be performed.
and RAM operations.
The
are
(lOW).
operations
RAM
and
operations
I/O
Write
The
and
the operation
is a read
lOW (see Basic
Instruction
by
the
~
of
Read
part
M2
received
is
(2nd
during
line
instruction
OPA
DJ
the
CH-RAM
RAM
or
receive
specify
the I/O or RAM operation
is a list
of the 15 possible
I/O
of
to
one
I/O
an
activate
will
When
memories.
or the address
regis-
selection
chip
flip-flop,
SRC
an
of
composed
is
control
RAM
The
.
the
of
loading
the
and
operations,
read/write
REGISTER
SHIFT
SERIAL.IN/PARALLEL.OUT.
4003 1o-BIT
The 4003 is a 10-bit
serial-in,
parallel-out,
serial-out
register
with
enable
logic.
The 4003 is used to expand
of ROM and RAM I/O ports
to communicate
with
peripheral
such
as
keyboards,
printers,
displays,
readers,
shift
the number
devices
teletypewriters,
etc.
Data is loaded
serially
and is available
in parallel
on 10 output
line.
which are accessed
throuah
enable
logic.
When enabled
(E - low),
the shift
register
contents
i8 read out;
when not enabled
(E - high),
the parallel-out
lines
are at VSS.
The serial-out
line
is not affected
by the enable
logic.
the
application
of
the
supply
number
voltage
and the
register
VSS)
.
internal
shift
An
the
the
by
together
clear
will
controlled
is
circuit
shifting
data
The
power-on-clear
between
an indefin~te
to provide
permitting
(Qi
serially
signal.
available
register
also
CP
is
shift
Data
of similar
device8
to be cascaded
length
multiples
of 10.
first
CP sig-
nal.
The 4003 output
buffer8
are push-pull
ratio
type,
useful
for multiple
key .depre88ion
rejection
when a 4003 is used in conjunction
with
a keyboard.
In thi8
mode if
up to
three
output
lines
are connected
together,
the state
of the output
Is high
(Logic
"0")
if at lea~t
one
1i!!.e
18 high.
internally
Fig.
delayed.
8 show8 the block
organization
of
the
4003.
_RIA&.
our
~
--LAY ~
F~r.
8.4003 Shift Register Block Di8gram
23
the
is
CP
Data-in
however,
msec.
10
condition8,
to
race
avoid
To
register;
limited
shift
i8
static
width
simultaneous.
be
can
phase
ID8Xim\D
a single
(cp)
is
pulse
CP
clock
The 4003
and
VI.
flip-flops.
SERIAL-OUT
output
RAM
the
buffers,
loaic,
an instruction
register,
instruction
decoder and I/O controllogic.
This block controls
the loading of the addres8
register,
the status
and main memory decoder switching,
the generation
of memory timing,
the enable of the data bus input-output
VII. THE 4008/4009 IN AN MCS-4SYSTEM
The standardmemoryand I/O interf-=eset (4008/4()(m)
provides
the
complete
control
functions
performed
by
the 4001 in MCS-4systems. The 4008/4009are com-
ory,
input
4004
the
MCS-4
mem-
program
decoders
of
the
TTL
control
of
words
4k
to
interface
four-bit
of
seYeral
under
members
and
still
is
other
4008/4009
activity
sixteen
output
with
of
to
set
One
$ufficient
is
CPU.
All
compatible
family.
pletely
ports and sixteen
four-bit
ports.
It should be noted that in any MCS-4 system the pro-
""am memoryis distinct from the re.t/write data st~
this
eight
data
but
in
read/write
memory,
can now
organized
be
will
4002
RAM
programs
the
from
from
memory
distinct
executed
the 4008/4009,
program
RAM
storage.
is
and
Using
memory
stored
RAM).
RAM
be
(4002
and
ROM,
PROM,
of
memory.
program
combination
as
to
Any
referred
4001.
be
the
will
RAM
inside
bit words am 256 word pages,just like the memory 8Tay
The ~companyingdiagramsshow the internal organiz.
tion
of both
4008 and 4009.
the
chip
number
(also referred
used
bit
and
1
num-
chip
A
eight
RAMs
the
and
during
to as page number)
bit
is
four
the
address
and
program
7
bit
A
eight
ROM
the
CPU
the
latches
ROMs
The
latches
it
by
4008
PROMs,
4004.
throu~
the
time
A3
out
The
standard
..,t
from
then presented at pins
AO
ber
During
address
memory.
to
4004
program
time.
A2
prO'#'~
for
the
The 4008 is the address latch chip which interfaces
is pre.nt.
ed at pins COthrou~ C3. Thesefour bits must be deand one page of program memory
is
1
M
activates
at
from
time
a
at
CPU
bits
by
four
bit instruction
~t
4004
sipl
the
to
command
memory
The
M2.
and
program
The 4CX» then transfers the ei~t
the
coded externally
.Iected.
the 4009 and initiates this tr.,sfer.
Whenthe CPUexecutesan SRC(SendRegisterControl)
instruction,
the 4O(m responds by storing the 110 address
in its eight bit SRC register. The content of this SRC
the chip .Iect lines (COthrou~ C3)
"by
he
I/O
~ppropria~
he
time.
1
X
chip
.Iect
POr!..!.s
lines.
The
the~~ted
IN
and
OUT
lines
of the 4009 indicate whether an input or output oper.
de-
9)
(pin
R
strobe
data
WR
bus
I/O
I/O
a
the
output
.,
output
interprets
from
en8bles
transfers
.oos
Port)
tr.,ster
ROM
I/O
strobe
(Read
RDR
and
(pin 10) to enable the .lected
and
bus
it
4CX»
data
It aim
input
port.
the
the
When
I/O
the
input
an
8nd
an
instruction
an
will
4009
transfer
input
instruction,
bus.
Port)
CPU
ROM
data
executes
primarily
.Iected
to
the
buffers
the
the
(Write
to
input
to enable
from
CPU
the
the
is
4CX»
When
instruction,
vice.
The
tion will occur.
to
-!
at
to the address lines
(AO
register is always transferred
~5iJd
output port.
24
memory.
RAM
progr~
in
RAM
stored
the
be
to
into
is
data
write
inStruCtion
to
an
When
4008/4009
the
with
111000111.
-
conjunction
Memory
in
used
Program
now
is
(Write
WPM
instruction
~11ed
is
undefined
instruction
formerly
new
This
A
..
system
the
In
instruction.
WPM
"1111".
the
by
with
jammed
activated
are
also
is
4~
the
memory,
the
the
on
for
high
A
generated
be
executed.
can
is
WPM
strobes
write
~nd
the
every
F/l,
when
and
becomesthe addressof the RAMword being
low
line,
W
pulses
the
then
It
lines,
select
on.
chip
comes
the
power
decoding
when
high
initially
is
appropriately
By
line
F/L
The
written.
The previously.lected SRCaddresson line AOthroughA7 of the 4~
4008
of
the
lines
line"on
select
W
chip
The
the
channel.
instruction,
RAM
WPM
the
a
as
executes
designated
CPU
be
the
When
should
this
design
written.
programmemory,it is written in two four.bit segments.The F/L signalfrom the 4008 keepstrackof which half is being
and a low means that the last four bits are being written. The 4009
transfersthe segmentof the instruction to the I/O busat X2 of the WPMinstruction. The SRCaddresssentto RAM is only
8 bits. Whenmore than one pageof RAM (256 bytes)is beingwritten, an output port mustbe usedto supplyadditional
F/L line means that, the first four bits are being written,
address lines for higher order addr~.
"1111"
the
AO
lines
four
on
to
forced
loaded
on
out
be
available
are
.nt
is
can
is
4008
the
of
address
memory
-=cumulator
lines
the
SAC
prQ9'am
of
select
content
previous
AAM
the
4008.
of
The
X2.
and
at
bus
time
time.
a
A7
at
110
X1
at
bits
through
4009
of
~
of
1/0,1/00
Co
C3C2C,
""'1/031/~
ACC
1111
4009
11100011
OPA:
OPA
Symbolic:
chip
Instruction
The
Memory
Description:
Propam
WPM
of Write
Mnemonic:
Definition
SAC Address --- Ao - A7 of 4008
System
Illustrations
Using
the 4008
8Id
4009
Four systems are shown where the MCS-4 components are used with standard Intel memory elements as the program memory.
Notice that severaldifferent approachesto chip .Iect. port decoding, and the 110 elements are shown.
Four
PtN'1a.
110
Four
PROM..,d
17O2A
Four
1:
Ex.",p'1702AI are u8d for program Itorage and four four.bit I/O ports
are used. In this caR D.type output latches are used and a one of eight decoder (3205) Is u8d to decode both the input and
output strobes. Note that the I/O bul is buffered from the outpJtI. Buffen are neededonly when the current sinking requi~
menton the busexceeds1.6mA. In smallsystemslow powerTTL could be usedand bufferscould be avoided.
~xample
2:
Memoryfor Pro,amSror..
ReadtWrir.
program
dewloped.
normal
for
be
could
4008
the
bit)
1
from
x
words
selects
(1k
chip
2102
the
of
the
Ports.
using
decoding
the
I/O
system
with
similar
.,d..,."
A
gated
also
shown.
block,
is
RAM
bit)
They.e
1
x
one
PROMs,
words
instruction.
17O2A
1256
WPM
a
1101
Se.."
The
executing
3:
Ex~p"
execution.
.when
This exampleshowsonly the RAM portion of a systemwhen RAM is usedfor programmemory. Note that the chip selects
aretied t~ther in ,#,oupsof four. The chip alects aregatedwith the F/L control line for writing only four bits at a time
This exampleusesa singleP9 of RAM programmemoryshownin Example2 in a completesystem. In this casethe input
ports .e 8: 1 muhipiexeswhich are bufferedfrom the I/O bul by a quadthreestatebuffer. The input port sefectionis then
the function of the multiplexers. The outpl.it ports are Intel 3404 latches and the port selection is done using an Intel
3205 decoder.
Ex8nple
in
-
for
used
I/O port alection rather than decoders - shown in previous ex.nples. In this caseall input portS are three state buffers.
IMPORTANT:
., MCS..fIYIMm urillf 4001~
the 4001 In t8r1nSof negetiw logic ~
nIenIOrY.nd . 'Y"""
uI/"f 4«1B/4/D P'o,¥II /rI8mOI'Y.
d..
Mcs.4
The
fa'
pr~.1tIouIcI
4(D.
logic.
prc.-8nI_"-1rI.t
the
potitiw
to
with
Notethet
used
respect
memory
with
NNNNI.
prQ9'lm
defin.t
...
in
NNNN
-
r8JIt,
4(D
~
AI.
CDX)CDX)
-
HOP
(i...,
logic.
4008
with ~/4009.
both
from
~
neg8tiw
'-I
"0"
to
mntrollmer
In the ..,.
with
Ind
~..
defi-
I/O~.
'-I
...
d_,
4004
hl~
-
the
memory
"1"
from
MId~,
comrolll~
M-V
co-.wlttliogic
be
8wJ
2.
be ~
~
,.;. .xilt be~
,. FM normeloper8tbt, 4001 }tOMs--'
-low
Thefollowi", dlff
th8t NOP- CDX)CDX)- pppp PPPP.C8r8fullycheckall tapes.,bmittad fM metalm"
ROMI to be
25
4001
.
.Ii'"
only
~
syItam.
prototyping
fM
may
line
4008/4(8
u*
I/O
the
88d\
4001
the
with
devi~
interf-
conlistant
On
The
functioN.
U-S.
b8inI
il
4CXI8/4008.
-
line
CM
irwtNctlon
distinctly d~t
WPM
--
the
the
~
They ~orm
to
4Ca/4008
connectad
40021
fa'
dataltor..
~
il
of. DCL b8f\8V818Xactly
like CM-ROM.
by
(WRMI
CM-ROM
~
M-V
Writ.
-.
GJ2I
control
to
be
u8t
interpretad
II
--'
Inl1ructlon
WPM
CM-RAMO
the
~
th8t
Is
~
CM.RAMoin ~
t'-
defin.t
If
c8P8bitity.
40011...
OUtput
the
poIitiV8logic.
~
fM
of
input
ports
-both
I/O
in
with
the
d8fiIi,.
th.t
is
~
be.,..
~
to
1/0
can
tMIn
4«»
4009
the
~tIMIf.
or
i"tlUt
with
be
the
from
d8t8
c.-eltlould
~tPlt
_i818d
811'-
~
m8n1a'Y,
I"""t""
I/O
An
- . .,bltitut. for the 4002 mdt-it.
CM-ROM
5. The RAM prc.-.m memorycannotbe u*
8.
function,
4.
Pl'C9'8n
3.
-- th8tthecorrKtlogicdetklltl- - u8t.
II
This
properly
function.
elements...
_Iection
by
organized
be
C8\
generated
this
logic
TTL
to
is
block
block
RAM
RAM
basic
dedicated
standard
is
each
EKh
eight
example
this
In
port
for
RAM.
(WCS)
in
written.
Output
select
bytes
chip
2k
m
being
is
alection.
write
ROM
P9
the
in
u~.
memory
for
is
bytes
2k
RAM
prO9'am
decoding
of
with
RAM
special
block
the
with
one
~ized
15
when
.I~t
than
memory
more
necessary
chip
When
only
gating
2.
Pro".8m
Example4: EifIJt 1702APROM" eigflt RAM Slocks,."d eilht I/O Ports.
Eump'-
2. Re./Write MemofY for Pro.--"'
26
Po.1I
1/0
Four
-
1102As
Four
1.
Eumple
,
Stor.
Eumple 3. PrOW8mMemorywith SevenP8g8tof PROM8nd One p.
of RAM
27
Example4. Pro".m Memorywith Ei9ht P8geS
of PROM.rId Eight P.~s of RAM
Instruction
As previously
of instruction.
discussed,
MCS-4
the MCS-4 micro computer set has two types
1 word instruction
10.8 psec.
with
b)
2 word instruction
with.
an 8-bit
time
code and an execution
time of
16-bit
code and an execution
of
pa8C.
called
is
code
of the system, the 8-bit
inon two successive
clock periods.
4-bit
CPR,
operation
at a time
called
i.
code
4-bit
first
Due to the time multiplexed
struction
18 fetChed 4-bit.
second
21.6
a)
The
THE
OF
Format
the
A.
REPERTOIRE
DETAILED
CPA.
The instruction
formats were illustrated
in Tables
I and II
and Abbreviations
The following
SyDbol8 and abbreviations
next few sections:
be used thorughout
the
(4-bit)
(4-bit)
(4-bit)
(4-bit)
Field
Field
addres8
counter
counter
pair
addres8
Register
Flip-Flop
ter
prosram
program
register
command
the
T
i
at
content
bus
character
location
of
content
character
i
main
statua
RAM
Stack
Data
(T)
RAM
M
Order
High order progr..
counter Field
(4-bit)
Order i content of the accumulator
CHi
PH
ai
order
order
regia
regi8ter
Buffer
/link
Carry
Accumulator
Index
Index
Low
Middle
~
~
RRR
RRRR
ACBR
CY
Accumulator
the content of
i8 transferred
to
ACC
( )
will
time
Symbols
~i
B.
DI
VIII.
INSTRUCTION
.~~
The 3 register8
in the address
the program
counter.
register
other
than
Throughout the text "pase" _ana a block. of 256 instructions
whose addre8s differs
only on the most 8ignificant
4 bits
(all of the instructiona on one page are all stored in one ROM).
Example: page 7 means all
locations
having addresses between
0111 0000 0000 and 0111 1111 1111
28
.
..:'~
c.
Format for Describing Each Instruction
Each iD8truct100
v111
cod.
0000 0000
Moc, ..,Uc81.
orA:
S,.oUc:
nec..aery)
Operation)
(No
Instructions
NOP
on
iD8tractiOD
(if n.ce..ery)
(if
excapt1oD8
OPA
aDd/or
OP"
Mad1ine
!t1_ic:
One Word
follow.:
_d --in.
S,.olic
repr..eotatiOD
of the
Deacript100
of the iD8truCtiOD
~le
_d
..
(3)
(4)
(5)
D.
."01
de.cr1b.d
(2)
(1) ~_ic
b.
D88cri,c,I_a .. ...~18
,.I'f.~.
MD88ODie: L~ (LoadDatato AeCU8lator)
of
The
fielcl
OPA
the
ae~tor.
iD
to
The
DB
1010
OPAl
ne8criptiOD:
The
4bi~
XCH (bch-.e
1011IDa
(l.1l.I.)
the
of
IlDaffected.
CODt8Dt
CODt8Dt8
reliater
indaz
prerlo.bit
are
4
bit
The
The
da8iaaated
tbe
carry/11IIk
cd
acc\8lator)
ACC. (ACBR)~
IDa
with
carry)
Cf
(Cf)
+
(ACC)
+
(DII.)
ne.criptioo:
acc~ator
ACC,
to
1000UI.I.
Sy8olic:
OPI.OPA:
rep.ter
ADD
*_ic:
iDdu
The 4 bit coat8Dt of the d..ilD&ted
ind.. re.18ter
18
lo8d8d into the ac~ator.
The prior coat_t
of the
ac~ator
18 loaded into the de.ilDated
re.18ter.
The
carry/liDk
bit 18 UDaffected.
(Add
Deacriptioa:
index re.18ter
ACU. (1Da>--
(ACC>-
S,-ol1c:
OPAl
loet.
ac~~or.
the
ad
are
the
coot8Dt
into
reliater
accU8Ulator
loedecl
the
18
of
indaz
MD_icl
of
(DB)--ACC
S,.olic:
~
OPI.
HD88ODic:
LD(L084
indez
re.i8ter
opa
the
atorecl
iDto
loaclecl
DODD
data.
e-teDt.
of the aeCU8lator are loat.
bit 18 unaffeetecl.
AccU8Ulator)
previ0U8
eury/liDk
are
vorcl
iD8trueti~
bit.
The 4
Deeeripti_:
of
.-.
ACC
DDOO
1101
DODD
OPAl
S,.olie:
on
The 4 bit coot8Dt of the de.ilDated
iDdcz rel18ter
i.
ad4ed to the ~teat
of the 8C~ator
with carry.
The re.lIlt
18 .tored iD the ac~ator.
The carry/liDk
i. .et to 1 if a .ua ar..ter th8D 1S10... leDerated to
affected.
'"
(ACC)
(cr)
(DU)
Aua~
~
~l.:
a3 a2 al ao
StD(
~
-
ro
~
rl
81
r2
82
r)
83
L~~
C4
-
CADI
+)
I
co +-_J
29
UD-
ia .et
18
reliater
the carry/liDk
iDdcz
the
ot.he~e,
of
coateat
out;
bit
4
a carry
The
O.
to
iDclicate
.
HD88DDic:
5lnI
(Subtract
on
1001
iDdex rea18ter
fro.
acCU8Ulator
with
borr~)
DescriptiOD:
4 bit
The
content
CY
ACC,
-
('ct")
+
(IDK)
+
lID
(ACC)
Sy8o1ic:
orA:
of the de8ilnated
iDdex relister
is
iD
stored
bit
4
carry
18
The
1.
to
the
r..u1t
the
geDerated,
set
18
unaffected.
18
rea18ter
it
18
_d
bo~
borr~
a
with
If
othervi.e,
0;
1Dd8z
to
the
ac~tor
ac~tor.
(cr)
~
"'u1t
'
4-
"io
eo
81
--
82
(ACC)
,-
un
ac~tor)
the
to
data
1084
8Dcl
back
(Brach
DODD
88L
(UD)
+1 -.DD.
The 4 bit coateDt of the deailD&ted indez reai8ter
i.
inCr888Dted by 1. The index rea1eter i. .et to .ero
in c..e of overflow.
The cerry/ltDk
18 unaffected.
1100
orA:
1D4ex resister)
(InCr888Dt
0110
OrA:
OPI.
S}8Iolic:
DeacriptiOD:
~c:
rl
al~
(ACC)
a3f2
r2
r3
+)
83
~
..
Io~
(Cf)
INN:
MDe.onic:
on
Subtr8bend
(RID.)
HiD_d
~l.:
of
set
i8
the
coatCDt
bit
the
cO8ple8ented(on.. ca8pl888Dt)8Ddaddedto CODtCDt
of
iD8tructi_.
(J1tS)
ACC
~
.ubroutiD8
DODD
to
PH;
j~
lut
the
foUov1Dl
~-
(Stack)---J
The proarCO18ter(addr...
.tack)18 pU8bed dOIfD _e
level.
Proar"
c_trol
tr8D8fer.
to the D8Kt iD.tructiOD
Pt-
S,.bolic:
Deacr1pti_:
'L;
De8criptiaa:
Tbe
_cb-.ecI
PM
PH
-.
8 bit caoteot of the d88i8Beteci 1DdcKrea18ter pair
1D8truCtiOD
18 loceted.
rel18ter
18 lmaffectecl.
indcK
reai8tu
(u..Q)
1.
(KIlO)
1)
+
(Pa
iD8trvctiOD
Jm
1.
the
addr...
where
Dazt
p...
(PH)
(01.1)
~t.rol)
(Xv
(%y
DB
DB
(1Dl)-.
The 8 bit. ~t.-t.
of t.be deei.-t.ed
iAdez re&i8t.er
pair
will
UK
t.be
of
operat.i-
I/O
or
vr1t.e.
reacl.
subseq-t.
is S8Dt.t.o t.be lAM addressrelist.er at. X2 and X3' A
ut.1l1.e t.b18 address.
Specifically,
t.be f1rat. 2 b1t.s of
t.be address dee1lDat.e a aAH chip; t.be secODd 2 bit.a d..il-
.
rit.biA
des1.-t.e
ch-act.ar8
t.o
used
-1'1
8180
~
18
4-bit.
16
c~d
of
Th18
out.
1
re.18t.er.
t.ba
deai.-t.e
nat.e 1 out. of 4 reliet.era wit.biA t.be chip; t.be laat. 4 bit.a
iD8t.ruCt.iOD 18 uecut.ed.
reli8t.er
is _affected.
30
s.c
nest.
t.be
_t.i1
cleared
not.
18
UK
or
~
iA
addr..s
sUbseq~t
ROM
for a
ROMI/O port. op.rat.~_. The firat.
4 bit.a dee1.-t.e f.h8 ROM
chip n,.ar t.o be s8lect.ed. The
The 8 bit. CODt_t. of the, iAdex
JIB
the
where
(.-
p...
I(J()
the
IDl
0010
the
.i.,
the
Dot
(010)-.-
OPA:
CODteDt of
(Pa) 1111 1111 proto the D8Zt pq8 in nq_ce
tr..ferred
That
_d
SAC (Send
Syllbolic:
on
t.
to
Dot
locat.d.
_d
_trol
(1Dl)
Descript.i_:
The 8 bit
of the proar"
to the 1D8true-
WbeoJIB t. located at the addr...
ar-
__ic:
.-
the
~
addra.
thet
at
tiaa
i8 loedad into the low order 8 po.iti0D8
COIater.
hoar~trol
18 treafea-
1IC8P'rtC8:
proar...
~
accU8Ulator.
to
tha
to
81IbrwtiD8
loaded
f~
are
retum
1D~ct)
to
iDatruct1U8ed
(010)
-.
ID1
(J~
18
the
JIN
0011
Sy8Iolic:
(.u.l)
OPA:
on.
~ic:
IBL
of
The 4 b1t8 of data DODD
.tored iD tb8 CWA
porti-
~
om
0011
orA:
~..,
->
f~
1D41rect
(I'etcb
FIN
~c:
on.
The 8 bit
(0001) --.
10M addre..
~
D88criptioa:
-
(Pa) (0000)
(On.)
SY8bolicl
(OlA)--91U1
coateDt
of
the
0 index
rel18ter
pair
(0000)
in~
d88ilDated
the
into
loaded
u
locati~
that
at
(0001) i. .eDt out .. 8D addre.. in the
paae
where the FII 1D8tructioa i. located. The 8 bit word
relute~ pair. Theproar" COUDte~
18 uaaffected;after
FII b.. beeD executed the next in.truction
in .equence
vi1l be addr...ed.
The conteDt of the 0 indez reli.ter
pair i. UDalteredUDl... indez re.uter
FII 1a a 1-word ~truct1OD.
ita
two ..-ory
cycle. (21.6 paec).
ezecut1oa
and
18
.equence
in
inetruct1oc
FIR
(1mI)
the
pqe
Dezt
(Pa) 1111 1111 4ata
wh.re
pa..
the
f~
Dot
at a4dre..
the
Wb8a FIB 18 located
f~
b)
fetched
Althouih
requ1r..
be
a)
(ao.o
:
will
UClPrII-.
0 v.. d..ignated
(0001).
(0000)
(Pa)
DOt
and
Instruction
Mdine
Two
E.
Word
(0001)
loc.ted. That18. Dezt addre.. 1. (PH+ 1) (0000)
Pg
AJ"""
AJ
AJ
AJ
-+PK.
A2
A2
A2
A2
--+Pt.
Al
Al
SubroutiDe)
AI-
~o
Al
(JU8p
JMS
~88ODic:
Al
Prolr.. control i. UDcoaditioaally traD8f.rred to the
1D8truction locater .t the addu.. AJ AJ AJ AJ. A2 A2 A2 A2.
Al
Deacription:
Al
Al
S,.ol1c:
HD88ODic:
JUN (JU8p unconditional)
l.t word on OPAl 0100 AJ AJ AJ AJ
2nd word on OPA: A2 A2 A2 A2 Al Al Al Al
18~ word OpROPA: 0101 A] A] A] A]
2Dd word OpROPA: A2 A2 A2 A2 Al Al Al
SY8bolic:
(PH.
PM. Pt + 2~Stack
Al Al Al Al - PL. A2 A2 A2 A2 -.
A3 A3 A3 A] -+ PI
8.-4
prolr..
the
~e
therefore.
will
8tack.
(IlL)
the
of
out
1D8tructlp~ed
nt1lZD
be
a
~o
addre88
of
'nIe eddrea8 of the next. 1D8truc~iiD 8equence foll~iDa
JNB (r8turD addr888) i8 88Ved iD the puah do.n st8ck.
P1'OI1'- control 18 traaferred
to the 1D8tructilocated
at the 12 bit eddr"8
(AJAJA~JA2A2A~IA1A1AV.
EaaCDti-
D88crlp~i_:
PM.
c_trol
18 tr_ferred
to the nest 8~t1al
1D8t1'UctiOD
after the l..t
JNB.
'nIe p.-h do.n 8tack h.. 4 rel18ten.
One of th18 \8ec1
.. the P1'Ol1'- COUD~er.therefore n..tiDa
Stack
~
--. JIG 11
-a.
recelY8d
hoar-
Co1mt..r
I.. t.1IZB
-.rStack
Stack
IPr°lrJ1tI 13
received
, "tuzn addr... '1
"tun 8ddr... ,.
.nm,.
nee1v-'
Ilatum
addr...
..,
18t:UZD8ddr...
12
rroar'rb8 --_to
-+
IlL
received
Co8tu
r8toUrft
add.-.f. t_..
31
-
lletum
8ddr...
12
I latum 8cldr... , 1
Stack
-.
~
-.
Ilat.1lZB
COImtu
C_ter
1~
I Proir-
#2
-.
~
"cd'"
lat:ara
JIm 12
I
-+
,1
13
RoJ18
nce1.-d
of JHS CaDoccur
3 1.-18.
Suck
~:
up to
-.
Caliit1CXi&l)
(J~
.K:N
*_1c:
AIAIAIAI -. PL'
if
CICZC3C4
PM
--.
A2AZA2AZ
t~,
CICZC3C4
If
Sy8bolic:
1.
AZAZA2A2
l.t word ora OPA:0001 CICZC3C4
2nd word opa OPAl
AIAIAIAl
PH unch8Dled
1.
f&18e,
(Pa) -t PH, ('K) -+ PM' (PL + Z)-. PL
the
duilDated cODAi1ti~ code 1. true,
proar-
1.
at
De.criptiOD:
If
tr~ferTed
to
the
ia8truct1~
locate'
addre.. AZAZAZAZ'
AIAIAIAl ODthe
~tzo1
the
8 bit
PAle(ROM)whereJC8i.
located.
fo11-.:
..
...iped
are
b1t8
~d1t1~
The
If the CODd1t1~18 Dot true the nest ia8truct1~ in
.eqU8Dceafter JCN18 ezecuted.
aero
1.
c~t_t
c~d1tiOD
ac~tor
the
ju.p
if
Invert
1
.
Ju.p
1
.
Cl
Cz
Cl . 0 DoDot invert jU8p c~dit1OD
9!.!.
~
~le:
C3 . 1 JU8p1f the carry'link CODteDt1. 1
C4 . 1 Ju.p if te.t .1IDal (pin 10 OD4004) 1. zero.
0001
0110
Ju.p 1f accU8Ulator
1. zero or carry
. 1
S...r~
cond1t10ft8
CaDbe tested e18ut8De0u81y.
The loaJ.c
equat1OD
jU8p
18 1198 belaw:
ducr1b1a,
the
coodit1OD
for
a
HD88Inic:
ISZ
Sy8bol1c:
{bIIJ
(Iocr_at.
indo
rep.t.er
lat. word on OPAl0111 lIaR
2ac1word on CWA:A.,~~
~~A,A,
C4)
.
m!
+
prolr-
addr...
.kip
if
on the next
.8ro)
+ 1 -'11111. if r..ult. . 0
A2A2A2A2..,.PM.
2) -. PLI
PH.
(Pa)
(PM)--. PH. (~+
0
~
t.
1'88ul
(PH)-. PH.
if
true.
18
coDditi-
the
and
control 18 traaaferred
to the 8-bit
PAle where Ja 18 located.
AlAlAlAl-t
PL
18 tr8D8fe1'1'ed
to
the
iDat.ructioa
locat.ed
acldre.. A,zAzA,zA,2.
AlAlAlAl oa the .--
cciDt.rol
pr°81'-
O.
fr~
differ_t.
18
r..ult.
the
If
The coat.eat. of t.he cleai.-r.ed
iDcIa re.18t.er 18 iDcr_t.ed
by 1. The accU8Ulat.or 804 carry/liDk
are unaffect.ed.
If t.he re.ult. i8 .ero. the next. 1D8t.1'\Ictioa aft.er ISZ i.
--cut
Deacript.ioal
C3
.
(cr--;-l)
.-Cz+
0)
-
«~
.-cuted
JCR
18
If JCRi. located ODword. 254 and 255 of a 10Mpale.
s
wben
aCIP'rI~
.
Cl
J1JHP
. C1 . «ACC. 0) . C2+ (Cf . 1) . C3+ "TiiT . C4)+
at. t.he 8 bit.
Pale (1(»1)where
the ISZ 1D8cructioa i. locat.ed.
i.
ISZ
where
p.,.
the
on
Dot
end
..qU8DC.
iD
If ISZ 18 locat.d on vorde 254 end 255 of a 10M pea.. wheD
ISZ 18 executed end the r..ulc
18 DOt ..ro.
proar..
ooatrol
18 cr8D8f.rred
Co cbe 8-bit eddr...
located OR the D8Zt
p.,.
Uc&PT1~S:
located.
MD88oaic:
FIM
(retched
188ediate
Oeacription:
01010101 .., u..l
The 2nd word repr-..nt.
8-bit.
of data which are loaded
into the d..ianatad
index rel18ter
pair.
!at word on CWA:OOlD ...
2ndword on orA: D2D202D2D10101D1
S,.bo1ic:
02020202
~ RRIO
32
tr08
IOMO
Instructions
RAM
Input/Output
F.
and
.,
Description:
RAM
(Read
ACC
-+
(M)
:
Sya,ol1c
1001
ADM
~~nic:
OPR
OPA:1110
have
character)
(The RAM's and ROK's operated
on in the I/O and RAN iD8tructi0D8
been previously
selected
by the last
SIC iuatruction
«Kecuted.)
The cooteat
of
the
previ0U8ly
selected
RAM ..in
-..cry
character i. tr8D8ferred
to the acc~tor.
The carry/link
i. unaffected.
The 4-bit data in memory 18 uoaffected.
0)
Mne8DDic: RtN> (ReadRAM
statu. character
ACC
(Kso)
Deacriptioa:
The 4-bit.
of statue
carry/link
and the statue
character
0 for
the prcv1oualy
.elected
RAM
regi8ter are transferredto the accU8Ulator.The
character
are unaffected.
RD1 (lead RAM
atatuacharacter
1110
OPAl
-OPI.
1)
~~1c:
1101
--
1
~
CM-AAM3
A2
1
:>--1
I
1
>---1
3201
1
A.11
CPU
4004
13
I
14
I
BANKO
CM-RAM2. and CM-RAMS
12
3
DECODER
15
38
>-1
13
14
RAMBANK,
.>0'
1>--
.>--
I
I
RAMBANK7
IX. AN INTRODUCTION TO PROGRAMMINGTHE MCS-4
Introduction
programmer
is known as progr8m8the
a computer
effectively,
for
computer
a
prolram
to
be
To
ing.
of instructions
able
sequences
Writinl
must understand the action of each of the machine instructiona.
instruction
set of the MCS-4 is described
in detail
in the last
at
The data may
next
the
registers,
CPU
the
ROM,
the
or
of
where
RAM
of
one
indicatee
contents
the
of
WbiCh
contents
the
found,
data in some way.
counter
flip-flop,
be
to
carry
i.
or
instruction
accumulator,
signals
prograa
(The
section.)
or
manipulates
Each machine
instruction
be the contents
of the
a port.
Programming is probably most easily
learned by use of examples.
In the
pages that follow,
a number of sample program segments are described.
In general,
the examples are shown in order of increasing
complexity.
These ex-.ple8
have been ch08en to illuatrate
loops,
multiple
precision
the use of the
arithmetic,
I/O
ports,
and the use of
11
EXAMPLE
basic program
subroutines.
Consider
the case where it is desired to teat the status
switch
connected
to the CPU (4004 chip)
on the test
input
of a single
(pin
10).
look
would
OPR
OPA
truction
ins
The
J.
(JCN) can be used to perform this test.
JCN TEST, 16 (2 word instruction)
is stored
&8 follows:
and
2
locations
memory
ROM
at
A jump on condition
instruction
Suppose the JCN instruction:
CIC2C3C,
signal
000
0
Location'
memory
ROM
to
0001
13
(Jump
Location
(Juaq»
(JOt)
1
test
000
0001
12
if
Location
-
Logic "0")
16)
When this
instruction
18 executed,
if
the switch
connects
a logic
"0"
(ground)
to the test
pto of the CPU, the program
counter
in the address
register
to the CPU will
jump
to 16.
(That
is, the next
iD8truction
to
be executed
would be fetched
fro.
ROM Meaory location
16).
If the switch
connected
to
a logic
"1"
(negative
voltage)
the
if
the
"1",
logic
Furthermore.
a
instruction.
equalled
one
signal
test
a
if
with
counter
instruction
switch
status
it
were
OPj.
-
CPR.
coded
be
siaply
jump
tested
to
be
desired
can
program
the
the
instruction
been
JCN
had
would not jump but would be incremented
by 1 and hence
to ROM aeaory
location
4 would be executed
next.
Thus
could
A.
CIC~JC4
Location
12
0001
1 0 0 1
+
Location
13
0001
000
37
0
Inverted
t-
jump
condition
jump
a
ind~cate
to
used
is
Cl
the
in
shown
as
used
be
may
signal.
port
on the test
a
"1"
required
are
more
If
next
bit
condition
invert
to be made on a logic
switches
is
ROM
In this case the
example.
EXAMPLE'?
the
connected to
necessary to
the contents
bers to select
loaded using
case where t is desired
to test the status
of a switch
the port of ROM #2.
To make access to the port,
it is
execute and SRC instruction.
The SRC instruction
utilizes
of a pair of registers,
which must contain the proper n~
the desired port.
Register
pairs may be most easily
the FIM instruction.
Consider
Thus the sequence
Mnemonic
DescriPtion
2 , 0
to
index
0000)
(0010,
data
ROM
O.
12)
input
ROM
In this
of
set
one
instruction.
at
the
appearing
into
the values
from
interrogated
be
ROM(ROM
them
by
tested
may
bits
with
a jump on condition
can
selected
accumulator
shifting
the
the accumulator
Individual
switches
4
of the previously
into
be
/Read
port
and using
to
up
manner
flip-flop
(4 of
from
to contents
of loading
12.
port
ROM
has the effect
ports
pair
of index register
pair
0 to select
a ROM. The first
4 bits
of data sent out at X2 time
(0010)
select
ROM 12.
input
carry
regiser
/Send the contents
RDR
SRC
0
(direct)
immediate
0
fletch
FIM
them).
EXAMPLE, J
must
be
generated,
to
perhaps
drive
the port
equivalent
(binary
Hence
#3.
chip.
1100
sent out at X2 time during
of data
RAM
RAM
select
to
X2
at
required
Since we must select
2 bits
the
order
selects
The high
pulses
port expander.Let us assume
that RAM
13 is
4003
a
of
line
of 10 clock
instruction
is
SRC
be used.
12)
of
an
to
clock
the
Suppose a series
on RAM 13 we will
require
0
SRC
rIM 0
12,0
This pair of instructions
sets up the desired port for use.
To generate
the cloCk pulses.
we must alternately
write
a 1 and an 0 into the appropriate
port bit.
Let us assume that we will
only use the high order bit
of the port on RAM 13 and that it is initially
set at zero (so that the
program does not have to reset it).
Furthermore.
let us assume that we
do not care about the other three bits of the port.
38
"':~
us set the accumulator
the
by
accumulator
the
of
to 0
t
the
complement
then
may
We
accumulator
bi
/Set
0
to 0
order
let
high
First
sequence
left
(accuaulator
ILoad
8 by
the high
may
We
accumulator.
to
8
15.
the
0
into
the carry
flip-flop,
order
bit
i8
to add 8 (binary
sequence:
DDDD(1000)
/Exchange contents
lS
LDK
say register
the bit
baCk.
register.
it
way to complement
the
to
1000)
An alternate
shiftina
and shiftina
one
it,
and carry)
of
the operation
complementing
(ac~ator
by
achieves
r18ht
data
which
IRotate
contents
BAR
and carry)
carry
the
/Complement
set
/Rotate
to the accumulator.
of index register
15 and accumulator
(0000) to accumulator
ILoad
tor,
because Regis ter
15 contains
the value
accumula-
the
to
1000
value
binary
the
add
will
15
ADD
operation
the
Now
The first
instruction
loads
the binary
number 1000 into
the accumulator
and the second placee
the contents
of the accumulator
into
register
15.
Since the prior
contents
of register
15 are also placed
in the accumulator,
an LDH instruction
is then executed
to clear
the accu.ulator.
8.
the
repeat
could
one
pulses,
clock
10
of
sequence
10 ti88S.
of register
contents
ADD 15
IAdd
4 inatructions
previoualy
stored
to accUDllator
15 (1000
in the register)
port
the contents
of the accumuinto the previously
selected
output
/Write
lator
RAM
following
the
generate
To
Note the difference
in how the LDH and the XCB and ADD instructions
utilize
the second half of the instruction.
The LDM loads the accumulator with the value carried
by the instruction
i.e.
in binary
code
LDM 8 appears..
1101 1000 and loads the accumulator
with 1000.
However, the ADD and XCB select
a register,
and the contents
of the register are used..
data.
That is, ADD 8 would add the contents
of register
8 to the accumulator,
not the value 8.
15
39
one clock pulse
generated
this would take some 40 instructions.
However,
available
with
the ISZ instruction
The indexing
operation
a program loop to be repeated
allows
10 times.
The ISZ instruction
initially
increments
contained any value
a selected
other
than
register.
the value
If the register
15 (binary
1111)
the instruction
performs a JUMP to an address specified
by the instruction.
This address must be on the same page (within
the same
ROM) as the instruction
immediately
following
the ISZ.
If
to
however,
execute
the register
originally
the next
instruction
in
By loading
a register,
execution
in
of
say register
an ISZ,
sequence rather
contained
sequence.
the
15,
14, with
proces8or
will
the
CPU will
the value
proceed
to
6, on the 10th
the
next
instruction
than jump.
Execution
of the ISZ does not affect
the accumulator.
accumulator
does not have to be "saved" prior
to its
The p~ogram
proceed
sequence
whiCh
performs
the
desired
80 that
the
execution.
action
i8
then
Address
Mnemonic
Description
OPA
-
N~
Instruction'
0000)
(1100
ROM,
Data
register
RAM
into
(called
Al
RAM
14.
Go
if
into
acc\Dulator
15 to accumu-
of register
skip.
otherwise
ROM
to
result
40
contents
A2,
ports
0
15 to accumu-
of Register
contents
output
/Increment
14
ISZ
LOOP
14
Loop)
ports
of
/Write
/Write
WHP
register
accumulator
/Add contents
lator
of
15
contents
/Set accumulator
to 0
/Add contents
of register
lator
output
ADD
15
location
of index
0
15
WHP
register
RAM
to
0)
to index register
pair
/Send address (contents
pair
LDK
ADD
LOOP
~
(7)
(8)
fro.
immediate
0
0
0
/FetCh
XCH
rIM
12,
SRC
(5)
address
XCH
6
14
LDK
(3)
(4)
/Load 1000 to accumulator
/Exchange contents
of index
and accumulator
/Load 0110 to accumulator
/Exchange contents
of index
and acc\Dulator
8
15
~O,
LDM
(1)
(2)
of Program
Instruction
(f)
Instruction
18,
regis-
RAM
desired
index
bank
pair
the
the
index regis-
RAM
to
of
address
stored
Sends
Instruction
the
Fetches
Instruction
address
Instruction
the
11 and 12
and
(e)
- Loads the number 8 (1000) into
ter n~er
15 (1111)
13 and 14 - Loads the number 6 (0110) into
I 5
- ter numer 14 (1110)
#6
- stores it in an index regi8ter
selects
the desired
#7
- and
Initializes
the accumulator to
Instruction
RAM
Ex:PlmatioD
of accuaulator
structiona
Instruction
(8)
(I~-
port
output
RAM
the
port
back
output
Highe8t order bit of accumulator
is complemented again and sent
of RAM
to
state
and
t
f
Initial
88 follows:
9)
pulse
18
port
bit
~
output
RAM
order
~
to
back
Send
Complement of highest
one clock
and
- Generates
.
11
(Instruction
9,10,
and
0000.
10 and 11)
- The
contents of Register
14 is incremented
by 1 (0001).
The number 7 (0111) is now
stored in register
14.
Since thi8 reault
is not equal to zero, prograa control
jump8
to the addre88 specified
in the 2nd word
of thi8 ins truction.
In thi8 C88e the
addres8 8tored in the 2nd word is the address
of instruction
18. The prograa then executes the next 4 instructions
in
sequence
and generate8 a 2nd clock pulse.
Thi.
sequence is repeated a total
of 10 times,
thus generating
10 clock pu18es.
On the 10th
#12
time when the contents of regi8ter 14 i.
increaented it goe. to the value 0000 and
the program .kips to the next instruction
in 8equence and gets out of the loop.
Example 14
for
41
two
via
reaistere
shift
2 selection.
Th18
RAM
one
11.
port
from
selection,
at
character
a
RAM
pulse
the
clock
for
the
port'
fetch
used.
to
and one for
one
issue
necessary
is
commands,
then
it
12,
SRC
port
system,
11 selection.
4
of
group
a
derived above are often used to drive
It may often be desirable
to tran8fer
to
regi8ter
RAM
a
of the type
regi8ters.
9 shows the connection
three
requires
port
at
thi8
Pig.
it
operate
ports.
present
sequence
and
To
output
of
content8
the
Clock pulse streams
groupe of 4003 shift
character
address.
The low
order
itself.
4
bits
will
be derived
The table
fro.
the
the
of
eaCh
in
&8
advantage
con-
code
storage and indexing.
each of these registers.
on
drtven.
selection.
port
and
of the resister
pair
skip.
The initiali-
the 4003's
were
However.
the
4003's.
address
may
the data
O.
#1
RAM
RAM
elected
(previously
accumulator
of
#2
RAM
to
addres8
accumulator
into
character
RAM
selected
/Read
RDM
RAM
selected
to
address
/Send
sac
Sewns..n.nt
~
reeult
if
Jump
1110.
register
"Q"
to
to
contents
/Send
sac
Driving
fetChed
to
segment
7
example.
wired
are
device
based
locations
RAM
for
contents
of
addresses.
Registen
the
space,
to
line
4
for
utilized
eaCh display
be
can
if
displays
LED
addrees
RAM
by 1 the
Shift
accessed
adjacent
of
contents
Port
be
to
A
be extended
regi8ter
two
registers
of
address
/Write
WMP
Fi..,e10.
4-bit8
the table
4004
displays:
accumulator
/Send
into
save
the
the
of
and two registers
for temporary
zation must provide
for loading
Ex.-ple
#5
sequence
Suppose
selected
/Set
0
LDM
character)
table
using
LED
otheIWise
To
ROM
a
pairs
3
the
!Increment
the
over
1.
for
by
LED
!Increment
Loop
14
ISZ
9. RAM OUtlMltPOI1sDrivingGrou.. of Shift
hfgh~rder
LDM
eaCh
uses
above
loop
The
1~--~~.-'1
=
15 I Generate
the
XCH
may be loaded
represent8
allowe
above might
and
0
capability
be used
or
FIM
with
segment
seven
driving
I
LDM
FIN
could
an
lookup
table
RON
Tbe example
the
converters.
the8e
eave
to
sac
~.,
table
by
data
Fig.l0
in
ehoWD
!Nt
in
iD8truction
The
the
registers
of
contents
verter
data
intialized
be
Loop,
the
where
Regilt...
F.".
vide
selection
of the next character.
Di.p.~
LED
The aain loop is then as follows:
#2
1 clock pulse
holdina
pro-
to
time
each
incremented
be
must
RAM
in
location
the
addition,
In
The main
loop
now becomes
as follows:
ACC
!select
1
table
register
ROM
at
from
into
!store
!fetch
!Read
!initial
table address
!fetch.data
character
output
port
!fetch 1st half of 7 seg88nts
!transfer
to output port
!select clock port
!Set accuaulator to "0"
I generate one clock pulse
!select
!transfer
! trans
output
port
2nd half
of
fer
to output
!select
clock
port
!Set
acc\Dulator
to
di8play
port
"0"
/ generate one clock p~.e
INC
ISZ
that
Note
/set
/test
14
two data characters
RAMcharacter
next
for
no.
(8 bite)
of
characters
are transferred
for each diait
to be displayed.
Proceeding
with
display
for
8
.
rei.
.et
and
digit.
of
DO.
/initialize
output port aelector
Subroutines
user
finds
RAM
the
different
that
the entire sequence a "subroutine".
the user can call
each time it'.
needed with only a JMS instruction.
making
by
The sequence of inatrucHowever,
necessary.
in the prograa.
of
8uppO8e
number
a
above,
of
places
thi8
whenever
used
outlined
contents
the
example
display
the
at different
be
could
tiona
registers,
to their
initial
is sufficient:
cloCk port selector
/initialize
/initialize
to
nece88ary
-
it
Example #6
/select
FIH
FIH
FIM
FIM
the resisters
4 instructions
register
by settins
sequence
of
RAM
must be initialized
The follow1nS
Was
This loop
conditions.
out the sequence
The JMS utilizes
the address push down stack.
When a JMS i8 executed,
the program counter is pushed up one level and 18 reloaded with the
address to whiCh the jump to take place,
and execution
will
proceed
43
~
from this new location.
the old value
is
.aved
However, before the program counter is reloaded,
the "stack".
This stack operates as follows:.
with
programmer
the
program.
the
in
point
any
followed
FIM
ROM:
fro.
of
register
only
4
use
bytes
any
display
To
The subroutine
would then include
the three rIM instructions
by the main loop and terminated
by the BBL.
need
dissUbroutine.
FIM which
the
of
part
the
the
to
transferred
be
to
counter.
program,
made
be
the
level,
one
stack
the
in
entry
regi8ter
the program
of
not
part8
should
regi8ter
RAM
entering
RAM
different
the
in
if
the stack
different
the
i8
8elect8
play
in
shown,
exa.ple
the
the top value
every
raises
instruction
The
2.
BBL
Each time a JHS is executed, all addreases saved in the stack are
pushed down 1 level.
The last value of the program counter is
loaded into the top of the stack, the program counter value corresponds to the instruction
immediately following the JHS.
1.
In
in
JMS
register
minus
pletely
in
Char-
number
Memory
decimal
and
point
Status
the
float1ng
a
use
sub-
characters
4-bit
twenty
usage
number
BCD
practical
point,
more
A
~loating
number.
signed,
(BCD)
and a 2-d1git
exponent.
-
are
de8cription
of
used
the
in Section
to
the
operation
(3).
of
It
IIIB
point.
44
18
the
16
the
just
signa
characters
16
C88e
negative),
thia
arbitrary
exponent.
this
status
4
(in
completely
digit
(in
case
The
thi.
(in
hold
and the 2 digit
hold
of the mantissa
exponent.
of
the
digits
of
the sign
can be used
to
this
definition
up to the user)
characters
(16- digit.)
both
2
sign
and
the
and
mantissa
of
digits
and 4 status
characters.
(320
of storing
a 20 digit,
unsigned,
L~~~~!!~~~~~~~
for
18 required
positive)
Storage
description
a
of
(fraction)
Mantis..
This
with
each
decimal
storage
mantissa
+
*
subroutine.
the n\8er
Consider
of the
presents
to
Fetching
registers,
the
is
binary-coded
register
a 16-digit
the
4002 RAM)
exponent
having
the
16 main memory characters
Each register
is capable
point,
the
for
fixed
divided
into
bits total).
in
4
has
RAM
4002
The
acters
(Row
~d
RAM
4002
Storing
17:
the
Example
and the JHS calla
Main
the resister
The FIH selects
case
a "1"
re-
and is com-
The 16 main memory
mantis.a.
addre8s
stack
look.
at it
i8 equivalent
from a different
to
the
view-
~
For example let' s store the previously shown number in Bank #2,
Chip number #3, register
#1. It would be stored in the 4002 8.
follows:
Main Memory
Character'
Status
The following
and exponent
instructions
value:
would be used to fetch
46
~aracter
,
Charact.1
16, the 8ign8 t
.
0110
~
=
a)
i
=
.
I
21
~
-,,-
0
~W
~
U11
1101
...
~
y1181
l-
i
i
*1
alO
1811
1110
IOU
U18
u.l
I8U
1181
1110
1100
I8U
~
1118
I8U
In
as
function.
the amount
treated
are
system
particular
from
fetChed
a
DaY be used to reduce
implement
to
words
data
required
ROM
mode programming
mode,
this
of
Interpretive
Mode
RAM
Interpretive
or
-
ROM
Example 8
tu.tructions
of a computer wbidb ~ght
be quite different
than
the MCS-4. The MCS-4 program "interprets"
the data, using it to
call appropriate
sUbroutines
whiCh 8imu1ate the instructions
of
the different
computer.
In effect
another computer ardbitecture
is s181lated.
The
ROM.
or
com-
operations
RAM
normal
the
RAM
the simulated
from
of
derived
via
be
may
RAM
from
fetched
instructions)
mode, the instructiona
are
(pseudo
instructions
puter
In the interpretive
routine
the
or
routine,
appropriate
aD
to
JMS
or
JMP,
a
of
ti~
(SRC, RDtO, using a simulated
progr8m counter to maintain
the
address.
The JIM instruction
is often useful
for interpreting
the fetched instruction.
(Address for the JIN is computed from
the fetched pseudo instruction.
Each address value is the loca-
program
control
the next
routine
As
the
for
as
is'used.
Chip
ROM
eaCh
of
of
imple-
be
can
locations
progr..
If the FIN
than
bytes,
254
2 rather
exceeds
to location
program
address
mode
two
counter
first
the
address
in
located
the chip
interpretive
the
If
O.
location
the
find
program
are
step
254
the
instructions
Chip,
BBL
ROM
the
and
can be used for pseudo iDatructi0D8.
The simulated
counter must correspond to this address structure.
mented by initializing
ROH
a
chip
FIN
of
ROM
the
bytes
an FIN followed
bytes
254
to allow
to
up
same
ROM,
the
8-bit
on
from
256
located
sufficient
Thus
is
Chip.
It
ROM
the
on
BBL
a
by
pseudo instructions.
all
use
be
instruction.
cannot
must
pseudo
one
data,
in.truction
fetChing
FIN
fetChed
the
When
itself.)
must determine the proper chip to
pseudo iDatruction.
The lnetruction
by a JMS to address 0 of the appropriate
48
chip.
is
then
fetChed
~
Notes
Format
Routine
Program
MCS-4
PROGRAMMING EXAMPLES
A.
x.
2.
and
1
Column
for
Values
Decimal
uses
D
Routine
RoutinesA, B, and C Assumethe Form Shown BeJow.
Example
Where
The. first
COlU8D represents
the
The second column represents
The third
column is
The fourth
the octal
the address
byte
label
of
thi8
value
field
byte
of the instruction
word.
and can be blank.
terminated
by a space or a
for
field
OPA
the
column
is
(;).
Tbe fifth
the
1st
byte
terminated
by a semi-
sixth
column
is
the
second
byte
specification
field
(for
a
2-word
or space or slash (I) or carriage return.
(;)
colon
addres8
column is the mneumonic field,
semicolon
The
octal
instruction).
The last
.
.
preceded
by a slash
(/)
NOTES
Each
a
complete
8ymbolic
All
source
line
followed
by
a carriage
return
is
considered
record.
data
following
a slash
will
be considered
comment
data
Any
by the assembler
(ignored).
operand
followed
by a less-than
sign
«) will
be truncated
at three
(3) bits
and used as an octal
numeral.
will
only work with
those instructions
which manipulate
register
pairs
in the 4004.
The semicolon
(;)
is used to indicate
the end of argument
for
The
.
.
.
the comment field
first
byte
«)
SPECIAL
column is
byte
must
of
a two
immediately
(2)-byte
follow
instruction.
the
47
semicolon.
Arguments
for
the
the
second
Addition
Routine
lie_ow.
J-_~IG.~.
k- -
CMARACTE~
.
Figure
11.
Chert
48
I
I
"
c.:-J;kJ
for
,.
AAM
:+
Flow
If.
II.~t.."k
RAM
I- . 1-. MQ8TIA
IN
Decimal
I
. Digit
STORE
B.
16
18 Digit
Dtdmel
Routine
48
/
SET IRC4-S)80
FOR
IN'
SEE NOTE $(2
.I LOAD AC WITH 0
.I EXCHANGE IR(10)
PROGRAM
,
IRC19>=IRC10>+lJSKIP
LSB
/
16
IRCI)=8JIRC2)=13
USED
TAGS
.I
THIS
IF
RAM
TO
AC
WRITE
J'
ACC
ADDRESS
DECIMAL
I
ENABLED
CARRY
AC.
TO
C=0
AND AC
[X]
IF
ASSEMBLY
IRC10>8
I CLEAR RAM DATA
SEE NOTE $(2
,~EXT=0200
PRINT=350
/01234567
/
the
i8
Then
as
second
the
the
of
IR (3).
pattern
lin
value
unit
character
that
content
index
(which
digit
(1110).
14
(0000),
~
Conversion
register
recall
the
i8
(which
number
binary
RAM chip
the ~
into
index
register
3,
digit
since
it has the same bit
Now
character'
in
i8 made on this
BCD
and 4 to zero
the
index
and
',1,2,3,
repre8entation.
the
of
digit
binary
of
its
BCD number
',1,
and 2 of register'
in
program
proceeds
88 follow8:
transfering
by
10.(1010),
to
5
begin8
register
conversion
the eontent
No conversion
its
character
Then this
registers
to
a 3 - digit
to
index
set8
(G
-255)
numbers
assumed that
of
First
is
6
stored
in
program.
BCD
it
significant
is previously
, by the main
it
Binary
converts
program
each
program
In this
least
following
to
BCD
C.
The
equivalent.
to
index
into
back
an
8
-
bit
that
verify
and IR (3).
higher
order
to
counter
is
(5)
the
last
index
IR
repeats
to
added
of
and
the
the
checking
of
Then
zero.
proces8
i.
content
~
examines
to
The
4,
the
the
IR(4)
digit
a
tran8fered
is
8tored
(2)
IR
then
2,
2.
count
to
in
2
case,
as
used
DJrID
AC
6)
AC
IOCC
Nt
I.
WITH
UCHNtGI.
3)
MC
I
TH
WI
AC
, u.:JINE RNf AOOItESS
, ill.AD RNI DATA TO AC
,
IRCI).IRCI)+I
AC-.
IF
J\»tl'
ACeAC-1
,
,
, DL'INE MNt AD~~ESS
, READRNf DATATO AC
IICC2)
WI1OC
AC
,
ca.,--"
,
, WHITEAC To) icM
CAAIi't MG
, LJAD AC WITH CCIRC3))
, ADD IRC~) II> AC
, EXCHMGEI RC3) NtD AC
IOCCa)
WITH
AC
PCHNtG&
,
ADD.
IRC.).6.IIcC~)..
, RE1UM
50
IItC6).e
I'
TO
151"BO8M
I"C6).IRC6)+IJSlCIP
2c,,"
fl"
,
, J~P ~CONDITIO~M.
,
1166
8He
AC; and
of the program.
, ADD IRC.) T? AC
J~ '8B'
8iL
BB2,
el..4
.e3"
8831
~.3S
e83' ~~13
the details
.
~1I"4
KCM
V262
1'1.
"33
1132e&IS
LOAD
,
,
LIJA~
3
~
3
ADD
KCH
~2V5
1263
LD.
~2V"
8~24
08iS
~021
VI3I
883'
(2)
the
3
JCN
CLC
LO
..22.361
..2312..3
WM
0242
to
to
I
u,...
UAC
182' .348
~V2'
form)
, IRC'-I).'
, I"C2-3).'
,
KC¥
I~C
SkC'c
ROM
RDM,
881,
13S'
e021 .31&
added
binary
explain.
EXCHMG&
2cl18
~
I
,
LOM
KCH
0336
110.'
..12e263
HI1..33
i8
, lilC.).'JIRCS).le
Ic
"816.124
IllS
881311..1
0814ee41
(5)
down
IR
of
Ic'l
ICI.
5rcC
e351
15841
(in
~Im
ImAar
to
IQ
further
FIM
0112
100
is
(6),
IR
chart
FIM
e.818266
11.11
"81.
zero)
checked.
nM
BCoelH,'
e.e8
..el
0005
this
adding
H81 Ie.
0082
8842
08831HI
"84
8844
is
register
it
and
in
character
6
of
contents
the
except,
and
been
flow
i8
register
result
The
index
to
(4)
until
into
IR
content
3
has
is
number obtained
is stored
in IR
order
4 bits
and IR (2) contains
6,
digits
4 (which
to
The binary
the lower
The following
index
of
AC.
to
content
back
repeated
set
the
equivalent
register
BCD
register
manner
is
to
is
stored
same
is
Index
3
index
register
This
number.
contains
bits.
the
added
the
is
10)
is
digit
(which
the
in
index
to
2.
binary
IR (3)
4
of
proceeds
second
digit
BCD
process
added
register
all
content
result
the
program
the
the
AC and
Next
is
3.
(which
regi8ter
5
has a value
of 10.
Hence the program
continues
a8 follows:
Transfer
the second digit
to the accumulator
(AC) and examine whether
the digit
is zero.
If the digit
i8 not zero the content
of the AC is decreased
by
one (i.e.
the value
of the second digit
is decreased
by one),
and the
result
is stored
back into
the same location
in the RAM. Then the content
of index register
3 is transfered
to AC and the content
of index
register
c-.LING ~UTINE ACe'
:
.'
0
.-=DtGIT1
(!)
I
I
;-. -'-=,,~
1:;'41
.
'.!RIII
.4\
~
-"
.
.
~R~
--
.-;:'AC:;'i
'IR..'
OP~1ORM'.
l~
RIG..~'
51
Comenion
Blrwy
to
BCD
for
a.rt
Flow
F.".12.
(
I
analog
an
of
value
the
determine
to
is
family
computer
MCS-4
Intel
the
using
application
One
single-chip
A-D CONVERTER USING DAC With MCS-4
D.
output
a
output
to
th~
The
wired
of
communication.
Two
is
signal.
DAC
input
analog
The
chip.
input/output
for
the
with
(DAC).
memory
"port"
a
converter
read-write
uses
compared
analog
or
MCS-4
be
to
to
memory
The
digital
a
DAC
the
of
of
read-only
achieved.
is
each
inputs
the
output
the
drive
to
with
conversion
the
associated
allows
used
is
how
which
been
port
shows
have
four-wire
comparator
ports
A
figure
voltage. While it was possible to use the conventional approach of interfacing an analog to digital converter
to the microprocessor, a cost saving is achieved by having a microprocessor execute a program which enables
a digital to analog converter and a comparator to perform the analog digital converter function.
The first
con-
the
when
instruction
new
a
memory,
starting
program
through
memory,
in
sequential
location
is
new
a
to
system
jumps
MCS-4
the
processor
within
the
flow
executed,
execution
is
jump
ditional
instruction
of the comparator is in turn wired to the test input of the 4004 ~ntral procesmr. This test input line is
interrogated when the ~ntral processor executes a certain conditional jump instruction. Whereas the normal
program
implements
a successive
approximation
conversion
technique.
Starting
with
The
language.
as.mbly
MCS-4
in
convertor
digital
to
analog
the
for
program
the
lists
figure
~nd
The
sequence.
the highest
order
bit,
turn
in
bit
next
the
and
off
turned
is
bit
the
input,
analog
the
than
larger
is
that
DAC
the
from
signal
eachbit in turn is turned on and the output of the comparatortested. If turning on the bit resultsin a
testing
of
consists
program
the
for
coding
The
on.
turned
left
be
will
bit
that
then
signaJ,
input
analog
the
tested. However, if turning on a bit leavesthe output of the digital-to analog converter still smaller than
port
output
The
port.
output
the
to
accumulator
the
of
contents
the
writing
then
and
(LDM)
instruction
eachof the lines of one port in turn usingin-line coding, then repeatingthe mquencefor the next set of
port lines by looping back. Setting a bit is accomplishedby loadingthe accumulator with a load immediate
of
saved
are
4
contents
the
register
of
updating
contents
not
or
the
updating
by
instructions,
of
cleared
or
sequen~
retained
test
is
4-line
test
basic
under
the
bit
of
A
end
the
tested.
At
4.
being
register
4-bits
is .Iected at the beginning of the program by the combination of fetch immediate (FIM) and send register
control (SAC) instructions. Aegister #4 (A4) is used to contain the current estimate of the value for the
decimal
next
digit
3
the
instruction
or
2
.Iect
NC)
or
will
(I
binary
bit
12
it
increment
the
executed,
handle
to
is
by
turn
in
instruction
port
SAC
next
the
next
modified
and as can be seen
for
comparator
separate
a
providing
by
easily
quite
added
memory.
takes less than one milli~nd
read-only
be
of
can
words
of instructions
inputs
29
analog
some
easily
be
the
.Iects
can
when
loop
that
The
so
program
AO
start.
occupies
of the ~uen~
multiple
for
listing,
the
Execution
multiplexer
A
from
conversions.
basic
This
registers
loop
the
to
sequence.
modified
back
in
port
which
ing
in an alternate location by a .ries of exchange (XCH) instructions and the instruction increment and skip
on zero (ISZ) is used to perform the function of counting the number of passesthrough the loop and jump-
of A-D Conwrter uti"' DAC.nd MCS-4
52
into
read
then
are
comparators
the
of
CPU.
the
outputs
of
the
and
terminal
DAC
test
the
Block Di..m
the
at
or
driving
port
ports
input
an
output
at
the
at
system
deposited
MCS-4
the
is
several si~als is above or below M>mepredetermined analog threshold value. The analog threshold value
the
of
any,
if
which,
determining
permits
figure
first
the
in
shown
structure
the
of
use
alternate
An
processor.
each analog input and performing digital multiplexing at the input to the test terminal of the 4004 central
Programfor A-D Con""-
53
IAFTER PAS 2. PROGRAM CONTINUES PAST THIS POINT. HIGH ORDER
/BITS OF RESULIf WILL BE IN R4. LOW ORDER BITS IN R5.
00004
UsingDACand MCS-4
1
PASS
AFTER
PAS
SECOND
PORT
ROM
NEXT
OF
SELECTION
PAS
FIRST
OF
END
AT
IF
PAS
NEXT
FOR
R4
CLEAR
AND
R4
CLEAR
PORT
OUTPUT
ROM
TO
/WRITE
-+3
R4
ADD
00132
0024
LDM 1
R4
XCH RS
AND
R4
R
WR
00228
0025
R4
XCH
001~
0022
-+3
TI
JCN
(XM)25
0020
WRR
cxrne
0018
R4
ADD
00132
0018
ILOADACCUMULATORWITH0010
LDM2
11210
0017
PORT
THIS
OF
BITS
TWO
LAST
FOR
PROCEDURE
IREPEAT
81G
TOO
NOT
IF
RESULT
CURRENT
/SAVE
R4
XCH
001~
0018
JCN TI -+3
FOR
ICLEARS
ZERO
RS
TI
JCN
(XM)25
0028
PORT
OUTPUT
ROM
TO
/WRITE
WRR
00228
0013
TEST
PREVIO~
OF
RESULT
IADD
R4
ADD
00132
0012
ILOADACCUMULATORWITH0100
LDM4
00212
0011
2ND
FOR
IIG
TOO
NOT
IF
RESULT
VE
/SA
R4
XCH
001~
0010
BIG
TOO
RESULT
IF
SCH
PAST
IJUMP
-+3
TI
JCN
~
DC.-
PORT
OUTPUT
ROM
TO
ACCUMULATOR
N;iRITE
WRR
00228
0007
1~
WITH
ACCUMULATOR
ILOAD
LDM'
00218
~
FLIP-FLOP
CARRY
AND
ACCUMULATOR
ICLEAR
CLB
00240
ADLP.
(XX)33
(XX)4
~
SRC PO
FOR
/PREPARE
R4
XCH
001~
0028
~
0
P2
M
I
F
000:.
0002
FIM PO
IRETURN
ADLP
WRR
00228
00:-.
0023 002C»
TO
BITS
4
THESE
MOVE
/NEXT
0014 (XM)25
RO
CONTAINED
INITIALLY
RS
/NOTE
(XXX) (XX)32
RI
0031 00181
XCH
001~
0032
INOW REPEAT
INC
(XX)98'
0033
ILDM 1.T1
ISZ
00113
0034
RI.po).
IRO,
PORT
OUTPUT
ROM
OF
SELECTION
FOR
UP
/SET
~
USING RI/AS A LOOP COUNTER .. VALUES IN BINARY
00015
(XXX)1111B
/CLEAR REGISTERS R4, R5. (THESE TWO REGISTERS ARE
IDESIGNATED PAIR 2 OR P2 BY THE FIM INSTRUCTION).
R4 AND R5 /WILL BE USED TO RECEIVE THE RESULT OF THE
CONVERSION
/START OF MAIN LOOP
/SELECT PORT USING CONTENTS OF RO. RI
THe HIGH OR:DERlIT Of THE ACCUMULATOR:
00011
HIGHEST BIT
00017
IJUMP PAST XCH IF RESULT TOO BIG
(XMJ23
ILOAD ACCUMULATOR WITH 0001
00029
/NOW WRITE FINAL RESULT TO ROM PORT
0028 00184
LD R4
ILOAD FINAL RESULT TO ACCUMULATOR
IACCUMULATOR TO RS. R5 TO ACCUMULATOR
54
u--.
other
to
.,eileble
them
malce
mey
~
that
~
.,bmit
to
users
ell
encour.
We
u.,.'slibrery.
microcomputer
the
of
memben
natUr8l1~
Routine (AO700)(1)
libr8ry
~8m
the
to
.td
ell
to
XOR,lOR,LOGIC.
.
Addition
to
. MCS-4
logic.,broutines
Sixteen digit D.:imal
MCS-4
the
for
The routin. may be procuredfrom Intel on m.,etic tape. Alternatively,desl~
P'09"8nL
the
to
~
for
-
Tymsh.-
and
Electric
General
simulated
Intel
AND,
MfVi~
to
.,8ileble
simulator
the
NOVA
th8t
for
time-tharing
end
.-nbl.
programming
prQ9'8ml
~bl.r
Cr~
.
aid
an
as
primarily
u.
rootln.,
aSIem~y
an
and
microcomputer,
MCS-4
an
of
oper8tlon
the
simulate
to
computer
the
enab!.
which
rootine,
simul8tlng
8
of
consists
peck.
The
IV.
FORTRAN
general
in
written
is
software
The
peripheral
listings...
.
Cro8
.
progrem
Th.-
to
non-propriet8ry
ell
develop.
Initi81
MCS-4.
the
for
code
object
generates
which
MCS-4
the
than
other
mechine
a
on
executing
-.mbler
an
me.,
we
.-mbter,
cros
By
MCS-4.
the
by
OKUted
m
lo8ded
be
can
which
form
a
into
d8ta
and
instructions
the
of
representation
symbolic
a
transf8tes
assembter
cr08
MCS-4
The
circuits.
computer
integrated
of
MCS-4.t
Intel's
from
E.
MCs.4 SOFTWARE LIBRARY
MCS-4Cr08 All8m~.r 8nd Simul8torSoftwereP8Ck8.
Intel now offen an asemblerand simulatorsoftw8repack. to help developPfOW'ImS
for microcomputersystemsbuilt
ment time C81be significantlyreducedby taking.tv.,tege of a 1-. -=8Iecomputer'sproceuing,editing and hi~ speed
capability.
microcomputer.
maycontxt nation-wldecom~ter
MCS-4u...'. Ubnry
runs on the PDP-8.
Q'8bychev polynomiMI ~roxim8tion
.,broutines for
.tdition, aAbtrection, multiplication, division, sine,
COline,erctangent. exponenti81,and
SYSTEM
MCS-4
THE
INTERFACE
DESIGN
A
General Discussion
MCS-4 computer systems are often used to replace random logic
controllers
in a wide variety of systems. In each of these systems a number of peripheral devices, such as keyboards, switches.
indicator
lamps, numeral displays, printer mechanisms, relays.
solenoids, etc., may have to be interrogated
or controlled.
The
face
1.
consi. ts of the
following
progr
and
as
by an MCS-4 computer are
asinter-
ports
of
data
design
The
and output
ROM.
input
4002
the
and
ROM
via
4001
system
the
the
with
sociated
to
include,
an
Devices to be operated or interrogated
attached
must
circuits
an MCS-4 system
interface
utilize
suitable
to
design,
his
who wishes
of
part
engineer
s tepa:
Assign peripheral
device connections to port connections.
If the number of available output ports is insufficient,
4003 output port expanders may be used. When the number
of input lines 1s insufficient,
multiplexers
must be added.
The.. multiplexers
must be controlled
by output ports.
2.
1
l~
typically
of
tance
is
res
output
series
-
a
with
OV
-
.
Develop the necessary level conditioning
circuits
for eaCh
signal.
Port inputs and outputs are at MaS levels (logic
logic
-7v with a series resistance of typically
2k
3.
Write
the programs necessary to interpret
erate the output
the peripherals.
levels
A.
Appendix
to
refer
compatibility
TTL
For
etc.
nixies,
for outputs.
Inputs U8e the same levels, and appear..
a
capacitive load of approximately 5Pf).
These levels aU8t
be converted to the levels necessary to drive solenoids,
inputs and gen-
necessary for proper operatioa
of
design
requires all three of these steps.
Each
design will
typically
involve
decisions
concernins
the interaction of the three areas.
For ex..p1e.
teChniques which reduce
the number of output lines may result
in more complicated
pro-
Any interface
sr_.
The following sections describe
of commonperipheral device..
typical
interfaces
for a number
Keyboards
mine if
a key has been pressed.
66
deter-
to
interrogated
be
may
CPU
4004
the
be pro.rammed to scan and deb ounce a keyboard or
to a keyboard which presents precoded (such 88
The output lines fro. a keyboard with precoded
at one or more input ports.
An input port line
of
line
test
The MCS-4 can
can interface
ASCII) data.
data are read
the
B.
or
XI
FOR
~
con-
colU8D8,
requires
program
it
Under
is,
is
(n
m
x
n
keyboard
an
status
key
to
instruction.
0000.
at
po8ition
1111.
bit
to
remains
the
set
ACC
a
scanning
deter1Dine
to
in a row can be
all output.
go to
simutaneously
8~1.d
be
By
"~".
logic
a
to
equivalent
8ultiple
key pressee
the 4003 is disabled,
can
keye
""',
if
F.,r. 13.
Inttrf8~'
58
(SC8nned Amy)
scans.
accomplished
complementec
are
inputs
ROM
is
succe8sive
etc.,
several
on
input.,
condition
K8ybolrd
The
interface.
keyboard
the
of the keYboard
"press"
s~
i8Pl~ted
by aoving a single
"f" in
the lines driving
the keyboard inputs.
18 useful
for generatin,
the 8cans.
In
the characteristic
that if two outputs are
a logic "1" (-6v) and the other at a logic
i8
required.
showe
13
all
and
"~"
the
be
will
reeult
the
'I~".
logic
Figure
for
is
after
0011
~
0100
with a 8)v!ng
Furthermore,
Debouncing
KBP
the
ACC
indicates
ACC
pressed,
the
ACC
ACC
before
0010
0100
DP
Scanning of a keyboard
a field
of "l"s
acrO8e
The 4003 8hift
regieter
addition,
the 4003 haa
connected, with one at
is
of
0001
1000
a scan
execution
as shown below.
0010
if
the
,
0001
keyboard
resolved.
arrays,
follows:
the keyboard
88
data
is
key
pressed,
one
is
than
key
more
one
If
of the key,
pro-
The input ports conto see if a key haa
corresponding
utilize
bits
"y
4
ACC)
testing
the
one column of
rearranges
KBP
for
If no key is pressed (ACC-OOOO)
If
the
1.
2.
3.
the
This
(into
pressed.
reading
After
been
control, each output is activated in turn.
nected to the keyboard are read and tested
information
that
-
of
as
lines.
input
m
outputs
type
arranged
m
and
MCS-4
and
This
usually
is
switChes.
inputs
key
n
the
had
from
it
if
of
keyboard
The
matrix
lines
as
rows)
output
n
nected
m
gram.
Scanning and debouncins a keyboard takes a more elaborate
by teetinl
c.
easily
DC
are
be
may
arrays
LED
displays
and
These
tubes
tea.
NIXIE
sys
MCS-4
the
to
interfaced
suCh
devices
Display
as
Display
dis-
the
mode,
multiplexed
the
use
To
display.)
continuouS
a
driven or multiplexed.
(In the multiplexed
mode, a number of
display
devices are activated
one at a time in rapid sequence.
For sufficiently
rapid scanning,
the eye accepts the data as
cathode
11)
or
(10
of
set
one
array,
NIXIE
multiplexed
a
play device usually
requires
some form of coincident
selection
technique.
For example, NIXIE tubes are activated
only when
the anode supply is present at the same time that the appropriate cathode is grounded (through
the proper resistance).
In
a scan rate of approximately
flicker,
avoid
To
drivers is used in combination with one anode driver for eaCh
NIXIE tube.
Under prograa control,
the array is scanned. One
tube is selected; the cathode driver corresponding to the
numeral for that posi tion is activated,
and then the anode
driver for that position is activated for a period.
The same
steps are executed for the next position in turn.
100 complete
scans per second (or higher)
should be maintained.
This figure
allows a scanning program to have up to 60 instruction
executions per displayed
digit,
giving
a l6-digit
display.
Multiplexed
displays
typically
require
high peak driving
currents to maintain
reasonable
average brightness.
The drivers
used must be capable of supplying
the peak currents.
segment
mentioned
7
to
applied
be
above specifically
can
technique
same
described
displays.
the
the technique
tubes.
n~ral
LED
NIXIE
Although
~7
In systems which combine a numeric display
and a keyboard,
considerable
savings in program meaory space and external
hardware can be achieved by combining the display
scan and keyboard
scan.
The same loop control
and output port logic can be used
for keyboard column selection
and numeral digit
position
selection.
Teletype I nterfac»
D.
The MCS-4 sys tam is designed to interface
with all types
of terminal
devices.
Interface
with teletype
is a typical
example.
The interface
consist.
of three simple transistor
circuits
which is shown in Fig. 15. One transi8tor
i8 used for
receiving
serial
data from the teletype,
one for transmitting
data back into the teletype,
and the third
one for tape reader
control.
flow
chart
further
expla~s
the
details
of
the
The
character.
the
out
print8
and
chip
CPU
4004
in
3
and
2
ter
It requires
approximately
100 msec for the teletype
to
tr8D8mit
or receive serially
8 data plus 3 control
bite.
The
first
and the last bits
are idling
bits.
The second bit i8 a
8tart
bit.
The following
eight bits are data.
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on for about 9.09 meec. The MCS-4 system i8 ideal for this timing
control.
Following
is a simple prograa which is written
for
thi8 purpose.
This program not only contro18
the teletype
timing but a180 s tares the data temporarily
in the index regi~program.
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lI
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r~~-..
PORTS
110
MAXI_'
Program
Alterable
Loading
for
Used
RAMs
and
ROMs
Intel
Memory
Program
the
of
4-bit
16
and
Ports
nput
I
4-bit
16
to
Up
-
2102)
(1101,
RAMs
and
(1301),
ROMs
Mask
Interface
TTL
Eliminates
Completely
-
CPU
4004
CPU
4009.
the
via
CPU
to
transmitted
is
data
ports,
output
and
input
sixteen
to
up
with
communicate
C81
-.
el~t.bit
the
of
Demultiplexing
X3.
end
X2
times
execution
the
during
selected
be
can
port
.
the
so
code
se4ection
port
1/0
the
stores
also
~
The
p...
byte
256
sixteen
to
up
contain
may
The
deta.
and
instructions
accepts
CPU
the
when
M2
and
1
M
during
memory
pro~m
the
to
a'lailable
is
add,..
The
ports.
1/0
TTL
to
RAM,-!d
or
ROM
either
memory,
program
standard
to
interface
direct
provide
4009,
and
~
the
devices,
new
These
systems to simulate the control logic of the 4001 is now embodied in two special interf~
time.
M2
and
M1
at
4009
word from prO'l'am memory and trW1smission to the data bus is carried out by the
GATI.o
~I.-.cr
I::~=.~
.
~
is
Size
the
of
to
4004
which
output
or
input
memory
Pl"owem
TTL
The
ROMs.
4001
masked
metal
of
instead
PROMs
1702A
.
~1'8Standard
of
Compatible
Metal
Directly
the
bus
1/0
four-bit
~ropriate
the use of
.
~
DATA"
Memory)
Output
Alterable
MY
~
TTL
and
in
Mix
any
are
(1702A),
Storage
nput
I
With
of
-=cumulator
e
of
wey
By
to permit
60
,
Independent
PROMs
Compatible
the
from
W1d
are designed
Program
from
Port
~
Lines
PROMs
Program
(Write
is
I/O
Both
Program
WPM
Expanded
be
Permits
Ports
1702A
Directly
instruction
May
Combine
Interface
.
The ~
I/O
Ports
Easily
.
systems
Control
and
of
Port
Ead1
.
Prototype
Programs
MCS-4
Ports
Output
for
Instruction
Number
.
.
I/O
.
.
Execute
.
.
New
.
used in the prototype
deviC8.
is used. the addresslatchingunit, acceptingtwelvebits of add,.. in eachof thr- time periodsA 1, A2, A3.
FEATURES
Memory
Storage
Capability
Storage(RAM)
~-.~@--
..-18OUTPUT
.PORTS~I_I
118 IWUT PORTS
.
(4008/4009)
Set
Interface
and
Memory
Standard
Mcs.4
A.
AIDS
DEVELOPMENT
XII,
Program
Analyzer
for
While the disptay of the seard1add,.. is latdwd.
NEXT
button
the
hitting
by
INCREMENT
the
examined
be
Pushing
~
switch.
can
this
and
count
more
one
the
throu~
made
been
h8V8
15)
to
(1
ADDRESS.
buffered
in
accessible
also
are
~I.
back
the
on
sockets
DIP
16-pin
external
via
form
L
TT
is
by
This allows for external monitoring neededfor data logging
appl ications.
(SRCinstruc-
PA4-04 requi~ a sin~ external power supply
(+5V DC, 2.0A) which is connected to banana plug provided
on the beck p81ei.
natu~ly
contents
instrucpr0-
1. Connect 5 volt
system
MCs.4
to
,#,ound
(Connect
plug
hit
is
button
~
the
until
hold
will
display
The
well.)
-
common
num-
instruction
.Iected
the
at
data
the
latch
will
PA4-04
ber.
2. Connectanalyzerto 4004 CPUvi. DIP-CLiPconnector.
(which also appliesa resetpul. to the MCS-4systembeing,
operated
to 8nalyzervi. b8\.,.
POWW' wpply
the
runs
switdtes
program
the
Operating PrOC8dures
points
the
.lected
at
ex8nining
CPU
for
the
ADDRESS
as
Now
SEARCH
panel.
the
front
into
the
number
on
vided
tion
in the program. This is done by entering the .Iected
connectors.
is
display
this
mode
of
made
status
been
runs.
the
and
bus
data
the
of
running
free
program
have
as the
Provisions
d1anging
the
In
tions).
The
is
line
execution
the
CM-RAM
and
point
which
ROM
indicate
from
RAM/ROM
last
the
also
b.:k
received
Displays
what
CPU.
and
parameters
All
four
the
CPU,
the
by
out
.nt
address
the
displaying
bus
data
bit
instruction
the
paaes
number
preset
pin
16
a
via
the
of
parameters.
CPU
SEARCH CONTROL and TEST switches provide additional features for e8y program debu8ng.
contents
the
CPU
4004
the
si~iflcant
to
the
of
display
and
latd1
all
connects
analyzer
displays
thus
and
The
displays
A swi1l:h"ectable passcounter provides interrOQation
loops
by defaying the display until after a preset
program
of
of
event detector, addresscomparator, binary display unit, and
trouble shooting in the field.
active
pr°'lam
fashion.
softwareand systemdebu.ing, CPUdatalogging,prQ9"am
DIP-CLIP
the
ex~ined
development tool "and for convenient field .Nice of microcomputer systems. It can also be used with any of the SIM
systems or the imm4-42 module.
Applications consist of
LED
indefinitely.
The previous instruction C81 be
by using the DECREMENT swi1l:h in the same
be continued
It was desi~ed as an MCS-4
SEARCH
capability for MCS-4u.rs.
will
x 1.5") portable unit providing a powerful real-time analysis
increment
9"
x
(9"
compact
a
is
Analyzer
Pr~
INSTRUCTION
The PA4-04
instruction
System
the
Development
displayed
MCS-4
next
B.
PA4.04
3. Set "SEARCH
add,...
on).
81
ADDRESS"
switches
to desired
program
p-.s.
from
of
when
switd18S
"SEARCH
JIN, ISZ, JMS,JCN, BBl).
(JUN.
line
test
CPU
~
switch
HOLD"
MCS-4
Dat8BusContent
DuringExecution
of EachInstruction
82
the
not
at
CNTR"
"PASS
does
pul.
sync
the
display
a
data
provide
to
mode.
thil
(CPU
switch
"RUN"
..rch
in
addr-.
to zero.)
one
by
8ddr88
switches must be .t
~
of
decrement
Summary
to
"DEC"
up
preset
from
location zero desired as well.)
Push
Push
c.
switch also if .x~tion
"TEST
time.
indefinitely.
following:
"RESET"
cycles.
to
RAMI
executed
line for 2 instruction
b. Push
latch
(Pu.,
operations:
a. Push"TEST ONE SHOr' switch to assertCPUtest
L Push"I NC" to incrementIe«ch add,.. by one I~
tion.
flow
prO9'aIn
the
when
li~t
SRC
"LAST
will
last
the
The
indicator
instruction.
display
will
COMPLETE"
9. Miscell81eoul
this-mode
at
willlatd\-up
displays
data
VALID"
SRC
.,
"POINTER
executes
POINTER"
"SEARCH
of the
(push
zerodesired
the above operations for analysis of altered-sequence
time.
CPU
All
on).
The
7.
CPU
ROM
before
anyone
Push "lOAD"
d. Push"NEXT INST" switch 81d perform .,y one of
8. Further prQ9'am"alysis C81 be made by performing
b.
new .tting.
. well).
search addressor after execution of the next instruction
after the searchaddrea!passcount ("NEXT -INST" switch
COMPLETE"
to desired
"RESET" alsoif executionfrom I~tion
the
of
li~t
pa-.
will
of
indicator
number
preset
the
COMPLETE"
executes
"SEARCH
CPU
The
the
6.
location zero desired as well.
In
number
execution
if
desired
also
to
switd8
"RESET"
(push
CNTR"
"PASS
"LOAD"
4.
Set
Push
5.
I~tion.
(Push "RESEr'
switch also if execution
from location zerodesiredaswell.)
c. Set "SEARCH ADDRESS" .,d/or "PASS CNTR"
-6V
Va
Va
"RED
/
BLACK
/
.I
/
CLIP
CONNECT
CPU
/
TO
ADR"iY'NC,
\
v.-6V
J-1
crulJl
CPt} 0fJf
DO
DB1
3
V.
V.
.1T
7
.2T
6
SYNCT
}-CLOCK
CPU
Vno
11
CMR2
CM&l
15
<:MaG
--
MIdTTL competibleex.-pt J1-CPUin silnllalrom 400.. (If
PA4-04 Rear Panel Layout
63
108'
CKT
~
I
~
ha
MId
1n88yzed
T.t
beln,
CInobO8rd
U..
MCs.4sys-
Red j-*
«'--
die
if
p-.M
only
ha
PM
of
(SIM4-03
dri_.
~
MId SIM4.02.1
3. All sips - positiveI.
~. +5V,Vno -10V.1
DATA
M1
X3
:i:ii
Xii
j8CkI.TIw MItIPIY
nMIIIl8 ~
- \\I Bleckj-* - \\I -6V.
- GND(conNnon
to ~
GNDI.
belng.wynd.
A8d- +5V,-.
functi-
~
-
MId
MId
T.t
*t
supplyto ~
DATA
X2
XU
m
'i:iO
Xii
11
12
13
14
SYNC
ADa
16
NOTES:
u.
2.
SIM4-031Y1t8m1
~i,.
pull-up
SEARCH
16
COMPLETE
CGmpetibie wid! die Mcs.4 IyIt8n
DATA
M2
iiB
iiD
m
XII
10
9
8
7
OUT
15
An
SA ClIP
PC CUP
1. Con.-t exwn8l5V (2A1po-
SIM4-01
CONTROL
m
MB
MH
8
5
4
AO
ADDRESS
STROBES
STATE
1
12
13
14
18
POINTER
VALID
ADRCUP
DATAOVI'
M'iO
Mil
Iii!
ClIP
14
15
m
SRC(X3)ST8
Ai
A1
Ai
Ai
Ai
A1
AI
AI
ADa
13
Ai
3
4
5
6
1
8
9
10
11
SRCIn) ST8
2
15
SRC
UPDATE
12
PIN
1
2
3
DATA
CM-RAMO
CONTROL
PIN AD"Ot7f
RST
fIN cn. otn'
lXB'fi
2Ai'fii
3A2m
4A38fi
5Mii'fi
sii2ifi
7iiifi
sX2fii
9
BOCSYNC
10
J.5
J.4
J.3
11
16
CM.RAMI
15
16
MEMORY
MEMORY
CM.RAM2
14
14
CM.RAM3
13
13
12
Voo
CMRa
11
CM-RON
12
CMRM
CONTROL
TB8T
CPU
10
CONTROL
SYNC
~
~
6
9iiiffi
10 T88'lT
9aaET
8
7
6
&
6
4
D3
4
DBa
D2
3
OAT~8US
BUS
2
01
DATA
2
DB2
1
DBO
PIN
1
PIN
J-2
c.
Intellec 4
Features
Idealfor prototypingMCS4 Systems.
Specifications
WordSi~e:
K
1
PROM
in
(8
bytes
4K
to
(4
words
320
deci-
and
branching.
binary
bit). expandable to 2560
words
46. including conditional
Instruction Set:
. The heart of the Intellec system is Intel's four-bit
Storage:
RAM
finished
bits)
a compact
Data
panel.. power supplies.
and
cabinet (less thanQ.S ft.3).
control
software.
standard
interface.
TTY
I/O,
switchable
storage.
data
memory.
program
of
bytes
5K
with
bits)
system
(8
microcomputer
Instruction
4 is a complete
Bytes
Intellec
Size:
The
Memory
.
Memory:
Data: 4 bits
Instruction: 8 or 16 bits
.
reglster-toI/O
and
Controlled
panel
control
the
output
8
ports.
nanoseconds
via
liS
Crystal
10.8
900
input
4
Time:
Standard
Time:
Cycle
Channels:
I/O
ports. expandable to 16
input ports. 48 output ports
OperatingTemperature:OoCto 55°C
program
RAM
to
loaded
is
which
assembler
. Standard software provided with the Intellec 4 includes a system monitor which provides a loader,
hex memory dump, and instruction editing, and an
Cycle
Memory
Direct access to memory via control console.
Access:
Machine
memory.
Memory
.
System
working registers. a four level address stack. and
capability of directly addressing over 43K bits of
Clock:
register
mal.
lel CPUwith a repertoireof 46 instructions.sixteen
arithmetic.
"computer on a chip;' the 4004. This is a 4-bit paral-
development
may
-10v:t:5%
+5v:::5%
be
.
grammable
and
Complete
system
erasable
be commitpro-
it may
1702A
is firm.
Intel's
program
in
the
storage
After
non-volatile
to
ted
option.
Read-Qnly-Memory.
control
and
hardware
debugging
Weight:
aids are provided via the control panel.
.
Crystal clocks are provided
.
System is expandable
Standard Software:
for system stability.
to 12 microcomputer
Support Software:
mod-
ules in a single chassis.
64
x
17~"
only)
x
7"
top
4:
(table
Intellec
12Y4"
Physical
. A complete PROMprogrammeris provided as an
Size:
fM"_",-
memory.
RAM
in
done
amps.
program
1.8
all
'"
system.
amps.
this
8
With
.L~po
.
Supplies:
Power
memory.
need
format.
or
a
on
memory
RAM
of
contents
the
Display
b.
printer.
of
memory.
blocks
RAM
fill
of
memory.
bytes
RAM
of
individual
blocks
move
.-
RAM memorywith constantdata.
d. Writecontentsof RAM memoryto papertape
Assembler
Monitor
Modify
c.
Software,
Resident
System
format
(t"L)
~
Panel
Cabinet~
Standard
are as follows:
~
Board
Mother
Display
and
Finished
functions
a. LoadRAMmemoryfrom papertape. either in
r,/
Module
Programmer
with
PROM
Chassis
V-
Supplies
Control
Power
operation
performed.
BNPF
.7r~
4./
Module
be
The monitor
c...:..4..:
V-
Memory
Module
RAM
Control
ever
c./
Central Processor Module
"bootstrap"
includes
hexadecimal
System
Accessories:
no
Standard
and
I
Modules
~
following
c.(.
the
that
4{imm4-40A)
Modules
so
INTELLEC
Central
and Optional
PROM
Systems
4004
The
Standard
Pr«essor Chip is the heart of e«:h Intellec 4 system.
BNPFor
in either
hexadecimal
format.
machine
binary
to
code
mnemonic
Translates
tape.
paper
via
Memory
RAM
system
into
Module
and
label
store
RAM)
(4002
devices
tape
program
a
monitor.
generates
the
via
assembter
(eight/RAM).
pass
reloaded
is
two
This
~ich
de-
and
and
provided
IV
assembler
software
cross
FORTRAN
a
standard
offers
the
to
Intel
general
in
4.
addition
Intellec
written
the
simulator
with
In
DevelopmentalSupport:CrossAssemblerand Sim-
for Rack Mounting
ulator
Universal Prototype
Module
Module Extender
Drawer Slides and extenders
4.
symbols
ROM Memory MQdule
storage
\'""'
3
Module
Module
2.
Storage
Input/Output
Data Storage
Data
Instruction/Data
Loaded
code.
4:
Bones
Bare
and
1.
4
Intellec
the
for
available
MODULES
OPTIONAL
B. ResidentAssembler
TTY.
the
through
provided
A SystemMonitor
1 Containedin four 1702APROMslocatedon the
The
computers.
purpose
general
on
operate
to
an
enof
which
operation
routine.
the
simulate
simu~ating
a
to
of
consists
computer
the
nation-
three
programs.
the
to
services-AL/COM.
access
time-sharing
Tymshare-for
computer
and
wide
65
contact
Modu.le.
microcomputer
systems have
called a Resident Monitor in
G.E.
2 Intellec 4 modular
a control program
may
Processor
alternatively.
Central
MCS-4 microcomputer
set and an assembly
routine
used primarily
as an aid to programming
the simulated microcomputer.
The routines may be procured directly from Intel, or
designers
is
start-up
system
after
dard software is via TTY.model ASR33. All control
ables
package
stan-
4
Intellec
to
interface
peripheral
All
Standard
signed
Software
Microcomputer
Modules
Modulesmaybe orderedIndividuallyAll modulesare 8" wide, 618"
high and use standard 10o-pin connectors
.
.
.
imm4-42 C~tr.'
This
Proceaor Module
is
a
compleJe
microcomputer
system
with
the
processor, program storage, data storage, and 1/0 in
a single module
The heart of this module is Intels 4004 single chip four-
bit parallelprocessor-p-channelsilicongateMOS
. Accumulator and sixteen working registers (4 bit)
Subroutine nesting up to 3 levels
(provided
by
Intel's
are
(4-bit)
of
data
storage
(Intel
4002)
Four 4-bit input ports and eight 4-bit outPut POrts (in-
.
.
.
.
M
Extender
test and system
imm4-76
PAO'M
debugging
Programmer
Module
. Providesall timing and level shifting circuitry for pro-
Control
. A maximumIntellec 4 system may contain up to 2560
.
Complete
. All outPutportsare TTl compatible
imm4-60Input/OutputModule
. This module provides input and output port expansion
ports are
fixed
systems
a
for
PROMs
1702A electrically
the
in
substituted
be
may
(1302)
ROMs
~
the
debugging
phase
of
program
also provided.
plug
into
common
for all boards
and unique
modules
bus.
in the system.
customer-developed
. A fan is provided
module.
MOS
. For volume requirements. Intel 2048-bit mask programmed
during
development
. Space is provided for additional
bytes/module)
4K
(maximum
erasable
for up to sixteen
and
memory
program
programmable
sockets
gram
tool
SEQUENCE.
and MODE CON.
easy examination
of the pro-
68
used
.
imm6-26 PROMMemoryModule
. Provides
development
Ch8ai1 Modu18 (usedon the Inlellec 4 andBareBones4)
. Capacityfor up to twelvemicrocomputermodules
. PCMotherBoardeliminatesback planewiring-all cards
compatible
TTl
are
module
this
on
without additional memory
. Eight 4-bit input POrts and eight 4-bit output
provided.
.
program
ADDRESS.
PROGRAM
TROL switches
permit
is
output
are
4-bit
programming
ports on each mOdule
sixteen
centers)
providing
mil
module
PROM
. A 4-bit output port is associatedwith each RAM on this
microcomputer
soft-
displays system status.
Address and Data Entry switches
Status. instruction code. data and address displays
is
(125
expansion
1702A
this
system
P8nel
for
for
8nd OfIPl8Y
connectors
storage-decoding
special
1702A
Provides complete operator control for Intellec 4 and
socket
words of
provided
by
erasable
module
ware
.
for sixteen
and
has capacity
and
is controlled
100-pin
module
Intel 4002 RAMS-1280 words (4-bit) of data storage
. 320 words (4-bit) of data storage are provided
programmable
programmer
Control
This microcomputer
This
Intels
with
.
Aramming
supplied
3~0 words (4-bit) of data storage are provided.
. Four4-bit input POrtsand eight 4-bit output ports
imm4-240... Stor8geModul.
Ports
Module
. Extends Intellec modules out of card chassis for ease in
are
storage
program
PROM
of
bytes
K
1
for
Sockets
imm6-72
provided
same
P~1or
and specialized Interface Circuits
Instruction/D...
Stor8ge
Module
This microcomputer
module
has memory
capacity
identical to the Central
Processor
Module
and is used for
expanding
memory
and 1/0.
.
Modute
.
expansion of memory and 1/0
. Twophasecrystalclock
imm4-22
Prototype
. Accommodates 14, 16, 24, or 40 pin wire wrap sockets
(maximum of 52 16-pin sockets)
Provides breadboard capability for developing custom
cludesTTYinterface)
. Bus-oriented
Universal
are
Standard
.
320 words
provided
Centr81
imm6-70
provided
.
imm4-42
PROM)
set 4008/4009).
(Intel
interface
PROM
bytes
1K
elements
and 1/0
1702A
memory
memory
for
Sockets
.
For developmentwork, the CPU Interfacesto standard
semiconductor
standard
of
.
Memory, 1/0 modules
systems interface
MCS-4EVALUATION KIT USING THE 4001-0009
way
This kit provides both a convenient
and an educational vehicle to better
evaluating
of
XIII.
the MCS-4 parts
understand the MCS-4 operation.
The 4001-009 stores a microprogram
that exercises
the 4004 and 4002's
and executes all of the 45 instructions
in the MCS-4 instruction
set.
pulse
a
storage.
of
applied
jump
same
address
END
be
RAM
must
by
or
signal
when
the
the
applied.
of
where
aode,
to
the
RESET
loop
pass
needs
clear
the
fully
a
address
be
the
must
RESET
is
on
single
RESET
to
of
circuit
TEST.
to
one-shot
a
width
the
"hang"
will
in
mode,
llSec)
The
either
continuous
condition
loop
I
the
-
4004
works
the
(=-350
tOOde.
by
connected
be
provided
periods
system
of
out
TEST
the
the
"1",
on
get
jump
is
If
in
clock
pulse"
be
should
"single
8
operated
x
To
a
on
03)
on.
is
32
the
can
10)
(RAM
to
condition.
Jump
(Pin
power
system
least
at
the
at
in
sianal
°0
RESET
case
The
generator
be
If
only
SEQUENCE
to
on
directly
that should be used.
The circuit
for single pass/
if only continuous
operation
is sought.
In this
Fig. 16 shows the hardware
continuous
can be omitted
The I/O
resistor.
Although
being
all
connected
alwaY8
be
to
circuit
4001
externally
is 110 msec. using a clock period
inputs
doing
with
according
in
is
the program
flow
(with
execute the prosraa stored
comments) and the truth
87
to
configuration-,
they are
lines
the waveforms may be
the ROM.
Attached
no
of 1.3 usec.
observed.
Both 4002-1's must be used in order to fully
chip
any
to
for
4001 where
reason
The
as inverting
must be supplied
the CM-RAMi lines
are not used in this
pulse4.
If a scope is hooked up to these
the
instructions
4001.
of
chip.
ROM
JUS
the
and
1
JMS
only
the
8e1ect
cause
chip
will
time
internal
use
still
are
operation
8e1ects
normal
of
time
A3
the
execution
at
the
16)
4001-0009
The two phase clocks, ('l and '2)
the KCS-4 data sheet specs.
The program execution
A3
the
at
with
coded
address
any
pins of the
copnected.
from
and
code)
time
.how
of
different
(out
i8
can
we
A3
(the
that
code
This
one
number
i8
only
selected.
80
been
has
therefore
4001-0009
activated,
The
To ~i
tor the program operation.
scope should be used in the I'B delayed
by AI' ~de.
By using the delay ti~
multiplier
the program execution
can
be easily
seen.
The synchronization
signals
for the B and A traces are
pin 13 of 4002-1 10 and SYNC, pin 8 of the 4004, respectively.
table.
~
".-~
CA'~.- ,
~
~
"..~A_&
,...
I..
4004
I
rl.r
~
eA-6_-
.."
0008
4002.1
#1
H
"!
-!
-
..
"
..
.J
-..
-.. { at
0;
0.
.,
~
Oi
_-'.0
0.
"-180
c-
.
..
~-
-
~.-.'
==$=
CM-I
CM-~
Diagram
for the MCS-4
68
4001-0009
Timing
the
17.
Using
Figure
Kit
llllf.'lll";:""
Evaluation
CMo-,-
,
,
.
,
.
,
,
" . . .. . ...
...~
,
T
T
T
T
~
~
f
~
~..~ - . . ... ..
.
Figure
16. MCS-4Evaluation
Kit Usingthe4001-0009
---
ROM
4001-0009 MCS-4 EXERCISER PROGRAM
~IC
acc~tor
and carry
atack cootent
15
Loanpointer 4002-1 11
5
nM,
BBL,
WD
Oleck
Oleck
4,1
JU8pto LDM( aubroutiua. Thia .ub-
indes
all
of
._routine
IDX
COGt8Gt
(%
the
locationa)
addrea.
FIR
Load
rea1.~er
IDX)
(~
(Checks
J~
J!§
to
1«)
(LD
.nm
routine i. U8ed to .ark the prolre88
of the prolr..
by ..nclinl out a
pattern on the output line. of 4002-1
11.
._routine.
2.54
FDO
J~to(%
FIR
ind.s r8&i.ter
locatiO118
254)
locatiOG
in
.tored
data
the
with
FIB)
(~
J}8
(Lo8d8 all
1m)
Loada all indes A.tater
locati0D8
with the data etored in location
255.
rIW)
(~
.JIm
(~
J!8
HOP
a..tore
pointer
Locat1OD
count8r
18
4002-1 II
255 coata1D8 HOP. prOlr88
1ncre88Qt8d
to
0;
0;
0
uaed
18
proar..
~he
Thi8 por~10D
of
L
255-
3183
32
JW 12
24
318LS
255
JW 15
255
nN1
12. 11
CL8
S': 5
..rker
.roB
output.
on 4002-1 Ii
0
SIC
~
==t ae.et
and
~o check
1D8~ruc~1OD8
and load ~he 8~ackvi~h a checkerb08rd.
JI8
«S IDX)
nN. 5
4.2
JlmLS
255
1
.
jim 7
26
2 IP
JW8
4
36
jim 15
255
jim
to -4002-1 10
1
Go to next cherecter
41
IU
IAC
WIN
Send pointer
IAC
VII
Thi. portion of the procr.. i.
0
2
41
IU
IKC
69
reliat8r
~
to
Go
WR3
IAC
va
IAC
VIl
uaed to l08d
4002-1 10.
STC
ADDRESS
COlG4!NTS
a checkerboard
into
fa
~Ct10D8
Jm
occur.
to the aequence
inat.
foll~
for
j~
refer
DAA
the
4002-1 10 pointer
addreaa
DU8bera
.ection 18 wed to checkthe
ODCOOdit1OD
1II8truct1OD.
which
PoiDter to 4002-1
tbj.e
XCB,
Ln,
mc,
Oieck
to
~
The
j~
O1.ck
17
Ie.tore
Olea M4
Load _rken
SUB 1netruct1OD
Load _rkera
Olea
in8truCti0U8
HefteR
IAC
Clear
DAA.
BAC.
0
~
~
J
1
Check
UP
5
6
0
3
PO
2
Ct-o
Ct-1
TwO
A
T-1
")
DCL)
(LD
7
(LD
15Z
STC
DC
LD
8
9
8
4
ISZ
SKC
4
I&)
SUB
SUB
4
5
0
«%
STC
SKC
ISZ
JIm
0
4
5
4
1
-.J
70
1D8truct10118
ISZ
DAA
LD
MC
JD
~
SKC
Am4
Am5
JD
79
~
nKO
~
~
JmO
J~
J~
J~
J~
J~
J~
MDDIC
9'
..
..
'4
'4
77
~
::
70
n
"
"
"
::
.,
"
"
::
"
..
.,
~
"
"
"
"
"
..
"
,.
..
li'
:::
"4
li'
::~
li'
i~
'"
:::
li'
li4
'"
li4
~
::;
::
'"
[!E
[
[
,
.
...
w,"',
["
57
IAL
w-.
71
67
Jt80
69
CLl
63
nK6
102
nK7
89
0
W8
BAa
ISZ
89
89
ne
Jt80
i17
J18
CLI
W8
104
ISZ
104
CLI
sac 5
%a9
W8
WD.
W8
117
CLI
WIM
DP
W8
ISZ
129
CLI
Iaz 4
136
lAC
W8
DAA
~
~
,,-
~
ROM
, r
15
LI»I
(X)IIt!In$-
WRK
141
a
~
A
141
JC8
Wmt
TCC
oIect TCC1D8truct1ou
..rke~e
Clear
5
sac
aa
OIeckfCS1n.truct1~
TCS
1.54
WDI
STC
WRK
TCS
L1»115
J-
155
153
152
151
150
149
148
:I-
CLI
147
-146
145
144
143
142
""
ADDRESS
!lfE!dIC
Q.:
TCC. QfC.
1n8truct1-
4
2
a
12
PIM
156
ISZ
WRK
RAa
atea
a
1
IU
coat_t
IDf
18ad
163
ofall-rr
aDZ
IDI
locatt-
219
220
221
a
4
UZ
163
a
PIMa
2
a
a
nJl1
3
SIC
1
saM
1
DC
SIC
S.
3
WDI
UZ
178
a
nJla
a
0
PIMa
1
.5
a.I
SIC
a
~
SIC
1
1
ArM
DC
sac
ArM
3
VB
ISZ
5
193
sac
IDf
A-o
cycl8.
~,
the
of
t..t
to
c_ected
10
0
.tart
To
.top.
will
proar"
0
71
applied
be
_t
.ipal
will .
be
in
operatiGD)
p.e
(.iDale
.y.ta
the
to
r-l
lAC
2
JURO
211
J(3
usn
S
SIC
aaaiD
CLI
the
ww
18
JC8
21'
1.1»18
sac
the
.
If pin 13i. DOtc0aD8ctad
to ~T
JTMO
L
~trol8
char8Cter
.tora
tbe cycle
At the _d of the 2nd
if pin 13 of the 4002-1
the proar8O4e.
WIf
213
-214
215
216
217
218
porti~
Statue
nl8»er.
cycle,
L1»12
hlll
'212
'DIJ..
2
...
OleckSBM
J.utructi-
Oteck AD!! iD8truct1on
SI.C
172
173
174
175
176
177
~178
179
1181
182
183
184
185
186
187
188
189
190
191
192
-'193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
ww
1n
DC
1D3
170
164
16-5
166
167
168
169
..
SIC
~
162
161
160
159
158
157
...1.56
contin-
SUBROUTINES
5
U
IC8
IAL
~
CLC
U
LD
SIC
.0
IlL
222
223
224
225
226
227
228
SIC
sac
sac
sac
SIC
SIC
sac
SIC
0
1
2
3
4
.5
6
7
BBL,O
237
236
235
234
233
IU
4
~6
~.s
~.
2
FIB
7
4
RAL
LD
FIB 0
BBL,O
DCL
247
248
249
250
FIBl
FIB
FIB]
XCB4
238
239
240
241
242
243
244
24.5
246
72
(.w)
Ull
.w
0000
nJ
255
2.54
1111
-'{:
0000
Dat-
0
BBL.
IDa
~~1
IX
232
231
2~
229
The following
pages provide
the electrical
the MCS-4 system.
For TTL compatibility,
added between
the ~utput
and VDD.
All
MCS-4
the
of
Characteristics
Electrical
APPENDICES
characteristics
a resistor
should
outputs
for
be
are push-pull
HOS outputs.
Figure18. MCS-4Output Configurationfor TTL Compatibility
option
is
(the
compatible
TTL
are
4003
and
4001
desimpedance
an exception).
Voo
4001 non-inverting
the
to
Inputs
inverters.
The input options
for the 4001 are shown with the detailed
cription
of the 4001 I/O ports.
All other inputs are high
MOS
v.
OUT
v.
XIV.
Figure19. TypicalMCS-4Input and Output Circuitry
73
Maximum
Ratings*
Temperature
those
listed
under
"Absolute
Maximum
Ratings"
4001,4002,4003,4004
-
W
-20V
onlY and functional operation of the device at these or any other
condition above those indicated In the operational sections of this
specification is not Implied.
Characteristics
Operating
1.0
+0.5
Vss
to
Respect
above
may causepermanentd8ma~ to the device.Thills a stressrating
Dissipation
and
Po_r
C.
VOL'
(~IL'
volt.
negatillt
mort
the
as
defined
is
"1"
Logic
~T
25Oc
TA'
TA~OC-
"4i
~
Y C~ENT
PINSI
INPUT
EXCEPT
I~
IALL
1/0
0
-,.-y
CIMRINT
LEAKAGI
VIL
. VDD~".c~,...~,! I
VOLTAGE
LOW
CLOCKS!
I
v
CLOCK!)
'JOLTAGI
HIGH
INPUT
I
:a
..
0.1
1.0
mA
CHARACTERISTICS
OUTPUT
SINKING
LINES
.
Your.ov. F.
T2t. __Ibility
IIUt_VOO~b8~3I.
121C0 1!.1",
.
LEVEL
"1"
CUMENT,
Vw'O.3 I
2.5
IOU
110
4001/2
0UT1'\IT
I/O
VIHC
CLOCK
4001/214
~~
LOWVOLTAOI
,~..
,,~,..
~
CLOCK
41»1/2/4
INPUT
(EXCIPT
VIL
VOO
V.-U
~1/2/4
INPUT
(EXCEPT
¥840.3
VOLTAGE
v.-t.5
VIH
INPUT
4001/2/4
HIGH
INPUT
~
!ilL
CHARACTERISTICS
INPUT
InM
---
AVI~AGIIU"L
4001/2/4
8_;
'WL'
8..
U
mA
CUA~ENT.
'003
;
~
AVE~AGE ~LY
'Wti'
mA
mA
TA-aoc
TA-2IOC
~
CUft~ENT
1002
4m2
AVI~AGI
~LY
MAX
TVP}"
MIN
'ii'
'001
~1
,.
IUWL Y CUR~ENT
TEST
.
LIMIT
'Y~L
PR~
,gA_TIN
AV~AGE
CO~DtTIO~S
S~LYCURRENT
VOH',
(VIH'
voltage
posltillt
more
the
as
tMflned
"0"
Is
D.
A
Stresses
Voltage
- OOCto +700C: VDD . -15V ~5"', Vss - GND, tiPPW- t ~D1 = 400 nMe, t~D2 - 150 nsec,unlessotherwiw IP8cifJ8d
Logic
T
'COMMENT
-SSOC to +1soOC
VOlteges and Supply
WIth
Input
OOC
to
+700C
Ambient
Tem~rature
Under
BI..
Stor.ge
to
Absolute
_~ility.
5..nC~I",__out,
V.-12 V.-7.1V.-u,
v
SI"KING
OV
mA
VOUT
2.0
1.0
.
pUt.~VOO
_Id be.w:l.
LEVEL
"'"
PINS
CURRENT,
VOUT-OY.F_T2L
LEVEL
HIH
LI"U
,~
~
VO'loget
-G.5V
.
-O.5V
.
VOUT
LEVEL
I» FooT2L _'OI,'V
on ,h. I/O I.-
supply.01'-
74
5~
+5V!
VSS'
5~
-IOY!
VOO'
_x,mum
Vol..
VOUT
LEVEL
OUTPUT
LeVeL
PI"'
"0"
OUTPUT
"0"
RESISTANCE
5_"y
-6.5
=
Nom.neI
-
VIL
UI8d.
25OC
.
n
n
_Id
be
,~
'
...
..
~,..,i
C
-G.-V
'
JW
-
OUT
400
I'01.3- 10
ow-:"
V
,
,I
V
1.8
Kl1
V..-e..,
1.2
AOH4
A
lor
T
opl_..
..
"'lOUt
non.,"-,'..
(2)11
(11Typial-
.
VOLTAGE
'-0-'
SEAIAL
4003
OUT
AUtSTANCE
PAAALLEL-OUT
AOH3
LINES
110
4CKI3
V..-7..
VII-II
AEIISTA"CE
I
RoH2
j
O\n'PUT
VOLTAGE
LOW
L~
[ VO'-3 !
«»3
-.oom-
OUTPUT
OUTPUT
IOU'~
You
110
4001/2
OUTPUT
CUAAEm.
~
SEAIAL
4003
O\n'
SINKI~G
PARALLEL
OL3
OUT
4003
~
C.
D.
Typical
Characteristics
POWER
CURRENT
VS.TEMPERATURE
SUPPL
SUPPLY
POWER
V CURRENT
VS. TEMPERATURE
(4001)
(4002)
POWER
CURRENT
VS. TEMPERATURE
S
.S'
-
.-
.
'-
.
'WI.
(4003)
(4004)
SUPPLY
SUPPLY
POWER
CURRENT
VS. TEMPERATURE
6
5
u
~
~
~
--~~.
...
-,.."
1
...
z
-14.3V
~1&.O
--
.
...
~
VI
I
~
1
...
>
f:::::::
.
~
I.CI
80
TEMPERATURE
.0
AMBIENT
20
OUTPUT CURRENT VI.
OUTPUT VOLTAGE
OUTPUT CURRENT vs.
OUTPUT VOLTAGE
j
/+~
5
1.2
..\
t"N"t"O,-481,'OZ- '50-
I
11.0
;+7V'C
1
1
.. I
i
c
I
~
,
~
..
z
...
1.-
~TA..O'C
-11.OV
Voo"
1-
_,IS.av
~O-
7
.
I
(4003)
4002)
1.4
(4001.
I
I
y
~
~
a.-!
2
.' I
..
i
..
i
a
OUTPUT
-4
-5
-8
0
:00'7
-2
75
-3
-4
'-5
{VI
-3
OOTPUT
-2
(VI
-1
VOLTAGE
o
I
y-
VOlTAGE
8
.21
...
Characteristics
C.
A.
4004
4002,
-I&ViR.
VSS"GNO
--., --1--. -. ---
,~
~/2J4
-.TI~
I
MAx.
MN.
UMT
~
LIMIT
fP'C"+~;VDO"
TA'
4001,
"
.
2
'10
t
Cour - -pP f8 _1_ppf88YNC
'~ppf8CM-AOM
~
a..
-
CoUT
1O-"-CM.ftAM
,
y~
Cour-
.ppf8C~M
Cour-app
~
--
ft-
CII__IVNC
100
OCTH
18
~
.
_1
-
t:i
~
-/2
.
Cow-."
'~
_A._.
c..-,I-"---
T",
~
",-,.,/Ocou.
COU.-_x
~-,
n..-
, ".Ct
___1/0-
4004
Timing
Diagram
on AC Ch8rKteriitici _.
'
'..
Outpuuwith ~jng condition._ifiod
10.
- =1.-
-'101
r-"'" ,
ft-o~
fQH-
TA
.-SV~
.-IV
(00.D,.~.D3)
DAT.tN
.-1
IV
DATA_LINES
.-IV
ow
..f:.-:t:--.;~~p
.~
,-
our
I-
~
-,
..
~
..
tM
4002,
,
_OUTPUT
.-IV
.-IV
'0-
-'ow'
j
I-f-U.
.
"OM
r--
-tV
1-
'wc
;~~~:::-4HC
~---:~:\
-IV
LINES
OUTPUT
110
.-IV
-I'c""
\.
'IH
ICL)
LIM
~
CLEAR
t
4t
--V
;1~:::
.
-
78
OW
.~::r
~OUT
LINES
CM
~
'D~
" CM
IN. -tV
--
4001,
~
Characteristics
GND
~L~-DTM
~
WlOTH
T-.
_LAY
our
DATA
-
~yo-our-LAY
-
~
DAT~'
TO
~~
~YODATA8T_LAY
YO
~
_.
'.
HIGH
~
~
~
1m
~
~
..
~.,-
- '." -
-
TODATA
our -LAY
.-y
_111
3
_at
,.
~
1-.1
--.
10'-
.
.
~T~
--
TWf
UWT
C.
A.
4003
TA. O"C to +70OC;Voo . -15.t. 5%, V..
I
I
~.a..
CouT.a..
~
~AClT~
~
~.
F~
OUTPUT
VI.
LIMaI
n(DATA
I
'-'-.'._'._-.-'.
".. '...
.--
~
-J-~
~
~
I~I
~R~-
~
..
.
I$-
~-
-.
1_!
'I
...,
i-
~
~
r-;:;-
-
OATA
~/C
110
LINEI
~
I -x.
10
77
~-.,.
em
.IOLI-
-
-,
DATA
CAPACITA~I
a.. boaI/O-
. IYNCFOR~I
,
1 ,
I
J
TaT
CAPACITA-
»
CAP~ANQ
I~.c.,
...
j!-
.
"
Characteristics
lET
Load
Groondld.
CAPAcrT-
~1WUf
.
a.OCKlWUf
~/2
I~.~
NOTE 111Rot..10..11-.1Po...
""-
Typical
~
IWUTtll
CAP~A*I
-
I
CIN
01/2/3141
,
-
~I--
Pins
TYP.
Unnwalr8d
26OC;
A.
T
OV;
a
Vw
=
1
f
MHz;
Capacitance
u
,.
B18.
Input
Volt..
-ssoC
8nd Supply
Stm~
+1SOOC
to
+0.5 to -20'1
1.0
DlsslP8tlon
above
those
listed
,.
under
Absolute
Maximum
Ratings"
may cause permanent dam.
to the device. This Is a stms rating
only and functional operation of the device at these or .any other
condition above those indicated in the operational sections of this
specification Is not implied.
Volt8~
WIth ReSf)8Ct
to Vss
Po_r
.COMMENT
100C
Und8r
Temper8ture
W
Temt)8r8ture
*
+
Ambient
Star.
Ratings
to
Maximum
OOC
Absolute
Characteristics
Operating
and
C.
D.
4008,4009
TA = ~ to 7~, VSS-VOO[1]
= 15V:t5%,~~ = ~O1 = 400n5,~O2 -150nlunlellotherwi.l~cified.
Product
Typj2JI Max.
Min.
10
4008/9
Average Supply Current
4008
4009
Input High Voltage
4008/9
Clock Input Low Voltage
4008/9
ILl
I "put LeakageCurrent
Vin =Vss-16V.Pins
1.S(4008)
Pins 1-S, 11, 13-15 (4(X»)
TA a 25°C Unloaded
Vss
Vss
V
~
TestConditions
mA
20
10
13
VIH
'DO
Unit
IJA
mA
Paramete,
Symbol
-1.5
+0.3
Voo
VILC
Vss
v
-12.5
Input Low Voltage
1/0 Input Low Voltage
4009
VDD
V1L2
v
Pins 1-6 (4008), Pins 11, 15,
20-23(4009)
v
Pins 1-8, 16-19
v
Capacitive Load Only
-5.5
I/O)
Vss
(Except
Vss
4008/9
VDD
V1L1
-4.2
4008/9
Address Line Sinking
Current
4008
Chip Select and
F Il Sinking Current
4008
9
1.8
W Output SinkingCurrent
4008
2.5
DataBusSinkingCurrent
4009
9
15
1/0 and Strobe Outpjt
Sink ing Current
4009
5
"[6
12
T
ROH1
Output on Resistance
4008
0.8
1.2
ROH2
DataBusOutput On
4009
1:,)
250
ROH3
I/O n
Strobe OutpUt
on Resistance
4009
250
1000
Output
4008/9
Vss
-10
v
-4.86V
mA
mA
=
mA
12
8
I 13
! 2.5
5.0
~~~
VOUt=Vss
[4)
IOL3
IOL2
VoutSVss
mA
IOL1(3J
-12
-8.5
Vss
Vss
Output Low Voltage
VOL
=Vss : Pins20-23
=Vss
Vout
mA
"mA
Vout='18 -4.85V
kn
Vout=Vss-O.5V
n
VO4It
-Vss -2V. Pins20-23
esiS1ance
Current
16
n
Vout=Vss-2V, Pins9,10,16-19
VOU!-Vss -6V. All outputs on
mA
Clamp
ICF
R
IOU
~..Qb!--
mA
Vout
4008. Pins 9,10,16-19 (4009)
NQTES:
78
input.
TTL
the
8nd
outPut
add,..
the
betWMn
-jet
in
~_ility.
o>nnec18d
TTL
is
for
oh~
VDD
470
and
of
W
Pin
resistor
a
if
be~n
10-'
TTL
a
o>nnec18d
dri-
be
must
will
li,.s
resistor
add,..
6.8kohm
The
A
4.
3.
1. For TTL ~lnPItibility on the 1/0 lines.the supplyvolt8getshouldbe Vss a +5V :t;5~. VOD- -10V t 5~.
2. Typic81willes.. for TA a 250CM1dno~nallUpply wlf9S0
-
..-cifiC8~
id8ntiml
A.C.Characteristics
TA. ~ to7~, VSS-Voo
- 11V
t 5""Alldock,
sync.
CMROM,
~ b~.1nd
110
timng
with the 4001 Ind 4004.
P..met8,
Unit
-
~
\ ClockPeriod
4C8/4(X»
I
1.36'.
,.
4CXMI
4fD
~
.,
~
~
from
I Add,.. toOutp.rtDelay. A,. X,
r--~~..-;
"300
4cx.
,.
CL. 5OpF
nI
CL = 100pF
lIS
"'
~
~!~~I
-
r-a-
4C8
...
~,;;
~
Writ8
In
~
I
C L
I~-
0...
4CX»
\
0,1
twc
tFD
I
I F/L Output DeI8y
Oel8y
Output
I/O
I
..
1.0
480
lIS
nI
1.0
lIS
.
CL
..
CL
Delay
1CK»pF
-
2(K)
pF
on
d8t8
t...
:DpF
tl2
Strobe
.
CL.~pF
tl1
4CX»
~
~Strobe~~
O'UT
,
CL.25QpF
-
DeI8y
OutJJUt
w
I
I Otip SelectOutput D818y8t A 3
I CL -2&OpF
lIS
I~
tA2.
,..
...
I "A:CtCt,.to OutJJUtDeI.y A2
5OpF
Clodt
Delay
ClockDetey
from, to,
LfDf
,.
,.
,.
-
4CXMI4CD 400
~~
4(X8/4fD
1&0
4008
C/odt
!
4008/4CD
-
t~tfR~'"
Test Conditions
limit
Product
~
Symbol
..
A
I
~
Diagram
Timing
,
..
--
-~-~-
~4=
--r-'~:~,
---
.
---
.
-__'-__1GMTA~_.
-
=-"=:.~~~=§~
- - .- t=
:
'--~_1G-
78
.
.
-
MCS-4CUSTOM ROM ORDER FORM
4001 Metal Masked ROM
All custom ROM orders must be submitted on forms provided by Intel. Pr.ammlng
information should be sent
in the form of computer punched cards or punched papet'ta.-.
In either ce_, a print-out of the truth teble
must 8CU)mpenv the order. Refer to Intel's Dat8 Catalog for com~.te .-ttern Sf)8cifications. Alternativelv, the
STANDARD
INTEL
Additional forms ... awilable from Intel.
MARKING
accom.-nving truth t8ble n.V be u*.
Int81 P8t18rn
The marking as shown at right must contain the Intel logo,
Number
O1lp Number
or
Customer
Number
Code
(ZZ).
number
chip
the
for
substituted
be
may
0-
number
identification
customer
optional
An
(DD).
number
the product type (P4001), the four digit Intel pattern number (PPPP), a date code (XXXX), and the two digit chip
Optional Customer Number (Maximum 6 characters or spaces)
B.
I/O
OPTION
-
Specify the connection
numbers for e~h
1/0 pin (next ~).
DD)
-
15
through
0
from
number
any
-
specified
be
CHIP
(Must
OPTION
SPECIFICATIONS
NUMBER
A.
MASK
Exampl.
of some of the possible 1/0
options are shown below:
EXAMPLES - OESIREO OPTION/CONNECTIONS REQUIREO
1. Non-Inverting
output - 1 and3 - connec~.
2. Invertingoutput - 1 end4.re con~t8d.
3. Non-inV8rtlngInput (no Input r...ltor)
4.
Inverting
InpUt
(Input
r8ll8tor
to VSS)
- only
6 I. connec~.
- 2.e.7.endg-
cOnn8Ct8d.
5. Non-invertll)9 Input (Input r.~to VOO) - 2, 7, 8, .nd 10 .r. COnn8Cted.
8. If Inpu1l .nd output. er. ml.ed on 111...me PO". ttIe pin. ul8d . ttIe OUtputsmutt hev. 111.Intlt'nel r.".tor connec~ to .11II.r
VOO or Vss (8 .nd g or 8 end 10 mUIt be connected), Ttli. II ft8C_ry for t88t1ngpurpo... For ...mple, If ttler..,. tWo Invent"'
Inputs (with no Input r8ll.or)
.nd 2 nOn-fnverting outputs""
COnMction _uld
Inputs- 2.nd 8.re connect8d
Outputs - 1, 3,8 .nd g .r. conn8Ct8dor
1.3.8 end 10 - connected
If 111.pin. on . PO" .,. ell Inputs or .11outputs1fl8 In_ne! r."stor. do nOt tIC.
4001
CUSTOM
ROM
PATTERN
-
Programming
information
be rn8d8..
followe:
to be connected.
should be sent in the form of computer
punched
cards or punched paper tape. In either caR, a print-out of the truth table must accomp.,y the order. Refer to Intel's Data
Catalog for comptete pattern specificationL
Alternatively,
the ~companying
truth table may be u~.
Based on the par-
ticular customer pattern, the charactersshould be written as a "P" for a high level output - n-loglc "0" (negative logic "0")
or an "N" for a low level output - n-iogic "1" (negative logic "1").
Note that NOP . BPPPP PPPPF . ~
S)
0000
DATA
~-
Otmtn
~.'OD,
'MIl
_FE~
-Jou:;"
.
...0 I/O,
r-o-:T2--
~.
v.
.
~Ra
.
L--.9-.9
a
r
-4--
~
, 'M_'
::-1
.
to--v.
18
b. If ~~..
input~
w~
--Id t»
CIRCLE
NUMBERS.
(lIST
DESIRED
8. For r2l
',..-d. VOL.-e.S VoItI_~
SCHEMATIC)
compatibility
on tIw I/O lines IN _Iy
vall..-
--ad
be
Vco . -10V.5%.~ . +5V.5%
b. II non-~.. '-' 0Pt* il~. V'L . -8.5Yo"---;.,.,.., (,* TTll
.5%
+5V
.
Vss
.5%.
-IOV
.
Voo
8. Forr2L competobility
ontheI/O "".. the~y
ON
CONNECTIONS
SCHEMATIC)
ON
CONNECTIONS
CONNECTIONS
CIRCLE
a
NUMBERS
(LIST
OESIREO
CONNECTIONS
1/01 (PIN 15)
,.. TT1.1
,
CIRCLE
NUMBERS.
(LIST
DESIRED
SCHEMATIC)
ON
b. II .--~...
(,* TTLI
81
be
-.ould
volte.-
supply
the
lines
.5%
1/0
the
'5V
.
on
Vss
t5%.
competib'I,ty
T7l
-1OV
.
For
Voo
e.
be
won.-
supply
the
lInes
1/0
the
~Id
SCHEMATIC)
ON
on
compatIbIlity
T2L
For
Vco . -10V '5%. \/ss . +5V.5~
11«I.~ing inPUtOption
, v.L . -U Voila--If
b.
8.
CONNECTIONS
CONNECTIONS
CIRCLE
a
NUMBERS
(LIST
OESIREO
CONNECTIONS
CONNECTIONS
1/03 (PIN 13)
inP"tOption
it..-d. VIL. -e.&Volts--j~
In« TTll
ORDERING INFORMATION
PACKAGING INFORMATION
MC5-4
,.
The 4004 (CPU) is .,ailable in ceramic only and should be
ordered - C4004.
2. The 4001 (ROMI, 4002 (RAMI and 4003 (SRI are presently
.,ailable off the shelf in plastic only. Standard devicesshould be
ordered as follows:
P4001
PI_tic Pack.
P4002-1 (Metal Option #11 - PI_tic Package
P4002-2 (Metal Option #21 - Plastic Pack.
P4003 Plastic Pack.
3. The 4008 and 4009 standard ~mory and 1/0 interf- set are
.,ailable in plastic only (24 pin DIPI. They sh~ld be used as a
set and ordered
as P4~
and P4009.
4. M- Proer8nmine of the 4001
The custom pat1Bms,chip numbers and 1/0 options (including
inverting and non-inverting
inputs or ~tputs
and on-chip resistor
connected to ei1f1erVDD or Vssl must be $p8Cifiedon e tru1f1
table for each 4001 ordered. Blank custom tru1f1 tables are .,eilable upon request from Intel.
5. PA4-04 Pr0gr8mAn8iyzer
Complete MCS-4data bus activity m8V be monitored. To order,
sPecify
PA4-04.
6. In.11ec 4
IIOP_-~dock
pt
~OM
PACKAGE
DUAL
OUTLINE
- -- fa..
4(XI2I,
- for
fa..
i~l- - 40021
- _itY for- _10...
!r.~.
72 -Ie
Ext-
Un-
Prot-
:iiI
n...e.70
I
1mm8-781702A
PROM
~
-
17O2A
oi.-
for
-.ckotI
IncI..-
-
1~-8input...8QU_M8tIory
-
'-~
-
S-.
I
D8t8
4CXI2s
~
I/OPons
~OM
IN.lINE
'-III
~OW, -24
n...e.a
16-LEAD PLASTIC
4002.._oto forfa.. ~OMS.
I
In_1oIIIO8t8
CPU,
-
~OMO
_22
with
4
- I~I-
In_.
Pr-
C--
C8ttf8I
~A
...m4--42
The Intellec 4 and microcomputer modules must be
~ifi~
individually by product code:
~~-J
FORTRAN
IV and are availablevia time-sharingserviceor directly from
24-LEAD PLASTIC
IN-LINE
DUAL
in
_itten
are
prograrN
MCS-4
These
the
program.
7. MCS-4 Cro. ~b"
end Simul8tor SohW8r8 P8Ckag8
This software pecltege conWrtS a tist of instruction mnemonics
into machine instructions and then simulates the operation of
OUTLINE
PACKAGE
Intel.
.~"'.","
I
L---~~~~~~I
-
-
-
-
-
-
-
-
-
-
_D.
- ciJ11--_"-"~T-
--1-=1
~~
..-
:I--'"
..M'
~
-
82
.
;;
;j;..//.-
~
r..'
...
-~j..
Jl
01'
I I
""'t,,""_oaf
--1 ~_R.'
-
18
..
-l-
~
-L.--
~
MAX.
~
..
~
mo.'1
1---8--1
.."..,...,
~
MCS-4
TM
InstructionSet
(1"- i~
P'-.d.t by., ~
I")- 2~
~
tII8t,
2--
-
-
INSTRUCTIONS
~
.. ~I
~
MACHINE
~~.,-.0 0 0 .
.,AZA2"
"""
X2 -
KJ -..
,-~
RAM.
1M ,-
Cy*.
.
AJ.A2.A,.-_~~,--
-
---'
~_-;--~;R~.I»
-
2.A,
-
.
_.
'"
_ion
ow.,
...
..
-
I
-
-
-
0000
-
~
~
-
__~_RR.R
t'"
~
L--
~~; 0
0
0
I
~
~
.
.
to.
'0
--
~
-
~
..
..
~
-
.
~-'-'--~---"-'
~---*
,
I 0
.
. . t t
I
~!
.
-
or_..
00
'-!..:!-'
;.
-
Iwr_Of_UT-
--.
--.
---~
--'~."/OL-
. I 0I
I
-
R_-
.
.. ,0
.
-
5=-~~::==
--
0001
~~U..-:r
. - -..
IIO
~0
-
--
R-
-
I/O
..
..
OR
--,
-
RAW.
-
AM)RAM
INSTRUCTIONS
INPUT/OUTPUT
In..
-0.
At
At
At
I""
~~~~
I
~
At
I
At
OSZ_.II-
R
R
R
R
I__"~
R
'R
.
,
~
R
.
,
.
,
.
~~~~
.,.,.,.,
,
.
.-
-
A
.
-~-~-_.
"_-~__M~
---
.:-+
--
DJ.O,
~.R..2t
-
-~
-
-
,
-
At
A,
A,
At
-WOM-
0010
~
--
0 0 I 0
DzD,DzDt
~___AI~~a,.A,A,
A,A,,--a---C,c,CJC4"1
c,c,ea~
"-_.~'
I
.0..
.~
0000
.,.
~-
_~W_RAn~
~Dt°.~
-
~~~__RAM__J_~--.
,-~4M_--3-_~.
I
...~~.
INTEL
CORPORATION,
Microcomputers.
first from the beginning.
3065 Bowers Avenue, Santa Clara, California
95051
C> Intel
.
(408) 246-7501
1974/Printed
in U.S.A./MC5-219-oS74/25K
Source Exif Data:
File Type : PDF File Type Extension : pdf MIME Type : application/pdf PDF Version : 1.6 Linearized : Yes Encryption : Standard V2.3 (128-bit) User Access : Print, Copy, Extract, Print high-res XMP Toolkit : 3.1-702 Create Date : 2006:10:27 11:09:26Z Modify Date : 2006:11:08 15:21:08-08:00 Metadata Date : 2006:11:08 15:21:08-08:00 Format : application/pdf Creator : Intel Corporation Title : MCS-4 Description : MCS-4 Producer : Hewlett-Packard Intelligent Scanning Technology.3 Document ID : uuid:095efa17-5521-402a-ad46-0a45f25723c1 Instance ID : uuid:8ff86a50-e252-4393-8aa5-2f31c90edd4b Page Count : 88 Subject : MCS-4 Author : Intel CorporationEXIF Metadata provided by EXIF.tools