N RF51 Series Reference Manual V2.0

• 1 About this document
  • 1.1 Writing conventions
    • 1.1.1 Peripheral naming and abbreviations
    • 1.1.2 Register tables
• 2 System overview
  • 2.1 Block diagram
  • 2.2 System blocks
    • 2.2.1 ARM® Cortextm-M0
    • 2.2.2 2.4 GHz radio
    • 2.2.3 Power management
    • 2.2.4 PPI system
    • 2.2.5 Debugger support
• 3 CPU
• 4 Memory
  • 4.1 Functional description
    • 4.1.1 Memory categories
    • 4.1.2 Memory types
    • 4.1.3 Code memory
    • 4.1.4 Random Access Memory (RAM)
    • 4.1.5 Peripheral registers
  • 4.2 Instantiation
• 5 Non-Volatile Memory Controller (NVMC)
  • 5.1 Functional description
    • 5.1.1 Writing to the NVM
    • 5.1.2 Writing to User Information Configuration Registers
    • 5.1.3 Erasing User Information Configuration Registers
    • 5.1.4 Erase all
    • 5.1.5 Erasing a page in code region 1
    • 5.1.6 Erasing a page in code region 0
    • 5.1.7 Availability of erase operations based on presence of pre-programmed factory code
  • 5.2 Registers
    • 5.2.1 READY
    • 5.2.2 CONFIG
    • 5.2.3 ERASEALL
    • 5.2.4 ERASEUICR
    • 5.2.5 ERASEPAGE/ERASEPCR1
    • 5.2.6 ERASEPCR0
• 6 Factory Information Configuration Registers (FICR)
  • 6.1 Functional description
    • 6.1.1 Override parameters
  • 6.2 Registers
    • 6.2.1 CODEPAGESIZE
    • 6.2.2 CODESIZE
    • 6.2.3 CLENR0
    • 6.2.4 PPFC
    • 6.2.5 NUMRAMBLOCK
    • 6.2.6 SIZERAMBLOCK[n] (n=0..3)
    • 6.2.7 CONFIGID
    • 6.2.8 DEVICEID[0]
    • 6.2.9 DEVICEID[1]
    • 6.2.10 ER[n] (n=0..3)
    • 6.2.11 IR[n] (n=0..3)
    • 6.2.12 DEVICEADDRTYPE
    • 6.2.13 DEVICEADDR[0]
    • 6.2.14 DEVICEADDR[1]
    • 6.2.15 OVERRIDDEN
    • 6.2.16 NRF_1MBIT[n] (n=0..4)
    • 6.2.17 BLE_1MBIT[n] (n=0..4)
• 7 User Information Configuration Registers (UICR)
  • 7.1 Functional description
  • 7.2 Registers
    • 7.2.1 CLENR0
    • 7.2.2 RBPCONF
    • 7.2.3 XTALFREQ
    • 7.2.4 FWID
• 8 Memory Protection Unit (MPU)
  • 8.1 Functional description
    • 8.1.1 Inputs
    • 8.1.2 Output
    • 8.1.3 Output decision table
    • 8.1.4 Exceptions from table
    • 8.1.5 NVM protection blocks
  • 8.2 Registers
    • 8.2.1 PERR0
    • 8.2.2 RLENR0
    • 8.2.3 PROTENSET0
    • 8.2.4 PROTENSET1
    • 8.2.5 DISABLEINDEBUG
• 9 Peripheral interface
  • 9.1 Functional description
    • 9.1.1 Peripheral ID
    • 9.1.2 Bit set and clear
    • 9.1.3 Tasks
    • 9.1.4 Events
    • 9.1.5 Shortcuts
    • 9.1.6 Interrupts
  • 9.2 Register overview tables
• 10 Debugger Interface (DIF)
  • 10.1 Functional description
    • 10.1.1 Normal mode
    • 10.1.2 Debug interface mode
    • 10.1.3 Resuming normal mode
• 11 Power management (POWER)
  • 11.1 Functional description
    • 11.1.1 Power supply
    • 11.1.2 System OFF mode
    • 11.1.3 System ON mode
    • 11.1.4 Power supply supervisor
    • 11.1.5 RAM blocks
    • 11.1.6 Reset
  • 11.2 Registers
    • 11.2.1 RESETREAS
    • 11.2.2 SYSTEMOFF
    • 11.2.3 GPREGRET
    • 11.2.4 POFCON
    • 11.2.5 RAMON
    • 11.2.6 RESET
    • 11.2.7 DCDCEN
• 12 Clock management (CLOCK)
  • 12.1 Functional description
    • 12.1.1 Low frequency clock (LFCLK)
    • 12.1.2 High frequency clock (HFCLK)
    • 12.1.3 Calibrating the 32.768 kHz RC oscillator
  • 12.2 Registers
    • 12.2.1 HFCLKSTAT
    • 12.2.2 LFCLKSRC
    • 12.2.3 LFCLKSTAT
    • 12.2.4 CTIV
    • 12.2.5 XTALFREQ
• 13 GPIO
  • 13.1 Functional description
  • 13.2 Registers
    • 13.2.1 OUT
    • 13.2.2 IN
    • 13.2.3 OUTSET
    • 13.2.4 OUTCLR
    • 13.2.5 DIR
    • 13.2.6 DIRSET
    • 13.2.7 DIRCLR
    • 13.2.8 PIN_CNF[n] (n=0..31)
• 14 GPIO tasks and events (GPIOTE)
  • 14.1 Functional description
    • 14.1.1 Pin events and tasks
    • 14.1.2 Port event
  • 14.2 Registers
    • 14.2.1 CONFIG[n] (n=0..3)
• 15 Programmable Peripheral Interconnect (PPI)
  • 15.1 Functional description
    • 15.1.1 Pre-programmed channels
  • 15.2 Registers
    • 15.2.1 CHEN
    • 15.2.2 CHENSET
    • 15.2.3 CHENCLR
    • 15.2.4 CH[n].EEP (n=0..15)
    • 15.2.5 CH[n].TEP (n=0..15)
    • 15.2.6 CHG[n] (n=0..3)
• 16 2.4 GHz radio (RADIO)
  • 16.1 Functional description
    • 16.1.1 EasyDMA
    • 16.1.2 Packet configuration
    • 16.1.3 Maximum packet length
    • 16.1.4 Address configuration
    • 16.1.5 Received Signal Strength Indicator (RSSI)
    • 16.1.6 Data whitening
    • 16.1.7 CRC
    • 16.1.8 Radio states
    • 16.1.9 Maximum consecutive transmission time
    • 16.1.10 Transmit sequence
    • 16.1.11 Receive sequence
    • 16.1.12 Interframe spacing
    • 16.1.13 Device address match
    • 16.1.14 Bit counter
    • 16.1.15 Override registers
  • 16.2 Register
    • 16.2.1 SHORTS
    • 16.2.2 CRCSTATUS
    • 16.2.3 RXMATCH
    • 16.2.4 RXCRC
    • 16.2.5 PACKETPTR
    • 16.2.6 TXPOWER
    • 16.2.7 MODE
    • 16.2.8 PCNF0
    • 16.2.9 PCNF1
    • 16.2.10 BASE0
    • 16.2.11 BASE1
    • 16.2.12 PREFIX0
    • 16.2.13 PREFIX1
    • 16.2.14 TXADDRESS
    • 16.2.15 RXADDRESSES
    • 16.2.16 CRCCNF
    • 16.2.17 CRCPOLY
    • 16.2.18 CRCINIT
    • 16.2.19 FREQUENCY
    • 16.2.20 TEST
    • 16.2.21 RSSISAMPLE
    • 16.2.22 STATE
    • 16.2.23 DATAWHITEIV
    • 16.2.24 DAI
    • 16.2.25 TIFS
    • 16.2.26 DAB[n] (n=0..7)
    • 16.2.27 DAP[n] (n=0..7)
    • 16.2.28 DACNF
    • 16.2.29 BCC
    • 16.2.30 OVERRIDE[n] (n=0..3)
    • 16.2.31 OVERRIDE[4]
    • 16.2.32 POWER
• 17 Timer/counter (TIMER)
  • 17.1 Functional description
    • 17.1.1 Compare
    • 17.1.2 Capture
    • 17.1.3 Task priority
    • 17.1.4 Task delays
  • 17.2 Registers
    • 17.2.1 SHORTS
    • 17.2.2 MODE
    • 17.2.3 PRESCALER
    • 17.2.4 BITMODE
• 18 Real Time Counter (RTC)
  • 18.1 Functional description
    • 18.1.1 Clock Source
    • 18.1.2 Resolution versus overflow and the PRESCALER
    • 18.1.3 The COUNTER register
    • 18.1.4 Overflow features
    • 18.1.5 The TICK event
    • 18.1.6 Event Control feature
    • 18.1.7 Compare feature
    • 18.1.8 TASK and EVENT jitter/delay
    • 18.1.9 Reading the COUNTER register
  • 18.2 Registers
    • 18.2.1 EVTEN
    • 18.2.2 EVTENSET
    • 18.2.3 EVTENCLR
    • 18.2.4 COUNTER
    • 18.2.5 PRESCALER
    • 18.2.6 CC[N] (n=0..3)
• 19 Watchdog timer (WDT)
  • 19.1 Functional description
    • 19.1.1 Reload criteria
    • 19.1.2 Temporarily pausing the watchdog
    • 19.1.3 Watchdog reset
  • 19.2 Registers
    • 19.2.1 RUNSTATUS
    • 19.2.2 REQSTATUS
    • 19.2.3 CRV
    • 19.2.4 RREN
    • 19.2.5 CONFIG
    • 19.2.6 RR[n] (n=0..7)
• 20 Random Number Generator (RNG)
  • 20.1 Functional description
    • 20.1.1 Digital error correction
    • 20.1.2 Speed
  • 20.2 Registers
    • 20.2.1 SHORTS
    • 20.2.2 VALUE
    • 20.2.3 CONFIG
• 21 Temperature sensor (TEMP)
  • 21.1 Functional description
  • 21.2 Registers
    • 21.2.1 TEMP
• 22 AES Electronic Codebook Mode Encryption (ECB)
  • 22.1 Functional description
    • 22.1.1 EasyDMA
    • 22.1.2 ECB Data Structure
    • 22.1.3 Shared resources
  • 22.2 Registers
    • 22.2.1 ECBDATAPTR
• 23 AES CCM Mode Encryption (CCM)
  • 23.1 Functional description
    • 23.1.1 Encryption
    • 23.1.2 Decryption
    • 23.1.3 AES CCM and RADIO concurrent operation
    • 23.1.4 Encrypting packets on-the-fly in radio transmit mode
    • 23.1.5 Decrypting packets on-the-fly in radio receive mode
    • 23.1.6 CCM data structure
    • 23.1.7 EasyDMA and ERROR event
    • 23.1.8 Shared resources
  • 23.2 Registers
    • 23.2.1 SHORTS
    • 23.2.2 MICSTATUS
    • 23.2.3 ENABLE
    • 23.2.4 MODE
    • 23.2.5 CNFPTR
    • 23.2.6 INPTR
    • 23.2.7 OUTPTR
    • 23.2.8 SCRATCHPTR
• 24 Accelerated Address Resolver (AAR)
  • 24.1 Functional description
    • 24.1.1 Resolving a resolvable address
    • 24.1.2 Use case example for chaining RADIO packet reception with resolving addresses with the AAR
    • 24.1.3 IRK data structure
    • 24.1.4 EasyDMA
    • 24.1.5 Shared resources
  • 24.2 Registers
    • 24.2.1 STATUS
    • 24.2.2 ENABLE
    • 24.2.3 NIRK
    • 24.2.4 IRKPTR
    • 24.2.5 ADDRPTR
    • 24.2.6 SCRATCHPTR
• 25 Serial Peripheral Interface (SPI) Master
  • 25.1 SPI master - functional description
    • 25.1.1 SPI master mode pin configuration
    • 25.1.2 Shared resources
    • 25.1.3 SPI master transaction sequence
  • 25.2 Registers
    • 25.2.1 RXD
    • 25.2.2 TXD
    • 25.2.3 ENABLE
    • 25.2.4 PSELSCK
    • 25.2.5 PSELMOSI
    • 25.2.6 PSELMISO
    • 25.2.7 CONFIG
    • 25.2.8 FREQUENCY
• 26 SPI Slave (SPIS)
  • 26.1 Pin configuration
  • 26.2 Shared resources
  • 26.3 EasyDMA
  • 26.4 SPI slave operation
  • 26.5 Registers
    • 26.5.1 SHORTS
    • 26.5.2 ENABLE
    • 26.5.3 SEMSTAT
    • 26.5.4 STATUS
    • 26.5.5 RXDPTR
    • 26.5.6 TXDPTR
    • 26.5.7 PSELCSN
    • 26.5.8 PSELSCK
    • 26.5.9 PSELMOSI
    • 26.5.10 PSELMISO
    • 26.5.11 CONFIG
    • 26.5.12 DEF
    • 26.5.13 ORC
    • 26.5.14 MAXRX
    • 26.5.15 MAXTX
    • 26.5.16 AMOUNTRX
    • 26.5.17 AMOUNTTX
• 27 I2C compatible Two Wire Interface (TWI)
  • 27.1 Functional description
  • 27.2 Master mode pin configuration
  • 27.3 Shared resources
  • 27.4 Master write sequence
  • 27.5 Master read sequence
  • 27.6 Master repeated start sequence
  • 27.7 Registers
    • 27.7.1 SHORTS
    • 27.7.2 ERRORSRC
    • 27.7.3 ENABLE
    • 27.7.4 PSELSCL
    • 27.7.5 PSELSDA
    • 27.7.6 RXD
    • 27.7.7 TXD
    • 27.7.8 FREQUENCY
    • 27.7.9 ADDRESS
• 28 Universal Asynchronous Receiver/Transmitter (UART)
  • 28.1 Functional description
  • 28.2 Pin configuration
  • 28.3 Shared resources
  • 28.4 Transmission
  • 28.5 Reception
  • 28.6 Error conditions
  • 28.7 Using the UART without flow control
  • 28.8 Parity configuration
  • 28.9 Registers
    • 28.9.1 RXD
    • 28.9.2 TXD
    • 28.9.3 ENABLE
    • 28.9.4 PSELRTS
    • 28.9.5 PSELTXD
    • 28.9.6 PSELCTS
    • 28.9.7 PSELRXD
    • 28.9.8 ERRORSRC
    • 28.9.9 CONFIG
    • 28.9.10 BAUDRATE
• 29 Quadrature Decoder (QDEC)
  • 29.1 Functional description
    • 29.1.1 Pin configuration
    • 29.1.2 Sampling and decoding
    • 29.1.3 LED output
    • 29.1.4 Debounce filters
    • 29.1.5 Accumulators
    • 29.1.6 Output/input pins
  • 29.2 Registers
    • 29.2.1 Shorts
    • 29.2.2 ENABLE
    • 29.2.3 LEDPOL
    • 29.2.4 SAMPLEPER
    • 29.2.5 SAMPLE
    • 29.2.6 REPORTPER
    • 29.2.7 ACC
    • 29.2.8 ACCREAD
    • 29.2.9 PSELLED
    • 29.2.10 PSELA
    • 29.2.11 PSELB
    • 29.2.12 LEDPRE
    • 29.2.13 DBFEN
    • 29.2.14 ACCDBL
    • 29.2.15 ACCDBLREAD
• 30 Analog to Digital Converter (ADC)
  • 30.1 Functional description
    • 30.1.1 Configuration
    • 30.1.2 Usage
    • 30.1.3 One-shot / continuous operation
    • 30.1.4 Pin configuration
    • 30.1.5 Shared resources
  • 30.2 Registers
    • 30.2.1 BUSY
    • 30.2.2 ENABLE
    • 30.2.3 CONFIG
    • 30.2.4 RESULT
• 31 Low Power Comparator (LPCOMP)
  • 31.1 Functional description
  • 31.2 Pin configuration
  • 31.3 Shared resources
  • 31.4 Registers
    • 31.4.1 SHORTS
    • 31.4.2 ENABLE
    • 31.4.3 RESULT
    • 31.4.4 PSEL
    • 31.4.5 REFSEL
    • 31.4.6 EXTREFSEL
    • 31.4.7 ANADETECT
• Appendix A: SoftDevice architecture
  • SoC library
  • SoftDevice Manager
  • Protocol stack
  • Application Program Interface (API)
  • Memory isolation and run-time protection
  • Call stack
  • Heap
  • Peripheral run-time protection
  • Exception (interrupt) management with a SoftDevice
  • Interrupt forwarding to the application
  • Events - SoftDevice to application
  • SoftDevice enable and disable
  • Power management
  • Error handling