UltraScale+ FPGA Product Tables And Selection Guide Ultrascale Plus
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© Copyright 2015–2017 Xilinx . Footprint compatible with 20nm UltraScale Devices with same footprint identifier KU3P 356 325 163 4.7 12.7 13.5 4 1,368 1 0 0 96 208 0 16 -1 -2 -2L -3 -1 -1L -2 96, 208, 0, 16 48, 208, 0, 16 72, 208, 0, 16 96, 208, 0, 16 KU5P KU9P KU11P KU13P 475 600 653 747 434 548 597 683 217 274 299 341 6.1 8.8 9.1 11.3 16.9 32.1 21.1 26.2 18.0 0 22.5 31.5 4 4 8 4 1,824 2,520 2,928 3,528 1 0 4 0 0 0 1 0 1 0 2 0 96 96 96 96 208 208 416 208 0 28 32 28 16 0 20 0 -1 -2 -2L -3 -1 -2 -2L -3 -1 -2 -2L -3 -1 -2 -2L -3 -1 -1L -2 -1 -1L -2 -1 -1L -2 -1 -1L -2 HD I/O, HP I/O, GTH 16.3Gb/s, GTY 32.75Gb/s 96, 208, 0, 16 48, 208, 0, 16 72, 208, 0, 16 96, 208, 0, 16 96, 312, 16, 0 96, 208, 28, 0 96, 208, 28, 0 48, 416, 20, 8 96, 416, 32, 20 Notes: 1. -2LE (Tj = 0°C to 110°C). For more details, see the Ordering Information section in DS890, UltraScale Architecture and Product Overview. 2. Maximum achievable performance is device and package dependent; consult the associated data sheet for details. 3. For full part number details, see the Ordering Information section in DS890, UltraScale Architecture and Product Overview. 4. GTY transceiver line rates are package limited: B784 to 12.5 Gb/s; A676, D900, and A1156 to 16.3 Gb/s. Refer to data sheet for details. 5. The B784 package is only offered in 0.8mm ball pitch. All other packages are 1.0mm ball pitch. Page 2 © Copyright 2015–2017 Xilinx . KU15P 1,143 1,045 523 9.8 34.6 36.0 11 1,968 5 4 4 96 572 44 32 -1 -2 -2L -3 -1 -1L -2 48, 468, 20, 8 96, 416, 32, 24 96, 416, 44, 32 96, 572, 32, 24 Kintex® UltraScale+™ FPGAs Device Name System Logic Cells (K) Logic CLB Flip-Flops (K) CLB LUTs (K) Max. Distributed RAM (Mb) Memory Total Block RAM (Mb) UltraRAM (Mb) Clocking Clock Mgmt Tiles (CMTs) DSP Slices Integrated PCIe® Gen3 x16 / Gen4 x8 IP 150G Interlaken 100G Ethernet w/RS-FEC Max. Single-Ended HD I/Os Max. Single-Ended HP I/Os I/O GTH 16.3Gb/s Transceivers GTY 32.75Gb/s Transceivers Extended(1) Speed Grades Industrial (2, 3) Footprint Dimensions (mm) (4) B784 23x23(5) A676(4) 27x27 B676 27x27 (4) D900 31x31 E900 31x31 A1156(4) 35x35 E1517 40x40 A1760 42.5x42.5 E1760 42.5x42.5 Footprint compatible with 20nm UltraScale Devices with same footprint identifier Notes: 1. A CCIX port requires the use of a PCIe Gen3 x16 / Gen4 x8 block. 2. -2LE (Tj = 0°C to 110°C). For more details, see the Ordering Information section in DS890, UltraScale Architecture and Product Overview. 3. For full part number details, see DS890, UltraScale Architecture and Product Overview. Page 3 Virtex® UltraScale+™ FPGAs VU3P VU5P VU7P VU9P VU11P VU13P Device Name VU31P VU33P VU35P VU37P 862 1,314 1,724 2,586 2,835 3,780 962 962 1,907 2,852 System Logic Cells (K) 788 1,201 1,576 2,364 2,592 3,456 879 879 1,743 2,607 CLB Flip-Flops (K) 394 601 788 1,182 1,296 1,728 440 440 872 1,304 CLB LUTs (K) 12.0 18.3 24.1 36.1 36.2 48.3 12.5 12.5 24.6 36.7 Max. Distributed RAM (Mb) 25.3 36.0 50.6 75.9 70.9 94.5 23.6 23.6 47.3 70.9 Total Block RAM (Mb) 90.0 132.2 180.0 270.0 270.0 360.0 90.0 90.0 180.0 270.0 UltraRAM (Mb) – – – – – – HBM DRAM (GB) 4 8 8 8 – – – – – – HBM AXI Interfaces 32 32 32 32 4 4 8 12 10 20 20 30 12 16 Clock Mgmt Tiles (CMTs) 2,280 3,474 4,560 6,840 9,216 12,288 DSP Slices 2,880 2,880 5,952 9,024 7.1 10.8 14.2 21.3 28.7 38.3 Peak INT8 DSP (TOP/s) 8.9 8.9 18.6 28.1 2 4 4 6 3 4 PCIe® Gen3 x16 / Gen4 x8 4 4 5 6 – – – – – – CCIX Ports(1) 4 4 4 4 3 4 6 9 6 8 150G Interlaken 0 0 2 4 3 4 6 9 9 12 2 2 5 8 100G Ethernet w/ RS-FEC 520 832 832 832 624 832 208 208 416 624 Max. Single-Ended HP I/Os 40 80 80 120 96 128 32 32 64 96 GTY 32.75Gb/s Transceivers Extended(2) -1 -2 -2L -3 -1 -2 -2L -3 -1 -2 -2L -3 -1 -2 -2L -3 -1 -2 -2L -3 -1 -2 -2L -3 -1 -2 -2L -3 -1 -2 -2L -3 -1 -2 -2L -3 -1 -2 -2L -3 -1 -2 -1 -2 -1 -2 -1 -2 -1 -2 -1 -2 – – – – Industrial Footprint(3,4) Dimensions (mm) HP I/O, GTY 32.75Gb/s C1517 40x40 520, 40 F1924(5) 45x45 624, 64 47.5x47.5 832, 52 832, 52 832, 52 A2104 52.5x52.5(6) 832, 52 47.5x47.5 702, 76 702, 76 702, 76 572, 76 B2104 52.5x52.5(6) 702, 76 47.5x47.5 416, 80 416, 80 416, 104 416, 96 C2104 52.5x52.5(6) 416, 104 47.5x47.5 676, 76 572, 76 D2104 52.5x52.5(6) 676, 76 A2577 52.5x52.5 448, 120 448, 96 448, 128 208, 32 H1924 45x45 208, 32 416, 64 H2104 47.5x47.5 416, 64 624, 96 H2892 55x55 4. All packages are 1.0mm ball pitch. 5. The GTY transceiver line rate in the F1924 footprint is package limited to 16.3Gb/s. Refer to data sheet for details. 6. These 52.5x52.5mm packages have the same PCB ball footprint as the 47.5x47.5mm packages and are footprint compatible. © Copyright 2015–2017 Xilinx . UltraScale Architecture Migration Table UltraScale and UltraScale+ families provide footprint compatibility to enable users to migrate designs from one device or family to another. Any two packages with the same footprint identifier code are footprint compatible. Kintex® UltraScale™ Pkg Kintex UltraScale+™ Virtex® UltraScale Virtex UltraScale+ mm KU025 A784 23 B784 23 A676 27 B676 27 A900 31 D900 31 E900 31 A1156 35 A1517 40 C1517 40 D1517 40 E1517 40 A1760 42.5 B1760 42.5 E1760 42.5 D1924 45 F1924 45 A2104 47.5(1) B2104 47.5(1) C2104 47.5(1) D2104 47.5(1) B2377 50 A2577 52.5 A2892 55 KU035 KU040 X X X X X X KU060 KU085 KU095 KU115 KU3P KU5P X X X X X X KU9P KU11P X X X X X X KU15P VU065 VU080 VU095 VU125 X X X X X X X X X VU160 VU190 VU440 VU3P VU5P VU7P VU9P VU11P X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X Legend X X Device X Migration Path X Notes: 1.The body size of the VU13P device in the A2104, B2104, C2104, and D2104 packages is 52.5mm. These packages are footprint compatible with the corresponding 47.5mm body size packages. See UG583, UltraScale Architecture PCB Design User Guide for important migration details. 2.Virtex UltraScale+ HBM devices migrate among each other but do not migrate to other devices. Page 4 VU13P X X X KU13P © Copyright 2015–2017 Xilinx . Kintex® UltraScale+™ FPGA Speed Grades Industrial Extended(2) Device Name(1) Speed Grade KU3P KU5P KU9P KU11P KU13P KU15P -1 -2 -2L -3 -1 -1L -2 Notes: 1. For full part number details, see the Ordering Information section in DS890, UltraScale Architecture and Product Overview. 2.-2LE (Tj = 0°C to 110°C). For more details, see the Ordering Information section in DS890, UltraScale Architecture and Product Overview. :: available – :: not offered Page 5 © Copyright 2015–2017 Xilinx . Virtex® UltraScale+™ FPGA Speed Grades Device Name(1) VU3P VU5P VU7P VU9P VU11P VU13P VU31P VU33P VU35P VU37P -1 -2 -2L -3 -1 – – – – -2 – – – – Industrial Extended(2) Speed Grade Notes: 1. For full part number details, see the Ordering Information section in DS890, UltraScale Architecture and Product Overview. 2.-2LE (Tj = 0°C to 110°C). For more details, see the Ordering Information section in DS890, UltraScale Architecture and Product Overview. :: available – :: not offered Page 6 © Copyright 2015–2017 Xilinx . UltraScale+ Device Ordering Information Footprint XC V U # P Xilinx Commercial V: Virtex UltraScale Value Denotes K: Kintex Index UltraScale+ Device -1 Speed Grade -1 = Slowest -L1 = Low Power -2 = Mid -L2 = Low Power -3 = Fastest F L F: Flip-Chip (1.0mm) S: Flip-Chip (0.8mm) V A F: Lid V: RoHS 6/6 Package L: Lid SSI G: RoHS 6/6 Designator B: Lidless w/ Exemption 15 S: Lidless SSI Stiffener H: Overhang SSI I: Overhang Lidless SSI Stiffener # Package Pin Count E Temperature Grade (E, I) E = Extended (Tj = 0°C to +100°C) I = Industrial (Tj = –40°C to +100°C) For valid part/package combinations, go to DS890, UltraScale Architecture and Product Overview: Device-Package Combinations and Maximum I/Os Tables Important: Verify all data in this document with the device data sheets found at www.xilinx.com Page 7 © Copyright 2015–2017 Xilinx . References DS890, UltraScale™ Architecture and Product Overview DS922, Kintex® UltraScale+™ FPGAs Data Sheet: DC and AC Switching Characteristics DS923, Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics UG570, UltraScale Architecture Configuration User Guide UG571, UltraScale Architecture SelectIO™ Resources User Guide UG572, UltraScale Architecture Clocking Resources User Guide UG573, UltraScale Architecture Memory Resources User Guide UG574, UltraScale Architecture Configurable Logic Block User Guide UG575, UltraScale and UltraScale+ FPGAs Packaging and Pinouts Product Specification UG576, UltraScale Architecture GTH Transceivers User Guide UG578, UltraScale Architecture GTY Transceivers User Guide UG579, UltraScale Architecture DSP Slice User Guide UG580, UltraScale Architecture System Monitor User Guide UG583, UltraScale Architecture PCB Design User Guide PG150, UltraScale Architecture-Based FPGAs Memory IP Product Guide PG182, UltraScale FPGAs Transceivers Wizard Product Guide Page 8 © Copyright 2015–2017 Xilinx . Important: Verify all data in this document with the device data sheets found at www.xilinx.com XMP103 (v1.11)
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