UltraScale+ FPGA Product Tables And Selection Guide Ultrascale Plus

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Page 2

Notes:

1. -2LE (Tj = 0°C to 110°C). For more details, see the Ordering Information section in DS890, UltraScale Architecture and Product Overview.

2. Maximum achievable performance is device and package dependent; consult the associated data sheet for details.

3. For full part number details, see the Ordering Information section in DS890, UltraScale Architecture and Product Overview.

4. GTY transceiver line rates are package limited: B784 to 12.5 Gb/s; A676, D900, and A1156 to 16.3 Gb/s. Refer to data sheet for details.

5. The B784 package is only offered in 0.8mm ball pitch. All other packages are 1.0mm ball pitch.

Device Name

KU3P KU5P KU9P KU11P KU13P KU15P

Logic

System Logic Cells (K)

356 475 600 653 747 1,143

CLB Flip-

Flops (K)

325 434 548 597 683 1,045

CLB

LUTs (K)

163 217 274 299 341 523

Memory

Max. Distributed RAM

(Mb)

4.7 6.1 8.8 9.1 11.3 9.8

Total Block RAM (Mb)

12.7 16.9 32.1 21.1 26.2 34.6

UltraRAM

(Mb)

13.5 18.0 0 22.5 31.5 36.0

Clocking Clock Mgmt

Tiles (CMTs)

4448411

Integrated

DSP Slices

1,368 1,824 2,520 2,928 3,528 1,968

PCIe®

Gen3 x16 / Gen4 x8

110405

150G Interlaken

000104

100G Ethernet w/RS-

FEC

010204

I/O

Max. Single-

Ended HD I/Os

96 96 96 96 96 96

Max. Single-

Ended HP I/Os

208 208 208 416 208 572

GTH 16.3Gb/s

Transceivers

0 0 28 32 28 44

GTY 32.75Gb/s

Transceivers

16 16 020 032

Speed Grades

Extended

(1)

-1 -2 -2L -3 -1 -2 -2L -3 -1 -2 -2L -3 -1 -2 -2L -3 -1 -2 -2L -3 -1 -2 -2L -3

Industrial

-1 -1L -2 -1 -1L -2 -1 -1L -2 -1 -1L -2 -1 -1L -2 -1 -1L -2

Footprint(2, 3)

Dimensions

(

mm)

HD I/O, HP I/O, GTH 16.3Gb/s, GTY 32.75Gb/s

Footprint compatible with 20nm

UltraScale Devices with same

footprint identifier

B784(4) 23x23(5) 96, 208, 0, 16 96, 208, 0, 16

A676(4) 27x27 48, 208, 0, 16 48, 208, 0, 16

B676 27x27 72, 208, 0, 16 72, 208, 0, 16

D900(4) 31x31 96, 208, 0, 16 96, 208, 0, 16 96, 312, 16, 0

E900 31x31 96, 208, 28, 0

96, 208, 28, 0

A1156(4) 35x35 48, 416, 20, 8 48, 468, 20, 8

E1517 40x40

96, 416, 32, 20

96, 416, 32, 24

A1760 42.5x42.5

96, 416, 44, 32

E1760 42.5x42.5

96, 572, 32, 24

Kintex® UltraScale+™ FPGAs

Page 3

Virtex® UltraScale+™ FPGAs

Device

Name

VU3P VU5P VU7P VU9P VU11P VU13P VU31P VU33P VU35P VU37P

System Logic Cells (K)

862 1,314 1,724 2,586 2,835 3,780 962 962 1,907 2,852

CLB Flip-

Flops (K)

788 1,201 1,576 2,364 2,592 3,456 879 879 1,743 2,607

CLB

LUTs (K)

394 601 788 1,182 1,296 1,728 440 440 872 1,304

Max. Distributed RAM

(Mb)

12.0 18.3 24.1 36.1 36.2 48.3 12.5 12.5 24.6 36.7

Total Block RAM (Mb)

25.3 36.0 50.6 75.9 70.9 94.5 23.6 23.6 47.3 70.9

UltraRAM (Mb)

90.0 132.2 180.0 270.0 270.0 360.0 90.0 90.0 180.0 270.0

HBM DRAM (

GB)

– – – – – – 4 8 8 8

HBM AXI

Interfaces

– – – – – – 32 32 32 32

Clock Mgmt

Tiles (CMTs)

10 20 20 30 12 16 4 4 8 12

DSP Slices

2,280 3,474 4,560 6,840 9,216 12,288 2,880 2,880 5,952 9,024

Peak INT8 DSP (TOP/s)

7.1 10.8 14.2 21.3 28.7 38.3 8.9 8.9 18.6 28.1

PCIe® Gen3 x16 / Gen4 x8

2 4 4 6 3 4 4 4 5 6

CCIX Ports

(1)

– – – – – – 4 4 4 4

150G Interlaken

3 4 6 9 6 8 0 0 2 4

100G Ethernet w/ RS-

FEC

3 4 6 9 9 12 2 2 5 8

Max. Single-

Ended HP I/Os

520 832 832 832 624 832 208 208 416 624

GTY 32.75Gb/s

Transceivers

40 80 80 120 96 128 32 32 64 96

Extended

(2)

1 -2 -2L -

Industrial

-1 -2 -1 -2 -1 -2 -1 -2 -1 -2 -1 -2 – – – –

Footprint(3,4)

Dimensions (mm)

HP I/O, GTY 32.75Gb/s

Footprint compatible with 20nm

UltraScale Devices with same footprint identifier

C1517 40x40 520, 40

F1924(5) 45x45 624, 64

A2104 47.5x47.5 832, 52 832, 52 832, 52

52.5x52.5(6) 832, 52

B2104 47.5x47.5 702, 76 702, 76 702, 76 572, 76

52.5x52.5(6) 702, 76

C2104 47.5x47.5 416, 80 416, 80 416, 104 416, 96

52.5x52.5(6) 416, 104

D2104 47.5x47.5 676, 76 572, 76

52.5x52.5(6) 676, 76

A2577 52.5x52.5 448, 120 448, 96 448, 128

H1924 45x45 208, 32

H2104 47.5x47.5 208, 32 416, 64

H2892 55x55 416, 64 624, 96

Notes:

1. A CCIX port requires the use of a PCIe Gen3 x16 / Gen4 x8 block.

2. -2LE (Tj = 0°C to 110°C). For more details, see the Ordering Information section in DS890, UltraScale

Architecture and Product Overview.

3. For full part number details, see DS890, UltraScale Architecture and Product Overview.

4. All packages are 1.0mm ball pitch.

5. The GTY transceiver line rate in the F1924 footprint is package limited to 16.3Gb/s. Refer to data sheet for details.

6. These 52.5x52.5mm packages have the same PCB ball footprint as the 47.5x47.5mm packages and are footprint

compatible.

Page 4

UltraScale Architecture Migration Table

Pkg mm

Kintex® UltraScale™ Kintex UltraScale+™ Virtex® UltraScale Virtex UltraScale+

KU025

KU035

KU040

KU060

KU085

KU095

KU115

KU3P KU5P KU9P

KU11P

KU13P

KU15P

VU065

VU080

VU095

VU125

VU160

VU190

VU440

VU3P VU5P VU7P VU9P

VU11P

VU13P

A784 23 X X

B784 23 X X

A676 27 X X

B676 27 X X

A900 31 X X

D900 31 X X X

E900 31 X X

A1156 35 X X X X X X X

A1517 40 X X X

C1517 40 X X X X X

D1517 40 X X X X

E1517 40 X X

A1760 42.5 X

B1760 42.5 X X X X X X

E1760 42.5 X

D1924 45 X

F1924 45 X X X

A2104 47.5(1) X X X X X X X X

B2104 47.5(1) XX XXXXX XXXXX

C2104 47.5(1) XXXX XXXXX

D2104 47.5(1) XXX

B2377 50 X

A2577 52.5 X X X X

A2892 55 X

Notes:

1.The body size of the VU13P device in the A2104, B2104, C2104, and D2104 packages is 52.5mm. These packages are footprint compatible with the corresponding 47.5mm body size packages. See UG583, UltraScale

Architecture PCB Design User Guide for important migration details.

2.Virtex UltraScale+ HBM devices migrate among each other but do not migrate to other devices.

UltraScale and UltraScale+ families provide footprint compatibility to enable users to migrate designs from one

device or family to another. Any two packages with the same footprint identifier code are footprint compatible.

Legend

Device

Migration Path

Page 5

Kintex® UltraScale+™ FPGA Speed Grades

Notes:

1. For full part number details, see the Ordering Information section in DS890, UltraScale Architecture and Product Overview.

2.-2LE (Tj = 0°C to 110°C). For more details, see the Ordering Information section in DS890, UltraScale Architecture and Product Overview.

:: available

–:: not offered

Device Name(1)

Speed Grade KU3P KU5P KU9P KU11P KU13P KU15P

Extended(2)

-1      

-2      

-2L      

-3      

Industrial

-1      

-1L      

-2      

Page 6

Device Name(1)

Speed Grade VU3P VU5P VU7P VU9P VU11P VU13P VU31P VU33P VU35P VU37P

Extended(2)

-1 

-2 

-2L 

-3 

Industrial

-1 ––––

-2 ––––

Virtex® UltraScale+™ FPGA Speed Grades

Notes:

1. For full part number details, see the Ordering Information section in DS890, UltraScale Architecture and Product Overview.

2.-2LE (Tj = 0°C to 110°C). For more details, see the Ordering Information section in DS890, UltraScale Architecture and Product Overview.

:: available

–:: not offered

Page 7

UltraScale+ Device Ordering Information

E = Extended (Tj = 0°C to +100°C)

I = Industrial (Tj = –40°C to +100°C)

Important: Verify all data in this document with the device data sheets found at www.xilinx.com

For valid part/package combinations,

go to DS890, UltraScale Architecture and Product Overview: Device-Package Combinations and Maximum I/Os Tables

F: Lid

L: Lid SSI

B: Lidless

S: Lidless SSI Stiffener

H: Overhang SSI

I: Overhang Lidless SSI Stiffener

V: RoHS 6/6

G: RoHS 6/6

w/ Exemption 15

Package

Designator

Speed Grade

-1 = Slowest

-L1 = Low Power

-2 = Mid

-L2 = Low Power

-3 = Fastest

Footprint

Temperature

Grade

(E, I)

Package

Pin Count

-1 F L V A # E

Xilinx

Commercial

UltraScaleV: Virtex

K: Kintex

Value

Index

XC V U

Denotes

UltraScale+

Device

F: Flip-Chip

(1.0mm)

S: Flip-Chip

(0.8mm)

© Copyright 2015–2017 Xilinx
.
DS890,UltraScale™ Architecture and Product Overview
DS922, Kintex® UltraScale+™ FPGAs Data Sheet: DC and AC Switching Characteristics
DS923, Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics
UG570,UltraScale Architecture Configuration User Guide
UG571,UltraScale Architecture SelectIO™ Resources User Guide
UG572,UltraScale Architecture Clocking Resources User Guide
UG573,UltraScale Architecture Memory Resources User Guide
UG574,UltraScale Architecture Configurable Logic Block User Guide
UG575, UltraScale and UltraScale+ FPGAs Packaging and Pinouts Product Specification
UG576, UltraScale Architecture GTH Transceivers User Guide
UG578, UltraScale Architecture GTY Transceivers User Guide
UG579, UltraScale Architecture DSP Slice User Guide
UG580, UltraScale Architecture System Monitor User Guide
UG583,UltraScale Architecture PCB Design User Guide 
PG150, UltraScale Architecture-Based FPGAs Memory IP Product Guide 
PG182, UltraScale FPGAs Transceivers Wizard Product Guide
Page 8
Important: Verify all data in this document with the 
device data sheets found at www.xilinx.com
References
XMP103 (v1.11)

UltraScale+ FPGA Product Tables And Selection Guide Ultrascale Plus

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