Renesas R61509V Users Manual ER61509V_0.11_20080424
R61509V R61509V
R61509V to the manual a8ca65a3-9abb-45fc-9ff1-2a1acc3f8dcb
2015-02-06
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Target Spec
R61509V
260k-color, 240RGB x 432-dot graphics liquid crystal
controller driver for Amorphous-Silicon TFT Panel
REJxxxxxxx-xxxx
Rev.0.11
April 25, 2008
Description ......................................................................................................... 6
Features
......................................................................................................... 7
Power Supply Specifications .............................................................................. 8
Differences Between R61509 and R61509V...................................................... 9
Block Diagram .................................................................................................... 10
Block Function.................................................................................................... 11
1. System Interface.....................................................................................................................................................11
2. External Display Interface (RGB, VSYNC interfaces)........................................................................................12
3. Address Counter (AC) ...........................................................................................................................................12
4. Graphics RAM (GRAM)........................................................................................................................................13
5. Grayscale Voltage Generating Circuit..................................................................................................................13
6. Liquid Crystal Drive Power Supply Circuit..........................................................................................................13
7. Timing Generator ..................................................................................................................................................13
8. Oscillator (OSC).....................................................................................................................................................13
9. Liquid crystal driver Circuit ..................................................................................................................................13
10. Internal Logic Power Supply Regulator...............................................................................................................13
Pin Function ........................................................................................................ 14
Pad Arrangement ................................................................................................ 19
Pad coordinate..................................................................................................... 21
Bump Arrangement............................................................................................. 36
Connection Example........................................................................................... 37
GRAM Address Map .......................................................................................... 38
Instruction ......................................................................................................... 40
Rev. 0.11 April 25, 2008, page 1 of 181
R61509V
Target Spec
Outline ..........................................................................................................................................................................40
Instruction Data Format..............................................................................................................................................40
Index (IR) .....................................................................................................................................................................41
Display control .............................................................................................................................................................41
Device code read (R000h)......................................................................................................................................41
Driver Output Control (R001h)..............................................................................................................................41
LCD Drive Wave Control (R002h).........................................................................................................................42
Entry Mode (R003h) ...............................................................................................................................................42
Display Control 1 (R007h) .....................................................................................................................................45
Display Control 2 (R008h) .....................................................................................................................................46
Display Control 3 (R009h) .....................................................................................................................................48
8 Color Control (R00Bh)........................................................................................................................................49
External Display Interface Control 1 (R00Ch)......................................................................................................50
External Display Interface Control 2 (R00Fh) ......................................................................................................52
Panel Interface Control 1 (R010h).........................................................................................................................53
Panel Interface Control 2 (R011h).........................................................................................................................55
Panel Interface Control 3 (R012h).........................................................................................................................56
Panel Interface Control 4 (R013h).........................................................................................................................58
Panel Interface Control 5 (R014h).........................................................................................................................59
Panel Interface Control 6 (R020h).........................................................................................................................60
Panel Interface Control 7 (R021h).........................................................................................................................62
Panel Interface Control 8 (R022h).........................................................................................................................63
Panel Interface Control 9 (R023h).........................................................................................................................65
Frame Marker Control (R090h).............................................................................................................................66
Power Control...............................................................................................................................................................67
Power Control 1 (R100h) .......................................................................................................................................67
Power Control 2 (R101h) .......................................................................................................................................69
Power Control3 (R102h) ........................................................................................................................................73
Power Control 4 (R103h) .......................................................................................................................................74
RAM Access..................................................................................................................................................................75
RAM Address Set (Horizontal Address) (R200h) RAM Address Set (Vertical Address) (R201h) ........................75
GRAM Data Write (R202h) ....................................................................................................................................76
GRAM Data Read (R202h).....................................................................................................................................77
NVM Data Read / NVM Data Write (R280h).........................................................................................................78
Window Address Control .............................................................................................................................................81
Window Horizontal RAM Address Start (R210h), Window Horizontal RAM Address End (R211h) ...................81
Window Vertical RAM Address Start (R212h), Window Vertical RAM Address End (R213h) ............................81
γ Control .......................................................................................................................................................................82
γ Control 1 ~ 14 (R300h to R309h) ........................................................................................................................82
Base Image Display Control ........................................................................................................................................84
Base Image Number of Line (R400h).....................................................................................................................84
Base Image Display Control (R401h) ....................................................................................................................84
Base Image Vertical Scroll Control (R404h) .........................................................................................................84
Partial Display Control ................................................................................................................................................88
Partial Image 1: Display Position (R500h), RAM Address 1 (Start Line Address) (R501h), RAM Address 1 (End Line Address)
(R502h) ................................................................................................................................................................88
Pin Control ...................................................................................................................................................................89
Test Register (Software Reset) (R600h) .................................................................................................................89
Rev. 0.11 April 25, 2008, page 2 of 181
R61509V
Target Spec
NVM Control ................................................................................................................................................................90
NVM Access Control 1 (R6F0h), NVM Access Control 2 (R6F1h), NVM Access Control 3 (R6F2h).................90
Instruction List .................................................................................................... 92
Reset Function .................................................................................................... 93
Basic Mode Operation of the R61509V.............................................................. 95
Interface and Data Format .................................................................................. 96
System Interface.................................................................................................. 99
80-System 18-bit Bus Interface ...................................................................................................................................100
80-System 16-bit Bus Interface ...................................................................................................................................101
80-System 9-bit Bus Interface .....................................................................................................................................104
Data Transfer Synchronization in 9-bit Bus Interface Operation ............................................................................105
80-System 8-bit Bus Interface .....................................................................................................................................106
Serial Interface.............................................................................................................................................................109
VSYNC Interface................................................................................................ 112
Notes to VSYNC Interface Operation .........................................................................................................................114
FMARK Interface ............................................................................................... 116
FMP Setting Example..................................................................................................................................................120
RGB Interface ..................................................................................................... 121
RGB Interface ..............................................................................................................................................................121
Polarities of VSYNCX, HSYNCX, ENABLE, and DOTCLK Signals.......................................................................122
Setting Example of Display Control Clock in RGB Interface Operation .................................................................123
RGB Interface Timing .................................................................................................................................................124
16-/18-Bit RGB Interface Timing ...........................................................................................................................124
RAM access via system interface in RGB interface operation ..................................................................................125
16-Bit RGB Interface ...................................................................................................................................................126
18-bit RGB Interface....................................................................................................................................................127
Notes to RGB Interface Operation ..............................................................................................................................128
RAM Address and Display Position on the Panel .............................................. 129
Instruction Setting Example........................................................................................................................................132
Window Address Function ................................................................................. 134
Scan Mode Setting .............................................................................................. 135
8-Color Display Mode ........................................................................................ 136
Frame-Frequency Adjustment Function ............................................................. 137
Relationship between Liquid Crystal Drive Duty and Frame Frequency.................................................................137
Rev. 0.11 April 25, 2008, page 3 of 181
R61509V
Target Spec
Partial Display Function ..................................................................................... 139
Liquid Crystal Panel Interface Timing ............................................................... 140
Internal Clock Operation.............................................................................................................................................140
RGB Interface Operation.............................................................................................................................................141
γ Correction Function.......................................................................................... 142
γ Correction Function..................................................................................................................................................142
γ Correction Circuit......................................................................................................................................................142
γ Correction Registers ..................................................................................................................................................143
Reference level adjustment registers...........................................................................................................................143
Interpolation Registers.................................................................................................................................................145
Frame Memory Data and the Grayscale Voltage.......................................................................................................148
Power Supply Generating Circuit ....................................................................... 149
Power Supply Circuit Connection Example 1 (VCI1 = VCIOUT)............................................................................149
Power Supply Circuit Connection Example 2 (VCI1 = VCI Direct Input)...............................................................150
Specifications of Power-supply Circuit External Elements................................ 151
Voltage Setting Pattern Diagram ........................................................................ 152
Liquid Crystal Application Voltage Waveform and Electrical Potential ..................................................................153
VCOMH and VREG1OUT Voltage Adjustment Sequence ............................... 154
NVM Control ...................................................................................................... 155
NVM Load (Register Resetting) Sequence .................................................................................................................156
NVM Write Sequence...................................................................................................................................................157
NVM Erase Sequence ..................................................................................................................................................158
Power Supply Setting Sequence ......................................................................... 159
Notes to Power Supply ON Sequence ................................................................ 161
Instruction Setting Sequence and Refresh Sequence .......................................... 162
Display ON/OFF Sequences and Refresh Sequence .................................................................................................162
Shutdown Mode Sequences .........................................................................................................................................163
Partial Display Setting .................................................................................................................................................166
Absolute Maximum Ratings ............................................................................... 167
Electrical Characteristics .................................................................................... 168
DC Characteristics .......................................................................................................................................................168
Step-up Circuit Characteristics..............................................................................................................................170
Internal Reference Voltage: Condition ..................................................................................................................170
Power Supply Voltage Range .................................................................................................................................171
Output Voltage Range ............................................................................................................................................171
AC Characteristics .......................................................................................................................................................172
Rev. 0.11 April 25, 2008, page 4 of 181
R61509V
Target Spec
Clock Characteristics .............................................................................................................................................172
80-system 18-/16-/9-/8-bit Bus interface Timing Characteristics .........................................................................172
Clock Synchronous Serial Interface Timing Characteristics.................................................................................173
RGB Interface Timing Characteristics...................................................................................................................173
LCD Driver Output Characteristics.......................................................................................................................174
Reset Timing Characteristics .................................................................................................................................174
Notes to Electrical Characteristics ..............................................................................................................................175
Test Circuits..................................................................................................................................................................176
Timing Characteristics.................................................................................................................................................177
80-system Bus Interface..........................................................................................................................................177
Clock Synchronous Serial Interface .......................................................................................................................178
Reset Operation ......................................................................................................................................................178
LCD Driver and VCOM Output Characteristics ...................................................................................................179
Rev. 0.11 April 25, 2008, page 5 of 181
R61509V
Target Spec
Description
The R61509V is a single-chip liquid crystal controller driver LSI for a-Si TFT panel, incorporating RAM
for a maximum 240 RGB x 432 dot graphics display, gate driver, source driver and power supply circuits.
For efficient data transfer, the R61509V supports high-speed interface via 8-/9-/16-/18-bit ports as system
interface to the microcomputer. As moving picture interface, the R61509V also supports RGB interface
(VSYNCX, HSYNCX, DOTCLK, ENABLE and DB17-0).
The power supply circuit incorporates step-up circuit and voltage follower circuit to generate TFT liquid
crystal panel drive voltages.
The R61509V’s power management functions such as 8-color display and shut down and so on make this
LSI an ideal driver for the medium or small sized portable products with color display systems such as
digital cellular phones or small PDAs, where long battery life is a major concern.
Rev. 0.11 April 25, 2008, page 6 of 181
R61509V
Target Spec
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
A single-chip controller driver incorporating a gate circuit and a power supply circuit for a maximum
240RGB x 432dots graphics display on amorphous TFT panel in 262k colors
System interface
– High-speed interfaces via 8-, 9-, 16-, 18-bit parallel ports
– Clock synchronous serial interface
Moving picture display interface
– 16-/18-bit RGB interface (VSYNCX, HSYNCX, DOTCLK, ENABLE, DB17-0)
– VSYNC interface (System interface + VSYNCX)
– FMARK interface (System interface + FMARK)
Window address function to specify a rectangular area in the internal RAM to write data
Write data within a rectangular area in the internal RAM via moving picture interface
– Reduce data transfer by specifying the area in the RAM to rewrite data
– Enable displaying the data in the still picture RAM area with a moving picture simultaneously
Abundant color display and drawing functions
– Programmable for 262k-color display
– Partial display function
Low -power consumption architecture (allowing direct input of interface I/O power supply)
– Shut down function
– 8-color display function
Input power supply voltages: IOVCC (interface I/O power supply)
VCC (logic regulator power supply)
VCI (liquid crystal analog circuit power supply)
Incorporates a liquid crystal drive power supply circuit
– Source driver liquid crystal drive/VCOM power supply: DDVDH
VCL
– Gate drive power supply: VGH
VGL
– VCOM drive (VCOM power supply): VCOMH
VCOML
Liquid crystal power supply startup sequencer
TFT storage capacitance: Cst only (common VCOM formula)
233,280-byte internal RAM
Internal 720-channel source driver and 432-channel gate driver
Single-chip solution for COG module with the arrangement of gate circuits on both sides of the glass
substrate
Internal NVM
User identification code: 8 bits
VCOM level adjustment: 7 bits x 2. Rewriting is available up to 5 times
Rev. 0.11 April 25, 2008, page 7 of 181
R61509V
Target Spec
Power Supply Specifications
Table 1
No.
1
Item
TFT data lines
R61509V
720 output
2
TFT gate lines
432 output
3
TFT display storage capacitance
Cst only (Common VCOM formula)
4
Liquid crystal
drive output
V0 ~ V63 grayscales
5
6
Input voltage
Liquid crystal
drive
voltages
S1~S720
G1~G432
VGH-VGL
VCOM
Change VCOMH-VCOML amplitude with electronic volume
Change VCOMH with either electronic volume or from
VCOMR
IOVCC
(interface voltage)
1.65V ~ 3.3V
Power supply to IM0_ID, IM1-2, RESETX, DB17-0, RDX,
SDI, SDO, WR_SCL, RS, CSX, VSYNCX, HSYNCX,
DOTCLK, ENABLE, FMARK
Connect to VCC and VCI on the FPC when the electrical
potentials are the same.
VCC
(logic regulator power
supply)
2.5V ~ 3.3V
Connect to IOVCC and VCI on the FPC when the electrical
potentials are the same.
VCI
(liquid crystal drive
power supply voltage)
2.5V ~ 3.3V
Connect to IOVCC and VCC on the FPC when the electrical
potentials are the same.
DDVDH
4.5 ~ 6.0V (VCI1 x 2)
VGH
10 ~ 18.0 V (VCI1 x 5, 6)
VGL
-4.5 ~ -13.5V (VCI1 x –3, -4, -5)
VGH-VGL
max. 28V
VCL
-1.9 ~ -3.0V (VCI1 x -1)
VCI-VCL
max. 6V
See “DC characteristics” in Chapter “Electrical Characteristics” for voltage spec.
Rev. 0.11 April 25, 2008, page 8 of 181
Difference Between R61509 and R61509V
2008.04.18
R61509V
Deleted
B509H
1 line inversion
Deleted
Index
(Pin)
R000h
R002h
R003h
Command
System Interface
Device Code Read
LCD Drive Waveform Control
Entry Mode
NW[1-0] --> NW bit is deleted.
HWM
R006h
R007h
Outline Sharpening Control
Display Control 1
EPF[1-0]
EGMODE, AVST[2:0], ADST[2:0]DTHU[1:0], DTHL[1:0]
PTDE[1-0]-->PTDE0
High Speed RAM Write
Sets data format when writing 16bit
data in 18bit format.
Outline Sharpening Function
Controls partial image 1 and 2.
VON
Starts VCOM output
Manual setting
GON
Sets gate output to OFF level.
Manual setting
DTE
Starts gate scan
Manual setting
D[1-0]
FP[3-0]
BP[3-0]
PTG[1-0] --> Deleted.
ISC[3:0]
PTS[2-0] -->PTS
VEM[0] --> VEM[1-0]
Manual setting
2-14 lines (in units of 1 line)
2-14 lines (in units of 1 line)
Normal scan / interval scan
3, 5, 7, 9, 11, 13 or 15 frames
V0-V31
VCOMH to VCOML only
Deleted
Deleted
Partial image 1
Deleted. (Because the sequence is changed. See "Power Supply
Setting Sequence" for detail. )
Deleted. (Because the sequence is changed. See "Power Supply
Setting Sequence" for detail. )
Deleted. (Because the sequence is changed. See "Power Supply
Setting Sequence" for detail. )
Deleted. (Because the sequence is changed. See "Power Supply
Setting Sequence" for detail. )
3-128 lines (in units of 1 line)
3-128 lines (in units of 1 line)
Normal scan only (Interval scan is not available)
Deleted
V0-V63
VCOML to VCOMH / VCOMH to VCOML (See description)
Supported
0, 1, 2 or 3 clock period
16-127 clocks
0 - 15 clocks
0 - 15 clocks
Deleted
0, 1, 2, 3, 4, 5, 6 or 7 clock period
16 - 63 clocks
0 - 7 clocks
0 - 7 clocks
Supported
Deleted
Deleted. (Because the sequence is changed. See "Power Supply
Setting Sequence" for detail. )
Deleted. (Because the sequence is changed. See "Power Supply
Setting Sequence" for detail. )
DDVDH: x2, VCL: x-1, VGH: x5, x6, VGL: x-3, x-4, x-5
Deleted. (Because the sequence is changed. See "Power Supply
Setting Sequence" for detail. )
Deleted
Synchronized with internal clock (Default)
Synchronized with internal clock (Default)
5bit (VRH [4:0]). Enables minute setting.
Code
IM2-0=011, TRI=1, DFM=0
Function
8bit 3 transfer (2bit-8bit-8bit)
R61509
Supported
1509H
1, 2, 3 or 4 line inversion
Supported
Supported
Supported
Partial image 1 and 2
R008h
Display Control 2
R009h
Display Control 3
R00Bh
Low Power Control
R00Ch
R012h
R020h
R021h
External Display Interface Control
Panel Interface Control 3
Panel Interface Control 4
Panel Interface Control 5
RIM[1-0]=10
VEQWI[1-0]-->VEQWI[2-0]
RTNE[6-0]-->RTNE[5-0]
NOWE[3-0]-->NOWE[2-0]
SDTE[3-0]-->SDTE[2-0]
R092h
MDDI Sub-display Control
SIM[1:0] --> Deleted.
R100h
Power Control 1
SAP[1-0]
Starts/halts display operation
Defines front porch
Defines back porch
Sets gate scan mode
Sets gate scan cycle
Sets source output level
Execute VCOM equalize.
Selects 6bit 3 transfer via RGB
interface
Defines VCOM equalize period.
Defines number of clock per line.
Defines gate non overlap period.
Defines source output delay period.
Defines data format for sub display
interface operation.
Adjusts bias current in source
amplifier.
SAP --> SOAPON
BT[2-0]
Enables source amplifier
Defines step-up factor
Supported
DDVDH: x2, VCL:x-1, VGH: x6, x7, VGL: x-3, x-4, x-5
Supported
Supported
Not synchronized with internal clock (Default)
Not synchronized with internal clock (Default)
4bit (VRH [3:0])
Selects external or internal reference voltage.
VCOML can be set at GND level
Supported
R101h
Power Control 2
R102h
Power Control 3
APE --> Deleted.
SLP --> Deleted.
DC1[2-0]
DC2[2-0]
VRH[3-0]
R103h
Power Control 4
VRG1R --> Deleted.
VCOMG
Enables power supply circuit
Selects sleep mode.
Defines step-up factor for DCDC1.
Defines step-up factor for DCDC2.
Sets a factor to generate
Defines reference level to generate
VREG1OUT
Defines VCOM amplitude
R110h
Power Control 6
PSE
Enables power supply sequencer
Supported
R112h
R280h
R281h
Power Control 7
NVM Data Read / NVM Data Write
TBT[1-0]
UID[3:0]
VCM1[4-0]
Used in power supply sequencer
User code
Defines VCOMH 1level
Supported
UID[3:0]
VCMSEL , VCM2[4-0]
Gamma Control
NL0[5-0]
Defines VCOMH 2level
Gamma control method changed.
Specifies LCD drive line.
Defines source output level in non-lit
display area
Inverts grayscale level in the display
area
Settings for partial image 2.
Software Reset
Selects the order of receiving data.
VCMSEL VCM2
84 bit
16 - 432 line (in units of 8 lines)
Internal reference voltage only
Deleted
Deleted. (Because the sequence is changed. See "Power Supply
Setting Sequence" for detail. )
Deleted. (Because the sequence is changed. See "Power Supply
Setting Sequence" for detail. )
VCM[6-0] UID[7-0]
NVM specification changed. VCM bit is moved to R280h.
Deleted. (Because the R61509V supports both NVM write and erase
functions).
100 bit (New gamma correction method)
240 - 432 lines (in units of 8 lines)
V31-V0
V63-V0
V31-V0
Partial image 1 and 2
Software Reset
Supported
V63-V0
Partial image 1 only
Only secret test registers are initialized.
Deleted
R282h
R300h-R309h
R400h
R401h
VCOM High Voltage 1
VCOM High Voltage 2
Gamma Control
Base Image Number of Line
Base Image Display Control
R503h-R505h
Partial Image Control
R600h
Software Reset
R606h
i80-I/F Endian Control
See each register's description for detail.
NDL0
REV0
PTDP1[8-0] PTSA1[8-0] PTEA1[8-0] --> Deleted.
SRST--> TRSR
TCREV[1] , TCREV[0]
VCM1[4-0]
R61509V
Target Spec
Block Diagram
GND
Control
㩷
Register
(CR)
AGND
18
㩷
㩷
18 bit
16 bit
9 bit
8 bit
Serial
Write data
latch 㩷
18
㩷
18
Read data
㩷
latch
㩷
18
Graphic RAM
(GRAM)
233,280byte
18
㩷
18
㩷
㩷
External
display㩷
㩷
interface
Gate line drive circuit
NVM
VDD
Figure 1
Rev. 0.11 April 25, 2008, page 10 of 181
VCOM
VCOML
VCOMH
VCOMR
VREG1OUT
VCL
VGL
VGH
DDVDH
C21P/C21M
C22P/C22M
VCI1
㩷
LCD drive level generating circuit
VCI
G1-G432
㩷
Internal logic
power supply 㩷
㩷
circuit
C11P/C11M
C12P/C12M
C13P/C13M
㩷
㩷
㩷
㩷
㩷
㩷
㩷
㩷
VCC
VMON
㩷
㩷
Internal reference
㩷
voltage generating
㩷
circuit
㩷
Scan data generating circuit
㩷
Oscillator
VGS
㩷
Timing
generator
Grayscale voltage
generating circuit
V63-0
㩷
㩷
Gamma
correction circuit
㩷
CSX
㩷 RS
WR_SCL
㩷
RDX
㩷 SDI
㩷 SDO
DB17-0
㩷
VSYNCX
㩷
HSYNCX
㩷
DOTCLK
ENABLE
㩷
㩷
RESETX
㩷
FMARK
PROTECT
㩷
㩷
㩷
㩷
㩷
㩷
㩷
Source line drive circuit
System
㩷
interface
Latch Circuit
IOVCC
㩷
IM2-1, IM0_ID
㩷
M alternation
Address
Counter
Latch circuit
㩷
Latch circuit
Index
㩷
Register (IR)
VPP1,
VPP3A,3B
R61509V
Target Spec
Block Function
1.
System Interface
The R61509V supports 80-system high-speed interface via 8-, 9-, 16-, 18-bit parallel ports and a clock
synchronous serial interface. The interface is selected by setting the IM2-0 pins.
The R61509V has 16-bit index register (IR), 18-bit write-data register (WDR), and 18-bit read-data register
(RDR). The IR is the register to store index information from control register and internal GRAM. The
WDR is the register to temporarily store write data to control register and internal GRAM. The RDR is the
register to temporarily store the read data from the GRAM. The write data from the host processor to the
internal GRAM is first written to the WDR and then automatically written to the internal GRAM by
internal operation. The data is read via RDR from the internal GRAM. Therefore, invalid data is sent to
the data bus when the R61509V performs the first read operation from the internal GRAM. Valid data is
read out when the R61509V performs the second and subsequent read operation.
The R61509V allows writing instructions consecutively by executing the instruction in the same cycle
when it is written (0 instruction cycle).
Table 2 Register Selection (80-System 8-/9-/16-/18-Bit Parallel Interface)
WRX
RDX
RS
Function
0
1
0
Write index to IR
1
0
0
Setting disabled
0
1
1
Write to control register or internal GRAM via WDR
1
0
1
Read from internal GRAM and register via RDR
Table 3 Register Selection (Clock Synchronous Serial Interface)
Start byte
R/W
RS
Function
0
0
Write index to IR
1
0
Setting disabled
0
1
Write to control register or internal GRAM via WDR
1
1
Read from internal GRAM and register via RDR
Rev. 0.11 April 25, 2008, page 11 of 181
R61509V
Target Spec
Table 4
2.
IM2
IM1
IM0
System interface
DB pins
0
0
0
80-system 18-bit
DB17-0
interface
Single transfer (18 bits)
0
0
1
80-system 9-bit
interface
2-transfer (1st: 9 bits, 2nd: 9 bits)
0
1
0
0
1
1
1
0
*
1
1
1
1
0
1
DB17-9
RAM write data
Single transfer (16 bits)
80-system 16-bit DB17-10,
2-transfer (1st: 2 bits, 2nd: 16 bits)
interface
DB8-1
2-transfer (1st: 16 bits, 2nd: 2 bits)
st
nd
2-transfer (1 : 8 bits, 2 : 8 bits)
80-system 8-bit
st
DB17-10 3-transfer (1 : 6 bits, 2nd: 6 bits, 3rd: 6
interface
bits)
Clock
2-transfer (1st: 8 bits, 2nd: 8 bits)
synchronous
(SDI,
serial interface
SDO)
Setting disabled
Setting disabled
-
Instruction write
transfer
Single transfer
(16 bits)
2-transfer
(1st: 8 bits, 2nd: 8
bits)
Single transfer
(16 bits)
2-transfer
(1st: 8 bits, 2nd: 8
bits)
2-transfer
(1st: 8 bits, 2nd: 8
bits)
-
External Display Interface (RGB, VSYNC interfaces)
The R61509V supports RGB and VSYNC interfaces as the external interface to display moving picture.
When the RGB interface is selected, the display operation is synchronized with externally supplied
synchronous signals (VSYNCX, HSYNCX, and DOTCLK). In RGB interface operation, data (DB17-0) is
written in synchronization with these signals when the polarity of enable signal (ENABLE) allows write
operation in order to prevent flicker when updating display data.
In VSYNC interface operation, the display operation is synchronized with the internal clock except frame
synchronization, which synchronizes the display operation with the VSYNCX signal. The display data is
written to the internal GRAM via system interface. When writing data via VSYNC interface, there are
constraints in speed and method in writing data to the internal RAM. For details, see Section “VSYNC
Interface”.
The R61509V allows switching interface by instruction according to the display image (still and/or moving
picture). This allows data to be transferred only when the data is updated hence less power consumption
during moving picture display.
3.
Address Counter (AC)
The address counter (AC) gives an address to the internal GRAM. When the index of a register is written
to the IR, the address information is sent from the IR to the AC. After data is written to GRAM, the
address in the AC is automatically updated plus or minus 1. The window address function enables writing
data only within the rectangular area specified in the GRAM.
Rev. 0.11 April 25, 2008, page 12 of 181
R61509V
4.
Target Spec
Graphics RAM (GRAM)
GRAM stands for graphics RAM, which can store bit-pattern data of 233,280 (240RGB x 432 (dots) x
18(bits)) bytes at maximum, using 18 bits per pixel.
5.
Grayscale Voltage Generating Circuit
The grayscale voltage generating circuit generates liquid crystal drive voltages according to the grayscale
data in the γ-correction registers to enable 262k-color display. For details, see the γ-Correction Register
section.
6.
Liquid Crystal Drive Power Supply Circuit
The liquid crystal drive power supply circuit generates DDVDH, VGH, VGL and VCOM levels to drive
liquid crystal.
7.
Timing Generator
The timing generator generates a timing signal for the operation of internal circuits such as the internal
GRAM. The timing signal for display operations such as RAM read and the timing signal for internal
operations such as RAM access from the host processor are generated separately in order to avoid mutual
interference.
8.
Oscillator (OSC)
The R61509V generates the RC oscillation clock internally. Using an external oscillation resistor is not
possible. The oscillation frequency is set to 678 kHz before shipment (for details, see Electrical
Characteristics). Use the frame frequency adjustment function to change the number of display lines and
the frame frequency. While the R61509V is shut down, RC oscillation halts so that reduce power
consumption is reduced.
9.
Liquid crystal driver Circuit
The liquid crystal driver circuit of the R61509V consists of a 720-output source driver (S1 ~ S720) and a
432-output gate driver (G1~G432). The display pattern data is latched when all of 240RGB data are
inputted. The latched data control the source driver and output drive waveforms. The gate driver for
scanning gate lines outputs either VGH or VGL level. The shift direction of 720-bit source output from the
source driver can be changed by setting the SS bit and the shift direction of gate output from the gate driver
can be changed by setting the GS bit. The scan mode by the gate driver can be changed by setting the SM
bit.
10. Internal Logic Power Supply Regulator
The internal logic power supply regulator generates internal logic power supply VDD.
Rev. 0.11 April 25, 2008, page 13 of 181
R61509V
Target Spec
Pin Function
Table 5 External Power Supply
Signal
I/O
Connect to
Function
Power supply for Internal VDD regulator.
When not
used
VCC
I
Power
supply
IOVCC
I
Power
supply
Power supply for interface pins.
―
GND
I
Power
supply
GND level for internal logic and interface pins. GND=0V.
―
VCI
I
Power
supply
Power supply for liquid crystal power supply analog circuit.
―
VCILVL
I
Reference
power
supply
Connect to an external power supply at the same level as VCI the
power supply for liquid crystal power supply analog circuit. In case of
COG, connect to VCI on the FPC to prevent noise.
―
AGND
I
Power
supply
Analog GND (for logic regulator and liquid crystal power supply).
AGND = 0V.
In case of COG, connect to GND on the FPC to prevent noise.
―
VPP1
I
Power
supply
VPP3A
I
Power
supply
VCC≧IOVCC
Power supply for internal NVM.
See section “NVM Control” for input voltages during write and erase
operation using VPP1-VPP3A pins.
―
Open or
AGND
Open or
AGND
Note 1: VCC, GND and AGND pins are allocated several different places on the chip. Make sure to connect
all of them to power following “Connection Example”.
Table 6 Bus Interface (Amplitude: IOVCC~GND)
Signal
I/O
Connect to
Function
When not
used
Chip selection signal. (Amplitude: IOVCC-GND)
Low: The R61509V is selected and accessible.
High: The R61509V is not selected and not accessible.
IOVCC
CSX
I
Host
processor
RS
I
Host
processor
Register selection signal. (Amplitude: IOVCC-GND)
Low: Index register is selected.
High: Control register is selected.
IOVCC
IOVCC
WRX_SCL
I
Host
processor
Write strobe signal when 80-system bus interface is selected.
Data are written when Low level.
Synchronous clock signal when clock synchronous serial
interface is selected.
(Amplitude: IOVCC-GND)
RDX
I
Host
processor
Read strobe signal when 80-system bus interface is selected.
Data are read when Low level. (Amplitude: IOVCC-GND)
IOVCC
SDI
I
Host
processor
Serial data input pin when clock synchronous serial interface is
selected. Data are inputted on the rising edge of SCL signal.
(Amplitude: IOVCC-GND)
GND
/IOVCC
SDO
O
Host
processor
Serial data output pin when clock synchronous serial interface is
selected. Data are outputted on the falling edge of SCL signal.
(Amplitude: IOVCC-GND)
Open
Rev. 0.11 April 25, 2008, page 14 of 181
R61509V
DB[17:0]
Target Spec
I/O
Host
processor
18-bit parallel bi-directional data bus for 80-system interface
operation (Amplitude: IOVCC-GND).
8-bit I/F: DB17-DB10 are used.
9-bit I/F: DB17-DB9 are used.
16-bit I/F: DB17-DB10 and DB8-1 are used.
18-bit I/F: DB17-DB0 are used.
18-bit parallel bi-directional data bus for RGB interface operation
(Amplitude: IOVCC-GND).
16-bit I/F: DB17-DB13 and DB11-1 are used.
18-bit I/F: DB17-DB0 are used.
GND /
IOVCC
ENABLE
I
Host
processor
Data enable signal for RGB interface operation.
Low: accessible (selected)
High: Not accessible (Not selected)
The polarity of ENABLE signal can be inverted by setting the
EPL bit. (Amplitude: IOVCC-GND).
VSYNCX
I
Host
processor
Frame synchronous signal. Low active. (Amplitude: IOVCCGND).
GND /
IOVCC
HSYNCX
I
Host
processor
Line synchronous signal, Low active. (Amplitude: IOVCC-GND)
GND /
IOVCC
DOTCLK
I
Host
processor
Dot clock signal. Data is input on the rising edge of DOTCLK.
(Amplitude: IOVCC-GND)
GND /
IOVCC
FMARK
O
Host
processor
Frame head pulse. (Amplitude: IOVCC-GND)
FMARK is used when writing data to the internal RAM.
Open
GND /
IOVCC
Select host processor interface. (Amplitude: IOVCC-GND)
DB pins
IM2 IM1 IM0
System Interface
Colors
in use
IM2-1,
IM0_ID
I
GND /
IOVCC
(ID)
80-system 18-bit
interface
80-system 9-bit
interface
80-system 16-bit
interface
80-system 8-bit
interface
Clock synchronous
serial interface
1
0
1
1
0
0
0
0
0
1
0
1
0
0
1
1
1
0
1
1
*
DB17-0
262,144
DB17-9
262,144
DB17-10,
8-1
262,144
(Note 1)
262,144
(Note 2)
DB17-10
―
65536
Setting inhibited
―
―
Setting inhibited
―
―
―
Note 1: 65,536 colors in one-transfer operation.
Note 2: 65,536 colors in two-transfer operation.
RESETX
I
Host
processor
or external
RC circuit
Reset pin. The R61509V is reset when RESETX is low. Make
sure to execute a power on reset after turning power on.
(Amplitude: IOVCC-GND)
Rev. 0.11 April 25, 2008, page 15 of 181
―
R61509V
PROTECT
Target Spec
I
Host
processor
Reset protect pin. The R61509V enters a reset protect status by
fixing PROTECT to GND level disabling hardware reset. With
this, erroneous operations caused by noise are prevented.
Low: Hardware reset is disabled (Reset protect status)
High: Hardware reset is enabled. (Normal status)
IOVCC
Table 7 Internal Power Supply Circuit
Signal
I/O
Connect
to
Function
When
not
used
VDD
O
Stabilizing
capacitor
Output from internal logic regulator. Connect to a stabilizing
capacitor.
―
VCI1
O
Stabilizing
capacitor
Reference voltage for step-up circuit 1. Make sure that DDVDH,
VGH and VGL output voltages do no go exceed the ratings.
―
DDVDH
O
Stabilizing
capacitor
Power supply for the source driver liquid crystal drive unit and
VCOM drive. Connect to a stabilizing capacitor.
―
VGH
O
Stabilizing
capacitor
Power supply for the gate driver liquid crystal drive unit.
Connect to a stabilizing capacitor.
―
VGL
O
Stabilizing
capacitor
Power supply for the gate driver liquid crystal drive unit.
Connect to a stabilizing capacitor.
―
VCL
O
Stabilizing
capacitor
Power supply for VCOML drive.
―
C11P,
C11M,
C12P,
C12M
I/O
Step-up
capacitor
Make sure to connect capacitors for internal step-up circuit 1.
―
C13P,
C13M,
C21P,
C21M,
C22P,
C22M
I/O
Step-up
capacitor
Make sure to connect capacitors for internal step-up circuit 2.
―
Rev. 0.11 April 25, 2008, page 16 of 181
R61509V
Target Spec
Table 8 LCD drive
Signal
I/O
VREG1OUT O
VCOM
O
Connect to
Function
When not in
use
Stabilizing Output voltage generated from the reference voltage VCIR. The factor
capacitor is determined by instruction (VRH bits).
VREG1OUT is used for (1) source driver grayscale reference voltage
VREG1OUT, (2) VCOMH level reference voltage, and (3) VCOM
amplitude reference voltage. Connect to a stabilizing capacitor.
VREG1OUT =4.0V ~ (DDVDH – 0.5)V
―
TFT panel Power supply to the TFT panel’s common electrode. VCOM alternates
common between VCOMH and VCOML. The alternating cycle is set by internal
electrode register. Also, the VCOM output can be started and halted by register
setting.
―
VCOMH
O
Stabilizing The High level of VCOM amplitude. The output level can be adjusted
capacitor by either external resistor (VCOMR) or electronic volume.
―
VCOML
O
Stabilizing The Low level of VCOM amplitude. The output level can be adjusted
capacitor by instruction (VDV bits). VCOML = (VCL+0.5) V ~ 0V
―
VCOMR
I
Variable
Connect a variable resistor when adjusting the VCOMH level between
resistor or VREG1OUT and GND.
open
Open
VGS
I
GND
Reference level for the grayscale voltage generating circuit.
―
S1~S720
O
LCD
Liquid crystal application voltages.
Open
G1~G432
O
LCD
Gate line output signals.
VGH: The gate line is selected.
VGL: The gate line is not selected.
Open
Rev. 0.11 April 25, 2008, page 17 of 181
R61509V
Target Spec
Table 9 Others (test, dummy pins)
When not in
use
Signal
I/O
Connect to
Function
VTEST
O
Open
Test pin. Leave open.
VREFC
I
GND
Test pin. Make sure to fix to the GND level.
VREFD
O
Open
Test pin. Leave open.
Open
Open
VREF
O
Open
Test pin. Leave open.
VDDTEST
I
GND
Test pin. Make sure to fix to the GND level.
VMON
O
Open
Test pin. Leave open.
VCIR
O
Open
-
Open
Open
Test pin. Leave open.
Open
GNDDUM1- O
10,
AGNDDUM1
-5,
VCCDUM,
IOVCCDUM
1-2
-
Pins to fix the electrical potentials of unused interface and test pins.
Open
DUMMYR
1-4
-
-
DUMMYR1 and DUMMYR4, DUMMYR2 and DUMMYR3 are shortcircuited within the chip for COG contact resistance measurement.
Open
VGLDMY
1-4
O
Unused
gate line
Output VGL level. Use when fixing unused gate line of the panel.
Open
DUMMYA
―
Open
Dummy pad. Leave open.
OPEN
DUMMYB
―
Open
Dummy pad. Leave open.
OPEN
DUMMYC
―
Open
Dummy pad. Leave open.
OPEN
TESTO1-15
O
―
Dummy pad. Leave open.
OPEN
TEST
1-5
I
GND
Test pin. Connect to GND.
GND
TS0-8
O
Open
Test pin. Leave open.
OPEN
VPP3B
I
AGND
Test pin. Connect to AGND.
―
TSC
I
GND
Test pin. Connect to GND.
Patents of dummy pin, which is used to fix to VCC or GND are granted.
PATENT ISSUED:
United States Patent No. 6,924,868
United States Patent No. 6,323,930
Japanese Patent No. 3,980,066
Korean Patent No. 401,270
Taiwanese Patent No. 175,413
Rev. 0.11 April 25, 2008, page 18 of 181
GND
R61509V Pad Arrangement Rev 0.6
(1-a)
7
No
□
□
Top View
BUMP
Chip
□
1
2
3
4
5
6
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250
251
252
253
254
255
256
257
258
259
260
261
262
DUMMYR1
DUMMYR2
AGNDDUM1
VPP3B
4
VPP3B
VPP3B
VPP3B
AGNDDUM2
VPP3A
VPP3A
VPP1
VPP1
VPP1
4
VPP1
VPP1
VPP1
VPP1
GNDDUM1
VDDTEST
VREFC
VREFD
VREF
VCCDUM1
DUMMYA
DUMMYA
5 DUMMYA
DUMMYA
DUMMYA
GNDDUM2
AGND
AGND
AGND
AGND
AGND
AGND
GND
GND
GND
GND
GND
VCC
VCC
VCC
VCC
VCC
VCC
VCC
TS8
TS7
TS6
TS5
TS4
TS3
TS2
TS1
TS0
TEST5
TEST4
TEST3
TEST2
TEST1
5 GNDDUM3
TSC
IM2
IM1
8
IM0_ID
IOVCCDUM1
PROTECT
8
RESETX
GNDDUM4
DUMMYB
5
DUMMYB
8
VSYNCX
8 HSYNCX
IOVCCDUM2
ENABLE
DOTCLK
DB17
DB16
5 GNDDUM5
DB15
DB14
DB13
DB12
5 GNDDUM6
DB11
DB10
DB9
IOVCC
IOVCC
IOVCC
IOVCC
IOVCC
IOVCC
DB8
5 GNDDUM7
DB7
DB6
DB5
DB4
5 GNDDUM8
DB3
DB2
DB1
DB0
5
GNDDUM9
CSX
8
RS
8
WRX_SCL
8
RDX
5 GNDDUM10
FMARK
SDI
SDO
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VMON
1
VCOM
1 VCOM
1
VCOM
1 VCOM
1
VCOM
1 VCOM
1
VCOM
1
VCOM
VCOMH
VCOMH
VCOMH
VCOMH
VCOMH
VCOMH
VCOML
VCOML
VCOML
VCOML
VCOML
VCOML
GND
GND
GND
GND
GND
GND
GND
GND
GND
VGS
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
VTEST
VCIR
VREG1OUT
VCOMR
C11M
C11M
C11M
C11M
C11M
C11P
C11P
C11P
C11P
C11P
C12M
C12M
C12M
C12M
C12M
C12P
C12P
C12P
C12P
C12P
DDVDH
DDVDH
5
DDVDH
DDVDH
DDVDH
DDVDH
DDVDH
DDVDH
DDVDH
VCI1
VCI1
VCI1
VCI1
VCI
VCI
VCI
VCI
VCI
VCI
VCILVL
DUMMYC
DUMMYC
5 DUMMYC
DUMMYC
DUMMYC
GND
GND
GND
3
GND
GND
AGND
AGND
AGND
AGND
AGND
VGL
VGL
VGL
VGL
VGL
VGL
VGL
VGL
5
VGL
AGNDDUM3
AGNDDUM4
VGH
5
VGH
VGH
VGH
VGH
VGH
AGNDDUM5
VCL
VCL
VCL
C13M
C13M
C13M
C13P
C13P
C13P
C21M
C21M
C21M
C21P
C21P
C21P
C22M
C22M
C22M
C22P
C22P
C22P
TESTO1
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G427
G429
G431
VGLDMY3
1217
1216
1215
1214
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Connect to GNDDUM3
Connect to GNDDUM3
Connect to GNDDUM3
Connect to GNDDUM3
Connect to GNDDUM3
□
□
□
□
Connect to GNDDUM3
Connect to IOVCCDUM1/GNDDUM3
Connect to IOVCCDUM1/GNDDUM3
Connect to IOVCCDUM1/GNDDUM3
1
No PAD
Open
Open
□
TESTO14
S1
S2
S3
S4
S5
1213
1212
1211
1210
1209
1208
S356
S357
S358
S359
S360
TESTO13
TESTO12
TESTO11
TESTO10
857
856
855
854
853
852
851
850
849
TESTO9
TESTO8
TESTO7
TESTO6
S361
S362
S363
S364
S365
848
847
846
845
844
843
842
841
840
□
S716
S717
S718
S719
S720
TESTO5
489
488
487
486
485
484
1
No PAD
□
□
□
□
□
□
□
□
Open
□
□
□
□
□
□
840um
□
□
□
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□
□
□
□
□
Open
Open
□
□
□
□
□
□
□
□
□
Open
Open
Open
Open
Open
VGLDMY2
G432
G430
G428
483
482
481
480
G10
G8
G6
G4
G2
VGLDMY1
TESTO4
TESTO3
TESTO2
271
270
269
268
267
266
265
264
263
6
□
□
□
□
□
□
□
□
7
No
1434
1433
1432
1431
1430
1429
1428
1427
1426
Connect to GNDDUM1
Connect to GNDDUM1
Open
Open
□
(1-b)
DUMMYR4
DUMMYR3
TESTO15
VGLDMY4
G1
G3
G5
G7
G9
Rev0.00 2007.12.13
First virsion
Rev0.10 2007.12.27
R61517's VCOMA, VCOMB --> R61509V's VCOM
Rev0.20 2008.02.13 Rev Mark 1 PAD No. 24～28, 71, 72, 208-217 changed to NC1-NC17
Rev0.21 2008.02.14 Rev Mark 2 NC's application voltage decided.
Rev0.30 2008.02.19 Rev Mark 4 VPP3C-->VPP3B, VPP2-->VPP1
Rev0.31 2008.02.27 Rev Mark 5 NC1-5-->DUMMYA
NC6-7-->DUMMYB
NC8-12-->DUMMYC
GNDDUM5-->GNDDUM2
GNDDUM6-->GNDDUM3
GNDDUM7-->GNDDUM4
GNDDUM8-->GNDDUM5
GNDDUM9-->GNDDUM6
GNDDUM10-->GNDDUM7
VLOUT1-->DDVDH
VLOUT2-->VGH
VLOUT3-->VGL
Rev0.4 2008.03.14 Rev Mark 6 DUMMYC's description "Open" added.
Rev0.5 2008.04.02 Rev Mark 7 Alignment mark (1-a) (1-b) added.
Rev0.6 2008.04.21 Rev Mark 8 Pin names changed.
Pad No66 IM0/ID→IM0_ID
Pad No69 RESET→RESETX
Pad No73 VSYNC→VSYNCX
Pad No74 HSYNC→HSYNCX
Pad No107 CS→CSX
Pad No109 WR/SCL→WRX_SCL
Pad No110 RD→RDX
R61509V
Target Spec
●Chip size: 19.03mm x 0.76mm
●Chip thickness: 280μm (typ)
●Pad coordinates: Pad center
●Coordinate origin: Chip center
●Au bump size
1. 50μm x 90μm (I/O side: No.1-262)
2. 15μm x 100μm (LCD output side: No.263-1434)
●Au bump pitch: See pad coordinate
●Au bump height:12μm
● Alignment mark
Table 10
Alignment marks
Type A
X-axis
Y-axis
(1-a)
-9381.0
-251.0
(1-b)
9381.0
-251.0
1-a: ( Left Alignment Mark )
1-b: ( Right Alignment Mark )
150um : Alignment Mark Area X-size
150um : Alignment Mark Area X-size
75um
75um
30um
30um
30um
30um
㩷
Y 㩷
㩷
㩷
30um
30um
30um
30um
30um
20um
30um
30um
30um
30um
Y
X
30um
X
Figure 2
Rev. 0.11 April 25, 2008, page 20 of 181
30um
20um
75um
75um
150um : Alignment Mark Area Y-size
20um
㩷
Alignment
Mark Area
30um
150um : Alignment Mark Area Y-size
Alignment
Mark Area
20um
30um
30um
30um
30um
R61509V Pad Coordinate （Unit：μm）
pad No
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
pad name
DUMMYR1
DUMMYR2
AGNDDUM1
VPP3B
VPP3B
VPP3B
VPP3B
AGNDDUM2
VPP3A
VPP3A
VPP1
VPP1
VPP1
VPP1
VPP1
VPP1
VPP1
GNDDUM1
VDDTEST
VREFC
VREFD
VREF
VCCDUM1
DUMMYA
DUMMYA
DUMMYA
DUMMYA
DUMMYA
GNDDUM2
AGND
AGND
AGND
AGND
AGND
AGND
GND
GND
GND
GND
GND
VCC
VCC
VCC
VCC
VCC
VCC
VCC
TS8
TS7
TS6
X
-9135.0
-9065.0
-8995.0
-8925.0
-8855.0
-8785.0
-8715.0
-8645.0
-8575.0
-8505.0
-8435.0
-8365.0
-8295.0
-8225.0
-8155.0
-8085.0
-8015.0
-7945.0
-7875.0
-7805.0
-7735.0
-7665.0
-7595.0
-7525.0
-7455.0
-7385.0
-7315.0
-7245.0
-7175.0
-7105.0
-7035.0
-6965.0
-6895.0
-6825.0
-6755.0
-6685.0
-6615.0
-6545.0
-6475.0
-6405.0
-6335.0
-6265.0
-6195.0
-6125.0
-6055.0
-5985.0
-5915.0
-5845.0
-5775.0
-5705.0
Y
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
2008.04.21 rev0.1
pad No
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
pad name
TS5
TS4
TS3
TS2
TS1
TS0
TEST5
TEST4
TEST3
TEST2
TEST1
GNDDUM3
TSC
IM2
IM1
IM0_ID
IOVCCDUM1
PROTECT
RESETX
GNDDUM4
DUMMYB
DUMMYB
VSYNCX
HSYNCX
IOVCCDUM2
ENABLE
DOTCLK
DB17
DB16
GNDDUM5
DB15
DB14
DB13
DB12
GNDDUM6
DB11
DB10
DB9
IOVCC
IOVCC
IOVCC
IOVCC
IOVCC
IOVCC
DB8
GNDDUM7
DB7
DB6
DB5
DB4
X
-5635.0
-5565.0
-5495.0
-5425.0
-5355.0
-5285.0
-5215.0
-5145.0
-5075.0
-5005.0
-4935.0
-4865.0
-4795.0
-4725.0
-4655.0
-4585.0
-4515.0
-4445.0
-4375.0
-4305.0
-4235.0
-4165.0
-4095.0
-4025.0
-3955.0
-3885.0
-3815.0
-3745.0
-3675.0
-3605.0
-3535.0
-3465.0
-3395.0
-3325.0
-3255.0
-3185.0
-3115.0
-3045.0
-2975.0
-2905.0
-2835.0
-2765.0
-2695.0
-2625.0
-2555.0
-2485.0
-2415.0
-2345.0
-2275.0
-2205.0
Y
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
R61509V Pad Coordinate （Unit：μm）
pad No
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
pad name
GNDDUM8
DB3
DB2
DB1
DB0
GNDDUM9
CSX
RS
WRX_SCL
RDX
GNDDUM10
FMARK
SDI
SDO
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VMON
VCOM
VCOM
VCOM
VCOM
VCOM
VCOM
VCOM
VCOM
VCOMH
VCOMH
VCOMH
VCOMH
VCOMH
VCOMH
VCOML
VCOML
VCOML
VCOML
VCOML
VCOML
GND
GND
GND
GND
GND
GND
X
-2135.0
-2065.0
-1995.0
-1925.0
-1855.0
-1785.0
-1715.0
-1645.0
-1575.0
-1505.0
-1435.0
-1365.0
-1295.0
-1225.0
-1155.0
-1085.0
-1015.0
-945.0
-875.0
-805.0
-735.0
-665.0
-595.0
-525.0
-455.0
-385.0
-315.0
-245.0
-175.0
-105.0
-35.0
35.0
105.0
175.0
245.0
315.0
385.0
455.0
525.0
595.0
665.0
735.0
805.0
875.0
945.0
1015.0
1085.0
1155.0
1225.0
1295.0
Y
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
2008.04.21 rev0.1
pad No
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
pad name
GND
GND
GND
VGS
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
VTEST
VCIR
VREG1OUT
VCOMR
C11M
C11M
C11M
C11M
C11M
C11P
C11P
C11P
C11P
C11P
C12M
C12M
C12M
C12M
C12M
C12P
C12P
C12P
C12P
C12P
DDVDH
DDVDH
DDVDH
DDVDH
DDVDH
DDVDH
DDVDH
DDVDH
DDVDH
VCI1
VCI1
VCI1
VCI1
X
1365.0
1435.0
1505.0
1575.0
1645.0
1715.0
1785.0
1855.0
1925.0
1995.0
2065.0
2135.0
2205.0
2275.0
2345.0
2415.0
2485.0
2555.0
2625.0
2695.0
2765.0
2835.0
2905.0
2975.0
3045.0
3115.0
3185.0
3255.0
3325.0
3395.0
3465.0
3535.0
3605.0
3675.0
3745.0
3815.0
3885.0
3955.0
4025.0
4095.0
4165.0
4235.0
4305.0
4375.0
4445.0
4515.0
4585.0
4655.0
4725.0
4795.0
Y
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
R61509V Pad Coordinate （Unit：μm）
pad No
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
pad name
VCI
VCI
VCI
VCI
VCI
VCI
VCILVL
DUMMYC
DUMMYC
DUMMYC
DUMMYC
DUMMYC
GND
GND
GND
GND
GND
AGND
AGND
AGND
AGND
AGND
VGL
VGL
VGL
VGL
VGL
VGL
VGL
VGL
VGL
AGNDDUM3
AGNDDUM4
VGH
VGH
VGH
VGH
VGH
VGH
AGNDDUM5
VCL
VCL
VCL
C13M
C13M
C13M
C13P
C13P
C13P
C21M
X
4865.0
4935.0
5005.0
5075.0
5145.0
5215.0
5285.0
5355.0
5425.0
5495.0
5565.0
5635.0
5705.0
5775.0
5845.0
5915.0
5985.0
6055.0
6125.0
6195.0
6265.0
6335.0
6405.0
6475.0
6545.0
6615.0
6685.0
6755.0
6825.0
6895.0
6965.0
7035.0
7105.0
7175.0
7245.0
7315.0
7385.0
7455.0
7525.0
7595.0
7665.0
7735.0
7805.0
7875.0
7945.0
8015.0
8085.0
8155.0
8225.0
8295.0
Y
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
2008.04.21 rev0.1
pad No
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
pad name
C21M
C21M
C21P
C21P
C21P
C22M
C22M
C22M
C22P
C22P
C22P
TESTO1
TESTO2
TESTO3
TESTO4
VGLDMY1
G2
G4
G6
G8
G10
G12
G14
G16
G18
G20
G22
G24
G26
G28
G30
G32
G34
G36
G38
G40
G42
G44
G46
G48
G50
G52
G54
G56
G58
G60
G62
G64
G66
G68
X
8365.0
8435.0
8505.0
8575.0
8645.0
8715.0
8785.0
8855.0
8925.0
8995.0
9065.0
9135.0
9397.5
9382.5
9367.5
9352.5
9337.5
9322.5
9307.5
9292.5
9277.5
9262.5
9247.5
9232.5
9217.5
9202.5
9187.5
9172.5
9157.5
9142.5
9127.5
9112.5
9097.5
9082.5
9067.5
9052.5
9037.5
9022.5
9007.5
8992.5
8977.5
8962.5
8947.5
8932.5
8917.5
8902.5
8887.5
8872.5
8857.5
8842.5
Y
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
-269.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
R61509V Pad Coordinate （Unit：μm）
pad No
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
pad name
G70
G72
G74
G76
G78
G80
G82
G84
G86
G88
G90
G92
G94
G96
G98
G100
G102
G104
G106
G108
G110
G112
G114
G116
G118
G120
G122
G124
G126
G128
G130
G132
G134
G136
G138
G140
G142
G144
G146
G148
G150
G152
G154
G156
G158
G160
G162
G164
G166
G168
X
8827.5
8812.5
8797.5
8782.5
8767.5
8752.5
8737.5
8722.5
8707.5
8692.5
8677.5
8662.5
8647.5
8632.5
8617.5
8602.5
8587.5
8572.5
8557.5
8542.5
8527.5
8512.5
8497.5
8482.5
8467.5
8452.5
8437.5
8422.5
8407.5
8392.5
8377.5
8362.5
8347.5
8332.5
8317.5
8302.5
8287.5
8272.5
8257.5
8242.5
8227.5
8212.5
8197.5
8182.5
8167.5
8152.5
8137.5
8122.5
8107.5
8092.5
Y
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
2008.04.21 rev0.1
pad No
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
pad name
G170
G172
G174
G176
G178
G180
G182
G184
G186
G188
G190
G192
G194
G196
G198
G200
G202
G204
G206
G208
G210
G212
G214
G216
G218
G220
G222
G224
G226
G228
G230
G232
G234
G236
G238
G240
G242
G244
G246
G248
G250
G252
G254
G256
G258
G260
G262
G264
G266
G268
X
8077.5
8062.5
8047.5
8032.5
8017.5
8002.5
7987.5
7972.5
7957.5
7942.5
7927.5
7912.5
7897.5
7882.5
7867.5
7852.5
7837.5
7822.5
7807.5
7792.5
7777.5
7762.5
7747.5
7732.5
7717.5
7702.5
7687.5
7672.5
7657.5
7642.5
7627.5
7612.5
7597.5
7582.5
7567.5
7552.5
7537.5
7522.5
7507.5
7492.5
7477.5
7462.5
7447.5
7432.5
7417.5
7402.5
7387.5
7372.5
7357.5
7342.5
Y
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
R61509V Pad Coordinate （Unit：μm）
pad No
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
pad name
G270
G272
G274
G276
G278
G280
G282
G284
G286
G288
G290
G292
G294
G296
G298
G300
G302
G304
G306
G308
G310
G312
G314
G316
G318
G320
G322
G324
G326
G328
G330
G332
G334
G336
G338
G340
G342
G344
G346
G348
G350
G352
G354
G356
G358
G360
G362
G364
G366
G368
X
7327.5
7312.5
7297.5
7282.5
7267.5
7252.5
7237.5
7222.5
7207.5
7192.5
7177.5
7162.5
7147.5
7132.5
7117.5
7102.5
7087.5
7072.5
7057.5
7042.5
7027.5
7012.5
6997.5
6982.5
6967.5
6952.5
6937.5
6922.5
6907.5
6892.5
6877.5
6862.5
6847.5
6832.5
6817.5
6802.5
6787.5
6772.5
6757.5
6742.5
6727.5
6712.5
6697.5
6682.5
6667.5
6652.5
6637.5
6622.5
6607.5
6592.5
Y
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
2008.04.21 rev0.1
pad No
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
pad name
G370
G372
G374
G376
G378
G380
G382
G384
G386
G388
G390
G392
G394
G396
G398
G400
G402
G404
G406
G408
G410
G412
G414
G416
G418
G420
G422
G424
G426
G428
G430
G432
VGLDMY2
TESTO5
S720
S719
S718
S717
S716
S715
S714
S713
S712
S711
S710
S709
S708
S707
S706
S705
X
6577.5
6562.5
6547.5
6532.5
6517.5
6502.5
6487.5
6472.5
6457.5
6442.5
6427.5
6412.5
6397.5
6382.5
6367.5
6352.5
6337.5
6322.5
6307.5
6292.5
6277.5
6262.5
6247.5
6232.5
6217.5
6202.5
6187.5
6172.5
6157.5
6142.5
6127.5
6112.5
6097.5
5887.5
5872.5
5857.5
5842.5
5827.5
5812.5
5797.5
5782.5
5767.5
5752.5
5737.5
5722.5
5707.5
5692.5
5677.5
5662.5
5647.5
Y
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
R61509V Pad Coordinate （Unit：μm）
pad No
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
pad name
S704
S703
S702
S701
S700
S699
S698
S697
S696
S695
S694
S693
S692
S691
S690
S689
S688
S687
S686
S685
S684
S683
S682
S681
S680
S679
S678
S677
S676
S675
S674
S673
S672
S671
S670
S669
S668
S667
S666
S665
S664
S663
S662
S661
S660
S659
S658
S657
S656
S655
X
5632.5
5617.5
5602.5
5587.5
5572.5
5557.5
5542.5
5527.5
5512.5
5497.5
5482.5
5467.5
5452.5
5437.5
5422.5
5407.5
5392.5
5377.5
5362.5
5347.5
5332.5
5317.5
5302.5
5287.5
5272.5
5257.5
5242.5
5227.5
5212.5
5197.5
5182.5
5167.5
5152.5
5137.5
5122.5
5107.5
5092.5
5077.5
5062.5
5047.5
5032.5
5017.5
5002.5
4987.5
4972.5
4957.5
4942.5
4927.5
4912.5
4897.5
Y
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
2008.04.21 rev0.1
pad No
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
pad name
S654
S653
S652
S651
S650
S649
S648
S647
S646
S645
S644
S643
S642
S641
S640
S639
S638
S637
S636
S635
S634
S633
S632
S631
S630
S629
S628
S627
S626
S625
S624
S623
S622
S621
S620
S619
S618
S617
S616
S615
S614
S613
S612
S611
S610
S609
S608
S607
S606
S605
X
4882.5
4867.5
4852.5
4837.5
4822.5
4807.5
4792.5
4777.5
4762.5
4747.5
4732.5
4717.5
4702.5
4687.5
4672.5
4657.5
4642.5
4627.5
4612.5
4597.5
4582.5
4567.5
4552.5
4537.5
4522.5
4507.5
4492.5
4477.5
4462.5
4447.5
4432.5
4417.5
4402.5
4387.5
4372.5
4357.5
4342.5
4327.5
4312.5
4297.5
4282.5
4267.5
4252.5
4237.5
4222.5
4207.5
4192.5
4177.5
4162.5
4147.5
Y
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
R61509V Pad Coordinate （Unit：μm）
pad No
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
pad name
S604
S603
S602
S601
S600
S599
S598
S597
S596
S595
S594
S593
S592
S591
S590
S589
S588
S587
S586
S585
S584
S583
S582
S581
S580
S579
S578
S577
S576
S575
S574
S573
S572
S571
S570
S569
S568
S567
S566
S565
S564
S563
S562
S561
S560
S559
S558
S557
S556
S555
X
4132.5
4117.5
4102.5
4087.5
4072.5
4057.5
4042.5
4027.5
4012.5
3997.5
3982.5
3967.5
3952.5
3937.5
3922.5
3907.5
3892.5
3877.5
3862.5
3847.5
3832.5
3817.5
3802.5
3787.5
3772.5
3757.5
3742.5
3727.5
3712.5
3697.5
3682.5
3667.5
3652.5
3637.5
3622.5
3607.5
3592.5
3577.5
3562.5
3547.5
3532.5
3517.5
3502.5
3487.5
3472.5
3457.5
3442.5
3427.5
3412.5
3397.5
Y
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
2008.04.21 rev0.1
pad No
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
pad name
S554
S553
S552
S551
S550
S549
S548
S547
S546
S545
S544
S543
S542
S541
S540
S539
S538
S537
S536
S535
S534
S533
S532
S531
S530
S529
S528
S527
S526
S525
S524
S523
S522
S521
S520
S519
S518
S517
S516
S515
S514
S513
S512
S511
S510
S509
S508
S507
S506
S505
X
3382.5
3367.5
3352.5
3337.5
3322.5
3307.5
3292.5
3277.5
3262.5
3247.5
3232.5
3217.5
3202.5
3187.5
3172.5
3157.5
3142.5
3127.5
3112.5
3097.5
3082.5
3067.5
3052.5
3037.5
3022.5
3007.5
2992.5
2977.5
2962.5
2947.5
2932.5
2917.5
2902.5
2887.5
2872.5
2857.5
2842.5
2827.5
2812.5
2797.5
2782.5
2767.5
2752.5
2737.5
2722.5
2707.5
2692.5
2677.5
2662.5
2647.5
Y
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
R61509V Pad Coordinate （Unit：μm）
pad No
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
pad name
S504
S503
S502
S501
S500
S499
S498
S497
S496
S495
S494
S493
S492
S491
S490
S489
S488
S487
S486
S485
S484
S483
S482
S481
S480
S479
S478
S477
S476
S475
S474
S473
S472
S471
S470
S469
S468
S467
S466
S465
S464
S463
S462
S461
S460
S459
S458
S457
S456
S455
X
2632.5
2617.5
2602.5
2587.5
2572.5
2557.5
2542.5
2527.5
2512.5
2497.5
2482.5
2467.5
2452.5
2437.5
2422.5
2407.5
2392.5
2377.5
2362.5
2347.5
2332.5
2317.5
2302.5
2287.5
2272.5
2257.5
2242.5
2227.5
2212.5
2197.5
2182.5
2167.5
2152.5
2137.5
2122.5
2107.5
2092.5
2077.5
2062.5
2047.5
2032.5
2017.5
2002.5
1987.5
1972.5
1957.5
1942.5
1927.5
1912.5
1897.5
Y
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
2008.04.21 rev0.1
pad No
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
pad name
S454
S453
S452
S451
S450
S449
S448
S447
S446
S445
S444
S443
S442
S441
S440
S439
S438
S437
S436
S435
S434
S433
S432
S431
S430
S429
S428
S427
S426
S425
S424
S423
S422
S421
S420
S419
S418
S417
S416
S415
S414
S413
S412
S411
S410
S409
S408
S407
S406
S405
X
1882.5
1867.5
1852.5
1837.5
1822.5
1807.5
1792.5
1777.5
1762.5
1747.5
1732.5
1717.5
1702.5
1687.5
1672.5
1657.5
1642.5
1627.5
1612.5
1597.5
1582.5
1567.5
1552.5
1537.5
1522.5
1507.5
1492.5
1477.5
1462.5
1447.5
1432.5
1417.5
1402.5
1387.5
1372.5
1357.5
1342.5
1327.5
1312.5
1297.5
1282.5
1267.5
1252.5
1237.5
1222.5
1207.5
1192.5
1177.5
1162.5
1147.5
Y
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
R61509V Pad Coordinate （Unit：μm）
pad No
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
pad name
S404
S403
S402
S401
S400
S399
S398
S397
S396
S395
S394
S393
S392
S391
S390
S389
S388
S387
S386
S385
S384
S383
S382
S381
S380
S379
S378
S377
S376
S375
S374
S373
S372
S371
S370
S369
S368
S367
S366
S365
S364
S363
S362
S361
TESTO6
TESTO7
TESTO8
TESTO9
TESTO10
TESTO11
X
1132.5
1117.5
1102.5
1087.5
1072.5
1057.5
1042.5
1027.5
1012.5
997.5
982.5
967.5
952.5
937.5
922.5
907.5
892.5
877.5
862.5
847.5
832.5
817.5
802.5
787.5
772.5
757.5
742.5
727.5
712.5
697.5
682.5
667.5
652.5
637.5
622.5
607.5
592.5
577.5
562.5
547.5
532.5
517.5
502.5
487.5
472.5
457.5
442.5
427.5
-427.5
-442.5
Y
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
2008.04.21 rev0.1
pad No
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
pad name
TESTO12
TESTO13
S360
S359
S358
S357
S356
S355
S354
S353
S352
S351
S350
S349
S348
S347
S346
S345
S344
S343
S342
S341
S340
S339
S338
S337
S336
S335
S334
S333
S332
S331
S330
S329
S328
S327
S326
S325
S324
S323
S322
S321
S320
S319
S318
S317
S316
S315
S314
S313
X
-457.5
-472.5
-487.5
-502.5
-517.5
-532.5
-547.5
-562.5
-577.5
-592.5
-607.5
-622.5
-637.5
-652.5
-667.5
-682.5
-697.5
-712.5
-727.5
-742.5
-757.5
-772.5
-787.5
-802.5
-817.5
-832.5
-847.5
-862.5
-877.5
-892.5
-907.5
-922.5
-937.5
-952.5
-967.5
-982.5
-997.5
-1012.5
-1027.5
-1042.5
-1057.5
-1072.5
-1087.5
-1102.5
-1117.5
-1132.5
-1147.5
-1162.5
-1177.5
-1192.5
Y
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
R61509V Pad Coordinate （Unit：μm）
pad No
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
pad name
S312
S311
S310
S309
S308
S307
S306
S305
S304
S303
S302
S301
S300
S299
S298
S297
S296
S295
S294
S293
S292
S291
S290
S289
S288
S287
S286
S285
S284
S283
S282
S281
S280
S279
S278
S277
S276
S275
S274
S273
S272
S271
S270
S269
S268
S267
S266
S265
S264
S263
X
-1207.5
-1222.5
-1237.5
-1252.5
-1267.5
-1282.5
-1297.5
-1312.5
-1327.5
-1342.5
-1357.5
-1372.5
-1387.5
-1402.5
-1417.5
-1432.5
-1447.5
-1462.5
-1477.5
-1492.5
-1507.5
-1522.5
-1537.5
-1552.5
-1567.5
-1582.5
-1597.5
-1612.5
-1627.5
-1642.5
-1657.5
-1672.5
-1687.5
-1702.5
-1717.5
-1732.5
-1747.5
-1762.5
-1777.5
-1792.5
-1807.5
-1822.5
-1837.5
-1852.5
-1867.5
-1882.5
-1897.5
-1912.5
-1927.5
-1942.5
Y
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
2008.04.21 rev0.1
pad No
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
pad name
S262
S261
S260
S259
S258
S257
S256
S255
S254
S253
S252
S251
S250
S249
S248
S247
S246
S245
S244
S243
S242
S241
S240
S239
S238
S237
S236
S235
S234
S233
S232
S231
S230
S229
S228
S227
S226
S225
S224
S223
S222
S221
S220
S219
S218
S217
S216
S215
S214
S213
X
-1957.5
-1972.5
-1987.5
-2002.5
-2017.5
-2032.5
-2047.5
-2062.5
-2077.5
-2092.5
-2107.5
-2122.5
-2137.5
-2152.5
-2167.5
-2182.5
-2197.5
-2212.5
-2227.5
-2242.5
-2257.5
-2272.5
-2287.5
-2302.5
-2317.5
-2332.5
-2347.5
-2362.5
-2377.5
-2392.5
-2407.5
-2422.5
-2437.5
-2452.5
-2467.5
-2482.5
-2497.5
-2512.5
-2527.5
-2542.5
-2557.5
-2572.5
-2587.5
-2602.5
-2617.5
-2632.5
-2647.5
-2662.5
-2677.5
-2692.5
Y
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
R61509V Pad Coordinate （Unit：μm）
pad No
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
pad name
S212
S211
S210
S209
S208
S207
S206
S205
S204
S203
S202
S201
S200
S199
S198
S197
S196
S195
S194
S193
S192
S191
S190
S189
S188
S187
S186
S185
S184
S183
S182
S181
S180
S179
S178
S177
S176
S175
S174
S173
S172
S171
S170
S169
S168
S167
S166
S165
S164
S163
X
-2707.5
-2722.5
-2737.5
-2752.5
-2767.5
-2782.5
-2797.5
-2812.5
-2827.5
-2842.5
-2857.5
-2872.5
-2887.5
-2902.5
-2917.5
-2932.5
-2947.5
-2962.5
-2977.5
-2992.5
-3007.5
-3022.5
-3037.5
-3052.5
-3067.5
-3082.5
-3097.5
-3112.5
-3127.5
-3142.5
-3157.5
-3172.5
-3187.5
-3202.5
-3217.5
-3232.5
-3247.5
-3262.5
-3277.5
-3292.5
-3307.5
-3322.5
-3337.5
-3352.5
-3367.5
-3382.5
-3397.5
-3412.5
-3427.5
-3442.5
Y
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
2008.04.21 rev0.1
pad No
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
pad name
S162
S161
S160
S159
S158
S157
S156
S155
S154
S153
S152
S151
S150
S149
S148
S147
S146
S145
S144
S143
S142
S141
S140
S139
S138
S137
S136
S135
S134
S133
S132
S131
S130
S129
S128
S127
S126
S125
S124
S123
S122
S121
S120
S119
S118
S117
S116
S115
S114
S113
X
-3457.5
-3472.5
-3487.5
-3502.5
-3517.5
-3532.5
-3547.5
-3562.5
-3577.5
-3592.5
-3607.5
-3622.5
-3637.5
-3652.5
-3667.5
-3682.5
-3697.5
-3712.5
-3727.5
-3742.5
-3757.5
-3772.5
-3787.5
-3802.5
-3817.5
-3832.5
-3847.5
-3862.5
-3877.5
-3892.5
-3907.5
-3922.5
-3937.5
-3952.5
-3967.5
-3982.5
-3997.5
-4012.5
-4027.5
-4042.5
-4057.5
-4072.5
-4087.5
-4102.5
-4117.5
-4132.5
-4147.5
-4162.5
-4177.5
-4192.5
Y
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
R61509V Pad Coordinate （Unit：μm）
pad No
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
pad name
S112
S111
S110
S109
S108
S107
S106
S105
S104
S103
S102
S101
S100
S99
S98
S97
S96
S95
S94
S93
S92
S91
S90
S89
S88
S87
S86
S85
S84
S83
S82
S81
S80
S79
S78
S77
S76
S75
S74
S73
S72
S71
S70
S69
S68
S67
S66
S65
S64
S63
X
-4207.5
-4222.5
-4237.5
-4252.5
-4267.5
-4282.5
-4297.5
-4312.5
-4327.5
-4342.5
-4357.5
-4372.5
-4387.5
-4402.5
-4417.5
-4432.5
-4447.5
-4462.5
-4477.5
-4492.5
-4507.5
-4522.5
-4537.5
-4552.5
-4567.5
-4582.5
-4597.5
-4612.5
-4627.5
-4642.5
-4657.5
-4672.5
-4687.5
-4702.5
-4717.5
-4732.5
-4747.5
-4762.5
-4777.5
-4792.5
-4807.5
-4822.5
-4837.5
-4852.5
-4867.5
-4882.5
-4897.5
-4912.5
-4927.5
-4942.5
Y
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
2008.04.21 rev0.1
pad No
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
pad name
S62
S61
S60
S59
S58
S57
S56
S55
S54
S53
S52
S51
S50
S49
S48
S47
S46
S45
S44
S43
S42
S41
S40
S39
S38
S37
S36
S35
S34
S33
S32
S31
S30
S29
S28
S27
S26
S25
S24
S23
S22
S21
S20
S19
S18
S17
S16
S15
S14
S13
X
-4957.5
-4972.5
-4987.5
-5002.5
-5017.5
-5032.5
-5047.5
-5062.5
-5077.5
-5092.5
-5107.5
-5122.5
-5137.5
-5152.5
-5167.5
-5182.5
-5197.5
-5212.5
-5227.5
-5242.5
-5257.5
-5272.5
-5287.5
-5302.5
-5317.5
-5332.5
-5347.5
-5362.5
-5377.5
-5392.5
-5407.5
-5422.5
-5437.5
-5452.5
-5467.5
-5482.5
-5497.5
-5512.5
-5527.5
-5542.5
-5557.5
-5572.5
-5587.5
-5602.5
-5617.5
-5632.5
-5647.5
-5662.5
-5677.5
-5692.5
Y
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
R61509V Pad Coordinate （Unit：μm）
pad No
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
pad name
S12
S11
S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
TESTO14
VGLDMY3
G431
G429
G427
G425
G423
G421
G419
G417
G415
G413
G411
G409
G407
G405
G403
G401
G399
G397
G395
G393
G391
G389
G387
G385
G383
G381
G379
G377
G375
G373
G371
G369
G367
G365
G363
G361
X
-5707.5
-5722.5
-5737.5
-5752.5
-5767.5
-5782.5
-5797.5
-5812.5
-5827.5
-5842.5
-5857.5
-5872.5
-5887.5
-6097.5
-6112.5
-6127.5
-6142.5
-6157.5
-6172.5
-6187.5
-6202.5
-6217.5
-6232.5
-6247.5
-6262.5
-6277.5
-6292.5
-6307.5
-6322.5
-6337.5
-6352.5
-6367.5
-6382.5
-6397.5
-6412.5
-6427.5
-6442.5
-6457.5
-6472.5
-6487.5
-6502.5
-6517.5
-6532.5
-6547.5
-6562.5
-6577.5
-6592.5
-6607.5
-6622.5
-6637.5
Y
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
2008.04.21 rev0.1
pad No
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291
1292
1293
1294
1295
1296
1297
1298
1299
1300
pad name
G359
G357
G355
G353
G351
G349
G347
G345
G343
G341
G339
G337
G335
G333
G331
G329
G327
G325
G323
G321
G319
G317
G315
G313
G311
G309
G307
G305
G303
G301
G299
G297
G295
G293
G291
G289
G287
G285
G283
G281
G279
G277
G275
G273
G271
G269
G267
G265
G263
G261
X
-6652.5
-6667.5
-6682.5
-6697.5
-6712.5
-6727.5
-6742.5
-6757.5
-6772.5
-6787.5
-6802.5
-6817.5
-6832.5
-6847.5
-6862.5
-6877.5
-6892.5
-6907.5
-6922.5
-6937.5
-6952.5
-6967.5
-6982.5
-6997.5
-7012.5
-7027.5
-7042.5
-7057.5
-7072.5
-7087.5
-7102.5
-7117.5
-7132.5
-7147.5
-7162.5
-7177.5
-7192.5
-7207.5
-7222.5
-7237.5
-7252.5
-7267.5
-7282.5
-7297.5
-7312.5
-7327.5
-7342.5
-7357.5
-7372.5
-7387.5
Y
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
R61509V Pad Coordinate （Unit：μm）
pad No
1301
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318
1319
1320
1321
1322
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342
1343
1344
1345
1346
1347
1348
1349
1350
pad name
G259
G257
G255
G253
G251
G249
G247
G245
G243
G241
G239
G237
G235
G233
G231
G229
G227
G225
G223
G221
G219
G217
G215
G213
G211
G209
G207
G205
G203
G201
G199
G197
G195
G193
G191
G189
G187
G185
G183
G181
G179
G177
G175
G173
G171
G169
G167
G165
G163
G161
X
-7402.5
-7417.5
-7432.5
-7447.5
-7462.5
-7477.5
-7492.5
-7507.5
-7522.5
-7537.5
-7552.5
-7567.5
-7582.5
-7597.5
-7612.5
-7627.5
-7642.5
-7657.5
-7672.5
-7687.5
-7702.5
-7717.5
-7732.5
-7747.5
-7762.5
-7777.5
-7792.5
-7807.5
-7822.5
-7837.5
-7852.5
-7867.5
-7882.5
-7897.5
-7912.5
-7927.5
-7942.5
-7957.5
-7972.5
-7987.5
-8002.5
-8017.5
-8032.5
-8047.5
-8062.5
-8077.5
-8092.5
-8107.5
-8122.5
-8137.5
Y
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
2008.04.21 rev0.1
pad No
1351
1352
1353
1354
1355
1356
1357
1358
1359
1360
1361
1362
1363
1364
1365
1366
1367
1368
1369
1370
1371
1372
1373
1374
1375
1376
1377
1378
1379
1380
1381
1382
1383
1384
1385
1386
1387
1388
1389
1390
1391
1392
1393
1394
1395
1396
1397
1398
1399
1400
pad name
G159
G157
G155
G153
G151
G149
G147
G145
G143
G141
G139
G137
G135
G133
G131
G129
G127
G125
G123
G121
G119
G117
G115
G113
G111
G109
G107
G105
G103
G101
G99
G97
G95
G93
G91
G89
G87
G85
G83
G81
G79
G77
G75
G73
G71
G69
G67
G65
G63
G61
X
-8152.5
-8167.5
-8182.5
-8197.5
-8212.5
-8227.5
-8242.5
-8257.5
-8272.5
-8287.5
-8302.5
-8317.5
-8332.5
-8347.5
-8362.5
-8377.5
-8392.5
-8407.5
-8422.5
-8437.5
-8452.5
-8467.5
-8482.5
-8497.5
-8512.5
-8527.5
-8542.5
-8557.5
-8572.5
-8587.5
-8602.5
-8617.5
-8632.5
-8647.5
-8662.5
-8677.5
-8692.5
-8707.5
-8722.5
-8737.5
-8752.5
-8767.5
-8782.5
-8797.5
-8812.5
-8827.5
-8842.5
-8857.5
-8872.5
-8887.5
Y
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
R61509V Pad Coordinate （Unit：μm）
pad No
1401
1402
1403
1404
1405
1406
1407
1408
1409
1410
1411
1412
1413
1414
1415
1416
1417
1418
1419
1420
1421
1422
1423
1424
1425
1426
1427
1428
1429
1430
1431
1432
1433
1434
pad name
G59
G57
G55
G53
G51
G49
G47
G45
G43
G41
G39
G37
G35
G33
G31
G29
G27
G25
G23
G21
G19
G17
G15
G13
G11
G9
G7
G5
G3
G1
VGLDMY4
TESTO15
DUMMYR3
DUMMYR4
X
-8902.5
-8917.5
-8932.5
-8947.5
-8962.5
-8977.5
-8992.5
-9007.5
-9022.5
-9037.5
-9052.5
-9067.5
-9082.5
-9097.5
-9112.5
-9127.5
-9142.5
-9157.5
-9172.5
-9187.5
-9202.5
-9217.5
-9232.5
-9247.5
-9262.5
-9277.5
-9292.5
-9307.5
-9322.5
-9337.5
-9352.5
-9367.5
-9382.5
-9397.5
Y
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
157.0
276.0
2008.04.21 rev0.1
Alignment mark
1-a
1-b
X
-9381.0
9381.0
Y
-251.0
-251.0
Rev0.1 2008.04.21
Pad No66 IM0/ID→IM0_ID (rename)
Pad No69 RESET→RESETX (rename)
Pad No73 VSYNC→VSYNCX (rename)
Pad No74 HSYNC→HSYNCX (rename)
Pad No107 CS→CSX (rename)
Pad No109 WR/SCL →WRX_SCL (rename)
Pad No110 RD→RDX (rename)
R61509V
Target Spec
Bump Arrangement
㪪㪈䌾㪪㪎㪉㪇䋬㩷
㪞㪈䌾㪞㪋㪊㪉䋬㩷
㪛㪬㪤㪤㪰㪩㪎㪄㪈㪇㪃㩷
㪫㪜㪪㪫㪦㪈㪈㪄㪈㪏㪃㩷
㪭㪞㪣㪛㪤㪰㪈㪄㪋㩷
㩿㪥㫆㩷㪉㪍㪊㪄㪈㪋㪊㪋㪀
㩷
㩷
㩷
㩷
㩷
㩷
㩷
㩷
㩷
㩷
㩷
㩷
㩷
㩷
㩷
㩷
㩷
㩷
㩷
㩷
㩷
15
15
100
19
219
12
Unit : um
50
50
20
S=4,500um2
90
㪠㪆㪦㩷㫇㫀㫅㫊㩷
㩿㪥㫆㪈㩷㵨㩷㪉㪍㪉㪀㩷
12
70
Figure 3
Rev. 0.11 April 25, 2008, page 36 of 181
S=1,500um2
Unit : um
R61509V Wiring Example & Recommended Wiring Resistance
(Pad Arrangement Rev0.6)
2008.04.21 Rev0.5
Rev0.1 2008.02.14 Made for PR
Rev0.11 2008.02.19 VPP3C-->VPP3B, VPP2-->VPP1
Rev0.2 2008.02.28 Pad names changed.
Rev0.3 2008.0314 Instruction changed.
Rev0.4 2008.0402 R61517's EEPROM IF deleted.
R61509V VPP2--> VPP1
Rev0.5 2008.04.21 Pad names changed.
Pad No66 IM0/ID→IM0_ID
Pad No69 RESET→RESETX
Pad No73 VSYNC→VSYNCX
Pad No74 HSYNC→HSYNCX
Pad No107 CS→CSX
Pad No109 WR/SCL→WRX_SCL
Pad No110 RD→RDX
R61517 outline
VCOM
Pad No.
Recommended
max.Rcog [ohm]
R61509V outline
R61509V Pad name
□
TP
TP
VPP3A
p
VPP1
p
30
8
10
12
GND
p
9
IM2
IM1
IM0
in
in
in
60
60
60
PROTECT
RESX
in
in
out
out
in
in
60
60
60
60
60
60
60
DE
PCLK
DB17
DB16
in
in
io
io
60
60
60
60
DB15
DB14
DB13
DB12
io
io
io
io
60
60
60
60
DB11
DB10
DB9
io
io
io
60
60
60
LEDON
LEDPWM
VSYNC
HSYNC
10
IOVCC
(MIPI name: VDDI)
p
DB8
io
60
DB7
DB6
DB5
DB4
io
io
io
io
60
60
60
60
DB3
DB2
DB1
DB0
io
io
io
io
60
60
60
60
CSX
DCX
WRX/SCL
RDX
in
in
in
in
60
60
60
60
60
60
60
TE out
DIN in
DOUT out
1uF/6V/B
7
8
1uF/6V/B
10
1uF/6V/B
10
7
60
7
1uF/6V/B
60
60
When VCOMH is adjusted
using variable resisrance
> 200kΩ
12
1uF/6V/B
12
1uF/6V/B
12
12
1uF/6V/B
7
Capacitor is not required when VCI voltage is directly applied to VCI1 pin
15
When VCI1 is adjusted by register
1uF/6V/B
0ohm
VCI
(MIPI name: VDDI)
p
10
60
12
12
1uF/25V/B
6
VF<0.38V/5mA@25℃, VR≧25V
1uF/25V/B
6
VF<0.38V/5mA@25℃, VR≧25V
20
1uF/6V/B
20
1uF/6V/B
20
20
1uF/10V/B
20
20
1uF/10V/B
20
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
DUMMYR1
DUMMYR2
AGNDDUM1
VPP3B
VPP3B
VPP3B
VPP3B
AGNDDUM2
VPP3A
VPP3A
VPP1
VPP1
VPP1
VPP1
VPP1
VPP1
VPP1
GNDDUM1
VDDTEST
VREFC
VREFD
VREF
VCCDUM1
DUMMYA
DUMMYA
DUMMYA
DUMMYA
DUMMYA
GNDDUM2
AGND
AGND
AGND
AGND
AGND
AGND
GND
GND
GND
GND
GND
VCC
VCC
VCC
VCC
VCC
VCC
VCC
TS8
TS7
TS6
TS5
TS4
TS3
TS2
TS1
TS0
TEST5
TEST4
TEST3
TEST2
TEST1
GNDDUM3
TSC
IM2
IM1
IM0_ID
IOVCCDUM1
PROTECT
RESETX
GNDDUM4
DUMMYB
DUMMYB
VSYNCX
HSYNCX
IOVCCDUM2
ENABLE
DOTCLK
DB17
DB16
GNDDUM5
DB15
DB14
DB13
DB12
GNDDUM6
DB11
DB10
DB9
IOVCC
IOVCC
IOVCC
IOVCC
IOVCC
IOVCC
DB8
GNDDUM7
DB7
DB6
DB5
DB4
GNDDUM8
DB3
DB2
DB1
DB0
GNDDUM9
CSX
RS
WRX_SCL
RDX
GNDDUM10
FMARK
SDI
SDO
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VMON
VCOM
VCOM
VCOM
VCOM
VCOM
VCOM
VCOM
VCOM
VCOMH
VCOMH
VCOMH
VCOMH
VCOMH
VCOMH
VCOML
VCOML
VCOML
VCOML
VCOML
VCOML
GND
GND
GND
GND
GND
GND
GND
GND
GND
VGS
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
VTEST
VCIR
VREG1OUT
VCOMR
C11M
C11M
C11M
C11M
C11M
C11P
C11P
C11P
C11P
C11P
C12M
C12M
C12M
C12M
C12M
C12P
C12P
C12P
C12P
C12P
DDVDH
DDVDH
DDVDH
DDVDH
DDVDH
DDVDH
DDVDH
DDVDH
DDVDH
VCI1
VCI1
VCI1
VCI1
VCI
VCI
VCI
VCI
VCI
VCI
VCILVL
DUMMYC
DUMMYC
DUMMYC
DUMMYC
DUMMYC
GND
GND
GND
GND
GND
AGND
AGND
AGND
AGND
AGND
VGL
VGL
VGL
VGL
VGL
VGL
VGL
VGL
VGL
AGNDDUM3
AGNDDUM4
VGH
VGH
VGH
VGH
VGH
VGH
AGNDDUM5
VCL
VCL
VCL
C13M
C13M
C13M
C13P
C13P
C13P
C21M
C21M
C21M
C21P
C21P
C21P
C22M
C22M
C22M
C22P
C22P
C22P
TESTO1
□
□
□
Connect
Connect
Connect
Connect
to
to
to
to
AGNDDUM1/2
AGNDDUM1/2
AGNDDUM1/2
AGNDDUM1/2
□
□
□
□
□
BUMP
Top View
□
□
Connect to GNDDUM1
Connect to GNDDUM1
Open
Open
□
□
□
□
□
Open
Open
Open
Open
Open
□
□
□
□
□
□
□
□
□
Open
Open
Open
Open
Open
Open
Open
Open
Open
Connect
Connect
Connect
Connect
Connect
Chip
to
to
to
to
to
GNDDUM3
GNDDUM3
GNDDUM3
GNDDUM3
GNDDUM3
□
□
30um_Space
□
□
Connect
Connect
Connect
Connect
to
to
to
to
GNDDUM3
IOVCCDUM1/GNDDUM3
IOVCCDUM1/GNDDUM3
IOVCCDUM1/GNDDUM3
VCOM
Glass substrate
G427
G429
G431
VGLDMY3
30um
1
VCOM
□
□
Open
Open
30um
□
□
30um_Space
□
□
□
□
TESTO14
S1
S2
S3
S4
S5
Note: When using same glass substrate for the R61517 and
the R61509V, make sure that the R61517's VCOMA and
VCOMB for VCOM drive mode are same polarity.
The R61509V does not have VCOM output pin on the output
side (the area is just flat surface). When supplying voltage to
panel from four corners of it, draw wires from VCOM pins on the
I/O side.
□
□
□ Open
□
□
□
□
□
□
□
S356
S357
S358
S359
S360
TESTO13
TESTO12
TESTO11
TESTO10
840um
□
□
□
□
□
□
□
□
□
□
□
TESTO9
TESTO8
TESTO7
TESTO6
S361
S362
S363
S364
S365
Open
Open
□
□
□
□
30um_Space
□
□
S716
S717
S718
S719
S720
TESTO5
30um
VCOM
30um
□
□
30um_Space
□
□
□
□
□
□
□
□
□
□
□
□
□
□
□
VGLDMY2
G432
G430
G428
Open
Open
Open
Open
Open
Open
□
□
FPC
DUMMYR4
DUMMYR3
TESTO15
VGLDMY4
G1
G3
G5
G7
G9
G10
G8
G6
G4
G2
VGLDMY1
TESTO4
TESTO3
TESTO2
R61509V
Target Spec
GRAM Address Map
GS=0 GS=1
S720
S719
S718
S717
S716
S715
S714
S713
S712
S711
S710
・・・・・
S709
S12
S11
S10
S9
S8
S7
S6
S5
S4
S3
S2
S/G pin
S1
Table 11 GRAM address and display position on the panel (SS = 0, BGR = 0)
WD[17:0]
WD[17:0]
WD[17:0]
WD[17:0]
・・・・・
WD[17:0]
WD[17:0]
WD[17:0]
WD[17:0]
G1
G432
h00000
h00001
h00002
h00003
・・・・・
h000EC
h000ED
h000EE
h000EF
G2
G431
h00100
h00101
h00102
h00103
・・・・・
h001EC
h001ED
h001EE
h001EF
G3
G430
h00200
h00201
h00202
h00203
・・・・・
h002EC
h002ED
h002EE
h002EF
G4
G429
h00300
h00301
h00302
h00303
・・・・・
h003EC
h003ED
h003EE
h003EF
G5
G428
h00400
h00401
h00402
h00403
・・・・・
h004EC
h004ED
h004EE
h004EF
G6
G427
h00500
h00501
h00502
h00503
・・・・・
h005EC
h005ED
h005EE
h005EF
G7
G426
h00600
h00601
h00602
h00603
・・・・・
h006EC
h006ED
h006EE
h006EF
G8
G425
h00700
h00701
h00702
h00703
・・・・・
h007EC
h007ED
h007EE
h007EF
G9
G424
h00800
h00801
h00802
h00803
・・・・・
h008EC
h008ED
h008EE
h008EF
G10
G423
h00900
h00901
h00902
h00903
・・・・・
h009EC
h009ED
h009EE
h009EF
G11
G422
h00A00
h00A01
h00A02
h00A03
・・・・・
h00AEC
h00AED
h00AEE
h00AEF
G12
G421
h00B00
h00B01
h00B02
h00B03
・・・・・
h00BEC
h00BED
h00BEE
h00BEF
G13
G420
h00C00
h00C01
h00C02
h00C03
・・・・・
h00CEC
h00CED
h00CEE
h00CEF
G14
G419
h00D00
h00D01
h00D02
h00D03
・・・・・
h00DEC
h00DED
h00DEE
h00DEF
G15
G418
h00E00
h00E01
h00E02
h00E03
・・・・・
h00EEC
h00EED
h00EEE
h00EEF
G16
G417
h00F00
h00F01
h00F02
h00F03
・・・・・
h00FEC
h00FED
h00FEE
h00FEF
G17
G416
h01000
h01001
h01002
h01003
・・・・・
h010EC
h010ED
h010EE
h010EF
G18
G415
h01100
h01101
h01102
h01103
・・・・・
h011EC
h011ED
h011EE
h011EF
G19
G414
h01200
h01201
h01202
h01203
・・・・・
h012EC
h012ED
h012EE
h012EF
G20
G413
h01300
h01301
h01302
h01303
・・・・・
h013EC
h013ED
h013EE
h013EF
：
：
：
：
：
：
：
：
：
：
：
：
：
：
：
：
：
：
：
：
G417
G16
h1A000
h1A001
h1A002
h1A003
・・・・・
h1A0EC
h1A0ED
h1A0EE
h1A0EF
G418
G15
h1A100
h1A101
h1A102
h1A103
・・・・・
h1A1EC
h1A1ED
h1A1EE
h1A1EF
G419
G14
h1A200
h1A201
h1A202
h1A203
・・・・・
h1A2EC
h1A2ED
h1A2EE
h1A2EF
G420
G13
h1A300
h1A301
h1A302
h1A303
・・・・・
h1A3EC
h1A3ED
h1A3EE
h1A3EF
G421
G12
h1A400
h1A401
h1A402
h1A403
・・・・・
h1A4EC
h1A4ED
h1A4EE
h1A4EF
G422
G11
h1A500
h1A501
h1A502
h1A503
・・・・・
h1A5EC
h1A5ED
h1A5EE
h1A5EF
G423
G10
h1A600
h1A601
h1A602
h1A603
・・・・・
h1A6EC
h1A6ED
h1A6EE
h1A6EF
G424
G9
h1A700
h1A701
h1A702
h1A703
・・・・・
h1A7EC
h1A7ED
h1A7EE
h1A7EF
G425
G8
h1A800
h1A801
h1A802
h1A803
・・・・・
h1A8EC
h1A8ED
h1A8EE
h1A8EF
G426
G7
h1A900
h1A901
h1A902
h1A903
・・・・・
h1A9EC
h1A9ED
h1A9EE
h1A9EF
G427
G6
h1AA00
h1AA01
h1AA02
h1AA03
・・・・・
h1AAEC
h1AAED
h1AAEE
h1AAEF
G428
G5
h1AB00
h1AB01
h1AB02
h1AB03
・・・・・
h1ABEC
h1ABED
h1ABEE
h1ABEF
G429
G4
h1AC00
h1AC01
h1AC02
h1AC03
・・・・・
h1ACEC
h1ACED
h1ACEE
h1ACEF
G430
G3
h1AD00
h1AD01
h1AD02
h1AD03
・・・・・
h1ADEC
h1ADED
h1ADEE
h1ADEF
G431
G2
h1AE00
h1AE01
h1AE02
h1AE03
・・・・・
h1AEEC
h1AEED
h1AEEE
h1AEEF
G432
G1
h1AF00
h1AF01
h1AF02
h1AF03
・・・・・
h1AFEC
h1AFED
h1AFEE
h1AFEF
Rev. 0.11 April 25, 2008, page 38 of 181
R61509V
Target Spec
GS=0 GS=1 WD[17:0]
S1
S3
S2
S4
S5
S6
S7
S8
S9
S10
S11
・・・・・
S12
S709
S710
S711
S712
S713
S714
S715
S716
S717
S718
S719
S/G pin
S720
Table 12 GRAM address and display position on the panel (SS = 1, BGR = 1)
WD[17:0]
WD[17:0]
WD[17:0]
・・・・・
WD[17:0]
WD[17:0]
WD[17:0]
WD[17:0]
G1
G432
h00000
h00001
h00002
h00003
・・・・・
h000EC
h000ED
h000EE
h000EF
G2
G431
h00100
h00101
h00102
h00103
・・・・・
h001EC
h001ED
h001EE
h001EF
G3
G430
h00200
h00201
h00202
h00203
・・・・・
h002EC
h002ED
h002EE
h002EF
G4
G429
h00300
h00301
h00302
h00303
・・・・・
h003EC
h003ED
h003EE
h003EF
G5
G428
h00400
h00401
h00402
h00403
・・・・・
h004EC
h004ED
h004EE
h004EF
G6
G427
h00500
h00501
h00502
h00503
・・・・・
h005EC
h005ED
h005EE
h005EF
G7
G426
h00600
h00601
h00602
h00603
・・・・・
h006EC
h006ED
h006EE
h006EF
G8
G425
h00700
h00701
h00702
h00703
・・・・・
h007EC
h007ED
h007EE
h007EF
G9
G424
h00800
h00801
h00802
h00803
・・・・・
h008EC
h008ED
h008EE
h008EF
G10 G423
h00900
h00901
h00902
h00903
・・・・・
h009EC
h009ED
h009EE
h009EF
G11 G422
h00A00
h00A01
h00A02
h00A03
・・・・・
h00AEC
h00AED
h00AEE
h00AEF
G12 G421
h00B00
h00B01
h00B02
h00B03
・・・・・
h00BEC
h00BED
h00BEE
h00BEF
G13 G420
h00C00
h00C01
h00C02
h00C03
・・・・・
h00CEC
h00CED
h00CEE
h00CEF
G14 G419
h00D00
h00D01
h00D02
h00D03
・・・・・
h00DEC
h00DED
h00DEE
h00DEF
G15 G418
h00E00
h00E01
h00E02
h00E03
・・・・・
h00EEC
h00EED
h00EEE
h00EEF
G16 G417
h00F00
h00F01
h00F02
h00F03
・・・・・
h00FEC
h00FED
h00FEE
h00FEF
G17 G416
h01000
h01001
h01002
h01003
・・・・・
h010EC
h010ED
h010EE
h010EF
G18 G415
h01100
h01101
h01102
h01103
・・・・・
h011EC
h011ED
h011EE
h011EF
G19 G414
h01200
h01201
h01202
h01203
・・・・・
h012EC
h012ED
h012EE
h012EF
G20 G413
h01300
h01301
h01302
h01303
・・・・・
h013EC
h013ED
h013EE
h013EF
：
：
：
：
：
：
：
：
：
：
：
：
：
：
：
：
：
：
：
：
G417 G16
h1A000
h1A001
h1A002
h1A003
・・・・・
h1A0EC
h1A0ED
h1A0EE
h1A0EF
G418 G15
h1A100
h1A101
h1A102
h1A103
・・・・・
h1A1EC
h1A1ED
h1A1EE
h1A1EF
G419 G14
h1A200
h1A201
h1A202
h1A203
・・・・・
h1A2EC
h1A2ED
h1A2EE
h1A2EF
G420 G13
h1A300
h1A301
h1A302
h1A303
・・・・・
h1A3EC
h1A3ED
h1A3EE
h1A3EF
G421 G12
h1A400
h1A401
h1A402
h1A403
・・・・・
h1A4EC
h1A4ED
h1A4EE
h1A4EF
G422 G11
h1A500
h1A501
h1A502
h1A503
・・・・・
h1A5EC
h1A5ED
h1A5EE
h1A5EF
G423 G10
h1A600
h1A601
h1A602
h1A603
・・・・・
h1A6EC
h1A6ED
h1A6EE
h1A6EF
G424
G9
h1A700
h1A701
h1A702
h1A703
・・・・・
h1A7EC
h1A7ED
h1A7EE
h1A7EF
G425
G8
h1A800
h1A801
h1A802
h1A803
・・・・・
h1A8EC
h1A8ED
h1A8EE
h1A8EF
G426
G7
h1A900
h1A901
h1A902
h1A903
・・・・・
h1A9EC
h1A9ED
h1A9EE
h1A9EF
G427
G6
h1AA00
h1AA01
h1AA02
h1AA03
・・・・・
h1AAEC
h1AAED
h1AAEE
h1AAEF
G428
G5
h1AB00
h1AB01
h1AB02
h1AB03
・・・・・
h1ABEC
h1ABED
h1ABEE
h1ABEF
G429
G4
h1AC00
h1AC01
h1AC02
h1AC03
・・・・・
h1ACEC
h1ACED
h1ACEE
h1ACEF
G430
G3
h1AD00
h1AD01
h1AD02
h1AD03
・・・・・
h1ADEC
h1ADED
h1ADEE
h1ADEF
G431
G2
h1AE00
h1AE01
h1AE02
h1AE03
・・・・・
h1AEEC
h1AEED
h1AEEE
h1AEEF
G432
G1
h1AF00
h1AF01
h1AF02
h1AF03
・・・・・
h1AFEC
h1AFED
h1AFEE
h1AFEF
Rev. 0.11 April 25, 2008, page 39 of 181
R61509V
Target Spec
Instruction
Outline
The R61509V adopts 18-bit bus architecture in order to interface to high-performance microcomputer in
high speed. The R61509V starts internal processing after storing control information (18, 16, 9, 8, 1 bit(s)),
sent from the microcomputer, in the instruction register (IR) and the data register (DR). Since the internal
operation of the R61509V is controlled by the signals sent from the microcomputer, the register selection
signal (RS), the read/write signal (R/W), and the internal 16-bit data bus signals (IB15 ~ IB0) are called
instructions. The following are the kinds of instruction of the R61509V.
1.
2.
3.
4.
Specify index
Display control
Power management control
Set internal GRAM addresssss
5.
6.
7.
8.
Transfer data to and from the internal GRAM
Window address control
γ-correction
Panel Display Control
Normally, the data write instructions (5) are used the most frequently. The internal GRAM address is
updated automatically as data is written to the internal GRAM, which, in combination with the window
address function, contributes to minimizing data transfer and thereby lessens the load on the microcomputer.
The R61509V writes instructions consecutively by executing the instruction within the cycle when it is
written (instruction execution time: 0 cycle).
Instruction Data Format
As the following figure shows, the data bus used to transfer 16 instruction bits (IB[15:0]) is different
according to the data format of a selected interface. Make sure to transfer the instruction bits according to
the format of the selected interface.
The bits to which no instruction is assigned must be set to either “0” or “1” according to the following
register tables. When changing only one instruction bit setting, the setting values in other bits in the
register must be written.
Rev. 0.11 April 25, 2008, page 40 of 181
R61509V
Target Spec
Index (IR)
R/W
RS
IB15
IB14
IB13
IB12
IB11
W
0
0
0
0
0
0
IB10
ID
[10]
IB9
ID
[9]
IB8
ID
[8]
IB7
ID
[7]
IB6
ID
[6]
IB5
ID
[5]
IB4
ID
[4]
IB3
ID
[3]
IB2
ID
[2]
IB1
ID
[1]
IB0
ID
[0]
The index register specifies the indexes of control register or RAM control to be accessed. It is prohibited
to access registers and instruction bits to which no index register is assigned.
Display control
Device code read (R000h)
R/W
R
RS
1
IB15
IB14
IB13
IB12
IB11
IB10
1
0
1
1
0
1
IB9
IB8
IB7
IB6
IB5
IB4
IB3
IB2
IB1
IB0
0
1
0
0
0
0
1
0
0
1
The device code “B509”H is read out when this register is read forcibly.
Driver Output Control (R001h)
R/W
RS
IB15
IB14
IB13
IB12
IB11
IB10
IB9
IB8
IB7
IB6
IB5
IB4
IB3
IB2
IB1
IB0
R/W
1
0
0
0
0
0
SM
0
SS
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Default value
SS: Sets the shift direction of output from the source driver.
When SS = “0”, the source driver output shift from S1 to S720.
When SS = “1”, the source driver output shift from S720 to S1.
The combination of SS and BGR settings determines the RGB assignment to the source driver pins S1 ~
S720.
When SS = “0” and BGR = “0”, RGB dots are assigned one to one from S1 to S720.
When SS = “1” and BGR = “1”, RGB dots are assigned one to one from S720 to S1.
When changing the SS and BGR bits, RAM data must be rewritten.
SM: Controls the scan mode in combination with GS setting. See “ Scan mode setting”.
Rev. 0.11 April 25, 2008, page 41 of 181
R61509V
Target Spec
LCD Drive Wave Control (R002h)
R/W
RS
IB15
IB14
IB13
IB12
IB11
IB10
IB9
IB8
IB7
IB6
IB5
IB4
IB3
IB2
IB1
IB0
R/W
1
0
0
0
0
0
0
0
BC
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
IB3
IB2
IB1
IB0
AM
0
0
0
0
0
0
0
Default value
BC: Selects the liquid crystal drive waveform VCOM.
BC = 0: frame inversion waveform is selected.
BC = 1: line inversion waveform is selected.
Entry Mode (R003h)
R/W
RS
R/W
1
Default value
IB15 IB14 IB13 IB12 IB11 IB10
IB9
IB8
IB7
IB6
TRI
DF
M
0
BGR
0
0
0
0
OR
G
0
0
0
0
0
0
0
0
0
0
0
IB5
IB4
ID
ID
[1]
[0]
1
1
The entry mode registers include instruction bits for setting how to write data from the microcomputer to
the internal GRAM of the R61509V.
AM: Sets either horizontal or vertical direction in updating the address counter automatically as the
R61509V writes data to the internal GRAM.
AM = “0”, sets the horizontal direction.
AM = “1”, sets the vertical direction.
When specifying window address area, the data is written only within the area in the direction determined
by ID and AM bits.
ID[1:0]: Either increments (+1) or decrements (-1) the address counter (AC) automatically as the data is
written to the GRAM. The ID[0] bit sets either increment or decrement in horizontal direction (updates the
address AD[7:0]). The ID[1] bit sets either increment or decrement in vertical direction (updates the
address AD[8:16]). The AM bit sets either horizontal or vertical direction in updating RAM address
counter automatically when writing data to the internal RAM.
ORG: Moves the origin address according to the ID setting when a window address area is described. This
function is enabled when executing burst data transfer within the window address area.
ORG = 0: The origin address is not moved. In this case, specify the address to start write
operation according to the GRAM address map within the window address area.
ORG = 1: The origin address “h00000” is moved according to the ID[1:0] setting.
Notes: 1. When ORG = 1, the origin address can be set only at “h00000”.
2. In RAM read operation, make sure to set ORG = 0.
Rev. 0.11 April 25, 2008, page 42 of 181
R61509V
Target Spec
BGR: Reverses the order from RGB to BGR in writing 18-bit pixel data in the GRAM.
BGR = 0:
BGR = 1:
Write data in the order of RGB to the GRAM.
Reverse the order from RGB to BGR in writing data to the GRAM.
DFM: In combination with the TRI setting, DFM sets the format to develop 16-/8-bit data to 18-bit data
when using either 16- or 8-bit bus interface. Make sure to set DFM = 0 when not transferring data via 16bit or 8-bit interface. Set DFM in accordance with selected interface and image data format in RAM write
operation.
DFM=0: 18bpp (R:G:B = 6:6:6), DFM=1: 16bpp (R:G:B = 5:6:5)
TRI: Selects the format to transfer data bits via 16-bit or 8-bit interface.
In 8-bit interface operation,
TRI = 0: 16-bit RAM data is transferred in two transfers.
TRI = 1: 18-bit RAM data is transferred in three transfers.
In 16-bit bus interface operation,
TRI = 0: 16-bit RAM data is transferred in one transfer.
TRI = 1: 18-bit RAM data is transferred in two transfers.
Make sure TRI = 0 when not transferring data via 16- or 8-bit interface. Also, set TRI = 0 during read
operation.
Rev. 0.11 April 25, 2008, page 43 of 181
R61509V
Target Spec
Automatic Address Update (ORG = 0, AM, ID)
ID1-0 = 00
Horizontal: Decrement
Vertical: Decrement
ORG = 0
AM = 0
Horizontal
17'h00000
ID1-0 = 01
Horizontal: Increment
Vertical: Decrement
17'h00000
17'h00000
17'hAFEF
Note:
17'h00000
17'h00000
17'hAFEF
17'hAFEF
ID1-0 = 11
Horizontal: Increment
Vertical: Increment
17'hAFEF
17'hAFEF
17'h00000
17'h00000
AM = 1
Vertical
ID1-0 = 10
Horizontal: Decrement
Vertical: Increment
17'hAFEF
17'h00000
17'hAFEF
17'hAFEF
When writing data within the window address area with ORG = 0,
any address within the window address area can be set as the starting point of data write operation.
Automatic Address Update (ORG = 1, AM, ID)
ORG = 1
AM = 0
Horizontal
ID1-0 = 00
Horizontal: Decrement
Vertical: Decrement
ID1-0 = 01
Horizontal: Increment
Vertical: Decrement
17'h00000
17'h00000
ID1-0 = 11
Horizontal: Increment
Vertical: Increment
17'h00000
17'h00000
S
17'hAFEF
17'hAFEF
17'hAFEF
17'h00000
17'h00000
S
17'hAFEF
17'h00000
17'h00000
S
S
S
17'hAFEF
17'hAFEF
Notes:
S
S
S
AM = 1
Vertical
ID1-0 = 10
Horizontal: Decrement
Vertical: Increment
17'hAFEF
17'hAFEF
1. When ORG = 1, the address to start data write operation within the window address area is set
at either corner of the window address area (the positions of the S in the circle in the above figure).
2. When ORG = 1, make sure to set the address h00000 in the RAM address set register.
Setting other addresses is prohibited.
Figure 4 Automatic Address Update
Rev. 0.11 April 25, 2008, page 44 of 181
R61509V
Target Spec
Display Control 1 (R007h)
R/W
RS
R/W
1
Default
IB15 IB14 IB13 IB12 IB11 IB10
PTD
0
0
0
0
0
E
0
0
0
0
0
0
IB9
0
0
IB8
BAS
EE
IB7
IB6
IB5
IB4
IB3
IB2
IB1
IB0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BASEE: Base image display enable bit.
BASEE = 0: No base image is displayed. The R61509V drives the LCD at non-lit display level or displays
partial images.
BASEE = 1: A base image is displayed.
PTDE: Partial display 1 enable bit.
PTDE=0: Partial display is turned off. Only a base image is displayed on the panel.
PTDE=1: Partial image is displayed. Set BASEE = 0 to turn off the base image.
Rev. 0.11 April 25, 2008, page 45 of 181
R61509V
Target Spec
Display Control 2 (R008h)
R/W
RS
R/W
1
IB15 IB14 IB13 IB12 IB11 IB10
FP
FP
FP
FP
FP
FP
[7]
[6]
[5]
[4]
[3]
[2]
Default
0
0
0
0
1
0
IB9
FP
[1]
IB8
FP
[0]
IB7
BP
[7]
IB6
BP
[6]
IB5
BP
[5]
IB4
BP
[4]
IB3
BP
[3]
IB2
BP
[2]
IB1
BP
[1]
IB0
BP
[0]
0
0
0
0
0
0
1
0
0
0
FP[7:0]: Sets the number of lines for front porch period (a blank period made after the end of display).
BP[7:0]: Sets the number of lines for back porch period (a blank period made before the beginning of
display).
In external display interface operation, a back porch (BP) period starts on the falling edge of the VSYNCX
signal and the display operation starts after the back porch period. After the front porch period, a blank
period continues until next VSYNCX input is detected.
Table 13
FP [7:0]
BP [7:0]
Number of front porch line
Number of back porch line
8’h00
Setting inhibited
Setting inhibited
8’h01
Setting inhibited
Setting inhibited
8’h02
Setting inhibited
2 lines
8’h03
3 lines
3 lines
8’h04
4 lines
4 lines
8’h05
5 lines
5 lines
8’h06
6 lines
6 lines
8’h07
7 lines
7 lines
8’h08
8 lines
8 lines
8’h09
9 lines
9 lines
8’h0A
10 lines
10 lines
8’h0B
11 lines
11 lines
8’h0C
12 lines
12 lines
8’h0D
13 lines
13 lines
8’h0E
14 lines
14 lines
8’h0F
15 lines
15 lines
：
：
：
8’h7F
127 lines
127 lines
8’h80
128 lines
128 lines
8’h81
Setting inhibited
Setting inhibited
：
：
：
8’hFF
Setting inhibited
Setting inhibited
Rev. 0.11 April 25, 2008, page 46 of 181
R61509V
Target Spec
VSYNCX
BP
Back porch
NL
Display Area
Front porch
FP
Note: The output timing to the panel is delayed by 2 line period
from the synchronous signal (VSYNCX) input.
Figure 5 Front and Back Porch Periods
Note on Setting BP and FP:
Set the BP and FP bits as follows in the following operation modes, respectively.
Table 14
BP ≥ 2 lines
FP ≥ 3 lines
FP + BP ≤ 256 lines
Rev. 0.11 April 25, 2008, page 47 of 181
R61509V
Target Spec
Display Control 3 (R009h)
R/W
RS
IB15 IB14 IB13 IB12 IB11 IB10
R/W
1
0
0
0
0
PTV
Default
0
0
0
0
0
IB9
IB8
IB7
IB6
IB5
IB4
IB3
IB2
IB1
IB0
PTS
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
PTS: Sets the source output level to drive non-display area. PTS also selects operation of grayscale
amplifier and step-up clock frequency.
Table 15
Source output in non-lit display area (Note)
PTS
Positive polarity
Negative polarity
Non-lit display area
Grayscale amplifier
in operation
Step-up clock frequency
0
V63
V0
V0 to V63
Register setting (DC0, DC1)
1
V63
V0
V0, V63
Register setting (DC0) x 1/2
Note: The power efficiency improved by halting grayscale amplifiers and slowing down the step-up clock
frequency can be obtained in non-display drive period.
PTV: Sets the VCOM output in non-lit display area. When PTV=1, frame inversion in non-lit display area
is selected.
Table 16
PTV
VCOM operation in non-lit display drive period
0
BC setting
1
Frame inversion
Rev. 0.11 April 25, 2008, page 48 of 181
R61509V
Target Spec
8 Color Control (R00Bh)
R/W
RS
IB15
IB14
IB13
IB12
IB11
IB10
IB9
IB8
IB7
IB6
IB5
IB4
IB3
IB2
IB1
IB0
W/R
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
COL
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Default value
COL: When COL = 1, the R61509V enters the eight-color display mode. RAM data rewrite operation is
not required when setting the eight-color display mode. Set the 8-color mode instruction according to the
8-color mode sequence.
The electrical potential of liquid crystal drive in 8-color display mode is V0/V63. Selecting frame inversion
is recommended to reduce power consumption.
Table 17
COL
Display Color
1’h0
262,144 colors
1’h 1
8 colors
Rev. 0.11 April 25, 2008, page 49 of 181
R61509V
Target Spec
External Display Interface Control 1 (R00Ch)
R/W RS
R/W
IB15 IB14 IB13 IB12 IB11 IB10 IB9
1
0
Default
0
ENC ENC ENC
[2]
[1]
[0]
0
0
0
IB8
IB7
IB6
0
0
0
RM
0
0
0
0
0
0
0
0
IB5
IB4
DM
DM
[1]
[0]
0
0
IB3
IB2
IB1
IB0
0
0
0
RIM
0
0
0
0
RIM: Sets the interface format when RGB interface is selected by RM and DM bits. Set RIM bit before
starting display operation via the external display interface. Do not change the setting while the R61509V
performs display operation.
Table 18
RIM
RGB interface operation
Color
0
18-bt RGB interface (1 transfer/pixel)
DB17-0
262,144
1
16-bit RGB interface (1 transfer / pixel)
DB17-13, 11-1
65536
Notes: 1: Instruction bits are set via system interface.
2: Transfer the RGB dot data one by one in synchronization with DOTCLK.
DM[1:0]: The DM[1:0] setting allows switching between internal clock operation mode and external
display interface operation mode. However, switching between the RGB interface operation and the
VSYNCX interface operation is prohibited.
Table 19 Display Interface
DM[1:0]
2’h0
Display Interface
Internal clock operations
2’h1
RGB interface
2’h2
VSYNC interface
2’h3
Setting inhibited
RM: Selects the interface for RAM access operation. RAM access is possible only via the interface
selected by the RM bit. Set RM = 1 when writing display data via RGB interface. When RM = 0, it is
possible to write data via system interface while performing display operation via RGB interface.
Table 20 RAM Access Interface
RM
RAM Access Interface
0
System interface/VSYNC interface
1
RGB interface
* Transfer instruction commands via clock synchronous serial interface.
Rev. 0.11 April 25, 2008, page 50 of 181
R61509V
Target Spec
ENC[2:0]: Sets the RAM write cycle via RGB interface.
Table 21
ENC[2:0]
RAM Write Cycle (frame periods)
3’h0
1 frame
3’h1
2 frames
3’h2
3 frames
3’h3
4 frames
3’h4
5 frames
3’h5
6 frames
3’h6
7 frames
3’h7
8 frames
Rev. 0.11 April 25, 2008, page 51 of 181
R61509V
Target Spec
External Display Interface Control 2 (R00Fh)
R/W
RS
IB15
IB14
IB13
IB12
IB11
IB10
IB9
IB8
IB7
IB6
IB5
R/W
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Default value
IB4
0
DPL: Sets the signal polarity of DOTCLK pin.
DPL = 0: input data on the rising edge of DOTCLK
DPL = 1: input data on the falling edge of DOTCLK
EPL: Sets the signal polarity of ENABLE pin.
EPL = 0: writes data DB17-0 when ENABLE = “0” and disables data write operation
when ENABLE = “1”.
EPL = 1: writes data DB17-0 when ENABLE = “1” and disables data write operation
when ENABLE = “0”.
HSPL: Sets the signal polarity of HSYNCX pin.
HSPL = 0: low active
HSPL = 1: high active
VSPL: Sets the signal polarity of VSYNCX pin.
VSPL = 0: low active
VSPL = 1: high active
Rev. 0.11 April 25, 2008, page 52 of 181
IB3
VSPL HSPL
0
IB2
IB1
IB0
0
EPL
DPL
0
0
0
R61509V
Target Spec
Panel Interface Control 1 (R010h)
R/W
RS
IB15 IB14 IB13 IB12 IB11 IB10
R/W
1
0
0
0
0
0
0
Default
0
0
0
0
0
0
IB9
DIV
I
[1]
0
IB8
DIV
I
[0]
0
IB7
IB6
IB5
IB4
IB3
IB2
IB1
IB0
0
0
0
RTNI
[4]
RTNI
[3]
RTNI
[2]
RTNI
[1]
RTNI
[0]
0
0
0
1
1
0
0
1
RTNI[4:0]: Sets 1H (line) period. This setting is valid when the R61509V’s display operation is
synchronized with internal clock signal.
Table 22 Clocks per Line (Internal Clock Operation)
RTNI[4:0]
Clocks per Line
RTNI[4:0]
Clocks per Line
5’h00-5’h0F Setting inhibited
5’h18
24 clocks
5’h10
16 clocks
5’h19
25 clocks
5’h11
17 clocks
5’h1A
26 clocks
5’h12
18 clocks
5’h1B
27 clocks
5’h13
19 clocks
5’h1C
28 clocks
5’h14
20 clocks
5’h1D
29 clocks
5’h15
21 clocks
5’h1E
30 clocks
5’h16
22 clocks
5’h1F
31 clocks
5’h17
23 clocks
Note: In Power Supply Instruction Setting, Deep Standby Exit Sequence and Sleep Mode Exit Sequence,
RTNI bit must be set at the “Initial instruction setting” state. See “Power Supply Setting Sequence”
and “Instruction Setting Sequence and Refresh Sequence”.
DIVI[1:0]: Sets the division ratio of the internal clock frequency. The R61509V’s internal operation is
synchronized with the frequency divided internal clock, which is set according to the division ratio
determined by DIVI[1:0] setting. The frame frequency can be changed by setting RTNI and DIVI bits.
When changing the number of lines to drive the LCD panel, adjust the frame frequency too. For details,
see Frame-Frequency Adjustment Function.
In RGB interface operation, the DIVI[1:0] setting has no effect.
Table 23 Division Ratio (Internal Operation)
DIVI[1:0]
Division Ratio
Internal Operation Clock Unit
2’h0
1/1
1 x OSC
2’h1
1/2
2 x OSC
2’h2
1/4
4 x OSC
2’h3
1/8
8 x OSC
Note: In Power Supply Instruction Setting, Deep Standby Exit Sequence and Sleep Mode Exit Sequence,
RTNI bit must be set at the “Initial instruction setting” state. See “Power Supply Setting Sequence”
and “Instruction Setting Sequence and Refresh Sequence”.
Rev. 0.11 April 25, 2008, page 53 of 181
R61509V
Target Spec
Frame Frequency Calculation
Frame frequency =
fosc
Clocks per line x division ratio x (line + BP + FP)
fosc : RC oscillation frequency
Line: Number of lines to drive the LCD (NL bits)
Division ratio: DIVI
Clocks per line: RTNI
Rev. 0.11 April 25, 2008, page 54 of 181
[Hz]
R61509V
Target Spec
Panel Interface Control 2 (R011h)
R/W
R/W
RS
IB15 IB14
IB13
IB12
IB11
1
0
0
0
0
0
Default
0
0
0
0
0
IB10
IB9
IB8
IB7
NOW NOW NOW
I[2]
I[1]
I[0]
0
0
1
IB6
IB5
IB4
IB3
0
0
0
0
0
0
0
0
0
0
IB2
IB1
NOWI[2:0]: Sets the non-overlap period of adjacent gate outputs. The setting is enabled when the
R61509V’s display operation is synchronized with internal clock signals.
Table 24
NOWI[2:0]
Non-overlap period
NOWI[2:0]
Non-overlap period
3'h0
0 (internal clock *see note)
3'h4
4 (internal clock *see note)
3'h1
1
3'h5
5
3'h2
2
3'h6
6
3'h3
Note:
3
3'h7
7
The internal clock is the frequency divided clock, which is set by DIVI[[1:0] bits.
SDTI[2:0]: Sets the source output delay period from the reference point. For the relationships between
gate interface signals, see Liquid Crystal Panel Interface Timing.
Table 25
SDTI[2:0]
Source output delay period
3’h0
0 clocks
3’h1
1 clock
3’h2
2 clocks
3’h3
3 clocks
3’h4
4 clocks
3’h5
5 clocks
3’h6
6 clocks
3’h7
7 clocks
Notes: 1. The number of clocks in the table setting is measured from the reference point.
2. 1 clock = (internal oscillation clock (OSC1) period) x (division ratio)
3. The reference point is the falling edge of gate output.
Rev. 0.11 April 25, 2008, page 55 of 181
IB0
SDTI SDTI SDTI
[2]
[1]
[0]
0
0
1
R61509V
Target Spec
Panel Interface Control 3 (R012h)
R/W
RS
R/W
1
Default value
IB15 IB14
IB12
IB11
0
0
IB13
0
0
0
0
0
0
0
0
IB10
IB9
IB8
VEQ VEQ VEQ
WI[2] WI[1] WI[0]
0
0
0
IB7
IB6
IB5
IB4
IB3
0
0
0
0
0
0
0
0
0
0
IB2
IB1
IB0
SEQ SEQ SEQ
WI[2] WI[1] WI[0]
0
0
VEQWI[2:0]: Sets VCOM equalize period. The VCOM equalize operation is executed from VCOM
alternating point defined by MCPI [2:0] for the period defined by VEQWI [2:0]. This function is disabled
when RGB interface is selected.
Table 26
VEQWI [2:0]
VCOM Equalize period
3’h0
0 clocks
3’h1
1 clock
3’h2
2 clocks
3’h3
3 clocks
3’h4
4 clocks
3’h5
5 clocks
3’h6
6 clocks
3’h7
7 clocks
Note: The clock is the frequency divided clock, which is set by DIVI[[1:0] bits.
㪭㪚㪦㪤㩷㫆㫌㫋㫇㫌㫋
㩷
1) VEQW [2:0]=0h
㪭㪜㪨㪮㪠㪲㪉㪑㪇㪴
㪭㪚㪦㪤㩷㫆㫌㫋㫇㫌㫋
㪭㪜㪨㪮㪠㪲㪉㪑㪇㪴
㪭㪚㪠㩷㫃㪼㫍㪼㫃㩷 㩷
㩷
㪞㪥㪛㩷㫃㪼㫍㪼㫃㩷
2) VEQWI [2:0] ≠0h
Figure 6
Rev. 0.11 April 25, 2008, page 56 of 181
0
R61509V
Target Spec
SEQWI[2:0]: Sets source equalize period. SEQWI setting is enabled only when the R61509V executes
display operation in synchronization with internal clock.
Table 27
SEQWI[2:0]
Source Equalize Period
3'h0
0 clocks
3'h1
1 clock
3'h2
2 clocks
3'h3
3 clocks
3'h4
4 clocks
3'h5
5 clocks
3'h6
6 clocks
3'h7
7 clocks
Note: The clock is the frequency divided clock, which is set by DIVI[[1:0] bits.
Rev. 0.11 April 25, 2008, page 57 of 181
R61509V
Target Spec
Panel Interface Control 4 (R013h)
R/W
RS
IB15 IB14 IB13 IB12 IB11 IB10
R/W
1
0
0
0
0
0
Default
0
0
0
0
0
IB9
IB8
IB7
IB6
IB5
IB4
IB3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
IB2
IB1
MC
MC
PI
PI[2]
[1]
0
0
IB0
MC
PI
[0]
1
MCPI: Defines VCOM alternating timing. This bit is enabled when displaying in synchronization with
internal clock. MCP cannot be used in RGB interface operation.
Table 28
MCPI [2:0]
VCOM alternating timing
3’h0
Setting inhibited
3’h1
1 clock
3’h2
2 clocks
3’h3
3 clocks
3’h4
4 clocks
3’h5
5 clocks
3’h6
6 clocks
3’h7
7 clocks
Note: The clock is the frequency divided clock, which is set by DIVI [1:0] bits.
Rev. 0.11 April 25, 2008, page 58 of 181
R61509V
Target Spec
Panel Interface Control 5 (R014h)
R/W
RS
IB15 IB14 IB13 IB12 IB11 IB10
R/W
1
0
0
0
0
0
Default
0
0
0
0
0
IB9
IB8
IB7
0
0
0
0
0
0
0
0
IB6
PC
DIV
H
[2]
1
IB5
PC
DIV
H
[1]
0
IB4
PC
DIV
H
[0]
1
IB3
0
0
IB2
PC
DIV
L
[2]
1
IB1
PC
DIV
L
[1]
0
IB0
PC
DIV
L
[0]
1
PCDIVH[2:0], PCDIVL[2:0]: When DM=1 and RGB I/F is selected, display operation is executed using
DOTCLKD. PCDIVH and PCDIVL define division ratio of DOTCLK to generate DOTCLKD.
PCDIVH is used to define number of DOTCLK in High period in units of one clock.
PCDIVL is used to define number of DOTCLK in Low period in units of one clock.
Make sure that PCDIVL=PCDIVH or PCDIVH-1.
Write PCDIVH and PCDIVL values so that DOTCLKD frequency is the closest to internal oscillation
clock frequency 678KHz.
For details, see “Setting Example of Display Control Clock in RGB Interface Operation”.
Table 29
PCDIVH[2:0]
Table 30
Number of DOTCLK
in High period
Number of DOTCLK
in Low period
PCDIVL[2:0]
3’h0
Setting inhibited
3’h0
Setting inhibited
3’h1
1 clock
3’h1
1 clock
3’h2
2 clocks
3’h2
2 clocks
3’h3
3 clocks
3’h3
3 clocks
3’h4
4 clocks
3’h4
4 clocks
3’h5
5 clocks
3’h5
5 clocks
3’h6
6 clocks
3’h6
6 clocks
3’h7
7 clocks
3’h7
7 clocks
Rev. 0.11 April 25, 2008, page 59 of 181
R61509V
Target Spec
Panel Interface Control 6 (R020h)
R/W
RS
IB15 IB14 IB13 IB12 IB11 IB10
R/W
1
0
0
0
0
0
0
Default
0
0
0
0
0
0
IB9
DIV
E[1]
0
IB8
DIV
E[0]
0
IB7
IB6
0
0]
0
0
IB5 IB4 IB3 IB2 IB1 IB0
RTN RTN RTN RTN RTN RTN
E[5] E[4] E[3] E[2] E[1] E[0]
0
1
1
0
0
1
DIVE[1:0]: Sets the division ratio of DOTCLK. The R61509V’s internal operation is synchronized with
the frequency-divided DOTCLK, the frequency of which is divided by the division ratio set by DIVE[1:0].
This setting is enabled while the R61509V’s display operation is synchronized with RGB interface signals.
Table 31 Division Ratio of DOTCLK (RGB interface operation)
DIVE[1:0]
Division ratio
2’h0
1/1
2’h1
1/2
2’h2
1/4
2’h3
1/8
Note: Clock frequency for internal operation = DOTCLK / (( DIVE x (PCDIVL + PCDIVH) ). For details, see
R014h.
Rev. 0.11 April 25, 2008, page 60 of 181
R61509V
Target Spec
RTNE[5:0]: Sets RTNE in combination with PCDIVH and PCDIVL to decide the number of DOTCLK in
1H (1 line) period according to the following formula. RTNE is enabled when RGB interface is selected.
DOTCLKD x RTNE (Number of clock) ≤ DOTCLK in 1H period.
Table 32 DOTCLKD in 1H period (RGB interface operation)
RTNE[5:0]
Clocks per
line period (1H)
RTNE[5:0]
Clocks per
line period (1H)
6'h00
Setting inhibited
6'h20
32 clocks
6'h01
Setting inhibited
6'h21
33 clocks
6'h02
Setting inhibited
6'h22
34 clocks
6'h03
Setting inhibited
6'h23
35 clocks
6'h04
Setting inhibited
6'h24
36 clocks
6'h05
Setting inhibited
6'h25
37 clocks
6'h06
Setting inhibited
6'h26
38 clocks
6'h07
Setting inhibited
6'h27
39 clocks
6'h08
Setting inhibited
6'h28
40 clocks
6'h09
Setting inhibited
6'h29
41 clocks
6'h0A
Setting inhibited
6'h2A
42 clocks
6'h0B
Setting inhibited
6'h2B
43 clocks
6'h0C
Setting inhibited
6'h2C
44 clocks
6'h0D
Setting inhibited
6'h2D
45 clocks
6'h0E
Setting inhibited
6'h2E
46 clocks
6'h0F
Setting inhibited
6'h2F
47 clocks
6'h10
16 clocks
6'h30
48 clocks
6'h11
17 clocks
6'h31
49 clocks
6'h12
18 clocks
6'h32
50 clocks
6'h13
19 clocks
6'h33
51 clocks
6'h14
20 clocks
6'h34
52 clocks
6'h15
21 clocks
6'h35
53 clocks
6'h16
22 clocks
6'h36
54 clocks
6'h17
23 clocks
6'h37
55 clocks
6'h18
24 clocks
6'h38
56 clocks
6'h19
25 clocks
6'h39
57 clocks
6'h1A
26 clocks
6'h3A
58 clocks
6'h1B
27 clocks
6'h3B
59 clocks
6'h1C
28 clocks
6'h3C
60 clocks
6'h1D
29 clocks
6'h3D
61 clocks
6'h1E
30 clocks
6'h3E
62 clocks
6'h1F
31 clocks
6'h3F
63 clocks
Rev. 0.11 April 25, 2008, page 61 of 181
R61509V
Target Spec
Panel Interface Control 7 (R021h)
R/W
RS
R/W
1
Default
IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7
NOW NOW NOW
0
0
0
0
0
0
E[2] E[1] E[0]
0
0
0
0
0
0
0
1
0
IB6
IB5
IB4
IB3
0
0
0
0
0
0
0
0
IB2 IB1 IB0
SDTE SDTE SDTE
[2]
[1]
[0]
0
0
1
NOWE[2:0]: Sets the non-overlap period of adjacent gate outputs. NOWE is enabled when RGB interface
is selected.
Table 33
NOWE[2:0] Non-overlap period
3’h0
0 clocks
3’h1
1 clock
3’h2
2 clocks
3’h3
3 clocks
3’h4
4 clocks
3’h5
5 clocks
3’h6
6 clocks
3’h7
Note:
7 clocks
1 clock = (number of data transfer/pixel) x DIVE (division ratio) x (PCDIVL + PCDIVH) [DOTCLK]
SDTE[2:0]: Sets the source output delay period from the reference point when the R61509V’s display
operation is synchronized with DOTCLK (DM = 2’h1). For the relationships between signals, see Liquid
Crystal Panel Interface Timing.
Table 34
SDTE[2:0]
Source output delay period
3’h0
0 clocks
3’h1
1 clock
3’h2
2 clocks
3’h3
3 clocks
3’h4
4 clocks
3’h5
5 clocks
3’h6
6 clocks
3’h7
7 clocks
Notes: 1. The number of clocks in the table setting is measured from the reference point.
2. 1 clock = DOTCLKD (when pixel data is transferred in one- transfer)
3. The reference point is falling edge of gate control signals.
Rev. 0.11 April 25, 2008, page 62 of 181
R61509V
Target Spec
Panel Interface Control 8 (R022h)
R/W
RS
R/W
1
Default
IB15 IB14 IB13 IB12 IB11 IB10
0
0
0
0
0
0
0
0
IB9
IB8
IB7
IB6
IB5
IB4
IB3
0
0
0
0
0
VEQ VEQ VEQ
WE WE WE
0
0
[2]
[1]
[0]
0
0
0
0
0
0
0
0
IB2
IB1
IB0
SEQ SEQ SEQ
WE WE WE
[2]
[1]
[0]
0
0
0
VEQWE[2:0]: Sets low power VCOM drive period. The setting is enabled when RGB interface is
selected.
Table 35
VEQWE[2:0]
Source output delay period
VEQWE[2:0]
Source output delay period
3’h0
0 clocks (*see Notes)
3’h1
1 clock
3’h5
5 clocks
3’h2
2 clocks
3’h6
6 clocks
3’h4
4 clocks
3’h3
3 clocks
3’h7
7 clocks
Notes: 1. 1 clock = (Number of data transfer/pixel) x DIVE (division ratio) x (PCDIVL + PCDIVH)) [DOTCLK]
2. The number of clocks is measured from the reference point. The reference point is the
alternating position of VCOM, which is set by SDTE bits.
㪭㪚㪦㪤㩷㫆㫌㫋㫇㫌㫋
㩷
1) VEQW [2:0]=0h
㪭㪜㪨㪮㪠㪲㪉㪑㪇㪴
㪭㪚㪦㪤㩷㫆㫌㫋㫇㫌㫋
㪭㪜㪨㪮㪠㪲㪉㪑㪇㪴
㪭㪚㪠㩷㫃㪼㫍㪼㫃㩷 㩷
㩷
㪞㪥㪛㩷㫃㪼㫍㪼㫃㩷
2) VEQWI [2:0] ≠0h
Figure 7
Rev. 0.11 April 25, 2008, page 63 of 181
R61509V
Target Spec
SEQWE[2:0]: Sets source equalize period. SEQWE setting is enabled when the R61509V executes
display operation via RGB interface.
Table 36
SEQWE[2:0]
Source Equalize Period
3'h0
0 clocks
3'h1
1 clock
3'h2
2 clocks
3'h3
3 clocks
3'h4
4 clocks
3'h5
5 clocks
3'h6
6 clocks
3'h7
7 clocks
Note: 1 clock = (number of data transfer/pixel) x DIVE(Division ratio) x (PCDIVL + PCDIVH))
Rev. 0.11 April 25, 2008, page 64 of 181
[DOTCLK]
R61509V
Target Spec
Panel Interface Control 9 (R023h)
R/W
RS
IB15 IB14 IB13 IB12 IB11 IB10
R/W
1
0
0
0
0
0
Default
0
0
0
0
0
IB9
IB8
IB7
IB6
IB5
IB4
IB3
IB2
IB1
IB0
0
0
0
0
0
0
0
0
MC
PE
[2]
MC
PE
[1]
MC
PE
[0]
0
0
0
0
0
0
0
0
0
0
1
MCPE [2:0]: Specifies VCOM alternating point. MCPE is enabled when RGB interface is selected.
Table 37
MCPE [2:0]
VCOM alternating point
3’h0
Setting inhibited
3’h1
1 clock
3’h2
2 clocks
3’h3
3 clocks
3’h4
4 clocks
3’h5
5 clocks
3’h6
6 clocks
3’h7
7 clocks
Note: 1 clock = (number of data transfer/pixel) x DIVE(Division ratio) x (PCDIVL + PCDIVH))
Rev. 0.11 April 25, 2008, page 65 of 181
[DOTCLK]
R61509V
Target Spec
Frame Marker Control (R090h)
R/W
RS
R/W
1
IB15 IB14 IB13 IB12 IB11 IB10
Default
FM
KM
FMI
FMI
FMI
[2]
[1]
[0]
0
0
0
0
IB9
0
0
0
0
0
0
IB8
IB7
IB6
IB5
IB4
IB3
IB2
IB1
IB0
FMP FMP FMP FMP FMP FMP FMP FMP FMP
[8]
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
0
0
0
0
0
0
0
0
0
FMI[2:0]: Sets FMARK output interval by FMI register setting according to the update period of display
data and transfer rate. Set FMKM = 1 if FMARK signal is output from FMARK pin. See “FMARK
Interface” for detail.
Table 38
FMI[2]
FMI[1]
FMI[0]
Output interval
0
0
0
1 frame
0
0
1
2 frames
0
1
1
4 frames
1
0
1
Other settings
6 frames
Setting inhibited
FMP[8:0]: Sets the output position of frame synchronous signal (frame marker). A pulse (FMARK) is
output by starting from back porch during a 1H period when FMP[8:0] = 9’h000 (high active, amplitude:
IOVCC1-GND). FMP[8:0] is used as a trigger signal for write operation in synchronization with frame.
Setting range: 9’h000 ≤ FMP ≤ BP + NL + FP
For details, see “FMARK Interface”.
Table 39
FMP[8:0]
FMARK output position
9’h000
0
9’h001
1
9’h002
2
：
9’h1BE
446
9’h1BF
447
9’h1C0 ~ 9’h1FF
Setting inhibited
Rev. 0.11 April 25, 2008, page 66 of 181
R61509V
Target Spec
Power Control
Power Control 1 (R100h)
R/W
R/W
RS
IB15 IB14 IB13 IB12 IB11 IB10
1
0
0
0
0
0
Default
0
0
0
0
0
IB9
IB8
BT
BT
BT
[2]
[1]
[0]
0
1
1
IB7
IB6
0
0
0
0
IB5
IB4
AP
AP
[1]
[0]
1
1
IB3
IB2
IB1
IB0
0
DST
B
0
0
0
0
0
0
DSTB: When DSTB = 1, the R61509V enters the shut down mode. In shut down mode, the internal logic
power supply is turned off to reduce power consumption. The GRAM data and instruction setting are not
maintained when the R61509V is in the shut down mode. Set the instruction again after the shut down
mode is exited. GND level is outputted to the panel in the shut down mode.
AP[1:0]: Adjusts the constant current in the operational amplifier circuit in the LCD power supply circuit.
The larger constant current, the better the drivability of the LCD, but it also increases the current
consumption. Adjust the constant current taking the trade-off between the display quality and the current
consumption into account. In no-display period, set AP[1:0]=2’h0 to halt operational amplifiers and stepup circuits to reduce power consumption.
Table 40 Constant Current in Operational Amplifiers
AP[1:0]
Electricity in LCD drive power supply amplifiers
2’h0
Operational amplifiers and step-up circuits halt
2’h1
0.5
2’h2
0.75
2’h3
1
Note: The values in the table represent the ratios of currents in respective settings to the current when
AP[1:0]=2’h3.
Rev. 0.11 April 25, 2008, page 67 of 181
R61509V
Target Spec
BT[2:0]: Sets the factor used in the step-up circuits. Select the optimal step-up factor for the operating
voltage. To reduce power consumption, set a smaller factor.
Table 41 Step-Up Factor for Step-Up Circuits
BT[2:0]
DDVDH
VCL
3’h0
Setting inhibited
VGH
3’h1
3’h2
VCI1 x2
[x 2]
-VCI1
[x –1]
DDVDH x 3
[x 6]
3’h3
3’h4
-(VCI1+DDVDH x 2)
[x –5]
-(DDVDH x 2)
[x –4]
-(VCI1+DDVDH)
[x –3]
Setting inhibited
3’h5
3’h6
VGL
VCI1 x2
[x 2]
-VCI1
[x –1]
VCI1+DDVDH
x2
[x 5]
3’h7
-(VCI1+DDVDH x 2)
[x –5]
-(DDVDH x 2)
[x –4]
-(VCI1+DDVDH)
[x –3]
Notes: 1. The factors in the brackets show the step-up factors from VCI1.
2. Make sure DDVDH=max.6.0V, VGH=max.18.0V, VGL=max -13.5V, VGH-VGL=max. 28.0V, and
VCL=max -3.0V.
Rev. 0.11 April 25, 2008, page 68 of 181
R61509V
Target Spec
Power Control 2 (R101h)
R/W
RS
IB15 IB14 IB13 IB12 IB11 IB10
R/W
1
0
0
0
0
0
Default
0
0
0
0
0
IB9
IB8
DC1 DC1 DC1
[2]
[1]
[0]
0
1
0
IB7
0
0
IB6
IB5
IB4
DC0 DC0 DC0
[2]
[1]
[0]
1
0
0
IB3
IB2
IB1
IB0
0
VC
[2]
VC
[1]
VC
[0]
0
1
1
1
DC1 [2:0]: Sets step-up clock frequency for Step-up Circuit 2. The step-up clock is in synchronization
with internal clock.
Table 42 Step-up Frequency (Step-up Circuit 1)
DC1[2:0]
Step-up Circuit 2
Step-up frequency (fDCDC2)
3’h0
Step-up Circuit 2 halts
3’h1
Setting inhibited
3’h2
Line frequency / 4
3’h3
Line frequency / 8
3’h4
Line frequency / 16
3’h5
Setting inhibited
3’h6
Setting inhibited
3’h7
Setting inhibited
[Step-up clock frequency for Step-up Circuit 2]
Line frequency
2(N)
Internal clock frequency fOSC
Step-up clock frequency (fDCDC2) =
[Hz]
[Hz]
=
Number of clock per line x Division ratio x 2(N)
fosc
:
Number of clock per line :
Internal clock frequency
RTN*[4:0]
(RTNI or RTNE)
Division ratio
: DIV*[1:0] (DIVI or DIVE)
N
: DC1 [2:0]
Rev. 0.11 April 25, 2008, page 69 of 181
R61509V
Target Spec
DC0 [2:0]: Sets step-up clock frequency for Step-up Circuit 1. The step-up clock is in synchronization
with internal clock.
Table 43 Step-up Frequency (Step-up Circuit 2)
DC0[2:0]
Step-up Circuit 1
Step-up frequency (fDCDC1)
3’h0
Step-up circuit 1 halts
3’h1
Setting inhibited
3’h2
Setting inhibited
3’h3
Setting inhibited
3’h4
FOSC / 8
3’h5
FOSC / 16
3’h6
FOSC / 32
3’h7
Setting inhibited
Note 1: Make sure that fDCDC1 ≥ fDCDC2.
Note 2: Set DC0 and RTN* so that ((DCDC1 step-up frequency) ≤ (Line frequency). If not, step-up operation
may not be completed satisfactory.
[Step-up clock frequency for Step-up Circuit 1]
Step-up clock frequency (fDCDC1) =
Line frequency
2(N-1)
Internal clock frequency fOSC
[Hz]
[Hz]
=
Number of clock per line x Division ratio x 2(N-1)
fosc
Division ratio
N
: Internal clock frequency
: DIV*[1:0] ((DIVI or DIVE)
: DC1 [2:0]
The step-up frequencies synchronize with display operation. Clock count is reset at the beginning of 1H
period.
Rev. 0.11 April 25, 2008, page 70 of 181
R61509V
Target Spec
VC[2:0]: Sets VCI voltage level.
VC[2:0]
VCI1 voltage (Reference voltage for step-up operation)
3’h0
Setting inhibited
3’h1
0.94 x VCILVL
3’h2
0.89 x VCILVL
3’h3
Setting inhibited
3’h4
Setting inhibited
3’h5
0.76 x VCILVL
3’h6
Setting inhibited
3’h7
1.00 x VCILVL
Rev. 0.11 April 25, 2008, page 71 of 181
■DC0ｘ Value and DCDC1 Step-up Clock Signal Waveform Example
DCDC1 performs charge operation and boost operation with the step-up clock generated from the timing generator.
The DCDC1 step-up clock frequency is adjusted by setting the division ratio of the reference clock frequency with DC0x register.
(To prevent flickering, the DCDC1 step-up clock signal is synchronized with the reference point of display operation in unit of lines.)
Note: Set DC0x and RTNx so that (DCDC1 step-up clock frequency) ≧ (line clock frequency)
If the above restriction is not followed, the duty cycle during the boost period is less than 50%. As a result, the step-up circuit may not operate normally.
Example) DIVn=2'h0, RTN＝5'h19 (reference clock period = 1/1 of internal operation clock, 1H period = 25 clocks)
Reference point
Reference point
1H period
Reference clock
Reference clock counter
5'h10 5'h00 5'h01 5'h02 5'h03 5'h04 5'h05 5'h06 5'h07 5'h08 5'h09 5'h0A 5'h0B 5'h0C 5'h0D 5'h0E 5'h0F 5'h10 5'h11 5'h12 5'h13 5'h14 5'h15 5'h16 5'h17 5'h18 5'h00 5'h01 5'h02 5'h03 5'h04 5'h05 5'h06 5'h07 5'h08
Synchronized with the reference point in unit of lines
Synchronized with the reference point in unit of lines
a) DC0x=3'h4
8 clock cycles
(1/8 of reference clock frequency)
8 clock cycles
8 clock cycles
DCDC1 step-up clock
b) DC0x=3'h5
16 clock cycles
(1/16 of reference clock frequency)
DCDC1 step-up clock
c) DC0x=3'h6
32 clock cycles (As the number of clocks per 1H period is less than 32, the duty cycle of the step-up clock is not 50%.
(1/32 of reference clock frequency)
DCDC1 step-up clock
Note: The duty cycle of the step-up clock should be close to 50%.
■DC1ｘ Value and DCDC2 Step-up Clock Signal Waveform Example
DCDC2 performs charge operation and boost operation with the step-up clock generated from the timing generator.
The DCDC2 step-up clock frequency is adjusted by setting the division ratio of the reference clock frequency with DC1x register.
(To prevent flicker, the DCDC2 step-up clock signal is synchronized with the head of BP period in unit of lines.)
Example) BP=FP=8'h08, NL=7'h6B (front porch = back porch 8 lines, the number of lines to drive the LCD = 432 lines)
Reference Reference Reference Reference Reference Reference Reference Reference Reference Reference Reference Reference Reference Reference Reference Reference Reference Reference Reference Reference Reference Reference Reference Reference Reference Reference Reference Reference
point
point
point
point
point
point
point
point
point
point
point
point
point
point
point
point
point
point
point
point
point
point
point
point
point
point
point
point
1H period 1H period 1H period
Reference clock
Line clock
Counter for the number of lines
'h1BE 'h1BF 'h000 'h001 'h002 'h003 'h004 'h005 'h006 'h007 'h008 'h009 'h00A 'h00B 'h00C 'h00D 'h00E 'h00F 'h010 'h011 'h012 'h013 'h014 'h015 'h016 'h017 'h018 'h019
Front Porch
Back Porch
Display Area
Synchronized with the head of BP period
a) DC1x=3'h2
(1/4 of line clock frequency)
4H cycles
4H cycles
4H cycles
4H cycles
DCDC2 step-up clock
b) DC1x=3'h3
(1/8 of line clock frequency)
8H cycles
8H cycles
DCDC2 step-up clock
c) DC0x=3'h4
(1/16 of line clock frequency)
DCDC2 step-up clock
16H cycles
R61509V
Target Spec
Power Control3 (R102h)
R/W
RS
R/W
1
Default
IB15 IB14 IB13 IB12 IB11 IB10
VRH VRH VRH VRH VRH
0
[4]
[3]
[2]
[1]
[0]
R/W R/W R/W R/W R/W
0
0
0
0
0
0
IB9
0
0
IB8 IB7
VCM
1
R
R/W R/W
1
1
IB6
0
0
IB5
IB4
PSON PON
W
W
0
0
IB3
IB2
IB1
IB0
0
0
0
0
0
0
0
0
Note: True values of PSON and PON are not read when instruction read is executed.
PON, PSON: Turn power supply ON. PON and PSON must be written to power supply ON and start the
internal power supply operation. Follow power supply sequencer to set PON and PSON bits.
VCMR: Selects either external resistance (VCOMR pin) or internal electronic volume (VCM[4:0]) to set
the electrical potential of VCOMH. The internal electronic volume is set by VCM bits
Table 44
VCMR0[0]
VCOMH Electrical Potential setting
0
VCOMR (externally supplied)
1
Internal electronic volume
VRH[3:0]: Sets the factor to generate VREG1OUT.
Table 45
VRH[4:0]
VREG1OUT
5’h00
Halt (Hiz)
5’h01-5’h0F
Setting inhibited
5’h10
VCIR x 1.600
5’h11
VCIR x 1.625
5’h12
VCIR x 1.650
5’h13
VCIR x 1.675
5’h14
VCIR x 1.700
5’h15
VCIR x 1.725
5’h16
VCIR x 1.750
5’h17
VCIR x 1.775
5’h18
VCIR x 1.800
5’h19
VCIR x 1.825
5’h1A
VCIR x 1.850
5’h1B
VCIR x 1.875
5’h1C
VCIR x 1.900
5’h1D
VCIR x 1.925
5’h1E
VCIR x 1.950
5’h1F
VCIR x 1.975
Rev. 0.11 April 25, 2008, page 73 of 181
Note: Write VC and VRH bits so that VREG1OUT ≤ DDVDH0.5V.
R61509V
Target Spec
Power Control 4 (R103h)
R/W
R/W
RS
IB15 IB14 IB13 IB12 IB11 IB10
1
0
0
0
Default
0
0
0
IB9
IB8
VDV
VDV
VDV
VDV
VDV
[4]
[3]
[2]
[1]
[0]
0
0
0
0
0
IB7
IB6
IB5
IB4
IB3
IB2
IB1
IB0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VDV[4:0]: Selects the factor of VREG1OUT to set the amplitude of VCOM alternating voltage from 0.70
to 1.32.
Table 46
VDV[4:0]
VCOM amplitude
VDV[4:0]
VCOM amplitude
5’h0
VREG1OUT x 0.70
5’h10
VREG1OUT x 1.02
5’h1
VREG1OUT x 0.72
5’h11
VREG1OUT x 1.04
5’h2
VREG1OUT x 0.74
5’h12
VREG1OUT x 1.06
5’h3
VREG1OUT x 0.76
5’h13
VREG1OUT x 1.08
5’h4
VREG1OUT x 0.78
5’h14
VREG1OUT x 1.10
5’h5
VREG1OUT x 0.80
5’h15
VREG1OUT x 1.12
5’h6
VREG1OUT x 0.82
5’h16
VREG1OUT x 1.14
5’h7
VREG1OUT x 0.84
5’h17
VREG1OUT x 1.16
5’h8
VREG1OUT x 0.86
5’h18
VREG1OUT x 1.18
5’h9
VREG1OUT x 0.88
5’h19
VREG1OUT x 1.20
5’hA
VREG1OUT x 0.90
5’h1A
VREG1OUT x 1.22
5’hB
VREG1OUT x 0.92
5’h1B
VREG1OUT x 1.24
5’hC
VREG1OUT x 0.94
5’h1C
VREG1OUT x 1.26
5’hD
VREG1OUT x 0.96
5’h1D
VREG1OUT x 1.28
5’hE
VREG1OUT x 0.98
5’h1E
VREG1OUT x 1.30
5’hF
VREG1OUT x 1.00
5’h1F
VREG1OUT x 1.32
Note 1:
Note 2:
Set VDV[4:0] so that VCOM amplitude becomes 6.0V or less.
Set VCOML (VCOMH-VCOM amplitude) ≤ 0V.
Rev. 0.11 April 25, 2008, page 74 of 181
R61509V
Target Spec
RAM Access
RAM Address Set (Horizontal Address) (R200h)
RAM Address Set (Vertical Address) (R201h)
R/W
R
200
R
201
R/W
RS
IB15 IB14 IB13 IB12 IB11 IB10
IB9
IB8
IB7
IB6
IB5
IB4
IB3
IB2
IB1
IB0
AD
AD
AD
AD
AD
AD
AD
AD
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
1
0
0
0
0
0
0
0
0
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
AD
AD
AD
AD
AD
AD
AD
AD
AD
[16]
[15]
[14]
[13]
[12]
[11]
[10]
[9]
[8]
0
0
0
0
0
0
0
0
0
R/W
1
0
0
0
0
0
0
0
Default
0
0
0
0
0
0
0
AD[16:0]: Sets a GRAM address in the AC (Address Counter) which is automatically updated according to
the combination of AM, ID[1:0] settings as the R61509V writes data to the internal GRAM. Data can be
written consecutively without resetting the address in the AC. The address is not automatically updated
after reading data from the internal GRAM.
Note 1: In RGB interface operation (RM = “1”), the address AD16-0 is set in the address counter every
frame on the falling edge of VSYNCX.
Note 2: In internal clock operation and VSYNC interface operation (RM = “0”), the address AD16-0 is set
when executing the instruction.
Table 47 GRAM Address setting range
AD[16:0]
GRAM Data Setting
17’h00000 – 17’h000EF
Bitmap data on the first line
17’h00100 – 17’h001EF
Bitmap data on the second line
17’h00200 – 17’h002EF
Bitmap data on the third line
17’h00300 – 17’h003EF
Bitmap data on the fourth line
17’h00400 – 17’h004EF
Bitmap data on the fifth line
:
:
17’h1AC00 – 17’h1ACEF
Bitmap data on the 429th line
17’h1AD00 – 17’h1ADEF
Bitmap data on the 430th line
17’h1AE00 – 17’h1AEEF
Bitmap data on the 431st line
17’h1AF00 – 17’h1AFEF
Bitmap data on the 432
Rev. 0.11 April 25, 2008, page 75 of 181
nd
line
R61509V
Target Spec
GRAM Data Write (R202h)
R/W
RS
W
1
RAM write data WD[17:0] is transferred via different data bus in different interface operation.
RGB
interface
RAM write data WD[17:0] is transferred via different data bus in different interface operation.
WD[17:0]: The R61509V develops data into 18 bits internally in write operation. The format to develop
data into 18 bits is different in different interface operation.
The GRAM data represents the grayscale level. The R61509V automatically updates the address according
to AM and ID[1:0] settings as it writes data in the GRAM. The DFM bit sets the format to develop 16-bit
data into the 18-bit data in 16-bit or 8-bit interface operation.
Note: When writing data in the GRAM via system interface while using the RGB interface, make sure
that write operations via two interfaces that do not conflict one another.
Rev. 0.11 April 25, 2008, page 76 of 181
R61509V
Target Spec
GRAM Data Read (R202h)
R/W
RS
R
1
RAM read data RD[17:0] is transferred via different data bus in different interface operation.
RD[17:0]: 18-bit data read from the GRAM. RAM read data RD[17:0] is transferred via different data bus
in different interface operation.
When the R61509V reads data from the GRAM to the microcomputer, the first word read immediately
after RAM address set is not outputted. Therefore, data on the data bus is invalid. Valid data is sent to the
data bus when the R61509V reads out the second and subsequent words.
When either 8-bit or 16-bit interface is selected, the LSBs of R and B dot data are not read out.
Note: This register is disabled in RGB interface operation
Set ID, AM,
HSA, HEA, VSA, and VEA bits
Set address N
First word
Second word
Dummy read (invalid data to DB17-0)
From GRAM to read data latch
Read (data of address N)
From read data latch to DB17-0
Set address M
First word
Dummy read (invalid data to DB17-0)
From GRAM to read data latch
Second word
Read (data of address M)
From read data latch to DB17-0
Read out data to the microcomputer
Figure 8 GRAM Read Sequence
Rev. 0.11 April 25, 2008, page 77 of 181
R61509V
Target Spec
NVM Data Read / NVM Data Write (R280h)
R
280h
R/W
RS
IB15 IB14 IB13 IB12 IB11 IB10
R/W
1
1
VC
M
[6]
VC
M
[5]
VC
M
[4]
VC
M
[3]
Default
1
1
1
1
1
IB9
IB8
IB7
IB6
IB5
IB4
IB3
IB2
IB1
IB0
VC
M
[2]
VC
M
[1]
VC
M
[0]
UID
UID
UID
UID
UID
UID
UID
UID
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
1
1
1
1
1
1
1
1
1
1
1
UID[3:0]: Used to temporarily store NVM data such as used identification code.
The write data is loaded to NVM data write register (NVDAT [7:0]) and then is written to NVM.
NVM data is loaded to UID[7:0] when power on reset, when shutdown mode is exited or when CALB=1 is
written. When NVM data write is not executed, UID[7:0] = 8’hFF (Default).
VCM[6:0]: Used to control VCOMH.
To use NVM data to adjust VCOMH, specify the VCOMH level using VCM [6:0], write the same value to
the NVM data write register NVDAT [14:8] (R6F1h) and then write the data to NVM.
NVM data is loaded to VCM[6:0] when power on reset, when shutdown mode is exited or when CALB=1
is written. When NVM data write is not executed, VCM[6:0]= 7’h7F (Default).
Rev. 0.11 April 25, 2008, page 78 of 181
R61509V
Target Spec
Table 48
VCM [6:0]
VCOMH voltage
VCM [6:0]
VCOMH voltage
7’h00
VREG1OUT x 0.492
7’h40
VREG1OUT x 0.748
7’h01
VREG1OUT x 0.496
7’h41
VREG1OUT x 0.752
7’h02
VREG1OUT x 0.500
7’h42
VREG1OUT x 0.756
7’h03
VREG1OUT x 0.504
7’h43
VREG1OUT x 0.760
7’h04
VREG1OUT x 0.508
7’h44
VREG1OUT x 0.764
7’h05
VREG1OUT x 0.512
7’h45
VREG1OUT x 0.768
7’h06
VREG1OUT x 0.516
7’h46
VREG1OUT x 0.772
7’h07
VREG1OUT x 0.520
7’h47
VREG1OUT x 0.776
7’h08
VREG1OUT x 0.524
7’h48
VREG1OUT x 0.780
7’h09
VREG1OUT x 0.528
7’h49
VREG1OUT x 0.784
7’h0A
VREG1OUT x 0.532
7’h4A
VREG1OUT x 0.788
7’h0B
VREG1OUT x 0.536
7’h4B
VREG1OUT x 0.792
7’h0C
VREG1OUT x 0.540
7’h4C
VREG1OUT x 0.796
7’h0D
VREG1OUT x 0.544
7’h4D
VREG1OUT x 0.800
7’h0E
VREG1OUT x 0.548
7’h4E
VREG1OUT x 0.804
7’h0F
VREG1OUT x 0.552
7’h4F
VREG1OUT x 0.808
7’h10
VREG1OUT x 0.556
7’h50
VREG1OUT x 0.812
7’h11
VREG1OUT x 0.560
7’h51
VREG1OUT x 0.816
7’h12
VREG1OUT x 0.564
7’h52
VREG1OUT x 0.820
7’h13
VREG1OUT x 0.568
7’h53
VREG1OUT x 0.824
7’h14
VREG1OUT x 0.572
7’h54
VREG1OUT x 0.828
7’h15
VREG1OUT x 0.576
7’h55
VREG1OUT x 0.832
7’h16
VREG1OUT x 0.580
7’h56
VREG1OUT x 0.836
7’h17
VREG1OUT x 0.584
7’h57
VREG1OUT x 0.840
7’h18
VREG1OUT x 0.588
7’h58
VREG1OUT x 0.844
7’h19
VREG1OUT x 0.592
7’h59
VREG1OUT x 0.848
7’h1A
VREG1OUT x 0.596
7’h5A
VREG1OUT x 0.852
7’h1B
VREG1OUT x 0.600
7’h5B
VREG1OUT x 0.856
7’h1C
VREG1OUT x 0.604
7’h5C
VREG1OUT x 0.860
7’h1D
VREG1OUT x 0.608
7’h5D
VREG1OUT x 0.864
7’h1E
VREG1OUT x 0.612
7’h5E
VREG1OUT x 0.868
7’h1F
VREG1OUT x 0.616
7’h5F
VREG1OUT x 0.872
7’h20
VREG1OUT x 0.620
7’h60
VREG1OUT x 0.876
7’h21
VREG1OUT x 0.624
7’h61
VREG1OUT x 0.880
7’h22
VREG1OUT x 0.628
7’h62
VREG1OUT x 0.884
7’h23
VREG1OUT x 0.632
7’h63
VREG1OUT x 0.888
7’h24
VREG1OUT x 0.636
7’h64
VREG1OUT x 0.892
7’h25
VREG1OUT x 0.640
7’h65
VREG1OUT x 0.896
7’h26
VREG1OUT x 0.644
7’h66
VREG1OUT x 0.900
7’h27
VREG1OUT x 0.648
7’h67
VREG1OUT x 0.904
7’h28
VREG1OUT x 0.652
7’h68
VREG1OUT x 0.908
7’h29
VREG1OUT x 0.656
7’h69
VREG1OUT x 0.912
7’h2A
VREG1OUT x 0.660
7’h6A
VREG1OUT x 0.916
7’h2B
VREG1OUT x 0.664
7’h6B
VREG1OUT x 0.920
7’h2C
VREG1OUT x 0.668
7’h6C
VREG1OUT x 0.924
7’h2D
VREG1OUT x 0.672
7’h6D
VREG1OUT x 0.928
7’h2E
VREG1OUT x 0.676
7’h6E
VREG1OUT x 0.932
7’h2F
VREG1OUT x 0.680
7’h6F
VREG1OUT x 0.936
7’h30
VREG1OUT x 0.684
7’h70
VREG1OUT x 0.940
7’h31
VREG1OUT x 0.688
7’h71
VREG1OUT x 0.944
7’h32
VREG1OUT x 0.692
7’h72
VREG1OUT x 0.948
7’h33
VREG1OUT x 0.696
7’h73
VREG1OUT x 0.952
7’h34
VREG1OUT x 0.700
7’h74
VREG1OUT x 0.956
7’h35
VREG1OUT x 0.704
7’h75
VREG1OUT x 0.960
7’h36
VREG1OUT x 0.708
7’h76
VREG1OUT x 0.964
7’h37
VREG1OUT x 0.712
7’h77
VREG1OUT x 0.968
Rev. 0.11 April 25, 2008, page 79 of 181
R61509V
Target Spec
7’h38
VREG1OUT x 0.716
7’h78
7’h39
VREG1OUT x 0.720
7’h79
VREG1OUT x 0.972
VREG1OUT x 0.976
7’h3A
VREG1OUT x 0.724
7’h7A
VREG1OUT x 0.980
7’h3B
VREG1OUT x 0.728
7’h7B
VREG1OUT x 0.984
7’h3C
VREG1OUT x 0.732
7’h7C
VREG1OUT x 0.988
7’h3D
VREG1OUT x 0.736
7’h7D
VREG1OUT x 0.992
7’h3E
VREG1OUT x 0.740
7’h7E
VREG1OUT x 0.996
7’h3F
VREG1OUT x 0.744
7’h7F
VREG1OUT x 1.000
Notes: 1. Make sure the VCOMH level is between 3.0V to (DDVDH-0.5)V.
2. The above setting is enabled when internal electronic volume is selected for setting the VCOMH
level.
Rev. 0.11 April 25, 2008, page 80 of 181
R61509V
Target Spec
Window Address Control
Window Horizontal RAM Address Start (R210h), Window Horizontal RAM Address End
(R211h)
Window Vertical RAM Address Start (R212h), Window Vertical RAM Address End (R213h)
R
210
R
211
R
212
R
213
R/W
RS
R/W
1
0
0
0
0
0
0
0
Default
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
Default
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
Default
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
Default
0
0
0
0
0
0
0
R/W
R/W
R/W
IB15 IB14 IB13 IB12 IB11 IB10
IB9
IB8
IB7
HSA
[7]
0
0
HEA
0
[7]
0
1
VSA VSA
[8]
[7]
0
0
VEA VEA
[8]
[7]
1
1
0
IB6
HSA
[6]
0
HEA
[6]
1
VSA
[6]
0
VEA
[6]
0
IB5
HSA
[5]
0
HEA
[5]
1
VSA
[5]
0
VEA
[5]
1
IB4
HSA
[4]
0
HEA
[4]
0
VSA
[4]
0
VEA
[4]
0
IB3
HSA
[3]
0
HEA
[3]
1
VSA
[3]
0
VEA
[3]
1
IB2
HSA
[2]
0
HEA
[2]
1
VSA
[2]
0
VEA
[2]
1
IB1
HSA
[1]
0
HEA
[1]
1
VSA
[1]
0
VEA
[1]
1
IB0
HSA
[0]
0
HEA
[0]
1
VSA
[0]
0
VEA
[0]
1
HSA[7:0], HEA[7:0]: HSA[7:0] and HEA[7:0] specify the start and end addresses of the window address
area in horizontal direction, respectively. See GRAM Address Map. HSA[7:0] and HEA[7:0] specify the
horizontal range to write data. Set HSA[7:0] and HEA[7:0] before starting RAM write operation. In
setting, make sure that 8’h00 ≤ HSA < HEA ≤ 8’hEF.
VSA[8:0], VEA[8:0]: VSA[8:0] and VEA[8:0] specify the start and end addresses of the window address
area in vertical direction, respectively. See GRAM Address Map. VSA[8:0] and VEA[8:0] specify the
vertical range to write data. Set VSA[8:0] and VEA[8:0] before starting RAM write operation. In setting,
make sure that 9’h000 ≤ VSA < VEA ≤ 9’h1AF.
17'h000-00
HSA
HEA
Window address area setting range:
HSA HEA 8'hEF,
8'h00
HEA - HSA 8'h4,
VSA VEA 9'h1AF
9'h000
VSA
Window address area
Notes: 1. Make an window address area within the GRAM address area.
2. Set an address within the window address area.
VEA
17'h1AF-EF
Figure 9 GRAM Address Map and Window Address Area
Rev. 0.11 April 25, 2008, page 81 of 181
R61509V
Target Spec
γ Control
γ Control 1 ~ 14 (R300h to R309h)
R/W
R
300
W
RS
1
Default
R
301
W
1
Default
R
302
R
303
R
304
R
305
W
R
R
R
308
R
309
0
0
PR0
P01
[3]
PR0
P01
[2]
IB8
PR0
P01
[1]
PR0
P01
[0]
IB5
0
0
0
0
0
0
IB4
IB1
IB0
PR0
PR0P PR0P PR0P
P00
00[4] 00[3] 00[2]
[1]
PR0
P00
[0]
0
0
0
0
0
0
0
0
PR0
P04
[3]
PR0
P04
[2]
PR0
P04
[1]
PR0
P04
[0]
PR0
P03
[3]
PR0
P03
[2]
PR0
P03
[1]
PR0
P03
[0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PR0
P06
[4]
PR0
P06
[3]
PR0
P06
[2]
PR0
P06
[1]
PR0
P06
[0]
0
0
0
0
0
0
0
0
IB3
0
IB2
0
0
PR0
PR0P PR0P PR0P
P02
02[4] 02[3] 02[2]
[1]
0
0
0
0
PR0
PR0P PR0P
P05
05[3] 05[2]
[1]
0
PR0
P02
[0]
0
PR0
P05
[0]
0
0
0
Default
0
0
0
0
0
0
0
0
0
PR0
P08
[4]
PR0
P08
[3]
PR0
P08
[2]
PR0
P08
[1]
PR0
P08
[0]
0
0
0
0
0
0
0
0
0
0
0
PI0
P2
[1]
PI0
P2
[0]
0
0
PI0
P1
[1]
PI0
P1
[0]
0
0
0
0
0
0
0
0
PR0
N00
[4]
PR0
N00
[3]
PR0
N00
[2]
PR0
N00
[1]
PR0
N00
[0]
W
1
0
0
Default
0
0
0
0
PI0
P3
[0]
0
0
0
0
PR0
PR0P PR0P PR0P
P07
07[4] 07[3] 07[2]
[1]
0
0
PR0
P07
[0]
0
0
0
0
PI0
P0
[1]
PI0
P0
[0]
1
0
0
PI0
P3
[1]
Default
0
0
0
0
0
0
0
0
0
PR0
N01
[4]
PR0
N01
[3]
PR0
N01
[2]
PR0
N01
[1]
PR0
N01
[0]
0
0
0
0
0
0
0
0
0
0
0
PR0
N02
[3]
PR0
N02
[2]
PR0
N02
[1]
PR0
N02
[0]
W
W
1
W
1
Default
307
0
PR0
P01
[4]
IB7
IB
6
IB9
1
Default
306
IB15 IB14 IB13 IB12 IB11 IB10
W
0
0
0
0
0
0
0
0
0
0
0
0
PR0
N04
[3]
PR0
N04
[2]
PR0
N04
[1]
PR0
N04
[0]
PR0
N03
[3]
PR0
N03
[2]
PR0
N03
[1]
PR0
N03
[0]
0
0
0
PR0
N02
[4]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PR0
N06
[4]
PR0
N06
[3]
PR0
N06
[2]
PR0
N06
[1]
PR0
N06
[0]
0
0
0
0
PR0
N05
[3]
PR0
N05
[2]
PR0
N05
[1]
PR0
N05
[0]
0
0
0
0
0
0
0
0
0
PR0
N07
[4]
PR0
N07
[3]
PR0
N07
[2]
PR0
N07
[1]
PR0
N07
[0]
0
0
0
0
PI0
N0
[0]
0
1
0
0
0
Default
0
0
0
0
0
0
0
0
0
PR0
N08
[4]
PR0
N08
[3]
PR0
N08
[2]
PR0
N08
[1]
PR0
N08
[0]
0
0
0
0
0
0
0
0
0
0
PI0
N2
[0]
0
0
PI0
N1
[1]
PI0
N1
[0]
0
0
PI0
N0
[1]
0
0
0
0
0
0
0
0
W
1
0
0
Default
0
0
0
0
PI0
N3
[0]
0
0
PI0
N2
[1]
0
0
0
0
1
0
0
PI0
N3
[1]
Default
0
0
0
W
Rev. 0.11 April 25, 2008, page 82 of 181
R61509V
PR0P00[4:0]
PR0N00[4:0]
PR0P01[4:0]
PR0N01[4:0]
PR0P02[4:0]
PR0N02[4:0]
PR0P03[3:0]
PR0N03[3:0]
PR0P04[3:0]
PR0N04[3:0]
PR0P05[3:0]
PR0N05[3:0]
PR0P06[4:0]
PR0N06[4:0]
PR0P07[4:0]
PR0N07[4:0]
PR0P08[4:0]
PR0N08[4:0]
PI0P0~1[1:0]
PI0N0~1[1:0]
PI0P2~3[1:0]
PI0N2~3[1:0]
Target Spec
Adjusts reference level for positive polarity output R0
Adjusts reference level for negative polarity output R0
Adjusts reference level for positive polarity output R1
Adjusts reference level for negative polarity output R1
Adjusts reference level for positive polarity output R2
Adjusts reference level for negative polarity output R2
Adjusts reference level for positive polarity output R3
Adjusts reference level for negative polarity output R3
Adjusts reference level for positive polarity output R4
Adjusts reference level for negative polarity output R4
Adjusts reference level for positive polarity output R5
Adjusts reference level for negative polarity output R5
Adjusts reference level for positive polarity output R6
Adjusts reference level for negative polarity output R6
Adjusts reference level for positive polarity output R7
Adjusts reference level for negative polarity output R7
Adjusts reference level for positive polarity output R8
Adjusts reference level for negative polarity output R8
Adjusts interpolation level for positive polarity output (V2~V7)
Adjusts interpolation level for negative polarity output (V2~V7)
Adjusts interpolation level for positive polarity output (V56~V61)
Adjusts interpolation level for negative polarity output (V56~V61)
Rev. 0.11 April 25, 2008, page 83 of 181
R61509V
Target Spec
Base Image Display Control
Base Image Number of Line (R400h)
Base Image Display Control (R401h)
Base Image Vertical Scroll Control (R404h)
R/W
R
400
RS
401
R
404
IB9
NL
NL
NL
NL
NL
NL
[5]
[4]
[3]
[2]
[1]
[0]
0
1
1
0
1
0
1
0
0
0
0
0
Default
0
0
0
0
0
R/W
1
Default
R
IB15 IB14 IB13 IB12 IB11 IB10
R/W
R/W
GS
IB8
IB7
IB6
IB5
IB4
IB3
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
Default
0
0
0
0
0
0
0
IB2
IB1
SCN SCN SCN SCN SCN SCN
[3]
[2]
[1]
[0]
[5] [4]
0
0
IB0
0
0
NDL VLE REV
0
0
0
0
0
0
0
0
0
VL
VL
VL
VL
VL
VL
VL
VL
VL
[8]
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
0
0
0
0
0
0
0
0
0
GS: Sets the direction of scan by the gate driver in the range determined by SCN and NL bits. The gate
scan direction determined by setting GS = 0 is reversed by setting GS = 1. Set GS bit in combination with
SM bits.
NL[5:0]: Sets the number of lines to drive the LCD at an interval of 8 lines. The GRAM address mapping
is not affected by the number of lines set by NL[5:0]. The number of lines must be the same or more than
the number of lines necessary for the size of the liquid crystal panel.
SCN[5:0]: Specifies the gate line where the gate driver starts scan.
NDL: Sets the source output level in non-lit display area. Settings are different depending on panel type
(i.e. normally black or normally white).
Table 49
NDL
Non-lit display area
Positive
Negative
0
V63
V0
1
Note:
V0
V63
NDL setting is enabled in non-lit display area in partial display operation.
VLE: Vertical scroll display enable bit. When VLE = 1, the R61509V starts displaying the base image
from the line (of the physical display) determined by VL[8:0] bits. VL[8:0] sets the amount of scrolling,
which is the number of lines to shift the start line of the display from the first line of the physical display.
Note that the partial image display position is not affected by the base image scrolling.
The vertical scrolling is disabled in external display interface operation. In this case, make sure to set VLE
= “0”.
Rev. 0.11 April 25, 2008, page 84 of 181
R61509V
Target Spec
Table 50
VLE
Base image
0
Fixed
1
Scrolling enabled
REV: Grayscale level of a image is inverted when REV = 1. This enables the R61509V to display the
same image from the same set of data both on normally black and white panels.
Table 51
REV
Source Output Level in Display Area
GRAM Data
Positive Polarity
18’h00000
V63
:
:
0
Negative Polarity
V0
:
18’h3FFFFF
V0
V63
18’h00000
V0
V63
1
:
:
18’h3FFFFF
V63
:
V0
Note: Source output of non-lit display area is set by NDL bit during partial display mode.
VL[8:0]: Sets the amount of scrolling of the base image. The base image is scrolled in vertical direction
and displayed from the line which is determined by VL.
Table 52
VL [8:0]
Line per scrolling
9’h000
0 lines
9’h001
1 line
9’h002
2 lines
:
:
:
:
9’h1A0
431 lines
9’h1B0
432 lines
9’h1FF
Setting inhibited
Rev. 0.11 April 25, 2008, page 85 of 181
R61509V
Target Spec
Table 53
NL [5:0]
6’h00
Number of drive line
NL [5:0]
Number of drive line
Setting inhibited
6’h1C
6’h01
16 lines
6’h1D
240 lines
6’h02
24 lines
6’h1E
248 lines
6’h03
32 lines
6’h1F
256 lines
6’h04
40 lines
6’h20
264 lines
6’h05
48 lines
6’h21
272 lines
6’h06
56 lines
6’h22
280 lines
6’h07
64 lines
6’h23
288 lines
6’h08
72 lines
6’h24
296 lines
6’h09
80 lines
6’h25
304 lines
6’h0A
88 lines
6’h26
312 lines
6’h0B
96 lines
6’h27
320 lines
6’h0C
104 lines
6'h28
328 lines
6’h0D
112 lines
6'h29
336 lines
6’h0E
120 lines
6'h2A
344 lines
6’h0F
128 lines
6'h2B
352 lines
6’h10
136 lines
6'h2C
360 lines
6’h11
144 lines
6'h2D
368 lines
6’h12
152 lines
6'h2E
376 lines
6’h13
160 lines
6'h2F
384 lines
6’h14
168 lines
6'h30
392 lines
6’h15
176 lines
6'h31
400 lines
6’h16
184 lines
6'h32
408 lines
6’h17
192 lines
6'h33
416 lines
6’h18
200 lines
6'h34
424 lines
6’h19
208 lines
6'h35
432 lines
6’h1A
216 lines
6'h36-6'h3F
Setting inhibited
6’h1B
224 lines
Rev. 0.11 April 25, 2008, page 86 of 181
232 lines
R61509V
Target Spec
Table 54
Gate scan start position
SCN[5:0]
SM=0
SM=1
GS=0
GS=1
GS=0
GS=1
6’h00
G1
G(N)
G1
G(2N-432)
6’h01
G9
G(N+8)
G17
G(2N-416)
6’h02
G17
G(N+16)
G33
G(2N-400)
6’h03
G25
G(N+24)
G49
G(2N-384)
6’h04
G33
G(N+32)
G65
G(2N-368)
6’h05
G41
G(N+40)
G81
G(2N-352)
6’h06
G49
G(N+49)
G97
G(2N-336)
6’h07
G57
G(N+56)
G113
G(2N-320)
6’h08
G65
G(N+64)
G129
G(2N-304)
6’h09
G73
G(N+72)
G145
G(2N-288)
6’h0A
G81
G(N+80)
G161
G(2N-272)
6’h0B
G89
G(N+88)
G177
G(2N-256)
6’h0C
G97
G(N+96)
G193
G(2N-240)
6’h0D
G105
G(N+104)
G209
G(2N-224)
6’h0E
G113
G(N+112)
G225
G(2N-208)
6’h0F
G121
G(N+120)
G241
G(2N-192)
6’h10
G129
G(N+128)
G257
G(2N-176)
6’h11
G137
G(N+136)
G273
G(2N-160)
6’h12
G145
G(N+144)
G289
G(2N-144)
6’h13
G153
G(N+152)
G305
G(2N-128)
6’h14
G161
G(N+160)
G321
G(2N-112)
6’h15
G169
G(N+168)
G337
G(2N-96)
6’h16
G177
G(N+176)
G353
G(2N-80)
6’h17
G185
G(N+184)
G369
G(2N-64)
6’h18
G193
G(N+192)
G385
G(2N-48)
6’h19
G201
G(N+200)
G401
G(2N-32)
6’h1A
G209
G(N+208)
G417
G(2N-16)
6’h1B
G217
G(N+216)
G2
G(2N-431)
6’h1C
G225
G(N+224)
G18
G(2N-415)
6’h1D
G233
G(N+232)
G34
G(2N-399)
6’h1E
G241
G(N+240)
G50
G(2N-383)
6’h1F
G249
G(N+248)
G66
G(2N-367)
6’h20
G257
G(N+256)
G82
G(2N-351)
6’h21
G265
G(N+264)
G98
G(2N-335)
6’h22
G273
G(N+272)
G114
G(2N-319)
6’h23
G281
G(N+280)
G130
G(2N-303)
6’h24
G289
G(N+288)
G146
G(2N-287)
6’h25
G297
G(N+296)
G162
G(2N-271)
6’h26
G305
G(N+304)
G178
G(2N-255)
6’h27
G313
G(N+312)
G194
G(2N-239)
6’h28
G321
G(N+320)
G210
G(2N-223)
6’h29
G329
G(N+328)
G226
G(2N-207)
6’h2A
G337
G(N+337)
G242
G(2N-191)
6’h2B
G345
G(N+344)
G258
G(2N-175)
6’h2C
G353
G(N+352)
G274
G(2N-159)
6’h2D
G361
G(N+360)
G290
G(2N-143)
6’h2E
G369
G(N+368)
G306
G(2N-127)
6’h2F
G377
G(N+376)
G322
G(2N-111)
6’h30
G385
G(N+384)
G338
G(2N-95)
6’h31
G393
G(N+392)
G354
G(2N-79)
6’h32
G401
G(N+400)
G370
G(2N-63)
6’h33
G409
G(N+408)
G386
G(2N-47)
6’h34
G417
G(N+416)
G402
G(2N-31)
6’h35-6’h3F
Setting inhibited
Setting inhibited
Setting inhibited
Setting inhibited
Note: “N” is the number of line decided by NL [5:0] bit.
Make sure that (Gate scan start position + NL = Gate scan end position) does not exceed 432 lines.
Rev. 0.11 April 25, 2008, page 87 of 181
R61509V
Target Spec
Partial Display Control
Partial Image 1: Display Position (R500h), RAM Address 1 (Start Line Address) (R501h), RAM
Address 1 (End Line Address) (R502h)
R/W
R
500h
R
501h
R
502h
R/W
RS
IB15
IB14
IB13
IB12
IB11
IB10
IB9
IB8
IB7
IB6
IB5
IB4
IB3
IB2
IB1
IB0
PTD
P [8]
PTD
P [7]
PTD
P [6]
PTD
P [5]
PTD
P [4]
PTD
P [3]
PTD
P [2]
PTD
P [1]
PTD
P [0]
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
Default
0
0
0
0
0
0
0
R/W
1
0
0
0
0
0
0
0
Default
0
0
0
0
0
0
0
R/W
1
0
0
0
0
0
0
0
Default
0
0
0
0
0
0
0
PTS PTS PTS PTS PTS PTS PTS PTS PTS
A [8] A [7] A [6] A [5] A [4] A [3] A [2] A [1] A [0]
0
PTE
A
[8]
0
0
PTE
A
0[7]
0
0
0
0
0
0
0
0
PTE PTE PTE PTE PTE PTE PTE
A [6] A [5] A [4] A [3] A [2] A [1] A [0]
0
0
0
0
0
0
0
PTDP[8:0]: Sets the display position of partial image 1.
If PTDP0 = “9’h000”, the partial image 1 is displayed from the first line of the base image.
PTSA[8:0] and PTEA[8:0]: Sets the start line and end line addresses of the RAM area, respectively for the
partial image 1. In setting, make sure that PTSA ≤ PTEA.
Rev. 0.11 April 25, 2008, page 88 of 181
R61509V
Target Spec
Pin Control
Test Register (Software Reset) (R600h)
R/W RS
R/W
1
Default value
IB15 IB14 IB13 IB12 IB11 IB10 IB9
IB8
IB7
IB6
IB5
IB4
IB3
IB2
IB1
IB0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
TRSR
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
TRSR: When TRSR = 1, test registers are initialized.
When TRSR = 0, initialization of test registers halts.
Instruction Write
R600h TRSR="1"
Test registers are initialized (0.1ms or longer)
Instruction Write
R600h TRSR="0"
㩷
Figure 10
Rev. 0.11 April 25, 2008, page 89 of 181
R61509V
Target Spec
NVM Control
NVM Access Control 1 (R6F0h), NVM Access Control 2 (R6F1h), NVM Access Control 3
(R6F2h)
R/W
R
6F0h
R/W
RS
1
Default
R
6F1h
R/W
1
Default
R
6F2h
R/W
1
Default
IB15
IB14
0
0
IB13
IB12
0
0
0
0
0
NV
NV
NV
DAT DAT DAT
[15] [14] [13]
0
0
0
0
NV
DAT
[12]
0
IB11
IB10
IB9
IB8
IB7
IB6
IB5 IB4 IB3
IB2 IB1
IB0
EOP EOP
0
0
0
0
TE
0
0
0
0
[1]
[0]
0
0
0
0
0
0
0
0
0
0
0
0
NV
NV
NV
NV
NV
NV
NV
NV
NV
NV
NV
NV
DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT
[11] [10]
[9]
[8]
[7]
[6]
[5]
[4]]
[3]
[2]]
[1]
[0]
0
0
0
0
0
0
0
0
0
0
0
0
CAL
B
0
0
0
0
0
0
0
0
0
0
0
0
NVV
RF
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
EOP [1:0]: Writes data on R280h to NVM or halts the write operation.
Table 55
EOP[1:0]
NVM control
2’h0
Halt
2’h1
Write
2’h2
Setting disabled
2’h3
Erase
CALB: When CALB=1, all data in NVM is read out and written to internal registers. When finished,
CALB is set to 0.
TE: Enables internal NVM control bit (EOP). Follow the NVM control sequence when setting TE.
NVDAT[15:0]: To write data to NVM, write the data on NVDAT (R6F1h) first, and then start write
operation using EOP bit.
・ NVM data written to NVDAT[14:8] are loaded to R280h VCM [6:0] when power on reset is executed
or CALB=1.
・ NVM data written to NVDAT[7:0] are loaded to R280h UID [7:0] when power on reset is executed or
CALB=1.
See “NVM Control” for details of write operation and required settings.
Rev. 0.11 April 25, 2008, page 90 of 181
R61509V
Target Spec
Write “1” to NVDAT[15].
R6F1h
Write data to NVM
(NVM)
Read data from NVM
㪥㪭㩷
㪛㪘㪫㩷
㪲㪈㪌㪴㩷
㪥㪭㩷
㪛㪘㪫㩷
㪲㪈㪋㪴㩷
㪥㪭㩷
㪛㪘㪫㩷
㪲㪈㪉㪴㩷
㪥㪭
㪛㪘㪫
㪲㪈㪈㪴
㪥㪭
㪛㪘㪫
㪲㪈㪇㪴
㪥㪭
㪛㪘㪫
㪲㪐㪴
㪥㪭
㪛㪘㪫
㪲㪏㪴
㪥㪭
㪛㪘㪫
㪲㪎㪴
㪥㪭
㪛㪘㪫
㪲㪍㪴
㪥㪭
㪛㪘㪫
㪲㪌㪴
㪥㪭
㪛㪘㪫
㪲㪋㪴
㪥㪭㩷
㪛㪘㪫㩷
㪲㪊㪴㩷
㪥㪭㩷
㪛㪘㪫㩷
㪲㪉㪴㩷
㪥㪭㩷
㪛㪘㪫㩷
㪲㪈㪴㩷
㪥㪭
㪛㪘㪫
㪲㪇㪴
㸣㩷㸣 㸣 㸣 㸣 㸣 㸣 㸣 㸣 㸣 㸣 㸣 㸣 㸣 㸣 㸣
㩷
㪥㪭㪤㩷
㪲㪈㪌㪴㩷
㪥㪭㪤㩷
㪲㪈㪋㪴㩷
㩷
㪥㪭㪤㩷
㪲㪈㪊㪴㩷
㩷
㪥㪭㪤㩷
㪲㪈㪉㪴㩷
㩷
㪥㪭㪤
㪲㪈㪈㪴
㪥㪭㪤
㪲㪈㪇㪴
㪥㪭㪤
㪲㪐㪴
㪥㪭㪤
㪲㪏㪴
㪥㪭㪤
㪲㪎㪴
㪥㪭㪤
㪲㪍㪴
㪥㪭㪤
㪲㪌㪴
㪥㪭㪤
㪲㪋㪴
㪥㪭㪤㩷
㪲㪊㪴㩷
㩷
㪥㪭㪤㩷
㪲㪉㪴㩷
㩷
㪥㪭㪤㩷
㪲㪈㪴㩷
㪥㪭㪤
㪲㪇㪴
㸣㸣㸣 㸣㸣㸣㸣㸣㸣㸣㸣㸣㸣㸣㸣 㸣
㩷
R280h
㪥㪭㩷
㪛㪘㪫㩷
㪲㪈㪊㪴㩷
㪈㩷
㩷
㪭㪚㪤㩷
㪲㪍㪴㩷
㩷
㪭㪚㪤㩷
㪲㪌㪴㩷
㩷
㪭㪚㪤㩷
㪲㪋㪴㩷
㩷
㪭㪚㪤
㪲㪊㪴
㪭㪚㪤
㪲㪉㪴
㪭㪚㪤
㪲㪈㪴
㪭㪚㪤
㪲㪇㪴
㪬㪠㪛
㪲㪎㪴
㪬㪠㪛
㪲㪍㪴
㪬㪠㪛
㪲㪌㪴
㪬㪠㪛
㪲㪋㪴
㪬㪠㪛㩷
㪲㪊㪴㩷
㩷
㪬㪠㪛㩷
㪲㪉㪴㩷
㩷
㪬㪠㪛㩷
㪲㪈㪴㩷
Figure 11
NVVRF: Enables erase verify. This bit is used only in the NVM erase sequence. See “NVM Erase
Sequence” for details.
Rev. 0.11 April 25, 2008, page 91 of 181
㪬㪠㪛
㪲㪇㪴
●R61509V Instruction List
Major category
Index
Upper Index
0**
Rev 0.50 2008. 04. 22
Middle category
Index
Display Control
－
00*
000h
Device Code Read
001h
Driver Output Control
0
0
0
0
0
004h
005h
006h
Setting inhibited
Setting inhibited
Setting inhibited
007h
Display Control 1
0
0
0
008h
Display Control 2
FP[7]
(0)
FP[6]
(0)
009h
Display Control 3
0
00Ah
Setting inhibited
00Bh
8 Color Control
External Display Interface Control
1
Setting inhibited
External Display Interface Control
2
0
0
IB10
IB9
IB8
IB7
IB6
IB5
Lower Code
IB4
IB3
IB2
IB1
IB0
ID10
ID9
ID8
ID7
ID6
ID5
ID4
ID2
ID21
ID0
0
0
TRI
(0)
0
0
0
DFM
(0)
0
0
0
0
0
0
0
SM
(0)
0
SS
(0)
0
0
0
BC
(0)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BASEE
(0)
0
0
0
0
0
0
-
0
0
0
-
0
0
0
-
0
0
0
0
0
0
0
0
0
-
0
0
0
ID[1]
(1)
0
0
0
ID[0]
(1)
0
0
0
AM
(0)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
-
FP[2]
(0)
FP[1]
(0)
FP[0]
(0)
BP[7]
(0)
BP[6]
(0)
BP[5]
(0)
BP[4]
(0)
BP[3]
(1)
BP[2]
(0)
BP[1]
(0)
BP[0]
(0)
-
0
0
0
0
0
0
0
0
0
0
0
0
-
0
0
0
PTS
(0)
0
0
0
PTV
(0)
0
0
0
0
0
0
0
0
0
0
-
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
COL
(0)
ENC[1]
(0)
0
ENC[0]
(0)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
HSPL
(0)
0
EPL
(0)
RIM
(0)
0
DPL
(0)
-
0
DM[0]
(0)
0
VSPL
(0)
0
0
DM[1]
(0)
0
0
0
RM
(0)
0
0
0
ENC[2]
(0)
0
DIVI[0]
(0)
0
0
0
RTNI[4]
(1)
RTNI[3]
(1)
RTNI[2]
(0)
RTNI[1]
(0)
RTNI[0]
(1)
-
0
0
0
0
0
SDTI[2]
(0)
SDTI[1]
(0)
SDTI[0]
(1)
-
SEQWI[1]
(0)
SEQWI[0]
(0)
-
MCPI[1]
(0)
MCPI[0]
(1)
0
Panel Interface Control 1
0
0
0
0
0
0
Panel Interface Control 2
0
0
0
0
0
NOWI[2]
(0)
NOWI[1]
(0)
NOWI[0]
(1)
VEQWI[1]
(0)
VEQWI[0]
(0)
ORG
(0)
0
0
0
0
0
0
0
0
012h
Panel Interface Control 3
0
0
0
0
0
VEQWI[2]
(0)
0
0
0
0
0
SEQWI[2]
(0)
013h
Panel Interface Control 4
0
0
0
0
0
0
0
0
0
0
0
0
0
MCPI[2]
(0)
014h
Panel Interface Control 5
0
0
0
0
0
0
0
0
0
014-01Fh
Setting inhibited
0
0
0
0
0
0
020h
Panel Interface Control 6
0
0
0
0
0
0
0
DIVE[0]
(0)
0
02*
0
DIVE[1]
(0)
Panel Interface
(External Clock)
021h
Panel Interface Control 7
0
0
0
0
0
NOWE[2]
(0)
NOWE[1]
(0)
NOWE[0]
(1)
0
VEQWE[2] VEQWE[1] VEQWE[0]
(0)
(0)
(0)
Panel Interface Control 8
0
0
0
0
0
0
0
PCDIVH[2] PCDIVH[1] PCDIVH[0]
(1)
(0)
(1)
0
0
0
RTNE[4]
0
0
(1)
0
0
0
0
0
0
0
0
RTNE[3]
(1)
0
0
PCDIVL[2] PCDIVL[1] PCDIVL[0]
(1)
(0)
(1)
0
0
0
RTNE[2]
RTNE[1]
RTNE[0]
(0)
(0)
(1)
SDTE[2]
(0)
SDTE[1]
(0)
SDTE[0]
(1)
SEQWE[2] SEQWE[1] SEQWE[0]
(0)
(0)
(0)
MCPE[2]
(0)
MCPE[1]
(0)
-
-
-
MCPE[0]
(1)
023h
Panel Interface Control 9
0
0
0
0
0
0
0
0
0
0
0
0
024h-08Fh
Setting inhibited
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
090h
Frame Marker Control
FMI[2]
(0)
0
FMI[1]
(0)
0
FMI[0]
(0)
0
0
0
0
0
FMP[6]
(0)
0
0
0
0
FMP[2]
(0)
0
DSTB
(0)
FMP[0]
(0)
0
0
FMP[4]
(0)
0
AP[0]
(1)
FMP[1]
(0)
0
0
FMP[5]
(0)
0
AP[1]
(1)
FMP[3]
(0)
0
0
0
BT[1]
(1)
FMP[7]
(0)
0
Power Control 1
0
BT[2]
(0)
FMP[8]
(0)
0
BT[0]
(1)
-
Setting inhibited
FMKM
(0)
0
0
0
-
DC1[2]
(0)
DC1[1]
(1)
DC1[0]
(0)
0
DC0[2]
(1)
DC0[1]
(0)
DC0[0]
(0)
0
VC[2]
(1)
VC[1]
(1)
VC[0]
(1)
-
0
PSON
(0)
PON
(0)
0
0
0
0
-
100h
101h
102h
0
Power Control 2
0
0
0
0
0
Power Control 3
VRH[4]
(0)
VRH[3]
(0)
VRH[2]
(0)
VRH[1]
(0)
VRH[0]
(0)
0
0
VCMR
(1)
VDV[3]
(0)
0
VDV[2]
(0)
0
VDV[1]
(0)
0
VDV[0]
(0)
0
103h
Power Control 4
0
0
0
104-1FFh
Setting inhibited
RAM Address Set
(Horizontal Address)
RAM Address Set
(Vertical Address)
GRAM Data Write/GRAM Data
Read
Setting inhibited
Window Horizontal RAM Address
Start
Window Horizontal RAM Address
End
Window Vertical RAM Address
Start
0
0
0
VDV[4]
(0)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
AD[16]
(0)
20*
200h
RAM Read/Write
201h
202h
203-20Fh
210h
211h
212h
1
0
0
0
0
0
0
0
0
0
0
0
AD[7]
(0)
0
AD[6]
(0)
0
AD[5]
(0)
0
AD[4]
(0)
0
AD[3]
(0)
0
AD[2]
(0)
0
AD[1]
(0)
0
AD[0]
(0)
AD[15]
(0)
AD[14]
(0)
AD[13]
(0)
AD[12]
(0)
AD[11]
(0)
AD[10]
(0)
AD[9]
(0)
AD[8]
(0)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
HSA[5]
(0)
0
HSA[4]
(0)
0
HSA[3]
(0)
0
HSA[2]
(0)
0
HSA[1]
(0)
0
HSA[0]
(0)
-
HEA[6]
(1)
HEA[5]
(1)
HEA[4]
(0)
HEA[3]
(1)
HEA[2]
(1)
HEA[1]
(1)
HEA[0]
(1)
-
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VSA[8]
(0)
VSA[7]
(0)
VSA[6]
(0)
VSA[5]
(0)
VSA[4]
(0)
VSA[3]
(0)
VSA[2]
(0)
VSA[1]
(0)
VSA[0]
(0)
-
0
VEA[8]
(1)
VEA[7]
(1)
VEA[6]
(0)
VEA[5]
(1)
VEA[4]
(0)
VEA[3]
(1)
VEA[2]
(1)
VEA[1]
(1)
VEA[0]
(1)
-
UID[7]
(1)
0
UID[6]
(1)
0
UID[5]
(1)
0
0
0
0
0
0
280h
NVM Data Read / NVM Data Write
1
281-2FFh
Setting inhibited
30*
300h
Gamma Control (1)
Gamma Control
301h
Gamma Control (2)
PR0P04[3] PR0P04[2] PR0P04[1] PR0P04[0] PR0P03[3] PR0P03[2] PR0P03[1] PR0P03[0]
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
302h
Gamma Control (3)
0
0
0
PR0P06[4] PR0P06[3] PR0P06[2] PR0P06[1] PR0P06[0]
(0)
(0)
(0)
(0)
(0)
0
303h
Gamma Control (4)
0
0
0
PR0P08[4] PR0P08[3] PR0P08[2] PR0P08[1] PR0P08[0]
(0)
(0)
(0)
(0)
(0)
0
0
0
0
0
VCM[6]
(1)
0
VCM[5]
(1)
0
0
0
0
0
0
0
-
304h
Gamma Control (5)
0
0
PI0P3[1]
(0)
305h
Gamma Control (6)
0
0
0
VCM[4]
VCM[3]
VCM[2]
VCM[1]
VCM[0]
(1)
(1)
(1)
(1)
(1)
0
0
0
0
0
PR0P01[4] PR0P01[3] PR0P01[2] PR0P01[1] PR0P01[0]
(0)
(0)
(0)
(0)
(0)
PI0P3[0]
(0)
0
0
PI0P2[1]
(0)
PI0P2[0]
(0)
PR0N01[4] PR0N01[3] PR0N01[2] PR0N01[1] PR0N01[0]
(0)
(0)
(0)
(0)
(0)
PR0N04[3] PR0N04[2] PR0N04[1] PR0N04[0] PR0N03[3] PR0N03[2] PR0N03[1] PR0N03[0]
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
UID[4]
UID[3]
UID[2]
UID[1]
UID[0]
(1)
(1)
(1)
(1)
(1)
0
0
0
0
0
PR0P00[4] PR0P00[3] PR0P00[2] PR0P00[1] PR0P00[0]
(0)
(0)
(0)
(0)
(0)
-
0
PR0P02[4] PR0P02[3] PR0P02[2] PR0P02[1] PR0P02[0]
(0)
(0)
(0)
(0)
(0)
-
0
0
PR0P05[3] PR0P05[2] PR0P05[1] PR0P05[0]
(0)
(0)
(0)
(0)
-
0
0
PR0P07[4] PR0P07[3] PR0P07[2] PR0P07[1] PR0P07[0]
(0)
(0)
(0)
(0)
(0)
-
0
0
PI0P1[1]
(0)
0
0
0
PR0N00[4] PR0N00[3] PR0N00[2] PR0N00[1] PR0N00[0]
(0)
(0)
(0)
(0)
(0)
-
PR0N02[4] PR0N02[3] PR0N02[2] PR0N02[1] PR0N02[0]
(0)
(0)
(0)
(0)
(0)
-
PR0N05[3] PR0N05[2] PR0N05[1] PR0N05[0]
(0)
(0)
(0)
(0)
-
PR0N07[4] PR0N07[3] PR0N07[2] PR0N07[1] PR0N07[0]
(0)
(0)
(0)
(0)
(0)
-
0
PI0P1[0]
(0)
0
306h
Gamma Control (7)
0
0
0
307h
Gamma Control (8)
0
0
0
PR0N06[4] PR0N06[3] PR0N06[2] PR0N06[1] PR0N06[0]
(0)
(0)
(0)
(0)
(0)
0
0
0
308h
Gamma Control (9)
0
0
0
PR0N08[4] PR0N08[3] PR0N08[2] PR0N08[1] PR0N08[0]
(0)
(0)
(0)
(0)
(0)
0
0
0
0
0
PI0N3[1]
(0)
PI0N3[0]
(0)
0
PI0N1[0]
(0)
0
GS
(0)
NL[5]
(1)
NL[4]
(1)
NL[3]
(0)
NL[2]
(1)
SCN[3]
(0)
SCN[2]
(0)
Setting inhibited
400ｈ
Base Image Number of Line
-
HEA[7]
(1)
Setting inhibited
Gamma Control (10)
-
0
HSA[6]
(0)
Window Vertical RAM Address End
309h
-
0
HSA[7]
(0)
213h
30Ah-3FFh
-
-
RAM write data WD[17:0] / RAM read data RD [17:0] is transferred via different data bus in different interface operation.
214-27Fh
Base Image Display Control
0
FP[3]
(1)
011h
28*
0
FP[4]
(0)
010h
Window Address
0
Device Code
"B509h"
FP[5]
(0)
0
0
0
01*
21*
0
Note
BGR
(0)
0
0
0
PTDE
(0)
0
Panel Interface
(Internal Clock)
Power Control
ID3
ALMID1[7] ALMID1[6] ALMID1[5] ALMID1[4] ALMID1[3] ALMID1[2] ALMID1[1] ALMID1[0] ALMID0[7] ALMID0[6] ALMID0[5] ALMID0[4] ALMID0[3] ALMID0[2] ALMID0[1] ALMID0[0]
(1)
(0)
(1)
(1)
(0)
(1)
(0)
(1)
(0)
(0)
(0)
(0)
(1)
(0)
(0)
(1)
Entry Mode
Frame Marker Control 091-0FFh
4**
0
Upper Code
IB12
IB11
DIVI[1]
(0)
09*
Gamma Control
IB13
LCD Drive Waveform Control
022h
3**
IB14
003h
00Fh
RAM Access
IB15
002h
00D-00Eh
2**
Index
Display Control
in general
00Ch
1**
Minor category
Command
0
PI0N2[1]
(0)
PI0N2[0]
(0)
0
0
PI0N1[1]
(0)
NL[1]
(0)
NL[0]
(1)
0
0
SCN[5]
(0)
SCN[4]
(0)
0
0
PI0P0[1]
(0)
PI0P0[0]
(0)
-
-
0
PI0N0[1]
(0)
PI0N0[0]
(0)
SCN[1]
(0)
SCN[0]
(0)
0
-
VLE
(0)
0
VL[1]
(0)
0
REV
(0)
0
VL[0]
(0)
0
-
-
401h
Base Image Display Control
0
0
0
0
0
0
0
0
0
0
0
0
0
402h-403h
Setting inhibited
0
0
0
0
0
0
0
404h
Base Image Vertical Scroll Control
0
0
0
0
0
0
0
405-4FFh
Setting inhibited
0
0
0
0
0
0
0
0
VL[8]
(0)
0
0
VL[7]
(0)
0
0
VL[6]
(0)
0
0
VL[5]
(0)
0
0
VL[4]
(0)
0
0
VL[3]
(0)
0
NDL
(0)
0
VL[2]
(0)
0
500h
Partial Image 1: Display Position
0
0
0
0
0
0
0
PTDP[8]
(0)
PTDP[7]
(0)
PTDP[6]
(0)
PTDP[5]
(0)
PTDP[4]
(0)
PTDP[3]
(0)
PTDP[2]
(0)
PTDP[1]
(0)
PTDP[0]
(0)
-
501h
RAM Address 1 (Start Line
Address)
0
0
0
0
0
0
0
PTSA[8]
(0)
PTSA[7]
(0)
PTSA[6]
(0)
PTSA[5]
(0)
PTSA[4]
(0)
PTSA[3]
(0)
PTSA[2]
(0)
PTSA[1]
(0)
PTSA[0]
(0)
-
PTEA[7]
(0)
PTEA[6]
(0)
PTEA[5]
(0)
PTEA[4]
(0)
PTEA[3]
(0)
PTEA[2]
(0)
PTEA[1]
(0)
PTEA[0]
(0)
-
5**
Partial Display Control
6**
Pin Control
60*
6F*
NVM-I/F
502h
RAM Address 2 (End Line Address)
0
0
0
0
0
0
0
PTEA[8]
(0)
503h-5FFh
Setting inhibited
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
600h
Test Register (Software Reset)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
601-6EFh
Setting inhibited
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
EOP[0]
(0)
0
0
0
EOP[1]
(0)
0
NVM Access Control 1
0
CALB
(0)
0
6F0h
0
TE
(0)
0
TRSR
(0)
0
0
0
0
0
6F1h
NVM Access Control 2
6F2h
NVM Access Control 3
6F3-FFFh
Setting inhibited
NVDAT[15] NVDAT[14] NVDAT[13] NVDAT[12] NVDAT[11] NVDAT[10] NVDAT[9] NVDAT[8] NVDAT[7] NVDAT[6] NVDAT[5] NVDAT[4] NVDAT[3] NVDAT[2] NVDAT[1] NVDAT[0]
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
0
0
0
0
0
0
0
0
0
0
0
0
NVVRF
(0)
0
0
-
-
0
-
Note 1: Values in parentheses ( ) are default values.
Note 2: Do not access instructions that are not shown in the above table.
R61509V
Target Spec
Reset Function
The R61509V is initialized by the RESETX input. During reset period, the R61509V is in a busy state and
instruction from the microcomputer and GRAM access are not accepted. The R61509V’s internal power
supply circuit unit is initialized also by the RESETX input. The RESET period must be secured for at least
1ms. In case of power-on reset, wait until the RC oscillation frequency stabilizes (for 1 ms). During this
period, GRAM access and initial instruction setting are prohibited.
1.
Initial state of instruction bits (default)
See the instruction list. The default value is shown in the parenthesis of each instruction bit cell.
2.
RAM Data initialization
The RAM data is not automatically initialized by the RESETX input. It must be initialized by software in
display-off period (D1-0 = “00”).
3.
Output pin initial state * see Note
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
LCD driver S1~S720
G1~G432
VCOM
VCOMH
VCOML
VREG1OUT
VCIOUT
DDVDH
VGH
VGL
VCL
FMARK
Oscillator
SDO
4.
Initial state of input/output pins* see Note
: GND
: VGL (= GND)
: Halt (GND output)
: VCI
: Halt (GND output)
: VGS
: Hi-z
: VCI
: DDVDH (VCI clamp)
: GND
: GND
: Halt (GND output )
: Oscillate
: High level (IOVCC1) when IM2-0 = “10*”(serial interface)
: Hi-z when IM2-0 ≠ “10*”(other than serial interface)
1. C11P
: Hi-z
2. C11M
: Hi-z
3. C12P
: Hi-z
4. C12M
: Hi-z
5. C13P
: VCI1 (= Hi-z)
6. C13M
: GND
7. C21P
: DDVDH ( = VCI)
8. C21M
: GND
9. C22P
: DDVDH ( = VCI)
10. C22M
: GND
11. VDD
: VDD
Note: The above-mentioned initial states of output and input pins are those of when the R61509V’s power
supply circuit is connected as in Connection Example.
Rev. 0.11 April 25, 2008, page 93 of 181
R61509V
Target Spec
5 When a RESETX input is entered into the R61509V while it is in shutdown mode, the R61509V starts
up the inside logic regulator and makes a transition to the initial state. During this period, the state of the
interface pins may become unstable. For this reason, do not enter a RESETX input in shutdown mode.
6 When transferring instruction in either two or three transfers via 8-/9-/16-bit interface, make sure to
execute data transfer synchronization after reset operation.
Rev. 0.11 April 25, 2008, page 94 of 181
R61509V
Target Spec
Basic Mode Operation of the R61509V
The basic operation modes of the R61509V are shown in the following diagram. When making a transition
from one mode to another, refer to instruction setting sequence.
Initial setting
Display
OFF
Display OFF sequence
(Power OFF sequence)
moving picture
display
VSYNC
interface
VSYNC i/F sequence 2
(DM=10, RM=0)
VSYNC i/F sequence 1
(DM=00, RM=0)
Display ON sequence
(Power ON sequence)
Internal clock
display
operation
Partial
display
sequence 2
Reset
state
DSTB = 1
Deep
standby set
Exit shut down mode
Shut down
mode
RGB i/F (1) sequence 1
(DM=01, RM=1)
RGB i/F (1) sequence 2
(DM=00, RM=0)
Partial
display
sequence 1
Partial
display
Display color control
262k-color
mode
8
262k
color display
sequence
262k
8
color display
sequence
8-color
mode
Figure 12
Rev. 0.11 April 25, 2008, page 95 of 181
Reset
moving picture
display
RGB
interface (1)
RAM access via
system i/F while displaying
moving picture
RGB i/F (2) sequence 1
(DM=01, RM=0)
RGB
interface (2)
RGB i/F (2) sequence 2
(DM=01, RM=1)
R61509V
Target Spec
Interface and Data Format
The R61509V supports system interface for making instruction and other settings, and external display
interface for displaying a moving picture. The R61509V can select the optimum interface for the display
(moving or still picture) in order to transfer data efficiently.
As external display interface, the R61509V supports RGB interface and VSYNC interface, which enables
data rewrite operation without flickering the moving picture on display.
In RGB interface operation, the display operation is executed in synchronization with synchronous signals
VSYNCX, HSYNCX, and DOTCLK. In synchronization with these signals, the R61509V writes display
data according to data enable signal (ENABLE) via RGB data signal bus (DB17-0). The display data is
stored in the R61509V’s GRAM so that data is transferred only when rewriting the frames of moving
picture and the data transfer required for moving picture display can be minimized. The window address
function specifies the RAM area to write data for moving picture display, which enables displaying a
moving picture and RAM data in other than the moving picture area simultaneously. To access the
R61509V’s internal RAM in high speed with low power consumption, use high-speed write function
(HWM = 1) in RGB or VSYNC interface operation.
In VSYNC interface operation, the internal display operation is synchronized with the frame
synchronization signal (VSYNCX). The VSYNC interface enables a moving picture display via system
interface by writing the data to the GRAM at faster than the minimum calculated speed in synchronization
with the falling edge of VSYNCX. In this case, there are restrictions in setting the frequency and the
method to write data to the internal RAM.
The R61509V operates in either one of the following four modes according to the state of the display. The
operation mode is set in the external display interface control register (R0Ch). When switching from one
mode to another, make sure to follow the relevant sequence in setting instruction bits.
Table 56 Operation Modes
Operation Mode
RAM Access Setting (RM)
Display Operation Mode (DM)
Internal clock operation
(displaying still pictures)
System interface
(RM = 0)
Internal clock operation
(DM1-0 = 00)
RGB interface (1)
(displaying moving pictures)
RGB interface
(RM = 1)
RGB interface
(DM1-0 = 01)
RGB interface (2)
(rewriting still pictures while
displaying moving pictures)
System interface
(RM = 0)
RGB interface
(DM1-0 = 01)
VSYNC interface
(displaying moving pictures)
System interface
(RM = 0)
VSYNC interface
(DM1-0 = 10)
Notes: 1. Instructions are set only via system interface.
2. When RGB interface is used, instructions should be transferred via clock synchronous serial
interface.
3. RGB and VSYNC interfaces cannot be used simultaneously.
4. Do not make changes to the RGB interface operation setting (RIM1-0) while RGB interface is
in operation.
5. See the “External Display Interface” section for the sequences when switching from one mode
to another.
Rev. 0.11 April 25, 2008, page 96 of 181
R61509V
Target Spec
CSX
System
interface
RS
WRX
(RDX)
System interface
18/16/9/8
System
DB17-0
RGB interface
18/16
R61509V
ENABLE
VSYNCX
RGB
interface
HSYNCX
DOTCLK
Figure 13
Internal clock operation
The display operation is synchronized with signals generated from internal oscillator’s clock (OSC) in this
mode. All input via external display interface is disabled in this operation. The internal RAM can be
accessed only via system interface.
RGB interface operation (1)
The display operation is synchronized with frame synchronous signal (VSYNCX), line synchronous signal
(HSYNCX), and dot clock signal (DOTCLK) in RGB interface operation. These signals must be supplied
during the display operation via RGB interface.
The R61509V transfers display data in units of pixels via DB17-0 pins. The display data is stored in the
internal RAM. The combined use of window address function can minimize the total number of data
transfer for moving picture display by transferring only the data to be written in the moving picture RAM
area when it is written and enables the R61509V to display a moving picture and the data in other than the
moving picture RAM area simultaneously.
The front porch (FP), back porch (BP), and the display (NL) periods are automatically calculated inside the
R61509V by counting the number of clocks of line synchronous signal (HSYNCX) from the falling edge of
the frame synchronous signal (VSYNCX). Make sure to transfer pixel data via DB17-0 pins in accordance
with the setting of these periods.
Rev. 0.11 April 25, 2008, page 97 of 181
R61509V
Target Spec
RGB interface operation (2)
This mode enables the R61509V to rewrite RAM data via system interface while using RGB interface for
display operation. To rewrite RAM data via system interface, make sure that display data is not transferred
via RGB interface (ENABLE = high). To return to the RGB interface operation, change the ENABLE
setting first. Then set an address in the RAM address set register and R22h in the index register.
VSYNC interface operation
The internal display operation is synchronized with the frame synchronous signal (VSYNCX) in this mode.
This mode enables the R61509V to display a moving picture via system interface by writing data in the
internal RAM at faster than the calculated minimum speed via system interface from the falling edge of
frame synchronous (VSYNCX). In this case, there are restrictions in speed and method of writing RAM
data. For details, see the “VSYNC Interface” section.
As external input, only VSYNCX signal input is valid in this mode. Other input via external display
interface becomes disabled.
The front porch (FP), back porch (BP), and the display (NL) periods are automatically calculated from the
frame synchronous signal (VSYNCX) inside the R61509V according to the instruction settings for these
periods.
FMARK interface operation
In the FMARK interface operation, data is written to internal RAM via system interface synchronizing with
the frame mark signal (FMARK), realizing tearing-less moving picture while using conventional system
interface. In this case, there are restrictions in speed and method of writing RAM data. See “FMARK
interface” for detail.
Rev. 0.11 April 25, 2008, page 98 of 181
R61509V
Target Spec
System Interface
The following are the kinds of system interfaces available with the R61509V. The interface operation is
selected by setting the IM2/1/0 pins. The system interface is used for instruction setting and RAM access.
Table 57 IM Bit Settings and System Interface
IM2
IM1
IM0
Interfacing Mode with Host Processor
DB Pins
Colors
0
0
0
80-system 18-bit interface
DB17-0
262,144
0
0
1
80-system 9-bit interface
DB17-9
262,144
0
1
0
80-system 16-bit interface
DB17-10, DB8-1
262,144
*see Note1
0
1
1
80-system 8-bit interface
DB17-10
262,144
*see Note2
1
0
*
Clock synchronous serial interface
-
65,536
1
1
0
Setting inhibited
-
-
1
1
1
Setting inhibited
-
-
Notes: 1. 65,536 colors in 16-bit single transfer mode.
2. 262,144 colors is 8-bit 3-transfer mode. 65,536 colors in 8-bit 2-transfer mode.
Rev. 0.11 April 25, 2008, page 99 of 181
R61509V
Target Spec
80-System 18-bit Bus Interface
IM[2:0] = 000
CSn
CSX
A1
RS
HOST
HWR
PROCESSOR
R61509V
WRX
(RDX)
(RDX)
DB17-0
D31-0
18
Figure 14 18-bit Interface
Instruction write
Input
DB
17
DB
16
DB
15
DB
14
DB
13
DB
12
DB
11
DB
10
Instruction
IB
15
IB
14
IB
13
IB
12
IB
11
IB
10
IB
9
IB
8
DB
9
DB
8
DB
7
DB
6
DB
5
DB
4
DB
3
DB
2
DB
1
IB
7
IB
6
IB
5
IB
4
IB
3
IB
2
IB
1
IB
0
IB
7
IB
6
IB
5
IB
4
IB
3
IB
2
IB
1
IB
0
DB
8
DB
7
DB
6
DB
5
DB
4
DB
3
DB
2
DB
1
DB
0
Instruction code
Device code read / Instruction read
Device code
IB
15
IB
14
IB
13
IB
12
IB
11
IB
10
IB
9
IB
8
Output
DB
17
DB
16
DB
15
DB
14
DB
13
DB
12
DB
11
DB
10
DB
9
DB
0
Instruction code
Figure 15 18-bit Interface Data Format (Instruction Write / Device Code Read / Instruction Read)
RAM data write
Input
DB
17
DB
16
DB
15
DB
14
DB
13
DB
12
DB
11
DB
10
DB
9
DB
8
DB
7
DB
6
DB
5
DB
4
DB
3
DB
2
DB
1
DB
0
GRAM write
data
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
1 pixel
Note: Normal display in 262,144 colors.
RAM data read
GRAM data
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
Read data
RD
[17]
RD
[16]
RD
[15]
RD
[14]
RD
[13]
RD
[12]
RD
[11]
RD
[10]
RD
[9]
RD
[8]
RD
[7]
RD
[6]
RD
[5]
RD
[4]
RD
[3]
RD
[2]
RD
[1]
RD
[0]
Output pins
DB
17
DB
16
DB
15
DB
14
DB
13
DB
12
DB
11
DB
10
DB
9
DB
8
DB
7
DB
6
DB
5
DB
4
DB
3
DB
2
DB
1
DB
0
Figure 16 18-bit Interface Data Format (RAM Data Write / RAM Data Read)
Rev. 0.11 April 25, 2008, page 100 of 181
R61509V
Target Spec
80-System 16-bit Bus Interface
IM[2:0] = 010
CSn
CS:
A1
RS
HOST
HWR
PROCESSOR
R61509V
WR:
(RD:)
(RD:)
DB17-10, 8-1
D15-0
16
Figure 17 16-bit Interface
Instruction
Input
DB
17
DB
16
DB
15
DB
14
DB
13
DB
12
DB
11
DB
10
DB
8
DB
7
DB
6
DB
5
DB
4
DB
3
DB
2
DB
1
Instruction
IB
15
IB
14
IB
13
IB
12
IB
11
IB
10
IB
9
IB
8
IB
7
IB
6
IB
5
IB
4
IB
3
IB
2
IB
1
IB
0
Instruction code
Device code read / Instruction read
Device code
IB
15
IB
14
IB
13
IB
12
IB
11
IB
10
IB
9
IB
8
Output
DB
17
DB
16
DB
15
DB
14
DB
13
DB
12
DB
11
DB
10
DB
9
IB
7
IB
6
IB
5
IB
4
IB
3
IB
2
IB
1
IB
0
DB
8
DB
7
DB
6
DB
5
DB
4
DB
3
DB
2
DB
1
Instruction code
DB
0
Note: Device code cannot be read in 2 transfer mode.
Figure 18 16-bit Interface Data Format (Instruction Write / Device Code Read / Instruction Read)
Rev. 0.11 April 25, 2008, page 101 of 181
R61509V
Target Spec
RAM data write (1-transfer mode: TRI = 0) (EPE=2'h0)
Input
DB
17
DB
16
DB
15
DB
14
DB
13
DB
12
DB
11
DB
10
R5
R4
R3
R2
R1
R0
G5
G4
G3
DB
8
DB
7
DB
6
DB
5
DB
4
DB
3
DB
2
DB
1
G2
G1
G0
B5
B4
B3
B2
B1
1 pixel
B0
Note: 65,536 colors are available.
RAM data write (2-transfer mode: TRI = 0, DFM = 0)
First transfer
Second transfer
Input
pins
DB
17
DB
16
DB
15
DB
14
DB
13
DB
12
DB
11
DB
10
DB
8
DB
7
DB
6
DB
5
DB
4
DB
3
DB
2
DB
1
DB
17
DB
16
GRAM
write data
WD
[17]
WD
[16]
WD
[15]
WD
[14]
WD
[13]
WD
[12]
WD
[11]
WD
[10]
WD
[9]
WD
[8]
WD
[7]
WD
[6]
WD
[5]
WD
[4]
WD
[3]
WD
[2]
WD
[1]
WD
[0]
RGB
assignment
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
1 pixel
Note: Normal display in 262,144 colors.
RAM data write (2-transfer mode: TRI = 1, DFM = 1)
First transfer
Second transfer
DB
DB
DB
10
8
7
Input pins
DB
2
DB
1
DB
17
DB
16
DB
15
DB
14
DB
13
DB
12
DB
11
GRAM write
data
WD
[17]
WD
[16]
WD
[15]
WD
[14]
WD
[13]
WD
[12]
WD
[11]
WD
[10]
WD
[9]
WD
[8]
WD
[7]
RGB
assignment
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
DB
6
DB
5
DB
4
DB
3
DB
2
DB
1
WD
[6]
WD
[5]
WD
[4]
WD
[3]
WD
[2]
WD
[1]
WD
[0]
G0
B5
B4
B3
B2
B1
B0
1 pixel
Note: Normal display in 262,144 colors.
Figure 19 16-bit Interface Data Format (RAM Data Write)
RAM data read (1-transfer mode: TRI = 0)
GRAM data
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
Read data
RD
[17]
RD
[16]
RD
[15]
RD
[14]
RD
[13]
RD
[12]
RD
[11]
RD
[10]
RD
[9]
RD
[8]
RD
[7]
RD
[6]
RD
[5]
RD
[4]
RD
[3]
RD
[2]
RD
[1]
RD
[0]
Output pins
DB
17
DB
16
DB
15
DB
14
DB
13
DB
12
DB
11
DB
10
DB
8
DB
7
DB
6
DB
5
DB
4
DB
3
DB
2
DB
1
Note: RAM data cannot be read in 2-transfer mode.
Figure 20 16-bit Interface Data Format (RAM Data Read)
Rev. 0.11 April 25, 2008, page 102 of 181
R61509V
Target Spec
Data Transfer Synchronization in 16-bit Bus Interface Operation
The R61509V supports data transfer synchronization function to reset the counters for upper 16-/2-bit and
lower 2-/16-bit transfers in 16-bit 2-transfer mode. When a mismatch occurs in upper and lower data
transfers due to noise and so on, the 000H instruction is written four times consecutively to reset the upper
and lower counters in order to restart the data transfer from upper 2/16 bits. The data transfer
synchronization, when executed periodically, can help the display system recover from runaway.
Make sure to execute data transfer synchronization after reset operation before transferring instruction.
RS
RDX
WRX
DB17 ~ DB10,
DB8 ~ DB1
Upper
Lower
"000"H
"000"H
"000"H
"000"H
Upper
Lower
Upper
(16-bit transfer synchronization)
Figure 21 16-bit Data Transfer Synchronization
Rev. 0.11 April 25, 2008, page 103 of 181
R61509V
Target Spec
80-System 9-bit Bus Interface
When transferring 16-bit instruction, it is divided into upper and lower 8 bits, and the upper 8 bits are
transferred first (the LSB is not used). The RAM write data is also divided into upper and lower 9 bits, and
the upper 9 bits are transferred first. The unused DB pins must be fixed at either IOVCC or IOGND level.
When transferring the index register setting, make sure to write upper byte (8 bits).
IM[2:0] = 001
CSn
CS:
A1
RS
HOST
HWR
PROCESSOR
WR:
(RDX)
R61509V
(RD:)
DB17-9
DB8-0
D15-0
9
9
Figure 22 9-bit Interface
Instruction write
First transfer
Second transfer
Input
DB
17
DB
16
DB
15
DB
14
DB
13
DB
12
DB
11
DB
10
Instruction
IB
15
IB
14
IB
13
IB
12
IB
11
IB
10
IB
9
IB
8
DB
9
DB
17
DB
16
DB
15
DB
14
DB
13
DB
12
DB
11
DB
10
IB
7
IB
6
IB
5
IB
4
IB
3
IB
2
IB
1
IB
0
IB
7
IB
6
IB
5
IB
4
IB
3
IB
2
IB
1
IB
0
DB
17
DB
16
DB
15
DB
14
DB
11
DB
10
DB
9
Instruction code
Device code read / Instruction read
Instruction
IB
15
IB
14
IB
13
IB
12
Output
DB
17
DB
16
DB
15
DB
14
IB
11
IB
10
IB
9
IB
8
DB
11
DB
10
First transfer
DB
13
DB
12
Second transfer
DB
9
DB
13
DB
12
DB
9
instruction code
Figure 23 9-bit Interface Data Format (Instruction Write / Device Code Read / Instruction Read)
Rev. 0.11 April 25, 2008, page 104 of 181
R61509V
Target Spec
RAM data write
Second transfer
First transfer
Input
GRAM write
data
DB
17
DB
16
DB
15
DB
14
DB
13
DB
12
DB
11
DB
10
DB
9
DB
17
DB
6
DB
5
DB
14
DB
13
DB
12
DB
11
DB
10
DB
9
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
1 pixel
Note: Normal display in 262,144 colors.
RAM read data
GRAM data
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
Read data
RD
[17]
RD
[16]
RD
[15]
RD
[14]
RD
[13]
RD
[12]
RD
[11]
RD
[10]
RD
[9]
RD
[8]
RD
[7]
RD
[6]
RD
[5]
RD
[4]
RD
[3]
RD
[2]
RD
[1]
RD
[0]
Output pins
DB
17
DB
16
DB
15
DB
14
DB
DB
13
12
First transfer
DB
11
DB
10
DB
9
DB
17
DB
16
DB
15
DB
DB
DB
14
13
12
Second transfer
DB
11
DB
10
DB
9
Figure 24 9-bit Interface Data Format (RAM Data Write/ RAM Data Read)
Data Transfer Synchronization in 9-bit Bus Interface Operation
The R61509V supports data transfer synchronization function to reset the counters for upper and lower 9bit transfers in 9-bit bus transfer mode. When a mismatch occurs in upper and lower data transfers due to
noise and so on, the 00H instruction is written four times consecutively to reset the upper and lower
counters in order to restart the data transfer from upper 9 bits. The data transfer synchronization, when
executed periodically, can help the display system recover from runaway.
Make sure to execute data transfer synchronization after reset operation before transferring instruction.
RS
RDX
WRX
DB17 ~ DB9
Upper
Lower
"00"H
"00"H
"00"H
"00"H
Upper
Lower
Upper
(9-bit transfer synchronization)
Figure 25 9-bit Data Transfer Synchronization
Rev. 0.11 April 25, 2008, page 105 of 181
R61509V
Target Spec
80-System 8-bit Bus Interface
When transferring 16-bit instruction, it is divided into upper and lower 8 bits, and the upper 8 bits are
transferred first. The RAM write data is also divided into upper and lower 8 bits, and the upper 8 bits are
transferred first. The RAM write data is expanded into 18 bits internally as shown below. The unused DB
pins must be fixed at either IOVCC1 or GND level. When transferring the index register setting, make sure
to write upper byte (8 bits).
IM[2:0] = 001
CSn
CSX
A1
RS
HOST
HWR
PROCESSOR
R61509V
WRX
(RDX
(RDX
DB17-10
DB9-0
D15-0
8
10
Figure 26 8-bit Interface
Instruction write
Second transfer
First transfer
Input
DB
17
DB
16
DB
15
DB
14
DB
13
DB
12
DB
11
DB
10
DB
17
DB
16
DB
15
DB
14
DB
13
DB
12
DB
11
DB
10
Instruction
IB
15
IB
14
IB
13
IB
12
IB
11
IB
10
IB
9
IB
8
IB
7
IB
6
IB
5
IB
4
IB
3
IB
2
IB
1
IB
0
Instruction code
Device code read / Instruction read
Instruction
IB
15
IB
14
IB
13
Input
DB
17
DB
16
DB
15
IB
12
IB
11
IB
10
IB
9
IB
8
IB
7
IB
6
IB
5
IB
4
DB
12
DB
11
DB
10
DB
17
DB
16
DB
15
DB
14
First transfer
DB
14
DB
13
IB
3
IB
2
IB
1
IB
0
DB
11
DB
10
Second transfer
DB
13
DB
12
Note: Device code canot be read out in 3 transfer mode.
Figure 27 8-bit Interface Data Format (Instruction Write / Device Code Read / Instruction Read)
Note: RAM data cannot be read in the 3-transfer mode.
Rev. 0.11 April 25, 2008, page 106 of 181
R61509V
Target Spec
RAM data write (2-transfer mode: TRI = 0)
Second transfer
First transfer
Input
DB
17
DB
16
DB
15
DB
14
DB
13
DB
12
DB
11
DB
10
R5
R4
R3
R2
R1
R0
G5
G4
G3
DB
17
DB
16
DB
15
DB
14
DB
13
DB
12
DB
11
DB
10
G2
G1
G0
B5
B4
B3
B2
B1
1 pixel
B0
Note: Normal display in 65,536 colors.
RAM data write (3-transfer mode: TRI = 1, DFM = 1)
First transfer
Input
GRAM write
data
Third transfer
Second transfer
DB
17
DB
16
DB
15
DB
14
DB
13
DB
12
DB
17
DB
16
DB
15
DB
14
DB
13
DB
12
DB
17
DB
16
DB
15
DB
14
DB
13
DB
12
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
1 pixel
Note: Normal display in 262,144 colors.
Figure 28 8-bit Interface Data Format (RAM Data Write)
RAM data read
GRAM data
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
Read data
RD
[17]
RD
[16]
RD
[15]
RD
[14]
RD
[13]
RD
[12]
RD
[11]
RD
[10]
RD
[9]
RD
[8]
RD
[7]
RD
[6]
RD
[5]
RD
[4]
RD
[3]
RD
[2]
RD
[1]
RD
[0]
Output pins
DB
17
DB
16
DB
15
DB
14
DB
DB
13
12
First transfer
DB
11
DB
10
DB
17
DB
16
DB
15
DB
DB
DB
14
13
12
Second transfer
DB
11
DB
10
Note: RAM data cannot be read in 3-transfer mode.
Figure 29 8-bit Interface Data Format (RAM Data Read)
Rev. 0.11 April 25, 2008, page 107 of 181
R61509V
Target Spec
Data Transfer Synchronization in 8-bit Bus Interface operation
The R61509V supports data transfer synchronization function to reset the counters for upper and lower 8bit transfers in 8-bit bus transfer mode. When a mismatch occurs in upper and lower data transfers due to
noise and so on, the 00H instruction is written four times consecutively to reset the upper and lower
counters in order to restart the data transfer from upper 8 bits. The data transfer synchronization, when
executed periodically, can help the display system recover from runaway.
Make sure to execute data transfer synchronization after reset operation before transferring instruction.
RS
RDX
WRX
DB17 ~ DB10
Upper
Lower
"00"H
"00"H
"00"H
"00"H
Upper
Lower
Upper
(8-bit transfer synchronization)
Figure 30 8-bit Data Transfer Synchronization
Rev. 0.11 April 25, 2008, page 108 of 181
R61509V
Target Spec
Serial Interface
The serial interface is selected by setting the IM2/1 pins to the IOVCC/GND levels, respectively. The data
is transferred via chip select line (CS), serial transfer clock line (SCL), serial data input line (SDI), and
serial data output line (SDO). In serial interface operation, the IM0_ID pin functions as the ID pin, and the
DB17-0 pins, not used in this mode, must be fixed at either IOVCC or GND level.
The R61509V recognizes the start of data transfer on the falling edge of CSX input and starts transferring
the start byte. It recognizes the end of data transfer on the rising edge of CSX input. The R61509V is
selected when the 6-bit chip address in the start byte transferred from the transmission unit and the 6-bit
device identification code assigned to the R61509V are compared and both 6-bit data match. Then, the
R61509V starts taking in subsequent data. The least significant bit of the device identification code is
determined by setting the ID pin. Send "01110” to the five upper bits of the device identification code.
Two different chip addresses must be assigned to the R61509V because the seventh bit of the start byte is
register select bit (RS). When RS = 0, index register write operation is executed. When RS = 1, either
instruction write operation or RAM read/write operation is executed. The eighth bit of the start byte is R/W
bit, which selects either read or write operation. The R61509V receives data when the R/W = 0, and
transfers data when the R/W = 1.
When writing data to the GRAM via serial interface, the data is written to the GRAM after it is transferred
in two bytes. The R61509V writes data to the GRAM in units of 18 bits by adding the same bits as the
MSBs to the LSB of R and B dot data.
After receiving the start byte, the R61509V starts transferring or receiving data in units of bytes. The
R61509V transfers data from the MSB. The R61509V’s instruction consists of 16 bits and it is executed
inside the R61509V after it is transferred in two bytes (16 bits: DB15-0) from the MSB. The R61509V
expands RAM write data into 18 bits when writing them to the internal GRAM. The first byte received by
the R61509V following the start byte is recognized as the upper eight bits of instruction and the second
byte is recognized as the lower 8 bits of instruction.
When reading data from the GRAM, valid data is not transferred to the data bus until first five bytes of data
are read from the GRAM following the start byte. The R61509V sends valid data to the data bus when it
reads the sixth and subsequent byte data.
Table 58 Start Byte Format
Transferred Bits
Start byte format
S
Transfer start
1
1
The ID bit is determined by setting the IM0_ID pin.
Table 59 Functions of RS, R/W Bits
RS
R/W
Function
0
0
Set index register
0
1
Setting inhibited
1
0
Write instruction or RAM data
1
1
Read instruction or RAM data
Rev. 0.11 April 25, 2008, page 109 of 181
3
4
5
6
Device ID code
0
Note:
2
1
1
0
ID
7
8
RS
R/W
R61509V
Target Spec
Instruction
Input
D
15
D
14
D
13
Instruction
IB
15
IB
14
IB
13
First transfer (upper)
D
D
D
D9
12
11
10
IB
12
IB
11
IB
10
IB
9
Sec on d t ransfer (lower)
D8
D7
D6
D5
D4
D3
D2
D1
D0
IB
8
IB
7
IB
6
IB
5
IB
4
IB
3
IB
2
IB
1
IB
0
D
7
D
6
Sec on d t ransfer (lower)
D
D
D
D
D
1
5
4
3
2
D
0
G2
G1
G0
B1
Instruction code
RAM data write
Input
D
15
D
14
D
13
GRAM write data
R5
R4
R3
First tran sfer (upper)
D
D
D
12
11
10
R2
R1
R0
D
9
D
8
G5
G4
G3
1 pixel
Figure 31 Serial Interface Data Format
Rev. 0.11 April 25, 2008, page 110 of 181
B5
B4
B3
B2
B5
Note: 65,536-color display in SPI
R61509V
Target Spec
(a) Clock synchronization serial data transfer (basic mode)
End of transfer
Transfer start
CSX
input
1
2
3
4
5
6
7
“0”
“1”
“1”
“1”
“0”
ID
RS
SCL
input
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
D9
D8
D7
D6
D5
D4
D3
D2
D1
LSB
MSB
SDI
input
Device ID code
24
RW D15 D14 D13 D12 D11 D10
D0
RS RW
Start byte
Set IR (index register), instruction, write RAM data
SDO
output
D15 D14 D13 D12 D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Read instruction, RAM data
(b) Clock synchronization serial consecutive data transfer
CSX
input
SCL
input
SDI
input
Start byte
Instruction (1)
Upper 8 bits
Instruction (1)
Lower 8 bits
Instruction (2)
Upper 8 bits
Instruction (2)
Lower 8 bits
End
Start Note: The eight bits read after start byte input is recognized
as the upper byte of instruction.
Instruction
execution time (1)
(c) RAM read data transfer
CSX
input
SCL
input
Start byte
RS = 1
R/W = 1
SDI
input
SDO
output
Dummy read Dummy read Dummy read Dummy read Dummy read RAM read
Upper 8 bits
5
1
2
3
4
Start
RAM read
Lower 8 bits
Note: Valid data is not sent until the R61509V reads five bytes from the GRAM after start byte input .
The R61509V sends valid data when it reads the sixth and subsequent bytes.
(d) Instruction read
CSX
input
SCL
input
Start byte
RS=0
R/W=1
SDI
input
Instruction read
Lower 8 bits
SDO
output
Instruction read
Upper 8 bits
Instruction read
Lower 8 bits
End
Start
Note: Valid RAM data is read out right after the start byte.
Figure 32 Data Transfer in Serial Interface
Rev. 0.11 April 25, 2008, page 111 of 181
End
R61509V
Target Spec
VSYNC Interface
The R61509V supports VSYNC interface, which enables displaying a moving picture via system interface
by synchronizing the display operation with the VSYNCX signal. VSYNC interface can realize moving
picture display with minimum modification to the conventional system operation.
VSYNCX
CSX
HOST
PROCESSOR
RS
R61509V
WRX
DB17-0, 8-1
16
Figure 33 VSYNC Interface
The VSYNC interface is selected by setting DM1-0 = 10 and RM = 0. In VSYNC interface operation, the
internal display operation is synchronized with the VSYNCX signal. By writing data to the internal RAM
at faster than the calculated minimum speed (internal display operation speed + margin), it becomes
possible to rewrite the moving picture data without flickering the display and display a moving picture via
system interface.
The display operation is performed in synchronization with the internal clock signal generated from the
internal oscillator and the VSYNCX signal. The display data is written in the internal RAM so that the
R61509V rewrites the data only within the moving picture area and minimize the number of data transfer
required for moving picture display.
VSYNCX
RAM data
write via
system interface
Display operation
synchronized with
internal clock
Figure 34 Moving Picture Data Transfers via VSYNC Interface
Rev. 0.11 April 25, 2008, page 112 of 181
R61509V
Target Spec
The VSYNC interface has the minimum for RAM data write speed and internal clock frequency, which
must be more than the values calculated from the following formulas, respectively.
Internal clock frequency (fosc) [Hz]
= FrameFrequency × ( DisplayLin es( NL ) + FrontPorch( FP ) + BackPorch( BP )) × 23( clocks ) × var iance
240 × DisplayLines( NL )
RAMWriteSpeed (min .)[ Hz ] >
( BackPorch( BP ) + DisplayLines( NL ) − m arg ins ) × 23( clocks ) ×
1
fosc
Note: When RAM write operation is not started right after the falling edge of VSYNCX, the time from
the falling edge of VSYNCX until the start of RAM write operation must also be taken into account.
An example of calculating minimum RAM writing speed and internal clock frequency in VSYNC interface
operation is as follows.
[Example]
Panel size
Total number of lines (NL)
Back/front porch
Frame frequency
Internal clock frequency
240 RGB × 432 lines (NL = 6’h35: 432 lines)
432 lines
14/2 lines (BP = 4h’E, FP = 4’h2)
60 Hz
678 kHz
Internal clock frequency (fosc) [Hz]
= 678 kHz × 1.07 / 1.0 = 726 kHz
Notes: 1. When setting the internal clock frequency, possible causes of fluctuation must also be taken into
consideration. In this example, the internal clock frequency allows for a margin of ±7% for
variances and guarantee that display operation is completed within one VSYNCX cycle.
2. This example includes variances attributed to LSI fabrication process and room temperature.
Other possible causes of variances, such as differences in voltage change are not considered in
this example. It is necessary to include a margin for these factors.
Minimum speed for RAM writing [Hz]
> 240 × 432 / {((14 + 432 - 2) lines × 23 clocks) × 1/726 kHz} = 7.4 MHz
Notes: 1. In this example, it is assumed that the R61509V starts writing data in the internal RAM on the
falling edge of VSYNCX.
2. There must be at least a margin of 2 lines between the line to which the R61509V has just
written data and the line where display operation on the LCD is performed.
In this example, the RAM write operation at a speed of 7.4 MHz or more, which starts on the falling edge
of VSYNCX, guarantees the completion of data write operation in a certain line address before the
R61509V starts the display operation of the data written in that line and can write moving picture data
without causing flicker on the display.
Rev. 0.11 April 25, 2008, page 113 of 181
R61509V
Target Spec
RAM
write
VSYNCX
Back porch
(14 lines)
RC oscillation
±7%
[line]
Display
operation
432
Line processing
FP = 2H
Main panel
Moving picture
display
(432 lines)
RAM write
7.4 MHz
Display
operation
16.67 [ms]
0
Front porch (2 lines)
(60 Hz)
BP = 14H
VSYNCX
Blank period
Figure 35 Write/Display Operation Timing via VSYNC Interface
Notes to VSYNC Interface Operation
1.
The above example of calculation gives a theoretical value. Possible causes of variances of internal
oscillator should be taken into consideration. Make enough margins in setting RAM write speed for
VSYNC interface operation.
2.
The above example shows the values when writing over the full screen. Extra margin will be created if
the moving picture display area is smaller than that.
RAM
write
Back porch (14 lines)
RC oscillation
±7%
[line]
432
Display
operation
FP = 2H
(16 lines)
376
Line processing
Base image
Moving picture
display
(360 lines)
(56 lines)
RAM write
7.4MHz
16
0
Front porch (2 lines)
BP = 14H
VSYNCX
VSYNC
Figure 36 RAM Write Speed Margins
Rev. 0.11 April 25, 2008, page 114 of 181
Display
operation
[ms]
16.67
(60 Hz)
R61509V
Target Spec
3.
The front porch period continues from the end of one frame period to the next VSYNCX input.
4.
The instructions to switch from internal clock operation (DM1-0 = 00) to VSYNC interface operation
modes and vice versa are enabled from the next frame period.
5.
The partial display and vertical scroll functions are not available in VSYNC interface operation.
6.
In VSYNC interface operation, set AM = 0 to transfer display data correctly.
Internal Clock Operation to VSYNC Interface
VSYNC Interface to Internal Clock Operation
Internal clock operation
VSYNC interface operation
AM = 0
RAM address set
Set DM1-0 = 01 and RM = 0
for VSYNC interface
Display operation in
synchronization with
internal clocks
*Instruction setting for
the RGB interface operation
is enebled from the next frame period.
Set internal clock
operation mode*
(DM1-0 = 00 and RM = 0)
Wait one frame period
or more
Internal clock operation
Display operation in
synchronization with
VSYNCX
*Instruction setting to the
internal clock operation
is enebled from the next
frame period.
Display operation in
synchronization with
internal clocks
Set index register to R202h
Note: Continue VSYNC interface signals at least for
one frame period after setting DM1-0, RM bits
to internal clock operation.
Wait one frame period
or more
Write data to RAM
via VSYNC interface
Display operation in
synchronization with VSYNCX
Operation via VSYNC interface
Internal clock synchronous
operation mode setting
(DM[1:0]=00, RM=0)
Wait one frame period
or more
Internal clock operation
Note: Input the VSYNC interface signals before setting the DM1-0 and RM bits
to the VSYNC interface operation.
Figure 37 Sequences to Switch between VSYNC and Internal Clock Operation Modes
Rev. 0.11 April 25, 2008, page 115 of 181
R61509V
Target Spec
FMARK Interface
In the FMARK interface operation, data is written to internal RAM via system interface synchronizing with
the frame mark signal (FMARK), realizing tearing less video image while using conventional system
interface. FMARK output position is set in units of line using FMP bit. Set the bit considering data transfer
speed.
FMARK
HOST
PROCESSOR
CSX
RS
R61509V
WRX
DB17-10, 8-1
16
Figure 38 FMARK Interface
In this operation, moving picture display is enabled via system interface by writing data at higher than the
internal display operation frequency to a certain degree, which guarantees rewriting the moving picture
RAM area without causing flicker on the display.
The data is written in the internal RAM. Therefore, when moving picture is displayed, data is written only
to the moving picture display area without using RGB or VSYNC interface, minimizing number of data
transfer required for moving picture display.
㩷
㩷FMARK
㩷
㩷
RAM data
㩷write via
㩷system interface
㩷Display operation
㩷synchronized with
internal clock
㩷
Figure 39 Moving Picture Data Transfers via FMARK Function
Rev. 0.11 April 25, 2008, page 116 of 181
R61509V
Target Spec
When transferring data in synchronization with FMARK signal, minimum RAM data write speed and
internal clock frequency must be taken into consideration. They must be more than the values calculated
from the following equations.
Internal clock frequency (fosc) [Hz]
= FrameFrequency × ( DisplayLin es( NL ) + FrontPorch( FP ) + BackPorch( BP )) × 23( clocks ) × var iance
240 × DisplayLin es( NL )
RAMWriteSp eed (min .)[ Hz ] >
( FrontPorch ( FP ) + BackPorch ( BP ) + DisplayLin es( NL ) − m arg ins ) × 16 ( clocks ) ×
1
fosc
Note: When RAM write operation is not started immediately following the rising edge of FMARK, the
time from the rising edge of FMARK until the start of RAM write operation must also be taken into
account.
Examples of calculating minimum RAM data write speed and internal clock frequency is as follows.
[Example]
Panel size
Total number of lines (NL)
Back/front porch
Frame marker position (FMP)
Frame frequency
Internal oscillation frequency
240 RGB × 432 lines (NL = 6’h35: 432 lines)
432 lines
14/2 lines (BP = 4h’E, FP = 4’h2)
Display end line: 432nd line (FMP = 9’h1BF)
60 Hz
678kHz
Internal oscillation frequency (fosc) [Hz] = 678kHz × 1.07 / 1.0 = 726 kHz
(variance is taken into account)
Notes: 1.When setting the internal clock frequency, possible causes of fluctuation must also be taken into
consideration. In this example, the internal clock frequency allows for a margin of ±7% for
variances and guarantee that display operation is completed within one FMARK cycle.
2.This example includes variances attributed to LSI fabrication process and room temperature.
Other possible causes of variances, such as differences in external resistors and voltage change
are not considered in this example. It is necessary to include a margin for these factors.
Minimum speed for RAM writing [Hz]
> 240 × 320 / {((2+14 + 320 – 2) lines × 16 clocks) × 1/726 kHz} = 7.4 MHz
Notes: 1. In this example, it is assumed that the R61509V starts writing data in the internal RAM on the
rising edge of FMARK.
2.There must be at least a margin of 2 lines between the line to which the R61509V has just written
data and the line where display operation on the LCD is performed.
3.The FMARK signal output position is set to the line specified by FMP[8:0] bits.
In this example, RAM write operation at a speed of 7.4MHz or more, when starting on the rising edge of
FMARK, guarantees the completion of data write operation in a certain line address before the R61509V
Rev. 0.11 April 25, 2008, page 117 of 181
R61509V
Target Spec
starts the display operation of the data written in that line and can write moving picture data without
causing flicker on the display.
RAM
write
Back porch (14 lines)
RC oscillation
7%
[line]
432
Front porch (2 lines)
Display
operation
RAM write
7.4MHz
Line processing
FMARK
Main panel
Moving picture
display
(432 lines)
Display
operation
0
FP+BP=16H
[ms]
16.67
(60Hz)
FMARK
Front porch (2 lines)
Back porch (14 lines)
Figure 40
Note to display operation synchronous data transfer using FMARK signal
The above example of calculation gives a theoretical value. Possible causes of variances of internal
oscillator should be taken into consideration. Make enough margin in setting RAM write speed for
this operation.
FMP bit setting
The microcomputer detects FMARK signal outputted at the position defined by FMP bit. The R61509V
outputs an FMARK pulse when the R61509V is driving the line specified by FMP bits. The FMARK
signal can be used as a trigger signal to write display data in synchronization with display operation by
detecting the address where data is read out for display operation.
The FMARK output interval is set by FMI bits. Set FMI bits in accordance with display data rewrite cycle
and data transfer rate.
Rev. 0.11 April 25, 2008, page 118 of 181
R61509V
Target Spec
Table 60
Table 61
FMP[8:0]
FMARK output position
FMI[2]
FMI[1]
FMI[0]
FMARK Output interval
9’h000
0
0
0
0
9’h001
1st line
One frame period
0
0
1
2nd line
2 frame periods
9’h002
0
1
1
4 frame periods
1
0
1
:
9’h1BD
445th line
9’h1BE
446th line
9’h1BF
447 line
9’h1C0 ~ 1FF
Setting disabled
th
Rev. 0.11 April 25, 2008, page 119 of 181
Other setting
6 frame periods
Setting disabled
R61509V
Target Spec
FMP Setting Example
FMARK output position
FMP=9’h008
FMP=9’h008
NL=6’h35 (432 lines)
FP=4’h8
BP=4’h8
VL=8’h00
Line address
0 (1st line)
1 (2nd line)
2 (3rd line)
3 (4th line)
4 (5th line)
5 (6th line)
6 (7th line)
7 (8th line)
8 (1st line)
9 (2nd line)
10 (3rd line)
Base image
Back porch
RAM physical line address
AD[16:8]=9’h000
AD[16:8]=9’h001
AD[16:8]=9’h002
Display area
NL=6'h35
439 (432nd line)
440 (1st line)
441 (2nd line)
442 (3rd line)
443 (4th line)
444 (5th line)
445 (6th line)
446 (7th line)
447 (8th line)
AD[16:8]=9’h13F
Front porch
Figure 41
Rev. 0.11 April 25, 2008, page 120 of 181
R61509V
Target Spec
RGB Interface
The R61509V supports the RGB interface. The interface format is set by RM[1:0] bits. The internal RAM
is accessible via RGB interface.
Table 62 RGB interface
RIM
0
1
Note:
RGB Interface
DB Pin
18-bit RGB interface
DB17-0
16-bit RGB interface
Using multiple interface at a time is prohibited.
DB17-13, DB11-1
RGB Interface
The display operation via RGB interface is synchronized with VSYNCX, HSYNCX, and DOTCLK. The
data can be written only within the specified area with low power consumption by using window address
function. In RGB interface operation, front and back porch periods must be made before and after the
display period. When RGB interface is used, instructions should be transferred via clock synchronous serial
interface. RGB and 80-system bus interfaces cannot be used simultaneously.
VSYNCX ENABLE (V)
Back porch period (BP)
Moving picture
display area
Display period (NL)
Front porch period (FP)
HSYNCX
DOTCLK
ENABLE (H)
DB17-0
VSYNCX: Frame synchronization signal
HSYNCX: Line synchronization signal
DOTCLK: Dot clock
ENABLE: Data enable signal
DB 17-0: RGB (6:6:6) display data
Back porch period (BPP):
Front porch period (FPP):
Display period:
The number of lines for one frame:
14H ҈ BP ҈ 2H
14H ҈ FP ҈ 2H
FP + BP ҇ 16H
NL ҇ 432H
FP + NL + BP
Notes: 1. The front porch period continues until next VSYNCX input is detected.
2. Make sure to match the VSYNCX, HSYNCX, and DOTCLK frequencies to the resolution of liquid crystal panel.
Figure 42 Display Operation via RGB Interface
Rev. 0.11 April 25, 2008, page 121 of 181
R61509V
Target Spec
Polarities of VSYNCX, HSYNCX, ENABLE, and DOTCLK Signals
The polarities of VSYNCX, HSYNCX, ENABLE, and DOTCLK signals can be changed by setting the
DPL, EPL, HSPL, and VSPL bits, respectively for convenience of system configuration.
㪟㫊㫐㫅㪺 㪟㪙㪧
㪟㪘㪻㫉
㪟㪝㪧
㪭㫊㫐㫅㪺
㪙㪧
㪭㪙㪧
㪭㪘㪻㫉
Valid data period
㪭㪝㪧
㪝㪧
Figure 43
Table 63
Parameters
Symbols
Min.
Typ.
Max.
Step
Unit
Horizontal Synchronization
Hsync
2
10
16
1
DOTCLKCYC
Horizontal Back Porch
HBP
2
20
24
1
DOTCLKCYC
Horizontal Address
HAdr
－
240
－
1
DOTCLKCYC
Horizontal Front Porch
HFP
2
10
16
1
DOTCLKCYC
Vertical Synchronization
Vsync
1
2
4
1
Line
Vertical Back Porch
VBP
1
2
－
1
Line
Vertical Address
VAdr
－
432
－
1
Line
Vertical Front Porch
VFP
3
4
－
1
Line
Note:
The values of typ. are based on the following conditions; the panel resolution is QVGA (240 ×
432), the clock frequency is 7.39MHz, and the frame frequency is about 60Hz.)
Vsync + VBP = BP. VFP = FP. Vadr = NL.
(Number of clocks per 1H) ≥ (Number of RTN clocks) × (1/1 div.) × (PCDIVL + PCDIVH)
The setting example is shown in the following page.
Rev. 0.11 April 25, 2008, page 122 of 181
R61509V
Target Spec
Setting Example of Display Control Clock in RGB Interface Operation
Register
The display operation via DPI is performed in synchronization with the internal clock (PCLKD) that is
generated by dividing PCLK frequency.
PCDIVH[3:0]: When PCLKD is High, the number of clocks is set in unit of 1 clock.
PCDIVL[3:0]: When PCLKD is Low, the number of clocks is set in unit of 1 clock.
PCDIVH and PCDIVL (division ratio setting registers) should be set so that the difference between
PCLKD frequency and the internal oscillation clock (678kHz) is minimized.
Set PCDIVL to PCDIVH or PCDIVH − 1.
Make sure (number of PCLK frequency) ≥ (number of RTN clocks) ∗ (division ratio of DIV) ∗ (PCDIVH +
PCDIVL)
Setting example (frame frequency: 60Hz)
Internal clock:
PCLK:
Internal oscillation clock = 678kHz
1/1 Div. = (DIVE[2:0] = 2’b0)
HFP = 10 clocks
FP = 8’h8, BP = 8’h8, NL = 6B (432 lines)
Æ 59.35Hz
Hsync = 10 clocks
HBP = 20 clocks
HFP = 10 clocks
60Hz × (8+432+8) lines (10+20+240+10) clocks = 7.53MHz
PCLK frequency = 7.53MHz
7.53MHz/678kHz = 11.11 (Set PCDIVH and PCDIVL so that PCLK frequency is divided into
11.)
7.53/11 = 685kHz
685kHz / 25 clocks / 448 lines = 61.2Hz
PCDIVH = 4’h6
PCDIVL = 4’h5
㪧㪚㪛㪠㪭㪟㪔㪋㩾㪿㪍
㪧㪚㪛㪠㪭㪣㪔㪋㩾㪿㪌
㪧㪚㪣㪢
㪧㪚㪛㪠㪭㪟
㪧㪚㪛㪠㪭㪣
Internal clock
㪧㪚㪣㪢㪛
㪟㪪㪰㪥㪚
Figure 44
Rev. 0.11 April 25, 2008, page 123 of 181
R61509V
Target Spec
RGB Interface Timing
The timing relationship of signals in RGB interface operation is as follows.
16-/18-Bit RGB Interface Timing
One frame
Back porch period
Front porch period
VSYNCX
HSYNCX
DOTCLK
ENABLE
DB17-0
1H or more
VSYNCX
1H
HLW ҈ 1CLK
HSYNCX
1 clock
DOTCLK
DTST ҈ 1CLK
ENABLE
DB17-0
Valid data
Figure 45
Note: VLW:
HLW:
DTST:
VSYNCX Low period
HSYNCX Low period
data transfer setup time
Rev. 0.11 April 25, 2008, page 124 of 181
R61509V
Target Spec
Moving Picture Display via RGB Interface
The R61509V supports RGB interface for moving picture display and incorporates RAM for storing
display data, which provides the following advantages in displaying a moving picture.
1.
2.
3.
4.
The window address function enables transferring data only within the moving picture area
It becomes possible to transfer only the data written over the moving picture area
By reducing data transfer, it can contribute to lowering the power consumption of the whole system
The data in still picture area (icons etc.) can be written over via system interface while displaying a
moving picture via RGB interface
RAM access via system interface in RGB interface operation
The R61509V allows RAM access via system interface in RGB interface operation. In RGB interface
operation, data is written to the internal RAM in synchronization with DOTCLK while ENABLE is “Low”.
When writing data to the RAM via system interface, set ENABLE “High” to stop writing data via RGB
interface. Then set RM = “0” to enable RAM access via system interface. When reverting to the RGB
interface operation, wait for the read/write bus cycle time. Then, set RM = “1” and the index register to
R22h to start accessing RAM via RGB interface. If there is a conflict between RAM accesses via two
interfaces, there is no guarantee that the data is written in the RAM.
The following is an example of rewriting still picture data via system interface while displaying a moving
picture via RGB interface.
updating frame data
updating frame data
VSYNCX
ENABLE
DOTCLK
DB17-0
Note 3)
Note 3)
System
interface
Index
R22
RM = 0
RAM
address
set
Index
R22
writing
moving picture area
Notes:
Update data in the
area other than
moving picture area
RAM
address
set
RM = 1
Index
R22
writing
moving picture area
writing
still picture area
1. In RGB interface operation, RAM address AD16-0 is set in the address counter on the falling edge of VSYNCX.
2. Set AD16-0 bits and the index R22h before starting RAM access via RGB interface.
3. When switching to the system interface operation after writing data via RGB interface, wait at least one write cycle (tcycw).
6/25 00:
6/2
00:00
00
Moving picture
area
6/25 00:
6/2
00:00
00
Moving picture
area
Figure 46 Updating the Still Picture Area while Displaying Moving Picture
Rev. 0.11 April 25, 2008, page 125 of 181
R61509V
Target Spec
16-Bit RGB Interface
The 16-bit RGB interface is selected by setting RIM = 1. The display operation is synchronized with
VSYNCX, HSYNCX, and DOTCLK signals. The display data is transferred to the internal RAM in
synchronization with the display operation via 16-bit ports while data enable signal (ENABLE) allows
RAM access via RGB interface.
Instruction bits can be transferred only via system interface.
RIM = 1
VSYNCX
HSYNCX
HOST
PROCESSOR
DOTCLK
R61509V
ENABLE
DB17-13, 11-1
16
DB12,0
2
Data format for the16-bit interface (RIM = 1)
Input
GRAM data
DB
17
R5
DB
16
R4
DB
15
DB
14
DB
13
R3
R2
R1
R0
DB
11
DB
10
DB
9
DB
8
G5
G4
G3
G2
1 pixel
DB
7
G1
DB
6
G0
DB
5
B5
DB
4
B4
DB
3
B3
B2
DB
1
B1
B0
Note: 65,536-color display
Figure 47 Example of 16-Bit RGB Interface and Data Format
Rev. 0.11 April 25, 2008, page 126 of 181
DB
2
R61509V
Target Spec
18-bit RGB Interface
The 18-bit RGB interface is selected by setting RIM = 0. The display operation is synchronized with
VSYNCX, HSYNCX, and DOTCLK signals. The display data is transferred to the internal RAM in
synchronization with the display operation via 18-bit ports (DB17-0) while data enable signal (ENABLE)
allows RAM access via RGB interface.
Instruction bits can be transferred only via system interface.
RIM = 0
VSYNCX
HSYNCX
DOTCLK
HOST
PROCESSOR
R61509V
ENABLE
DB17-0
18
Data format for the 18-bit interface (RIM = 0)
Input
DB
17
DB
16
DB
15
DB
14
DB
13
DB
12
DB
11
DB
10
GRAM write
data
R5
R4
R3
R2
R1
R0
G5
G4
DB
9
DB
8
DB
7
DB
6
DB
5
DB
4
DB
3
DB
2
DB
1
DB
0
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
1 pixel
Note: Normal display in 262,144 colors
Figure 48 Example of 18-Bit RGB Interface and Data Format
Rev. 0.11 April 25, 2008, page 127 of 181
R61509V
Target Spec
Notes to RGB Interface Operation
1. The following functions are not available in RGB interface operation.
Table 64 Functions Not Available in RGB Interface operation
Function
RGB Interface
Internal Display Operation
Partial display
Not available
Available
Scroll function
Not available
Available
2. The VSYNCX, HSYNCX, and DOTCLK signals must be supplied during display period.
3. The reference clock to generate liquid crystal panel controlling signals in RGB interface operation is
DOTCLK, not the internal clock generated from the internal oscillator.
4. When switching between the internal operation mode and the external display interface operation mode,
follow the sequences below in setting instruction.
5. In RGB interface operation, front porch period continues after the end of frame period until next
VSYNCX input is detected.
6. RGB and 80-system bus interfaces cannot be used simultaneously.
7. In RGB interface operation, RAM address AD16-0 is set in the address counter every frame on the
falling edge of VSYNCX.
Internal Clock Operation to RGB Interface (1)
RGB Interface (1) to Internal Clock Operation
Internal clock operation
RGB interface operation
Set internal clock
operation mode*
(DM1-0 = 00 and RM = 0)
AM = 0
RAM address set
Set DM1-0 = 01 and RM = 1
for RGB interface
Display operation in
synchronization with
internal clocks
Wait one frame period
or more
*Instruction setting for
the RGB interface operation
is enebled from the next frame period.
Internal clock operation
Set index register to R202h
*Instruction setting to the
internal clock operation
is enebled from the next
frame period.
Display operation in
synchronization with
internal clocks
Note: Continue RGB interface signals at least for
one frame period after setting DM1-0, RM bits
to internal clock operation.
Wait one frame period
or more
Write data to RAM
via RGB interface
Display operation in
synchronization with
VSYNCX, HSYNCX, and
DOTCLK
Display operation in
synchronization with VSYNCX,
HSYNCX, and DOTCLK
Operation via RGB interface
Note: Input the RGB interface signals before setting the DM1-0 and RM bits
to the RGB interface operation.
Figure 49 RGB and Internal Clock Operation Mode Switching Sequences
Rev. 0.11 April 25, 2008, page 128 of 181
R61509V
Target Spec
RAM Address and Display Position on the Panel
The R61509V has memory to store display data of 240RGB x 432 lines. The R61509V incorporates a
circuit to control partial display, which allows switching driving method between full-screen display mode
and partial display mode.
The R61509V makes display arrangement setting and panel driving position control setting separately and
specifies RAM area for each image displayed on the panel.
The following is the sequence of setting full-screen and partial display.
1.
2.
3.
Set (PTSA, PTEA) to specify the RAM area for each partial image
Set the display position of each partial image on the base image by setting PTDP.
Set NL to specify the number of lines to drive the liquid crystal panel to display the base
image
After display ON, set display enable bits (BASEE, PTDE) to display respective images
4.
BASEE = 1, PTDE = 0
BASEE = 0, PTDE = 1
Normal display
Partial display
5.
Changes BASEE, PTDE settings when turning on and off the full and partial displays 1/2.
In driving the liquid crystal panel, the clock signal for gate line scan is supplied consecutively via interface
in accordance with the number of lines to drive the liquid crystal panel (NL setting).
When switching the display position in horizontal direction, set SS bit when writing RAM data.
Table 65
Display ENABLE
Numbers of lines
RAM area
Base image
Note:
BASEE
NL
(VSA, VEA)
The base image is displayed from the first line of the screen.
Table 66
Display ENABLE
Partial image
PTDE
Rev. 0.11 April 25, 2008, page 129 of 181
Display position
PTDP
RAM area
(PTSA, PTEA)
R61509V
Target Spec
Display data
output position
Panel display
position
Base image
RAM address
Partial image
RAM address
1
RAM write
address
(HSA,HEA)
9’h000
Partial
image
PTSA0
PTDP
Scan
direction
䇼LCD䇽
PTEA0
Base
image
Window
Address
(VSA,VEA)
NL
9’h1AF
Figure 50 RAM Address, Display Position and Drive Position
Restrictions in Setting Display Control Instruction
There are restrictions in coordinates setting for display data, display position and partial display.
Screen setting
In setting the number of lines to drive the liquid crystal panel, make sure that the total number of lines is
432 lines or less (NL ≤ 432 lines).
Base image display
The base image is displayed from the first line of the screen: Base image display start position = 1st line
Rev. 0.11 April 25, 2008, page 130 of 181
R61509V
Target Spec
The following figure shows the relationship among the RAM address, display position, and the lines driven
for the display.
LCD panel
physical line address
Display
data output
order
0
RAM line address
Display screen
0 (1st line)
1 (2nd line)
2 (3rd line)
1
2
3
4
5
9’h000
PTDP
Partial image
Display area
Base image 1
RAM area
NL
( n line)
NL
n-1
NL
PTSA
Partial image
RAM area
PTEA
9’h1AF
Figure 51 Display RAM Address and Panel Display Position
Note: This figure shows the relationship between RAM line address and the display position on the panel.
In the R61509V’s internal operation, the data is written in the RAM area specified by the window
address setting.
Rev. 0.11 April 25, 2008, page 131 of 181
R61509V
Target Spec
Instruction Setting Example
The followings are examples of settings for 240(RGB) x 432(lines) panel.
1.
Full screen display (no partial display)
The following is an example of settings for full screen display.
Table 67
Base image display instruction
BASEE
1
NL[5:0]
6’h35
PTDE
0
Display
data output
order
LCD panel
physical line address
0 (1st line)
1 (2nd line)
2 (3rd line)
1
2
3
4
5
NL
(432 lines)
RAM line address
BSA=9'h000
9’h000
Base image
BASE image
RAM area
432
431 (432nd line)
BEA = 9’h1AF
Figure 52 Full Screen Display (no Partial)
Rev. 0.11 April 25, 2008, page 132 of 181
R61509V
2.
Target Spec
Partial only
The following is an example of settings for displaying partial image 1 only and turning off the base image.
The partial image 1 is displayed at the position specified by PTDP0 bit.
Table 68
Base image display instruction
BASEE
0
NL[5:0]
6’h35
partial image 1 display instruction
PTDE
1
PTSA[8:0]
9’h000
PTEA[8:0]
9’h00F
PTDP[8:0]
9’h080
Display
data output
order
LCD panel
physical line address
1
2
3
4
5
RAM line address
PTSA=9’000
0 (1st line)
1 (2nd line)
2 (3rd line)
Partial image
RAM area
PTEA=9’00F
PTDP
Partial image
display area
NL
(432 linrs)
432
Base image
RAM area
Base image
(non-lit display)
431 (432nd line)
Figure 53 Partial Display
Rev. 0.11 April 25, 2008, page 133 of 181
9’h1AF
R61509V
Target Spec
Window Address Function
The window address function enables writing display data consecutively in a rectangular area (a window
address area) made in the internal RAM. The window address area is described by the horizontal address
register (start: HSA7-0, end: HEA7-0 bits) and the vertical address register (start: VSA8-0, end: VEA8-0
bits). The AM and ID bits set the transition direction of RAM address (either increment or decrement,
horizontal or vertical, respectively). Setting these bits enables the R61509V to write data including image
data consecutively without taking the data wrap position into account.
The window address area must be made within the GRAM address map area. Also, the AD16-0 bits (RAM
address set register) must be set to an address within the window address area.
[Window address area setting range]
(Horizontal direction)
(Vertical direction)
[RAM Address setting range]
(RAM address)
8’h00 ≤ HSA ≤ HEA ≤ 8’hEF
9’h000 ≤ VSA ≤ VEA ≤ 9’h1AF
HSA ≤ AD7-0 ≤ HEA
VSA ≤ AD16-8 ≤ VEA
GRAM address map
17'h00000
17'h000EF
Window address area
17'h02010
17'h02110
17'h0202F
17'h05F10
17'h05F2F
17'h0212F
17'h1AF00
17'h1AFEF
Window address area
HSA = 8'h10, HEA = 8'h2F
VSA = 9'h020, VEA = 9'h05F
ID = 2'h3 (increment)
AM = 1'h0 (horizontal writing)
ORG = 0 RAM address set = 17'02010 (arbitrary)
ORG = 1 RAM address set = 17'00000
Both are set to the same RAM address.
Figure 54 Automatic Address Update within a Window Address Area
Rev. 0.11 April 25, 2008, page 134 of 181
R61509V
Target Spec
Scan Mode Setting
The R61509V can set the gate pin assignment and the scan direction in the following 4 different ways by
setting SM and GS bits to realize various connections between the R61509V and the LCD panel.
Scan direction
SM
Interchanging backward direction (GS=1)
Interchanging forward direction (GS=0)
431
429
432
430
2
4
1
3
main
Panel
main
Panel
432
(GS)
(GS)
0
429
176
431
240
430
4
432
2
176
240
3
1
R61509V
R61509V
(Non-bump view)
(Non-bump view)
Scan order (Gate line No.)
Scan order (Gate line No.)
G1ЈG2ЈG3ЈG4.... G429ЈG430ЈG431ЈG432
G432ЈG431ЈG430ЈG3429.... G4ЈG3ЈG2ЈG1
Left/right forward direction (GS=0)
Left/right backward direction (GS=1)
1
2
215
216
432
431
main
Panel
432
(GS)
218
217
217
main
Panel
432
(GS)
218
216
215
1
240
431
432
240
R61509V
2
1
R61509V
(Non-bump view)
(Non-bump view)
Scan order (Gate line No.)
Scan order (Gate line No.)
G1ЈG3.... G429ЈG431Ј G2ЈG4....
G430ЈG432
G432ЈG430 .... G4ЈG2ЈG431ЈG429 ....
G3ЈG1
Note: the numbers in the circles in the figure shows the order of scan.
Figure 55
Rev. 0.11 April 25, 2008, page 135 of 181
R61509V
Target Spec
8-Color Display Mode
The R61509V has a function to display in eight colors. In this display mode, only V0 and V63 are used
and power supplies to other grayscales (V1 to V62) are turned off to reduce power consumption.
In 8-color display mode, the γ-adjustment registers R300 to R309 are disabled and the power supplies to V1
to V62 are halted. The R61509V does not require GRAM data rewrite for 8-color display by writing the
MSB to the rest in each dot data to display in 8 colors.
GRAM
MSB
Display data
LS B
R5 R4 R3 R2 R1 R0
G5 G4 G3 G2 G1 G0
B5 B4 B3 B2 B1 B0
Grayscale amplifier
V0
R5
2-level grayscale
control
2
V63
LCD driver
G5
2-level grayscale
control
LCD driver
B5
2-level grayscale
control
LCD driver
R G B
LCD
Figure 56 8-Color Display Mode
Rev. 0.11 April 25, 2008, page 136 of 181
R61509V
Target Spec
Frame-Frequency Adjustment Function
The R61509V supports a function to adjust frame frequency. The frame frequency for driving liquid
crystal can be adjusted by setting the DIVI, RTNI bits without changing the oscillation frequency.
By changing the DIVI and RTNI settings, the R61509V can operate at high frame frequency when
displaying a moving picture, which requires the R61509V to rewrite data in high speed, and it can operate
at low frame frequency when displaying a still picture.
Relationship between Liquid Crystal Drive Duty and Frame Frequency
The following equation represent the relationship between liquid crystal drive duty and frame frequency.
The frame frequency can be changed by setting the 1H period adjustment bit (RTNI) and the operation
clock frequency division ratio setting bit (DIVI).
Equation for calculating frame frequency
FrameFrequency =
fosc
[ Hz ]
NumberofClocks / line × DivisionRatio × ( Line + FP + BP)
fosc: RC oscillation frequency
Number of clocks per line: RTNI bit
Division ratio: DIVI bit
Line: number of lines to drive the LCD panel (NL bit)
Number of lines for front porch: FP
Number of lines for back porch: BP
Example of Calculation: when maximum frame frequency = 60 Hz
fosc: 678 kHz
Number of lines: 432 lines
1H period: 25 clock cycles (RTNI [4:0] = “11001”)
Division ratio of operating clock: 1/1
Front porch: 2 lines
Back porch: 14 lines
fFLM = 678 (kHz) / 25 (clocks) × 1/1 × (432+2+14) (lines) ≒ 60.5 (Hz)
Rev. 0.11 April 25, 2008, page 137 of 181
R61509V
Target Spec
Under the above conditions, the frame frequency can be changed according to the table shown below.
Table 69 Frame Frequency Setting (NL = 432 lines, BP = 14 lines, FP = 2 lines, fosc = 678 kHz)
RTNI[4:0]
DIVI = 2’h0
DIVI = 2’h1
5’h00 - 5’h0F
-
-
5’h10
95 Hz
47 Hz
5’h11
89 Hz
45 Hz
5’h12
84 Hz
42 Hz
5’h13
80 Hz
40 Hz
5’h14
76 Hz
38 Hz
5’h15
72 Hz
36 Hz
5’h16
69 Hz
34 Hz
5’h17
66 Hz
33 Hz
5’h18
63 Hz
32 Hz
5’h19
61 Hz
30 Hz
5’h1A
58 Hz
29 Hz
5’h1B
56 Hz
28 Hz
5’h1C
54 Hz
27 Hz
5’h1D
52 Hz
26 Hz
5’h1E
50 Hz
25 Hz
5’h1F
49 Hz
24 Hz
Rev. 0.11 April 25, 2008, page 138 of 181
R61509V
Target Spec
Partial Display Function
The partial display function allows the R61509V to drive lines selectively to display partial images by
setting partial display control registers. The lines not used for displaying partial images are driven at nonlit display level to reduce power consumption.
The power efficiency can be enhanced in combination with 8-color display mode. Check the display
quality when using low power consumption functions.
Non-lit display area
G41
Partial image:
20 lines
G60
Non-lit display area
Number of lines to drive LCD: NL = 6’h35 (432 lines)
Base image display enable:
BASEE = 0
Partial image display RAM area: (PTSA, PTEA) = (9’h000, 9’h013)
Partial image display position: PTDP = 9’h028
Partial image display enable:
PTDE = 1
Figure 57 Partial Display
Note: See the RAM Address and Display Position on the Panel for details on the relationship between the
display positions of partial images and respective RAM area setting.
Rev. 0.11 April 25, 2008, page 139 of 181
R61509V
Target Spec
Liquid Crystal Panel Interface Timing
The relationships between RGB interface signals and liquid crystal panel control signals in internal
operation and RGB interface operations are as follows.
Internal Clock Operation
One Frame
reference
point
reference
point
reference
point
reference
point
reference
point
reference
point
1H
FMARK
(FMP=BP-1)
NOWI
G1
G2
G432
SDTI
S(3n+1)
S(3n+2)
S(3n+3)
SDTI
R,G,B
R,G,B
R,G,B
n=0to239
First line
Second line
VCOM
Figure 58
Rev. 0.11 April 25, 2008, page 140 of 181
432nd line
reference
point
reference
point
R61509V
Target Spec
RGB Interface Operation
One frame
BP
FP
VSYNCX
1H
HSYNCX
DOTCLK
ENABLE
DB
1
2
3
4
5
6
430
431
432
1
2
3
5DOTCLK See note
Reference
point
Reference
point
1H
FMARK
(FMP=BP-1)
NOWE
G1
G2
G3
G432
SDTE
S(3n+1)
S(3n+2)
S(3n+3)
RGB
RGB
RGB
432
n=0 to 239
432nd line
Third line
FIrst line
Second line
VCOM
Note: Transfer RGB data in one transfer via 16-bit port
Figure 59
Rev. 0.11 April 25, 2008, page 141 of 181
1
R61509V
Target Spec
γ Correction Function
γ Correction Function
The R61509V supports γ-correction function to make the optimal colors according to the characteristics of
the panel. The R61509V has registers for positive and negative polarities.
γ Correction Circuit
The following figure shows the γ-correction circuit. According to the settings of variable resistors R0 to R8,
the voltage level, the difference between VREG1OUT and VGS, is evenly divided into 8 grayscale
reference voltages (V0, V1, V8, V20, V43, V55, V62, and V63). Other 56-grayscale voltages are
generated by setting the level at a certain interval between the reference voltages. For grayscale voltage,
see “Grayscale Voltage Calculation Formula”.
VREG1OUT
0~31R (1R)
R: Resistor outputting voltage evenly divided into 12
(1R): Trimming step
R0
㪭㪇
1~32R (1R)
R1
㪭㪈
2~33R (1R)
Interpolation
adjustment
R2
㪭㪏
4~19R (1R)
R3
㪭㪉㪇
8~23R (1R)
Linear
interpolation
R4
㪭㪋㪊
4~19R (1R)
R5
㪭㪌㪌
2~33R (1R)
R6
㪭㪍㪉
1~32R (1R)
Interpolation
adjustment
R7
㪭㪍㪊
2~33R (1R)
R8
VGS (=GND)
Figure 60
Rev. 0.11 April 25, 2008, page 142 of 181
R61509V
Target Spec
γ Correction Registers
The γ-correction registers include 42 bits for each of R, G, and B dots and 8-bit interpolation adjustment
registers.
Reference level adjustment registers
Table 70 Reference level adjustment registers
Resistor
Gamma Control
Positive
polarity
Negative
polarity
R0
PR0P00[4:0] PR0N00[4:0]
R1
PR0P01[4:0] PR0N01[4:0]
R2
PR0P02[4:0] PR0N02[4:0]
R3
PR0P03[3:0] PR0N03[3:0]
R4
PR0P04[3:0] PR0N04[3:0]
R5
PR0P05[3:0] PR0N05[3:0]
R6
PR0P06[4:0] PR0N06[4:0]
R7
PR0P07[4:0] PR0N07[4:0]
R8
PR0P08[4:0] PR0N08[4:0]
Rev. 0.11 April 25, 2008, page 143 of 181
R61509V
Target Spec
Table 71 Reference Level Adjustment Registers and Resistors
Resistor
R0
R1
R2
R3
R4
Register
Name
PR0*00[4:0]
PR0*01[4:0]
PR0*02[4:0]
PR0*03[3:0]
PR0*04[3:0]
Value
Resistance
Resistor
Register
Name
Valie
Resistance
5'h00
0R
4'h0
4R
5'h01
1R
4'h1
5R
5'h02
2R
4'h2
6R
5'h1F
31R
4'hF
19R
5'h00
1R
5'h00
2R
5'h01
2R
5'h01
3R
5'h02
3R
5'h02
4R
5'h1F
32R
5'h1F
33R
5'h00
2R
5'h00
1R
5'h01
3R
5'h01
2R
5'h02
4R
5'h02
3R
5'h1F
33R
5'h1F
32R
4'h0
4R
5'h00
2R
4'h1
5R
5'h01
3R
4'h2
6R
5'h02
4R
4'hF
19R
5'h1F
33R
4'h0
8R
4'h1
9R
4'h2
10R
4'hF
23R
Note: * indicates P / N.
Rev. 0.11 April 25, 2008, page 144 of 181
R5
R6
R7
R8
PR0*05[3:0]
PR0*06[4:0]
PR0*07[4:0]
PR0*08[4:0]
R61509V
Target Spec
Interpolation Registers
Table 72 Interpolation Registers
Gamma Control
Interpolation
adjustment
V2~V7
V56~V61
Positive
polarity
Negative
polarity
PI0P0[1:0]
PI0N0[1:0]
PI0P1[1:0]
PI0N1[1:0]
PI0P2[1:0]
PI0N2[1:0]
PI0P3[1:0]
PI0N3[1:0]
Table 73 Interpolation factor for V2 to V7
(See “Grayscale Voltage Calculation Formula” for IPV* level)
PI0*0[1:0]
2'h0
2'h1
2'h2
2'h3
PI0*1[1:0]
IPV2
IPV3
IPV4
IPV5
IPV6
IPV7
2'h0
81%
67%
52%
39%
26%
13%
2'h1
78%
61%
43%
33%
22%
11%
2'h2
73%
52%
31%
23%
15%
8%
2'h3
72%
50%
28%
21%
14%
7%
2'h0
80%
68%
56%
42%
28%
14%
2'h1
76%
62%
48%
36%
24%
12%
2'h2
70%
52%
35%
26%
17%
9%
2'h3
69%
50%
31%
23%
16%
8%
2'h0
78%
70%
61%
46%
30%
15%
2'h1
74%
63%
53%
39%
26%
13%
2'h2
66%
53%
39%
29%
20%
10%
2'h3
64%
50%
36%
27%
18%
9%
2'h0
78%
70%
63%
47%
31%
16%
2'h1
73%
64%
54%
41%
27%
14%
2'h2
65%
53%
41%
31%
20%
10%
2'h3
63%
50%
37%
28%
19%
9%
Rev. 0.11 April 25, 2008, page 145 of 181
R61509V
Target Spec
Table 74 Interpolation Factor for V56 to V61
PI0*3[1:0]
2'h0
2'h1
2'h2
2'h3
PI0*2[1:0]
IPV56
IPV57
IPV58
IPV59
IPV60
IPV61
2'h0
87%
74%
61%
48%
33%
19%
2'h1
89%
78%
67%
57%
39%
22%
2'h2
92%
85%
77%
69%
48%
27%
2'h3
93%
86%
79%
72%
50%
28%
2'h0
86%
72%
58%
44%
32%
20%
2'h1
88%
76%
64%
52%
38%
24%
2'h2
91%
83%
74%
65%
48%
30%
2'h3
92%
84%
77%
69%
50%
31%
2'h0
85%
70%
54%
39%
30%
22%
2'h1
87%
74%
61%
47%
37%
26%
2'h2
90%
80%
71%
61%
47%
34%
2'h3
91%
82%
73%
64%
50%
36%
2'h0
84%
69%
53%
38%
30%
22%
2'h1
86%
73%
59%
46%
36%
27%
2'h2
90%
80%
69%
59%
47%
35%
91%
81%
72%
63%
50%
37%
2'h3
Note: * indicates P/N.
Rev. 0.11 April 25, 2008, page 146 of 181
R61509V
Target Spec
Table 75 Grayscale Voltage Calculation Formula
Grayscale
voltage
Formula
Grayscale
voltage
Formula
V0
ΔV ｘ Σ（R1～R8)/SUMR
V32
V43 + (V20 - V43) x 11/23
V1
ΔV ｘ Σ（R2～R8)/SUMR
V33
V43 + (V20 - V43) x 10/23
V2
V8 + (V1 - V8) x IPV2
V34
V43 + (V20 - V43) x 9/23
V3
V8 + (V1 - V8) x IPV3
V35
V43 + (V20 - V43) x 8/23
V4
V8 + (V1 - V8) x IPV4
V36
V43 + (V20 - V43) x 7/23
V5
V8 + (V1 - V8) x IPV5
V37
V43 + (V20 - V43) x 6/23
V6
V8 + (V1 - V8) x IPV6
V38
V43 + (V20 - V43) x 5/23
V7
V8 + (V1 - V8) x IPV7
V39
V43 + (V20 - V43) x 4/23
V8
ΔV ｘ Σ（R3～R8)/SUMR
V40
V43 + (V20 - V43) x 3/23
V9
V20 + (V8 - V20) x 11/12
V41
V43 + (V20 - V43) x 2/23
V10
V20 + (V8 - V20) x 10/12
V42
V43 + (V20 - V43) x 1/23
V11
V20 + (V8 - V20) x 9/12
V43
ΔV ｘ Σ（R5～R8)/SUMR
V12
V20 + (V8 - V20) x 8/12
V44
V55 + (V43 - V55) x 11/12
V13
V20 + (V8 - V20) x 7/12
V45
V55 + (V43 - V55) x 10/12
V14
V20 + (V8 - V20) x 6/12
V46
V55 + (V43 - V55) x 9/12
V15
V20 + (V8 - V20) x 5/12
V47
V55 + (V43 - V55) x 8/12
V16
V20 + (V8 - V20) x 4/12
V48
V55 + (V43 - V55) x 7/12
V17
V20 + (V8 - V20) x 3/12
V49
V55 + (V43 - V55) x 6/12
V18
V20 + (V8 - V20) x 2/12
V50
V55 + (V43 - V55) x 5/12
V19
V20 + (V8 - V20) x 1/12
V51
V55 + (V43 - V55) x 4/12
V20
ΔV ｘ Σ（R4～R8)/SUMR
V52
V55 + (V43 - V55) x 3/12
V21
V43 + (V20 - V43) x 22/23
V53
V55 + (V43 - V55) x 2/12
V22
V43 + (V20 - V43) x 21/23
V54
V55 + (V43 - V55) x 1/12
V23
V43 + (V20 - V43) x 20/23
V55
ΔV ｘ Σ（R6～R8)/SUMR
V24
V43 + (V20 - V43) x 19/23
V56
V62 + (V55 - V62) x IPV56
V25
V43 + (V20 - V43) x 18/23
V57
V62 + (V55 - V62) x IPV57
V26
V43 + (V20 - V43) x 17/23
V58
V62 + (V55 - V62) x IPV58
V27
V43 + (V20 - V43) x 16/23
V59
V62 + (V55 - V62) x IPV59
V28
V43 + (V20 - V43) x 15/23
V60
V62 + (V55 - V62) x IPV60
V29
V43 + (V20 - V43) x 14/23
V61
V62 + (V55 - V62) x IPV61
V30
V43 + (V20 - V43) x 13/23
V62
ΔV ｘ (R7 + R8)/SUMR
V31
V43 + (V20 - V43) x 12/23
V63
ΔV ｘ R8/SUMR
Note:
Make sure that
ΔV = VREG1OUT – VGS
SUMR = Σ(R0～R8) ≥ 70R.
V63 ≥ 0.2V
Rev. 0.11 April 25, 2008, page 147 of 181
R61509V
Target Spec
Frame Memory Data and the Grayscale Voltage
Table 76
Grayscale Voltage
Frame memory
data
REV = 1
Grayscale Voltage
REV = 0
Frame memory
data
REV = 1
REV = 0
Positive
polarity
Negative
polarity
Positive
polarity
Negative
polarity
6'h20
V32
V31
V31
V32
V1
6'h21
V33
V30
V30
V33
V61
V2
6'h22
V34
V29
V29
V34
V60
V3
6'h23
V35
V28
V28
V35
V59
V59
V4
6'h24
V36
V27
V27
V36
V5
V58
V58
V5
6'h25
V37
V26
V26
V37
V6
V57
V57
V6
6'h26
V38
V25
V25
V38
6'h07
V7
V56
V56
V7
6'h27
V39
V24
V24
V39
6'h08
V8
V55
V55
V8
6'h28
V40
V23
V23
V40
6'h09
V9
V54
V54
V9
6'h29
V41
V22
V22
V41
6'h0A
V10
V53
V53
V10
6'h2A
V42
V21
V21
V42
6'h0B
V11
V52
V52
V11
6'h2B
V43
V20
V20
V43
Positive
polarity
Negative
polarity
Positive
polarity
Negative
polarity
6'h00
V0
V63
V63
V0
6'h01
V1
V62
V62
6'h02
V2
V61
6'h03
V3
V60
6'h04
V4
6'h05
6'h06
6'h0C
V12
V51
V51
V12
6'h2C
V44
V19
V19
V44
6'h0D
V13
V50
V50
V13
6'h2D
V45
V18
V18
V45
6'h0E
V14
V49
V49
V14
6'h2E
V46
V17
V17
V46
6'h0F
V15
V48
V48
V15
6'h2F
V47
V16
V16
V47
6'h10
V16
V47
V47
V16
6'h30
V48
V15
V15
V48
6'h11
V17
V46
V46
V17
6'h31
V49
V14
V14
V49
6'h12
V18
V45
V45
V18
6'h32
V50
V13
V13
V50
6'h13
V19
V44
V44
V19
6'h33
V51
V12
V12
V51
6'h14
V20
V43
V43
V20
6'h34
V52
V11
V11
V52
6'h15
V21
V42
V42
V21
6'h35
V53
V10
V10
V53
6'h16
V22
V41
V41
V22
6'h36
V54
V9
V9
V54
6'h17
V23
V40
V40
V23
6'h37
V55
V8
V8
V55
6'h18
V24
V39
V39
V24
6'h38
V56
V7
V7
V56
6'h19
V25
V38
V38
V25
6'h39
V57
V6
V6
V57
6'h1A
V26
V37
V37
V26
6'h3A
V58
V5
V5
V58
6'h1B
V27
V36
V36
V27
6'h3B
V59
V4
V4
V59
6'h1C
V28
V35
V35
V28
6'h3C
V60
V3
V3
V60
6'h1D
V29
V34
V34
V29
6'h3D
V61
V2
V2
V61
6'h1E
V30
V33
V33
V30
6'h3E
V62
V1
V1
V62
6'h1F
V31
V32
V32
V31
6'h3F
V63
V0
V0
V63
Rev. 0.11 April 25, 2008, page 148 of 181
R61509V
Target Spec
Power Supply Generating Circuit
The following figures show the configurations of liquid crystal drive voltage generating circuit of the
R61509V.
Power Supply Circuit Connection Example 1 (VCI1 = VCIOUT)
In the following example, the VCI1 level can be adjusted.
(1)
VREG1OUT
(2)
VREG1
ࠡࡘ࠲
㓏⺞㔚
↢ᚑ࿁〝
VCILVL
VCIOUT
ജ࿁〝
ౝㇱၮḰ
㔚↢ᚑ࿁〝
࠰ࠬ
࠼ࠗࡃ
VCOMR
(3)
VCI1
S1-720
VCOMH
(16)
C11M
(4)
VCOM
ജ࿁〝
C11P
C12M
(5)
࿁〝㧝
VCOM
(17)
VCOML
C12P
DDVDH
(6)
VCOM
ࡌ࡞⺞ᢛ࿁〝
R61509V
C13M
(7)
(11)
VGH
C13P
See note 2.
VGL
ࠥ࠻
࠼ࠗࡃ
G1-432
C21M
(8)
C21P
VCC
C22M
(9)
GND
C22P
࿁〝㧞
VCILVL
VCI
AGND
(10)
IOVCC
VGH
GND
(12)
VGL
(13)
See note 1.
VCL
(14)
VDD
(15)
Figure 61
Notes: 1. The wiring resistances between the schottky diode and GND/VGL must be 5Ω or less.
2. The wiring resistances between the schottky diode and DDVDH/VGH must be 5Ω or less.
Rev. 0.11 April 25, 2008, page 149 of 181
R61509V
Target Spec
Power Supply Circuit Connection Example 2 (VCI1 = VCI Direct Input)
In the following example, the electrical potential VCI is directly applied to VCI1. In this case, the
VCIOUT level cannot be adjusted internally but step-up operation becomes more effective. Make sure that
VCI≤ 3.0V.
(1)
VREG1OUT
(2)
VREG1
ࠡࡘ࠲
㓏⺞㔚
↢ᚑ࿁〝
VCILVL
VCIOUT
ജ࿁〝
ౝㇱၮḰ
㔚↢ᚑ࿁〝
࠰ࠬ
࠼ࠗࡃ
VCOMR
VCI1
VCI
S1-720
VCOMH
(16)
C11M
See note 3. (4)
VCOM
ജ࿁〝
C11P
C12M
(5)
࿁〝㧝
VCOM
(17)
VCOML
C12P
(6)
DDVDH
VCOM
ࡌ࡞⺞ᢛ࿁〝
R61509V
C13M
(7)
(11)
VGH
C13P
See note 2.
VGL
C21M
(8)
ࠥ࠻
࠼ࠗࡃ
G1-432
VCC
C21P
GND
C22M
(9)
C22P
࿁〝㧞
VCILVL
VCI
AGND
(10)
VGH
IOVCC
(12)
GND
VGL
(13)
See note 1.
VCL
(14)
VDD
(15)
Figure 62
Notes: 1. The wiring resistances between the schottky diode and GND/VGL must be 5Ω or less.
2. The wiring resistances between the schottky diode and DDVDH/VGH must be 5Ω or less.
3. When directly applying the VCI level to VCI1, set VC = 3’h7. Capacitor connection to VCIOUT is
not necessary.
Rev. 0.11 April 25, 2008, page 150 of 181
R61509V
Target Spec
Specifications of Power-supply Circuit External Elements
The specifications of external elements connected to the power-supply circuit of the R61509V are as
follows.
Table 77 Capacitor
Capacitance
1µF
(B characteristics)
Voltage proof
Pin Connection
6V
(1) VREG1OUT, (3) VCI1, (4) C11P, C11M, (5) C12P, C12M,
(7) C13P, C13M, (14) VCL, (16) VCOMH, (17) VCOML
10 V
(6) DDVDH, (8) C21P, C21M, (9) C22P, C22M
25 V
(10) VGH, (12) VGL
Table 78 Schottky Diode
Specification
Pin Connection
VF < 0.38 V/20 mA@25 °C, VR ≥ 25 V
(Recommended diode: HS*226)
(13) GND–VGL,
(11) DDVDH–VGH,
Table 79 Variable Resistor
Specification
Pin Connection
(2) VCOMR
> 200 kΩ
Table 80 Internal Logic Power Supply
Capacitance
1µF (B characteristics)
Voltage proof (recommended)
3V
Rev. 0.11 April 25, 2008, page 151 of 181
Pin Connection
(15) VDD
R61509V
Target Spec
Voltage Setting Pattern Diagram
The following are the diagrams of voltage generation in the R61509V and the TFT display application
voltage waveforms and electrical potential relationship.
VGH
BT
Internal reference
㩷
voltage (VCIR)
VRH
VCILVL(2.5~3.3V)
VCC(2.5~3.3V)
DDVDH
VREG1OUT
VC
VREG1OUT
BT
VCM/VCOMR
IOVCC(1.65~3.3V)
VCOMH
VCI1
VDV
GND(0V)
VCOML
VCL
BT
VGL
Figure 63
Notes: 1. The DDVDH, VGH, VGL, and VCL output voltages will become lower than their theoretical levels
(ideal voltages) due to current consumption at each output level. Make sure that output voltage
level in operation maintains the following relationships: (DDVDH – VREG1OUT) > 0.5V, (VCOML
– VCL) > 0.5V. Also make sure VGH-VGL ≤ 28V, VCI-VCL ≤ 6V. When the alternating cycle of
VCOM is high (e.g. polarity inverts every line cycle), current consumption will increase. In this
case, check the voltage before use.
2. In operation, setting voltages within the respective voltage ranges is recommended.
Rev. 0.11 April 25, 2008, page 152 of 181
R61509V
Target Spec
Liquid Crystal Application Voltage Waveform and Electrical Potential
VGH
VREG1OUT
VCOMH
VCOM
VCOML
Sn (source driver output)
Gn (panel interface output)
Figure 64
Rev. 0.11 April 25, 2008, page 153 of 181
R61509V
Target Spec
VCOMH and VREG1OUT Voltage Adjustment Sequence
When adjusting the VCOMH voltage by setting VCM[6:0] (R280h, internal VCOMH level adjustment
circuit), follow the sequence below.
The R61509V can retain permanently the VREG1OUT and VCOMH level adjustment setting values in
NVM.
To write data to NVM, see “NVM Control” and NVM Write Sequence”.
Display ON Sequence
㩷
VCOM level adjustment
R280h: VCM[6:0]
Set VCM[6:0] adjustment
value.
The display on the panel will
flicker when the VCOMH 㩷
level is adjusted internally.
Check the display
quality.
㩷
Complete the VCOMH level adjustment.
NVM (1)
㪠㫅㪻㪼㫏
㪈㪌
㪈㪋
㪭㪚㪤㩷
㪲㪍㪴
㪉㪏㪇㪿
㪈㪊
㪈㪉
㪈㪈
㪈㪇
㪐
㪏
㪎
㪍
㪌
㪋
㪊
㪭㪚㪤㩷
㪲㪌㪴
㪭㪚㪤
㪲㪋㪴
㪭㪚㪤㩷
㪲㪊㪴
㪭㪚㪤㩷
㪲㪉㪴
㪭㪚㪤
㪲㪈㪴
㪭㪚㪤
㪲㪇㪴
㪬㪠㪛
㪲㪎㪴
㪬㪠㪛
㪲㪍㪴
㪬㪠㪛
㪲㪌㪴
㪬㪠㪛
㪲㪋㪴
㪬㪠㪛
㪲㪊㪴
Set NVDAT[10:4] to the value set in 㩷the
VCM[6:0] after VCOMH level
adjustment. Then, write data to NVM.
㩷
㪉
㪬㪠㪛
㪲㪉㪴
㪈
㪇
㪬㪠㪛㩷
㪲㪈㪴
㪬㪠㪛㩷
㪲㪇㪴
Adjust VCOMH
level
㩷
Set NVDAT[3:0] to the value set 㩷in
UID[7:0]. Then, write data to NVM.
㩷
NVM Data Write Register
㪠㫅㪻㪼㫏
㪈㪌
㪈㪋
㪈㪊
㪈㪉
㪍㪝㪈㪿
㪥㪭㪛㪘㪫㩷
㪲㪈㪌㪴
㪥㪭㪛㪘㪫㩷
㪲㪈㪋㪴
㪥㪭㪛㪘㪫㩷
㪲㪈㪊㪴
㪥㪭㪛㪘㪫
㪲㪈㪉㪴
㪈㪈
㪈㪇
㪥㪭㪛㪘㪫㩷 㪥㪭㪛㪘㪫㩷
㪲㪈㪈㪴
㪲㪈㪇㪴
㪐
㪏
㪎
㪍
㪌
㪋
㪊
㪉
㪈
㪇
㪥㪭㪛㪘㪫
㪲㪐㪴
㪥㪭㪛㪘㪫
㪲㪏㪴
㪥㪭㪛㪘㪫
㪲㪎㪴
㪥㪭㪛㪘㪫
㪲㪍㪴
㪥㪭㪛㪘㪫
㪲㪌㪴
㪥㪭㪛㪘㪫
㪲㪋㪴
㪥㪭㪛㪘㪫
㪲㪊㪴
㪥㪭㪛㪘㪫
㪲㪉㪴
㪥㪭㪛㪘㪫㩷
㪲㪈㪴
㪥㪭㪛㪘㪫㩷
㪲㪇㪴
Set NVDAT[15] to 1.
Figure 65
Rev. 0.11 April 25, 2008, page 154 of 181
㩷 write data.
Set
㩷
R61509V
Target Spec
NVM Control
The R61509V incorporates 16-bit NVM for user’s use.
•
7 bits are for VCOM adjustment (VCM register value is stored).
•
8 bits are for UID.
•
1 bit is for a dummy bit.
To write, read and erase data from/to the NVM, follow the sequences below. Data on the NVM is loaded to
internal registers automatically when the sequences are performed.
•
Power On reset
•
Exit shutdown mode
Data stored in the NVM is retained permanently even if power supply is turned off.
Table 81
Operation mode
Power supply voltage (TBD)
Write
VPP1
VPP3A
Open or AGND
Erase
VPP1
9.2V±0.3V
VPP3A
-9.2V±0.3V
Remarks
Temperature
(TBD)
Write period:
150ms±50ms
-
+20°C~+30C°
Erase period:
10ms±1ms x n
time(s) (N ≤ 30, total
≤ 300ms)
Verify erase operation
at intervals of
10ms±1ms.
+20°C~+30C°
−40°C~+85C°
VPP3A
Open or AGND
NVM data rewrite (erase-write) operation should be performed up to 5 times per address.
Except
Write/Erase
Note:
9.2V±0.3V
Time (TBD)
VPP1
Open or AGND
Rev. 0.11 April 25, 2008, page 155 of 181
-
-
R61509V
Target Spec
NVM Load (Register Resetting) Sequence
Data on the NVM is loaded either automatically or by setting a command.
During the following sequence, the data written to the NVM is automatically loaded to the internal register.
Except for the shutdown mode
Index: 6F0h
Command: 16’h0040
TE = 1’b0
CALB = 1’b1
EOP[1:0] = 2’b00
Wait
1ms
or more
Index: 280h
VCM[6:0], UID[7:0]
NVM data read
Figure 66 NVM Load (Register Resetting) Sequence
Rev. 0.11 April 25, 2008, page 156 of 181
R61509V
Target Spec
NVM Write Sequence
Defined 16 bit data is written to the selected address. When “0” is written to these bits, the bits are set to
“0”. If the data is erased from the bit, the bit is returned to ”1”. The bit to which data is not written should
be set to “1”.
NVM Write Sequence
NVM Load (Register Resetting) Sequence
Power supply (VCC, VCI, IOVCC) ON
NVM load
6F0h:16’h0040
(CALB=1)
1msec
or more
1ms
or more
VPP1=9.2r0.3V
VPP3A/VPP3B=GND
GND
NVM load end
(Automatically CALB = 0)
1msec
or more
Power ON reset
2msec
or more
NVM data read
Transfer synchronization
RS=0, DB=16’h0000
RS=0, DB=16’h0000
RS=0, DB=16’h0000
RS=0, DB=16’h0000
R280h: VCM[6:0], UID[7:0]
Instruction read
NVM write data set
R6F1:16’h****
(NVDAT=16’hXX (arbitrary data))
NVM write setting
R6F0:16’h0010
(TE=0,CALB=0,EOP=2’h1)
NVM write start
R6F0:16’h0090
(TE=1,CALB=0,EOP=2’h1)
150msr50ms(TBD)
NVM write end
RA0: 16’h0000
(TE=0, EOP=2’h0,
NVAD=2’h0)
1us
or more
VPP1=9.2r0.3V
VPP3A =GND
GND
Figure 67 NVM Write Sequence
Rev. 0.11 April 25, 2008, page 157 of 181
R61509V
Target Spec
NVM Erase Sequence
The data written to the selected 16 bits is erased all together. The bits from which data is erased are set to
“1”. To erase data from NVM, make sure VGL < VPP3A, and follow the sequence below after power
supply ON sequence.
NVM Erase Sequence
Power supply ON sequence
㩷
㩷
NVM erase power supply
setting
㩷 and BT bits
To erase data from NVM, set the VC
㩷
as follows to make sure VGL < VPP3A < -9.5V.
(R100h): BT[2:0] = 3’h6 (VGL = -10.8V)
(R101h): VC[2:0] = 3’h7 (VCI = 2.7V)
NVM power supply ON
VPP1 = 9.2±0.3V
GND
1ms
or more㩷
Fix VPP3B to GND.
㩷
VPP3A = -9.2±0.3V 㩷 㩷
1ms or more
R6F0h:
TE=1, EOP[1:0]=2’h03
Start of rasing
Erase period
10ms±1ms
R6F2h:
NVVRF=0
R6F0h:
TE=0, EOP[1:0]=2’h00㩷
R6F2h:
NVVRF=1
㪩㪍㪝㪇㪿
End of erasing
Verify ON
㪚㪘㪣㪙㪔㪈
1ms or more
NVM power supply OFF
R280h: NVM data read
VPP1 = 9.2±0.3V
NO
NVM data read result:
15’h7FFF
GND
VPP3 = -9.2±0.3V
YES
NVVRF=0
R6F2h:
1ms
or more
Verify OFF
Power supply OFF
sequence
Figure 68 NVM Erase Sequence
Rev. 0.11 April 25, 2008, page 158 of 181
R61509V
Target Spec
Power Supply Setting Sequence
The following are the sequences for setting power supply ON/OFF instructions. Set power supply ON/OFF
instructions according to the following sequences in Display ON/OFF, Sleep set/exit sequences.
Power Supply ON Sequence
Power supply (VCC, VCI, IOVCC) ON
㪭㪚㪠
㪠㪦㪭㪚㪚
㪭㪚㪚
㪞㪥㪛
VCC → IOVCC → VCI
or VCC, IOVCC, VCI simultaneously
PON=1
R102h: PSON=1,
(1) Other mode setting instruction
(2) RAM write instruction,
etc.
Power ON reset
Power supply startup time
(6 frames x 1/osc)
1ms
or more
Automatic NVM data load
Access is prohibited
㩷
㩷
1ms after reset.
Transfer synchronization
RS=0, DB=16’h0000
RS=0, DB=16’h0000
RS=0, DB=16’h0000
RS=0, DB=16’h0000
(B) Liquid crystal
power supply
ON
(DCDC ON) state
Display OFF state
(A) Liquid crystal
power supply OFF
(DCDC OFF) state
㩷
Display OFF state
Display ON sequence
Instruction user setting
R400h:
NL[5:0]
R008h:
BP[7:0], FP[7:0]
R300h~R309h:
γ control
R010h:
RTNI[4:0], DIVI[1:0]
R100h:
BT[2:0], AP[1:0]
R101h:
VC[2:0], DC0[2:0], DC1[2:0]
Other user settings: see notes 1 and 2.
OR
NVM erase sequence
(1) To turn the display on, follow “Display ON Sequence”
in “Instruction Setting Sequence and Refresh Sequence”.
(2) To erase data from NVM, follow “NVM Erase Sequence”.
Erase data from NVM according to “NVM Control”.
Notes: 1. Set VCMR to 1 when using internal electric volume.
2. When NVM is in the status that the R61509V is shipped out, set the instruction register (R280h: VCM[6:0], and
UID[7:0]). If writing values to VCM[6:0] and UID[7:0] has been completed, setting this instruction register is
㩷
unnecessary.
Figure 69
Rev. 0.11 April 25, 2008, page 159 of 181
R61509V
Target Spec
Power Supply OFF Sequence
(B) Liquid crystal
power supply
ON
(DCDC ON) state
Display OFF state
ޣᶧ᥏㔚Ḯ
ࠝࡈࡈࡠ
R102h: PON=0 PSON=0
ޤ
5 frames or more
(A) Liquid crystal
power supply
OFF
(DCDC OFF)
Display OFF state
Power supply (VCC, VCI, IOVCC) OFF
VCI
IOVCC
VCC
㪞㪥㪛
VCI → IOVCC → VCC
or VCC, IOVCC, VCI simultaneously
Figure 70
Rev. 0.11 April 25, 2008, page 160 of 181
R61509V
Target Spec
Notes to Power Supply ON Sequence
When voltages do not rise in the order of VCC, IOVCC and then VCI and have to change the order, please
follow the following note.
Note
Internal operation of the R61509V is unstable until VCC rises. If IOVCC rose before VCC rises, the
R61509V may be in “output” status. In this case, do not send or receive any data before power supply is
completed.
Changing order of voltage input will not cause troubles such as latchup or destruction of the LSI.
Rev. 0.11 April 25, 2008, page 161 of 181
R61509V
Target Spec
Instruction Setting Sequence and Refresh Sequence
Display ON/OFF Sequences and Refresh Sequence
In setting instruction in the R61509V, follow the sequences below. To reduce malfunction caused by noise,
execute refresh sequence 1 regularly. To exit shutdown mode, execute refresh sequence 2.
Display ON sequence
Display OFF sequence
(B) Liquid crystal
power supply ON
(DCDC ON) state
㩷
Display OFF state
(C) Liquid crystal
power supply ON
(DCD ON) state
㩷
Display ON state
㩷
Display ON
R007h: BASEE=1
Display OFF
㩷
R007h: BASEE=0
(C) Liquid crystal
power supply ON
(DCD ON) state
Display ON state
(B) Liquid crystal
power supply ON
(DCDC ON) state
㩷
Display OFF state
Note: For power supply setting, see “Power Supply Setting Sequence”.
Refresh Sequence 1
Refresh Sequence 2
Transfer synchronization
RS=0, DB=16’h0000
RS=0, DB=16’h0000
RS=0, DB=16’h0000
RS=0, DB=16’h0000
Transfer synchronization
RS=0, DB=16’h0000
RS=0, DB=16’h0000
RS=0, DB=16’h0000
RS=0, DB=16’h0000
Test register initialization
㩷
R600h: TRSR=1
Test register initialization
㩷
R600h: TRSR=1
0.1ms
or more
NVM data load
㩷
R6F0h: CALB=1
0.3ms
or more
R600h: TRSR=0
All instruction initial setting
and user setting
R600h: TRSR=0
All instruction initial setting
and user setting
Except the following㩷 instructions:
R600h: TRSR
R6F0h: CALB
R6F1h: NVDAT[15:0]
Figure 71
Rev. 0.11 April 25, 2008, page 162 of 181
Except the following
㩷 instructions:
R600h: TRSR
R6F0h: CALB
R6F1h: NVDAT[15:0]
R61509V
Target Spec
Shutdown Mode Sequences
Shutdown Sequence (Exit shutdown mode by inputting CSX = “Low”)
㩷
18-/16-/9-/8-bit interface operation
Display OFF sequence
Set shutdown mode
Set shutdown mode
R100h: DSTB=1
CSX=”Low”(1)
CSX=”Low”(2)
VDD startup,
Oscillation startup period
1ms
or more
Exit shutdown mode
Input CSX = “Low” 6 times.
CSX=”Low” (3)
CSX=”Low” (4)
CSX=”Low” (5)
Initialize the
R61509V.
CSX=”Low” (6)
0.3ms
or more
Automatic NVM data load
User setting
Refresh sequence 2
NL, BP, FP, γ control,
RTNI, DIVI, and others
RAM data setting
Executing refresh sequence
regularly is recommended.
Display ON sequence
Notes: 1. See AC characteristics in Electrical Characteristics for details on low width (PWLW), high width (PWHW), and cycle (tCYCW) periods.
2. Leave at least 1 ms between the 2nd and 3rd inputs of CSX = Low in exiting shutdown mode.
WRX
“High” 㩷
RDX
“High” 㩷
RS
Data
2
1
CSX
Wait
1ms.
3
4
5
6
Don’t care
Don’t care
Don’t care
“Low” or “High”
Don’t care
Don’t care
Don’t care
Waveforms in Exiting Shutdown Mode (Input CSX="Low")
Figure 72
Rev. 0.11 April 25, 2008, page 163 of 181
㩷
Data and RS = Don’t
care
R61509V
Target Spec
Shutdown Sequence (Exit shutdown mode by inputting CSX = “Low” and WRX = “Low” (Index Write))
㩷 interface operation
(1) 18-/16-bit
Display OFF sequence
Set shutdown mode
Set shutdown mode
R100h: DSTB=1
Index Write (Data=16’h0000)
Index Write (Data=16’h0000)
VDD startup,
Oscillation startup period
1ms
or more
Exit shutdown mode
Index Write (Data=16’h0000)
Initialize the
R61509V.
Index Write (Data=16’h0000)
Index Write (Data=16’h0000)
Index Write (Data=16’h0000)
0.3ms
or more
Automatic NVM data load
User setting
Refresh sequence 2
NL, BP, FP, γ control,
RTNI, DIVI, and others
RAM data setting
Executing refresh sequence
regularly is recommended.
Display ON sequence
Notes: 1. See AC characteristics in Electrical Characteristics for details on low width (PWLW), high width (PWHW), and cycle (tCYCW) periods.
2. Leave 1 ms or more between the 2nd and 3rd inputs of Index Write.
1
CSX
2
Wait
1ms.
3
4
5
16’h0000
16’h0000
16’h0000
6
WRX
RDX
“High”
RS
“Low”
Data
16’h0000
16’h0000
Waveforms in Exiting Shutdown Mode (Input RS = “Low”and Index Write)
Figure 73
Rev. 0.11 April 25, 2008, page 164 of 181
16’h0000
R61509V
Target Spec
(2) 9-/8-bit interface operation
Display OFF sequence
Set shutdown mode
Set shutdown mode
R100h: DSTB=1
Index Write (Data=8’h00)
Index Write (Data=8’h00)
VDD startup,
Oscillation startup period
1ms
or more
Exit shutdown mode
Index Write (Data=8’h00)
Initialize the
R61509V.
Index Write (Data=8’h00)
Index Write (Data=8’h00)
Index Write (Data=8’hFF)
Index Write (Data=8’h00)
Index Write (Data=8’h00)
Transfer synchronization command (see note 3)
Index Write (Data=8’h00)
Index Write (Data=8’h00)
0.3ms
or more
Automatic NVM data load
User setting
Refresh sequence 2
NL, BP, FP, γ control,
RTNI, DIVI, and others
RAM data setting
Display ON sequence
Executing refresh sequence
regularly is recommended.
Notes: 1. See AC characteristics in Electrical Characteristics for details on low width (PWLW), high width (PWHW), and cycle (tCYCW) periods.
2. Leave at least 1 ms between the 2nd and 3rd Index write.
3. Set transfer synchronous command data 8'h00 when using 8 bit interface and 9'h000 when using 9-bit interface.
1
CSX
2
Wait
1ms.
3
5
4
6
1
2
3
4
WRX
RDX
RS
Data
“High” 㩷
“Low”㩷
Upper IW㩷 Lower IW
00h
00h
Upper IW Lower IW Upper IW Lower IW
00h
00h
00h
FFh
Upper IW㩷 Lower IW㩷 Upper IW㩷 Lower IW
00h
00h
00h 㩷
00h㩷
Execute transfer synchronization command by inputting RS = “Low” and Index Write after exiting shutdown mode.
Waveforms in Exiting Shutdown Mode (Input RS = “Low”and Index Write)
Figure 74
Rev. 0.11 April 25, 2008, page 165 of 181
Transfer synchronization
㩷
R61509V
Target Spec
8-Color Mode Setting
262,144 color to 8 color mode
8 color to 262,144 color mode
262,144-color mode
display
8-color mode display
R00Bh: COL=1
R00Bh: COL=0
8-color mode display
262,144-color mode
display
Figure 75
Partial Display Setting
Partial Display Setting Sequence
Full-screen display
Partial display setting
R500h: PTDP[8:0]
R501h: PTSA[8:0]
R502h: PTEA[8:0]
Base image display OFF
Partial display ON
R007h: BASEE=0, PTDE=1
8-color display, low power
consumption settings
R007h: COL=1,
R009h: PTS
Partial display
Base image display ON
Partial display OFF
R007h: BASEE=1, PTDE=0
Full-screen display
Figure 76
Rev. 0.11 April 25, 2008, page 166 of 181
Set as required
R61509V
Target Spec
Absolute Maximum Ratings
Table 82
Items
Symbol
Unit
Value
Note
Power supply voltage 1
VCC, IOVCC
V
-0.3 ~ +4.6
1, 2
Power supply voltage 2
VCI – AGND
V
-0.3 ~ +4.6
1, 3
Power supply voltage 3
DDVDH – AGND
V
-0.3 ~ +6.5
1, 4
Power supply voltage 4
AGND – VCL
V
-0.3 ~ +4.6
1
Power supply voltage 5
DDVDH – VCL
V
-0.3 ~ +9.0
1, 5
Power supply voltage 7
AGND– VGL
V
-0.3 ~ +13.0
1, 6
Power supply voltage 8
VGH – VGL
V
-0.3 ~ +30.0
1
1, 7
Power supply voltage 9
VCI – VGL
V
-0.3 ~ +6.5
Power supply voltage 10
VPP1
V
-0.3 ~ +10.0
1
Power supply voltage 11
VPP3A
V
-0.3 ~ +0.3
1
Input voltage
Vt
V
-0.3 ~ IOVCC + 0.3
Operation temperature
Topr
℃
-40 ~ +85
1, 8
Storage temperature
Tstg
℃
-55 ~ +110
1
1
Notes: 1. If used beyond the absolute maximum ratings, the LSI may be permanently damaged. It is
strongly recommended to use the LSI under the condition within the electrical characteristics in
normal operation. If exposed to the condition not within the electrical characteristics, it may affect
the reliability of the device.
2. Make sure VCC≥GND, and IOVCC≥GND.
3. Make sure VCI≥AGND.
4. Make sure DDVDH ≥ AGND.
5. Make sure DDVDH≥VCL.
6. Make sure AGND≥VGL.
7. Make sure VCI≥VGL.
8. The DC/AC characteristics of the die and wafer products are guaranteed at 85℃.
Rev. 0.11 April 25, 2008, page 167 of 181
R61509V
Target Spec
Electrical Characteristics
DC Characteristics
(VCC= 2.50V~3.30V, VCI=2.50V~3.30V, IOVCC=1.65V~3.30V, Ta= -40°C~+85°C *See note 1)
Table 83
Items
Symbol
Unit
Test condition
Min.
Typ.
Max.
Notes
Input high-level voltage
VIH
V
IOVCC=1.65V～3.30V
0.80×
IOVCC
Input low-level voltage
VIL
V
IOVCC=1.65V～3.30V
-0.3
－
0.20×
IOVCC
2, 3
VOH1
V
IOVCC=1.65V～3.30V，
0.8×
IOVCC
－
－
2
VOL1
V
－
－
0.20×
IOVCC
2
ILI1
µA
Vin=0～IOVCC
-1
－
1
4
IOP1
µA
fosc=678kHz (432-line drive), I80-IF,
IOVCC=VCC=3.00V, fFLM=60Hz,
Ta=25℃, RAM data: 18’h000000, See
other as well.
－
600
TBD
5, 6
Iop2
µA
fosc=678kHz (64-line partial display),
IOVCC=VCC=3.00V, fFLM=40Hz,
Ta=25℃, RAM data: 18h’000000, see
other as well.
－
300
－
5, 6
Ishut1
µA
IOVCC=VCC=3.00V, I80-IF, Ta=25℃
－
0.1
1.0
5, 6
IRAM1
mA
IOVCC=2.40V, VCC=3.00V,
tCYCW=110ns, Ta=25℃, I80-8bit-I/F,
TRIREG=1’h1, Consecutive RAM access
during display operation, BC0=0, FP=5,
BP=8, γ register; 0(default), COL=0
－
3.0
－
5
mA
IOVCC=1.8V, VCC=VCI=2.8V,
432-line drive, fFLM=60Hz, Ta=25℃,
Frame memory data: 18’h00000, REV=0,
BC0=0, FP[7:0]=8’h8, BP[7:0]=8’h8,
VC[2:0]=3’h1, BT[2:0]=3’h2,
VRH[4:0]=5’h18, VCM[6:0]=7’h7F,
VDV[4:0]=5’h11, AP[1:0]=2’h3,
DC0[2:0]=3’h3, DC1[2:0]=3’h4,
PR*P00=PR*N00=5’h00,
PR*P01=PR*N01=5’h02,
PR*P02=PR*N02=5’h04,
PR*P03=PR*N03=4’h8,
PR*P04=PR*N04=4’hF,
PR*P05=PR*N05=4’h8,
PR*P06=PR*N06=5’h04,
PR*P07=PR*N07=5’h02,
PR*P08=PR*N08=5’h04,
PIR*P0= PIR*P1= PIR*P2= PIR*P3=2'h0
PIR*N0= PIR*N1= PIR*N2= PIR*N3=2'h0
(*: 0, 1, 2)
No load on the panel.
－
3.5
TBD
6
Output high voltage 1
（DB0-17,FMARK）
Output low voltage 1
（DB0-17,FMARK）
I/O leakage current
IOH=-0.1mA
IOVCC=1.65V～3.30V，
IOL=0.1mA
－
IOVCC
2, 3
Current consumption
((IOVCC-IOGND)+
(VCC-GND))
Normal operation mode (262,144 color
display)
Current consumption
((IOVCC-IOGND)+
(VCC-GND))
8-color, 64-line partial display on sub
display
Current consumption
((IOVCC-IOGND)+
(VCC-GND))
Shutdown mode
Current consumption
((IOVCC-IOGND)+
(VCC-GND))
RAM access mode 1
LCD power supply current (VCI-GND)
262,144-color display
Ici1
Rev. 0.11 April 25, 2008, page 168 of 181
R61509V
Target Spec
Ici2
mA
IOVCC=1.8V, VCC=VCI=2.8V,
64-line partial, fFLM=40Hz, Ta=25℃,
Frame memory data: 18’h00000, REV=0,
BC0=0, FP[7:0]=8’h8, BP[7:0]=8’h8,
VC[2:0]=3’h1, BT[2:0]=3’h2,
VRH[4:0]=5’h18, VCM[6:0]=7’h7F,
VDV[4:0]=5’h11, AP[1:0]=2’h3,
DC0[2:0]=3’h3, DC1[2:0]=3’h4,
PR*P00=PR*N00=5’h00,
PR*P01=PR*N01=5’h02,
PR*P02=PR*N02=5’h04,
PR*P03=PR*N03=4’h8,
PR*P04=PR*N04=4’hF,
PR*P05=PR*N05=4’h8,
PR*P06=PR*N06=5’h04,
PR*P07=PR*N07=5’h02,
PR*P08=PR*N08=5’h04,
PIR*P0= PIR*P1= PIR*P2= PIR*P3=2'h0
PIR*N0= PIR*N1= PIR*N2= PIR*N3=2'h0
(*: 0, 1, 2)
No load on the panel.
VPP1AGND
IVPP1W
mA
VPP1=9.2V
VPP3AAGND
IVPP3AW
mA
(Write period)
－
－
1.0
6
VPP1AGND
IVPP1E
mA
VPP1=9.2V
－
－
1.0
6
VPP3AAGND
IVPP3AE
mA
(Erase period)
－
－
1.0
6
Output voltage dispersion
ΔVO
mV
－
－
5
－
7
Average output variance
ΔVΔ
mV
－
－35
－
35
8
LCD power supply current (VCI-GND)
8-color, 64-line partial display
NVM current
consumption
Write
NVM current
consumption
Erase
－
0.8
TBD
5, 6
－
－
30.0
6
VPP3A=GND
VPP3A=-9.2V
Rev. 0.11 April 25, 2008, page 169 of 181
R61509V
Target Spec
Step-up Circuit Characteristics
Table 84
Item
Step-up
output
voltage
Unit
DDVDH
VGH
VGL
VCLV
Test condition
Min.
Typ.
Max.
Note
V
IOVCC=VCC=VCI=2.80[V], fosc=678[kHz], Ta=25℃,
VC=3’h1, AP=3’h3, BT=3’h2, DC0=3’h4 (div. 1/8),
DC1=3’h2 (div. 1/4), COL=0, D=2’h0,
C11=C12=C13=C21=C22=1[uF]/B characteristics,
DDVDH=VGH=VGL=VCL=1[uF]/B characteristics,
Iload1=-3 [mA], No load on the panel.
4.8
5.1
-
-
V
IOVCC=VCC=VCI=2.80[V], fosc=678[kHz], Ta=25℃,
VC=3’h1, AP=3’h3, BT=3’h2, DC0=3’h4 (div. 1/8),
DC1=3’h2 (div. 1/4), COL=0, D=2’h0,
C11=C12=C13=C21=C22=1[uF]/B characteristics,
DDVDH=VGH=VGL=VCL=1[uF]/B characteristics,
Iload2=-100[uA], No load on the panel.
14.4
15.1
-
-
V
IOVCC=VCC=VCI=2.80[V], fosc=678[kHz], Ta=25℃,
VC=3’h1, AP=3’h3, BT=3’h2, DC0=3’h4 (div. 1/8),
DC1=3’h2 (div. 1/4), COL=0, D=2’h0,
C11=C12=C13=C21=C22=1[uF]/B characteristics,
DDVDH=VGH=VGL=VCL=1[uF]/B characteristics,
Iload3=+100[uA], No load on the panel.
-
-10.0
-9.6
-
V
IOVCC=VCC=VCI=2.80[V], fosc=678[kHz], Ta=25℃,
VC=3’h1, AP=3’h3, BT=3’h2, DC0=3’h4 (div. 1/8),
DC1=3’h2 (div. 1/4), COL=0, D=2’h0,
C11=C12=C13=C21=C22=1[uF]/B characteristics,
DDVDH=VGH=VGL=VCL=1[uF]/B characteristics,
Iload4=+200[uA], No load on the panel.
-
-2.55
-2.4
-
Internal Reference Voltage: Condition
(VCC= 2.50V~3.30V, Ta= -40°C~+85°C)
Table 85
Item
Internal reference
voltage
Unit
Symbol
VCIR
Rev. 0.11 April 25, 2008, page 170 of 181
V
Min.
-
Typ.
2.50
Max.
-
Note
12
R61509V
Target Spec
Power Supply Voltage Range
(Ta= -40°C~+85°C, GND=AGND=0V)
Table 86
Symbol
Unit
Min.
Typ.
Max.
Condition
Power Supply Voltage
IOVCC
V
1.65
1.80/2.80
3.30
-
Power Supply Voltage
VCC
V
2.50
2.80
3.30
-
Power Supply Voltage
VCI
Item
Power Supply Voltage
VPP1
Power Supply Voltage
VPP3A
V
2.50
2.80
3.30
-
V
8.9
9.2
9.5
Write
V
8.9
9.2
9.5
Erase
V
-0.3
0.0
+0.3
Write
V
-9.5
-9.2
-8.9
Erase
Output Voltage Range
(Ta= -40°C~+85°C, GND=AGND=0V)
Table 87
Item
Grayscale, VCOM
reference
Unit
Symbol
VREG1O
UT
V
VCOMH output
VCOMH
VCOML output
VCOML
Source driver
VCOM amplitude
Min.
Typ.
Max.
Condition
-
-
DDVDH-0.5
-
V
GND+0.2
-
VREG1OUT
-
V
-
-
VREG1OUT
-
V
VCL+0.5
-
-
-
V
-
-
6.0
-
Step-up output
DDVDH
V
4.5
-
6.0
-
Step-up output
VGH
V
10.0
-
18.0
-
Step-up output
VGL
V
-13.5
-
-4.5
-
Step-up output
VCL
V
-3.0
-
-1.9
-
VCI-VCL
V
-
-
6.0
-
VGH-VGL
V
-
-
28.0
-
Rev. 0.11 April 25, 2008, page 171 of 181
R61509V
Target Spec
AC Characteristics
(VCC= 2.50V~3.30V, IOVCC=1.65V~3.30V, Ta= -40°C~+85°C *See note 1)
Clock Characteristics
Table 88
Item
Symbol
Oscillation clock
fosc
Unit
kHz
Test condition
Min.
VCC=IOVCC=3.0V
Typ.
631
Max.
678
725
9
80-system 18-/16-/9-/8-bit Bus interface Timing Characteristics
(1-/2-/3-transfer, IOVCC=1.65V~3.30V) TBD
Table 89
Items
Bus cycle time
Symbol
Unit
Test
condition
Min.
Typ.
Max.
Write
tCYCW
ns
Figure A
75 (TBD)
－
－
Read
tCYCR
ns
Figure A
450 (TBD)
－
－
Write low- level pulse width
PWLW
ns
Figure A
30 (TBD)
－
－
Read low-level pulse width
PWLR
ns
Figure A
170 (TBD)
－
－
Write high-level pulse width
PWHW
ns
Figure A
25 (TBD)
－
－
Read high-level pulse width
PWHR
ns
Figure A
250 (TBD)
－
－
Write/ Read rise/fall time
tWRr，
ns
Figure A
－
－
15
ns
Figure A
0 (TBD)
－
－
ns
Figure A
10 (TBD)
－
－
Setup time
Write (RS to CSX,
WRX)
Read (RS to CSX,
RDX)
WRf
tAS
Address hold time
tAH
ns
Figure A
2 (TBD)
－
－
Write data setup time
tDSW
ns
Figure A
25 (TBD)
－
－
Write data hold time
tH
ns
Figure A
10 (TBD)
－
－
Read data delay time
tDDR
ns
Figure A
－
－
150
Read data hold time
tDHR
ns
Figure A
5 (TBD)
－
－
Rev. 0.11 April 25, 2008, page 172 of 181
Note
R61509V
Target Spec
Clock Synchronous Serial Interface Timing Characteristics
(IOVCC=1.65V~3.30V) TBD
Table 90
Item
Serial clock cycle
time
Serial clock
high-level width
Serial clock
low-level width
Symbol
Unit
Test condition
Min.
Typ.
Max.
Write (receive)
tSCYC
ns
Figure B
100 (TBD)
－
20,000
Read (transmit)
tSCYC
ns
Figure B
350 (TBD)
－
20,000
Write (receive)
tSCH
ns
Figure B
40 (TBD)
－
－
Read (transmit)
tSCH
ns
Figure B
150 (TBD)
－
－
Write (receive)
tSCL
ns
Figure B
40 (TBD)
－
－
Read (transmit)
tSCL
ns
Figure B
150 (TBD)
－
－
Serial clock rise/fall time
tSCr，tSCf
ns
Figure B
－
－
15 (TBD)
Chip select setup time
tCSU
ns
Figure B
20 (TBD)
－
－
Chip select hold time
tCH
ns
Figure B
60 (TBD)
－
－
Serial input data setup time
tSISU
ns
Figure B
30 (TBD)
－
－
Serial input data hold time
tSIH
ns
Figure B
30 (TBD)
－
－
Serial output data delay time
tSOD
ns
Figure B
－
－
130 (TBD)
Serial output data delay time
tSOH
ns
Figure B
5 (TBD)
－
－
RGB Interface Timing Characteristics
(18-/16-bit RGB interface, IOVCC=1.65V~3.30V) TBD
Table 91
Item
Symbol
Unit
VSYNC/HSYNC setup time
tSYNCS
clock
Figure D
0.5 (TBD)
－
1.5
ENABLE setup time
tENS
ns
Figure D
10 (TBD)
－
－
ENABLE hold time
tENH
ns
Figure D
20 (TBD)
－
－
DOTCLK low-level pulse width
PWDL
ns
Figure D
40 (TBD)
－
－
DOTCLK high-level pulse width
PWDH
ns
Figure D
40 (TBD)
－
－
DOTCLK cycle time
tCYCD
ns
Figure D
100 (TBD)
－
－
Data setup time
tPDS
ns
Figure D
10 (TBD)
－
－
Data hold time
tPDH
ns
Figure D
40 (TBD)
－
－
DOTCLK, VSYNCX and HSYNCX
rise/fall time
trgbr，
trgbf
ns
Figure D
－
－
15
Rev. 0.11 April 25, 2008, page 173 of 181
Test condition
Min.
Typ.
Max.
R61509V
Target Spec
LCD Driver Output Characteristics
Table 92
Item
Symbol
Unit
Test condition
Min.
Typ.
Max.
Note
VCC=IOVCC =2.80V, VC[2:0]=3’h7
VRH[4:0]=5’h1F,
fosc=678kHz (432-line drive), Ta=25°C,
PR*P00=PR*N00=5’h00,
PR*P01=PR*N01=5’h02,
PR*P02=PR*N02=5’h04,
PR*P03=PR*N03=4’h8,
PR*P04=PR*N04=4’hF,
PR*P05=PR*N05=4’h8,
Source driver
output delay time
tdds
µs
PR*P06=PR*N06=5’h04,
PR*P07=PR*N07=5’h02,
－
25 (TBD)
－
10
－
25 (TBD)
－
11
PR*P08=PR*N08=5’h04,
PIR*P0= PIR*P1= PIR*P2= PIR*P3=2'h0
PIR*N0= PIR*N1= PIR*N2= PIR*N3=2'h0
Same change from the same grayscale at
all time-division source output pins.
Time to reach the target voltage ±35mV
from VCOM polarity inversion timing.
R=10kohm, C=30pF
VCC=IOVCC=2.80V, VC[2:0]=3’h7,
VRH[4:0] =5’h1F,
fosc=678kHz (432-line drive), Ta=25°C,
PR*P00=PR*N00=5’h00,
PR*P01=PR*N01=5’h02,
PR*P02=PR*N02=5’h04,
PR*P03=PR*N03=4’h8,
VCOM output
delay time
PR*P04=PR*N04=4’hF,
PR*P05=PR*N05=4’h8,
tddv
µs
PR*P06=PR*N06=5’h04,
PR*P07=PR*N07=5’h02,
PR*P08=PR*N08=5’h04,
PIR*P0= PIR*P1= PIR*P2= PIR*P3=2'h0
PIR*N0= PIR*N1= PIR*N2= PIR*N3=2'h0
Time to reach ±35mV when shifting
between source Ｖ0⇔V63 in the worst
case of scenario.
R=100ohm, C=10nF
Reset Timing Characteristics
Table 93（IOVCC=1.65V～3.30V）
Item
Symbol
Unit
Test condition
Min.
Typ.
Max.
Reset ”Low” level width
tRES
ms
Figure C
1
－
－
Reset rise time
trRES
µs
Figure C
－
－
10
Rev. 0.11 April 25, 2008, page 174 of 181
R61509V
Target Spec
Notes to Electrical Characteristics
Note 1. The DC/AC electrical characteristics of bare die and wafer products are guaranteed at 85℃.
Note 2. The following figures illustrate the configurations of input, I/O, and output pins.
Pins: FMARK, SDO
Pins: RESETX, IM2-1, IM0_ID
VSYNCX, HSYNCX, DOTCLK, ENABLE,
CSX, RDX, SDI
IOVCC
IOVCC
PMOS
PMOS
Output data
(Input circuit)
NMOS
NMOS
GND
GND
Pins: WR_SCL, RDX
IOVCC
PMOS
Input enable (CSX)
PMOS
(Input circuit)
NMOS
NMOS
GND
Pins: DB17-DB0
IOVCC
PMOS
Input enable (CSX)
PMOS
(Input circuit)
NMOS
NMOS
GND
IOVCC
(Output circuit: three states)
Output enable
PMOS
Output data
NMOS
GND
Figure 77
Rev. 0.11 April 25, 2008, page 175 of 181
R61509V
Target Spec
Note 3: Test 1, 2 and 3 pins must be grounded. The VDDTEST and VREFC must be fixed to AGND. The
IM0_ID pin must be fixed to IOVCC or be grounded.
Note 4: This excludes the current in the output drive MOS.
Note 5: This excludes the current in the input/output lines. Make sure that the input level is fixed because
through current will increase in the input circuit when the CMOS input level takes a middle range
level. The current consumption is unaffected by whether the CSX pin is high or low while not
accessing via interface pins.
Note 7: The output voltage deviation is the difference in the voltages from adjacent source pins for the
same display area. This value is shown for reference.
Note 8: The average output voltage dispersion is the variance source-output voltage of different chips of the
same product. The average source output voltage is measured for each chip with same display area.
Note 9: This applies to internal oscillators when using an internal RC oscillator.
Note 10: The liquid crystal driver output delay time depends on the load on the liquid crystal panel. Adjust
the frame frequency and the cycle per line by checking the quality of display on the actual panel in
use.
Test Circuits
[Data bus DB17-DB0]
[Liquid output: S1-S720]
Test Point
Test Point
Test Point
50pF
10kΩ
Figure 78
Rev. 0.11 April 25, 2008, page 176 of 181
Load capacitance C
30pF
Load resistance R
100Ω
Load capacitance C
10nF
R61509V
Target Spec
Timing Characteristics
80-system Bus Interface
VIH
VIH
VIL
VIL
RS
tAH
tAS
CSX
VIH
VIH
VIL
VIL
Note 1
PWLW PWLR
PWHW PWHR
VIH
WRX
RDX
VIH
VIL
VIH
VIL
tWRr
tWRf
tCYCW tCYCR
tDSW
tH
Note 2
VIH
VIH
Write Data
DB17-0
VIL
VIL
tDDR
Note 2
tDHR
VOH
VOH
Read Data
DB17-0
VOL
VOL
Note 1: PWLW and PWLR are defined by the overlap period when CSX is "Low" and either of WRX or RDX is "Low".
Note 2: Unused DB pins must be fixed at "IOVCC" or "GND".
Figure A 80-system Bus Interface
Rev. 0.11 April 25, 2008, page 177 of 181
R61509V
Target Spec
Clock Synchronous Serial Interface
Start: S
End: P
VIH
CSX
VIL
tSCYC
tscr
tscf
tCSU
tSCH
VIH
SCL
VIH
VIL
tSCL
VIH
VIL
VIH
VIL
tSISU
VIL
tSISH
VIH
VIH
Input Data
SDI
tCH
VIL
Input Data
VIL
tSOD
tSOH
VOH1
VOH1
Output Data
SDO
Output Data
VOL1
VOL1
Figure B Clock Synchronous Serial Interface Timing
Reset Operation
trRES
tRES
VIH
RESETX
VIL
VIL
Figure C Reset Timing
Rev. 0.11 April 25, 2008, page 178 of 181
R61509V
Target Spec
RGB Interface
trgbf
trgbr
tSYNCS
VSYNCX
VIH
VIH
HSYNCX
VIL
VIL
tENS
ENABLE
tENH
VIH
VIH
VIL
VIL
trgbf
trgbr
PWDL
DOTCLK
PWDH
VIH
VIH
VIL
VIH
VIL
VIL
tCYCD
tPDS
tPDH
VIH
DB17-0
VIH
Write Data
VIL
VIL
Figure D RGB Interface Timing
LCD Driver and VCOM Output Characteristics
tDDv
Target voltage r35mV
VCOM
Target voltage r35mV
tDDs
Target voltage r35mV
S1-720
Target voltage r35mV
Figure E LCD Driver and VCOM Output Timing
Rev. 0.11 April 25, 2008, page 179 of 181
Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
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Colophon .1.0
R61509V
Target Spec
Revision Record
Rev.
0.11
Date
2008/04/25
Page No.
Contents of Modification
First issue
Rev. 0.11 April 25, 2008, page 181 of 181
Drawn
by
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