Sensitech T11012087 PART 15 CLASS B COMPUTING DEVICE PERIPHERAL User Manual
Sensitech, INC. PART 15 CLASS B COMPUTING DEVICE PERIPHERAL Users Manual
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![© SENSITECH INC. CONFIDENTIAL – CONTROLLED DOCUMENT Page 24 of 83 A Carrier Corp. Company PART NUMBER T82002163 REV A frequency-change modes • Provides signals and controls for fly-by DMA transfers • Supports non-volatile memory configured as bank 0 from either 16- or 32-bit devices • Provides three independent output clocks (SDCLK<2:0>) that can be turned on/off separately and can be programmed to be free-running. The clocks can be the same frequency or half the frequency of the input clock, CLK_MEM. One clock (SDCLK<0>) can also be programmed as one quarter of the input-clock frequency. A fourth output clock (SDCLK<3>) depends on configuration bits used to control SDCLK<0>. • Provides a programmable power-down mode for saving power Memory Controller Operation The processor has three different memory spaces: SDRAM, static memory, and PC Card space. SDRAM has four partitions, static memory has six partitions, and PC Card space has two partitions (or sockets). When user software performs a memory burst across the boundary between any two adjacent partitions, the configurations for each partition must be identical. They must have the same external bus width, burst length, and so forth. In theory, the partitions can be different types of memory sharing the same configuration characteristics. In practice, cross-partition memory bursts are conducted only when the two partitions hold the same memory type. A typical case is a transfer across two SDRAM partitions, 0 and 1, which are mandated to have the same characteristics. Figure 6-1 is a block diagram of the maximum configuration of the memory controller. Stacked SDRAM and Flash Memory This section describes memory types that may be supported in the PXA271 and PXA272 processors. Stacked SDRAM On the Intel® PXA271 processor, SDRAM is stacked and connected to SDRAM partition 0. On systems using the Intel® PXA271 processor, external SDRAM memory chips must not exist within the same SDRAM partition pair as that of the internal stacked SDRAM. This could cause negative signal reflection to the stacked SDRAM device. For the Intel® PXA271 processor stacked SDRAM, the Intel® PXA27x processor memory controller must be programmed to multiplex the SDRAM address lines out differently because the address lines to the stacked SDRAM are not connected to the usual MA<24:10> lines. The MDCNFG[STACKx] field on a Intel® PXA271 processor must be programmed to 0b01 to send the SDRAM address out on MA<24:23,13:1> for stacked 16-bit SDRAM of this product. For a non stacked part (Intel® PXA270 processor) or flash only stacked part (Intel® PXA272 processor) the MDCNFG[STACKx] field must be programmed to 0b00 to send the SDRAM address out on MA<24:10>. Stacked Flash Memory A fourth SDCLK, SDCLK<3> is driven by the memory controller, to be used in the PXA271 and PXA272 processors containing stacked flash devices. SDCLK<3> is a buffer duplicate of](https://usermanual.wiki/Sensitech/T11012087/User-Guide-1121184-Page-24.png)
![© SENSITECH INC. CONFIDENTIAL – CONTROLLED DOCUMENT Page 25 of 83 A Carrier Corp. Company PART NUMBER T82002163 REV A SDCLK<0> and does not have any control bits of its own to turn it on or off. Use the buffer strength field associated with SDCLK<3> to turn off SDCLK<3> if there is no stacked flash in the system. This buffer strength setting is located in the BSCNTR2 register. Static partitions 0 and 1 may contain stacked flash. The memory controller must be aware of which static memory partitions contain stacked flash. This is programmed in the SA1111[SXSTACK] field. When a flash device is being written to, the nCS and nWE signals swap functionality from a normal flash write to an off-chip device. This is shown by timing diagrams in the Intel® PXA27x Processor Family EMTS. Figure 6-1. General Memory Interface Configuration](https://usermanual.wiki/Sensitech/T11012087/User-Guide-1121184-Page-25.png)
![© SENSITECH INC. CONFIDENTIAL – CONTROLLED DOCUMENT Page 26 of 83 A Carrier Corp. Company PART NUMBER T82002163 REV A Synchronous Dynamic Memory (SDRAM) Interface The processor supports the JEDEC synchronous dynamic memory (SDRAM) interface. The SDRAM interface supports four 16-bit or 32-bit wide partitions of SDRAM. Each partition is allocated 64 or 256 Mbytes of the internal memory map. The actual size of each partition depends on the SDRAM configuration used. The four partitions are divided into two partition pairs: the 0/1 pair and the 2/3 pair. Both partitions in a pair must be identical in size and configuration. Pairs 0/1 and 2/3 can be different. For example, the 0/1 pair can be 100-MHz SDRAM on a 32-bit data bus, while the 2/3 pair can be 50-MHz SDRAM on a 16-bit data bus. The SDRAM interface includes the following: • Four partition selects, nSDCS<3:0> • Four byte mask signals, DQM<3:0> • 15 multiplexed bank/row/column address signals, MA<24:10>, MA<24:23,14:2>, or MA<24:23,13:1>, depending on the MDCNFG[STACKx] setting • One write enable, nWE • One column-address strobe (nSDCAS) • One row-address strobe (nSDRAS) • One clock enable (SDCKE) • Two clocks (SDCLK<2:1>) The processor performs auto-refresh (CBR) during normal operation and supports self-refreshing SDRAM during sleep, deep-sleep, standby, and frequency-change modes. An SDRAM autopower- down mode bit (MDREFR[APD]) can be set so that the two clocks (SDCLK<2:1>) and the clock-enable signal (SDCKE) to SDRAM are automatically de-asserted whenever none of the corresponding partitions is being accessed. Each possible SDRAM section of the memory map is referred to as a partition, to distinguish them from banks internal to SDRAM devices. Maximum Row Active Time (TRAS) The maximum amount of time that any SDRAM row can be active is defined as TRASMAX. When programming MDREFR[DRI], ensure that the refresh cycle time is less than TRASMAX because it is not monitored by the memory controller. Programmable Larger SDRAM Memory Space The read/write MDCNFG register contains control bits for configuring the SDRAM for larger SDRAM configurations than fit in the 64-Mbyte SDRAM partitions. Refer to Table 6-23 for configuration programming. Figure 6-2 shows the programmable option for the SDRAM memory space.](https://usermanual.wiki/Sensitech/T11012087/User-Guide-1121184-Page-26.png)
![© SENSITECH INC. CONFIDENTIAL – CONTROLLED DOCUMENT Page 28 of 83 A Carrier Corp. Company PART NUMBER T82002163 REV A SDRAM Power-ON State Machine (figure below): Sleep, deep-sleep, standby, or frequency-change requests cause the SDRAM state machine to enter the self-refresh and clock-stop state. Software must then complete the appropriate reset procedure. Clearing MDREFR[E1PIN] and MDREFR[KnRUN] provides software control of the SDRAM memory system low-power modes. Note: (1) Use these modes with extreme caution, because the resulting states prohibit automatic toggles from mode register set, read, write, and refresh commands. The Auto_Power_Down and Auto_Power_Up transitions (made possible by setting the APD bit in MDREFR) provide a completely automatic alternative for minimizing power consumption in the SDRAM system. (2) Some companion chips require the clock to be present at all times. Use the following prioritization scheme for transitions out of the NOP state. If enabled with the APD bit, the Auto_Power_Down transition occurs when none of the higher priority transitions are asserted. The Auto_Power_Up transitions occur when refresh, New_MRS, or read/write is asserted during the Power_Down state.](https://usermanual.wiki/Sensitech/T11012087/User-Guide-1121184-Page-28.png)
![© SENSITECH INC. CONFIDENTIAL – CONTROLLED DOCUMENT Page 29 of 83 A Carrier Corp. Company PART NUMBER T82002163 REV A Highest Priority- ”Enter Sleep” “Set_SLFRSH” “Clear_E1PIN” “Refresh” “New_MRS” “Read/Write” Lowest Priority - “Auto_Power_Down” KnRUN = MDREFR[K1RUN] OR MDREFR[K2RUN] Auto_Power_Down = MDREFR[APD] Clear_E1PIN = !(MDREFR[E1PIN]) Set_SLFRSH = MDREFR[SLFRSH] Enter_Sleep = Sleep/Deep-Sleep/Standby/ Frequency Change Request and no more transactions to process Auto_Power_Up = Read/Write is asserted during the power-down state OR New_MRS OR Refresh OR !(MDREFR[APD]) Synchronous, Static, and Variable-Latency I/O (VLIO) Interfaces The static memory and VLIO interfaces have six chip selects (nCS<5:0>) and 26 bits of byte address (MA<25:0>) for accesses of up to 64 Mbytes of memory in each of six banks. Alternately, a mode is available to support up to two 128-Mbyte chip selects (nCS<1:0>) with 26 bits of halfword address (MA<0>, MA<25:1>) and two 64-Mbyte chip selects (nCS<5:4>) with 25 bits of byte address (MA<25:0>). This programmable option resides in the Static Memory Configuration register SA1110[SXENX]. Each chip select is individually programmed to select one of the supported static memory types. • Non-burst ROM or flash memory (Section 6.4.3.2) is supported on each of nCS<5:0> • Burst ROM or flash memory with non-burst writes (Section 6.4.3.2) is supported on each of nCS<5:0> • SRAM is supported on each of nCS<5:0> • Variable-latency I/O is supported on each of nCS<5:0> • Synchronous flash memory is supported on each of nCS<3:0> The four synchronous-flash memory partitions (nCS<3:0>) are divided into two partition pairs: the 0/1 pair and the 2/3 pair. Both partitions in a pair must be identical in size and configuration. The two pairs can be different. For example, the 0/1 pair can be 66-MHz synchronous flash memory on a 32-bit data bus while the 2/3 pair is 33-MHz synchronous flash memory on a 16-bit data bus. The VLIO interface differs from SRAM in that it allows the use of the data-ready input signal, RDY, to insert a variable number of wait states. For all static memory types, each chip select can be configured individually to a 16-bit or 32-bit wide data bus. The nOE signal is asserted on reads, the nPWE signal is asserted on writes to VLIO devices, and the nWE signal is asserted on writes to all other static devices, both synchronous and asynchronous. For SRAM and VLIO, DQM<3:0> are byte enables for both reads and writes. When the processor comes out of reset, it begins to fetch and execute instructions at address 0x00, which corresponds to memory selected by nCS<0>, which is the required location of the boot ROM. The BOOT_SEL pin determines the width of the boot memory. Asynchronous Static Operation The static-memory interface is comprised of six chip selects, nCS<5:0>. These six chip selects are](https://usermanual.wiki/Sensitech/T11012087/User-Guide-1121184-Page-29.png)
![© SENSITECH INC. CONFIDENTIAL – CONTROLLED DOCUMENT Page 30 of 83 A Carrier Corp. Company PART NUMBER T82002163 REV A configurable for the following: • Non-burst ROM or flash memory • Burst ROM or flash memory • SRAM • VLIO devices The VLIO interface differs from SRAM in that it allows the use of a data-ready input signal, RDY, to insert a variable number of memory-cycle wait states. The data bus width for each chip-select region can be programmed to be 16- or 32-bit. The nCS<3:0> signals are also configurable for synchronous static memory. The following list describes the use of nOE, nWE, and nPWE: • nOE is asserted for all reads. • nWE is asserted for flash memory and SRAM writes. • nPWE is asserted for VLIO writes. For SRAM and VLIO implementations, DQM<3:0> are used for the write byte-enables, where DQM<3> corresponds to the MSB. The processor supplies 26 bits of byte address for access of up to 64 Mbytes per chip select. This byte address is sent out on the 26 external address pins. If the byte address is unimportant for an application, the lower bit must be truncated for 16-bit systems and the lower two bits must be truncated for 32-bit systems. For reads, the byte address bits is 0. For writes, the byte address bits are summarized in Table 6-10 and Table 6-11. Table 6-10. 32 Bit Byte Address Bits MA <1.0> for Writes Based on DQM <3.0> Transaction DQM<3:0> MA<1:0> Word 0b0000 0b00 Byte 0 0b1110 0b00 Byte 1 0b1101 0b01 Byte 2 0b1011 0b10 Byte 3 0b0111 0b11 Lower half word 0b1100 0b00 Upper half word 0b0011 0b10 Table 6-11. 16-Bit Byte Address Bit MA <0> for Writes Based on DQM <1.0> Transaction DQM<1:0> MA<0> Half word 0b00 0b0 Byte 0 0b10 0b0 Byte 1 0b01 0b1 The MSCx[RTx] fields specify the type of memory: • Non-burst ROM or flash memory • SRAM • VLIO • Burst-of-four ROM or flash memory](https://usermanual.wiki/Sensitech/T11012087/User-Guide-1121184-Page-30.png)
![© SENSITECH INC. CONFIDENTIAL – CONTROLLED DOCUMENT Page 31 of 83 A Carrier Corp. Company PART NUMBER T82002163 REV A • Burst-of-eight ROM or flash memory The MSCx[RBWx] fields specify the bus width for the memory space selected by nCS<5:0>. If a 16-bit bus width is specified, transactions occur across data pins MD<15:0>. Use the BOOT_SEL pin or SXCNFG register to configure nCS<3:0> for synchronous static memory. Asynchronous Flash Memory Interface The MSCx[RDFx] bit fields define the latency for each read access of non-burst flash memory or the first read access of burst flash memory. The same bit field also controls the nWE de-assertion time during a write cycle to flash memory. The MSCx[RDN] field controls subsequent read access times to burst flash memory. The MSCx[RRR] bit field calculates the minimum period from the nCS signal de-assertion following a read or write and before the start of the read from a different memory. The following requirements apply to reads from flash memory: • Because flash memory defaults to read-array mode, burst reads from it are permitted, which allows instruction caching and burst reads (DMA and USB host) from flash memory. • Some areas of flash memory might not permit burst reads. When attempting to read from these areas, do not attempt burst reads. Consult the flash-memory data sheet for more information. Table 6-10. 32-Bit Byte Address Bits MA<1:0> for Writes Based on DQM<3:0> Transaction DQM<3:0> MA<1:0> Word 0b0000 0b00 Byte 0 0b1110 0b00 Byte 1 0b1101 0b01 Byte 2 0b1011 0b10 Byte 3 0b0111 0b11 Lower half word 0b1100 0b00 Upper half word 0b0011 0b10 Table 6-11. 16-Bit Byte Address Bit MA<0> for Writes Based on DQM<1:0> Transaction DQM<1:0> MA<0> Half word 0b00 0b0 Byte 0 0b10 0b0 Byte 1 0b01 0b1 Memory Controller • Software must partition commands and data, then write the commands to flash memory before a read. The memory controller does not insert any commands before flash-memory reads. The following requirements apply to writes to flash memory: • Flash memory space must be uncacheable and unbuffered. • Burst writes to flash memory do not exist. Writes to flash memory must be exactly the width of the populated flash devices on the data bus and must be a burst length of one write (for instance, no byte writes to a 32-bit bus, no word writes to a 16-bit bus, no writes of 2 bytes to a 32-bit bus, no writes of 1 byte to a 16-bit bus). The allowable writes are 2 bytes to a 16-bit bus and 4 bytes to a 32-bit bus. • For writes to flash memory, the command and data must be given to the memory controller in separate write instructions. The first instruction carries the command; the next carries the data. • Software must partition commands and data and write them to flash memory in the appropriate sequence. The memory controller does not insert any commands before flash-memory writes. • Because burst writes to flash memory cannot occur, the DMA controller and USB host controller must never write to flash memory. Burst writes to flash memory are not performed.](https://usermanual.wiki/Sensitech/T11012087/User-Guide-1121184-Page-31.png)
![© SENSITECH INC. CONFIDENTIAL – CONTROLLED DOCUMENT Page 33 of 83 A Carrier Corp. Company PART NUMBER T82002163 REV A MSCx[RDF] defines the latency (in memory clock cycles) for the first and all subsequent data beats from non-burst ROMs and the first data beat from a burst ROM. The value of MSCx[RDN] defines the latency for the burst data beats after the first for burst ROMs. Specifying the MSCx[RRR] value allows a delay on the next access to a different memory space to allow time for the current ROM to three-state the data bus. MSCx[RRR] must be programmed with the maximum TOFF value divided by two, as specified by the ROM manufacturer. MSC0<15:0> is selected when the address space corresponding to nCS<0> is accessed. SRAM Interface Overview The processor provides a 16- or 32-bit synchronous SRAM interface that uses the DQM pins for byte enables on writes. Bits nCS<5:0> select the SRAM bank to be used. nOE is asserted on reads and nWE is asserted on writes. Address bits MA<25:0> allow up to 64 Mbytes of SRAM per bank to be addressed. The RDF fields in the MSCx registers define the latencies for a read access. The MSCx[RDN] field controls the nWE low time during a write cycle. MSCx[RRR] is defined as the minimum time from nCS de-assertion to the beginning of a read or write access of any memory bank Any DMA mode that does not increment the address is not supported for SRAM reads or writes. DCMDx[INCSRCADDR] and DCMDx[INCTRGADDR] clear cause the address not to be incremented. This DMA mode is not supported for SRAM. The only valid memory types for this mode are VLIO and PC Card/CompactFlash devices. Variable-Latency I/O Interface Overview When a companion chip is used as a VLIO device, its functionality is similar to that of an SRAM with the additional ability to insert a variable number of wait states through the RDY pin. VLIO can be used in the memory space for any of the six static memory locations (nCS<5:0>) by programming the corresponding MSCx[RTx] to 0b100. 13:11 FREQUENCY CONFIGURATION 0b010 -> Code 2 (CAS latency 3) 0b011 -> Code 3 (CAS latency 4) 0b100 -> Code 4 (CAS latency 5) 0b101 -> Code 5 (CAS latency 6) 0b110 -> Code 6 (CAS latency 7) Choose this value based on the “AC Characteristics—Read-Only Operation” section of the flash-memory device data sheet. 14 reserved 0b0 15 READ MODE 0b0 = Synchronous operation 0b1 = Asynchronous operation Table 6-12. Sample Read Programming Values for Synchronous Flash Memory Bits Field Name Value to Program Memory Controller VLIO read accesses differ from SRAM read accesses in that nOE toggles for each beat of a burst. The first nOE assertion occurs two CLK_MEM cycles after the chip select, nCSx, is asserted. For VLIO writes, nPWE is used instead of nWE, which allows SDRAM refreshes to execute while performing the VLIO transfers.](https://usermanual.wiki/Sensitech/T11012087/User-Guide-1121184-Page-33.png)
![© SENSITECH INC. CONFIDENTIAL – CONTROLLED DOCUMENT Page 34 of 83 A Carrier Corp. Company PART NUMBER T82002163 REV A For both reads and writes from and to VLIO, clearing DCMDx[INCSRCADDR] and DCMDx[INCTRGADDR] causes the source and target addresses not to be incremented to the VLIO interface, which allows port-type VLIO chips to interface with the processor. The only valid memory types for this DMA mode are VLIO and PC Card/CompactFlash devices. For writes to VLIO, if all byte enables are turned off (masking out the data, DQM = 0b1111), then the write enable is suppressed (nPWE = 1) for this write-beat to VLIO. This suppression can cause a period when nCS is asserted but neither nOE nor nPWE is asserted, which would happen if there is a write of one beat to VLIO with all byte enables turned off. In this case, the memory controller ignores the RDY signal. The RDY signal must not be asserted late if it is to still be asserted, which could interfere with any following transfers. If the VLIO device does not see an nOE or a nPWE, it must not change the state of RDY, keeping it either asserted or de-asserted. With the exception of the case above, and when entering a frequency change, the memory controller indefinitely waits for the RDY signal to be asserted, which can hang the system if the external VLIO is not responding. To prevent indefinite hangs, set the watchdog timer when starting a VLIO transfer; a watchdog reset occurs if no response is received from the VLIO device. Figure 6-5. Variable-Latency I/O Diagram UARTs This chapter describes the universal asynchronous receiver/transmitter (UART) serial ports included in the PXA27x processor. The serial ports are controlled using direct-memory access (DMA) or programmed I/O. The PXA27x processor has three UARTs: full-function (FFUART), Bluetooth (BTUART), and standard (STUART). All UARTs use the same programming model. Overview Each serial port contains a UART and a slow infrared-transmit encoder and receive decoder that conform to the IrDA serial-infrared specification.1 Each UART performs serial-to-parallel conversion on data characters received from a peripheral device or a modem and parallel-to-serial conversion on data characters received from the processor. The processor can read a UART’s complete status during functional operation. Status information includes the type and condition of transfer operations and error conditions (parity, overrun, framing, or break interrupt) associated with the UART. Each serial port operates in either FIFO or non-FIFO mode. In FIFO mode, a 64-byte transmit FIFO holds data from the processor until it is transmitted on the serial link, and a 64-byte receive](https://usermanual.wiki/Sensitech/T11012087/User-Guide-1121184-Page-34.png)
![© SENSITECH INC. CONFIDENTIAL – CONTROLLED DOCUMENT Page 36 of 83 A Carrier Corp. Company PART NUMBER T82002163 REV A — 1, 1½, or 2 stop-bit generation — Baud-rate generation up to 921 kbps for all UARTs — False start-bit detection • 64-byte transmit FIFO • 64-byte receive FIFO • Complete status-reporting capability • Ability to generate and detect line breaks • Internal diagnostic capabilities that include: — Loopback controls for communications-link fault isolation — Break, parity, and framing-error simulation • Fully prioritized interrupt system controls • Separate DMA requests for transmit and receive data services • Slow infrared asynchronous interface that conforms to the Infrared Data Association (IrDA) specification Signal Descriptions Table 10-1 lists and describes each external signal that is connected to a UART module. The pins transmit digital CMOS-level signals and are connected to the PXA27x processor through GPIOs. Refer to Section 24, “General-Purpose I/O Controller” for details on the GPIOs. Table 10-1. UARTs I/O Signal Descriptions (Sheet 1 of 2) Name Type Description RXD Input Serial Input- Serial data input to the receive shit register. In infrared mode, it is connected to the infrared receiver input. This signal is present on all three UARTs. TXD Output Serial Output—Serial data output to the communications-link peripheral, modem, or data set. The TXD signal is set to the logic 1 state upon a reset operation. It is connected to the output of the infrared transmitter in infrared mode. This signal is present on all three UARTs. nCTS Input Clear to Send—When low, indicates that the modem or data set is ready to exchange data. The nCTS signal is a modem status input, and its condition can be tested by reading bit 4 (CTS) of the Modem Status register (MSR). MSR[CTS] is the complement of the nCTS signal. MSR[DCTS] indicates whether the nCTS input has changed state since the last time MSR was read. nCTS has no effect on the transmitter. This signal is present on the FFUART and BTUART. When MSR[CTS] changes state and the modem-status interrupt is enabled, an interrupt is generated. Non-Auto-Flow Mode—When not in auto-flow mode, MSR[CTS] indicates the state of nCTS. MSR[DCTS] indicates whether the nCTS input has changed state since the previous reading of MSR. nCTS has no effect on the transmitter. The user can program the UART to interrupt the processor when DCTS changes state. Software can then stall the outgoing data stream by starving the transmit FIFO or disabling the UART with the IER register. NOTE: If UART transmission is stalled by disabling the UART, no MSR interrupt is received when nCTS reasserts, because disabling the UART also disables interrupts. To get around this, either use auto-CTS in auto-flow mode or program the nCTS GPIO pin to interrupt. Auto-Flow Mode—In this mode, the UART transmit circuity checks the state of nCTS before transmitting each byte. IF nCTS is high, no data is transmitted.](https://usermanual.wiki/Sensitech/T11012087/User-Guide-1121184-Page-36.png)
![© SENSITECH INC. CONFIDENTIAL – CONTROLLED DOCUMENT Page 37 of 83 A Carrier Corp. Company PART NUMBER T82002163 REV A nDSR Input Data Set Ready—When low, indicates that the modem or data set is ready to establish a communications link with a UART. The nDSR signal is a modem-status input. Its condition can be tested by reading MSR[DSR], which is the complement of nDSR. MSR[DDSR] indicates whether the nDSR input has changed state since MSR was last read. This signal is present only on the FFUART. When MSR[DSR] changes state, an interrupt is generated if the modem-status interrupt is enabled. nDCD Input Data Carrier Detect—When low, indicates that the data carrier has been detected by the modem or data set. The nDCD signal is a modem-status input. Its condition can be tested by reading MSR[DCD], which is the complement of the nDCD signal. MSR[DDCD] indicates whether the nDCD input has changed state since the previous reading of MSR. nDCD has no effect on the receiver. This signal is present only on the FFUART. When the DCD bit changes state and the modem-status interrupt is enabled, an interrupt is generated. Table 10-1. UARTs I/O Signal Descriptions (Sheet 2 of 2) Name Type Description nRI Input Ring Indicator—When low, indicates that the modem or data set has received a telephone ringing signal. The nRI signal is a modem-status input. Its condition can be tested by reading MSR[RI], which is the complement of the nRI signal. MSR[TERI] (trailing-edge-of-ring indicator) indicates whether the nRI input has changed from low to high since MSR was last read. This signal is present only on the FFUART. When the RI bit of the MSR changes from a high to low state and the modem-status interrupt is enabled, an interrupt is generated. nDTR Output Data Terminal Ready—When low, signals the modem or the data set that the UART is ready to establish a communications link. To assert the nDTR output (active low), set MSR[DTR], which is the complement of the output signal. A reset operation deasserts this signal (high). Loopback-mode operation holds nDTR deasserted. This signal is present only on the FFUART. nRTS Output Request to Send—When low, signals the modem or the data set that the UART is ready to exchange data. To assert the nRTS output (active low), set MSR[RTS], which is the complement of the output signal. A reset operation deasserts this signal (high). Loopback-mode operation holds nRTS deasserted. This signal is used by the FFUART and BTUART. Non-Auto-Flow Mode—To assert the nRTS output (active low), set MSR[RTS]. Auto-Flow Mode—nRTS is automatically asserted by the auto-flow circuitry when the receive buffer exceeds its programmed trigger threshold. It is deasserted when enough bytes are removed from the buffer to lower the data level back to the trigger threshold. Operation Figure 10-1 shows the format of a UART data frame. Figure 10-1. Example UART Data Frame](https://usermanual.wiki/Sensitech/T11012087/User-Guide-1121184-Page-37.png)
![© SENSITECH INC. CONFIDENTIAL – CONTROLLED DOCUMENT Page 38 of 83 A Carrier Corp. Company PART NUMBER T82002163 REV A The receive-data sample counter frequency is 16 times the value of the bit frequency. The 16X clock is created by the baud-rate generator. Each bit is sampled three times in the middle. Shaded bits in Figure 10-1 are optional and can be programmed by software. Each data frame is between 7 and 12 bits long, depending on the size of the data programmed, whether parity is enabled, and the number of stop bits. A data frame begins by transmitting a start bit that is represented by a high-to-low transition. The start bit is followed by from 5 to 8 bits of data that begin with the least significant bit (LSB). The data bits are followed by an optional parity bit. The parity bit is set if even-parity is enabled and the data byte has an odd number of ones, or if odd parity is enabled and the data byte has an even number of ones. The data frame ends with 1, 1½, or 2 stop bits, as programmed by software. The stop bits are represented by 1, 1½, or 2 successive bit periods of logic 1. Each UART has two FIFOs: one transmit and one receive. The transmit FIFO is 64 bytes deep and 8 bits wide. The receive FIFO is 64 bytes deep and 11 bits wide. Three bits are used for tracking errors. The UART can use non-return-to-zero (NRZ) coding to represent individual bit values. To enable NRZ coding, set IER[5]. A bit value of 0b1 is represented by a line transition, and 0b0 is represented by no line transition. Figure 10-2 shows the data byte 0b0100_1011 in NRZ coding. The byte’s LSB is transmitted first. Figure 10-2. Example NRZ Bit Encoding—0b0100_1011 Reset The UARTs are disabled on reset. To enable a UART, software must program the GPIO registers (see Section 24, “General-Purpose I/O Controller”), then set IER[UUE]. When the UART is enabled, the receiver waits for a frame-start bit and the transmitter sends data if it is available in the Transmit Holding register. Transmit data can be written to the Transmit Holding register before the UART unit is enabled. In FIFO mode, data is transmitted from the FIFO to the Transmit Holding](https://usermanual.wiki/Sensitech/T11012087/User-Guide-1121184-Page-38.png)
![© SENSITECH INC. CONFIDENTIAL – CONTROLLED DOCUMENT Page 42 of 83 A Carrier Corp. Company PART NUMBER T82002163 REV A are 53 sources for this interrupt. Each of the 24 endpoints (0 and A–X) has two interrupts: packet complete and FIFO error. In addition, the UDC has five interrupts that can be generated based on USB activity. The interrupt sources are shown in the UDC Interrupt Status registers, which must be read to determine the cause of the interrupt being generated. In addition, USB activity can be determined by reading the UDC Interrupt Status registers. If polling is used, the Endpoint Control/ Status registers can be read to determine activity on the USB. The UDC Interrupt Control registers contain interrupt-enable bits that enable the generation of the UDC interrupt. When an interruptible event occurs, the appropriate status bit in the Endpoint Control/Status register is set, and if the corresponding interrupt-enable bit in the Interrupt Control register is set, then the appropriate bit in the Interrupt Status register is set and an interrupt is generated. An interrupt is cleared by setting the appropriate bit in the Interrupt Status registers Endpoint 0 is the only control endpoint and the only bidirectional endpoint in the UDC, and has characteristics different from the programmable endpoints A–X. Key characteristics of endpoint 0 include the following: • Control/Status, Byte Count, and Data registers • Configuration is fixed and does not use a configuration register • Enabled for every USB configuration and interface • Bidirectional endpoint with 32 bytes of USB data-storage space allocated in the endpoint memory: 16 bytes of FIFO memory are used for IN data and 16 bytes are used for OUT data • USB data space is not double-buffered. • Only endpoint configured and available for USB operation after USB reset, and before the USB host controller has enumerated the UDC The Endpoint 0 Control/Status and Byte Count registers provide the status of the endpoint 0 IN and OUT buffers. The Receive FIFO Not Empty bit (UDCCSR0[RNE]) and OUT Packet Complete bit (UDCCSR0[OPC]) are set when a complete data packet has been received from the USB host controller. If the packet is part of a SETUP transaction, the Setup Active bit (UDCCSR0[SA]) is also set. The endpoint 0 transmit FIFO is flushed by the UDC after receiving an OUT data packet from the USB host controller. The Byte Count register (UDCBCR0) indicates the number of bytes of data that need to be unloaded from the receive buffer. As data is read from the endpoint 0 receive buffer using the Endpoint 0 Data register UDCDR0, the Byte Count register value is decremented to indicate the number of bytes remaining in the buffer. When all of the data has been unloaded from the receive buffer, UDCCSR0[RNE] is cleared by the UDC to indicate the receive buffer is empty. After reading all of the data from the endpoint 0 receive buffer, software must clear UDCCSR0[OPC] to enable the buffer to receive another USB data packet. Loading a maximum packet size of 16 bytes into the endpoint 0 transmit FIFO automatically sets UDCCSR0[IPR]. If less than 16 bytes are loaded into the endpoint 0 transmit FIFO, UDCCSR0[IPR] must be explicitly set to indicate a complete packet has been loaded. When the data has been transmitted to the USB host controller, the UDC clears UDCCSR0[IPR] to indicate the packet has been sent Each of the 23 programmable endpoints, referred to as endpoints A–X, has a Configuration register, Control/Status register, Byte Count register, and a Data register. The Configuration registers set the configuration, interface, alternate setting and endpoint numbers, and maximum packet size, as well as enable double-buffering for each endpoint. The Configuration registers can be written only when the UDC is not enabled (UDCCR[UDE] is clear). When UDCCR[UDE] is set, the endpoint configurations are loaded into the USB interface block and are set to read-only access. The Control/Status, Byte Count, and Data registers control the operation of each endpoint after enumeration. If an endpoint has double-buffering disabled, the Control/Status and Byte Count registers provide the status of the endpoint buffer. If the endpoint is configured as an OUT](https://usermanual.wiki/Sensitech/T11012087/User-Guide-1121184-Page-42.png)
![© SENSITECH INC. CONFIDENTIAL – CONTROLLED DOCUMENT Page 44 of 83 A Carrier Corp. Company PART NUMBER T82002163 REV A remote wake-up feature of the UDC, after the UDC has entered the suspend state, sending a wakeup signal to the USB host controller is performed by setting UDCCR[UDR]. Doing so forces the UDC to drive a non-idle state (K state) onto the USB for 3 milliseconds without further user intervention. The UDC hardware then clears UDCCR[UDR]. The UDC waits for the resume signal to be reflected back to it by the USB host controller, and when the resume state is detected on the USB, if the resume interrupt is enabled, an interrupt is sent to the processor. The USB host controller can wake up the UDC by driving the non-idle state (K state) either by driving a resume or USB reset onto the USB. When the UDC pads detect this non-idle state on the USB, they signal the processor clock manager module to start the 48-MHz clock to the UDC, and (if the resume interrupt is enabled) an interrupt is sent to the processor. Software must take the appropriate action to resume activity. Sleep Mode Operation If the UDC has entered the suspend state before the PXA27x processor is in sleep mode, the UDC pins USBC_P and USBC_N are used to detect the resume state on the USB and resume operation while the processor is in sleep mode. If the USB host controller tries to access the UDC when the processor is in sleep mode, the USBC_P and USBC_N pins detect the resume state and signal the processor to begin the wake-up sequence. The UDC will have lost all state information and the UDC Configuration registers must be reloaded prior to setting UDCCR[UDE]. The USB host controller must issue a USB reset and re-enumerate the UDC. If the UDC has been disconnected from the USB and the processor is in sleep mode, a GPIO pin must be programmed to detect connection to the USB and to signal the processor to begin the wake-up sequence. The GPIO pin must be connected through a level-shifter to the USB power signal to detect connect/disconnect to the USB. The UDC will have lost all state information and users must load the UDC Configuration register and enable the UDC before the UDC is ready for USB operation. USB On-The-Go Operation The processor USB device and host controllers can be used to provide A- and B-device On-The-Go (OTG) operation as specified in the On-The-Go Supplement to the USB 2.0 Specification. The onchip OTG transceivers provide on-chip pull-up and pull-down resistors as specified in the Pull-up/ Pull-down Engineering Change Notice to the USB 2.0 Specification. OTG operation requires user intervention but interrupts are provided to notify the user of OTG activities including Vbus changes, session detection, and OTG ID changes. The user must use these interrupts along with the OTG control and status registers to operate as an OTG device. The UDC OTG support includes the following: • Decoding of SET_FEATURE commands with OTG specific selector values • Control for on-chip OTG transceiver with multiplexing between UDC and USB host controller (UHC) port 2 • Control for multiplexing between UDC, UHC port 2 and UHC port 3 data through GPIOs • Control, status and interrupt registers for interfacing to off-chip OTG transceivers • Control, status and interrupt registers for interfacing to off-chip charge pump devices • OTG ID support Figure 12-15 shows each of the configurations provided to support OTG operation. Each of these is](https://usermanual.wiki/Sensitech/T11012087/User-Guide-1121184-Page-44.png)
![© SENSITECH INC. CONFIDENTIAL – CONTROLLED DOCUMENT Page 46 of 83 A Carrier Corp. Company PART NUMBER T82002163 REV A Figure 12-16. Host Port 2 OTG Transceiver Interface to External OTG Transceiver In the case where the user does not use the internal OTG transceiver, the UDC contains control, status, and interrupt registers to provide seamless interfacing to external transceivers. External transceivers can be used to provide D+, D–, and Vbus driver to the USB. In this mode, the USB D+ and D– signals are output through GPIO pads with UP2OCR[SEOS] used to control multiplexors to select between UDC and USB host controller D+, D–, and transmit enable signals. In addition, the USB Port 2 Output Control Register (UP2OCR) provides the external transceiver suspend (EXSUS) and external transceiver speed (EXSP) control output bits, and the external transceiver interrupt input to interface to the external transceiver. Figure 12-17 illustrates the OTG connection to an external transceiver. Figure 12-17. Connection to External OTG Transceiver](https://usermanual.wiki/Sensitech/T11012087/User-Guide-1121184-Page-46.png)
![© SENSITECH INC. CONFIDENTIAL – CONTROLLED DOCUMENT Page 47 of 83 A Carrier Corp. Company PART NUMBER T82002163 REV A Note: For Figure 12-17, UP2OCR[SEOS] = 4 for USB client and UP2OCR[SEOS] = 5 for USB host. Interface to External Charge Pump Device In addition to the interface options described in Section 12.5.4, the UDC provides control outputs and interrupt inputs to drive and monitor an external charge pump device. To do so, the USB D+ and D– signals can be output using the on-chip OTG transceiver and the Vbus interface provided by an external charge pump device. In this mode, UP2OCR[HXS] is used control multiplexors to select between UDC and USB host controller D+, D–, and transmit enable signals to be output through the USB host controller port 2 transceiver. In addition, USB Port 2 Output Control Register (UP2OCR) provides the charge pump Vbus enable (CPVEN) and charge pump Vbus pulse enable (CPVPE) control output bits used to enable the driving of Vbus and to enable the driving of pulses on Vbus, respectively. Additionally, USB Port 2 Output Control Register (UP2OCR) provides the Vbus valid 4.0-V, Vbus valid 4.4-V, session valid, and session request protocol detected interrupt inputs to interface to the external charge pump device. Figure 12-18 illustrates the OTG connections to an external charge pump device. Figure 12-18. Connection to External OTG Charge Pump](https://usermanual.wiki/Sensitech/T11012087/User-Guide-1121184-Page-47.png)
![© SENSITECH INC. CONFIDENTIAL – CONTROLLED DOCUMENT Page 49 of 83 A Carrier Corp. Company PART NUMBER T82002163 REV A Functional Description The Memory Stick system, depicted in Figure 17-1, consists of the memory stick host controller and an attached Memory Stick card. Figure 17-1. Memory Stick System Block Diagram The memory stick host controller interfaces with the Memory Stick using a 32-bit internal application interface. It allows: • Sending of transfer protocol commands (TPCs) to the Memory Stick using the MSHC Command register. • Data transfer using the two separate receive (RX) and transmit (TX) FIFOs (this data can be transferred using polling, interrupts to the processor, or DMA). • Responding directly to Memory Stick interrupts by issuing a predefined command, the AutoCommand (ACD). • Placing the card into a low-power mode. Interrupts The memory stick host controller generates a single interrupt to the interrupt controller. The cause of the interrupt can be determined by reading the Interrupt and Status register. Status bits in this register indicate which event caused the interrupt to be generated. Interrupts can be disabled (either individually or in total) by setting bits in the Interrupt Enable register. To process an interrupt, MSINTEN[INTEN] must be set, and the enable bit for the specific interrupt in register MSINTEN must be set. It is possible for multiple secondary interrupts to occur if more than one MSINTEN register bit besides INTEN are set. To determine the specific cause of the interrupt, read the Interrupt and Status register, MSINT. To handle more than one interrupt at a time, set MSINTEN[INTEN] and the specific MSINTEN interrupt enable bits. Memory Stick Insertion and Removal The nMSINS signal indicates the insertion and removal of a Memory Stick. nMSINS is connected to the interrupt controller, but not to the memory stick host controller. Thus, the interrupt controller must be programmed to generate an nMSINS interrupt.](https://usermanual.wiki/Sensitech/T11012087/User-Guide-1121184-Page-49.png)
![© SENSITECH INC. CONFIDENTIAL – CONTROLLED DOCUMENT Page 50 of 83 A Carrier Corp. Company PART NUMBER T82002163 REV A Software must monitor the nMSINS interrupt. When an interrupt occurs due to the removal of the memory stick, the software must halt all MHSC activity and reset the memory stick host controller. Reset The memory stick host controller is reset in either of two ways: • Any PXA27x processor reset causes all of the MSHC registers to be reset. • Setting MSCRSR[RST] causes the memory stick host controller to enter and remain in reset until MSCRSR[RST] is cleared. In this case, all of the registers except for the RST bit are reset, and the output signals BS, SDIO, and SCLK are driven low. Any currently-executing protocol is terminated when MSCRSR[RST] is asserted. These methods do not cause a reset TPC to be sent to the Memory Stick. Note: Before writing any of the control registers for a new bus protocol, always set MSCRSR[RST] and then clear it. Power-Save Mode When the memory stick is not being used, software may optionally place it into a low-power mode. This is controlled entirely by software and is not related in any way to the PXA27x processor lowpower modes. Figure 17-2 shows how to enter and exit the Memory Stick power-save mode. To maximize overall system power saving, software must place the Memory Stick in power-save mode prior to entering any of the system low-power modes.](https://usermanual.wiki/Sensitech/T11012087/User-Guide-1121184-Page-50.png)
![© SENSITECH INC. CONFIDENTIAL – CONTROLLED DOCUMENT Page 73 of 83 A Carrier Corp. Company PART NUMBER T82002163 REV A Motor driving pulse rate: Motor driving speed varies with driving voltage. It is determined with the following formula: Motor driving speed (pps) = [200 * (Vp) – 600] Therefore, for our application Vp = 6.25VDC. As a result, [200 * (6.25) – 600] = 650 pps 11.0 Control Board Dip Switch Setting: Pin No. Function ON OFF DS1-1 Auto Cutter X 1-2 CR Selection X 1-3 Print Density X 1-4 DTR/XON-XOFF X 1-5 Baud Rate X 1-6 Baud Rate X 1-7 Baud Rate X 1-8 Baud Rate X](https://usermanual.wiki/Sensitech/T11012087/User-Guide-1121184-Page-73.png)
![© SENSITECH INC. CONFIDENTIAL – CONTROLLED DOCUMENT Page 80 of 83 A Carrier Corp. Company PART NUMBER T82002163 REV A 8.2.2 Formatting YAFFS Partitions All file systems need to be formatted before they can be mounted. Because YAFFS was designed from the ground up to work with embedded flash technologies, it understands an 'erased' flash device to be both formatted and empty. To prepare your partition for mounting, simply use LogicLoader's 'erase' command to erase the area of flash where the partition is to be located. Using the example partition scheme in the “Developing a Partition Scheme” section, above, the partitions could be prepared for initial use by erasing the regions of the flash device spanned by them. For example (LH7A404-11 system address used): losh> erase 0x000C0000 0x00800000 losh > erase 0x00900000 0x00400000 Warning: Erasing flash blocks that will be used for YAFFS partitions will erase everything in those areas of flash. It is not required to format the partition every time the device is rebooted. The partition should only be formatted when an entirely new YAFFS partition is created, or when the data on a stored partition needs to be completely erased. 8.2.3 Adding YAFFS Type Partitions LogicLoader maintains a partition table in RAM. Before a YAFFS partition can be mounted, it must be added to the partition table. To do this, the 'add-yaffs' command is used. The 'add-yaffs' command takes the following arguments: • <name> a unique string which identifies the partition • <type> type of flash device the partition resides on • <start> the physical starting address of the partition • <length> the length (in bytes) of the partition Continuing with the example partitions above, LogicLoader can be instructed to add the partitions by executing the commands as shown below (LH7A404-11 system address used): losh> add-yaffs boot nor 0x000C0000 0x00800000 losh> add-yaffs data nor 0x00900000 0x00400000 Note: The above steps must be performed every time LogicLoader boots. Because LogicLoader keeps the partition table in RAM, the existence and locations of YAFFS partitions does not persist across resets or power cycles. 8.2.4 Mounting the Partition To mount a partition in the partition table, the 'mount' command is used. That command takes the following arguments: • <fstype> the type of filesystem being mounted (‘yaffs’ here) • [drive addr] not used when mounting a YAFFS partition • <point> the name of the YAFFS partition For example: losh> mount yaffs /boot](https://usermanual.wiki/Sensitech/T11012087/User-Guide-1121184-Page-80.png)
