Sharp Mz 3500 Users Manual
MZ-3500 to the manual 30945b32-ab8c-422f-a17d-e85d340b9cd3
2015-01-23
: Sharp Sharp-Mz-3500-Users-Manual-285119 sharp-mz-3500-users-manual-285119 sharp pdf
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MZ-3500
SERVICE MANUAL
CODE: OOZMZ 3500SM/E
PERSONAL COMPUTER
MODEL
Z-350
CONTENTS
1. Specifications
2. Software (Memory) Configuration
3. CPU and memory
4. CRT display
5. MFD interface
6. R232C interface
7. Printer interface
8. Other interface
9. Power circuit description
10. Keyboard controller circuit discription
11. Self check functions
12. IPL flow chart
13. Circuit diagram & P.W.B
Parts list & Guide
SHARP CORPORATION
1
7
12
25
52
72
yg
81
gy
90
94
103
M 7 3500
1. SPECIFICATIONS
1-1. Specification of the main unit (Model 35XX)
Outline
1)
2)
3)
4)
High speed processing using multi-CPL'
Built in mini floppy disk
Built in printer interface and RS232C Aerial interface
Connection of up to two video displa, mitt (separate graphic display or overlaid display possible on two individual color
monitor units)
5) Permits the use of standard CP/M
Model 3530 incluse a single double-side, double density mini floppy
disk and 64 KB RAM.
Model MZ3540 has two double-side, density mini floppy disks and
64 KB RAM.
CPU
Multi-CPU processing
MEMORY
Z80A microprocessor x 2
8K Byte ROM
IPL
ROM
RAM
C, G
8K Byte ROM
For main CPU
64K Bit DRAM x 16 chips or 8 chips
For sub-CPU
16K Bit SRAM x 4 chips
Shared RAM
16K Bit SRAM x
VIDEO
RAM
16K B't SRAM x 1 chip
4K Bit SRAM x 2 chips
Memory mapper
LSI
Model 3531 includes a single double side,
double density mini floppy disk and 128 KB
Model 3541 has two double side, double
density mini floppy disks, and 128 KB
TH
1 chip
SP6102R001
Custom LSI
Screen controller
CSP-1 SP6102C002
CSP 2 SP6102C003
GDC
CRT controller
MPD7220
FDC
Floppy disk controller
pPD765
PIO
Parallel I/O port
8255
SIO
Serial I/O port
8251
TIMER
Counter
8253
CLOCK
Clock
/iPD1990AC
Screen structure
80 characters x 25 lines. 80 x 20, 40 x 25. or 40 x 20
Elements
Attribute
8 x 16,8x8
Reverse, blink, line (horizontal, vertical)
Colors
8 colors on each character and background color
I/F
2 channels (applicable CRT 640 x 400, 640 x 200, B/W or color)
MZ353X
One double-side,
double density
floppy disk
256 bytes/sector, 16 sectors/track, 80 tracks/disk
MZ354X
Two double-side,
double density
floppy disks
Built-in interface for optional MFD
I/O
DISPLAY
MFD
Light pen
Other I/F
Other
functions
Keyboard
Dedicated keyboard
Printer
Centronics interface
RS232C
No protocol, asynchronus mode, 110 to 9600 bps, half-duplex
Speaker (500mW)
Battery backup clock
BASIC
HALT SW
Speaker volume control
High class compatible with PC3200 BASIC, supplemented and graphic
control commands
Expanded RS232C, GPIB, and GPIO
FDOS
Software
Utilities
CP/M
Accessories
Basic CP/M
Expanded CP/M
Intstruction Manual
master floppy disk
power cord
BACKUP, INIT, COPY, DEBUG, KILLALL
MZ3500
1-2. MZ-1K01 (Keyboard) specification
Outline
MZ1K02 U.S. keyboard (ASCII)
MZ1K04 German keyboard
MZ1K03: U.K. keyboard (ISO).
MZ1K05: French keyboard
Keyboard controller
80C49 or 8749
CMOSIC
4049x2,4514
LSI, 1C
Sculpture key
Keys (98)
Mechanical contact key, with life of 10,000,000 operations.
Alphanumeric keys
Mode switch
Interfacing cables
Ten key
61
15
Function keys
6
Definable keys
1
For data transfer with the CPU (serial) and power supply (transmission under 15,000 baud)
Use of coiled cable with 8-pin DIN plug
Specification
Repeat function
Automatic repeat occurs 0.64 seconds after
. . . .
.
continuous depression of the same key.
Indicators (4 LED's)
POWER, Alphanumeric keys
Other
Molded
Cabinet
Color
2
Two-key rollover
Office gray
Size (W x H x U
467 x 35 x 190
Weight
| About 1 .5kg (3.3 Ib)
Keyboard layout
Refer to the page TIN "CIRCUIT DIAGRAM"
1-3. MZ-1U02
Outline
Expansion unit for the MZ-3500 series CPU, which can be attached to the rear side of the main unit.
Optional boards are plugged in to the expansion box.
The expansion box will accomodate up to four option boards.
Number of slots: 4 slots
Slot connector. 60-pin edge connector x 4
Specifications
Area of the slot inserting option board: 140.5 x 140
Slot for option and slot number
Slot 1
MZ-1R06
(expansion RAM)
Slot2
o
Slot 3
O
o
SFDI/F
Slot 4
O
Expansion RS232C
o
o
O
0
GPIO
o
o
o
o
GPIB
(IEEE I/F)
o
0
o
o
-2-
10
MZ3500
Expansion unit
Screw (1)
1-4. MZ-IR03
Outline
Optional board used graphic display functions with the Model-3500 series CPU. It includes 32KB of RAM.
It is inserted through the slot on the front panel of the PU.
The MZ-1U02 expansion box is not required.
GDC
LSI
Graphic controller
vinrn HAM
Specifications
~~~~~
Graphic functions
(Color must be
specified for each
dot. when the color
video unit is in use)
MPD7220
Basic (buit-in)
16KDRAM x 16 (32KB)
Expansion
(optional)
16KORAM x 32 (64KB)
—_ _ _ _ W D E O RAM
640 x 200
green monitor
640 x 200
color monitor
32KB
(basic)
96KB
(maximum expansion)
640 x 200 dots
Two screens
640 x 200 dots
Six screens
640 x 200 dots
Two screens
_____
640 x 400
green monitor
640 x 400 dots
One screen
640 x 400
color monitor
^______-
BASIC graphic control statements
Software
-3-
—
640 x 400 dots
Three screens
~"
640 x 400 dots
One screen
SDISP
Screen designation for two video units.
ODISP
Designation of output screen.
CHANGE DISP
Mode designation
GCOLOR
Graphic pattern designation
CLS
Cleared by the color specified.
PSET
Dot set
PRESET
Dot reset
LINE
Line creation
GTABLE
Table creation
CIRCLE
Circle creation
PAINT
Paint over
GINPUT
Input of graphic pattern
GDISP
Display of graphic pattern
GPRINT
Output of graphic pattern on printer
GREAD
Read of coordinates
CENTER
Input of pattern within the specified area
GCURSOR
Graphic cursor position designation
GSCROL
Graphic screen scrolling
SYMBOL
Graphic symbol displaying
SCALE
Scren scle-down designation
MZ3500
1-6. MZ-1R06
Outline
Optional board for memory expantion of the MZ-3500 sries CPU. with this option the main memory (RAM) can be expanded
up to a maximum of 256 KB.
This option plug into the expantion box in slot 1 or 3.
LSI
Specifications
Basic
64KDRAM x8 (64KBI
Expansion
64KDRAM x8 (128KB)
Memory and user
area
Main CPU only Use of MZ-1R06 Using eight 64K RAM's
on theMZ-1R06
Total capacity of
the main CPU RAM
SYSTEM
AREA
BASIC:
(RAM
USER
BASE
'
AREA
128 KB
192 KB
256KB
• 57 KB
«-
*-
128 KB
208 KB
80 KB
- 4-
MZ3500
1-7.
MZ-1D07
Outline
High resolution MZ 3500 series 12 green monitor
Video tube
Type
Non glare green
Size
12", 90" deflection
Display capacity
640 horizontal dots,
400 vertical lines
Vertical
47 8 Hz
Weight
7.2kg
Fluorescent color P39 (green, long PERSISTANCE)
Display capacity
Total number of
display characters
Display size
220 x 145
2,000 characters
(80 characters x 25 lines)
Specifications
Method
Separate input, TTL level
Horizontal
20 86kHz
Input signals
Power supply
29W power consumpt ion
Molded
Color
Office gray
Cabinet
Size (W x H x U
324x310x356
Adjusting knobs
3
Accessories
CPU connection cable and power cord and Tilt stand
Vertical synchronization, contrast, brightness
r
- 5-
MZ3500
1-8. System configuration of Model 3500
Keyboard
MZ-1K02
MZ-1K03
MZ-1K04
MZ-1K05
Printer
IO2824E
I
I
6
I
Option MFDI
CE-331M |
I
"Model-3541 = Model-3531 + MZ-1F03
'
I
I
MZ3500
2. SOFTWARE (MEMORY) CONFIGURATION
Memory will be operated under four states of SDO ~ SD3,
depending on the hardware and software configurations.
In the paragraphs to follow, description will be made for
those four states.
2-1. SDO (INITIALIZE STATE)
SDO can only exist immediately after power on, and the
system executes IPL under this condition and that the
system thus loaded will automatically assign memory area
for SD1, SD2. and SD3.
MAIN CPU
SUB CPU
MAS
0
MAI
0
0
0
0
0
1
MA2
MAO
0
1
1
V
FFFF
1
MS1
= ° (D
MSO = 0 (L)
1
FFFF
T
? IRAM(COM^
jOO11——
^\
reoo
RAMA
RAMA
cooo
BFFF
\\
u
\\
\\
RAMA
8000
7FFF
\\
N
ROM
(SPAPE)
v
V
\
\
RAMA
4000
3FFF i
4000
| ROME [
I
I
2000 I
'
27FF
RAM (COM)
ROM
IPL
OFFF
0000
2000
1 FFF
ROM
JPL
0000
*7
M 7. 3500
Operational description
(1) Upon reset after power on, the main CPU loads the
contents of the initial program loader (IPL) into RAM
starting at address 4000H, during which time reset is
applied to the sub-CPU.
(2) The main CPU then terminates resetting the sub CPU
and starts the sub-CPU. At the same time, the ROM
IPL is assigned to the sub-CPU.
(3) The main CPU then send the memory allocation (state)
to SD1, and starts to load DOS from the system floppy
disk.
TIMING OF RESET SIGNAL
VtcSYSKES-
Signal generated from the
CR network and power supply
SKES-
Output signal from the main CPU port
pr)WFjJSUB
PO E
CPU
* ^ START
POWER
OFF
MAIN CPU
START
a. Main CPU reset time
b. Main CPU IPL load time
Memory Map Data:
1. ROM-B is tested to determine if ROM's are present.
2. The ROM-IPL functions under control of the main CPU
at first, but later it functions under the sub-CPU after
the IPL program has been loaded in RAM.
3. RAM-COM is shared by both the main CPU and the subCPU.
INITIALIZE FLOW
«TABT
4. Memories other than described above cannot be accessed
under the SDO state.
5. Bank select, MAO~MA3, is used within the address range
ofCOOOH-FFFFH.
MZ3500
ROM-IPL
1. An 8KB ROM (2764 or mask ROM equivalent) is used
2.
3.
4.
5.
Mam CPU logical address (during IPL operation)
Logical address of the sub-CPU
for the ROM-IPL.
When the system reset signal turns from low to high
state after power on, the main CPU starts to operate At
this stage, the ROM-IPL is addressed.
The CPU starts from address OOOOIROM address 10000)
The main CPU sets the sub-CPU reset signal from low to
high state as it goes out of its initial state via the memory
mapper and the sub-CPU starts to operate. At this point,
the ROM-IPL is addressed by the sub-CPU.
Address 0000 of the sub-CPU is ROM address (0000)
The memory area above ROM address (1000) cannot
be used by the sub-CPU because the mam CPU initial
program has been loaded there.
ROM physical address
OfFF
1 FFF
1 FFF
0800
1 800
1 7FF
1 800
I 7FF
ROM IPL
0000
1 OOP
OFFF
1 OOP
OFFF
0800
07FF
0800
07FF
0000
0000
2-2. SD1 (SYSTEM LOADING & CP/M)
SD1 determines which operating system ts in use. The
system is loaded in the CP/M (Control Program for Microprocessors) mode.
MS1 = 0( L)
MSO=l(Hj
M A I N CPU
rr
F?'
r
RAMicnu: \
\
> \
^
x
\
V
4
\
^\
3
\\
\\
\\
\\
\\
\\
\\
\\
\\
\\
i
RAM
sn
RAM
SA
KAM«.(IH) 2000
1FFF
f. ft f
n
-9-
MZ3500
Operational description
(1) As soon as the sub-CPU is started, it initializes the I/O
port and waits for program transfer (IOCS) from the
main CPU. This IOCS (Input Output Control System)
is the program resident at address 4000H-5FFFH.
(2) As the main CPU loads the information from sector
"1" of track "0" of the floppy disk, it loads the IOCS
and bootstrap routine to the sub-CPU.
(3) The bootstrap program is loaded next.
(4) The bootstrap program determines rnemory allocation.
Communication between Main and SUB CPU
BUSRQ
H
OUTPUT
(ISOLATION OF COM RAM)
|
2:3. SD2 (ROM based BASIC)
SD2 is active when "SHARP BASIC" is executed via ROM.
MAIN
M A S
BANK
SELECT
0
0
M A 2
°
MAI 0
°
0
MAO
1
0
FFFF
0
0
1
0
1
i\
1
1
1
I
1
1
0
0
0
0
1
1
0
I
0
0
1
I
0
1
0
1
0
1
0
1
0
1
KAMB
4
Sffi
0
1
I
0
I I I
R\MA
i
.
0
0
0
1
0
0
0
1
1
1,
MS] = I (H)
MSO = 0 Li
CPU
1
1
1
4
3|
11
2|
3,
4
3
2
IFF?
ROME
IFF?
J
ROMC
ROMU
ROM!
ROM 2
ROMA
0000
(MO2
M
M
0
O
O
0
1
O
0
0
0
0
0
1
1
1
1
0
0
1
1
KAMI!
K \M L
2,
1
0
1. Bank select, MAO~MA3. is effective for memory area COOOH-FFF FH.
2. Bank select, MOO~MA2, is effective for memory area 2000H-3FFFH
- 10 -
11
2,
3 |
4
SUB CPU
MZ3500
2-4. SD3 (RAM based BASIC)
SD3 is active when "SHARP BASIC" is ececuted via RAM.
"SHARP BASIC" is loaded in RAM from the floppy disk.
MSI = 1< H)
MAIN CPU
RAM
BANK
SELECT
MAS
0
0
0
0
0
0
MA2
0
0
0
0
1
1
MAI
0
0
1
MAO
0
1
Ffft
0
1
0
1
0
0
0
1
0
I
1
1
1
I I I
)
0
I
I
0
0
1
!
0
0
1
0
1
0
1
1
1
1
1
lRwnuf%
\\
I I I
RANC
SUB CPU
1
0
0
I I I
RAMB
\
MSO = HH)
KAMI)
r
1
v\
\v
1
2
,
3
,
4
1
,
2
,
3
,
4
1
,
2
,
3
gFFF
4
\ \
\\
N\
-
vx
\\
\\
\ ,
,
RAMA
ROM!
ROM2
KOM3
K(IM4
1FFF
RAN. SP
RAN SC
RAM SB
\\
0 0 0
0
0
'
ROM 1 PI
0000
0
1
0
1
"
0
)
i
]
1
0
0
1
1
0
1
0
1. Bank select, MAO-MA3. is effective for memory area COOOH-FFFFH.
2. Bank select, MOO-MO2, is effective for memory area 2000H-3FFFH.
Operational description
The state of the system is determined by the bootstrap
program before the load of the system program.
KU
"°
ROM BAS
k
]L
ROM M02
[NOI
BANK
SELECT MOO
,
SUB CPU
3. CPU AND MEMORY
3-1. Block diagram
1) Relation between MMR (Main Memory Mapper) and
main memory.
I
RECEI VFR
, RAM
I
(II'TION
1
4-
RAN
VI
' 64KBV2)
°l
1
OPTION
1
.
||
I
'7220
i
JK» 2K*
J
(, , A P M , C
{)
R
MPXR
VIIIK1 RAM
32KB
V 1 HI O RAM
32KB
It
Ml DM1 I MO*J
OK II K U MO* 400
kl Mil I 1 ION
V I D H ) RAM
32KH
L
si v i (.us TOM
1 SI CSI -2
SEMI CUSTOM
IS! CSI'-I
RS-232C l/f
MZ3500
3-2. Main CPU and I/O port
r^
IX
M
A
I
N
Connector
I PC 2
|~^T
1
A2
A3
""
~s
j^
A4
—££-1
A6
M
C
P
A
v~\
P
r (jtA.
v
f^-r-^r-.—r
Y 1 ~~>
\J> -•> r DL
iZ
\J I Obr
J
This paragraph discusses main CPU I/O
Port select and addressing.
The address output from the main CPU
is decoded in the 74LS138 to create the
select signal.
Table below describes address map and
signal functions.
Y3
C
-)
Y4 J
IORQ
f\
-\J
G2 B
u
Y5 ^
0 MFUC
Mi
Ol
• \J lUMr
Y6
5
O IOABCMEMORY MAPPER)
74LSI38
ADDRESS
A7
A6
A5
A4
A3
A2
A1 AO
0
0
0
0
0
0
0
0
00
0
0
0
0
0
0
0
1
01
1
1
0
1
1
1
1
0
DE
1
1
0
1
1
1
1
1
DF
^
^
^
Q
o
o
x
x
HEX
NOT USE
EO
NOT USE
E3
E4
^
^
^
Q
O
•
^
x
x
SFD interface FDC chip select.
SFDC (UPD765)
E7
AO used for RD and WR.
A1 is "don't care".
E8
i
i
i
o
t
o
x
x
IOSF
SFD interface I/O port and DMAC chip select.
EB
EC
1
1
1
0
1
1
X.
X
Interrupt signal from the sub-CPU to the main CPU.
INTR
Flipflop resetting signal.
EF
FO
1
1
1
1
Q
O
X
X
NOT USE
F3
F4
1
1
1
1
0
1
X
MFDC (UPD765)
X
MFD interface FDC chip select.
F7
F8
1
1
1
1
1
0
X
MFD interface I/O port.
IOMF
X
FB
AO used for RD and WR.
AT is "don't care".
FC
1
1
1
1
1
1
X
IOAB (MEMORY MAPPER)
X
FF
I/O port select in the memory mapper.
AO and A1 used during ~W5. WR.
MZ3500
3-3. Sub CPU and I/O port
SUB
AS6
5
ASS
2
AS4
i
Y6
CPU
Y4
4G
4_
AST
J
s07
~9
S06
_JQ
J
SOS
.Jl
SO4 ^ .
012
S03
,.
D15
S 2
HEC3 -C*
*.
^
r CKP 1 . CSP 2
.
Shown at the left is the circuit used by
the CPU to select the I/O ports The out
put address from the sub CPU is decoded
by the 74LS138to create the select signal.
Shown below is the address map and
select signals.
......
-^
*""
5
"MT
6
Gl
Yl
YO
14
°
-^
"SOT
D15 '*°° r MAIN CPU \m
74LS138
8
8
AS 7654 M £X\
0000
1
8
8
Signal description
2 3 4 5 6 7 8 9 A B C D E F
soo
Output signal to set the flipflop to apply interrupt (INTO) to the
main CPU. Enables communication between CPU's.
8251 SIO chip select.
0001
S018251
ASO is used for data control selection.
AS1, AS2, and ASS are "don't care".
8253 counter chip select.
0010
S02 8253
ASO and AS1 are used for programming during write.
AS2 and ASS are "don't care".
8255 PIO chip select.
0011
S03 8255
ASO and AS1 are used for port/control selection.
AS2 and ASS are "don't care".
8-bit input port.
0100
S04 input port select
Used for read.
AS3 are "don't care".
CRT control I/O port chip select.
0101
AS1, AS2, and ASS are used for write.
805
ASO is "don't care".
UPD7220 (graphic) chip select.
0110
ASO is used for read and write.
S06
AS1, AS2, and AS3 are "don't care"
UPD7220 (character) chip select.
0111
S07
ASO is used for read and write.
AS1, AS2, and AS3 are "don't care"
1000
1001
1010
1011
1100
NOT USE
1101
1110
1111
- 18-
MZ3500
3-4. Memory mapper (MMR) SP6102R-001
1) Block diagram
Memory mapping logic
ADDRESS BUS
AO . i. is.
COAB
A 15
A15
A14
AI3
A]
AO
AU
COAB
MKEQB
RFSH
~L
I/O
CONTROL BUS
MERQ
RFSH
RD
"WR
PORT
LOGIC
RB
—L -
n
OAB
DATA BUS I— \
DO-D7
V
INTB
WAITB
WAIT
TIMING
GENERATOR
INTERRUPT
PRIORITY
ENCORDER
CLK
SYSR
->TO
RESET
1NTFI)
- 19 -
MZ3500
2) Memory mapper (MMR) SP6102R-001 signal description
Polarity
Signal Name
1
ST
2
DO
IN
IN/OUT
9
D7
10
A15
A13
13
A1
Bidirectional main CPU data bus.
(Data bus 0 ~ 7)
Main CPU address bus.
IN
12
Main CPU DRAM output buffer (LS244) switching strap.
Used in the memory mapping logic of the MMR for address output for the DRAM, ROM, and
shared RAM.
IN
(Address bus 13 ~ 15)
Main CPU address bus.
Used in the I/O port select logic of the MMR to assign device number.
Sub-CPU bus request signal.
14
SRES
OUT
•
After power on: Halts the sub-CPU.
•
After write command (LDA-80H: OUT#FD) by the main CPU- Starts the sub-CPU.
This signal is issued after transfer of the main CPU program contained in the ROM-IPL.
(Sub CPU Reset)
Sub-CPU bus request signal.
15
SRQ
OUT
•
After power on: Resets bus request to sub-CPU.
•
After write command (LDA-02H1 OUT#FC) by the main CPU' Place bus request to the sub-CPU
This signal is issued to bus of the sub-CPU, after the main CPU writes to the shared RAM a command
parameter to the sub-CPU or reads the message status from the sub-CPU.
(Sub CPU Request)
16
Address signal to the main CPU dynamic RAM.
AR13
OUT
18
The main CPU address signals, A 13-A 15, merged in the memory mapping logic circuit to produce
AR13-AR15. This is means by which the 4 basic and CP/M memory maps are made, along with MS1
AR15
and MSO.
BASIC interpreter 32KB mask ROM chip select signal.
19
R32
OUT
Valid when SD2 is active (Sharp ROM based BASIC). Command (LDA 02H OUT 3FD)
(ROM 32K select)
Internal MMR I/O port select logic signal.
20
IOAB
IN
Goes low by the command IN/OUT #FC-#FF.
(Input/Output Address)
21
SRDY
IN
22
ROPB
OUT
Input of ready signal from the sub-CPU.
(Sub CPU Ready)
Chip select signal issued from the main CPU to the 8KB mask ROM.
Valid with SDO active (initialize state).
(ROM ipl)
23
ROAB
Chip select signal for four chip BASIC interpreter 8KB EPROM (A. B. C, D).
OUT
26
RODS
Valid with SD2 active (Sharp ROM based BASIC).
"R32B (alternate choice with the 32KB mask ROM chip select signal).
(ROM A~D Buffer)
27
RSAB
~
~
30
RSDB
Row address select signal for the main CPU dynamic RAM (block A-block D).
OUT
RAS (ROW ADDRESS SELECT; LINE ADDRESS SELECT) SIGNAL
(Row address Select)
Input of bus acknowledge signal from the sub-CPU.
31
SACK
IN
command is written in the shared RAM after acknowledgement from the sub-CPU
1
At the end of the command cycle bus request is released and the sub CPU executes the command
/
- 20-
M 7, 3500
Polarity
Pin No.
IN/OUT
Function
Signal Name
Main CPU 128KB dynamic RAM output buffer (LS244) output enable signal.
32
RF1B
OUT
33
RF2B
OUT
34
WATB
OUT
(RAM buffer 1)
Signal identical to R F 1 B
For option RAM
(RAM buffer 2)
Wait signal to the mam CPU
(One wait cycle 15 applied during the memory fetch cycle of the main CPU. It consists of one clock
period)
(WA|T)
Chip select signal issued from the mam CPU to select the RAM shared by the main CPU and
35
RCMB
OUT
the sub-CPU
(RAM Common)
36
ITFB
37
ITOB
IN
IN
Interrupt input from the UPD765 FDC (Floppy Disk Controller).
(Interrupt from Floppy)
Interrupt input from the sub-CPU.
(Interrupt from No. 0)
38
IT1B
IN
39
TT2B
40
MRQB
41
WRB
42
IT3B
IN
IT4B
44
SEC
(Interrupt from No. 1, 2)
Memory request signal from the main CPU.
(Memory Request)
Write signal from the main CPU.
IN
IN
43
Interrupt input from slot 1 or 2.
(Write)
Interrupt input from slot 3 or 4.
(Interrupt from No. 3, 4)
Input from the FDD (Floppy Disk Drive) assignment dip switch (A), No. 1.
IN
'See the dip switch description, provided separately.
(Section)
45
GND
IN
Ground
46
Vcc
IN
5V supply
47
SW1
IN
48
SW2
49
AO
IN
RFSH
IN
50
51
SW3
IN
52
SW4
53
GND
IN
54
FD1
IN
55
Vcc
IN
56
FD2
IN
Input from The s v s t e m assignment dip switch,
"See the dip switch description, provided separately.
Mam CPU address bus
Used rn the I/O port select logic in the MMR to designate device number.
Refresh signal from the main CPU.
(Refresh)
Input from the system assignment dip switch.
•See the dip switch description, provided separately.
Ground
Input from the system assignment dip switch.
'See the dip switch description, provided separately.
5V supply.
Input from the FDD assignment dip switch (A), No. 2.
*See the dip swi'ch description, provided separately.
MX 3500
Polarity
IN/OUT
Pin No
Function
Signal Name
System reset signal.
57
SYSR
IN
Used to reset I/O port in the MMR.
(System Reset)
58
FD3
IN
59
COAB
IN
Input from the sytem assignment dip switch.
"See the dip switch description, provided separately.
Shared RAM select signal.
Address of the shared RAM is *F800-#FFFF for the main CPU
(Common RAM Address)
Select signal for 8KB area allocated to slot 1.
60
RO1B
OUT
Valid when SD2 is active (ROM based BASIC) and SD3 (RAM based BASIC)
(ROM 1)
61
GND
IN
Ground
62
Vcc
IN
5V supply
63
RO2B
64
R03B
65
RDB
66
CLK
67
R04B
Select signal for 8KB area allocated to slot 2 or 3
OUT
Valid when SD2 is active (ROM based BASIC) and SD3 (RAM based BASIC).
(ROM2, 3)
IN
Read signal from the main CPU.
(Read)
EAIT signal generation clock.
(Clock)
Select signal for 8KB area allocated to slot 4.
OUT
Valid when SD2 or SD3 (RAM based BASIC) are active.
(ROM 4)
RAS/CAS address switching signal for the main CPU DRAM.
68
MPX
OUT
High: Row address
Low: Column address
(Multiplex)
69
GND
IN
70
CASB
OUT
Ground
CAS (Column Address) signal for the main CPU 64K DRAM.
•Refresh for the RAM only.
(Column Address Select Buffer)
71
GND
IN
72
INTB
OUT
73
Ground
(Interrupt)
Not used
- 22 -
M 7.3500
MAIN CPU
I/O PORT IN MEMORY MAPPER
ADDKKSS
A7 A6 A5|A4|A3|A2|Al|AO H E X UHUS
01
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
0
1 1 1 1 1 1 1 1
KI)
FE
FF
1 O
r\i IT
SKQB
DO
D7
SKI S
Dl
MS]
DO
1)7
D6
D5
D4
D2
Dl
DO
D4
D3
D2
Dl
DO
D7
D6
D5
1)4
D3
D2
Dl
DO
D7
D6
MSO
SRQ Bus request from the mam CPU to the sob-CPU
1 1
Sub-CPU reset signal
Memory system define
M<\3
Bank select signal to memory area of COOO-FFFF.
MA2
MAI
OUT
MAO
_J
MO2
MOI
MOO
Bank select signal to memory area of 2000-3FFF.
SW4
b«3
INI
System assign switch
M\2
Sttl
she
FD3
FD2
IN
FD assign
(SW8)
H>1
SKDY
•f>
Sub-CPU READY signal
SACK
•p
Sub-CPU acknowledge signal
1NP2
I MM
Interrupt status
IN'1'0
MF2
Mhl
1. All output signals are reset to low level upon power on,
except for SRBQ that goes high.
2. Noted with a star mark "£" are input/output signals, and
rest of others are processed in the LSI.
M II
#1 I/O port output of ME1 and ME2 uses the memory at
the addresses.
( ME2->8000~BFFF
I ME1->-4000~7FFF
When ME1 and ME2 are in high state. RSAB (RASA) is
inhibited during memory addresses in RAM-A that
correspond to overlayed addresses for MET and ME2
This is not true during SD1 mode.
01 iri T hkoM fMont
TO t MOI«m
Mm n (i H j 1 I 1 H M 2 hTisn 1 T4h
-^. t <|,
TvfT J i\=TjTNT7 JM3
i i
1
IM 2
IM 1
h
|M It
"- T"
1
X
"fJ~
11
1
1
j
X
X
1
L
1
H
H
I
H
H
1
H
|
1
L
H
" I "
H
j
H
j
H
H
I
'
H
H
j
H
j
H
L
1
j
H
i
l
""•»
H
|
H
H
1
FKOM SI in
M
" l"
Wait timing generator
WAIT is issued once per main CPU fetch cycle.
Its outut is tri state
H
|
TO HA
MZ3500
3-5. Memory (ROMIPL, RAMCOM, S-RAM) select circuit
To main CPU
1) ROM-IPL select by the main CPU
As ROM IPL turns to low level after power on address
bus buffers (LS244, LS367) and data bus buffer
(LS245) are enabled. S of the data selector 1C (LS157)
is set to a low level to enable input 1A-4A. The 3Y and
2Y outputs of the LS157 then go low so that CE and OE
of the ROM-IPL are from main CPU. The contents of
the IPL-ROM are then read by the main CPU. Because
the input pin (^16) of the address buffer (LS367) is
connected to Vcc, IPL for the main CPU will be at
address 1000 of the IPL-ROM. Switch SW2BA is the
operation test dip switch which should be ON at all
times.
4) RAM-COM select by sub-CPU
Y1 of the LS139 changes to low level when AS13 is high
and AS14 and AS15 are low. In other words, the input
4B of the LS157 is at low level which brings the output
Y4 to low level, so that CS of the RAM-COM chip select
signal should become effective.
If SMRQ, SRD or SMRQ, SWR is in low level at this
point, it enables read (OE) or write (WE). Address range,
however, is 2000 to 3FFF
5) RAM (SA, SB, SC, SD) select by sub-CPU
SMRQ, SRD (Of) or SMRQ, SWR (WE) is at low level
to select the sub-CPU dedicated RAM, SA-SD. Tne
following chip select signal, then becomes valid under
these conditions:
RAMSA .. ASVi, AS12, AS13, AS14, AST!
(address 4000^17FF)
RAMSB .. AS11, AST2, AST3, AS14, AS15
(address 4800-4FFF)
RAMSC .. AS11, AS12, AS13, AS14, AS15
(address 5000-57FF)
RAMSD .. AS11, AS12, AS13, ASK, ASHi
(address 5800-5FFF)
2) RAM-COM select by the main CPU
When RAM COM is low, SRES high, and SACK low, the
select input S of the selector 1C (LS157) is in low state
so that input 1A-4A becomes effective. That is, the output 4Y is low and either 1Y (WE) or 2Y (OE) becomes
low level, so as to enable to read or write RAM-COM.
3) ROM-IPL select by sub-CPU
Normally, the select signal S of the selector is pulled up
to Vcc level that inputs 1B-4B are enabled by sub CPU.
If A13 thru A15 were to be at low level, the output YO
of the LS139 becomes low level so that the output 3Y
of the LS147 or CE of the ROM-IPL should be at low
level. Should SRD, SMRQ be at low lebel as well, the
output 2Y of the LS157 or OE of the ROM-IPL turnde
to low lebel to read the ROM-IPL. Though the sub-CPU
can access an address range of 0000 to 1FFF theoretically, it would be from 0000 to OFFF, actually.
- 24 -
4. CRT DISPLAY
4-1. Specification
Ust of high resolution CRT
3KB (characit>-s!
Display memory
Character display
96KB. max (graphic i
Screen structure
Use of medium resolution (,RT
Option
80 chrs x 25 lines. 80 chrs x 20 lines
40 chrs x 25 lines, 40 chrs x 20 lines
Programmable
8 x 1 6 dots
8 x 8 dots
With lower case descenders
Character
structure
255 characters
Alphanumencs and 69 symbols
26 small characters
97 graphic patterns
Attributes
Graphic display
(option)
Revers, vertical line, blink, horizontal line
Programmable for each character
Blink, revers
Programmable for each character.
Colors
8 colors, programmable for each character
32KB type
640 x 400 dots, B/W (one frame)
640 x 200 dots, B/W (Two frames)
Color designation for each character
Color designation possible for each character
640 x 400 dots. B/W (three frames)
Color designation possible for each character
640 x 200 dots. B/W (six frames)
Color designation possible for each character
Color (one frame)
Color (Two frame)
96KB type
Screen merge
Merge any graphic screen (1 to 3 frames)
Merge of chracters and graphics
Merge a character screen with a graphic screen
Background color
Choice of 8 colors
Control of two independent screens
Possible to d aplay on separate two screens ongind 1 graphic screen and character screen
Separate graphic screens can be merged into one
Possible to affix attributes (CRT2 only)
Selection of character/non-character screen display
Control channel number
Incorporation of two independent video outut channels
Light pen input (option)
Scans coordinates and character code
Table 1
Summary of video display specification
Medium resolution CRT (640 x 200 dots mode)
High resolution CRT (640 x 400 dots mode)
^""~-\^
Characters
Function
^^\^^
Elements
Character s t r u c t u r e
Color monitor
Green monitor
Type of monitor
Graphics (option)
B/W
ASCII
Color
ASCII
8x8
8 x 20
8x 20
8x10
8x10
5x14
5x14
5x7
(Characters x ines)
40 x 25 mode
80 x 20
40 x 25
640 x 400
80 x 25
80x20
640 x 200
40 x 25
40 x 20
40 x 20
80 x 20
640 x 200
40 x 25
40 x 20
By character
Basic
Color
5x7
80 x 25
80 x 25
640 x 400 dot
40 x 20 mode
By character
Option 1 (48KB)
t
By character
Option II (96KB)
t
By dot
Small t e t t e r descenders
O
O
X
Line creation
O
X
X
Frames
ASCI:
8x8
80 x 25 mode
Basic
B/W
ASCII
I
Graphics ( o p t i o n )
Characters
8x 16
80 x 20 mode
Display memory
Graphics (option)
Characters
8x16
Screen s t r u c t u r e
Color
designation
Graphics (option)
Characters
Color monitor
Green monitor
3KB
32KB
3KB
32KB I I ) , 9 6 K B ( I I )
3KB
1 frame
No frame
1 frame
No frame
1 frame (1 page)
16KB
No frame
t
By dot
t
t
X
X
3KB
48KB
1 frame (1 page)
No frame
Option 1 ( 4 8 K B )
t
1 frame
t
1 frame
t
3 frames
t
1 frame
Option II (96KB)
t
3 frames
t
1 frame
t
6 frames
t
2 frames
Basic
Not possible
*-
«-
One B/W character screen agamst
Option 1 ( 4 8 K B )
One character screen Against
One character screen against
One character screen against
t h r e e graphic screens
one graphic screen
one graphic screen
t h r e e graphic screens
One color c h a r a c t e r screen a g a i n s t
one graphic s c r e e n
Screen
One B/W c h a r a c t e r screen a g a i n s t
overlay
Option II (96KB)
One c h a r a c t e r screen igain-,t
t h r e e graphic srrpens
t h r e e graphic screens
One color c h a r a c t e r s c r e e n against
'
•
one graphic screen
NOTE
Graphics o p t i o n
M7 3500
1) Character display
1.1. Screen structure
CRT used
Character
Medium resolution CRT
(640 x 200 dot)
fH = 15 7KHz
fV = 60Hz
High resolution CRT
(640 x 400 dot)
fH = 20 9KHz
( N e w ) f V = 47 3Hz
W Whne
80 x 25 lines
80 x 25 lines
-
ASCIL
40 x 25 lines
40 x 20 lines
Dip switch in the mam unit is used to select assignment of
Three basic colors
high resolution/medium resolution CRT.
Display mode must be chosen by programming.
4) Attribute
1-2. Character structure and picture elements
Color
B/W
640 x 200
640 x 400
Elements
Structure
8x 16
ASCII
Structure
5x7
8x10
1
symbol
8x8
5 x 14
8 x 20
Graphic
Elements
AT1
Vertical line
B
AT2
Horizontal line
R
AT3
Reverse
G
AT4
Blink
Blink
and character
r,,uy
may
also
be dis-
played on the 80 charac
8x8
ters x 25 lines screen.)
Small letter descenders
and line creating
functions are not
available.
Small letter descenders
and line creating
functions are available.
5} Screen overlay
It will be possible to have an overlaid screen that consists
of
NOTE:
Line
exist in the same element
(Line
I
8 x 16
Designated for each chaiacter.
one character
(screen and a maximum of
three
In the case of 8 x 8 and 8 x 1 6 picture elements,
graphic screens. (For detail of overlay screen, refer to
vertically
Table 1.)
adjoining graphic symbols will joint
together in the 25-line mode.
In the color mode, if there are two colors in the same
As for character structure of 6 x 14, 7 x 14, 6 x 7 ,
screen and other designated for a dot on the graphic
or 7 x 7, decision must be given on an actual dot
screen element — the one designated for a character on
the character — both colors will be merged sltorjpther
pattern.
to produce image.
2) Graphic display (option)
(High resolution CRT)
(Red)
© Dot color designated by
character attribute
(Medium resolution CRT)
640 dot
640 dot
o
200 dot
400 dot
Dot pitch
Dot pitch
Horizontal vertical = 1 : 2
Horizontal vertical = 1
3) Color designation
Eight colors are usable (white, yellow, cyan, green,
violet, red, blue, black)
Color designation
ASCII
Graph
48K b y t e
| 96 K b y t e
640 x 400 dot
640 x 200 dot
By character
By character
By character
By dot
By dot
By dot
Background color
8 c o l o r s for designation
00
o
o
O
(Blue)
O Dot color designated by
graphic dot.
(Violet)
Q Dot composed of more than
two color Jj>i"jrn*ion:.
MZ 3500
6) Screen
overlay
and displaying on two
CRT's
As there are two video output channels
independent
it will be pos
screens
sible to display two independent screens on separate
video display unit
Overlay is possible on either
Data
Address
Hex
50
AS AS AS
3 2 1 0
0
0
0
AS
DS
2
DS
1
DS
0
1
0
1
1
;p i
51
0
0
0
1
1
1
52
0
0
1
1
0
1
1
53
0
0
1
1
1
1
54
0
1
0
of
Internal
S gnat name
of CSP
Function
ECH1
Choice of outputting the character screen on CRT1
0 No
1 Yes
ECH2
Cho ce of outputting the character screen on CRT2
0 No
1 Yes
EAT2
Choice of whether attribute or cursor be put on the frame that displayed
on CRT2 (0 No 1 Yes)
SR1
Displays on CRT1 the blue elements contained in the VRAM
SR2
Displays on CRT1 the red elements contained in the VRAM
SR3
Displays on CRT1 the green elements contained in the VRAM
SR4
Displays on CRT2 the blue elements contained in the VRAM
SR5
Displays on CRT2 the red elements contained in the VRAM
SR6
Displays on CRT2 the green elements contained m the VRAM
BGC B
BGC R
1
(See preceding item 5) ) The following bit
selection is needed for screen overlay
[
Choice of background color display
BGCG
1
0
1
COLOR
Color mode
BODER
Border color mode in effect
08/16
Defines the data size for the graphic RAM (0 8 bits, 1 16 bits)
40/80
Defines display digits for the character screen
1
55
(50)
0
1
0
1
1
1
1
56
0
1
1
(0 40 digits 1 80 digits)
1
0
0
1
1
1
Connection of a 400 raster CRT
V RAM2
Connection of the 96K bytes VRAM
V RAM1
Connection of graphio GDC
1
25/20
25 lines/20 lines switching (0 25 lines, 1 20 lines)
1
08/16
Defines data size for the graphic RAM (0 8 bits 1 16 bits)
40/80
Defines display digits for the character screen
1
1
57
RA-400
1
1
5D
1
1
0
1
;P2
1
1
(0 40 digits, 1 80 digits)
NOTE Both CRT1 and CRT2 must be high resolution CRT's (640 x 400) or medium resolution CRT's 'RO x
Output to each CRT may be possible in the following combination .
Output to each CRT may be possible in the following
CRT1
CH ( AT )
C.KA7 )
CH AI ) + ( , ! ^ AT)
CH
GF
CRT2
CH( AT)
(,f- AT)
CH(Ar)+(,!
CH
(.1CH+GI
ASCII
Graphic screen, including overlay of two graphics
screens
M
(AT) Attached with attribute
MZ3500
7) ASCII CG
Uses an 8KB MROM contains two patterns'
640 x 400 dots ( 8 x 1 6 dots) and 640 x 200 dots ( 8 x 8
dots)
#OFFF
8 x 8 d o t pattern
(2K byte)
For Model 3200 series
With 8 x 8 dot format
two kinds of patterns coexist
Refer to ROM address and data
! x 8 dot pattern
(2K byte)
#0000
Without lower-case,
code on separate information
letter descenders
#1 FFF
Model 3500
8 x 16 dot pattern
(4K byte)
With lower-case,
letter (h i j) descenders
#1 000
D7|
Address and pattern in picture element
| DO
(Address)
. #1000
O
o
O
12
o o
o o
0
o
o
ooooo
ooooo
o
o
0
0
0
0
o
o
(Example of 5 x 12 dots pattern for 1 x 16 elements)
(Data)
#00
#1001
10
#1002
#1003
#1004
#1005
#1006
#1007
#1008
#1009
#100A
#1006
#100C
#100D
#100E
.- #100F
10
28
28
44
44
7C
7C
44
44
44
44
00
00
00
8) Element structure, character structure, and line
Element structure, character structure, and line
640 x 200 dot
1) 25 line display mode
/— Character pattern area
\— Line area
X— Area where pattern and line are overload
640 x 400 dot
1) 25 line display mode
12
1 5
2
IASCD/JIS]
8
Without line
'With line
HL On 16th line
VL Line ot the right of
element
In the case of graphic
symbol display
Both HL and V L a r e
overlaid to the pattern
[Graphic symbol
- 29 -
MZ3500
2) 20 line display mode
2) 20 line display mode
8
20
\\NS\\\\Mi
ASCII
With line
HL On 18th raster
VL Line to the right of
element
e VL does not join
a In the case of graphic
symbol display, VL is
overlaid to the pattern
Without line
10
20
Graphic symbol
j I Graphic symbol
9) Cursor
Sharp of the cursor: Same as seen in Model 3200
Reverse and blink)
4-2. Video RAM
1) Structure of VRAM
GDC1 (for character)
10) Light pen input
Incorporates the light pen input connector and its interface. The light pen, however, is an option.
Accuracy: By each character
Function: Coordinates/character code
GDC2 (for graphic)
#BFFF
16Kbit
i
i
t
1
1
j
i
1
1
1
1
i
i
xg
11) Difference in specification with that of Model 3200
(1) There are two modes for the Model 3200; normal
mode ( 6 x 9 elements) and graphic mode ( 6 x 8 elements). In the normal mode of 25-line displaying of
the PC-3200, vertically adjacent graphic symbols do
not joint. But, they will joint with the Model 3500.
(G)
Attribute
Model-3200
Model 3500
I
*07FF
(D-RAM)
16Kh,t 16Kbit
2Kbit > 8 2Kbit
( S-RA.M)
x4
ts-
(ASCI L
RAM)
(B)
' 0000
#0000
DO-
DO-
-D7 1)8—Oil
(R)
-D7 D8-
-D15
Solid line 48KB option
Broken line. To be added to comprise
the 96KB option.
(2) No line will be displayed for the medium resolution
CRT (640x200 dot).
It is possible to display line on the high resolution
CRT, compatible to line the utilizing program of
the Model 3200
V R A M capacity
Graphic option 1: 48KB
Basic 3KB (including a t t i b u t e s )
Graphic option 2 96KB
Bit structure of V R A M
— —______ CRT j
Character VRAM
Graphic
VRAM
- 30-
! 48KB
[ 96KB
640 x 400 dot
8 bu / word
'
640 x 200 do i
8 bit / word
16 bit ,' word
8 bit / word
16 bit / word
16 bit / wo-d
M 7 3500
2) Read/write from Z 80 to VRAM
(1) Timing period for display and
V-RAM Read/write.
//><-' Range wh°r? GDC can draw.
Fly back period
H • SYNCJ
BLNK-
(2) Timing that the Z-80 can read/write VRAM
The Z-80 can read/write VRAM when GDC FIFO
buffer is either empty or Full, and can be accessed by
refreshing during the display period. Number of
characters that can be read/write within one raster in
any mode.
3) Structure of character VRAM
(1) When read/write from GDC
(A)
#07FF
(B)
(A)
2KX8
ASC I I
ASCI I ( 8 b i t )
#0000
DO
8bi t
"D7
V&
4bit
«-Dll
( 12bit )
DO Dl D2 D3 D4 D5 1)6 D7 DO Dl D2 D3
• Blink
Reverse (G)
Vertical line (R)
. Horizontal line (B)
(2) During display
#07FF
(A)
2KX8
#0000
12bi t
(B)
2KX4
MZ3500
4) Graphic V R A M memory (MZIR03)
• Block Diagram
R ASA ^ RAS • A14 • A15
RASB~ RAS • A14 • AlS ...
RASC =• RAS • A14 • A15
0000 ~ 3 F F F
4000-7FFF
8000 ~ BFFF
2. Display mode
A14 and A15 are not valid and RASA, RASB, RASC are selected
together. By the DBIN signal from GDC-2. 08/16 signal is generated by CSP-2.
The signal of 08/16 select, after P-5 conversion for RAMA,
RAMB output signal then output to VB by serial signal, or sprit
the signal to VB and VR.
(08/16 select: 08 for 200 rasters. 16 for 400 rasters)
1. read/write Mode
The select signal RASA, RASB and RASC are generate from
RAS, A14 and A1 5 which is signal of GDC-2.
The address is allocated to each area selected by above signal.
Read/write by Z-80 via the GDC
During displaying
(1) 640 x 200 dots display mode
Low
byte
High
byte
B/W:
3 frames
Color: 1 frame
Option I
(48K byte)
8bit structure
1
#BFFF
G
+ 8000
#3FFF
16K
#4000
#0000
A
B
8bit
16K
R
#0000
8bit
31,L
i
8bit
8bit
Option I I
#BFFF
(96K byte)
16bit structure
B/W:
6 frames
Color: 2 frames
#8000
#3FFF
#4000
16K
#0000
I
16K
*0000
ifit.it
16bit
- 32-
1
1
M Z 3500
(2) 640 x 400 dots display mode
B/W: 1 frame
Color: 1 frame
Option I
(48Kbyte)
16 bits structure
#4000
# 3 KKK
16K
16K
*0000
(
Option II
Color can be
designated for
sach character.
i
#3FFF
#0000
BFFF
B/W: 3 frames
Color: 1 frame
(96K byte)
16 bits s t r u c t u r e
#8000
#3FFF
16K
#4000
#0000
16K
#0000
16bit
16bit
16bit
16bit
5) Synchronize signal timing
(1)
For 640 x 200 dots display mode
X : Y- 1 :2
fH = 15.87kHz
fV =
60 Hz
GDC-2 graphic)
GDC-1 (80 digits)
Character display (40 digits)
Dot clock (OD)
2XCCLK
Horizontal display time
8 bits
16 bits
(16MHz)
( 8MHz)
16MHz
16MHz
(4MHz)
<2MHz>
4MHz
2MHz
40MS
-
-
HFP
?A«
HS
6>js
(1?Chr )
(tREF-0.8ms)
5^s
( t R E F = 1.6ms)
10/js
- (20 Chr.)
8ns
1 2.6ms
-
-
VFP
1.2ms
-
VS
1 ms
-
-
VBP
1.8ms
-
-
HBP
Vertical display time
Total rasters: 261 rasters
Display raster: 200 rasters
•^(14
•—n.
—-1
r~-
Chr.)
10MS
j
MZ3500
(2) 640 x 400 bits display mode
fH = 20.92 kHz
fV = 47.3 Hz
X : Y : 1: 1
GDC-1 (80 digits)
Character display (40 digits)
8 bits
16 bits
Dot clock (OD)
(19 66MHz)
(9 83 MHz)
19.66MHz (50.86ns)
9.83MHz (101 92ns)
2XCCLK
(4.9152MHz)
(2.4575MHz)
4.9152MHz (203.45ns)
24575MHz (406 9ns)
-
-
Horizontal display time
HFP
GDC-2 graphic)
32 55^s 80 Chr. /40 Chr.
4.88fjs
4^is
HS
*~
«-
-
(tREF=0.6ms)
5 Chr.
(tREF = 1.23ms)
6 5ys
HBP
Vertical display time
19.16ms
VFP
0.527ms
VP
0.24 ms
VBP
1.198ms
*~
-
-
-
-
-
-
-
«-
-
-
Total rasters: 441 rasters
Display rasters 400 rasters
(3) CRT synchronizing signal specification (400 raster
CRT)
1. Horizontal synchronization frequency (fH): 20.92kHz
2. Vercial synchronization frequency ( f V ) : 47.3Hz
3. Total rasters: 441 rasters
4. Rasters used: 400 rasters
5. Display dots: 640 x 400 dots
6. Dot clock: (19.66MHz)
7. Timing
9. HS, VS, and VIDEO signals are supplied from the LS
type TTL 1C (totem pole)
6) Setup of GCD master/slave
(1) Master/slave setup by combination
^^•v^^
Character
^^•\^^
GDC
40 digits
80 digits
Without VRAM PWB
Character
Character
8 bit structure
48K byte
200 rasters
Character
Ch3rai.te'
16-bit structure
96 K byte
48K byte
400 rasters
Character
Graphic
Graphic
^^^^
GDC
^"\^
Master should be setup in the above i.ia.
(2) I/O signal switching
ft
PIT A
to
(8255.PB7 )
fiQ /I
!
8. Output method
outputs.
VFP: 11 rasters (0.5ms)
VS5 rasters (0.24ms)
VBP- 25 rasters (1.2ms)
HS, VS. and VIDEO are indpendent
p
(CSP-2)
,,
,.
,fc
VSYNC
Switching
Circuit
M-3500
CH48 -
I 08/16 -
0 For 40 digit display
1 : For 80 digit display
There is a 40/80 digit switching signal I/O port
in the gate array of CSP1 and CSP2, but, the I/O
signal called CH48 is provided apart from the I/O
port.
I/O port inside CSP1 and CSP2.
Relation between V R A M address and screen
16-bit structure
Graphic
address
map for
400 rasters
7) Graphic V-RAM Address
Relation between V R A M address and screen (640 x 200 d o t s )
8-bit s t r u c t u r e
0000
0050
00\0
OOFO
t
lnntn"~^
~
Graphic
address
map for
200 rasters
LXH)
liytr
bOb\ir —
CRTC block diagram
Color graphic VRAM PWB (option)
MZ3500
4/6. Master slice LSI (CSP-1) SP6102C 002 signal description
Priority
Signal Name
1
HSYi
IN
Horizontal synchronizing signal from the GDC1 Also, it becomes the refresh timing signal in the
dynamic RAM mode.
2
NABC
IN
Input from the UPD7220 GDC1. When the GDC1 is in the character display mode, the attribute,
blinking timing and line counter ciear signals are multiplexed.
3
CSR
IN
Input from the GDC1 which is the cursor display input when the GDC1 is in the character display
mode.
4-6
ASO - AS2
IN
Address bus input from the sub-CPU.
ABO = ASO, AB1 = AS1 , AB2 = AS2
7-9
DSO - DS2
IN
Data bus input from the sub-CPU.
DBO = DBO, DB1 = DB1 , DB2 = DB2
10
G2
OUT
11
NWRO
IN
CSP1 I/O port select signal (OUT # 5 X )
12
NVB
IN
Input of the blue image from the graphic R A M ( A ) and (B).
Green image output to the CRT2.
13
NVR
IN
Input of the red image from the graphic RAM (B), (C), and (D).
14
NVB
IN
Input of the green image from the graphic RAM (E) and (F).
15
FYD2
IN
Input of the graphic RAM parallel/serial conversion 1C 74LS166 shift out clock.
(Used to latch the image data in CSP1 .)
16-18
AT2 - AT4
IN
Attribute
f AT-2 AT-3 |_AT-4 -
19
CH
IN
Input of character display data signal.
20.21
GND
IN
0V supply
22
DSP2
IN
Input of display timing signal supplied from the CSP-2. (BLINK signal from the GDC2 is delayed by
two flipflop intervals in the CSP-2 to creat this signal.)
data input from the 21 14A-1 attribute RAM.
Horizontal Ime/R "]
Reverse/G
Blink
J
23
VID2
OUT
VIDEO output to CRT2.
24
LCD
OUT
Character CG line counter output.
(Becomes address input to the CG when LCD = CG address AO.)
25
AT1
IN
26-28
LC1 - LC3
OUT
Attribute data input (vertical line/B) from the 2114A-1 attribute RAM.
Character CG line counter output.
(LC1 = A1, LC2 = A2, LC3 = A3CG = A3)
29
NCL4
OUT
Character CG output data latch timing.
30
HSYO
OUT
CRT1 , 2 horizontal synchronizing signal
31
RA40
OUT
The signal that turns high level when the 400-raster CRT is in connection. LDA, 01 H OUT??56
32
VIDI
OUT
VIDEO output to the CRT1 .
33
B1
OUT
Blue image output to the CRT1 .
34
R1
OUT
Red image output to the CRT1.
35
Of
OUT
Green image output to the CRT1.
36
SL1
IN
37
Character CG output parallel/serial converter 1C 74LS166 shift load signal, and character CG address
latch signal input. (Used for the image data latch signal in the CSP-1 and horizontal synchronizing
signal delay flipflop clock.)
B2
OUT
Blue image output to CRT2.
38
R2
OUT
Red image output to CRT2.
39
BLNK
IN
Erase signal from the GDC1 which becomes input at the following times.
1. Horizontal flyback period
2. Vertical flyback period
3. Period from the execution of the SYNC SET command to the execution of the DISP START
command.
4. Line drawing period
40
Vcc
IN
+5V supply.
- 39 -
MZ3500
CSP-1 Block Diagram
ASO
1
1
AS1
AS2
1
4 ,. ..
o
MkRO
(bO)
(51)
Jl J,
„
o >
J
*
DSO '
DS1
n
x
— H
I)S2
—
to
—
fO
t—
(52)
'S3)
1
1
1
ro
CO
(54)
'55,50)
1
I
^.
,r»T ,
• 5fi .
II
I
I
c
n
n
r-
Cn
<7>
]
~
|
X
O
C
X
0 "
m
O
m
?
-_ i
^
0 = 5 °
o re —
3
"
fr
HSYI
K \ 400
1
NABC
j
1^
SL1
Line counter/
Line signal generator
>
RA400 — 1
25 /20 —1
FYD2
BLNK
B-VL
__
0/1..
DSP2
^ .« ". +, i,
..._.
.
.
<
—
*-
"\
AT 2
s
ATS
**
AT 4
'
CSR
J
}
*
n F/F
l-» CK
1 i > CK
*
. HSYI
"
BINK'
y^m-i™
t» o
r \
SO
1
to
5C
<
D
ECH1
NVR
DF/F
.V
1
»
?
X
Merge
circuit
4
1
-»-DSPT
<
r-
r~
M~^y_
-c
40/80 d,q,t
shift circu t
,
^
„ _
tr
r-
<
t~
r
??? U
*ili
Cursor
erase
circuit
^ '
''
JTV
"
-^
—
"
>
- Boder 1— =H>-^
background (
— -D "c
merge
* '• ~^
CSR-2D
*— ~*^
^
"O
<
r-|
OK;
^SR4
1
-
^
J
4
\j
X—^
}__S
|
.
- —'
°^SR6
O3
4
4
bri
' —0
5
n
X
C
4
fin
G. RV -> — ° " '" — i
f.
/ »
*
'
B 'VL-»> 1 S ^ ^
V
O-l
>- V1D2
T * 31
l^^^ro
/
color designation
during graphic
mode.
I
OM pS
4
'—+ Cursor; Blink ;Reverse Line
COLOR-*
RA400
~
B/W attribute merge circuit
i-r- --r
-^
c
r-
{> {> i>-hi>,
ECH2
"
r-
>- V I D 1
£
'"'
08 -'16
HSYO
j
o~"^o
s
L
,.
)— »-
-
\
.
'^
'p
^
~*—
ndividual
9/VL~* character]
V-RAM2
5-
1 4 4 1 4
J?^"
S
^
B/W attribute merge circuit
I
s
1
80
j
1
T
P
—
F/F
1
,.„
*
,)FXF
CH
D
H
-|
n F/F
n
u:
hIr1
1
40
D F/F
CK
NVB -C
\
— . >J
.
"N
} }
-* CK
n
•
\
ATI
I
'
^
^\_
^
^
_ Border
'~) ") *•
background
y-
OJ
0
-
*-
U
0G
FAT 2
1
CSH-
- 40-
-TV 5*= -""
fAIL-
"
4^V^
•>-
MZ3500
46. LSI (CSP-2) SP6012C-003 Signal Description
Polarity
IN/OUT
Signal Name
1
HSY2
IN
Horizontal synchronizing signal from GDC2 which also becomes the refresh tirniny . i j r . s ' i in the
dynamic RAM mode.
2
BLK2
IN
Erase signal input from the GDC2 which is supplied 4T the following times:
1. Horizotal flyback period.
2. Vertical flyback period.
3. Period from the execution of the SYNC SET command to -be execution of the DISP S T A R T
command.
4. Line drawing period.
3
OWE
OUT
4-5
AD14-AD15
IN
Input of the display output signals (AD14, AD1 5) from GDC2.
(Used to create DBIA-DBIC in the CSP-2.)
6
DBI2
IN
Input from the GDC2 by which the image memory output is sent on the data bus.
(Used to create RASA-RASC, CAS, PS, OWE in the CSP-2.)
7
DBI1
IN
Input from the GDC1 by which the image memory output is sent on the data bus.
(Used to create BUSG, SOE, SWE in the CSP-2.)
8
BUSG
OUT
Gate signal of the bidirection bus buffer (LS245) which is used to read/write attribute, and character,
data from the static RAM (21 14A-1 , 61 16P-3).
9
SOE
OUT
OUTPUT ENABLE for character static RAM (61 16P-3).
10
SWE
OUT
WRITE ENABLE for attribute, character static RAM.
11
0816
OUT
8-bit/word and 16-bit/word select signal.
(8-bit/word chosen with LDA. OOH OUT#5D, and 16-bit/word is chosen with LDA, 01 H OUTiSD.)
12
RAS1
IN
Memory control signal RAS from GDC1.
(Used to create CGOE, SL1 in CSP-2.)
13
RAS2
IN
Memory control signal RAS from CDC3.
(Used to create SL2, LOAD, RASA-RASC, CAS, FS. DBIA-DBIC. DSP2 in CSP-2.)
14
ASS
IN
Address bus input from the sub-CPU (ASS = AB3)
Chip select (OUT#5X) of the I/O port in CSP-2.
WRITE ENABLE output for the graphic dynamic RAM.
15
NWRO
IN
16-17
DSO-DS1
IN
Data bus input from the sub-CPU (DSO = DBO, DS1 = DB1 ).
18
RA40
IN
The signal that goes to high level (input from CSP-1) when the 400-raster CRT is connected.
(Used for clock frequency selection in CSP-2.)
19
M40
IN
Clock input from the clock generator (39.32MHz, for 400-raster mode.)
20
GND
IN
0V supply
21
SL2
OUT
Graphic DRAM output parallel/serial converter 1C 74LS166 shift load signal.
22
RASA
OUT
Graphic DRAM (A), (B) RAS signal.
23
2CM2
OUT
Double character clock output. In the character display mode, a single phase clock of the half the
one character wide frequency is supplied. In the graphic display mode, a single phase clock of
8/16 dot frequency is supplied to GDC2.
24
LOAD
OUT
Graphic DRAM output parallel/serial converter 1C 74LS166 load timing clock.
25
Vcc
IN
26
FYD2
OUT
Graphic DRAM output parallel/serial converter 1C 74LS166 shift out clock.
27
2CK1
OUT
Double character clock output same as 2CK2. In the character display mode, a single phase clock
of one half the one character wide frequency is supplied to GDC1 .
28
SL1
OUT
Character CG output parallel/serial converter 1C 74LS166 shift out clock.
29
SL1
OUT
Character CG output parallel/serial converter 1C LS166 shift load signal.
Character CG address.
30
CGOE
OUT
Character CG output enable signal.
31-33
DB1C-DB1A
OUT
Timing signal by which the graphic DRAM output is sent on the data bus.
34-35
RAS-C ~
RAS-B
OUT
Graphic DRAM RAS (ROW ADDRESS SELECT) signal
RAS-B; RAM(C), (D)
RAS-C; RAM (E), (F)
+5V supply.
- 41 -
M/3 r >00
Priority
Signal Name
36
M32
IN
37
FS
OUT
Graphic DRAM address multiplexer signal (High order 8 bits I ADS ADI 5] /low 3'der S hi"
|ADO A D 7 ] select signal )
38
DSP2
OUT
Display timing signal (In the CSP 2, the signal BLINK from GDC2 is delayed by 2 collor intervals to
create this signal )
39
CAS 2
OUT
Graphic D RAM CAS (COLUMN ADDRESS SELECT) signal
(Line address selection)
40
Vcc
IN
Clock input 32MHz, 200 raster
+ 5V supply
CSP 2 Block Diagram
S-RAM & CG
control signal
generator
^— Bl SC,
D- SOf
O- SHE
Ci
^
''
: co
3 6
L
ii
Jl
PR
r*
™
Hexadecimal
counter
D
£
O
-a.
GDC1 &
character
display clock
generator
5
32MHz
L>
*M n~,
4U(J
HasTer
*
^00/41to
rasters
•
0
GOC2&
graphic display
clock
generator
t
T
ft.
Cfi
CK
VWRO — C
Oh
16
5
DBI2D
3«32MHz
Clock select
^ ClfCU1,
8/1 6 bill
select circuit
200 Raster
Q
I)
F F
O
1 O
40/80
K A S 2 —C
F
'
Ubl 2 —C
DRAM
control signal
generator
' ' '•
, cK
F
GDC2
Read
ignal
generator
n
Q
2 — 3
)ECODER
n
L} \
t
- 42 -
h P°
CK
f
O—HB 1 A
M 7.3500
4-7. GDC (Graphic display controller) (UPD7220) signal description
Polarity
Signal Name
1
2XCCLK
IN
2
DBIN
OUT
Memory contro signal supp'ied to the image memory from the GDC, which causes the image
memory output data to be sent on the data bus.
3
HSYNC-REF
OUT
Memory contro' signal sent to the image memory from the GDC, which is the horizontal
synchronizing signal.
• Since the image drawing process is automatically interrupted in the dynamic RAM mode the refresh
address is output during the HSYNC period. It can also be used as the refresh timing signal.
• Refresh is accomplished by suppressing the CAS signal derived from the RAS signal in the external
circuit when the HSYC is at h gh lebel (Horizontal Synchronous - Refresh timing)
4
VSYNC
EX.SY
NC
IN/OUT
5
BLNK
OUT
Erase signal output is issued at the following times (blanking signal):
1. Horizontal flyback period.
2. Vertical flyback period
3. Period from the execution of the SYNC SET command to the execution of the DISP START
command.
6
RAS
OUT
Memory control signal sent to the image memory from the GDC,
• In the dynamic RAM mode, it is used as the reference signal of RAS. When at high level, used
as the timing signal by which the address signal is latched.
(Row Address Strobe)
7
DRQ
(NO USE)
OUT
DMA request output which is connected with the DRQ input of the DMA controller is output by the
following two commands'
1. DREQE (DMA request write): CPU memory to image memory.
2. DREQR (DMA request read). Image memory to CPU memory.
It will be continuously output until the DMA transfer word/byte number set by the VECTW (vector
write) command becomes zero.
(DMA Request)
8
DACK
(NO USE)
IN
Signal supplied from the DMA controller that is subsequently decoded by the GDC as the read or
write signal during DMA.
(DMA Acknowledge)
9
RD
IN
In the external circuit RD is combined with the chip select signal (CS). And is used when the CPU
reads from the GDC either data or status flag and the signal DACK.
(Read strobe)
10
WR~
IN
In the external circuit WR is combined with the chip select signal. And is used when the CPU
writes to the GDC either a command or parameter and the signal DACK.
(Write strobe)
11
AO
IN
Normally, connected with the address line and is used TO designate data type.
Double character clock supplied from the external dot timing generator which has the followin^
two modes:
1. Character display mode 1 Single phaseclock at one half of the one character wide cycle
2. G r aphic disp'ay mode: Single phase clock of eight dots that cycles
Establishes one of following two modes, depending on whether the GDC is operated by the master
or the slave.
1. When the master is operational: sends out the vertical synchronizing signal.
2. When the slave is operational : The synchronizing signal generation counter is initialized by a high
level input.
AO
RD
WR
0
1
0
1
0
0
1
1
1
1
0
0
function
READ STATUS FLAG
READ DATA
WRITE PARAMETER
WRITE COMMAND
^Mode^'
IN
#70
IN
#71
OUT #70
OUT #71
GDC1
IN
#60
IN
#61
OUT #60
OUT #61
GDC2
(Address Bus 0)
12~19
DBO-DB7
IN/OUT
Bidirectional data bus connected to the system bus.
(Data Bus 0 - 7 )
20
GND
IN
0V supply.
21
LPEN
IN
Light pen strobe nput. When a input light is sensed by the light pen, it outputs a high level signal.
The CPU can then read the display address via the LPENR (Light Pen Read) command.
22-34
ADO-AD12
IN/OUT
Bidn ectional address/data bus connected between the image memory and the GDC on which address
and data are sent on the bus by means of multiplexer ALE (Address Latch Enable) is drived from
the RAS output in the exte r nal circu t.
(Address/Data bus 0 - 1 2 )
M Z 3500
Polar, ty
Pin No
IN/OUT
Function
Signal Name
35-37
AD13ILCO)AD15ILC2)
IN/OUT
Provides the following functions based on the operational mode of the GDC (graphic display mode,
character display mode 0, character display mode 1).
1. In the graphic display mode and character display mode 0: Bidirectional address/data bus
2. In the character display mode 1 : Line counter output in connected to the character generator
ROM or graphic RAM address.
• In the graphic and character display mode 0: AD13~AD1 5.
• In the character display mode 1 : LCO~LC1.
(Address Data bus 13 ~ 15)
(Line Count 0 - 2 )
38
A16 (LC3)
(AT~BTI
NK-CLC)
OUT
Provides the following functions based on the operational mode of the GDC (graphic display mode.
0. character display mode 1 ):
1. Graphic display mode: Image memory address output.
2. Character display mode 1 : Line counter output.
3. Character display mode 0: Attribute/blinking/timing signal and external line counter clear signal
(Address 16}
(Line Count 3)
(Attribute Blink — Clear Lire Counter)
39
A17 (CSR)
(CSR-1MAGE)
OUT
Provides the following functions based on the operational mode of the GDC (graphic display mode,
character display mode 0, character display mode 1):
1. Graphic display mode: Image memory address output.
2. Character display mode 1 : Cursor display output.
3. Character display mode 0: Cursor display output, character display area (graphic) display area
select timing signal.
(Address)
(Cursor)
(Cursor-image)
40
Vcc
IN
+ 5V supply.
- -14 -
M
"
4 8 CG Address Select Circuit
When 200 rasters on ASCII in use
(only the high order 8 bytes of 16 bytes are set to low level I
ASCII C.G. Structure
»
Ii rr
=^=^
1020
10! 1-
leBytes
ASCII character structure
of the 200 raster CRT
Character
Code 01
For
Model 3500
lOOh
ifiBytes
Character
Code 00
For
Model 3500
[Circuit description]
(Purpose)
I
The character genrerator (CG) incorporates all character code^ used by
\ l'= I -
1000
01-1^
ASCII character structure
of the 400 raster CRT
8 x 1 6 dot
> Pattern
400 Rasters
M'-O
the 200 raster video display unit of the \X
•>
3500 and by the 400 raster
video display unit of the \X 3500 The CG address select cirruit is
I
therefore used to select those modes
=
=
[Operational description]
1 When the 400 raster CRT is in use, RA40 is set to high level which
sets A12 of the CG to high level at all times, so that the CG address
0020
001 t
a Bytes
0018
0017
above 1000 is selected Also, gate (1) opened so that LC3 is input to
Code 01
For
Model 3200
'/ '///'
s/
/////^
I
A3=l
f
K Bytes ' Code 01 ',
' For
x
(Hi in ,. Model 3500: \ 1-0
001 1
Character
*
Code 00
8 Bytes
1
For
Model 3200 \ i i
0 Iftk
OKI
/ Character /i
fc Bytes Code 00 ',
' For
Pattern
200 Rasters
A3 of the CG At the same time, gate (3) is opened so that the gate
of the LS240 is closed every 16 bytes
2 When the 200 raster CRT is in use, RA40 is set turned to low level
which sets A12 of the CG to low level continuously, so that the CG
address 0000 OFFF is selected Also, gate (2) is opened so that the
CPU
t
8 b ts
- 45-
MZ 3500
4-9.
VSYNC
From
(8255 PB7) CH48
0 40 Digit
1 80 Digu
SRES ( F r o m MMR)
40 digit. 16bu/word
80 digit, 8bit/word
Master is GDC
40 digit, Sbit'word
Master is GDC 1
80 digit, 16bit/word
Master is GDC-2
[Circuit description]
When more than two UPD7220 GDC's are to be operated in
parallel, one must be assigned to the master and the other
to the slave in order to mantain synchronous display
timing. The master and the slave are determined according
to the table below. The above circuit shoud be used to
compare with the table description.
""~~~-~^GDC-1 (character)
CH48 = 0 40 digit CH48 = 1 80 digit
GDC-2 (graphic)"""
^^^
Without VRAM PWB
GDC1 (character)
is the master.
GDC 1
8-bit structure [0816=0)
(48KB, 200 raster)
GDC1
GDC 1
16-bit structure [0816=1]
(4896KB, 400 rasters)
GDC1
GDC2 (Graphic)
The master GDC must be set as indicated above.
[Oprational example]
If it was set to 80 digit, 16 bit/word mode SRES will be
0 when CH48 = 1, 0816 = 1 when not in the reset condition. These signals are supplied to terminal A (weight 1),
B (weight 2), and G (gate), and set terminal Y3 of the
decoder 1C LS139 to "0", so that the YSYNC output of
the GDC2 is input to terminal EX SYNC of the GDC2.
- 46-
MZ3500
4-10. Character VRAM select circuit
Lov*/ when
0 300^07FF
The signal BLNK is used to address the ASCII RAM
within address area of 0000-07FF in transferring
the display data from the VRAM to the CG.
CS
6 1 1 6( 2 K * 8 )
ASCB
V-RAM
2114(!Kx4)
First half of
attribute
*0000
-07PF
*0000
-03FF
2114(1K*4)
Latter half of
attribute
#0400
-07FF
#0000
-07FF
BL'SC
BLNK Erase signal
TTJ
H-SYNC
Period that the GDC is enabled to read/write
and draw graphic data.
TT_
BLANK
[Circuit description]
With respect to GCD1, the assignment during read/write
of the character VIDEO-ROM is per the table below. The
character VRAM select circuit is provided. Jo accomplish
this function.
6 I 1 6 >2K»8 )
Latter half of
attribute
ASL C
V-KAM
First half
of attribute
*07FF
t
ARIO = H1
T
AK10 = Low
8bil
- 47 -
*0400
#03KF
toooo
MZ3500
4-12. Read/write from the Z-80 to V-RAM
Read/write of the Model 3500 V-RAM is done via the
UPD7220GDC. There are two methods used to read/write
data. The method (1) is used for the model 3500.
(1) Read/write via the 16 byte FIFO.
(2) Read/write of V-RAM in the DMA mode without
intervention of the FIFO.
(Outline of the read/write data via the FIFO;
NO
YES
Set GDC command code
Method used to give a command
to the GDC.
YES
Set parameter for the command
YES
Set parameter for the command.
I
Command must be given to the GDC in the same manner.
On next page is the program of the above flowchart.
- 48-
MZ3500
(Subroutine lo send command and parameter to the GDC
via the F I F O )
HL reg — First address of the command code oarametpr
B. reg — Q'ty of data.
C reg - 60H (graphic GDC), 70H (character GDC)
> FIFO Empty?
; COMMAND —• GDC
; Return if parameter not sent.
f F I F O Empty?
; PARAMETER — GDC
;
Return when all parameters were sent.
RET
Example of graphic drawing by GDC
1) Dot display
0000
0001
Example to display a dot on the fourth bit of the address
CSRW C
49H -COMMAND CODE
0027
0028
VRAM 16-bit
structure
- 49-
P1
01H
— Low order one byte of the ab-
P2
solute address
OOH — High order one byte of thp ah
P3
solute address
30H - Dot address (dAD)
WRITE C
23H - COMMAND CODE
VECTE C
6CH - COMMAND CODE
M23500
[Explanation]
C-COMMAND CODE
) To
A
p_ PARAMETER
'
Display dot, specify the display address of the VRAM and
the dot address. Set the command code of the SET mode
(set mode plus CLEAR, REPLACE, and COMPLEMENT
modes using "WRITE", and specify to start with
"VECTE". Dot address is structured on the screen in the
following manner.
Address 0001
dAD= 0
1
2
3
1
5
6
7
[Dot display program example-1]
LD
LD
INC
LD
INC
LD
INC
LD
INC
LD
INC
LD
LD
LD
LD
CALL
LD
LD
LD
CALL
LD
LD
LD
CALL
HL .5000H
(HL) . 49H
L
(HL) ,01H
L
(HL) , OOH
L
(HL) 30H
L
(HL) ,23H
L
(HL) , 6CH
C
,60H
B ,4H
HL , 5 0 0 0 H
GDC
C
,60H
B , 1H
HL . 5 0 0 4 H
GDC
C , 60H
B , 1H
HL . 5 0 0 5 H
GDC
5000 — 49 H
5001
5002
5003
5004
5005
—
—
—
—
—
01 H
CSRWdata
00 H
30 H
23 H } W R I T E data
6CH } VECTE data
C — BOH (port address during graphic draw)
B - Byte size CSRW data
HL - Top address of the CSRW data
Command, parameter of CSRW - GDC
B - Byte size of the WRITE data
HL - Top address of the WRITE data
Command, parameter of W R I T E - GDC
B — Byte number of the VECTE data
HL - Top address of the VECTE data
; Command, parameter of the VECTE - GDC
8
9 10 11 12 13 14 15
M 7. 3500
2) Straight line drawing
00000
0001
0027
0028
0050
VRAM 16 bit
structure
Example to draw a straight line from (X, Y) = (3, 1) to (X,
Y) = (635, 1).
Coordinates must be changed to absolute addresses.
(3, 1) - absolute address = 0028H
Dot address = 2H
Displacement between two points when the line draw
direction is OA (to the right): X = 635-3 = 632 (=278H),
Y=0
Whereas.
CSRW
TEXTW
VECTW
C
PI
P2
P3
49H
28H
OOH
20H
HAD
dAU
C 78H
PI FF
P2 FF
C
PI
P2
P3
P4
P5
P6
P7
P8
P9
I, , H
Kind of line (solid line)
4CH
OAH
} Drawing direction
78H
}
02H
88H
H>H
1 OH
FBH
OOH
OOH
WRITE
C
23H
VECTE
C
6CH
\
1 AX I
1
f 2 ! AY 1 - I A x I
1
> 2 1 AY
1
1 -2
1 AX
I
2 i AY !
[Explanation]
Specify the kind of line by TEXTW, using C for command
code and P for parameter, and specify the line drawing
direction using VECTW and above four values using X and
Y. The rest will be same the dot display It is also possible
to display a dot using the line drawing method for any line
drawing direction using X = Y = 0.
M Z 3500
5. MFD INTERFACE
1) Floppy disk nomenclature
5-1. Outline
Floppy disk is a disk which is made of a mylar sheet whose
surface is coated with magnetic particles and set on the
device to write and read data on the surface of the disk
It will be necessary to know operating pnciple of the
floppy disk unit and operational description, including
recording method and format.
5-2. Floppy disk
As various recording methods and formats are used for
floppy disk (F.D.) systems we will discuss some of them
3) Components of FD's:
Floppy disks called by different names dependng on the
manufacturer
[>- Floppy media (or simply as medn)
<•' Diskette
Floppy disk
2) Types of media
Four types are used at present depending on their
storage capacity
(>- Single sided, double density (floppy disk-1)
[° Double-sided, double density (floppy disk-2D)
Single sided media index detect hole
Double sided media index detect hole
Front side-
Feverse side
Head engage slit
(do not touch)
Head 1
Head-0
4) Write protect notch
Different write protects are adopted depending on the
drive unit used.
Example-1:
In the case of the CE331 the presence of
light reflection is sensed by the photo
coupler and decoded as write protect
Write protected
Front side
Write enabled
- No reflection (Write enable)
o
0
Front side
o
0
- (Reflect"n
+
— »•
"^
r\
vy
i irn
n
D
0
»•
_
n
fi_i
.— > k
C
n ILJi
l— 1i
r\
^
D
0
—*•
J
Shaped waveform
C
— L_J
Write current
Differentiate
waveform
I)
fl_Jn_jn
Wrote
•\
Xy
f-'
Read
LJ
9 US
4
Write current: The write data is input to the flipflop and
is inverted each time a pulse is received to change the
direction of writing current.
Read waveform: The peak of the waveform is detected
at a change of magnetic flux. The waveform is than
shaped to obtain read data identic it >.<_• tlirf write data.
Data cycle will be 4/^s.
MZ3500
times the data density of the MFM mode (The unneceb
sary clock pulse is eliminated using this method )
(Condition) Clock is written only when there is no data
o MFM method (double density)
The MFM method writes data on the basis of the condi
tion metntioned below, and it yields a data density two
0
Input data
£
0 £
0
1
0 •'•> 0
1
1
1
0
1
0^0
n
n n n
n
7 /
nnn
n(O
n n nnn n ' VnVn
n
nV
[ci |D (ci |u ici ,i> ci
(0 ;i> (c)
\ /\ /\ X"V /\ /
Write data
C
C
(C) I) (C)
t \
Data that follows
'(_
<
i
i
i
Data that precedes
The clock pulse (Ci will be eliminated in above illustra
tion as there is no data preceding or following the clock
Because the data rate is 2/Js for this method, it is
possible to obtain twice the density of the FM method
NOTE
6) Media recording format
Media is formatted according to the IBM format
For Double side media, data is written on the front side
(head-1) and the reverse side (head-00)
Floppy disk
Tracks, consists of 40 tracks, 00-39. (May also be called
cylinders)
Sector. 01-16
Recording density: 256 bytes/sector
Three types of write data cycl»- (2f
~>t"> SA*S)
are used The read/write waveform is identical
to FM method
M 7 3500
Shown
below
is an enlarged view of
data format
sequence W r i t i n g starts as soon as the index hole comes
through the index detect hole
1 Track
Sector 02
Sector 01
DATA
<[
DATA
Firnl ^p
IU
II)
DA I A
t
INDEX
\M
Start point
Hatched portion is
a recording gap
51
ID
TT HH SS DL CRC CRC
AM
DATA
AM
DATA
Data
ID section CRC check code
CRC CRC
Data section
CRC check code
Size of data section
' Data address mark
(or delete address mark)
(00) H — 128 bytes
(01) H — 256 bytes
NOTE
Sector number
Head number
(00) H -» Head 0 (side 0)
(01) H -* Head 1 (side 1)
The delete address mark
is written to indicate invalid
data It is often written on
a new floppy disk as there are
no valid data on it
• Track number
• ID address mark which
begins the ID section
7) Formatting
(6) The sector of the identical ID is read and verified
To write the above format (ID section, data section, gap)
with the write data Because of thr
on an entire surface of
formatting
capability the possibility of an error in the written
a new floppy disk is called
Note 1 Formatting may also be called initialization. The
word "initialize" is also used as a software term to clear
the data section or to partition data area. Keep the
difference between formatting and initializing in mind.
Note 2
Unless formatting has been done on a properly
adjusted floppy disk drive unit, an erroe may occur on
another floppy disk drive unit
pad dftei A r . ' e
data is quite low
9) Data read procedure
Described next is the procedure to read data from the
FD.
(1) The head is moved over the track tu -^ i ead
(2) The head is loaded
(3) The ID section is read and repeated until the desired
sector is reached
(4) When the identical IDsection is found, the <~i-m IP
8) Data write procedure
Described next is the procedure to write data on the FD.
(1)
The head is moved over the track to be written.
(2) The head is loaded
(3) ID section is read and repeated until the desired
section is reached
(4) When the desired ID section is found, data is written
on that area (DATA AM is also written )
(5) The data thus written is now checked if it was
written correctly (read after write) The respective
ID section is read while the media makes a full turn
that data section is then read
MZ3500
5-3. MFD interface block diagram
> MOTOT ON
- 56 -
M 2 3500
FDC (UPD765)
UPD765 block diagram
UPD765 pin configuration (top view)
R L S t IQ
»•
1
RDO
»
2
39
WRO
»•
3
38
K3LCT/DIR
CSO
>
4
*O FLTR/STEP
AOO
DBOo-«
>
»
5
6
37
36
DB1CX
»
7
DB2O4
K
DB304
8
». 9
DB4 O<
ft- 10
^
OVcc
40
K3HDLD
35 «
0 READY
34 4
33 4
O WPRX/2S1DE
32
K> PSO
K> PS1
DB5CX—* 11
K> WDATA
DB6O4— t- 12
29
>0 USO
DB7O4 — *• 13
14
DRQcn
28
K5 US1
27
K> S I D E
26
25
K> MFM
NDWE
24
23 •<
>0 SYNC
* 15
TCO
> 16
INDEXO
»• 17
INT04
*0
GNDO
18
»• 19
20
22
1 Mf K F A C f c
READ/
WRITE/
RD-
DUA
WR—K
CONTROL
L.OGIC
DR 1 VE
1NTERFACE
CONTMO1
LER
O RDATA
0 WCLK
: Reset
: Read
: Write
: Chip Select
:AO
: Data Bus
: DMA Request
: DMA Acknowledge
: Terminal Count
: Index
: Interrupt Request
: Clock
: Ground
: Write Clock
: Data Window
: Read Data
: VFO Synchronize
: Write Enable
I SPUT
- » I KT
POKT
- 1 M)t X
- Fl T T
•«— o WINDOW
21 4
RESET
RD
WR
CS
AO
DBO-7
DRQ
DACK
TC
INDEX
INT
0
GND
WCLK
WINDOW
RDATA
SYNC
WE
SER f AL
O FLT/TRKO
31
30
DACKO
A-N.
No/
KDRW/SEEK
MFM
SIDE
USO. 1
WDATA
PSO, 1
FLT
TRKO
WPRT
2 SIDE
READY
HOLD
FLTR
STEP
LCT
DIR
RW/SEEK
- 57 -
: MFM Mode
: Side Select
: Unit Select
: Write Data
: Pre Shift
: Fault
: Track 0
: Write Protected
: Two Side
: Ready
: Head Load
: Fault Reset
: Step
: Low Current
: Direction
: Read Write/Seek
MZ3500
UPD765 signal description
Function
Pin No.
Signal name
I/O
40
Vcc
-
+5V
20
GND
-
0V
19
0
I
Single phase, TTL level clock
1
RESET
1
Set the FDC into an idle state, and all drive unit interface outputs, except PSO, 1 , and WDATA
(don't care), are set to low level In addition, INT and DRW outputs are set to low level DB goes
into an input state.
4
CS
1
Validates RD and WR signals
DB7 ~ DBO
I/O
13-6
3
i
Bidirectional, tri-state data bus
Control signal to write data to the FDC via the data bus
WR
2
RD
'
1
18
INT
o
5
AO
1
The signal used to select the status register or data register of the FDC for access via the data
bus. When 0, it selects the status register When 1. it selects the data register.
14
DRQ
FDC to memory data transfer request signal in the DMA mode
15
DACK
o
1
29,28
USD, 1
0
Drive unit select signal, with which up to four drive units can be selected.
26
MFM
o
The signal used to designate the operation mode of the VFO circuit When 0, the MFM mode is
assigned. When 1, the FM mode is assigned
24
SYNC
o
The signal used to designate the operation mode of the VFO circuit When 1, it permits reading
operation. When 0, it prohibits reading operation
39
RW/SEEK
o
Signal used to discriminate the read/write signal from the seek signal that used for drive unit
interfacing signal. When 0, it indicates RW When 1 , it indicates
36
HOLD
0
Signal used to load the read/write head
27
SIDE
0
Signal used to select head #0 and head #1 for the double-sided floppy disk drive unit. When 0,
it selects head 0. When 1, it selects head 1.
38
LCT/DIR
0
When the RW/seek signal is operating as RW, the signal works as LCT which indicates that the
read/write head is selecting the cylinder above 43. When the RW/SEEK is operating as SEEK,
it works as DIR which indicate seek direction When 0. seek is made towards outer side
When 1, seek is made towards inner side
37
FLTR/STEP
o
When the RW/SEEK signal functions as RW, it works as F LTR which resets any fault condition
as the seek step signal.
35
READY
1
Signal used to indicate that the drive unit is ready for operation
34
WPRT/2 SIDE
1
When the RW/SEEK signal is operating as RW, it function as WPRT which indicates that the drive
unit or the floppy disk is write protected. When the RW/SEEK is function as the SEEK signal
produces 2 SIDE which indicates that a double sided media is in use.
17
INDEX
'
33
FLT/TRKO
1
When the RW/SEEK signal is operating as RW. it works as FLT which indicates that the drive
unit is in a fault condition. When the RW/SEEK is operating as SEEK, it works as TRKO
which indicates that the read/write head is on cylinder 0.
16
TC
1
Signal used to indicate the termination of a read or write operation
30
WDATA
0
Data written on the floppy disk consists of clock bits and data bits
25
WE
o
Signal to indicate write enable to the drive unit
21
WCLK
1
Data write timing signal which is 250kHz in the FM mode or 500kHz in the MFM mode
Control signal to read data from the FDC via the data bus
The signal used to indicate a service request from the FDC It is issued at every byte in the nonDMA mode, or upon completion execution of a command in the DMA mode
The signal that indicates use of the DMA cycle During the DMA cycle, it functions identically
toCS.
Signal to indicate the physical start point of the track.
- 58-
MZ350C
P,n No
Signal name
I/O
32. 31
PSO. 1
O
23
RDATA
22
WINDOW
Function
Signal used to either advance or delay the write data in writi ng under the MFM mode,
to obtain tirrung adjustment for reading. The WDATA signal is controlled as shown in
the table be ow
FM
MFM
PSO
PS1
0
0
0
1
-
LATE
225~250ns
1
0
-
EARLY
225~250ns
1
1
-
-
Not changed Not changed
1
Read data from the drive unit consists of clock bits and data bits.
'
Signal created in the VFO circuit which is used to sample RDATA. Phase syncroni^i
carried out in the FDC for RDATA data bits and WINDOW.
5-5. Data recording method
1) MF recording method
(1) Clock bit indicates a bit cell.
(2) Data bit is placed in a middle of a bit cell. (See Fig. I.
There are two ways of recording data; FM recording
method and MFM recording method.
2) MFM recording method
(1) Data bit is placed in a middle of a bit cell.
(2) When the data bit is "0", a clock bit is placed before
the current bit cell. (See Fig. 1)
'
' •__ —1
v
i
—JUULJUULJLJlJLJLnJl
1
i
n
i
!i n
ii
i
0
!
i
!
i
i
!
n
r-JLJLJ1
0
| ,
i
i
|
0 | 0
• (MFM recording method)
1
o
Model 3500, only side 0 of track 0 (128 bytes/sector) is
written in the FM mode and rest of other tracks are
recorded in the MFM mode.
As seen from the above illustration, bit density of the MFM
recording method is twice the FM recording method. In
other words, data density of the MFM recording method
doubles that of the FM recording method. For the
5-6. I/O port in the MFD interface
I/O port used in the MFD interface is as follows.
D-BUS
IOMF#F9-AO
IOMF#F8-AO
I/O
OUT
D7
D6
D5
D4
D3
1)2
1)1
DO
U2
Dl
DO
DACK
ME
SCTRL
TC
OUT
IN
TRIG
SEL3
SKI. 2
SEL1
SELO
M . ON
I NDEX
DRQ
Used for data transfer between the CPU and the FDC.
INT from the FDC is output enabled on INTFD.
FDD select signal output is enabled.
TC to FDC.
Trigger (motor on) of the timer (555)
Selects FDD 3
Selects FDD 2
Selects FDD 1
Selects F D D O
ON/OFF state of the motor
INDEX signal from the motor
DRO from the FDC.
- 59-
M 7.3 500
5-7. Precompensate Circuit
Set the counter to 200ms.
(Actually, slightly longer than 200ms.)
K K I T E DATA
(Fig. 2)
PSO
PS1
FM
MFM
Value of LSI 63
0
0
Not changed
Not changed
1101
0
1
-
LATE(125»is)
1100
1
1
0
-
EARLY(125ja)
1110
1
-
-
-
Media is present.
(Table!)
Media is not present.
5-9. Controls during read, write, seek, and recalibrate
Above operations are all controlled via the FDC.
1) Control during read and write
WDATA8MHz
CLOCK
I
f
READ (or WRITE)
command to FDC.
EARLYNOMAL-
I
TC-»FDC.
HALT
(Wait for interrupt) H-">uit staius
is read by FDC.
LATEDATA<- FDC
DATA-* FDC
(Fig.3)
The precompensate circuit is used to compensate the peak
shift before writing.
The FDC sends out the compensation rate to PSO and PS1
and the data bit location is shifted according to this signal.
With issuance of WDATA. the value dependent on PSO and
PS1 is set in the LS163. (See Table 1.) For instance, when
both PSO and PS1 are low, it will set "1101 (D)" to the
LS163, counted up by the 8MHz clock, and QB is sent out
When it becomes "1110, 1111". When in EARLY (PSO=
"H", PS1="L"), the value "1110(E)" will be set to the
LS163 so that the output is issued 125ns earier than "not
changed". The QB output, however, will be supplied for a
period of two clock cycles.
2) Control during seek and recalibration
SEEK (or RECALB)
command to FDC
I
HALT
(waits for interrupt)
5-8. Media detection
Insertion of a media on the MFD is detected via the signal
INDEX from the MFD. Since it takes 200ms for the media
to make a full turn, "NO MEDIA" is detected signal
INDEX does not appear within 200ms.
tNI)
- 60 -
RtTKY
Read'result
status from FDC.
MZ 3500
In the case of the MFM method, need to trace cycle fluctuation is further increased, as a peak shift is apt to occur
because there are three write data cycles.
(Peak shift). Data read cycles fluctuate as the flux change
point is moved forwards or backwards.
Write pulse
Polarity inversion
Read waveform
Advanced peak shift Regenerated pulse
*— Delayed peak shift
H
Cb)
{VFO circuit): Variable frequency oscillator
Polarity inversion
f~J
Polarity inversion
Write pulse
J
Read waveform
j I
6.0 40 20
0
20 40
Advanced peak shift —-| t—
60
(a)
I
—•) j*- Delayed peak shift
(c)
When the output waveform is observed after writing a single
pluse on the floppy disk, the waveform show in (a) appears.
Shown in (b) is two pluses of 4jis interval.
Deviation in the peak point is called peak shift. Since pluse
intervals of the MFD in actual operation are 4ns, 6/JS, and
8/^s, the largest shift takes place when a pluse appears 8/Js
before or after 4/JS, as shown in (c).
5-10. VFO circuit
1) Purpose
n
String of data
pulses from the FDD.
n
Data window
String of
separate data
Data from the clock or data portion must be differentiated
when read from the FDD. For this purpose a window pulse
is used. In order to increase read tolerance, the VFO circuit
carses the window to trace phase changes in the read data
that take place during a floppy disk drive motor speed
change.
- 61 -
MZ3500
2) VFO circuit configuration
READ
DATA"
—»
h,
Phase
detector
k.
Filter
amplifier
^
Window
Data
separator
SEPARATED DATA
SEPARATED CLOCK
The VFO circuit has the following capabilities.
(1) Two modes: MFM and FM.
(2) The VFO circuit operation is suspended during the
SYNC field located before the ID field and data field.
(3) After suspention, the VFO circuit will synchronize
with the read data (timing is affected by a speed
change in the FDD). Fluctuations in an individual bit
that may be seen (peak shift are ignored.
VFO circuit
+5V
RtAD
DATA
-62-
MFM Mode
AlMHz
_rLTLJT_r
B)QA)
1_
Nomal
STD
Eary
n
Delay
©
J~L
MZ3500
FM mode timing chart
A 4M
B(QA)
C(QB)
D(QC)
WINDOW
E
F
L
Normal
O
P
F
L
Advanced
Q
O
P
L
K
Delayed
Q
O
P
Does not trace ± I
j
1
1
[
1
1
1
1
1
1
1
1
I
*
~
*
oinQle density ~^~^~~~^~~~
0
~—~^——^— LJQUOI6 density
*"
U.
o
/
1
/
2
c
o
,— ^
c
UJ
o
o
~
Q
s
..
5
o
o
o
0
O
O
0
0
\
S3
0
\
I
o
\
\
/
o
o
U,
U-
U,
U.
a.
s
5
cD
-
/
/
*
\
u.
u.
1/5
U
lO
U?
a)
U
10
w
/
Q
U
o
tQ
^_t
OS
UJ
H
.
c
o
^
(O
u
0
02-
1£
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L-i
O
o
*#-
ca
Csl
h
O
O
cc
m
H
8«
Q. J2
(J
I 2
£
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w
T— 1
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u
ro
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(U
O
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CO
s
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00
0)
lO
•
00
0!
,„
^
O
^"^-^
to
IN
VO
^—^_^
.2
73
QJ
•• Reverse side
•~"
M/asoo
Track 0, sector 1 information (SBACIS) (Fig
AA
7
L'
1
(
1)
00
02
00
00
04 i
i
1
00
!
i
I
/
M HF
i
c
|
1
'. OO1
i
'
1
1
48
1
!
i
1
i
041
1
Jv
IM
1
No, of sectors
m media
1
48
i
'
Start address
>
1
02
I
!
*
I
,
.
;
—I
'T
'< Oo!
01
i
>
1 r u U S I IM' SJ"L tor
01
'
i
,
N
I
SUB IOCS
BOOT
r
;
02
10
01
01
01
10
i
No of Track SIDE Sector
sectors
N
j
i
FF
,
No of END
sectors
f 0 . Single density, other than front side, track 0.
1 .
SIDE =
Double density, other than front side, track 0.
. Side 0 (front side)
1
Side 1 (reverse side)
No of data transfers INT=[IOCScapacity/1k] +1
0 track
*
8 sector
78
FF
F 10 11
FF|
+
Volume
name
IF 20
18
FI-
FF
t
FF
FF
Diskette Type
m SH/DD(M,ni)
<-C DH/DD(M.m)
Track No 1
Error Mep (Bad Treck)
Tr 3Ck No 2
cc
FF
80
01
I
Fail name (8 bytes) Expander
M A,r,Ar.
.4 (3 bytes)
No ALOAD command
File specification only
With operand
SC 3D
7F
FF
FF
For FLOAD command
Volume name
(8 bytes)
ALOAD
Status line No label
(8 bytes)
All "F" when ALOAD command
is not on
(Sbytes)
Contents of X register
When used for the line number (when line No 1 23)
These three bytes are in effect
Drive NO
34 35 36
3b>tesfj$!l
00 01 23
Channel
A (<•)
B (I)
When used for a label (Wight bytes are in e f f e c t a n d r e s e a r e )
1'
11
34
A B C I)
- 66 -
3C
f ?
7 F
M7 350?
o Map information
0 track 10 sector
0 track 9 sector
//
x
1
/
/
/
/
2
1 7H
129
&0H
130
I 71!
131
FFH
151
FFH
3
1
FFH
22
\
J
FFH
4CH
FFH
/
23
24
FFH
128 blocks are controlled
by one sector.
OOH-7FH
80H: End of link
FEH: Links to next map,
and the starting
block number.
152
FFH
153
75
76
77
\
\
126
\ 127
1
iy
/
1
^
\128
FFH
7 EH
FFH
FEH
FFH
FFH
Indicates the byte position
• from the top of directory.
25
01
00
02
01
FF
29
30
31
FF
FF
FF
MAPNa
Block NO
Starting block number (directory)
- 67 -
32
H
MZ3500
o Block number allocation
The program and data areas are located after Track 2
1 block = 2K bytes (8 sector)
(Double side)
(Single sided)
Block No
track
Block No
Front
track
Reverse
Front
2
BO
Bl
B2
B3
2
BO
Bl
3
B4
B5
B6
B7
3
B2
B3
I
I
38
B144
6145
B146 B147
38
B72
B73
39
B148 B149
B150 B151
39
B74
B75
2Kx 152 = 304K
2KX 76=152K
Each track is blocked in the following manner:
2 sec tor '
4
6
1 sector
3
5
1 block
1 block
13
15 sector
14
16 sector
o Track 1, Sector 1 information (CP/M)
0
i
AA
t
TRACK
SIDE
SECTOR
N
SECTO
^1 NUM
BER
t
Drive unit
specification
Represents the
system media
i
i
.
.
.
Load address
i
i
i
PATAT
*ANSF| -TRACK
ER NU 1KAt*
MBER 1
SIDE
SECTOR
N
.
.
.
Start address
BOOT
(•
20
SECTO
R NUM TRACK
BER
15
10
5
50
51
SECTO|~
I
R NUM T?F%! \
BER
j
j
SECTO
R NUM
BER
Indicates
the end
SUB-IOCS
._
0
1
Single density (front, Track 0)
Double density (other than front. Track 0)
0
Side 0 (front)
SIDE =
1
Side 1 (reverse)
Nosof data transfers = INT [IOCS capacity/1 K] + 1
• Sub IOCS can be divided into either blocks If divided to
less than eight blocks, the block that follows
- 68-
MZS500
6. R232C INTERFACE
6-1. General specification
Input/output format
RS-232C bit serial input/output
No of channels
1 channel
Code used
JIS 7-channel/JIS 8 channel
Baud rate
Transmission system
Half-duplex
Synchronization method
Start-stop
Communication control
procedure
Non-procedure
Data format
Stop bif 1/1.5/2, with or without
even or odd parity.
LSI used
8251 AC or8253C-5
(Programmable interval Timer)
110 to 9600 bits/sec
6-2. Data transmission format
2°
21
22
23
24
25
26
7-bit,
with parity
v
j v__^___/
„ _i \
Start bit
Data bit (7 bits)
Parity bit Stop bit (1 or 2 bits)
7-bit,
without parity
V
X
XV
Start bit
Data bit (7 bits)
V
X
'
Stop bit
8-bit
with parity
V
•
w
•'
V
Start bit
^
Data bit (8 bits)
^
Parity bit
_
Stop bit (1 or 2 bits)
8-bit,
without parity
v
,
y
Tr
Start bit
Data bit (8 bits)
Y
Stop bit (1 or 2 bit
Example: 7-bits, even parity, 1 stop bit
Start bit
7-bit data (26H)
Stop bit of preceding data
Parity bit
Start bit of
succeeding data
Stop bit
- 7) -
MZ3500
6-3. Block diagram of the interface
Control signal
Peripheral
6-4. System switch functions
ON
OFF
SW5
Causes an error when the
ER signal is low or open
during data output.
ER signal is disabled.
SW6
Always high when power is
on to the main unit.
The CD signal is set high
while data output, but
would not be set high
when the echo-back
function is selected for
the host computer.
SW7
Causes on error when the
PO signal is high during
data output.
Polarity is inverted.
6-5. 8251AC controls
c
There are two control words for the 8251 AC.
(1) Mode instruction: Defining general operational parameters, such as unit, stop bit, etc.
(2) Command instruction: Defining status words used for
actual operation, such as send/receive enable, etc.
START
8251AC internal reset
1) Definition of generation operational parameters
• Baud rate
• Character size
• Even/odd/off parity assignment
••Stop bit size
"Corresponds to channel command of BASIC.
8251AC mode instruction
- 72 -
MZ3500
2) Data output control
SKNU
Command instruction
(KTS,RXEN,TXEN)
8251 AC
"L"->KTS
»- 8251 AC
Set counter (200ms)
ERROR 101
Stop
Output data to
8251AC
The 8251 send data when CTS goes low.
The 8251 AC would not output, unlessv
CTS goes low. Therefore, the state of \
CTS will be checked when the buffer I
.becomes empty.
/
ERROR 101
- 73 -
M/3SOO
3) Data input control
RCV
Command nstruction
8251 AC
( E R . R X DISLN)
8251 AC
/Error reset
\
\Data input disable/
Read one data
/Clears the data before
N
Vthe start of the receive command /
Command instruction
(RXEN,UTR,TXEN)
- 8251 AC
8251 AC
,
\" L "-»DTR
Waits for NMI by
the RXRDY signal
Resets error by setin
DTR high
Command instruction
( tK >
8251 AC
ERROR
ERROR
- 74 -
N
/ Data input enabled
( Data output enabled (echo-back, selected)
MZ 3500
6-6. 8253 Controls
Baud rate of this interface will be determined by the clock
output of the 8253. The 8251 is configured such that its
baud rate is 1/16 of the input clock and has the following
relation between the 8253 output clock and the baud rate:
1 1 0 .t 300
1760Hz
4800
600
9600
1 200
2400
4800
9600
8253 input frequency: 2457.6kHz
8253 Mode set: Mode 3(rec'angle waveform rate generator)
8253
Parameter
8253
Output frequency
Baud rale
1 3 9 6.3 6
51 2
256
128
64
32
16
1 9200
38400
76800
153600
Control signals
Signal name
Symbol
IN/OUT
Transmission enabled
CS
-* Peripheral
When high, data input from a peripheral is enabled.
When low, data input from a peripheral is disabled.
Data set ready
DR
— Peripheral
Goes high when power is on to the interface unit.
Carrier detect
CD
— Peripheral
(SW6-ON) High at all times when power is on to the interface unit.
(SW6-OFF) Goes high only when data is on output.
READY
— Peripheral
Data output from the interface is enabled.
(ON) Data is output from the interface.
(OFF) Waits for data output.
NOTE: A maximum of two bytes are output after the signal goes from high to low
state.
Equipment ready
ER
«- Peripheral
Indicates that the peripheral is ready. It results in an error if low or open when data
is sent from the interface. This signal will be invalidated when the SW5 is turned
off.
Paper out
PO
<- Peripheral
(SW7-ON) Causes an error if set high during data output.
(SW7-OFF) Causes an error if set low during data output.
Ready
Function
6-7. Description of LSI's
1) UPD8251AC (Programmable Communication Interface)
The UPD8251A is a USART (Universal Synchronous/
Asynchronous Receiver/Transmitter that was specifically designed for data communication.
The USART receives parallel data from the CPU and
converts it into serial data before transmitting. Also,
serial data is received from an external circuit and transferred to the CPU after converting it into parallel. The
CPU can monitor the current state of the USART at
any time (data transfer error, and control signal of
, SYNDETandTXEMPTY.
,-eatures
• 8080A/8085A compatible
• Synchronous/asychronous operation
• Synchronous operation
5 — 8 bits character
Clock rate: baud rate x 1, x16, x64
BREAK character generation
Stop bit: 1, 1.5, 2 bits
Error start bit detection
Automatic break detection and operation.
• Baud rate: DC - 64K baud
• Full-duplex
Double buffer type transmitter/receiver
• Error detect
Parity, overrun, framing
• Input/output TTL compatible
• N-channel MOS
• Single +5V supply
• Single phase TTL level clock
• 28-pin, plastic DIP
• Intel 8251A compatible
Pin configuration (Top View)
<28 »OD1
3?5 PORTS'
422-0 DSR
-i-2—XDTXEMPTY
3*12-0 CT3
SYNDET BD
TXRDY
Block diagram
1)7-1)004
8
»
Data
bus
buffer
8
„«.
8
RESET O
»•
8
Read/
write
control
logic
1
Transmission
t *
Transmissic>n
control '
34
_
X>TXE
OTXC
Reception
8 buffer
Dsko
m
MOOhM
t rscx — x: controller
k'l so*
( S -• P )
*
^_
8
c
V
Internal data bus^
- 75 -
t 1
Receiver
^ control
HI)
M Z 3500
DO~D7
Data Bas
RXD
Receive Data (IN/OUT)
WR
Write (IN)
RD
Read (IN)
C/D
Control/Data (IN/OUT)
CS
Chip Select (IN)
DSR
Data Set Ready (IN)
DTR
Data Terminal Ready (OUT)
RTS
Request to Send (OUT)
TXC
UO
O
Data bus AA
buffer
v-v
Counter •«
t 1 KO
Counter
<
# 1
<
/«--N
\r,V
C1K 1
OA1 ^ 1
»-()l
£
I1
t
^
^
2) UPD8253C-5 (Programmable Interval Timer)
—
Control
word
register
The UPD8253-5 is a programmable counter/timer specifically designed for the 8-bit microcomputer system.
Counter
/"
**w
'
1
A^S
S— K]
*«
Cl K2
GA1L2
# 2
KHT2
It consists of three sets of 16-bit counters that operate
under a maximum counter rate of 4MHz. Timer and six
1
operational modes are programmed to be used for a wide
t
range of microcomputer system timing control.
Features
•
Z-80 compatible
D7-DO
Data Bus (8 bit)
•
Three sets of 16-bit counters
CLKN
Counter Clock Inputs
•
DC-4MHz of count rate
GATEN
Counter Gate Inputs
Programmable
OUTN
•
six operational modes
and timer
duration
RD
Counter Outputs
. Read Counter
•
Choice of binary counter/BCD counter
WR
Write Command or Data
•
N-channel MOS, input/output TTL compatible
CS
Chip Select
•
Single +5V supply, 24-pin DIP
A1~AO
: Counter Select
Intel 8253-5 compatible
Vcc
. +5 Volts
GND
. Ground
•
Pin configuration (Top View)
.VCC
- 76 -
M 2 3500
8251
CLK
DTK
IN
IN
OUT
CTS
1 N
DSK
8251
chip address[0001/xxxx]
IN
Uix
OUT)
2.45MHz clock
DATA SET READY
READY
DATA TERMINAL READY
TRANSMITTER DATA
CS
PO (MPER SUT), ER
CD
RD
TRANSMITTER CLOCK
RECEIVE DATA
OUT 0 of 8253
SD
RECEIVER READY
To 3iil>CPU of
RECEIVE CLOCK
8253 OUT
CLEAR TO SEND
OUT
Rl S
OUT
TXD
TXRDY N.C.
TXE
N.C.
IN
TXC
IN
RXD
RXRDY OUT
IN
"RXC
SYN/BD N.C.
REQUEST TO SEND
8253
CLKO
GATED
8253
chip address[0010/xxxx]
IN
#UxH
OUT#|2XH
OUTO
CLK1
GATE1
OUT1
CLK2
GATE 2
OUT 2
IN
IN
OUT
IN
IN
OUT
IN
IN
OUT
2.45MHz
Vcc
To TXC, RXC of the 8251
2.45MHz
From OUT2
MUSIC
2.45MHz
Vcc
To GATE 1
INTO TO MAIN FROM SUB
POWER ON RESET
INTO
H
SOO - S I W ( I O R Q - W R o f S U B )
L
fNTR=L(FROM MAIN)
H
INT TO SUB FROM KEY
STK= (L)
- 77 -
M 7. 3500
7. PRINTER INTERFACE
7-1. Printer interfacing circuit
AS 4 • AS 5 AS6 • AS 7
AR
SO3
Chip
CS 8255
I )fi i >de r
rs.
RI)
3C r-— •^ —°
I ORQ
°^ *-!-"N
cf^
1i—
cjX
Al
Z80
SUB
CPU
AO
PA 0
-^jp
-J
S1W
PA
RD
H/
PA 2
WR
A
© DA1A2
© "A^A3
H^
PA 3
Al
^
1
PA 4
°
PA 5
C|^»
ts^
CP^»
PA 6
i^^
PA 7
ol ^^
rv_"v*~i
PC 5
PC 6
rs_
1 "No
(3) DAT 16
—
(g) DATA?
Op) D \TA S
ffi\ STRDRF
^o^l-X}—^^^ACK
PC 7
PC 0
PC 1
PC 2
1
, DSO
_ DS1
^ DS2
L_
0<
~ xr
DS4
^ DS5
v
Io^l
^J
DS3
.^
///
n EU®
©) PDTR
LS244
DS6
^ DS7
* 2,4,6,... 28areGND.
* Ahnwp nin numbers are of the model-3
'arallel interfacing signals
Function
Pin No.
Signal name
IN/OUT
1
STROB
- PRINTER
Data is transfered to printer when STROB is high.
3
DATA 1
5
DATA 2
7
DATA 3
9
DATA 4
-PRINTER
Data output to the printer
11
DATA 5
13
DATA 6
15
DATA 7
17
DATA 8
19
ACK
- PRINTER
Indicates the end of character input or function input
21
BUSY
• PRINTER
When high, it enables to receive data
23
PE
- PRINTER
When high, it indicates paper empty
25
PDTR
- PRINTER
When high, it indicates the SELECT mode (receive enabled!.
27
SYSRES
- PRINTER
Reset signal, normally high
- 78 -
i
7-3. General description of the parallel interface
The 8255 is used for the LSI to control the parallel interface. The 8255 can be set in the following mode.
/PORT A: MODE 0
I P O R T B : MODE 1
C: Output
74.
Because it is not possible to directly sense the ACK signal as
it uses interrupt for key processing and RS232C input, the
ACK signal is latched by means of the OBF pin function
Data transfer timing
BUSY
ACK
( 8255 A
v
PC-7J
DATA
STROBE
(M1N)
l^s(MIN)
PRINTER: MZ-1P02, MZ-1P03 CE330P, 331P, 332P
* Broken line in the above figure represents timing for the
CE-330Pand331P.
'For detail of timing, refer to Manual provided with
printer.
7-5. General description of control software
Set the 20 second counter.
STROBE OUT
Set the 20 second counter.
- 79 -
M / 3500
7-6. I/O port map
8255 ON SUB CPU BUS
PA6
DATA8
DATA"
i'A5
DATA6
PA7
IN
OUT
I'A4
I'A3
8255
PA2
chip address(0011/xxxxj
PA1
I) AT A 5
Output
DATA4
DATA3
PAO
ACK T-SET
ACK
PC6 ACK inputi
STROBE J
PCS
MUS 1C , sustain
PC4
1NTR
NOT USE
PCS
ACKC
PC 2
PC7
Group A: Mode 1
Group B: Mode 0
O
3
OBF output
PCI
STC
PCO
PB7
PB6
PBS
PB4
PBS
DC
Output
P/M
CG selection
SRDY
Sub CPU R E A D Y
Dm
C2
Cl
CO
STRB
PB1
PBO
INPUT P O R T C 7 4 L S 2 4 4
74LS244
CDS6D
HLT KEY
STK
-i
port address[0100/xxxx]
CDS5D
DK
CDS43
PUTR
CDS33
CDS2D
PE
BUSY
CDS7D
Keyboard
CLK
PB2
IN
#4X
OUT
Printer
DATA2
DATA1
Keyboard
J
Printer
cosn
Reads the 8255 OBF (PC7)
CDSOD
output or timer output.
- 80-
Clock
M 2 3500
8. OTHER INTERFACES
8-1. Clock circuit
1) Schematic
T;
10
*
Ii2
u
HDH
l«"-.r
"
1
2) Clock timing
READ
mode
Cn(CO~C2)
STB
HOLD .
mode [
0 X
READ
mode
3
/
Y~l
\
/
^Ones digit of seconds
Tens digit of seconds
WRITE
mode
DIN
Tens digit of month '
HOLD
mode
SET
mode
Don't care
X
CLK
DOUT
Tens digit of seconds
Tens digit of month*
- 8) -
i
I
HOLD
mode
MZ3500
3) ^PD1990AC
Block diagram
OK O
Command specification
Data Shift
DOUT
C1
CO
Command
0
0
0
Register hold
Holds 40-bit S/R
1Hz
Not possible
Data retention
0
0
1
Register shift
Data input/output
[LSB] Output of LSB
Possible
Shifts in synchronization
with the clock
0
1
0
Time set
Data of the 40-bit S/R is
preset to the time counter.
ILSB] Output
Not possible
Time read
Data in the time counter
is read to the 40-bit S/R.
[LSB] Output
Not possible
0
1
1
Description
Note
C2
Input/output format
Example: In the case of 10 o'clock, 25 minutes, 49 seconds, July 30th.
(LSB)
9
(MSB)
4
«- Seconds—'
5
2
L(\/|jnutes—I
0
1
Lnoure_)
- 82 -
0
3
L_Dey—I
7
Won
!Onth
J
8-2.
Voice input/output circuit
PD8255
Music output waveform
•
mmmil
Tonal signal
OUT1
• Sustain
PC4
•
2SC458
emitter
•
2SC458
collector
• Speaker
output
» GETE1
u
-Tlj
1
J
- 83 -
M/3500
83.
Expansion and interrupt (See 3-(2)-4 for interrupt)
1) Options and expansion units
Options not requiring expansion unit
JIS keyboard
14" medium resolution color CRT
12" high resolution green CRT
1 2" high resolution color CRT
14" CRT tilt stand
12" CRT tilt stand
Light pen
80-character pnnte
MZ 1K01
1001
1D02
•1D03
-1S01
-1S02
•1X02
-1P02
-1P03
-1P04
CE-330P
-333P
-33 1M
-330X
MZ-1F02
-1F03
-1R03
-1R05
MZ-1E01
RS232C 1/F
-1E02
•1E03
GP I/O
SFD 1/F
-1F05
-1R06
SFD unit
RAM
(7)
©
Color injket printer
80-character printer
136-character printer
Optional MFD drive unit
Plotter
Optional MFD drive unit
Optional MFD drive unit (single deck)
Graphic board
2) Expansion unit
Signal assignment by slot
Main CPU
bus line
SLOT1
SLOT2
SFD CONTROL •
VOICE
DRAM control signal
32K mask ROM
BASIC(
8K mask ROM
ROM1
ROM2
ROMS
ROM4
INT1
INT2
I NTS
INT4
-84-
L
SLOTS
SLOT4
M 7 3500
8 4
System SW1 (DIP SW) (User operative through the cabinet bottom)
No
Signal name
1
SW1
Function
Description
Position
Polarity
ON
L
OFF
H
ON
L
OFF
H
ON
L
High resolution CRT (MZ1D02. MZ1D03)
OFF
H
Medium resolution CRT (MZ1D01, MZ1D06)
ON
L
A period is output for a decimal point
OFF
H
A comma is outputted for a decimal point
ON
L
Low state or open ER signal during data output
will result in an error
OFF
H
The signal ER becomes invalid
ON
L
CD is high as long as power is on to the main
unit
OFF
H
CD goes high only during data output However,
it would not go high if the echo back function is
on the host side
ON
L
An error is cause when the PO signal is high
during data output
OFF
H
Polarity is inverted for the above
ON
L
Normally in capital letter, but in small letter
when shifted
OFF
H
Normally small leter and in capital letter when
shifted
ON
L
3500 CG will be assigned when the 200 raster
CRT is in use
H
2000 CG will be assigned when the 200 raster
CRT is in use
SW2
ON
OFF
ON
OFF
Printer select
SW2
2
SW3
3
SW4
4
SW1
ON
ON
OFF
OFF
#47 pin of MMR
CE332P
MZ1P02
IO2824
£48 pin of MMR
#51 pin of MMR
CRT select
Choice of decimal
point output
format
#52 pin of MMR
SW5
5
SW6
6
7
RS232C
assign
SW7
FD1
(SW8)
8
P/M
(SW9)
9
Key shift mode
setup
Choice of CG
for display
OFF
ToCTS, DSR
of the 8251
ToCTS of the
8251
#54 pin of MMR
(FDD
P/M signal
(To A3 CG)
NC
10
^
=
— =T
Dip switches (A) and (B) located on the PWB are used for
servicing the MFD or for other machine service and there
fore the user is not supposed to use these switches
In
addition, these switch must be used when either the CE
330M or 331M is used as the expansion MFD
DIPSW(A)
No
Signal name
1
SEC
(SW1A)
t
44 pin of MMR
2
FD2
(SW2A)
56 pin of MMR
3
FD3
(SW3A)
58 pin of MMR
SRQ
(SW4A)
Bus request
to sub-CPU
4
DIPSW (B)
No
Signal name
1
SRES
(SW1B)
SUB CPU
reset signal
2
SW2B
SUB CPU BUS
select signal
1
2
3
OFF
OFF
OFF
WhenSH in use
ON
OFF
OFF
When DH in use
OFF
ON
OFF
ON
ON
OFF
OFF
OFF
ON
—
—
Use of the CE330M as an expansion unit
ON
OFF
ON
Use of the CE331M as an expansion unit
OFF
ON
ON
Check mode *1
ON
ON
ON
Check mode *2
*1
Test program is loaded and executed
*2
Provided for the test of the MFD interface
The
read/write test is carried out for the expansion unit
\
Used for an individual test of the CPU PWB When these
three switches are turned off altogether, it makes the
sub CPU operated independently
condition under a normal situation
To be used in th ON
MZ3500
DIPSW(B)
DIP S W ( A )
•
1
2
3
4
1
2
OFF
OFF
OFF
ON
ON
ON
Switches are set in this manner before shipment of machines this us the
single-sided minifloppy disk drive.
ON
OFF
OFF
ON
ON
ON
Switches are set in this manner before shipment of
machines that use the double-sided minifloppy
disk drive.
OFF
OFF
ON
ON
ON
ON
Switches are set in this manner when the SH is used for the optional MFD
ON
OFF
ON
ON
ON
ON
Switches are set in this manner when the DH is used for the optional MFD
OFF
ON
ON
ON
ON
ON
Test mode * 1
ON
ON
ON
ON
ON
ON
Test mode "2
OFF
OFF
OFF
X ><^
\(f
Individual CPU PWB test
Can be in either state
- 86 -
, My-it^n Pn^41
( 11/171540' vv"=/n
' '
MZ3500
9, POWER CIRCUIT DESCRIPTION
1. BLOCK DIAGRAM
(Block diagram)
A. +5V and +12V supplies
1. Functions
a. Supply voltage is first rectified in the rectifier circuit
and sent out to the switching regulator via the overcurrent detector provided in the overcurrent protect
circuit.
b. Next, the voltage is converted to the +5/+12V output
in the switching regulator and sent out to the noise
• Nfilter.
c. Change in the switching regulator output voltage is
sensed by the control circuit and is fed back to the
switching regulator after being amplified in the amplifier
located in the control circuit, for maintaining the output
voltage to a constant level.
d. The signal from the oscillator is supplied to the switching regulator through the control circuit for driving the
switching regulator.
e. For prevention of overcurrent, the protect circuit is used
for stopping the oscillator when an overcurrent is met,
and it makes the switching regulator to halt in order to
shut off +12V/+5V supply.
2. Description of each block
a. Overcutrent protect (control/protect) circuit
When an overcurrent is met in the +5V/+12V circuit, it
causes to increase the voltage at both ends of the overcurrent detector resistor R1, which in turn causes to
increase the Q3 collector current, for, there arises larger
voltage difference between the emitter and base of the
transistor Q3. This makes the gate voltage of the thynstor increased owing to activation of SR. Witr, jctivation
of SR it makes the oscillator voltage dropped to the
GND level at the point "a" to stop oscillation, which
also makes the switching regulator stopped by the deactivation of the transistor Q5 oscillation. This causes
the transistor Q5 inactive, and it shuts off the +5V/
+ 12V supply,
b. Oscillation circuit
As the Q1 emitter voltage is at almost GND level whethe transistor Q1 is active, the Q2 base voltage temporarily drops close to the GND level by means of C6,
which in turn makes Q2 inactive and the Q2 emittei
voltage increases.
Then, the Q2 base voltage comes to rise as C6 begins to
be charged through R6, and the transistor Q2 starts to
activate again. With activation of the transistor Q2, the
Q2 emitter voltage starts to drop and the Q1 base
voltage is temporarily dropped by means of C5, to shut
off the transistor Ql, which causes to increase the
transistor Q1 emitter voltage.
Next, as C5 is charged by R5, it makes the Q1 base
voltage increased which puts the transistor Ql into
activation. In this manner, transistors Q1 and O2 are
alternately turned on and off to keep oscillating.
C5 and C6 are charged through R5 and R6 by on/off
action of the Q1 and Q2, and discharged through Ql and
Q2.
M 7,3500
Switching regulator
+ 5V
or
Q5
(Switching regulator and constant
voltage control circuit)
« VR is the+5V or+12V adjusting VR.
• D3 is provided to discharge current from Cj after power off.
- 88-
M23500
c. Power switching circuit
As the signal from the oscillator is amplified through Q7
to Q6 to change current to the transformer T2. it causes
voltage to appear on the base of Q5 (one of components
is cut by D1), so that the transistor Q5 begins to perform switching operation in synchronization with the
oscillation frequency. As Q2 is switched, current is
supplied to the emitter side of the transistor Q5, which
produces smoothed voltage through the capacitor C1
and the coil L2. The circuit composed of D4 and VR1 is
the reference voltage for the +5 or + 12V supply, which
is used to control the emitter current flowing to the
transistor Q9. The current supplied from Q9 is used to
create Tr3 inactive by the delayed C1 and C2 voltages
which supplied from Tr1-R2-VR1-D3. It goes high with
deactivation of Tr3.
3. Alarm circuit
(Alarm generation circuit)
When power turns off, the voltage accumulated in C1
and C2 are supplied to the base of Tr2 via Tr1 ... and
D3, so that Tr2 is kept active and Tr3 inactive for sometimes after power off.
Timing chart
SW
+ 5V
PFD
-89 -
MZ3500
10. MZ1K01 KEYBOARD CONTROLLER CIRCUIT DESCRIPTION
10-1. Specification of keyboard control
11) One-step commands
uior
1) Input Buffer
Capacity: 64 bytes
• Key-in data is written to the input buffer first, and is
supplied to the CPU, byte by byte.
• When an overflow is detected, the overflow code is
affired to the key-in data already sent, before being
sent to the CPU.
2) Rollover
• 2 key rollover (exemption in the CTRL mode)
(Entry of the second key depression can be accepted
even if more than one key is pressed at same time.)
• Simultaneous depression of more than three keys is
ingnored.
3) Key bounce
15msec (Key spec is 5-10msec)
(Indicates unstable state as shown in Fig. 3-2 that key
signal does not turn off immediately after releasing of
finger from the key.)
LMU /
5)
[
6)
7)
8)
LML) o
INrU T
UMU 4
USING
pft/in "7 .
(jU I U
pr\ci ID
Kb 1 UnN
Lib 1
PMH n .
PMn A
At rrn
ULUbt
PMH n -
n ATA
CMU K.
K.hY
IN
i OAH
nrUnMA 1 fF
PMH i
r*Mn r\ -
nhAU
PMH c
4) Key
5msec (norma), 20msec (max),
15msec (allows for key bounce)
DEF Key
Twenty definable keys are available in combination with
the CTRL key.
DFK1-DFK10
(DEF1A-DEF10A)
DEF1-DFK10 in conjunction with the CTRL key
- - - (DEFIB-DEF10B)(DEF1B-DBF10B)
Handling of functional symbols and graphic symbols
See the code table.
Use of the CTRL key to discriminate RUN and CONT of
the DEB key.
Push the DEB in conjunction with the CTRL key to
start running.
Handling of special codes
COPY command: CTRL | 1 J (ten key)
ESCape
CTRL
BRK
CTRL
rnlNI
CA\/C
12) Mode indication on LED
Acrn
i nr^w
13) REP
Key repetition will take place when a key depressed for
more than 0.64 second. Entry of other keys is permitted
during key repetition. When two keys are depresssd at
the same time, an alternate key entry will not be
accepted. This rule does not apply to simultaneous
depression of more than three keys.
9) PRO/OP
Sent to the CPU after power on and when PRO/OP is
changed.
10) HOME key
CTRL
[ HOME] Returns home after clearing the
display screen.
[HOME] Only the cursor returns home.
- 90 -
MZS500
10-2. Key search timing
Single key entry
Bounding
/
Key
n
STROBE
n
n
n
n
n
n
n
15ms
1 Strobe *~5.5ms M 5ms -»
RETURN
cvcle
n
n
n
n
n
n
n
DATA OUT
Two key entry
/A"
Key 1
Key 2
n
STROBE
n
n
n
-5.5ms—M—•6.5ms —M—5ms —W
n
RET
n
n
n
n
n
n
n
n
15ms
M
15ms
DATA
(1)
OUT
DATA
(2)
OUT
10-3.
Key serial transmission procedure
1) Data format
Key -» CPU
2s
2s
22
21
2°
Parity
DATA
All nine bits
Command
AM 4 bits
Key
Parity
- 91 -
MZ 3500
•
Command flag: "0" when succeedeing 8 bits are a key
data. "1" when it is a command or a graphic control
data.
• Data: Positive logic (negative logic on the cable)
• Parity: Odd parity up to 27 bit from the correction flag.
2) Interfacing signals
CPU level
• D(K): Output data from the keyboard.
Positive logic
• ST(K): D(K) strobe signal. Also use for Active H
interrupt to the CPU.
• ACK(C): Acknowledge signal form the Active H
CPU. Also use for the data
transfer
interrupt disable
signal.
• D(C): Output data from the CPU.
Positive logic
• ST(C): D(C) strobe signal. Also use for Active L
interrupt to the keyboard side.
3) Protocol
Key to sub CPU
• Keyboard to the sub-CPU data transfer tapes place with
interrupt applied at every signal word (STK).
• As the sub-CPU detects a next strobe (STK) after going
into the interrupt routine, it read data (K) as far as the
final parity bit, and the ACK (C) signal is sent back to
the keyboard side when the check-sum is correct.
• If the ACK (C) signal returns with normal timing, the
keyboard controller accepts it. Unless the ACK signal
was detected, the same data is sent again assuming a
transmission error.
•
Case when the error data link (sub-CPU not enable to
receive data properly) is established.
1) When parity error is found after the check-sum test.
2) When the sub-CPU is in execution of the NMI routine
or when NMI is applied during data tranJ.jj,
3) When an error is detected in the couting of strobe
(STK(K)) due to noise.
When one of above conditions is detected, data will be
sent again until received correctly. Key entries during
this periode are strobe in the key buffer. Should the key
buffer overflow, key entry will not be stored in the key
buffer.
• When a key buffer overflow is detected a KBOF error
code is inserted in the area vacant immediately after
transmission of one key-in data, without clean '~ "
key buffer contents.
SUB CPU TO KEYBOARD
• Basically the same as the above cases.
• Data is 3 bits plus parity bit.
• Return acknowledge pluse: Parity OK . .. STK + DK
Parity NO ... STK only
•
KEY TO CPU (80C49, Z-80)
CPU level
D(K)
n__TL_n
ST(K)
32.5
12.5
SUB CPU
INT
ACK(C)
50
22.5/-s
50
I
17.5 ,«s
60~ 300ns
CPU ->• KEY
D(C)
ST(C)
~ir~Ln_rrr~Lr
.
132.5
ST(K)
D(K)
1
60
7.5
*s
AS
/d« SEEK error
and RECALIBRATE
- 99-
MZ3500
MAIN CPU CHECKER FLOW CHART
M?
Option HAM
read/write check
Change bank of
the option RAM
Error
on display
C
- 100 -
HALT
M 7*500
SUB CPU CHECKER FLOW CHART 1/3
(
SUB CPU
CHECKER START
^
I
CRTmt*f face t«t
SeiGDCto«00
1
DATA
1
[r
IA
IB
2Y
2A
2B
F
CLfcAH
A
R
1
1
A
B
C
U
CLOCK
INHIBIT
JJ
>T
LJ LLTLJ LiJ LJ LJ LlJ LJ
L
D
N
PARALLEL
-
Vt
Y4
i
Yd
Y*
Y5
CLOCK CLOCK
" INHIBIT
(MI>
INPUTS
Y6
I [
Y6
A
<
<
t\
( 1
Y7
ii
Y7
H
r LJ
, 1 , LJ
LJ U LJ U LJ LJ
LJ LiJ LiJ LJ LL! LiJ LJ
1Y
Jl
Y]
QH
1
H
(H TPLTb
V
i
M
(,
SFRIA1
INPUT
74 LS 1 38
Yl
UH
I OAD
SERIAL
INPUT
mm
H
SHIf I
Jr
[
LU LLI LiJTiMU LU LU
GNI)
( M
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LJ LJ U U U LJ U
if
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Va
C^D
1
A
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C
CSD
74 LS 03
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4A
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3B
3A
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tNAHI t
1C
1AI
2Y4
K
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IA3
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CM
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74 LS 139
SELECT
DATA
OUTPtTS
E \.AHI t ,
C
H
LJ LJ LJ LJ LJ LJ LJ
IA
IB
1Y
2A
2B
2Y
GND
NtC
A
1
1
J>
j],
C
A
B
YO
Yl
Y2
Y3
A
B
YO
Yl
Y2
Y3
1
i
Y
Y
IA
IB
1 Y2
1 Y3
C
74 tS 04
6A
6Y
SA^
5Y
4A
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SELECT
Y Y
1 YO
*
IYI
DATA
A
^
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1C
GND
IA1 2Y4
1A2
2Y3
1A3
2Y2
lAi ZY]
GND
'
OUTPUTS
m
LJ LJ LJ LJ LJLJ LJ
IA
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4B
4A
2Y
1A
1Y
3B
3A
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74 IS 08
4Y
H I r1 I
I
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LJ
LJ
LJ
LJ
LJ
LJ
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1Y
2A
2Y
3A
SY
LULU LD LJ LU LU LU LJ LU Lll
C.ND
/
1NPLTS
A
OUTPUT
,
INPUTS
y
OUTPUT
LJ LJTJLJ LJ LJ LJ
IA
IB
IY
2A
2B
2Y
GN1>
J
(
Vg
1C
IY
3C
3B
3A
4A
4B
4Y
SA
3B
—s
3Y
3Y
M R R R R Rm
J
Y
LJ LJ LJ LJ LJ LJ LJ LJ
SI-1
tO
IA
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1 Sf I I ^
IN
2A
B
2Y
LJLJLJLiJLJLJLJLJLJLJ
CLEAW
1Q
ID
2V
2Q
3Q
3D
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GND
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LJ
LJ
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LJ LiJ LJ bJ LJ LUTJ TZT
LLlQJ
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1A
1Y
2A
2Y
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3Y
GND
LH008O
S4S1S7
INPUTS
ENABLE
' O
f
STROBE
4A
4B
A! 1C 1
A12C 2
A13C 3
IN
4Y
2A
A14C
C
4B
4A
4Y
2A
S
-
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bJ
LJ
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2D
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2B
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2B
CLKC
2Y
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SELECT
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2A.
2B
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CND
4Y
SB
JA
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171 m nyi ryirTi n
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D7C 13
DOC 14
D l C 15
TVTT: 16
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N M l C 17
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HALTC 18
MK1-.OC 19
TOKOC 20
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IT3B
3
Dl
13
A
2j
KOAB
33
kh2B
43
IT4B
4
D2
14
24
ROBR
34
WATB
44
She
5
D3
15
SKO
2S
35
RLMB
45
(,M>
6
D4
16
AR1 3
26
KI;LB
RO[>n
36
1TI-B
46
(AD
7
D5
17
AR1 4
27
K-, Mi
37
i roB
47
S»l
8
ns
18
\K1 *
28
K'-MH
38
IT] R
48
M
,r
I"
su 2
\"
\1 5
20
30
I1
10
1' i 1
1 O\
50
Rl-SH
51
SW3
61
C,M>
71
(.NO
52
S»4
62
(,ND
72
1MB
53
(,M>
63
K02B
7d
Nt
54
h»l
64
K03B
1
ksim
i i ; i,
40
VkOIl
©©
©©©©©©©©©©
A7C
55
(.SD
65
HDD
2O1 6P
56
H)2
66
(.1 k
M58725-15
6116P-3
57
SYSR
67
K04B
58
H>3
68
MPX
59
COAB
69
(,M>
60
RO 1 B
70
C ASB
~
^~
24 D V U)
A6C 2
A5C 3
23 DA8
A4C 4
A3C 5
21 ]K'-»
20 3cFI
\2C 6
11 D AIO
AlC 7
18 ]c_!-2
22
DAS
AOC
8
17 3 1 1)8
i>i C
9
16 3 1 XT7
1>2C 10
•03 C I I
15 3 1 'J6
.MC 12
13 3 I 04
14 3 I 1)5
20
MZ-35OO
PARTS GUIDE LI
MZ-3500
li Exteriors
PARTS CODE
NO
1 CCABC1007ACZZ
2
31
4|
!>
6
7
8
9
10
11
12
16
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
G F T A F 1 0 0 1 A C Z Z
HBDGB3004GESA
T L A B Z 1 0 0 3 A C Z Z
T L A B Z 1 0 0 8 A C Z Z
QCNCW1008AC01
Q PWB F 1 0 0 5 A C Z Z
V H P G L 9 P R 2//1
GCABA1003ACZZ
G F T A U 1 0 0 5 A C Z Z
PSPAG1004ACZZ
T L A B Z 1 0 1 7 A C Z Z
X B P S F 3 0 P 0 6 K O O
OUNT-1018ACZZ
DUNT-1035ACZZ
GCABB1004ACZZ
GCOVH1 00 1ACZZ
LANGT1003ACZZ
LANGT1010ACZZ
LCHSM1008ACZZ
L X-l Z 6 0 2 3 R C Z Z
NFANP1001ACZZ
RMEMR1002ACZZ
GLEGP0010UCZZ
XBPSD30P08KSO
XBPSD40P06KSO
L X-B Z 1 0 0 1 ACZ Z
X B P S D 4 0 P 0 6 K O O
X B T S C 4 0 P 0 6 0 0 0
X B T S F 4 0 P 0 8 0 0 0
XCPSD40P12000
PHOG-1001ACZZ
GFTAF1002ACZZ
LHLDW6655RCZZ
QLUGL0006UCZZ
XBPSD30P30KSO
VR S - P T 3 L B3 3 0 J
LHLDW6655RCZZ
PSLDM1003ACZZ
TLABZ1400CCZZ
PRICE
RANK
A Y
A E
A E
AB
A A
AC
A A
AC
BM
A L
AC
AC
A A
**
**
BG
AM
AX
A E
AY
A A
BM
**
AB
A A
A A
AC
A A
A A
A A
A A
AC
A E
AB
AB
A A
AC
AB
AP
A A
NEW
MARK
N
N
N
N
N
N
N
N
N
N
N
N
N
PART
RANK
D
D
D
D
0
C
C
B
D
D
C
C
C
E
E
D
D
C
C
C
C
B
E
C
C
C
C
C
C
C
C
C
D
C
C
C
C
C
C
C
D E S C R I P T I O N
Front Cabinet assembly
Lid for Graphic slot
Badge "SHARP'
Label "POWER 1
Drive No label
Connector 2pm
LED PWB
Photo transistor
Bottom cabinet
Lid for ROM LSI
Rubber spacer
Label for l/O^ort
Screw
Power supply unit for 200V series
Power supply unit for 100V series
Top cabinet
Slot cover
Fixing angle for MFD
Fixing angle for fan
Chassis
Rivet
Fan motor
MFD unit
Rubber foot
Screw
Screw
Screw
Screw
Screw
Screw
Screw
Rubber cushion
Cover
Wire holder
Lug terminal
Screw
Resistor (3 OW 33n ±5%)
Cord holder
Shield for MFD
Label
1
1
I
oe
IE--or
ooss-zw
MZ-3500
[2] PWB & Fixing angles
NO
1
2
3J
4
5
6
7
8
9
11
12
13
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
31
32
33
34
35
PARTS CODE
JKNBM0004PAZZ
LANGS1006AC2Z
L A N G K 1 0 0 7 A C Z Z
OCNCW1 0 0 8 A C 0 2
Q S W - K 1 0 0 7 ACZ Z
R V R-A 5 4 5 2 QCZ Z
VSP0080P-608N
XBPSD30P06KOO
DUNTK1082ACZZ
DUNTK
083ACZZ
DUNTK
0 6 4 ACZ Z
DUNTK
060ACZZ
GFTAR 003ACZZ
G F T A R 0 0 4 AC Z Z
LHLDZ
001ACZZ
Q C N W — 0 0 3 ACZ Z
QCNW- 0 0 4 A C Z Z
QCNW- 0 4 7 A C Z Z
Q C N W - 0 4 4 ACZ Z
X B B S C 2 6 P 0 4 0 0 0
XBBSC30P06000
XBPSD30P06KSO
XUPSD26P06000
LANGQ1004ACZZ
LANGQ1005ACZZ
PCUSG1001ACZZ
P Z E T Y 1 0 0 1 A C Z Z
QCNCM1002ACZZ
Q C N W — 1 0 0 7 ACZ Z
XBPSD30P10000
XBPSD40P08KSO
XNESD30—24000
PHQG-1002ACZZ
XN E SD3 0-2 4 0 0 0
LHLDF6648RCZZ
PCUSG1001ACZZ
PRICE
RANK
NEW
MARK
PART
RANK
AC
N
N
N
N
C
C
C
C
B
B
C
C
E
E
E
E
D
D
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
N
C
C
C
A F
AB
A
A
A
A
A
F
E
F
N
A
*
*
*
*
*
*
*
*
AD
AC
AD
AK
AM
AM
AM
A
A
A
A
N
N
N
N
N
N
N
N
N
A
A
A
A
AH
A F
A A
A E
N
N
N
N
AQ
AX
N
A A
A A
A A
AC
A A
AB
A A
D E S C R I P T I O N
Knob for V R
Fixing angle for speaker
Fixing angle for speaker
Connector
HALT switch
Variable resistor
Speaker
Screw
CPU PWB unit (Model 3541)
CPU PWB unitiModel 3530)
CPU PWB unit (Model 3540)
MFD I/F PWB unit
Cover for RS232C I/O slot
Cover for I/O slot
Guide for PWB
Connector for light pen
Connector for key board
Connector for CRT-1
Connector for CRT — 2
Screw
Screw
Screw
Screw
Connector "A" angle
Connector "B" angle
Cushion for PWB
Insulator for MFD
Connector
Connector (18pm)
Screw
Screw
Nut
Rubber cushion
Nut
Holder
Rubber cushion for PWB
!
(1-22)--
32
M2-3500
13. Connector
PARTS CODE
NO
11 O C N C P 6 0 4 1 Q C Z Z
T
QCNCP4841QCZZ
3 QCNCW1001ACZZ
4 QCNCM1 0 0 4 A C Z Z
6 QC N W- 1 0 0 7 AC Z Z
9 QCN CWO 2 0 7 HC Z Z
10 Q C N C M 1 0 0 9 A C Z H
11 Q C N C M 1 0 0 9 A C Z i
12 Q C N C M 1 0 0 9 A C Z B
13 Q C N C M 1 0 0 9 A C Z G
14 Q C N C M 1 0 0 9 A C Z E
1&1 Q C N C W 1 0 0 8 AC 0 1
17 QC NCW 1 0 0 8 AC 0 2
18 QC NW— 1 0 4 7 AC Z Z
19 QC NW— 1 0 4 4 AC Z Z
20 Q C N W - 1 0 0 4 A C Z Z
21 Q C N W - 1 0 0 3 ACZ Z
26 L H L D F 6 6 4 8 R C Z Z
PRICE
RANK
AW
AT
AZ
AQ
AX
AK
AC
AC
AA
AC
AB
AC
AF
AM
AM
AM
AK
AB
NEW
MARK
N
N
N
N
N
PART
RANK
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
D E S C R I P T I O N
Connector
Connector
Connector
Connector
Connector
Connector
Connector
Connector
Connector
Connector
Connector
Connector
Connector
Connector
Connector
Connector
Connector
Holder
for CRT -2
for CRT— 1
for key board
for light pen
18
15
20
21
MZ-3500
[41 Others
NO.
PARTS
CODE
1 RMEMR1004AC07
9
10
13
UBNDA1 0 0 8 C C Z Z
S P A K A 1 0 0 3 A C Z Z
SSAKH3002KCZZ
PRICE
RANK
BA
A A
A Z
AD
NEW
MARK
PRICE
RANK
AH
AB
A K
AZ
A A
AB
AC
AC
AC
A T
AW
A D
AD
A E
A E
AG
A Z
AK
AR
A E
AU
AU
AU
AT
AC
AC
AD
A S
A A
A A
A A
AB
AB
AB
AB
AC
AC
AB
AB
AB
A A
A A
A B
A A
AB
A B
AB
AD
AU
BN
A X
A Z
A E
A E
A E
A E
A E
A E
A H
A K
A L
AM
A K
A L
AM
AR
AP
A F
NEW
MARK
N
N
PART
RANK
D
D
D
D
DESCRIPTION
Master media
AC Cord band
Packing cushion
Plastic bag
CPU PWB
NO.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
PARTS CODE
LANGQ1004ACZZ
LHLDF6648RCZZ
QCNCW0207HCZZ
Q C N C W 1 0 0 1 AC Z Z
QCNCM1 0 0 9 A C Z B
QCNCM1009ACZE
QCNCM1009ACZG
QCNCM1009ACZH
QCNCM1009ACZi
QCNCP484 1QCZZ
QCNCP604 1QCZZ
QSOCZ6414ACZZ
QSOCZ6416ACZZ
Q S C - C Z 6 4 2 4 ACZ Z
QSOCZ6428ACZZ
QSOCZ6440ACZZ
QSW-Z1002SCZZ
QSW-Z2005SCZZ
Q SW-Z 9 6 6 0 K C Z Z
R C - K Z 1 0 1 8 CCZ Z
RCRS-1001ACZZ
RCRS-1002ACZZ
RCRS— 10 0 3 A C Z Z
RCRSP1 003CCZZ
RMPTC4333QCKB
RMPTC4682QCKB
RMPTC8333QCKB
UBATN1001ACZZ
VCCSPU1HL100D
VCCSPU1HL330J
VCCSPU1HL470J
VC E A A A 1 CW 1 0 6 Q
VC E A A A 1 CW 1 0 7M
VCEAAA1CW336M
VCEAAA1EW106M
VCEAAA1EW107M
VCEAAA1EW227M
VC E A A A 1 HW 1 0 5 M
VCEAAA HW335M
VC E A A A HW4 7 5M
VCKYPA HB681K
VCKYPA HB681K
VCKYPU HB221K
V C K Y P U 1 H B 5 6 IK
VCTYPA1NX104M
VCTYPA1NX104M
VCTYPU1EX103M
VHDDS1588L1-1
VH HM472114-1
VH HM6 1 1 6 P 3-1
VH L H 0 0 8 0 A/— 1
VH M 5 8 7 2 5 P - 1 5
VH M74LSOO/-1
VH M 7 4 L S 0 2 / - 1
VH M 7 4 L S 0 3 / - 1
VH M 7 4 L S 0 4 /— 1
VH M 7 4 L S 0 8 /— 1
VH M 7 4 L S 1 0 / - 1
VH M 7 4 L S 1 2 5-1
VH M 7 4 L S 1 3 8 - 1
VH M 7 4 L S 1 3 9 - 1
V H M 7 4 L S 1 4/ — 1
VH M 7 4 1 S 1 5 7— 1
VH M 7 4 L S 1 6 6 - 1
VH
M74LS244-1
VH
M74LS245-1
VH M 7 4 L S 2 7 3 —1
VH M 7 4 L S 3 2/— 1
N
L
N
N
N
PART
RANK
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
B
B
B
C
B
B
B
B
C
C
B
A
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
DESCRIPTION
Connector "A" angle
Holder
Connector
Connector
Connector
Connector
Connector
Connector
Connector
Connector
Connector
1C socket (14pm)
1C socket (16pm)
1C socket (24pm)
1C socket (28pm)
1C socket (40pm)
DipSW
Dip SW
DipSW
Capacitor
X-Tal (3932MHz)
X-Tal (32MHz)
X-Tal (245MHz)
X-Tal (32KHz)
Block resistor (1/8W 33KOX4)
Block resistor (1/8W 68KOX4)
Block resistor (33KQX 8 1/8W ±10%)
Battery
Capacitor (50V 10PF)
Capacitor (50WV 33PF)
Capacitor (50V 47PF)
Capacitor (16WV 10,, F)
Capacitor (16WV lOO^F)
Capacitor (16WV 33WF)
Capacitor (25WV 10j.F)
Capacitor (25WV 100,uF)
Capacitor (25WV 220,/F)
Capacitor (50WV 1 O^F)
Capacitor (50WV 33^F)
Capacitor (50WV 4 7^F)
Capacitor (50WV 680PF)
Capacitor (50WV 680PF)
Capacitor (50WV 220PF)
Capacitor (50WV 560PF)
Capacitor (12WV 0 10,, F)
Capacitor (1 2WV OlO^F)
Capacitor (25WV OOIO^F)
Diode (1S1588L1)
1C
1C
1C
1C
1C
1C
1C
1C
1C
1C
1C
1C
1C
1C
1C
1C
1C
1C
1C
1C
MZ-3500
,5! CPU PWB
NO
PARTS
CODE
69
70
71
72
VH M 7 4 L S 3 6 7 - 1
VH M 7 4 L S 3 7 3 — 1
VH M 7 4 L S 7 4/- 1
VH M 7 4 L S 7 5/— 1
74
75
76
77
78
79
80
81
82
83
84
85
86
87
V H
VH
VH
VH
VH
VH
VH
VH
VH
VH
VH
VH
VH
VH
M 7 4 L S 9 3/1
S N 7 4 0 4 N/- 1
S N 7 4 0 6 N/1
S N 7 4 1 5 7 N - 1
SN75188N-1
S N 7 5 1 8 9 A —1
S P 6 1 0 2 C 0 0 2
SP6102C003
S P 6 1 0 2 R 0 0 1
T A 7 3 1 3 A P —1
T C 4 0 4 9 P/— 1
U P 0 1 9 9 0 A C C
UPD7220D—1
UPD8255/-1
V H 276 4 / / A C
0 1
V H 2 7 6 4/ / A C 0 2
VH
276 4 //AC
03
V H 276 4 / / A C
04
VH
4 1 6 4 —1 5 0 — H
V H 8 2 5 1 A C//—
1
V H 8 2 5 3 ////—
1
V H P G L 3 P R 2//— 1
VRD-ST2EY331J
89
90
91
92
93
94 V R D — S T 2 E Y 4 7 0 J
95 V R D - R V 2 E Y O O O J
% V RD-ST 2 E Y 1 0 1 J
97 V R D - S T 2 E Y 1 0 2 J
98 V R D - S T 2 E Y 1 0 3 J
99 V R D - S T 2 E Y 1 0 4 J
100 V R D - S T 2 E Y 2 2 2 J
101 V R D - S T 2 E Y 3 3 1 J
102 V R D - S T 2 E Y 3 3 2 J
103 V R D - S T 2 E Y 3 3 3 J
104 V R D - S T 2 E Y 5 6 1 J
105 V R D — R V 2 E Y 6 8 2 J
106 V R D - S U 2 E Y 1 5 2 J
107 V R D - S U 2 E Y 4 7 0 J
108 V R D - S U 2 E Y 6 8 1 J
109 V R D - S U 2 E Y 8 2 1 J
110 V R D — S U 2 E Y 8 2 2 J
KC/-1
111 V S 2 S C 4 5 8
112 X B P S D 3 0 P 0 6 K S O
113 X B P S D 3 0 P 0 8 0 0 0
PRICE
RANK
AH
AQ
AG
A E
NEW
MARK
PART
RANK
B
B
B
B
A K
AF
B
B
B
B
AG
AM
AM
L
A P
A L
AN
AT
BS
A Y
LM
LM
LM
LM
A2
A
B
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
B
C
C
BG
BG
BP
Y
A
E
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
AD
A A
A A
D E S C R I P T I O N
1C
1C
1C
1C
1C
1C
1C
1C
1C
1C
1C
1C
1C
1C
1C
1C
1C
1C
LSI PROM-IPL
LSI PROM-CG (English)
LSI PROM-CG (Germany)
LSI PROM-CG (French)
1C
1C
1C
Photo transistor GL3PR2
Resistor (1/4W 3300 J)
Resistor (EX 110V.220V onjy) (1/4W 47O ±5%)
Resistor (1/4W ±5%)
Resistor (1/4W lOOO ±5%)
Resistor (1/4W 1KO)
Resistor (1/4W 10KO)
Resistor (1/4W 100KQ ±5%)
Resistor (Japan only) (1/4W 2 2KD ±5%)
Resistor (1/4W 330(1 J)
Resistor (1/4W 33KD ±5%)
Resistor (1/4W 33KO)
Resistor (1/4W 5600 J)
Resistor (1/4W 6 8K(1 ±5%I
Resistor (1/4W 1 5Kfl J)
Resistor (47fi)
Resistor (1/4W 680(1 J)
Resistor (1/4W 8200 ±5%)
Resistor (1/4W 8 2KO ±5%)
Transistor
Screw
Screw
[6] Power supply unit
NO
PARTS CODE
1 O A E 3 0 2 1 6 9 0 4 //
2 O A E 3 0 2 6 3 0 2 5 / /
3 O A E 3 0 2 6 3 0 2 5 / /
4 O A E 3 0 1 0 9 0 6 6 / /
5 O A E 3 0 1 0 9 0 6 6 / /
6 O A E 3 0 2 5 8 7 8 4 / /
7 O A E 3 0 2 2 1 5 1 7 / /
8 O A E 3 0 2 2 1 5 2 0 / /
9 O A E 3 0 2 6 3 0 2 5 / /
10 O A E 3 0 3 6 2 0 5 2 / /
11 O A E 3 0 2 6 3 0 2 5 / /
12 O A E 3 0 2 6 3 0 2 5 / /
13 O A E 3 0 2 6 3 0 2 5 / /
14 J D A E 3 0 1 0 9 0 6 6 / /
15 O A E 3 0 1 0 9 0 6 6 / /
16 O A E 3 0 2 7 9 8 4 4 / /
17 O A E 3 0 1 6 7 3 7 0 / /
18 O A E 3 0 2 2 1 5 4 6 / /
19 O A E 3 0 2 6 3 0 2 5 / /
20 O A E 3 0 2 6 9 4 3 0 / /
21 O A E 3 0 2 6 1 6 5 8 / /
22 O A E 3 0 1 2 1 9 4 7 / /
23 O A E 3 0 4 9 9 8 3 1 / /
24 O A E 3 0 3 6 2 0 8 1 / /
PRICE
RANK
A S
AD
A F
A E
AE
A X
A L
AH
A D
AD
AD
AD
AD
AE
A E
A H
A T
A H
A D
A Y
A D
A F
1_J\D
A D
NEW
MARK
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
PART
RANK
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
D E S C R I P T I O N
1C (UPC78M12H)
Transistor (2SC1815-Y)
Transistor (2SC1815-Y)
Transistor (2SA733-Q)
Transistor (2SA733-Q)
Transistor (2SC2750-L)
Transistor (2SA965-Y)
Transistor (2SC1 627- Y)
Transistor (2SC1815-Y)
Transistor (2SA1015-Y)
Transistor (2SC1815-Y)
Transistor (2SC1815-Y)
Transistor (2SC1815-Y)
Transistor (2SA733-Q)
Transistor (2SA733-Q)
Transistor (2SA1 020- Y)
Transistor (2SC2334-L)
Transistor (2SC2655-Y)
Transistor (2SC1815-Y)
Transistor (SI OSC4M)
Zener diode (H29L-A1)
Diode (1S234-8H)
Zener diode (HZ11L-B1)
Zener diode (HZ7L-C2)
[M001]
[Q001]
[Q002]
[Q003]
[0004]
[Q005]
[Q006]
[0007]
[Q008]
[Q009]
[Q010]
[Q011]
[Q012]
[Q013]
[Q014]
[Q015J
[Q016]
[Q017]
[Q018]
[DU001]
[D001]
[D002]
[D003]
[D004]
MZ-3500
[6j Power supply unit
NO.
25
26
27
28
29
30
31
32
33
34
35
36
37
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
PARTS CODE
OAE30121921XX
O A E 3 0 1 2 1 9 2 1 / /
OAE30379029//
OAE30121921//
O A E 3 0 1 2 1 9 2 1/ /
O A E 3 0 2 0 0 7 7 4 / /
O A E 3 0 2 0 0 7 7 4 / /
OAE30379029XX
O A E 3 0 2 5 0 3 2 6 / /
OAE30121921XX
OAE30159870 / /
OAE30121866//
O A E 3 0 1 6 5 2 6 2 / /
OAE30511353 / /
O A E 3 0 2 7 2 3 9 1/ /
O A E 3 0 5 0 9 7 2 1/ /
O A E 3 0 5 0 9 7 2 1 //
O A E 3 0 5 2 3 3 7 0 / /
O A E 3 0 1 4 3 5 7 2 / /
O A E 3 0 1 4 3 5 7 2XX
O A E 3 0 1 2 0 6 5 0 / /
OAE30169653 / /
OAE30227236 / /
OAE30120524 / /
OAE30129460 //
OAE30129460 //
OAE30129460XX
O A E 3 0 2 8 0 6 7 1XX
OAE30165576 / /
O A E 3 0 1 6 5 5 7 6XX
OAE30169653XX
OAE30169653XX
O A E 3 0 1 2 0 5 2 4 XX
O A E 3 0 1 6 4 4 0 9XX
OAE30120456XX
OAE30 29460 XX
OAE30 2 0 4 5 6 XX
OAE30 70008 XX
OAE30 7 0 0 0 8 XX
OAE30 13525 XX
OAE30 9 5 2 5 8 XX
OAE30 2 0 5 2 4XX
OAE30 2 0 5 2 4 XX
OAE30 6 4 4 0 9 XX
OAE30 16729 XX
OAE30 1672 9XX
V R S—P T 3 A B 1 0 2 J
VR S - P T 3 DB 1 5 2 K
V RD-ST 2 E Y 1 5 2 J
V RD-ST 2 E Y 3 3 3 J
V RD-ST 2 E Y 3 3 3 J
V R D—S T 2 E Y 1 5 2 J
O A E 3 0 4 9 1 1 6 9XX
VRD-ST 2 EY 1 0 0 J
VRD-ST 2 EY 1 0 2 J
O A E 3 0 5 0 8 0 4 9XX
VRD-ST2EY4R7J
O A E 3 0 5 0 1 8 6 8 XX
O A E 3 0 1 4 3 2 8 4XX
VRD-ST 2 EY 3 3 1 J
V R S - P T 3 AB 1 0 0 J
V RD-ST 2 E Y 2 7 2 J
V RD-ST 2 E Y 1 0 2 J
VRD-ST2EY391J
VRD-ST 2 EY 4 7 1 J
VRD-ST 2 EY 3 3 1 J
VRD-ST 2 E Y 1 8 2 J
VRD-ST 2 EY 1 5 2 J
VRD-ST 2 E Y 2 2 2 J
VRD-ST 2 E Y 1 0 2 J
V RD-ST 2 E Y 2 2 2 J
VRD-ST 2 E Y 6 8 1 J
VRD-ST 2 E Y 2 2 0 J
VRD— S T 2 E Y 1 0 2 J
VRD-ST 2 E Y 1 0 2 J
VRD-ST2EY331J
VRD— S T 2 E Y 3 3 1J
O A E 3 0 4 9 0 9 4 0XX
VRD— S T 2 E Y 3 9 0 J
V RD-S ' 2 E Y 1 5 1 J
PRICE NEW
RANK MARK
AC
AC
AD
AC
AC
AG
AG
AD
AG
AC
AY
AN
AH
AP
AP
AG
AG
AP
AC
AC
AG
AC
AD
AC
AC
AC
AC
A E
AG
AG
AD
AD
AC
AC
AC
AC
AC
AG
AG
AG
AG
AC
AC
AC
AK
AK
AC
AB
A
A
A
A
A
A
A
A
A
A
A
E
A
A
AG
AB
AC
AC
A A
AB
AA
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
E
A
A
PART
RANK
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
B
B
B
B
B
B
B
B
B
B
B
B
B
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
N
N
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
D E S C R I P T I O N
Diode (1S2076A-FEC)
Diode (1S2076A-FEC)
Zener diode (HZ7L- 62)
Diode (1S2076A-FECJ
Diode (1S2076A-FEC)
Diode I30DF-1)
DiodeI30DF -_1)
Zener diode (HZ7L- 32}
Diode {10DF-_1J
Diode (1S2076A-FEC)
Diode (SI OVBIQ}
Diode QB4B1)
Thyristorip3P05M)
Capacitor (0 22^,F 250V)
Capacitor (O.ljiF 125V)
Capacitor (DE1107E222M250VAC)
Capacitor (DE1107E222M250VAC)
Capacitor (KM50VRSN10000HR)
Capacitor (50F2S102K)
Capacitor (50F2S102K)
Capacitor (50F2S154K)
Capacitor (50ULB10-M)
Capacitor (10ULB220-M)
Capacitor (50F2S223K)
Capacitor (50F2S103K)
Capacitor (50F2S103K)
Capacitor (50F2S103K)
Capacitor £35ULB33-M)
Capacitor (10ULB1000-M)
Capacitor (10ULB1000-M)
Capacitor (50ULB10-M)
Capacitor (50ULB10-M)
Capacitor (50F2S223K)
Capacitor (50F2S332K)
Capacitor (50F2S472K)
Capacitor (50F2S103K)
Capacitor (50F2S472K)
Capacitor (25ULB330-M)
Capacitor (25ULB330-M)
Capacitor (35ULB220-M)
Capacitor (25ULB220-M)
Capacitor (50F2S223K)
Capacitor (50F2S223K)
Capacitor (50F2S332K)
Resistorr (TMIOK(PVB)B 2Kfl)
Resistorr (TMIOK(PVB)B 2KQ)
Resistorr (RSI FB IKOJ)
Resistorr (RS2FB 1.5KOJ)
Resistorr (CR25 1.5KOJJ
Resistorr (CR25 33KOI)
Resistorr (CR25 33KHJ)
Resistorr (CR25 1.5KHJ)
Wire resistor
Resistor (CR25 lOflJ FJ
Resistor (CR25 1KOJ)
Resistor (MDS 05N 5.6fl)
Resistor (CR37 4.7OJ)
Resistor (RS1FB 63OI)
Resistor (MR25 47DG)
Resistor (CR25 330OJ F)
Resistor {RSI FB lOflJ)
Resistor (CR25 2.7KHJ F)
Resistor (CR25 IKflJ F)
Resistor (CR25 390HJ F)
Resistor (CR25 470fU)
Resistor (CR25 330flJ F}
Resistor [CR25 1.8KOJ F)
Resistor (CR25 1.5KOJ F)
Resistor (CR25 2.2KC2J F)
Resistor (CR25 1KOI F)
Resistor (CR25 2.2KfiJ F)
Resistor (CR25 680HJ)
Resistor (CR25 22OI)
Resistor (CR25 1KOJ F)
Resistor (CR25 1KOJ)
Resistor (CR25 330nj)
Resistor (CR25 330OJ)
Wire resistor
ResistoriCR25 39DJ F)
Resistor (CR25 150OJ F)
[D005]
[D006]
[D0071
[D008J
[D'.'09j
[D010]
[D011]
[D012]
[D013]
[0014]
[RC001]
[RC002]
[TH001]
[C001 ]
[C001]
[C0021
[C003]
[C004J
[COOS]
[C006]
[C007]
[COOS]
[C009]
[C011]
[C012]
C013]
C014]
[C015]
[C016]
C017]
.0018]
C019]
[C020]
[C021 .
[C022.
[C023.
[C024.
[C025]
C026.
C027!
:C028!
C029]
[C030]
[C031]
[RV001]
[RV002]
[R001]
.R002]
R003]
[R004]
[R005]
[R006]
[R007]
[R008]
[R009]
[R010]
[R012]
[R013]
[R014]
[R015J
[R016
[R01 7
[R018
[R019]
[R020]
[R021 ]
[R022]
[R023]
[R024]
[R025]
[R026]
[R027]
[R028]
[R029]
[R030]
[R031
[R032]
[R033]
[R034]
[R035]
M2-3500
J9, MZ1K02,1K03,1K04,1K05 (Key unit)
19
19
i <,
MZ-3500
[1Q! MZ1R03 (Graphic board)
NO
PRICE
RANK
PARTS CODE
1 DUNTK1025ACZZ
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
*
A
A
A
A
A
S P A K A 1 0 1 3 A C Z Z
SPAKC1 0 7 8 A C Z Z
X B P S D 4 0 P 0 6 0 0 0
T S E L F 0 0 0 3 P A Z Z
LANGT 1 0 0 8 A C Z Z
Q SOC Z 6 4 1 6 A C Z Z
Q S O C Z 6 4 4 0 A C Z Z
RC-C Z 1 0 0 0 Q C Z Z
RC-SZ200 1HCZZ
VCEAAU1CW107M
VCEAAU1CW336M
VCEAAU1EW107M
VCKYPA1HB33 IK
VCTYPA1NX104M
VHERD5
6E5/-1
VH i M5 K 4 1 1 6 P-2
VHiM74LSOO/-l
V H i M 7 4 L S 1 5 7 —1
V H i M 7 4 L S 1 6 6 —1
V H i M 7 4 L S 2 4 4 —1
VHiM74LS273-l
VHiM74LS367-l
VHiM74LS373-l
V H i S N 7 4 0 4 //- 1
VHiUPD7220D—1
V R D—S T 2 E Y 1 0 1 J
V R D— S T 2 E Y 1 0 3 J
V R D— S T 2 E Y 3 3 1 J
V RD-ST 2 E Y 3 3 2 J
V RD-SU 2 E Y 4 7 0 J
V R S - P T 3 DB 6 8 0 K
VS2SA673-01-1
XBTSD30P04000
*
H
K
A
A
F
NEW
MARK
PART
RANK
N
N
N
N
E
C
C
C
D
C
C
C
C
C
C
C
C
C
C
B
B
B
B
B
B
B
B
B
B
B
C
C
C
C
C
C
B
C
N
AD
AG
AB
A F
A B
A B
AB
A A
AB
AC
A
A
A
A
P
E
K
L
AM
A P
A H
AQ
A
B
A
L_A
A
A
A
E
S
A
A
A
A
A
AB
AC
AA
D E S C R I P T I O N
PWB unit
Packing cushion
Packing case
Screw
Sealing label
Angle
1C socket
LSI socket
Capacitor
Capacitor
Capacitor (16V lOOj/F)
Capacitor (16V 33>iF)
Capacitor (25V 100j/F)
Capacitor (50V 330pF)
Capacitor (12V 0 Ijif^
Zener diode
LSI RAM
1C
1C
1C
1C
LC
1C
1C
1C
LSI
Resistor (1/2W lOOfi)
Resistor (1/2W 10KO)
Resistor (1/2W 330O)
Resistor (1/2W 3 3KH)
Resistor (1/2W 47fl)
Resistor (2W 68n)
Transistor (2SA673D)
Screw (30X4)
MZ1R06 (RAM board)
NO.
1
2
3
4
5
6
7
8
9
10
11
12
13
PRICE
RANK
PARTS CODE
LBNDJ0009FCZZ
SPAKA1016ACZZ
SPAKC1082ACZZ
T i N S J 1 0 0 9 A C Z Z
TiNSM1017ACZZ
QSOCZ64 16ACZZ
VCEAAA1CW476M
VCTYPA1NX104M
V H i M 7 4 L S 3 6 7 - l
V H i S N 7 4 1 5 7 /— 1
V H i 4 1 6 4 — 150-H
V RD-R V 2 E Y 1 0 1 J
DUNTK1028ACZZ
NEW
MARK
AC
A F
A H
A E
AG
AD
A B
J
AB
AH
AH
A Z
A A
* *
N
N
N
N
PART
RANK
D
D
D
D
0
C
C
C
B
B
B
C
DESCRIPTION
Clamp band
Packing cushion
Packing case
Instruction book
Instruction book
1C socket
Capacitor (16V 47^F)
Capacitor (12V 0 1//F)
1C
1C
LSI DRAM
Resistor
PWB unit
1
j
14
MZ-3500
Index
PARTS CODE
[C]
C C A B C 1 007ACZZ
[D]
DUNT-1 0 1 8 A C Z Z
DUNT-1 0 3 5 A C Z Z
D U N T K 1 0 2 5ACZZ
D U N T K 1 02 8 A C Z Z
DUNTK 1 060ACZZ
D U N T K 1 064 A C Z Z
D U N T K 1 082ACZZ
D U N T K 1 083 ACZZ
DUNTK1085ACZZ
[G]
G C A B A 1 00 1 ACZZ
G C A B A l 003ACZZ
GCABB1002ACZZ
GCABB1004ACZZ
G C O V H 1 00 1ACZZ
G F T A F 1 001ACZZ
G F T A F 1 002ACZZ
GFTAR1003ACZZ
GFTAR1004ACZZ
GFTAU1005ACZZ
GLEGG1001ACZZ
G L E G P O O 10UCZZ
GLEGP1001CCZZ
GSTN-100 1ACZZ
[H]
HBDG83004GESA
n
[J ]
JKNBM0004PAZZ
[L]
LANGK1007ACZZ
L A N G Q l 004ACZZ
//
LANGQ1005ACZZ
//
LANGS1006ACZZ
L A N G T 1 0 0 1 ACZZ
L A N G T 1 002ACZZ
LANGT1003ACZZ
LANGT1008ACZZ
LANGT1010ACZZ
LBNDJ0009FCZZ
LCHSM1008ACZZ
LHLDF6648RCZZ
II
II
LHLDW6655RCZZ
//
L H L D Z 1 00 1ACZZ
L P L T P 1 0 0 1ACZZ
LPLTP1072CCZZ
LX-BZ1001 ACZZ
LX-LZ6023RCZZ
[N]
N F A N P 1 0 0 1ACZZ
[P]
PCUSG1 00 1 ACZZ
H
H
PCUSU1003ACZZ
PHOG-1 0 0 1 A C Z Z
PHGG-1002ACZZ
PSLDM1 001ACZZ
PSLDM1003ACZZ
P S L D P 1 00 1 ACZZ
P S P A G 1 004ACZZ
P S P A X 1 00 1ACZZ
P Z E T Y 1 00 1ACZZ
//
NO.
1- 1
PRICE NEW PART
RANK MARK RANK
AY
0
CODE
QCNCMl 0 0 9 A C Z E
QCNCMl 0 0 9 A C Z G
//
**
**
**
**
**
**
**
**
11101122229-
17
17
1
13
11
9
9
9
8
if *
91911112219199-
16
9
3
18
19
2
35
12
13
10
18
26
19
17
AS
BM
AR
BG
AM
AE
AE
AD
AC
AL
AA
AB
AB
AE
19-
3
1
22252829911011112351129911-
N
N
E
E
E
QCNCMl 0 0 9 A C Z H
//
//
QCNCM1009ACZ i
N
E
E
E
E
E
it
QCNCMl 0 0 9 A C Z J
QCNCP484 1QCZZ
//
QCNCP604 1QCZZ
it
N
N
N
N
N
N
QCNCW0207HCZZ
N
D
D
D
D
D
D
D
D
D
D
C
C
C
D
AE
AE
N
D
D
QCNW-1007ACZZ
1
AC
N
C
//
//
3
24
1
25
1
2
10
15
20
6
21
1
22
34
26
2
36
40
15
5
4
29
23
AB
AH
AH
AF
AF
AF
AG
AC
AX
AF
AE
AC
AY
AB
AB
AB
AB
AB
AD
AC
AD
AC
AA
N
N
N
N
N
N
C
C
C
C
C
C
C
C
C
C
C
D
C
C
C
C
C
C
C
D
D
C
C
1- 24
BM
N
B
2289129191928-
26
35
2
100
34
32
11
41
23
11
7
27
3
AA
AA
AA
AA
AC
AC
AN
AP
AB
AC
AB
AE
AE
N
N
N
C
C
C
C
C
C
C
C
C
C
C
C
C
2- 28
8- 4
3- 4
8- 5
3- 12
5- 5
3- 14
AQ
AQ
AQ
AQ
AA
AA
AB
N
N
N
N
//
QCNCW1 00 1 A C Z Z
ii
QCNCW1 0 0 6 A C Z Z
QCNCW1 0 0 7 A C Z Z
QCNCW1 0 0 8 A C O 1
//
QCNCW1 0 0 8 A C O 2
ii
QCNW-1 0 0 1 A C Z Z
QCNW-1002ACZZ
QCNW-1 0 0 3 A C Z Z
//
QCNW-1004ACZZ
II
QCNW-1 0 4 4 A C Z Z
N
N
N
N
//
QCNW-1 04 7 A C Z Z
//
QLUGL0006UCZZ
QP I N - 2 0 0 5 S C Z Z
QPWBF 1 0 0 5 A C Z Z
QSOCZ64 14ACZZ
QSOCZ64 16ACZZ
;/
//
QSOCZ6424ACZZ
QSOCZ6428ACZZ
QSOCZ6440ACZZ
//
//
//
QSW-K 1 0 02 A C Z Z
QSW-K 1 0 0 3 A C Z Z
QSW-K1 0 0 4 A C Z Z
QSW-K 1 0 0 5 A C Z Z
QSW-K 1 0 0 7 A C Z Z
QSW-S1006ACZZ
QSW-Z1002SCZZ
QSW-Z2005SCZZ
QSW-Z9660KCZZ
PRICE NEW
RANK MARK
NO.
AB
AC
AC
AC
5F* A C
9- 101
AC
3- 11
AC
59
AC
9- 102
AC
AT
32
AT
5- 10
AW
31
AW
5- 11
AK
39
AK
53
AZ
33
AZ
54
AD
9- 103
9- 104
AE
16
AC
3- 16
AC
AF
24
AF
3- 17
BB
9- 13
9- 14
AP
AK
2- 16
AK
3- 21
AM
2- 17
AM
3- 20
AX
2- 29
AX
36
AX
86
AM
2- 19
AM
3- 19
AM
2- 18
AM
3- 18
AB
IT 37
AA
87
AA
17
AD
5- 12
AD
5- 13
107
AD
AD
116
5- 14
AE
5- 15
AE
5- 16
AG
AG
88
AG
9- 105
108
AG
BU
9- 43
BU
9- 43
BU
9- 43
BU
9- 43
AE
25
AF
99
AZ
5- 17
AK
5- 18
AR
5- 19
5353-
PART
RANK
C
C
C
C
6
13
7
10
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
B
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
E
E
E
E
B
B
B
B
B
[R]
N
N
N
N
[Q]
Q C N C M l 0 0 2 ACZZ
//
Q C N C M l 0 04 A C Z Z
//
QCNCMl 009ACZB
//
QCNCMl009ACZE
PARTS
C
C
C
C
C
C
C
RC-CZ 1 O O O Q C Z Z
u
H
RC-KZ1 0 1 8 C C Z Z
R C - S Z 2 0 0 1HCZZ
R C R S - 1 00 1A C Z Z
RCRS-1 0 0 2 A C Z Z
RCRS-1 0 0 3 A C Z Z
RCRS-1 0 0 4 A C Z Z
RCRSP1003CCZZ
RMEMR 1 0 0 2 A C Z Z
R M E M R 1 0 04 ACO 7
RMPTC4 3 3 1QCKB
RMPTC4 3 3 3QCKB
RMPTC468 2QCKB
RMPTC8333QCKB
RMPTC8333QCK J
RVR-A54 52QCZZ
RVR-MC3 2 1QCZZ
89
9- 106
109
5- 20
10- 10
5- 21
5- 22
5- 23
9- 107
5- 24
1- 25
41
8- 10
5- 25
5- 26
5- 27
9- 108
26
8- 11
AB
AB
AB
AE
AF
AU
AU
AU
AG
AT
* *
B A
N
N
N
N
AB
AC
AC
AD
AD
A F
AH
C
C
C
C
C
B
B
B
B
B
E
D
B
C
C
B
C
B
C
IS]
SPAKA 10 0 3ACZZ
4-
10
A Z
N
D
MZ-3500
NO
PARTS CODE
S P A K A 0 04 A C Z Z
9- 109
S P A K A 0 09 A C Z Z
9- 110
S P A K A 0 1 3 ACZZ
10 2
S P A K A 0 1 6 A C Z Z 1 11- 2
SPAKA 045ACZZ
9- 111
S P A K A 1 27 A C Z Z
9 112
9 113
SPAKC 0 33ACZZ
9- 113
SPAKC1035ACZZ
9- 113
S P A K C 1 03 7ACZZ
S P A K C 1 0 3 9ACZZ
9- 113
10- 3
S P A K C 1 07 8 A C Z Z
11- 3
SPAKC1 082ACZZ
9- 114
S P A K F 1 1 0 4 ACZZ
SSAKH3002KCZZ
4- 13
IT]
T i N S J 1009ACZZ
11- 4
T iN S M 1 0 1 7ACZZ
11
5
T L A B J 1 769CCZZ
9- 115
TLABZ1002ACZZ
9- 2
T L A B Z 1 003 A C Z Z
1- 4
TLABZ1008ACZZ
1- 5
T L A B Z 1 0 1 7ACZZ
1- 12
T L A B Z 1400CCZZ
1- 41
TSELF0003PAZZ
10- 5
TSPC-1010ACZZ
9- 20
9- 20
TSPC-1 0 1 1 A C Z Z
TSPC-1 0 1 2 A C Z Z
9- 20
TSPC-1 0 1 3 A C Z Z
9- 20
tin
U B A T N l 001ACZZ
5- 28
4- 9
U B N D A 1 008CCZZ
[V]
V C C C P U 1 H H 2 0 1J
VCCCPU1HH680 J
VCCSPU1HL1 ODD
//
V C C S P U 1 H L 3 3 0J
//
V C C S P U 1 H L 4 7 0J
//
H
VCEAAA1CW106Q
V C E A A A 1 C W 1 07M
II
VCEAAA1CW336M
VCEAAA1CW476M
VCEAAA1EW106M
V C E A A A 1 E W 1 07M
VCEAAA1EW227M
V C E A A A 1 H W 1 0 5M
V C E A A A 1 H W 2 25M
VCEAAA1HW335M
VCEAAA1HW475M
V C E A A U 1 C W 1 07M
VCEAAU1CW336M
//
VCEAAU1CW475M
V C E A A U 1 E W 1 07M
V C K Y P A 1 H B 3 3 IK
V C K Y P A 1 H B 6 8 IK
H
VCKYPU1HB1 02K
//
V C K Y P U 1 H B 2 2 IK
VCKYPU1HB56 1K
V C S A T U 1 VE 1 04M
V C T Y P A 1 N X 1 04M
V C T Y P U 1 EX 1 0 3M
//
//
V H D D S 1 5 8 8 11-1
//
//
V H E R D 5 6E5/-1
VH i DB 7 4 9 H A C O 5
1
1
PRICE NEW PART
RANK MARK RANK
D
AG
AB
D
AH
N
C
N
AF
D
AP
N
D
AD
N
D
AP
N
D
AP
N
D
AP
N
D
AP
N
D
AK
N
C
AH
N
D
AD
D
AD
D
PARTS CODE
VH i H M 4 7 2 1 1 4 - 1
55-
49
50
510-
51
17
5510-
52
53
18
585558585855558108851088510585810858510115105-
54
25
55
56
57
26
58
27
59
28
60
61
62
63
29
19
30
31
64
20
32
33
65
21
66
34
67
35
22
36
68
37
69
23
9
70
24
71
//
8VH i M 7 4 L S 7 5 / — 1
5VH I M 7 4 L S 8 6 / — 1
55VH.M74LS93/-1
VH . M 7 4 3 8 / / / - 1 _^ 88VH .NE555///-1
VH i S N 7 4 04//-1
10VH i S N 7 4 04N/-1
5//
8VH i S N 7 4 0 6 N / - 1
5V H I S N 7 4 1 4 N/— 1
8VH i S N 7 4 1 57/-1
11VH i S N 7 4 1 5 7 N - 1
5VH I S N 7 5 188N-1
5VH I S N 7 5 1 8 9 A - 1
5VHi SP61 02C002
5VH i S P 6 1 0 2 C 0 0 3
5VH i SP6 1 0 2 R O O 1
5VH i T A 7 3 13AP-1
5VH I T C 4 0 4 9 P / - 1
5//
9V H i T C 4 5 14P/-1
9VH i T L 4 5 5 8 / / - 1
8VHiUPDl 990ACC
5VH.UPD7220D-1
5//
108VH i U P D 7 6 5//-1
VH i U P D 8 2 5 5 / - 1
5VH i 2 7 6 4 / / A C 0 1
5VH i 2 7 6 4 / / A C 0 2
5n
9VH i 27 6 4 / / A C 0 3
5;/
9VH i 2 7 6 4 / / A C 0 4
5//
9-
38
72
73
74
39
40
25
75
41
76
42
10
77
78
79
80
81
82
83
84
122
123
VH i HM6 1 1 6 P 3 - 1
VHi L H 0 0 8 0 A/- 1
VH I M 5 K 4 1 1 6 P - 2
VH i M 5 8 7 2 5 P - 1 5
V H i M 7 4 L S O 0/-1
//
VHiM74LSO
2/-1
//
VH iM7 4 L S 0 3 / - 1
V HI M 7 4 L S 0 4 / - 1
VH . M 7 4 L S 0 8 / - 1
//
VH I M 7 4 L S 1
0/-1
//
AE
AG
AA
AA
AB
A A
AC
AA
AA
AC
AC
AC
AC
AS
AA
8- 12 A B
8- 13 A B
5- 29 A A
9- 116 A A
5- 30 A A
8- 14 A A
5- 31 A A
8- 15 A A
9- 117 A A
5- 32 A B
5- 33 A B
8- 16 A B
5- 34 A B
11- 7 A B
5- 35 A B
5- 36 A C
5- 37 A C
5- 38 A B
8- 17 A B
5- 39 A B
5- 40 A B
10- 11 A B
9- 118 A B
10- 12 A B
9- 119 A B
10- 13 A B
10- 14 A A
5- 41 A A
5- 42 A A
8- 18 A A
8- 19 A A
5- 43 A B
5- 44 A A
8- 20 A C
5- 45 A B
5- 46 A B
8- 21 A B
8- 22 A B
10- 15 A B
11
8 AB
5- 47 A B
8- 23 A B
9- 120I AB
5- 48 I A D
8 24 A B
9 121 . A D
10 16 A C
9 125 B R
N
N
N
N
N
N
N
N
N
N
D
D
D
D
D
D
C
C
D
D
D
D
D
VH I M 7 4 L S 125-1
VH I M 7 4 L S 1 2 6 - 1
VH I M 7 4 L S 1 3 8 - 1
VH I M 7 4 L S 1 3 9 - 1
V H I M 7 4 L S 1 4/-1
V H i M 7 4 L S l 57-1
//
//
VHiM74LS161-l
V H i M 7 4 L S l 63-1
VH I M 7 4 L S 1 66-1
//
VH . M 7 4 L S 2 1 / - 1
VH I M 7 4 L S 2 2 1 - 1
VHiM74LS244-l
A
D
//
VH I M 7 4 L S 2 4 5 - 1
VHiM74LS27/-l
VH iM74L S 2 7 3 - 1
C
C
C
C
C
C
C
C
C
//
//
VH I M 7 4 L S 2 9 3 - 1
VH I M 7 4 L S 3 2 / - 1
//
VHiM74LS367-l
//
//
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
VH I M 7 4 L S 3 7 3 - 1
II
VHiM74LS74/-l
C
N
C
C
C
C
C
C
C
C
C
C
C
C
C
B
B
B
B
B
Ih-
PRICE NEW
RANK MARK
NO
43
85
86
26
44
87
88
88
124
88
124
88
124
PART
RANK
AU
BN
AX
AP
AZ
AE
AE
AE
AE
AE
AE
AE
AE
AE
AE
AH
AH
AK
AL
AM
AK
AK
AK
AH
AH
AL
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
A L
AD
AH
AM
AM
AR
AF
AP
AP
AP
AG
AF
AF
AH
AH
AH
AQ
AQ
AG
AG
AE
AF
AK
AE
AG
A E
AF
AF
AG
AM
AH
AM
AM
AP
BG
BG
BP
AL
AN
AN
AW
A F
AT
BS
BS
BR
AY
LM
LM
BM
LM
BM
LM
BM
N
N
N
I
B
MZ-3500
PARTS
CODE
VH i 4 1 6 4 - 1 5 0 - H
//
VH i 825 1 AC//-1
VH i 8253////-1
VHPGL3PR2//-1
VHPGL9PR2//-1
//
VRO-RV2EYOO 0J
VRD-RV2EY 1 0 1J
VRD-RV2EY682 J
V R O - S T 2 E Y 100 J
H
VRD-ST2EY 1 0 1J
//
//
//
V R D - S T 2 E Y 1 02 J
//
//
//
//
//
V R D - S T 2 E Y 1 03 J
//
//
V R O - S T 2 E Y 1 04 J
//
V R O - S T 2 E Y 1 51 J
VRD-ST2EY152 J
//
II
V R D - S T 2 E Y 1 82 J
VRD-ST2EY220 J
//
VRD-ST2EY222 J
//
ii
H
V R O - S T 2 E Y 2 72 J
V R D - S T 2 E Y 3 3 1J
//
//
//
//
//
//
//
//
VRD— S T 2 E Y 3 3 2 J
H
ii
ti
VRD-ST2EY333 J
//
//
//
VRD-ST2EY390J
//
VRD-ST2EY391 J
VRD-ST2EY392 J
VRD-ST2EY4R7 j
V R D - S T 2 E Y 4 70 J
V R D - S T 2 E Y 4 7 1J
n
VRD-ST2EY472J
//
V R D - S T 2 E Y 5 6 1J
V R D - S T 2 E Y 6 8 1J
ii
II
H
V R D - S U 2 E Y 10 1J
V R D - S U 2 E Y 1 52 J
VRD-SU2EY39 1j
VRD-SU2EY470 J
//
V R D - S U 2 E Y 6 8 1J
VRD-SU2EY8 2 1J
VRD-SU2EY8 2 2 J
//
NO
5- 89
11- 11
5- 90
5- 91
5- 92
1- 8
9- 6
5- 95
11- 12
5- 105
6- 77
6- 105
5- %
8- 45
9- 126
10- 27
5- 97
6- 78
6- 86
6- 93
6- 97
6- 98
5- 98
9- 127
10- 28
5- 99
9- 128
6- 103
6- 72
6- 75
6- 91
6- 90
6- %
6- 114
5- 100
6- 92
6- 94
9- 129
6- 85
5- 93
5- 101
6- 83
6- 89
6- 99
6- 100
6- 106
8- 46
10- 29
5- 102
8- 47
9- 130
10- 30
5- 103
6- 73
6- 74
9- 131
6- 102
6- 113
6- 87
6- 115
6- 80
5- 94
6- 88
9- 132
6- 107
8- 48
5- 104
6- 95
6- 109
6- 110
9- 133
8- 49
5- 106
8- 50
5- 107
10- 31
5- 108
5- 109
5- 110
8- 51
PRICE NEW
RANK MARK
AZ
A2
AY
BA
ft
AC
A C '
A A
A A
A A
AA
A A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
AA
AA
A A
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
AA
A A
N
AA
AA
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
N
N
N
N
N
N
N
AB
N
N
N
N
N
A A
A A
N
AA
AA
AA
AA
A A
A A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
N
N
N
N
PART
RANK
PARTS CODE
B
B
B
B
B
B
B
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
V R D - S U 2 E Y8 24 J
V R N - R T 2 EK 1 0 2 F
V R N - R T 2 E K 1 05F
V R N - R T 2 EK 1 2 3F
VRN-RT 2 EK2 2 2F
V R N - R T 2 E K 4 7 2F
V R N - R T 2 E K 9 1 2F
V R S - P T 3 A B 1 00 J
//
V R S - P T 3 A B 1 02 J
V R S - P T 3 D B 1 02 J
VRS-PT3DB1 52K
VRS-PT3DB680K
VRS-PT3LB330 J
VSP0080P-608N
VS2SA673-C/-1
VS2SA673-D1-1
VS2SC4 58KC/-1
[X]
XBBSC26P04000
XBBSC30P06000
XBPSD30P06KSO
//
//
XBPSD3 OPO 6 K O O
//
XBPSD30P08KSO
XBPSD30P08000
XBPSD30P1 0000
II
XBPSD30P30KSO
XBPSD40P06KSO
XBPSD40P06KOO
XBPSD40P06000
XBPSD4 O P 0 8 K S O
XBPSF3 O P 0 6 K O O
XBTSC4 OP06000
XBTSD30P04000
XBTSF40P08000
XCPSD40P12000
XNESD30-24000
n
II
XUPSC26P06000
XUPSC30P08000
XUPSD26P06000
[0 1
O A E 1 0447 1 OO//
O A E 1 0 4 4 7 1 13//
O A E 1 0 4 8 0 3 87//
O A E 1 0 5 0 0 6 23//
O A E 1 0 5 0 4 9 1 7//
O A E 1 0504933//
O A E 1 0507778//
OAE1050778 I//
OAE 105 1 84 8 2//
O A E 10526940//
O A E 1 052 798 I//
OAE 1 053 1087//
OAE 1 0538909//
OAE 1 05389 1 2//
O A E 1 0 5 4 3 4 8 6//
O A E 2 0 4 9 0 4 4 5//
O A E 2 0 5 10574//
O A E 2 0 5 1 2336/X
O A E 2 0 5 2 1 194//
OAE20527978//
OAE22830579//
OAE 2 2 83 1688//
OAE 2 3 594 924//
O A E 3 0 1 0 9 0 6 6//
n
II
n
OAE 30 1 1 67 29//
u
O A E 3 0 1 2 0 4 56//
//
OAE 30 1 20524//
//
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
[_
1
c
17
NO
B68
86886666610128105-
52
111
53
54
112
55
56
84
108
70
104
71
32
39
7
57
33
111
22259291528111-
20
21
22
112
12
8
134
27
113
30
58
38
28
30
102111011228992-
4
30
16
31
34
32
33
31
33
59
21
22
23
PRICE NEW PART
RANK MARK ANK
AA
C
AB
N
C
AA
C
AB
C
AB
N
C
AB
C
AC
C
AB
N
C
AB
N
C
AC
N
C
AB
N
C
AB
N
C
AB
C
AC
C
AN
C
B
AE
B
AC
AD
B
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
6- 125 A F
6- 126 A D
6- 127 A F
6- 129 A M
6- 138 A R
6- 139 AW
6- 130 BQ
6- 131 AQ
6- 128 A V
6- 133 BM
6- 132 A X
6- 140 A Q
6- 147 AW
6- 148 AW
6- 134 A Y
6- 142 A C
6- 137 AC
6- 145 A M
6- 141 A A
6- 144 A G
6- 136 A C
6- 143 A R
6- 146 A C
6- 4 A E
6- 5 A E
6- 14 A E
6- 15 A E
6- 68 A K
6- 69 A K
6- 58 A C
6- 60 AC
6- 47 A C
6- 56 A C
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
c
c
c
c
c
c
c
c
c
c
c
c
c
c
c
c
c
c
c
c
c
c
c
c
c
c
c
c
c
c
c
c
c
B
B
B
B
C
C
c
c
c
c
MZ-3500
PARTS CODE
O A E 3 0 1 20524//
//
O A E 3 0 1 206 5 O//
O A E 3 0 1 2 1 8 6 6//
OAE30121921//
//
//
//
//
O A E 3 0 1 2 1 9 4 7//
O A E 3 0 1 29460//
//
//
//
O A E 3 0 143284//
O A E 3 0 1 4 3 5 7 2//
//
O A E 3 0 1 59870//
O A E 3 0 164409//
//
O A E 3 0 1 6526 2//
O A E 3 0 1 6 5 5 7 6//
//
O A E 3 0 1 67370//
O A E 3 0 1 69653/7
//
;/
O A E 3 0 1 7 0008//
//
O A E 3 0 1 95258/7
OAE30200774//
//
O A E 3 0 2 13525//
O A E 3 0 2 1 69 0 4//
O A E 3 0 2 2 1 5 1 7//
OAE30221520//
O A E 3 02 2 1 546//
OAE30227236//
OAE30250326//
OAE30258784//
O A E 3 0 2 6 1 658//
O A E 3 0 2 6 3 0 2 5//
//
//
//
//
//
//
O A E 3 0 2 6 9 4 3 O//
OAE30272391//
OAE30279844//
O A E 3 0 2 8 0 6 7 I//
OAE30362052//
OAE30362081//
OAE30379029//
//
OAE30490940//
O A E 3 049 1 1 69//
O A E 3 0 4 9 9 8 3 I//
OAE30500979//
OAE30500982//
O A E 3 0 5 0 1868//
O A E 3 0 5 0 8 0 4 9//
OAE30508528//
O A E 3 0 5 0 8 5 3 I//
OAE30508557//
O A E 3 0 5 0 8 5 6 O//
//
OAE30509721//
//
OAE30509941//
O A E 3 0 5 1 1 3 53//
O A E 3 0 5 1 54 6 9//
O A E 3 0 5 2 3 3 7 O//
O A E 3 0 5 6 4 740//
OAE30566353//
O O P A 7 K F 0 9 5C//
O O P A 7 K F 1 0 2B//
0 O P A 7 K F 1 03B//
O O P A 7 K F 1 0 4 B//
NO
6666666666666666666666666666666666666666666666666666666666666666666666666666
9999
65
66
44
36
25
26
28
29
34
22
48
49
50
59
82
42
43
35
57
67
37
52
53
17
45
54
55
61
62
64
30
31
63
1
7
8
18
46
33
6
21
2
3
9
11
12
13
19
20
38
16
51
10
24
27
32
101
76
23
116
117
81
79
118
118
120
121
123
39
40
116
38
119
41
124
122
51
51
51
51
PRICE NEW PART
RANK MARK RANK
N
AC
C
N
AC
C
N
AG
C
AN
N
B
N
AC
B
N
AC
B
N
AC
B
N
B
AC
N
AC
B
AF
N
B
N
AC
C
N
AC
C
N
AC
C
N
AC
C
N
AC
C
N
AC
C
N
AC
C
AY
N
B
N
AC
C
N
AC
C
AH
N
B
N
AG
C
N
AG
C
AT
N
B
N
AC
C
N
AD
C
AD
N
C
N
AG
C
N
AG
C
N
AG
C
N
AG
B
N
AG
B
N
AG
C
N
AS
B
AL
N
B
AH
N
B
AH
N
B
AD
N
C
AG
N
B
AX
N
B
AD
N
B
N
AD
B
N
AF
B
AD
N
B
AD
N
B
N
AD
B
N
AD
B
AD
N
B
AY
N
B
AP
N
C
AH
N
B
AE
N
C
AD
N
B
N
AD
B
N
AD
B
N
AD
B
AE
N
AE
C
AD
N
B
AH
N
A
AW
N
B
N
AC
C
N
AG
C
BP
N
B
BY
N
B
N
AX
C
N
AL
C
AX
N
C
N
AG
C
N
AG
C
AG
N
A
AP
N
C
AR
N
B
AP
N
C
AP
N
C
AX
N
C
BX
N
C
BX
N
C
BX
N
C
BX
N
C
PARTS CODE
O O P A 8 K F 1 1 5 A//
OOPCH52203 A//
OOPKCC 1 0 9 0 1-Z
OOPKFL10901-Z
O O P K F L 1 190 1-Z
OOP08KF018 B//
OOP16KF005 A//
0 0 P 1 9 K F 0 0 5 A//
0 0 P 1 9 K F 0 0 7 A//
OOP21KF008 A//
OOP21KF009 A//
0 0 P 2 1 K F 0 1 3 A//
0 0 P 2 1 K F 0 1 4 A//
OOP23KF001 A//
OOP23KF011 B//
OOP23KF014 A//
OOP25KF006 B//
OOP25KF007 A//
OOP25KF008 A//
0 0 P 2 7 K F 0 2 1 A//
OOP29KF006 B//
O O P 2 9 K F 0 0 7 B//
OOP80D9E43000
OOP85Y2K56000
OOP85Y2K60000
- 18-
PRICE NEW PART
RANK MARK RANK
AT
N
9- 50
C
N
9- 39
AC
C
N
B
9- 27
AG
N
B
9- 25
AG
AH
N
9- 26
B
AN
N
9- 28
C
N
9- 37
AC
C
N
9- 35
AC
C
N
9- 36
AC
C
N
9- 31 A D
C
AF
N
9- 33
C
AD
N
9- 32
C
N
9- 34
AC
C
N
9- 46
AC
C
N
AL
9- 29
C
9- 47
N
AC
C
AM
N
9- 30
C
N
9- 48
AC
C
N
9- 49
AC
C
N
B
9- 38
AC
AK
N
9- 44
C
AH
N
9- 45
C
N
9- 42
AQ
C
9- 40
AH
N
C
9- 41 A H
N
C
NO
SHARP CORPORATION
Industrial Instruments Group
Reliability & Quality Control Department
Yamatokoriyama, Nara 639-11, Japan
1983 January Printed in Japan s
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