Sharp Mz 3500 Users Manual

MZ-3500 to the manual 30945b32-ab8c-422f-a17d-e85d340b9cd3

2015-01-23

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MZ-3500
SERVICE
MANUAL
CODE:
OOZMZ
3500SM/E
PERSONAL COMPUTER
MODEL
Z-350
CONTENTS
1.
Specifications
1
2.
Software (Memory) Configuration
7
3. CPU and
memory
12
4. CRT
display
25
5. MFD
interface
52
6.
R232C interface
72
7.
Printer interface
yg
8.
Other interface
81
9.
Power
circuit
description
gy
10.
Keyboard controller
circuit
discription
90
11.
Self check functions
94
12. IPL
flow
chart
103
13.
Circuit diagram
&
P.W.B
Parts
list
&
Guide
SHARP
CORPORATION
M
7
3500
1.
SPECIFICATIONS
1-1.
Specification
of the
main
unit (Model
35XX)
Outline
1)
High
speed
processing
using multi-CPL'
2)
Built
in
mini
floppy disk
3)
Built
in
printer interface
and
RS232C
Aerial
interface
4)
Connection
of up to two
video displa,
mitt
(separate
graphic
display
or
overlaid display
possible
on two
individual
color
monitor
units)
5)
Permits
the use of
standard CP/M
Model 3530
incluse
a
single
double-side, double
density
mini
floppy
disk
and 64 KB
RAM.
Model MZ3540
has two
double-side,
density
mini
floppy
disks
and
64 KB
RAM.
LSI
DISPLAY
MFD
Other
I/F
Other
functions
Software
Accessories
CPU
MEMORY
I/O
MZ353X
MZ354X
Light
pen
Keyboard
Printer
RS232C
Multi-CPU
processing
ROM
RAM
Custom
LSI
GDC
FDC
PIO
SIO
TIMER
CLOCK
Screen
structure
Elements
Attribute
Colors
I/F
One
double-side,
double
density
floppy
disk
Two
double-side,
double
density
floppy
disks
IPL
C, G
For
main
CPU
For
sub-CPU
Shared
RAM
VIDEO
RAM
Memory mapper
Screen
controller
CRT
controller
Floppy disk controller
Parallel
I/O
port
Serial
I/O
port
Counter
Clock
Model
3531 includes
a
single
double
side,
double
density
mini
floppy
disk
and 128 KB
Model 3541
has two
double
side,
double
density
mini
floppy
disks,
and 128 KB
Z80A
microprocessor
x 2
8K
Byte
ROM
8K
Byte
ROM
64K Bit
DRAM
x 16
chips
or 8
chips
16K Bit
SRAM
x 4
chips
16K Bit
SRAM
x 1
chip
16K B't
SRAM
x 1
chip
4K Bit
SRAM
x 2
chips
TH
SP6102R001
CSP-1
SP6102C002
CSP
2
SP6102C003
MPD7220
pPD765
8255
8251
8253
/iPD1990AC
80
characters
x 25
lines.
80 x 20, 40 x 25. or 40 x 20
8 x
16,8x8
Reverse,
blink,
line
(horizontal, vertical)
8
colors
on
each character
and
background color
2
channels (applicable
CRT 640 x
400,
640 x
200,
B/W or
color)
256
bytes/sector,
16
sectors/track,
80
tracks/disk
Built-in
interface
for
optional
MFD
Dedicated keyboard
Centronics interface
No
protocol,
asynchronus
mode,
110 to
9600
bps, half-duplex
Speaker
(500mW) Battery backup clock HALT
SW
Speaker
volume control
FDOS
CP/M
BASIC
Utilities
Basic
CP/M
Expanded CP/M
High
class
compatible
with
PC3200 BASIC, supplemented
and
graphic
control commands
Expanded
RS232C, GPIB,
and
GPIO
BACKUP,
INIT,
COPY, DEBUG,
KILLALL
Intstruction
Manual
master
floppy
disk
power
cord
MZ3500
1-2. MZ-1K01 (Keyboard)
specification
Outline
Specification
MZ1K02 U.S. keyboard
(ASCII)
MZ1K03: U.K. keyboard (ISO).
MZ1K04
German
keyboard
MZ1K05:
French keyboard
LSI,
1C
Keys
(98)
Interfacing
cables
Other
Cabinet
Keyboard
controller
CMOSIC
Sculpture
key
Alphanumeric
keys
Mode switch
61
1
80C49
or
8749
4049x2,4514
Mechanical contact key,
with
life
of
10,000,000
operations.
Ten key
15
Function
keys
6
Definable
keys
10
For
data transfer
with
the CPU
(serial)
and
power
supply
(transmission under
15,000
baud)
Use
of
coiled
cable
with
8-pin
DIN
plug
Repeat
function
Indicators
(4
LED's)
Molded
Size
(W x H
Automatic
repeat occurs 0.64 seconds after
....
. 2
Two-key rollover
continuous
depression
of the
same key.
POWER,
Alphanumeric
keys
Color
xU
Office gray
467
x 35 x 190
Weight
|
About
1
.5kg
(3.3
Ib)
Keyboard
layout
Refer
to the
page
TIN
"CIRCUIT
DIAGRAM"
1-3. MZ-1U02
Outline
Specifications
Expansion
unit
for the
MZ-3500
series
CPU, which
can be
attached
to the
rear side
of the
main
unit.
Optional
boards
are
plugged
in to the
expansion
box.
The
expansion
box
will
accomodate
up to
four
option
boards.
Number
of
slots:
4
slots
Slot
connector.
60-pin
edge
connector
x 4
Area
of the
slot
inserting
option
board:
140.5
x 140
Slot
for
option
and
slot
number
MZ-1R06
(expansion RAM)
SFDI/F
Expansion RS232C
GPIO
GPIB
(IEEE
I/F)
Slot
1
o
o
o
o
Slot2
o
o
o
0
Slot
3
O
O
o
o
Slot
4
O
0
o
o
-2-
MZ3500
Expansion
unit
Screw
(1)
1-4. MZ-IR03
Outline
Specifications
Optional board
used
graphic display
functions
with
the
Model-3500
series
CPU.
It
includes 32KB
of
RAM.
It is
inserted
through
the
slot
on the
front
panel
of the PU.
The
MZ-1U02
expansion
box is not
required.
LSI
Graphic
functions
(Color
must
be
specified
for
each
dot. when
the
color
video
unit
is in
use)
Software
GDC
Graphic
controller
Basic
(buit-in)
vinrn
HAM
Expansion
(optional)
~~~~~
—
____WDEO
RAM
640 x 200
green
monitor
640 x 200
color
monitor
640
x 400
green
monitor
640 x 400
color
monitor
BASIC
graphic
control
statements
MPD7220
16KDRAM
x 16
(32KB)
16KORAM
x 32
(64KB)
32KB
(basic)
640 x 200
dots
Two
screens
_____
640 x 400
dots
One
screen
^______-
— ~"
SDISP
ODISP
CHANGE DISP
GCOLOR
CLS
PSET
PRESET
LINE
GTABLE
CIRCLE
PAINT
GINPUT
GDISP
GPRINT
GREAD
CENTER
GCURSOR
GSCROL
SYMBOL
SCALE
96KB
(maximum
expansion)
640 x 200
dots
Six
screens
640 x 200
dots
Two
screens
640 x 400
dots
Three
screens
640 x 400
dots
One
screen
Screen
designation
for two
video units.
Designation
of
output
screen.
Mode designation
Graphic
pattern
designation
Cleared
by the
color specified.
Dot set
Dot
reset
Line
creation
Table creation
Circle creation
Paint over
Input
of
graphic pattern
Display
of
graphic pattern
Output
of
graphic pattern
on
printer
Read
of
coordinates
Input
of
pattern
within
the
specified
area
Graphic
cursor position
designation
Graphic
screen
scrolling
Graphic
symbol displaying
Scren
scle-down
designation
-3-
MZ3500
1-6.
MZ-1R06
Outline
Specifications
Optional board
for
memory expantion
of the
MZ-3500
sries
CPU. with this option
the
main memory (RAM)
can be
expanded
up to a
maximum
of 256 KB.
This
option
plug
into
the
expantion
box in
slot
1 or 3.
LSI
Memory
and
user
area
Basic
Expansion
64KDRAM
x8
(64KBI
64KDRAM
x8
(128KB)
Total capacity
of
the
main
CPU RAM
BASIC
(RAM
BASE
SYSTEM
:
AREA
USER
'
AREA
Main
CPU
only
128 KB
• 57 KB
80 KB
Use
of
MZ-1R06
192 KB
«-
128 KB
Using
eight
64K
RAM's
on
theMZ-1R06
256KB
*-
208 KB
-
4
-
MZ3500
1-7.
MZ-1D07
Outline
Specifications
High
resolution
MZ
3500
series
12
green
Video
tube
Display
capacity
Display
size
Input
signals
Power
supply
Cabinet
Adjusting knobs
Accessories
Type
monitor
Non
glare
green
Size
12",
90"
deflection
Fluorescent
color
P39
(green,
long
PERSISTANCE)
Total
number
of
display
characters
2,000
characters
(80
characters
x 25
lines)Display capacity
640
horizontal
dots,
400
vertical lines
220 x 145
Method
Horizontal
Separate
input,
TTL
level
20
86kHz
29W
power consumpt
MoldedColor
Size
(W x H x U
3
Vertical
47
8 Hz
ion
Office
gray
324x310x356
Weight
7.2kg
Vertical synchronization,
contrast,
brightness
CPU
connection
cable
and
power
cord
and
Tilt
stand
r
- 5-
MZ3500
1-8.
System
configuration
of
Model 3500
Keyboard
MZ-1K02
MZ-1K03
MZ-1K04
MZ-1K05
Printer
'
IO2824E
I
I I
Option
MFDI
I
CE-331M
|
I I
"Model-3541
=
Model-3531
+
MZ-1F03
6
MZ3500
2.
SOFTWARE (MEMORY) CONFIGURATION
Memory
will
be
operated under
four
states
of
SDO
~
SD3,
depending
on the
hardware
and
software configurations.
In the
paragraphs
to
follow,
description
will
be
made
for
those
four
states.
2-1.
SDO
(INITIALIZE
STATE)
SDO
can
only
exist
immediately after power
on, and the
system
executes
IPL
under this
condition
and
that
the
system
thus loaded
will
automatically
assign
memory
area
for
SD1, SD2.
and
SD3.
MAIN
CPU
SUB
CPU
MAS
MA2
MAI
MAO
FFFF
0
0
0
0
cooo
BFFF
8000
7FFF
RAMA
RAMA
RAMA
4000
3FFF
i
|
ROME
[
I
I
2000
I '
0
0
0
1
V
FFFF
RAMA
1
1
1
1
T
MS1
= ° (D
MSO
= 0 (L)
?
IRAM(COM^
jOO1——
^\
reoo1
\\
u
\\
\\
\\
N
v
V\
\
ROM
(SPAPE)
OFFF
0000
ROM
JPL
RAM
(COM)
ROM
IPL
4000
27FF
2000
1
FFF
0000
*7
M 7.
3500
Operational
description
(1)
Upon
reset
after
power
on, the
main
CPU
loads
the
contents
of the
initial
program
loader
(IPL)
into
RAM
starting
at
address
4000H,
during which time
reset
is
applied
to the
sub-CPU.
TIMING
OF
RESET
SIGNAL
Vtc-
SYSKES-
SKES-
pr)WFjJSUB
CPU
PO*E^
START
POWER
OFF
(2)
The
main
CPU
then
terminates
resetting
the sub CPU
and
starts
the
sub-CPU.
At the
same
time,
the ROM
IPL is
assigned
to the
sub-CPU.
(3)
The
main
CPU
then
send
the
memory
allocation
(state)
to
SD1,
and
starts
to
load
DOS
from
the
system
floppy
disk.
Signal
generated
from
the
CR
network
and
power supply
Output
signal
from
the
main
CPU
port
MAIN
CPU
START
a.
Main
CPU
reset
time
b.
Main
CPU IPL
load time
Memory
Map
Data:
1.
ROM-B
is
tested
to
determine
if
ROM's
are
present.
2. The
ROM-IPL functions under
control
of the
main
CPU
at
first,
but
later
it
functions under
the
sub-CPU after
the IPL
program
has
been
loaded
in
RAM.
3.
RAM-COM
is
shared
by
both
the
main
CPU and the
sub-
CPU.
INITIALIZE
FLOW
«TABT
4.
Memories
other
than
described
above
cannot
be
accessed
under
the SDO
state.
5.
Bank
select, MAO~MA3,
is
used
within
the
address
range
ofCOOOH-FFFFH.
ROM-IPL
1. An 8KB ROM
(2764
or
mask
ROM
equivalent)
is
used
for the
ROM-IPL.
2.
When
the
system
reset
signal
turns from
low to
high
state
after
power
on, the
main
CPU
starts
to
operate
At
this
stage,
the
ROM-IPL
is
addressed.
3. The CPU
starts
from
address
OOOOIROM
address
10000)
4. The
main
CPU
sets
the
sub-CPU
reset
signal from
low to
high
state
as it
goes
out of its
initial
state
via the
memory
mapper
and the
sub-CPU
starts
to
operate.
At
this
point,
the
ROM-IPL
is
addressed
by the
sub-CPU.
5.
Address
0000
of the
sub-CPU
is ROM
address
(0000)
The
memory
area
above
ROM
address
(1000)
cannot
be
used
by the
sub-CPU
because
the mam CPU
initial
program
has
been loaded
there.
2-2.
SD1
(SYSTEM
LOADING
&
CP/M)
SD1
determines
which
operating
system
ts in
use.
The
system
is
loaded
in the
CP/M
(Control
Program
for
Micro-
processors)
mode.
MZ3500
Mam
CPU
logical
address
(during
IPL
operation)
Logical
address
of the
sub-CPU
ROM
physical
address
OfFF
0800
0000
1
FFF
1
800
1
7FF
1
OOP
OFFF
0800
07FF
0000
1
FFF
1
800
I
7FF
1
OOP
OFFF
0800
07FF
0000
ROM IPL
MS1
= 0( L)
MSO=l(Hj
MAIN
CPU
r r
F?'
f. ft f
r
^
n
RAMicnu:
4
3
i
\
\
>
\
x
\
V
\
^ \
\ \
\
\
\
\
\ \
\
\
\ \
\
\
\ \
\ \
\ \
RAM sn
RAM SA
KAM«.(IH) 2000
1FFF
- 9 -
MZ3500
Operational
description
(1)
As
soon
as the
sub-CPU
is
started,
it
initializes
the I/O
port
and
waits
for
program transfer (IOCS)
from
the
main CPU.
This
IOCS
(Input
Output
Control
System)
is
the
program resident
at
address
4000H-5FFFH.
(2)
As the
main
CPU
loads
the
information
from
sector
Communication
between
Main
and SUB CPU
"1" of
track
"0" of the
floppy
disk,
it
loads
the
IOCS
and
bootstrap routine
to the
sub-CPU.
(3)
The
bootstrap program
is
loaded next.
(4)
The
bootstrap program determines
rnemory
allocation.
BUSRQ
H
OUTPUT
|
(ISOLATION
OF COM
RAM)
2:3.
SD2
(ROM based BASIC)
SD2 is
active when
"SHARP
BASIC"
is
executed
via
ROM.
MAIN
CPU
MS]
= I (H)
MSO
= 0 Li
SUB CPU
MAS
00
0000
BANK
MA2 ° °
00.1
SELECT
MAI 0 0
1100
MAO
FFFF
i
Sffi
i
\
IFF?
IFF?
J
0000
(MO2
01
0101
1
III
R\MA KAMB
4
3
2
ROME
ROMA
0
1
1, 2, 3| 4
ROMC ROMU ROM!
ROM 2
0001
MO1
00110
MOO
01010
0
1
I
0
1
1 1
0 1 1
1
0 0
I 0 0
1
0 1
1 1
K
\M L
2| 3, 4
1 I 1
0 0 1
1 I 0
0 1 0
1
1 1
1 1
KAMI!
2,
3 |
4
1.
Bank
select, MAO~MA3.
is
effective
for
memory
area
COOOH-FFF
FH.
2.
Bank
select, MOO~MA2,
is
effective
for
memory
area
2000H-3FFFH
-
10
-
MZ3500
2-4.
SD3
(RAM based BASIC)
SD3 is
active
when "SHARP BASIC"
is
ececuted
via
RAM.
"SHARP
BASIC"
is
loaded
in RAM
from
the
floppy
disk.
RAM
BANK
SELECT
ROM
BANK
SELECT
MAS
MA2
MAI
MAO
Ffft
\
gFFF
1FFF
0000
M02
[NOI
MOO
MSI
= 1< H)
MAIN
CPU
MSO
= HH) SUB CPU
0000
0000 III!
1
0000
1111
0000
1
0011 001) 0011
1
0101 0101 0101
1
III III III
lRwnuf%
r 1
\\
RAMB
RANC
KAMI)
v\
\v
1
2,3,4
1,2,3,4 1,2,3,4
\\
\\
N\
-
vx
\\
RAN.
SP
\\
RAN
SC
, \ ,
RAM
SB
KU
"°
RAMA
ROM!
ROM2
KOM3
K(IM4
\\ ROM BAS
k
' SUB CPU
]L
ROM
1 PI
000 0 ) i ]
0
0 1 " 1 0 0 1
010
10 1 0
1.
Bank select, MAO-MA3.
is
effective
for
memory
area
COOOH-FFFFH.
2.
Bank select, MOO-MO2,
is
effective
for
memory
area
2000H-3FFFH.
Operational description
The
state
of the
system
is
determined
by the
bootstrap
program
before
the
load
of the
system
program.
3. CPU AND
MEMORY
3-1.
Block
diagram
1)
Relation between
MMR
(Main Memory Mapper)
and
main
memory.
, RAM
I
(II'TION
1
4-
RAN
'
64KBV2)
VI
°l
RECEI
VFR
1
1
OPTION
.
Ml
DM1
I
MO*J
OK
II K U MO* 400
kl Mil I 1 ION
I
JK» 2K*
J
(,
{)
R
si v i
(.us
TOM
1
SI CSI -2
It
L
||
'7220
i
,APM,C
MPXR
VIIIK1
RAM
32KB
V
1 HI O RAM
32KB
VIDH)
RAM
32KH
RS-232C
l/f
SEMI
CUSTOM
IS!
CSI'-I
I
MZ3500
3-2.
Main
CPU and I/O
port
M
A
I
N
C
P
u
r^
IX
A2
A3
A4
—££-1
A6
A
v~\
r
M
P C
IORQ
M
i
j^
Y 1
iZ
(jtA.
Y3
Y4
G2
B
Y5
Ol Y6
74LSI38
This
paragraph
discusses
main
CPU I/O
Connector
Port
select
and
addressing.
I
PC
2 The
address
output
from
the
main
CPU
|~^T
1 is
decoded
in the
74LS138
to
create
the
""
v
select
signal.
~s
f^-r-^r-.
—
r
Table
below
describes
address
map and
~~>
\J>
-•>
r DL
signal
functions.
J
\J I
Obr
-)
f\
J -\J
^
0
MFUC
•
\J
lUMr
5 O
IOABCMEMORY
MAPPER)
ADDRESS
A7 A6 A5 A4 A3 A2 A1 AO
00000000
00000001
11011110
11011111
^^^Qooxx
^^^QO•^xx
iiiotoxx
11101
1 X. X
1111QOXX
1 1 1 1 0 1 X X
1 1 1 1 1 0 X X
1
1 1 1 1 1 X X
HEX
00
01
DE
DF
EO
E3
E4
E
7
E8
EB
EC
EF
FO
F3
F4
F
7
F8
F
B
FC
F
F
NOT USE
NOT USE
SFDC
(UPD765)
IOSF
INTR
NOT USE
MFDC (UPD765)
IOMF
IOAB
(MEMORY
MAPPER)
SFD
interface
FDC
chip
select.
AO
used
for RD and WR.
A1 is
"don't
care".
SFD
interface
I/O
port
and
DMAC chip select.
Interrupt
signal
from
the
sub-CPU
to the
main
CPU.
Flipflop
resetting signal.
MFD
interface
FDC
chip
select.
MFD
interface
I/O
port.
AO
used
for RD and WR.
AT
is
"don't
care".
I/O
port
select
in the
memory mapper.
AO
and A1
used
during
~W5.
WR.
MZ3500
3-3.
Sub CPU and I/O
port
SUB
CPU
AS6 5
ASS
2
AS4
i
AST 4_
*""
5
"MT
6
Y6
4G
Y4
Gl
Yl
YO
74LS138
J s07 *.
~9
S06
_JQ
SOS ^
J
r
CKP
1 .
CSP
2
.Jl
SO4
^ . .
......
012
S03 ,. -^
D15
S°2
HEC3
-C*
14
"SOT
-^
D15
'*°°
r
MAIN
CPU
\m
Shown
at the
left
is the
circuit
used
by
the CPU to
select
the I/O
ports
The out
put
address
from
the sub CPU is
decoded
by the
74LS138to
create
the
select
signal.
Shown
below
is the
address
map and
select
signals.
AS
7654
M£X\
88
1
23456789ABCDEF
88
Signal
description
0000
soo
Output
signal
to set the
flipflop
to
apply
interrupt
(INTO)
to the
main CPU.
Enables
communication between
CPU's.
0001
S01
8251
8251
SIO
chip
select.
ASO
is
used
for
data
control
selection.
AS1,
AS2,
and ASS are
"don't
care".
0010
S02
8253
8253
counter
chip
select.
ASO
and AS1 are
used
for
programming during write.
AS2 and ASS are
"don't care".
0011
S03
8255
8255
PIO
chip
select.
ASO
and AS1 are
used
for
port/control
selection.
AS2
and ASS are
"don't care".
0100
S04
input port
select
8-bit
input port.
Used
for
read.
AS3
are
"don't
care".
0101
805
CRT
control
I/O
port
chip
select.
AS1,
AS2,
and ASS are
used
for
write.
ASO
is
"don't care".
0110
S06
UPD7220
(graphic)
chip
select.
ASO
is
used
for
read
and
write.
AS1,
AS2,
and AS3 are
"don't
care"
0111
S07
UPD7220
(character)
chip
select.
ASO
is
used
for
read
and
write.
AS1, AS2,
and AS3 are
"don't
care"
1000
1001
1010
1011
1100
1101
1110
1111
NOT USE
-
18-
MZ3500
3-4. Memory mapper
(MMR)
SP6102R-001
1)
Block
diagram
ADDRESS
BUS
AO
. i. is.
COAB
CONTROL
BUS
MERQ
RFSH
RD
"WR
DATA
BUS
I
— \
DO-D7
INTB
WAITB
SYSR
A15
A14
AI3
A]
AO
COAB
MKEQB
RFSH
V
Memory
mapping
logic
A 15
AU
RB
OAB
I/O
PORT
LOGIC
~L
—
L
n
-
WAIT
TIMING
GENERATOR
CLK
->TO
RESET
INTERRUPT
PRIORITY
ENCORDER
1NTFI)
-
19
-
MZ3500
2)
Memory
mapper
(MMR)
SP6102R-001
signal
description
1
2
9
10
12
13
14
15
16
18
19
20
21
22
23
26
27
~
30
31
Polarity
Signal
Name
ST
DO
D7
A15
A13
A1
SRES
SRQ
AR13
AR15
R32
IOAB
SRDY
ROPB
ROAB
RODS
RSAB
~
RSDB
SACK
IN
IN/OUT
IN
IN
OUT
OUT
OUT
OUT
IN
IN
OUT
OUT
OUT
IN
Main
CPU
DRAM
output
buffer
(LS244)
switching
strap.
Bidirectional main
CPU
data
bus.
(Data
bus 0 ~ 7)
Main
CPU
address
bus.
Used
in the
memory mapping logic
of the MMR for
address
output
for the
DRAM,
ROM,
and
shared
RAM. (Address
bus 13 ~ 15)
Main
CPU
address
bus.
Used
in the I/O
port
select
logic
of the MMR to
assign
device
number.
Sub-CPU
bus
request
signal.
•
After power
on:
Halts
the
sub-CPU.
•
After write command (LDA-80H: OUT#FD)
by the
main
CPU-
Starts
the
sub-CPU.
This
signal
is
issued after transfer
of the
main
CPU
program contained
in the
ROM-IPL.
(Sub
CPU
Reset)
Sub-CPU
bus
request
signal.
•
After power
on:
Resets
bus
request
to
sub-CPU.
•
After write command (LDA-02H1 OUT#FC)
by the
main CPU'
Place
bus
request
to the
sub-CPU
This signal
is
issued
to bus of the
sub-CPU, after
the
main
CPU
writes
to the
shared
RAM a
command
parameter
to the
sub-CPU
or
reads
the
message
status
from
the
sub-CPU.
(Sub
CPU
Request)
Address
signal
to the
main
CPU
dynamic RAM.
The
main
CPU
address
signals,
A
13-A
15,
merged
in the
memory mapping logic circuit
to
produce
AR13-AR15. This
is
means
by
which
the 4
basic
and
CP/M memory
maps
are
made,
along
with
MS1
and
MSO.
BASIC
interpreter 32KB
mask
ROM
chip
select
signal.
Valid
when
SD2 is
active (Sharp
ROM
based
BASIC). Command (LDA
02H OUT
3FD)
(ROM
32K
select)
Internal
MMR I/O
port
select
logic
signal.
Goes
low by the
command
IN/OUT
#FC-#FF.
(Input/Output
Address)
Input
of
ready
signal from
the
sub-CPU.
(Sub
CPU
Ready)
Chip select signal
issued
from
the
main
CPU to the 8KB
mask
ROM.
Valid
with
SDO
active
(initialize
state).
(ROM
ipl)
Chip select
signal
for
four
chip
BASIC interpreter
8KB
EPROM
(A. B. C, D).
Valid
with
SD2
active (Sharp
ROM
based
BASIC).
"R32B (alternate choice
with
the
32KB
mask
ROM
chip select signal).
(ROM
A~D
Buffer)
Row
address
select
signal
for the
main
CPU
dynamic
RAM
(block A-block
D).
RAS
(ROW
ADDRESS
SELECT; LINE
ADDRESS
SELECT)
SIGNAL
(Row
address
Select)
Input
of bus
acknowledge
signal
from
the
sub-CPU.
command
is
written
in the
shared
RAM
after
acknowledgement
from
the
sub-CPU
1
At the end of the
command
cycle
bus
request
is
released
and the sub CPU
executes
the
command
/
-
20-
M 7,
3500
Pin
No.
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
Polarity
Signal
Name
RF1B
RF2B
WATB
RCMB
ITFB
ITOB
IT1B
TT2B
MRQB
WRB
IT3B
IT4B
SEC
GND
Vcc
SW1
SW2
AO
RFSH
SW3
SW4
GND
FD1
Vcc
FD2
IN/OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
Function
Main
CPU
128KB
dynamic
RAM
output
buffer
(LS244)
output
enable signal.
(RAM
buffer
1)
Signal
identical
to R F 1 B For
option
RAM
(RAM
buffer
2)
Wait
signal
to the mam CPU
(One
wait
cycle
15
applied during
the
memory fetch cycle
of the
main CPU.
It
consists
of one
clock
period)
(WA|T)
Chip
select
signal
issued
from
the mam CPU to
select
the RAM
shared
by the
main
CPU and
the
sub-CPU
(RAM
Common)
Interrupt
input
from
the
UPD765
FDC
(Floppy
Disk
Controller).
(Interrupt
from
Floppy)
Interrupt
input
from
the
sub-CPU.
(Interrupt
from
No. 0)
Interrupt
input
from slot
1 or 2.
(Interrupt
from
No. 1, 2)
Memory
request signal
from
the
main
CPU.
(Memory
Request)
Write
signal from
the
main CPU.
(Write)
Interrupt
input
from slot
3 or 4.
(Interrupt
from
No. 3, 4)
Input
from
the FDD
(Floppy Disk Drive) assignment
dip
switch
(A),
No. 1.
'See
the dip
switch
description,
provided
separately.
(Section)
Ground
5V
supply
Input from
The
svstem
assignment
dip
switch,
"See
the dip
switch
description,
provided
separately.
Mam CPU
address
bus
Used
rn the I/O
port
select
logic
in the MMR to
designate device
number.
Refresh
signal from
the
main CPU.
(Refresh)
Input
from
the
system
assignment
dip
switch.
•See
the dip
switch
description,
provided
separately.
Ground
Input
from
the
system
assignment
dip
switch.
'See
the dip
switch
description,
provided
separately.
5V
supply.
Input
from
the FDD
assignment
dip
switch (A),
No. 2.
*See
the dip
swi'ch
description, provided
separately.
M
7.3500
MAIN
CPU
I/O
PORT
IN
MEMORY
MAPPER
ADDKKSS
A7
A6
A5|A4|A3|A2|Al|AO
1
1 1 1 1 1 0 1
11111110
11111111
HEX
KI)
FE
FF
UHUS
01
DO
D7
Dl
DO
1)7
D6
D5
D4
D2
Dl
DO
D4
D3
D2
Dl
DO
D7
D6
D5
1)4
D3
D2
Dl
DO
D7
D6
1
O
r\i IT
OUT
INI
IN
SKQB
1 1
SKI
S
MS]
MSO
M<\3
MA2
MAI
MAO
MO2
MOI
MOO
SW4
b«3
M\2
Sttl
she
FD3
FD2
H>1
SKDY
SACK
1NP2
I
MM
IN'1'0
MF2
Mhl
_J
SRQ
Bus
request from
the mam CPU to the
sob-CPU
Sub-CPU
reset signal
Memory
system
define
Bank
select
signal
to
memory
area
of
COOO-FFFF.
Bank
select signal
to
memory
area
of
2000-3FFF.
System
assign
switch
FD
assign
(SW8)
•f>
Sub-CPU READY
signal
•p
Sub-CPU acknowledge
signal
Interrupt
status
1. All
output
signals
are
reset
to low
level
upon
power
on,
except
for
SRBQ
that
goes
high.
2.
Noted
with
a
star
mark
"£" are
input/output
signals,
and
rest
of
others
are
processed
in the
LSI.
#1 I/O
port
output
of ME1 and ME2
uses
the
memory
at
the
addresses.
(
ME2->8000~BFFF
I
ME1->-4000~7FFF
When
ME1 and ME2 are in
high state.
RSAB
(RASA)
is
inhibited
during memory
addresses
in
RAM-A
that
correspond
to
overlayed
addresses
for MET and ME2
This
is not
true during
SD1
mode.
Mm
i i -^. t
<|,
"fJ~
11
1 H
" I "
H
j H
M II TO t
MOI«m
n (i H j 1 I 1 H M 2 h
TvfT
J
i\=TjTNT7
1
j X X
H 1 H | 1
H j H j H
Tisn
JM3
H
j H j H | H
1
T4h
01
iri T
hkoM
fMont
IM 2
1
1
1
L
H
H
IM 1
X
L
H
H
|M It
"-
T"
H
I
H
I ' 1
1
h
L
1 H |
i
l
FKOM
SI
in
TO
HA
""•»
M" l"
Wait
timing
generator
WAIT
is
issued once
per
main
CPU
fetch
cycle.
Its
outut
is tri
state
MZ3500
3-5.
Memory
(ROMIPL,
RAMCOM,
S-RAM) select circuit
To
main
CPU
1)
ROM-IPL
select
by the
main
CPU
As
ROM IPL
turns
to low
level after
power
on
address
bus
buffers
(LS244,
LS367)
and
data
bus
buffer
(LS245)
are
enabled.
S of the
data selector
1C
(LS157)
is
set to a low
level
to
enable
input
1A-4A.
The 3Y and
2Y
outputs
of the
LS157
then
go low so
that
CE and OE
of the
ROM-IPL
are
from
main
CPU.
The
contents
of
the
IPL-ROM
are
then
read
by the
main
CPU. Because
the
input
pin
(^16)
of the
address
buffer
(LS367)
is
connected
to
Vcc,
IPL for the
main
CPU
will
be at
address
1000
of the
IPL-ROM.
Switch
SW2BA
is the
operation
test
dip
switch
which
should
be ON at all
times.
2)
RAM-COM select
by the
main
CPU
When
RAM COM is
low, SRES
high,
and
SACK low,
the
select
input
S of the
selector
1C
(LS157)
is in low
state
so
that
input
1A-4A
becomes
effective.
That
is, the
out-
put 4Y is low and
either
1Y
(WE)
or 2Y
(OE) becomes
low
level,
so as to
enable
to
read
or
write
RAM-COM.
3)
ROM-IPL
select
by
sub-CPU
Normally,
the
select
signal
S of the
selector
is
pulled
up
to Vcc
level
that
inputs
1B-4B
are
enabled
by sub
CPU.
If A13
thru
A15
were
to be at low
level,
the
output
YO
of the
LS139
becomes
low
level
so
that
the
output
3Y
of the
LS147
or CE of the
ROM-IPL
should
be at low
level.
Should
SRD, SMRQ
be at low
lebel
as
well,
the
output
2Y of the
LS157
or OE of the
ROM-IPL
turnde
to low
lebel
to
read
the
ROM-IPL.
Though
the
sub-CPU
can
access
an
address
range
of
0000
to
1FFF theoretical-
ly, it
would
be
from
0000
to
OFFF, actually.
4)
RAM-COM
select
by
sub-CPU
Y1 of the
LS139
changes
to low
level
when AS13
is
high
and
AS14
and
AS15
are
low.
In
other words,
the
input
4B of the
LS157
is at low
level
which
brings
the
output
Y4 to low
level,
so
that
CS of the
RAM-COM
chip
select
signal
should
become
effective.
If
SMRQ,
SRD or
SMRQ,
SWR is in low
level
at
this
point,
it
enables
read
(OE)
or
write (WE). Address range,
however,
is
2000
to
3FFF
5) RAM
(SA,
SB, SC, SD)
select
by
sub-CPU
SMRQ,
SRD
(Of)
or
SMRQ,
SWR
(WE)
is at low
level
to
select
the
sub-CPU dedicated RAM, SA-SD.
Tne
following
chip
select
signal, then becomes valid under
these
conditions:
RAMSA
..
ASVi,
AS12, AS13, AS14, AST!
(address
4000^17FF)
RAMSB
..
AS11,
AST2,
AST3,
AS14, AS15
(address
4800-4FFF)
RAMSC
..
AS11, AS12, AS13, AS14, AS15
(address
5000-57FF)
RAMSD
..
AS11, AS12, AS13, ASK,
ASHi
(address
5800-5FFF)
-
24
-
4. CRT
DISPLAY
4-1. Specification
Display
memory
Character
display
Graphic display
(option)
Screen
structure
Programmable
Character
structure
Attributes
Colors
32KB
type
96KB
type
Screen
merge
Merge
of
chracters
and
graphics
Background color
Control
of two
independent
screens
Control channel number
Light
pen
input
(option)
Ust
of
high
resolution
CRT
3KB
(characit>-s!
Option
96KB.
max
(graphic
i
80
chrs
x 25
lines.
80
chrs
x 20
lines
40
chrs
x 25
lines,
40
chrs
x 20
lines
8x16
dots
With
lower
case
descenders
255
characters
Alphanumencs
and 69
symbols
26
small
characters
97
graphic
patterns
Revers,
vertical
line,
blink,
horizontal line
Programmable
for
each
character
8
colors, programmable
for
each
character
640 x 400
dots,
B/W
(one frame)
Color
designation
for
each
character
640 x 400
dots.
B/W
(three frames)
Color
designation
possible
for
each
character
Color
(one frame)
Use
of
medium resolution (,RT
8x8
dots
Blink,
revers
Programmable
for
each character.
640 x 200
dots,
B/W
(Two frames)
Color designation possible
for
each
character
640 x 200
dots.
B/W
(six frames)
Color designation possible
for
each character
Color
(Two
frame)
Merge
any
graphic screen
(1 to 3
frames)
Merge
a
character
screen
with
a
graphic
screen
Choice
of 8
colors
Possible
to d
aplay
on
separate
two
screens
ongind1
graphic
screen
and
character
screen
Separate
graphic
screens
can be
merged into
one
Possible
to
affix
attributes
(CRT2 only)
Selection
of
character/non-character
screen
display
Incorporation
of two
independent video
outut
channels
Scans
coordinates
and
character
code
Summary
of
video
display
specification
Table
1
^""~-\^
Type
of
monitor
Function
^^\^^
Elements
Character
structure
Screen
structure
(Characters
x
ines)
Color
designation
Basic
Option
1
(48KB)
Option
II
(96KB)
Small
tetter
descenders
Line
creation
Display
memory
Frames
Screen
overlay
Basic
Option
1
(48KB)
Option
II
(96KB)
Basic
Option
1
(48KB)
Option
II
(96KB)
High
resolution
CRT
(640
x 400
dots
mode)
Green
monitor
Characters
ASCII
8x16
8 x 20
5x14
80 x 25
mode
80 x 20
mode
40 x 25
mode
40 x 20
mode
O
O
3KB
1
frame
t
t
Graphics
(option)
B/W
640 x 400 dot
32KB
No
frame
1
frame
3
frames
Not
possible
One
character
screen
Against
one
graphic
screen
One
character
screen
igain-,t
three
graphic
srrpens
Color
monitor
Characters
ASCII
8x 16
8x 20
5x14
80 x 25
80 x 20
40 x 25
40 x 20
By
character
t
t
O
X
3KB
1
frame
t
t
Graphics
(option)
Color
640 x 400
By
character
By
dot
32KB
II),96KB(II)
No
frame
1
frame
1
frame
*-
One
character screen against
one
graphic screen
One B/W
character
screen
against
three
graphic
screens
One
color
character
screen
against
one
graphic
screen
Medium
resolution
CRT
(640
x 200
dots
mode)
Green
monitor
Characters
ASCII
8x8
8x10
5x7
80 x 25
80x20
40 x 25
40 x 20
X
X
3KB
1
frame
(1
page)
t
t
Graphics
(option)
B/W
640 x 200
16KB
No
frame
3
frames
6
frames
«-
One
character
screen
against
three
graphic
screens
'
Color
monitor
Characters
ASCI:
8x8
8x10
5x7
80 x 25
80 x 20
40 x 25
40 x 20
By
character
t
t
X
X
3KB
1
frame
(1
page)
t
t
Graphics (option)
Color
640 x 200
By
dot
t
48KB
No
frame
1
frame
2
frames
-
One B/W
character screen agamst
three
graphic
screens
One
color
character
screen
against
one
graphic
screen
•
I
NOTE
Graphics option
M7
3500
1)
Character
display
1.1.
Screen
structure
CRT
used
Character
ASCIL
High
resolution
CRT
(640
x 400
dot)
fH = 20
9KHz
(New)fV
= 47 3Hz
80 x 25
lines
80 x 25
lines
40 x 25
lines
40 x 20
lines
Medium
resolution
CRT
(640
x 200
dot)
fH = 15
7KHz
fV =
60Hz
-
Dip
switch
in the mam
unit
is
used
to
select assignment
of
high
resolution/medium resolution CRT.
Display
mode
must
be
chosen
by
programming.
1-2.
Character
structure
and
picture elements
ASCII
Graphic
symbol
640 x 400
Elements
8x 16
8 x 20
1
Structure
5 x 14
8 x 16
Small
letter
descenders
and
line creating
functions
are
available.
640 x 200
Elements
8x8
8x10
I
Structure
5x7
8x8
Small letter descenders
and
line
creating
functions
are not
available.
NOTE:
In the
case
of 8 x 8 and
8x16 picture elements,
vertically
adjoining graphic symbols
will
joint
together
in the
25-line mode.
As
for
character
structure
of 6 x 14, 7 x 14,
6x7,
or 7 x 7,
decision must
be
given
on an
actual
dot
pattern.
2)
Graphic display
(option)
(High resolution CRT) (Medium resolution CRT)
640 dot 640 dot
400 dot
200
dot
Dot
pitch
Horizontal
vertical
= 1
Dot
pitch
Horizontal
vertical
= 1 : 2
W
Whne
Three
basic
colors
4)
Attribute
AT1
AT2
AT3
AT4
B/W
Vertical
line
Horizontal
line
Reverse
Blink
Color
B
R
G
Blink
Designated
for
each
chaia-
cter.
Line
and
character r,,uy
exist
in the
same
element
(Line
may
also
be
dis-
played
on the 80
charac
ters
x 25
lines
screen.)
5}
Screen
overlay
It
will
be
possible
to
have
an
overlaid
screen
that
consists
of one
character (screen
and a
maximum
of
three
graphic
screens.
(For
detail
of
overlay
screen,
refer
to
Table
1.)
In the
color
mode,
if
there
are two
colors
in the
same
screen
and
other
designated
for a dot on the
graphic
screen
element
— the one
designated
for a
character
on
the
character
—
both
colors
will
be
merged sltorjpther
to
produce image.
00
o
o
O
o
(Red)
© Dot
color designated
by
character
attribute
(Blue)
O Dot
color
designated
by
graphic
dot.
(Violet)
Q Dot
composed
of
more
than
two
color
Jj>i"jrn*ion:.
3)
Color
designation
Eight
colors
are
usable
(white,
yellow,
cyan, green,
violet, red, blue, black)
Color
designation
ASCII
Graph
48K
byte
|
96 K
byte
640 x 400 dot
By
character
By
character
By
dot
640 x 200 dot
By
character
By
dot
By
dot
Background
color
8
colors
for
designation
MZ3500
7)
ASCII
CG
Uses
an 8KB
MROM
contains
two
patterns'
640 x 400
dots (8x16 dots)
and 640 x 200
dots
(8x8
dots)
#OFFF
#0000
#1 FFF
#1 000
8x8 dot
pattern
(2K
byte)
! x 8 dot
pattern
(2K
byte)
8 x 16 dot
pattern
(4K
byte)
For
Model
3200
series
Without
lower-case,
letter
descenders
With
lower-case,
letter
(h i j)
descenders
With
8 x 8 dot
format
two
kinds
of
patterns
coexist
Refer
to ROM
address
and
data
code
on
separate
information
Model 3500
Address
and
pattern
in
picture
element
12
(Example
of 5 x 12
dots
pattern
for 1 x 16
elements)
8)
Element structure,
character
structure,
and
line
D7| |
DO
(Address)
O
o
o
o
o
o
O
0
o o
ooooo
ooooo
o o
0 0
o o
0 0
.
#1000
#1001
#1002
#1003
#1004
#1005
#1006
#1007
#1008
#1009
#100A
#1006
#100C
#100D
#100E
.-
#100F
(Data)
#00
10
10
28
28
44
44
7C
7C
44
44
44
44
00
00
00
Element
structure,
character
structure,
and
line
/—
Character
pattern
area
\—
Line
area
X—
Area
where
pattern
and
line
are
overload
640
x 200 dot
1)
25
line
display
mode
15 2
IASCD/JIS]
8
Without
line
[Graphic
symbol
640 x 400 dot
1)
25
line
display
mode
12
'With
line
HL On
16th
line
VL
Line
ot the
right
of
element
In the
case
of
graphic
symbol
display
Both
HL and
VLare
overlaid
to the
pattern
-
29
-
M
7
3500
2)
Read/write
from
Z 80 to
VRAM
(1)
Timing
period
for
display
and
V-RAM
Read/write.
//><-'
Range
wh°r?
GDC can
draw.
H •
SYNC-
BLNK-
J
(2)
Timing
that
the
Z-80
can
read/write VRAM
The
Z-80
can
read/write VRAM when
GDC
FIFO
buffer
is
either
empty
or
Full,
and can be
accessed
by
3)
Structure
of
character VRAM
(1)
When read/write
from
GDC
#07FF
#0000
(A)
2KX8
ASC I I
8bi t
4bit
DO
"D7 V&
«-Dll
Fly
back
period
refreshing
during
the
display
period.
Number
of
characters
that
can be
read/write
within
one
raster
in
any
mode.
(A)
(B)
ASCI
I(8bit)
(
12bit
)
DO
Dl D2 D3 D4 D5 1)6 D7
DO
Dl
D2
D3
•
Blink
Reverse
(G)
Vertical
line
(R)
.
Horizontal line
(B)
(2)
During display
#07FF
#0000
(A)
2KX8
(B)
2KX4
12bi
t
(2)
640 x 400
dots display mode
Option
I
(48Kbyte)
#4000
16
bits
structure
# 3 KKK
*0000
Option
II
(96K byte)
16
bits
structure
(BFFF
#8000
#4000
#0000
16K
16K
#3FFF
#0000
#3FFF
#0000
M
Z
3500
B/W:
1
frame
Color:
1
frame
Color
can be
i
designated
for
sach
character.
16K
B/W:
3
frames
Color:
1
frame
16bit
16bit
16bit
16K
16bit
5)
Synchronize signal timing
(1)
For 640 x 200
dots
display
mode
fH =
15.87kHz
fV
= 60 Hz
X
: Y - 1 : 2
Dot
clock (OD)
2XCCLK
Horizontal display
time
HFP
HS
HBP
Vertical
display
time
VFP
VS
VBP
GDC-1
(80
digits)
Character
display
(40
digits)
(16MHz)
(
8MHz)
(4MHz)
<2MHz>
40MS
?A«
6>js
10/js
1
2.6ms
1.2ms
1 ms
1.8ms
GDC-2
8
bits
16MHz
4MHz
-
•^(14 Chr.)
(1?Chr
)
(tREF-0.8ms)
-
(20
Chr.)
-
-
-
-
graphic)
16
bits
16MHz
2MHz
-
10MS
5^s
(tREF
=
1.6ms)
8ns
-
j
-
-
Total
rasters:
261
rasters
Display
raster:
200
rasters
—-1 r~-
•—n.
MZ3500
(2)
640 x 400
bits
display
mode
fH =
20.92
kHz
fV =
47.3
Hz
X
: Y : 1 : 1
Dot
clock
(OD)
2XCCLK
Horizontal
display
time
HFP
HS
HBP
Vertical
display
time
VFP
VP
VBP
GDC-1
(80
digits)
Character
display
(40
digits)
(19
66MHz)
(9
83
MHz)
(4.9152MHz)
(2.4575MHz)
32
55^s
80
Chr.
/40
Chr.
4.88fjs
4^is
6 5ys
19.16ms
0.527ms
0.24
ms
1.198ms
GDC-2
8
bits
19.66MHz
(50.86ns)
4.9152MHz (203.45ns)
-
«-
*~
(tREF=0.6ms)
-
-
-
«-
-
graphic)
16
bits
9.83MHz (101
92ns)
24575MHz (406 9ns)
-
-
5
Chr.
*~
(tREF
=
1.23ms)
-
-
-
-
-
Total
rasters:
441
rasters
Display
rasters
400
rasters
(3) CRT
synchronizing
signal
specification
(400
raster
CRT)
1.
Horizontal
synchronization frequency
(fH):
20.92kHz
2.
Vercial synchronization frequency (fV): 47.3Hz
3.
Total
rasters:
441
rasters
4.
Rasters
used:
400
rasters
5.
Display
dots:
640 x 400
dots
6. Dot
clock:
(19.66MHz)
7.
Timing
9. HS, VS, and
VIDEO
signals
are
supplied
from
the LS
type
TTL 1C
(totem
pole)
6)
Setup
of GCD
master/slave
(1)
Master/slave setup
by
combination
^^•v^^
Character
^^•\^^
GDC
Graphic
^^^^
GDC
^"\^
Without
VRAM
PWB
8 bit
structure
48K
byte
200
rasters
16-bit
structure
96 K
byte
48K
byte
400
rasters
40
digits
Character
Character
Character
80
digits
Character
Ch3rai.te'
Graphic
Master
should
be
setup
in the
above
i.ia.
(2)
I/O
signal
switching
!
VFP:
11
rasters
(0.5ms)
VS-
5
rasters
(0.24ms)
VBP-
25
rasters
(1.2ms)
8.
Output
method
HS, VS. and
VIDEO
are
indpendent
outputs.
PIT A ft to
(8255.PB7
)
fiQ /I p ,, ,. ,fc
(CSP-2)
VSYNC
Switching
Circuit
M-3500
CH48
-
0 For 40
digit
display
Relation
between VRAM
address
and
screen
1
: For 80
digit
display
There
is a
40/80 digit switching
signal
I/O
port
in the
gate
array
of
CSP1
and
CSP2,
but,
the I/O
signal
called
CH48
is
provided
apart
from
the I/O
port.
I
08/16
- I/O
port
inside
CSP1
and
CSP2.
7)
Graphic
V-RAM
Address
Relation between
VRAM
address
and
screen
(640
x 200
dots)
8-bit
structure
t
lnntn"~^
~
Graphic
address
map
for
200
rasters
LXH)
liytr
0000
0050
00\0
OOFO
16-bit
structure
Graphic
address
map for
400
rasters
bOb\ir
—
CRTC block
diagram
Color graphic
VRAM
PWB
(option)
MZ3500
4/6.
Master
slice
LSI
(CSP-1)
SP6102C
002
signal
description
1
2
3
4-6
7-9
10
11
12
13
14
15
16-18
19
20.21
22
23
24
25
26-28
29
30
31
32
33
34
35
36
37
38
39
40
Priority
Signal
Name
HSYi
NABC
CSR
ASO
-
AS2
DSO
-
DS2
G2
NWRO
NVB
NVR
NVB
FYD2
AT2
-
AT4
CH
GND
DSP2
VID2
LCD
AT1
LC1
-
LC3
NCL4
HSYO
RA40
VIDI
B1
R1
Of
SL1
B2
R2
BLNK
Vcc
IN
IN
IN
IN
IN
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
OUT
OUT
IN
IN
Horizontal
synchronizing
signal
from
the
GDC1
Also,
it
becomes
the
refresh
timing
signal
in the
dynamic
RAM
mode.
Input
from
the
UPD7220
GDC1. When
the
GDC1
is in the
character
display
mode,
the
attribute,
blinking timing
and
line
counter
ciear
signals
are
multiplexed.
Input
from
the
GDC1 which
is the
cursor
display
input when
the
GDC1
is in the
character
display
mode.
Address
bus
input
from
the
sub-CPU.
ABO
=
ASO,
AB1 = AS1 , AB2 = AS2
Data
bus
input
from
the
sub-CPU.
DBO
=
DBO,
DB1 = DB1 , DB2 = DB2
Green
image
output
to the
CRT2.
CSP1
I/O
port
select
signal
(OUT #5X)
Input
of the
blue image from
the
graphic
RAM(A)
and
(B).
Input
of the red
image from
the
graphic
RAM
(B), (C),
and
(D).
Input
of the
green
image
from
the
graphic
RAM (E) and
(F).
Input
of the
graphic
RAM
parallel/serial
conversion
1C
74LS166
shift
out
clock.
(Used
to
latch
the
image
data
in
CSP1
.)
Attribute
data
input
from
the 21
14A-1
attribute
RAM.
f
AT-2
-
Horizontal Ime/R
"]
AT-3
-
Reverse/G
|_AT-4
-
Blink
J
Input
of
character display data signal.
0V
supply
Input
of
display
timing
signal supplied from
the
CSP-2.
(BLINK signal
from
the
GDC2
is
delayed
by
two
flipflop
intervals
in the
CSP-2
to
creat
this
signal.)
VIDEO
output
to
CRT2.
Character
CG
line counter
output.
(Becomes
address
input
to the CG
when
LCD = CG
address AO.)
Attribute
data
input
(vertical line/B)
from
the
2114A-1 attribute RAM.
Character
CG
line
counter
output.
(LC1
= A1, LC2 = A2, LC3 =
A3CG
= A3)
Character
CG
output
data latch
timing.
CRT1
, 2
horizontal
synchronizing
signal
The
signal that turns high
level
when
the
400-raster
CRT is in
connection. LDA,
01 H
OUT??56
VIDEO
output
to the
CRT1
.
Blue image
output
to the
CRT1
.
Red
image
output
to the
CRT1.
Green
image
output
to the
CRT1.
Character
CG
output
parallel/serial converter
1C
74LS166
shift
load
signal,
and
character
CG
address
latch
signal
input.
(Used
for the
image data latch signal
in the
CSP-1
and
horizontal synchronizing
signal
delay
flipflop
clock.)
Blue image
output
to
CRT2.
Red
image
output
to
CRT2.
Erase
signal from
the
GDC1 which
becomes
input
at the
following
times.
1.
Horizontal flyback period
2.
Vertical flyback period
3.
Period from
the
execution
of the
SYNC
SET
command
to the
execution
of the
DISP
START
command.
4.
Line drawing period
+5V
supply.
-
39
-
M/3r>00
36
37
38
39
40
Priority
Signal
Name
M32
FS
DSP2
CAS
2
Vcc
IN
OUT
OUT
OUT
IN
Clock
input
32MHz,
200
raster
Graphic
DRAM
address
multiplexer
signal
(High
order
8
bits
I ADS ADI 5]
/low
3'der
S hi"
|ADO AD7] select signal
)
Display
timing
signal
(In the CSP 2, the
signal
BLINK
from
GDC2
is
delayed
by 2
collor
intervals
to
create
this signal
)
Graphic
D RAM CAS
(COLUMN
ADDRESS
SELECT)
signal
(Line
address
selection)
+
5V
supply
CSP
2
Block Diagram
VWRO
—
C
KAS2
—
C
Ubl 2
—
C
r*
-a.
32MHz
Jl
PR
Hexadecimal
counter
200
Raster
Clock
select
3«32MHz
^
ClfCU1,
*M
n~, *
^00/41
4U(J HasTer
rasters
to
1
O
L>
•
Oh
16
40/80
, c
F
™
O
D
£
5
8/1
6
bill
0 t
T
ft.
CK
Q
I)
F
F
O
5
select
circuit
S-RAM
& CG
control
signal
generator
C
i i
i ' '
:
co
3
6
GDC1
&
character
L
display
clock
generator
GOC2&
graphic
display
clock
generator
Cfi
DBI2D
^
F
'
DRAM
control
signal
generator
K
n
Q
2
— 3
)ECODER
' '
' •
GDC2
Read
ignal
generator
n
L}
h
P°
\ C K
t f
^—
Bl SC,
D-
SOf
O- SHE
O—HB
1 A
-
42
-
M
7.3500
4-7.
GDC
(Graphic
display
controller)
(UPD7220)
signal
description
1
2
3
4
5
6
7
8
9
10
11
12~19
20
21
22-34
Polarity
Signal
Name
2XCCLK
DBIN
HSYNC-REF
VSYNC
EX.SY
NC
BLNK
RAS
DRQ
(NO
USE)
DACK
(NO
USE)
RD
WR~
AO
DBO-DB7
GND
LPEN
ADO-AD12
IN
OUT
OUT
IN/OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN/OUT
IN
IN
IN/OUT
Double
character
clock supplied from
the
external
dot
timing
generator
which
has the
followin^
two
modes:
1.
Character
display
mode1
Single
phaseclock
at one
half
of the one
character
wide
cycle
2.
Graphic
disp'ay
mode:
Single
phase
clock
of
eight
dots
that
cycles
Memory contro
signal
supp'ied
to the
image
memory from
the
GDC, which
causes
the
image
memory
output
data
to be
sent
on the
data
bus.
Memory
contro'
signal sent
to the
image memory
from
the
GDC,
which
is the
horizontal
synchronizing
signal.
•
Since
the
image drawing
process
is
automatically interrupted
in the
dynamic
RAM
mode
the
refresh
address
is
output during
the
HSYNC period.
It can
also
be
used
as the
refresh
timing signal.
•
Refresh
is
accomplished
by
suppressing
the CAS
signal
derived from
the RAS
signal
in the
external
circuit when
the
HSYC
is at h gh
lebel
(Horizontal Synchronous
-
Refresh
timing)
Establishes
one of
following
two
modes,
depending
on
whether
the GDC is
operated
by the
master
or the
slave.
1.
When
the
master
is
operational:
sends
out the
vertical synchronizing signal.
2.
When
the
slave
is
operational
: The
synchronizing
signal
generation counter
is
initialized
by a
high
level
input.
Erase
signal
output
is
issued
at the
following
times (blanking
signal):
1.
Horizontal flyback period.
2.
Vertical flyback period
3.
Period from
the
execution
of the
SYNC
SET
command
to the
execution
of the
DISP START
command.
Memory
control
signal
sent
to the
image
memory from
the
GDC,
• In the
dynamic
RAM
mode,
it is
used
as the
reference
signal
of
RAS. When
at
high level, used
as
the
timing
signal
by
which
the
address
signal
is
latched.
(Row Address Strobe)
DMA
request
output
which
is
connected
with
the DRQ
input
of the DMA
controller
is
output
by the
following
two
commands'
1.
DREQE (DMA request write):
CPU
memory
to
image
memory.
2.
DREQR (DMA
request
read).
Image memory
to CPU
memory.
It
will
be
continuously
output
until
the DMA
transfer
word/byte number
set by the
VECTW
(vector
write)
command
becomes zero.(DMA
Request)
Signal
supplied
from
the DMA
controller that
is
subsequently decoded
by the GDC as the
read
or
write signal
during
DMA.(DMA Acknowledge)
In the
external circuit
RD is
combined with
the
chip
select
signal
(CS).
And is
used when
the CPU
reads
from
the GDC
either
data
or
status
flag
and the
signal
DACK.
(Read
strobe)
In the
external
circuit
WR is
combined
with
the
chip
select
signal.
And is
used when
the CPU
writes
to the GDC
either
a
command
or
parameter
and the
signal DACK.
(Write
strobe)
Normally, connected
with
the
address
line
and is
used
TO
designate
data
type.
AO
RD WR
function
^Mode^'
0 0 1
READ STATUS FLAG
IN #70 IN #60
1
0 1
READ DATA
IN #71 IN #61
0 1 0
WRITE PARAMETER
OUT #70 OUT #60
1
1 0
WRITE COMMAND
OUT #71 OUT #61
GDC1 GDC2
(Address
Bus 0)
Bidirectional
data
bus
connected
to the
system
bus.
(Data
Bus
0-7)
0V
supply.
Light
pen
strobe
nput.
When
a
input
light
is
sensed
by the
light pen,
it
outputs
a
high
level
signal.
The CPU can
then
read
the
display
address
via the
LPENR
(Light
Pen
Read)
command.
Bidn
ectional
address/data
bus
connected
between
the
image memory
and the GDC on
which
address
and
data
are
sent
on the bus by
means
of
multiplexer
ALE
(Address
Latch
Enable)
is
drived from
the
RAS
output
in the
external
circu
t.
(Address/Data
bus
0-12)
M
Z
3500
Pin
No
35-37
38
39
40
Polar,
ty
Signal
Name
AD13ILCO)-
AD15ILC2)
A16
(LC3)
(AT~BTI
NK-CLC)
A17
(CSR)
(CSR-1MAGE)
Vcc
IN/OUT
IN/OUT
OUT
OUT
IN
Function
Provides
the
following functions
based
on the
operational mode
of the GDC
(graphic display
mode,
character
display mode
0,
character
display mode
1).
1.
In the
graphic display mode
and
character display mode
0:
Bidirectional
address/data
bus
2.
In the
character
display mode
1 :
Line counter
output
in
connected
to the
character
generator
ROM
or
graphic
RAM
address.
• In the
graphic
and
character display mode
0:
AD13~AD1
5.
• In the
character
display mode
1 :
LCO~LC1.
(Address
Data
bus 13 ~ 15)
(Line
Count
0-2)
Provides
the
following
functions
based
on the
operational mode
of the GDC
(graphic display mode.
0.
character
display
mode
1 ):
1.
Graphic display
mode:
Image memory address
output.
2.
Character
display mode
1 :
Line
counter
output.
3.
Character
display mode
0:
Attribute/blinking/timing
signal
and
external
line counter
clear
signal
(Address
16}
(Line
Count
3)
(Attribute
Blink
—
Clear Lire Counter)
Provides
the
following
functions
based
on the
operational mode
of the GDC
(graphic display mode,
character
display mode
0,
character display
mode
1):
1.
Graphic display mode: Image memory address
output.
2.
Character
display
mode
1 :
Cursor
display
output.
3.
Character
display mode
0:
Cursor
display
output,
character display
area
(graphic)
display
area
select
timing
signal.
(Address)
(Cursor)
(Cursor-image)
+
5V
supply.
-
-14
-
M
"
4 8 CG
Address
Select
Circuit
When
200
rasters
on
ASCII
in use
(only
the
high order
8
bytes
of 16
bytes
are set to low
level
I
ASCII C.G. Structure
»
I i r r
1020
10! 1-
leBytes
lOOh
ifiBytes
1000
01-1^
0020
001
t
a
Bytes
0018
0017
K
Bytes
(Hi
in
001 1
8
Bytes
0
Iftk
OKI
fc Bytes
ii i
=^=^
Character
Code
01
For
Model 3500
Character
Code
00
For
Model 3500
==
Code
01
For
Model
3200
'/
'///'
s/
/////^
'
Code
01 ',
' For x
,.
Model
3500:
Character
Code
00
For
Model
3200
/
Character
/i
Code
00 ',
' For <l
^Model
3500^
I
\
l'= I -
M'-O
•>
I
I
A3=l
f
\
1-0
*
1
\
i i
t
M
8x16
dot
>
Pattern
400
Rasters
8x8 Dot
>
Pattern
200
Rasters
i
in
i
ASCII
character
structure
of the 200
raster
CRT
ASCII character structure
of the 400
raster
CRT
[Circuit
description]
(Purpose)
The
character genrerator (CG)
incorporates
all
character
code^
used
by
the
200
raster video
display
unit
of the \X
3500
and by the 400
raster
video
display
unit
of the \X
3500
The CG
address
select
cirruit
is
therefore
used
to
select
those
modes
[Operational
description]
1
When
the 400
raster
CRT is in
use,
RA40
is set to
high
level
which
sets
A12 of the CG to
high
level
at all
times,
so
that
the CG
address
above 1000
is
selected
Also,
gate
(1)
opened
so
that
LC3 is
input
to
A3 of the CG At the
same
time,
gate
(3) is
opened
so
that
the
gate
of the
LS240
is
closed
every
16
bytes
2
When
the 200
raster
CRT is in
use,
RA40
is set
turned
to low
level
which
sets
A12 of the CG to low
level
continuously,
so
that
the CG
address
0000
OFFF
is
selected
Also,
gate
(2) is
opened
so
that
the
CPU
8 b ts
-
45-
MZ
3500
4-9.
VSYNC
0 40
Digit
From
1 80
Digu
(8255
PB7) CH48
SRES
(From
MMR)
40
digit. 16bu/word
80
digit,
8bit/word
Master
is GDC
40
digit, Sbit'word
Master
is GDC 1
80
digit,
16bit/word
Master
is
GDC-2
[Circuit
description]
When
more than
two
UPD7220 GDC's
are to be
operated
in
parallel,
one
must
be
assigned
to the
master
and the
other
to the
slave
in
order
to
mantain synchronous display
timing.
The
master
and the
slave
are
determined
according
to the
table below.
The
above
circuit
shoud
be
used
to
compare
with
the
table
description.
""~~~-~^GDC-1
(character)
GDC-2
(graphic)"""
^^^
Without
VRAM
PWB
8-bit
structure
[0816=0)
(48KB,
200
raster)
16-bit
structure
[0816=1]
(4896KB,
400
rasters)
CH48
= 0 40
digit
GDC1 (character)
is
the
master.
GDC1
GDC1
CH48
= 1 80
digit
GDC 1
GDC 1
GDC2 (Graphic)
The
master
GDC
must
be set as
indicated
above.
[Oprational example]
If it was set to 80
digit,
16
bit/word
mode
SRES
will
be
0
when CH48
= 1,
0816
= 1
when
not in the
reset
condi-
tion.
These
signals
are
supplied
to
terminal
A
(weight
1),
B
(weight
2), and G
(gate),
and set
terminal
Y3 of the
decoder
1C
LS139
to
"0",
so
that
the
YSYNC
output
of
the
GDC2
is
input
to
terminal
EX
SYNC
of the
GDC2.
-
46-
MZ3500
4-10. Character
VRAM
select
circuit
The
signal
BLNK
is
used
to
address
the
ASCII
RAM
within
address
area
of
0000-07FF
in
transferring
the
display
data
from
the
VRAM
to the CG.
Lov
0
*/
when
300^07FF
6 1 1 6(
2K*8)
ASCB
CS
V-RAM
*0000
-07PF
2114(!Kx4)
First
half
of
attribute
2114(1K*4)
Latter half
of
attribute
*0000
-03FF
#0400
-07FF
#0000
-07FF
BL'SC
BLNK
Erase
signal
H-SYNC
TT_
TTJ
Period
that
the GDC is
enabled
to
read/write
and
draw graphic data.
BLANK
[Circuit
description]
With
respect
to
GCD1,
the
assignment
during read/write
of the
character VIDEO-ROM
is per the
table below.
The
character
VRAM
select
circuit
is
provided.
Jo
accomplish
this
function.
6
I 1 6 >
2K»8
)
ASL C
V-KAM
Latter
half
of
attribute
First
half
of
attribute
t
ARIO
= H1
T
AK10
= Low
*07FF
*0400
#03KF
toooo
8bil
-
47
-
MZ3500
4-12. Read/write
from
the
Z-80
to
V-RAM
Read/write
of the
Model
3500
V-RAM
is
done
via the
UPD7220GDC. There
are two
methods used
to
read/write
data.
The
method
(1) is
used
for the
model
3500.
(1)
Read/write
via the 16
byte FIFO.
(2)
Read/write
of
V-RAM
in the DMA
mode
without
intervention
of the
FIFO.
(Outline
of the
read/write data
via the
FIFO;
NO
YES
Set
GDC
command
code
YES
Set
parameter
for the
command
YES
Set
parameter
for the
command.
I
Method
used
to
give
a
command
to the
GDC.
Command
must
be
given
to the GDC in the
same
manner.
On
next
page
is the
program
of the
above
flowchart.
-
48-
MZ3500
(Subroutine
lo
send
command
and
parameter
to the GDC
via
the
FIFO)
HL reg —
First
address
of the
command code
oarametpr
B. reg —
Q'ty
of
data.
C
reg - 60H
(graphic GDC),
70H
(character GDC)
>
FIFO
Empty?
;
COMMAND
—• GDC
;
Return
if
parameter
not
sent.
f
FIFO
Empty?
;
PARAMETER
—
GDC
;
Return when
all
parameters
were
sent.
RET
Example
of
graphic
drawing
by GDC
1)
Dot
display
0000
0028
0001
0027
VRAM
16-bit
structure
Example
to
display
a dot on the
fourth
bit of the
address
CSRW
C 49H
-COMMAND
CODE
P1
01H — Low
order
one
byte
of the ab-
solute
address
P2
OOH —
High
order
one
byte
of thp ah
solute
address
P3
30H - Dot
address
(dAD)
WRITE
C 23H -
COMMAND
CODE
VECTE
C 6CH -
COMMAND CODE
-
49-
M23500
[Explanation]
C-COMMAND
CODE
) To A
p_
PARAMETER
'
Display
dot, specify
the
display
address
of the
VRAM
and
the dot
address.
Set the
command
code
of the SET
mode
(set
mode
plus CLEAR, REPLACE,
and
COMPLEMENT
modes
using
"WRITE",
and
specify
to
start
with
"VECTE".
Dot
address
is
structured
on the
screen
in the
following
manner.
Address 0001
dAD=
0 1 2 3 1 5 6 7 8 9 10 11 12 13 14 15
[Dot
display
program example-1]
LD
LD
INC
LD
INC
LD
INC
LD
INC
LD
INC
LD
HL
(HL)
L
(HL)
L
(HL)
L
(HL)
L
(HL)
L
(HL)
.5000H
.
49H
,01H
,
OOH
30H
,23H
,
6CH
CSRWdata
5000
— 49 H
5001
— 01 H
5002
— 00 H
5003
— 30 H
5004
— 23 H }
WRITE
data
5005
— 6CH }
VECTE
data
LD
LD
LD
C
,60H
B ,4H
HL
,5000H
C — BOH
(port
address
during
graphic draw)
B
-
Byte
size CSRW data
HL
- Top
address
of the
CSRW data
CALL
GDC
Command,
parameter
of
CSRW
-
GDC
LD
LD
LD
C
,60H
B
, 1H
HL
.5004H
B
-
Byte
size
of the
WRITE data
HL
- Top
address
of the
WRITE data
CALL
GDC
Command,
parameter
of
WRITE
- GDC
LD
LD
LD
C
, 60H
B , 1H
HL
.5005H
B —
Byte
number
of the
VECTE
data
HL
- Top
address
of the
VECTE data
CALL
GDC
;
Command,
parameter
of the
VECTE
- GDC
M
7.
3500
2)
Straight
line drawing
00000
0028
0001
0027
0050
VRAM
16 bit
structure
Example
to
draw
a
straight
line
from
(X, Y) = (3, 1) to (X,
Y)
=
(635,
1).
Coordinates must
be
changed
to
absolute
addresses.
(3,
1) -
absolute
address
=
0028H
Dot
address
= 2H
Displacement between
two
points
when
the
line draw
direction
is OA (to the
right):
X =
635-3
= 632
(=278H),
Y=0
Whereas.
CSRW
TEXTW
VECTW
C 49H
PI
28H
P2 OOH
P3
20H
C
PI
78H
FF
P2 FF
HAD I, , H
dAU
Kind
of
line
(solid
line)
C
PI
P2
P3
P4
P5
P6
P7
P8
P9
4CH
OAH
78H
02H
88H
H>H
1
OH
FBH
OOH
OOH
}
Drawing direction
}
\ 1 AX I
1
f
2 ! AY 1 - I A x I
1
>
2 1 AY 1 -2 1 AX I
1
2 i AY !
WRITE
C 23H
VECTE
C 6CH
[Explanation]
Specify
the
kind
of
line
by
TEXTW, using
C for
command
code
and P for
parameter,
and
specify
the
line drawing
direction
using VECTW
and
above
four
values
using
X and
Y. The
rest
will
be
same
the dot
display
It is
also
possible
to
display
a dot
using
the
line drawing method
for any
line
drawing
direction
using
X = Y = 0.
Example
2:
CE330S (light
passing
through
the
notch
is
sensed
and
decoded
as
write
protect)
(Double
side,
Double density)
Write
enabled
Front
side
O
0
Light
is
interrupted
by the
label
Write
protected
Front
side
o
0
-r-
nhibit notch
Two
types
of
write
protection
are
used
and
attention
must bepaid
to the
presience
of the
label
because
it may
cause
a
wrong result
if the
label
is
used
improperly.
5)
Media recording methods
Two
recording methode
are
used:
• FM
method
(Single density)
This
method
is
called
the
freqency modulation (FM)
1
0 0
n n n n
C D C D C D C
or
double
frequency
(DF).
Clock
and
data
are
written
on
the
media
which
requires
that
a
clock
bit
that
precede
the
data.
I
fL_JL_fl
0
JL
(C:
clock,
D:
data)
Waveforms
of
data
written
or
read
in the FM
mode
are
shown
below.
r*-
Write
data
(WD)
Write
current
Residual magnetic
flux
on the
media
y
Differentiate
^
waveform
Shaped
waveform
Read
data
(RD)
T_J
—
•«—
\
_
fi_i
.—
>
9
US
4
D
ILJ
1
L_J
—
*•
/
J
r\
i
—
i
i_
k
C
I) C D C
n
n n
0
^v
n
0
»•
^s
r/
n
l
—
i
.«—
~\
\
vy
i i
fl_J
D
ILJ
1
1
—
»•
J
r\
rn
n_j
C
D C D
i n i
0
+
"^
X
n
0
•\
y
f-'
LJ
>
Wrote
Read
Write
current:
The
write
data
is
input
to the
flipflop
and
is
inverted
each
time
a
pulse
is
received
to
change
the
direction
of
writing current.
Read
waveform:
The
peak
of the
waveform
is
detected
at
a
change
of
magnetic
flux.
The
waveform
is
than
shaped
to
obtain
read
data identic
it
>.<_•
tlirf
write
data.
Data
cycle
will
be
4/^s.
MZ3500
o MFM
method (double density)
The
MFM
method writes data
on the
basis
of the
condi
tion
metntioned
below,
and it
yields
a
data density
two
Input
data
Write
data
times
the
data density
of the MFM
mode (The
unneceb
sary
clock
pulse
is
eliminated using this method
)
(Condition) Clock
is
written
only
when there
is no
data
0 £ 0 £ 0 1 0
•'•>
n
\ /\ /\
X"V
/\ /
n n nnn n
C C (C) I) (C) '(_
0111
n
n n
'
VnVn
n nV
[ci
|D (ci |u ici ,i> ci
<
i i
0
1 0^0
n
nnn7
n/
(0 ;i> (c) (O
i
t
\
Data
that follows Data that
precedes
The
clock pulse
(Ci
will
be
eliminated
in
above illustra
tion
as
there
is no
data preceding
or
following
the
clock
Because
the
data rate
is
2/Js
for
this
method,
it is
possible
to
obtain
twice
the
density
of the FM
method
NOTE
Three
types
of
write data cycl»-
(2f
~>t"> SA*S)
are
used
The
read/write
waveform
is
identical
to FM
method
6)
Media
recording
format
Media
is
formatted
according
to the IBM
format
For
Double
side media, data
is
written
on the
front
side
(head-1)
and the
reverse
side (head-00)
Floppy
disk
Tracks, consists
of 40
tracks,
00-39.
(May also
be
called
cylinders)
Sector.
01-16
Recording density:
256
bytes/sector
M
7
3500
Shown
below
is an
enlarged
view
of
data format
sequence
Writing
starts
as
soon
as the
index hole comes
through
the
index
detect hole
1
Track
Sector
01
Sector
02
Firnl
^p
DATA
DATA
IU
II)
DA I A
<[
t
INDEX
\M
Start
point
Hatched
portion
is
a
recording
gap
ID
AM
TT
HH
SS
DL
CRC
CRC
DATA
AM
51
DATA
CRC
CRC
ID
section
CRC
check
code
Size
of
data
section
(00)
H — 128
bytes
(01)
H — 256
bytes
Sector
number
Head
number
(00)
H -»
Head
0
(side
0)
(01)
H -*
Head
1
(side
1)
•
Track
number
•
ID
address
mark
which
begins
the ID
section
Data
Data
section
CRC
check
code
'
Data
address
mark
(or
delete
address
mark)
NOTE
The
delete
address
mark
is
written
to
indicate
invalid
data
It is
often
written
on
a
new
floppy
disk
as
there
are
no
valid
data
on it
7)
Formatting
To
write
the
above
format
(ID
section, data section, gap)
on an
entire
surface
of a new
floppy
disk
is
called
formatting
Note
1
Formatting
may
also
be
called
initialization.
The
word
"initialize"
is
also used
as a
software
term
to
clear
the
data section
or to
partition
data area. Keep
the
difference
between
formatting
and
initializing
in
mind.
Note
2
Unless
formatting
has
been
done
on a
properly
adjusted
floppy
disk drive
unit,
an
erroe
may
occur
on
another
floppy
disk drive
unit
8)
Data write procedure
Described
next
is the
procedure
to
write
data
on the FD.
(1)
The
head
is
moved over
the
track
to be
written.
(2)
(3)
(4)
The
head
is
loaded
ID
section
is
read
and
repeated
until
the
desired
section
is
reached
When
the
desired
ID
section
is
found,
data
is
written
on
that
area
(DATA
AM is
also
written
)
(5)
The
data
thus written
is now
checked
if it was
written correctly
(read
after
write)
The
respective
ID
section
is
read while
the
media
makes
a
full
turn
(6)
The
sector
of the
identical
ID is
read
and
verified
with
the
write
data
Because
of thr pad
dftei
Ar.'e
capability
the
possibility
of an
error
in the
written
data
is
quite
low
9)
Data
read
procedure
Described
next
is the
procedure
to
read data
from
the
FD.
(1)
The
head
is
moved over
the
track
tu -^ i ead
(2) The
head
is
loaded
(3) The ID
section
is
read
and
repeated
until
the
desired
sector
is
reached
(4)
When
the
identical
IDsection
is
found,
the
<~i-m
IP
that
data section
is
then
read
M
2
3500
FDC
(UPD765)
UPD765
pin
configuration (top
view)
UPD765
block
diagram
RLSt
IQ »•
RDO
»
WRO »•
CSO
>
AOO
>
DBOo-«
»
DB1CX
»
DB2O4
K
DB304
».
DB4
O< ft-
DB5CX
— *
DB6O4
—
t-
DB7O4
—
*•
DRQcn
DACKO
*
TCO
>
INDEXO
»•
INT04
*0 »•
GNDO
1
^
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
OVcc
KDRW/SEEK
K3LCT/DIR
*O
FLTR/STEP
K3HDLD
«
0
READY
4 O
WPRX/2S1DE
4 O
FLT/TRKO
K> PSO
K>
PS1
K>
WDATA
>0
USO
K5 US1
K>
SIDE
K> MFM
NDWE
>0
SYNC
•<
O
RDATA
•«
— o
WINDOW
4 0
WCLK
A-N.
No/
RD-
WR—K
READ/
WRITE/
DUA
CONTROL
L.OGIC
SER f AL
1
Mf
KFACfc
DR 1 VE
1NTERFACE
CONTMO1
LER
I
SPUT
POKT
- » I KT
- 1 M)t X
- Fl T T
RESET
RD
WR
CS
AO
DBO-7
DRQ
DACK
TC
INDEX
INT
0
GND
WCLK
WINDOW
RDATA
SYNC
WE
:
Reset
:
Read
:
Write
:
Chip Select
:AO
:
Data
Bus
:
DMA
Request
:
DMA
Acknowledge
:
Terminal Count
:
Index
:
Interrupt
Request
:
Clock
:
Ground
:
Write Clock
:
Data
Window
:
Read
Data
:
VFO
Synchronize
:
Write Enable
MFM
SIDE
USO.
1
WDATA
PSO,
1
FLT
TRKO
WPRT
2
SIDE
READY
HOLD
FLTR
STEP
LCT
DIR
RW/SEEK
:
MFM
Mode
:
Side
Select
:
Unit
Select
:
Write Data
:
Pre
Shift
:
Fault
:
Track
0
:
Write Protected
:
Two
Side
:
Ready
:
Head
Load
:
Fault
Reset
:
Step
:
Low
Current
:
Direction
:
Read
Write/Seek
-
57
-
MZ3500
UPD765
signal
description
Pin
No.
40
20
19
1
4
13-6
3
2
18
5
14
15
29,28
26
24
39
36
27
38
37
35
34
17
33
16
30
25
21
Signal
name
Vcc
GND
0
RESET
CS
DB7
~ DBO
WR
RD
INT
AO
DRQ
DACK
USD,
1
MFM
SYNC
RW/SEEK
HOLD
SIDE
LCT/DIR
FLTR/STEP
READY
WPRT/2
SIDE
INDEX
FLT/TRKO
TC
WDATA
WE
WCLK
I/O
-
-
I
1
1
I/O
'
1
o
1
o
1
0
o
o
o
0
0
0
o
1
1
'
1
1
0
o
1
Function
+5V
0V i
Single phase,
TTL
level
clock
Set
the FDC
into
an
idle
state,
and all
drive
unit
interface
outputs,
except
PSO,
1 , and
WDATA
(don't
care),
are set to low
level
In
addition,
INT and DRW
outputs
are set to low
level
DB
goes
into
an
input
state.
Validates
RD and WR
signals
Bidirectional,
tri-state data
bus
Control
signal
to
write
data
to the FDC via the
data
bus
Control
signal
to
read data
from
the FDC via the
data
bus
The
signal used
to
indicate
a
service
request
from
the FDC It is
issued
at
every
byte
in the
non-
DMA
mode,
or
upon
completion
execution
of a
command
in the DMA
mode
The
signal used
to
select
the
status
register
or
data
register
of the FDC for
access
via the
data
bus. When
0, it
selects
the
status
register
When
1. it
selects
the
data
register.
FDC
to
memory
data transfer request signal
in the DMA
mode
The
signal that indicates
use of the DMA
cycle
During
the DMA
cycle,
it
functions identically
toCS.
Drive
unit
select signal,
with
which
up to
four drive units
can be
selected.
The
signal used
to
designate
the
operation mode
of the VFO
circuit When
0, the MFM
mode
is
assigned.
When
1, the FM
mode
is
assigned
The
signal
used
to
designate
the
operation
mode
of the VFO
circuit
When
1, it
permits
reading
operation.
When
0, it
prohibits
reading operation
Signal
used
to
discriminate
the
read/write signal
from
the
seek
signal
that
used
for
drive
unit
interfacing
signal. When
0, it
indicates
RW
When
1 , it
indicates
Signal used
to
load
the
read/write head
Signal used
to
select head
#0 and
head
#1 for the
double-sided floppy disk drive
unit.
When
0,
it
selects head
0.
When
1, it
selects
head
1.
When
the
RW/seek signal
is
operating
as RW, the
signal
works
as LCT
which indicates
that
the
read/write
head
is
selecting
the
cylinder
above
43.
When
the
RW/SEEK
is
operating
as
SEEK,
it
works
as DIR
which indicate
seek
direction When
0.
seek
is
made towards outer side
When
1,
seek
is
made towards inner
side
When
the
RW/SEEK signal functions
as RW, it
works
as F LTR
which
resets
any
fault
condition
as
the
seek
step signal.
Signal used
to
indicate
that
the
drive
unit
is
ready
for
operation
When
the
RW/SEEK signal
is
operating
as RW, it
function
as
WPRT which indicates
that
the
drive
unit
or the
floppy
disk
is
write protected. When
the
RW/SEEK
is
function
as the
SEEK signal
produces
2
SIDE
which
indicates that
a
double
sided media
is in
use.
Signal
to
indicate
the
physical start
point
of the
track.
When
the
RW/SEEK signal
is
operating
as RW. it
works
as FLT
which
indicates
that
the
drive
unit
is in a
fault
condition.
When
the
RW/SEEK
is
operating
as
SEEK,
it
works
as
TRKO
which
indicates
that
the
read/write head
is on
cylinder
0.
Signal
used
to
indicate
the
termination
of a
read
or
write
operation
Data
written
on the
floppy
disk
consists
of
clock bits
and
data
bits
Signal
to
indicate write
enable
to the
drive
unit
Data
write
timing
signal
which
is
250kHz
in the FM
mode
or
500kHz
in the MFM
mode
-
58-
MZ350C
P,n
No
32. 31
23
22
Signal
name
PSO.
1
RDATA
WINDOW
I/O
O
1
'
Function
Signal
used
to
obtain
tir
the
table
be
to
either
advance
or
delay
the
write
data
in
writi
rung
adjustment
for
reading.
The
WDATA
signal
ow
PSO
0
0
1
1
PS1
0
1
0
1
FM
Not
changed
-
-
-
MFM
Not
changed
LATE
225~250ns
EARLY
225~250ns
-
ng
under
the MFM
mode,
is
controlled
as
shown
in
Read
data
from
the
drive
unit
consists
of
clock
bits
and
data
bits.
Signal
created
in the VFO
circuit
which
is
used
to
sample
RDATA.
Phase
syncroni^i
carried
out in the FDC for
RDATA
data
bits
and
WINDOW.
5-5. Data recording
method
There
are two
ways
of
recording data;
FM
recording
method
and MFM
recording
method.
1)
MF
recording
method
(1)
Clock
bit
indicates
a bit
cell.
(2)
Data
bit is
placed
in a
middle
of a bit
cell. (See Fig.
I.
2)
MFM
recording method
(1)
Data
bit is
placed
in a
middle
of a bit
cell.
(2)
When
the
data
bit is
"0",
a
clock
bit is
placed before
the
current
bit
cell. (See Fig.
1)
JUULJUULJLJlJLJLnJl
—
1
n
i
i
!
n
i
i
i
i
0
| ,
v
i
! !
i i
r-JLJLJ
i !
i i
0
| 0 | 0
' '
1
o
•__ —1
n
1
•
(MFM recording method)
As
seen
from
the
above
illustration,
bit
density
of the MFM
recording method
is
twice
the FM
recording
method.
In
other words,
data
density
of the MFM
recording method
doubles that
of the FM
recording
method.
For the
Model
3500,
only
side
0 of
track
0
(128 bytes/sector)
is
written
in the FM
mode
and
rest
of
other
tracks
are
recorded
in the MFM
mode.
5-6.
I/O
port
in the MFD
interface
I/O
port
used
in the MFD
interface
is as
follows.
IOMF#F9-AO
IOMF#F8-AO
D-BUS
D7
D6
D5
D4
D3
1)2
1)1
DO
U2
Dl
DO
I/O
OUT
OUT
IN
DACK
ME
SCTRL
TC
TRIG
SEL3
SKI.
2
SEL1
SELO
M
. ON
I
NDEX
DRQ
Used
for
data transfer between
the CPU and the
FDC.
INT
from
the FDC is
output
enabled
on
INTFD.
FDD
select
signal
output
is
enabled.
TC
to
FDC.
Trigger
(motor
on) of the
timer (555)
Selects
FDD 3
Selects
FDD 2
Selects
FDD 1
Selects
FDDO
ON/OFF state
of the
motor
INDEX
signal
from
the
motor
DRO
from
the
FDC.
-
59-
In the
case
of the MFM
method, need
to
trace
cycle
fluc-
tuation
is
further
increased,
as a
peak
shift
is apt to
occur
because
there
are
three
write
data
cycles.
(Peak
shift).
Data
read
cycles
fluctuate
as the
flux
change
point
is
moved
forwards
or
backwards.
Write
pulse
Polarity
inversion
Read
waveform
MZ
3500
Advanced
peak
shift
-
Regenerated
pulse
H
*—
Delayed
peak
shift
Cb)
{VFO
circuit):
Variable frequency oscillator
Polarity
inversion
f~J
Polarity
inversion
Write
pulse
J
Read
waveform
6.0
40 20 0 20 40 60
(a)
j
I I
Advanced
peak
shift
—-| t— —•) j*-
Delayed
peak
shift
(c)
When
the
output
waveform
is
observed after
writing
a
single
pluse
on the
floppy
disk,
the
waveform
show
in (a)
appears.
Shown
in (b) is two
pluses
of
4jis
interval.
Deviation
in the
peak
point
is
called
peak
shift.
Since pluse
intervals
of the MFD in
actual
operation
are
4ns, 6/JS,
and
8/^s,
the
largest
shift
takes place
when
a
pluse appears 8/Js
before
or
after
4/JS,
as
shown
in
(c).
5-10.
VFO
circuit
1)
Purpose
String
of
data
pulses
from
the
FDD.
Data
window
String
of
separate
data
n
n
Data
from
the
clock
or
data
portion
must
be
differentiated
when
read
from
the
FDD.
For
this
purpose
a
window
pulse
is
used.
In
order
to
increase read
tolerance,
the VFO
circuit
carses
the
window
to
trace phase
changes
in the
read
data
that
take place
during
a
floppy
disk drive
motor
speed
change.
-
61
-
MZ3500
2) VFO
circuit configuration
READ
DATA"
—
»
h,
Phase
detector
k.
Filter
amplifier
^
Window
Data
separator
SEPARATED DATA
SEPARATED CLOCK
The VFO
circuit
has the
following capabilities.
(1)
Two
modes:
MFM and FM.
(2)
The VFO
circuit
operation
is
suspended
during
the
SYNC
field located before
the ID
field
and
data
field.
(3)
After suspention,
the VFO
circuit
will
synchronize
with
the
read
data
(timing
is
affected
by a
speed
change
in the
FDD). Fluctuations
in an
individual
bit
that
may be
seen
(peak
shift
are
ignored.
VFO
circuit
+5V
RtAD
DATA
-62-
MFM
Mode
AlMHz
_rLTLJT_r
B)QA)
1_
Nomal
STD
Eary
n
J~L
Delay
©
MZ3500
FM
mode timing chart
A 4M
B(QA)
C(QB)
D(QC)
WINDOW
E
F
L
j 1 [
1
1
1 1 1 1
1
1 1
Normal
O
P
Advanced
F
L
Q
O
P
Delayed
L
K
Q
O
P
Does
not
trace
± I
I
o
*#-
.2
73
QJ
2
,—
^
UJ
s
..
5
S3
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density
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VO
10
w
•~"
••
Reverse
side
M/asoo
Track
0,
sector
1
information
(SBACIS)
(Fig
1)
AA ( 1
/
i
m
media
L'
00
00
M
HF
02
c
00
IM
No,
7
1 1 | 1 i 1 I 'T
—
I
0 4 i 0 0 ! 48 '. OO1 4 8 ! 041 02 '< Oo! 01 ! 01 '
i i i ' i > i > * i
I 1 1 1 1 i I . ; , ,
1
J v ' 1 r u U S I IM'
SJ"L
tor N
of
sectors
1
Start address
I
BOOT
SUB
IOCS
r
;
10
02
0 1
01
01
10 j FF
i
i ,
No
of
Track
SIDE
Sector
N No of END
sectors
sectors
f
0 .
Single
density,
other
than
front
side,
track
0.
1 .
Double
density,
other
than
front
side,
track
0.
.
Side
0
(front
side)
1
Side
1
(reverse
side)
No of
data
transfers
INT=[IOCScapacity/1k]
+1
SIDE
=
0
track
8
sector
* 78 F
Volume
name
FF
FF
10 11
+
Tr
18
FI-
FF|
t
IF
FF
FF
Diskette
Type
3Ck
No 2 m
SH/DD(M,ni)
Track
No 1
Error
Mep
(Bad
Treck)
20 SC
For
FLOAD
command
<-C
DH/DD(M.m)
3D 7F
FF FF
I
Fail name
(8
bytes) Expander
Volume
name
cc M
A,r,Ar.
.4 (3
bytes)
(8
bytes)
FF
No
ALOAD
command
80
File specification
only
01
With operand
Drive
NO
Channel
A
(<•)
B
( I )
1
'
1 1
All "F"
when
ALOAD
command
is
not on
ALOAD
Status
line
No
label
(8
bytes)
(Sbytes)
Contents
of X
register
When used
for the
line
number
(when line
No 1 23)
These three
bytes
are in
effect
34
35 36
3b>tesfj$!l
00 01 23
When used
for a
label (Wight bytes
are in
effect
andreseare)
34
3C
A
B C
I)
f
? 7
F
-
66
-
o Map
information
0
track
9
sector
/- x
/ 1
/ 2
/
3
/
22
23
24
75
76
77
\
\ 126
\ 127
\128
/ 1 7H
/ &0H
1
FFH
\ FFH
J
4CH
FFH
1
FFH
iy 7 EH
/ FFH
1
^
FEH
FFH
FFH
25
M7
350?
0
track
10
sector
129
130
131
151
152
153
29
FFH
I
71!
FFH
FFH
FFH
128
blocks
are
controlled
by one
sector.
OOH-7FH
80H:
End of
link
FEH:
Links
to
next
map,
and
the
starting
block
number.
Indicates
the
byte
position
•
from
the top of
directory.
30
31
32
01
00
02
01
FF
FF
FF
FF
H
MAPNa
Block
NO
Starting block number (directory)
-
67
-
MZ3500
o
Block number allocation
The
program
and
data
areas
are
located
after
Track
2
1
block
= 2K
bytes
(8
sector)
(Double side)
2Kx
152 =
304K
Each
track
is
blocked
in the
following
manner:
1
sector
3
5
13
15
sector
1
block
2 sec tor '
4
6
14
16
sector
1
block
o
Track
1,
Sector
1
information
(CP/M)
0
5
(Single
sided)
track
2
3
I
38
39
Block
No
Front
BO
Bl
B4
B5
B144
6145
B148
B149
Reverse
B2
B3
B6
B7
B146
B147
B150
B151
track
2
3
I
38
39
Block
No
Front
BO
Bl
B2
B3
B72
B73
B74
B75
2KX
76=152K
10
15
AA
TRACK
SIDE
SECTOR
N
SECTO
^1
NUM
BER
i
i
i
i
i
i
PATAT
*ANSF|
-TRACK
ER
NU
1KAt*
MBER
1
SIDE
SECTOR
N
t
t
......
Drive
unit
specification
Represents
the
system
media
(•
Load
address
Start
address
BOOT
20
SUB-IOCS
50
51
SECTO
R
NUM
BER
TRACK
SECTO
R
NUM
BER
SECTO|~
I
R
NUM
T?F%!
\
BER j j
Indicates
the
end
SIDE
=
.
_ 0
Single density
(front,
Track
0)
1
Double density (other
than
front.
Track
0)
0
Side
0
(front)
1
Side
1
(reverse)
Nosof
data
transfers
= INT
[IOCS capacity/1
K] + 1
• Sub
IOCS
can be
divided
into
either blocks
If
divided
to
less
than eight blocks,
the
block that follows
-
68-
MZS500
6.
R232C
INTERFACE
6-1. General specification
Input/output
format
No of
channels
Code used
Baud
rate
Transmission
system
Synchronization
method
Communication control
procedure
Data
format
LSI
used
RS-232C
bit
serial
input/output
1
channel
JIS
7-channel/JIS
8
channel
110 to
9600
bits/sec
Half-duplex
Start-stop
Non-procedure
Stop
bif
1/1.5/2,
with
or
without
even
or odd
parity.
8251
AC
or8253C-5
(Programmable
interval Timer)
6-2. Data transmission
format
2°
21 22 23 24 25 26
7-bit,
with
parity
v
„ _
i
\
j
v__^___/
Start
bit
Data
bit (7
bits)
Parity
bit
Stop
bit (1 or 2
bits)
7-bit,
without
parity
V
XV X V X '
Start
bit
Data
bit (7
bits)
Stop
bit
8-bit
with parity
V
•
w •
'
V
^ ^ _
Start
bit
Data
bit (8
bits)Parity
bit
Stop
bit (1 or 2
bits)
8-bit,
without
parity
v
,
Tr
y Y
Start
bit
Data
bit (8
bits)
Stop
bit (1 or 2 bit
Example:
7-bits,
even
parity,
1
stop
bit
Start
bit
Stop
bit of
preceding
data
7-bit
data
(26H)
Parity
bit
Start
bit of
succeeding
data
Stop
bit
-
7)
-
MZ3500
6-3. Block diagram
of the
interface
Control
signalPeripheral
6-4. System switch
functions
SW5
SW6
SW7
ON
Causes
an
error when
the
ER
signal
is low or
open
during data
output.
Always
high when power
is
on
to the
main
unit.
Causes
on
error when
the
PO
signal
is
high
during
data
output.
OFF
ER
signal
is
disabled.
The CD
signal
is set
high
while
data
output,
but
would
not be set
high
when
the
echo-back
function
is
selected
for
the
host
computer.
Polarity
is
inverted.
6-5.
8251AC
controls
There
are two
control
words
for the
8251
AC.
(1)
Mode instruction: Defining
general
operational
para-
meters,
such
as
unit,
stop bit, etc.
(2)
Command instruction: Defining
status
words
used
for
actual
operation,
such
as
send/receive enable, etc.
1)
Definition
of
generation operational parameters
•
Baud rate
•
Character
size
•
Even/odd/off parity
assignment
••Stop
bit
size
"Corresponds
to
channel command
of
BASIC.
c
START
8251AC
internal
reset
8251AC
mode
instruction
-
72
-
MZ3500
2)
Data
output control
SKNU
Command instruction
(KTS,RXEN,TXEN)
»-
8251
AC
8251
AC
"L"->KTS
Set
counter (200ms)
Stop
Output data
to
8251AC
ERROR
101
The
8251 send
data
when
CTS
goes
low.
The
8251
AC
would
not
output,
unlessv
CTS
goes
low. Therefore,
the
state
of \
CTS
will
be
checked when
the
buffer
I
.becomes
empty.
/
ERROR
101
-
73
-
M/3SOO
3)
Data
input
control
RCV
Commandnstruction
(
ER.RX
DISLN)
8251
AC
8251
AC
/Error
reset
\
\Data
input
disable/
Read
one
data
/Clears
the
data before
N
Vthe
start
of the
receive
command
/
Command
instruction
(RXEN,UTR,TXEN)
-
8251
AC
8251
AC
, N
/
Data
input
enabled
(
Data
output
enabled (echo-back,
selected)
\" L
"-»DTR
Waits
for NMI by
the
RXRDY signal
Resets
error
by
setin
DTR
high
Command
instruction
( tK >
8251
AC
ERROR
ERROR
-
74
-
MZ
3500
6-6. 8253
Controls
Baud
rate
of
this
interface
will
be
determined
by the
clock
output
of the
8253.
The
8251
is
configured such
that
its
baud
rate
is
1/16
of the
input
clock
and has the
following
relation
between
the
8253
output
clock
and the
baud
rate:
8253
input
frequency:
2457.6kHz
8253
Mode set: Mode 3(rec'angle waveform
rate
generator)
Control
signals
Baud
rale
1
1 0 .t -
300
600
1
200
2400
4800
9600
8253
Output
frequency
1760Hz
4800
9600
1
9200
38400
76800
153600
8253
Parameter
1
3 9 6.3 6
51 2
256
128
64
32
1
6
Signal
name
Transmission
enabled
Data
set
ready
Carrier
detect
Ready
Equipment
ready
Paper
out
Symbol
CS
DR
CD
READY
ER
PO
IN/OUT
-*
Peripheral
—
Peripheral
—
Peripheral
—
Peripheral
«-
Peripheral
<-
Peripheral
Function
When
high,
data
input from
a
peripheral
is
enabled.
When
low,
data
input from
a
peripheral
is
disabled.
Goes
high when power
is on to the
interface
unit.
(SW6-ON)
High
at all
times
when power
is on to the
interface
unit.
(SW6-OFF)
Goes
high only when data
is on
output.
Data
output from
the
interface
is
enabled.
(ON)
Data
is
output
from
the
interface.
(OFF)
Waits
for
data
output.
NOTE:
A
maximum
of two
bytes
are
output
after
the
signal
goes
from high
to low
state.
Indicates
that
the
peripheral
is
ready.
It
results
in an
error
if low or
open when data
is
sent
from
the
interface.
This
signal
will
be
invalidated when
the SW5 is
turned
off.
(SW7-ON)
Causes
an
error
if set
high during data
output.
(SW7-OFF)
Causes
an
error
if set low
during
data
output.
6-7.
Description
of
LSI's
1)
UPD8251AC
(Programmable
Communication
Interface)
The
UPD8251A
is a
USART (Universal Synchronous/
Asynchronous Receiver/Transmitter
that
was
specifical-
ly
designed
for
data
communication.
The
USART
receives
parallel data
from
the CPU and
converts
it
into
serial data
before
transmitting.
Also,
serial
data
is
received
from
an
external
circuit
and
trans-
ferred
to the CPU
after converting
it
into
parallel.
The
CPU
can
monitor
the
current
state
of the
USART
at
any
time
(data
transfer
error,
and
control
signal
of
,
SYNDETandTXEMPTY.
,-eatures
•
8080A/8085A
compatible
•
Synchronous/asychronous
operation
•
Synchronous operation
5
—
8
bits
character
Clock rate: baud
rate
x 1,
x16,
x64
BREAK
character
generation
Stop
bit:
1,
1.5,
2
bits
Error start
bit
detection
Automatic
break
detection
and
operation.
•
Baud rate:
DC
-
64K
baud
•
Full-duplex
Double
buffer
type transmitter/receiver
•
Error detect
Parity, overrun, framing
•
Input/output
TTL
compatible
•
N-channel
MOS
•
Single
+5V
supply
•
Single
phase
TTL
level
clock
•
28-pin,
plastic
DIP
•
Intel
8251A compatible
Pin
configuration (Top
View)
<28
»OD1
3?5
PORTS'
422-0
DSR
-i-2—XDTXEMPTY
3*12-0
CT3
SYNDET
BD
TXRDY
Block diagram
1)7-1)004
8 »
RESET
O »•
Data
bus
buffer
Read/
write
control
logic
*
Dsko
m
t
rscx
—
x:
k'l so* c
MOOhM
controller
8
8
^_
8
V
Internal
data
bus^
„«.
8
8
^
1
Transmission
t *
Transmissic
control
'
Reception
buffer
(
S -• P )
t
1
Receiver
control
>n
_
X>TXE
34
OTXC
HI)
-
75
-
M
Z
3500
DO~D7
Data
Bas
RXD
Receive
Data
(IN/OUT)
WR
Write
(IN)
RD
Read
(IN)
C/D
Control/Data
(IN/OUT)
CS
Chip
Select
(IN)
DSR
Data
Set
Ready
(IN)
DTR
Data
Terminal
Ready
(OUT)
RTS
Request
to
Send (OUT)
CTS
Clear
to
Send (IN)
TXRDY
.
Transmitter
Ready
(OUT)
TXC
Transmitter
Clock
(IN)
TXE
.
Transmitter
Empty
(OUT)
RXC
.
Receiver
Clock (IN)
SYNET/BD
:
SYNC Detect/Break Detect
(IN/OUT)
2)
UPD8253C-5 (Programmable
Interval
Timer)
The
UPD8253-5
is a
programmable
counter/timer
speci-
fically
designed
for the
8-bit
microcomputer
system.
It
consists
of
three
sets
of
16-bit
counters
that
operate
under
a
maximum counter rate
of
4MHz.
Timer
and six
operational modes
are
programmed
to be
used
for a
wide
range
of
microcomputer system
timing
control.
Features
•
Z-80 compatible
•
Three
sets
of
16-bit
counters
•
DC-4MHz
of
count
rate
•
Programmable
six
operational
modes
and
timer
duration
•
Choice
of
binary
counter/BCD
counter
•
N-channel MOS,
input/output
TTL
compatible
•
Single
+5V
supply,
24-pin
DIP
•
Intel 8253-5 compatible
Pin
configuration
(Top View)
.VCC
Block
diagram
UOO
wl —
»<:
AO
1
Al >
Data
bus
buffer
Read/
write
logic
c- ^
AA
v-v
^
Control
word
register
1
—
/" '
**w 1
Internal
£
VV
/«-
\r
-N
,V
Counter
# 0
_t
Counter
# 1
•«
t 1 KO
<l
C.MtO
'
*-"no
< C 1 K 1
< OA1 ^ 1
»-()l
I 1
t
A^S
S —
K]
Counter
# 2
t
*- Cl K2
«
GA1L2
KHT2
D7-DO
Data
Bus (8
bit)
CLKN Counter Clock Inputs
GATEN Counter
Gate
Inputs
OUTN
Counter Outputs
RD
.
Read
Counter
WR
Write Command
or
Data
CS
Chip
Select
A1~AO
:
Counter Select
Vcc
. +5
Volts
GND
.
Ground
-
76
-
M
2
3500
8251
8251
chip
address[0001/xxxx]
IN
Uix
OUT)
CLK
DSK
DTK
CTS
Rl
S
TXD
TXRDY
TXE
TXC
RXD
RXRDY
"RXC
SYN/BD
IN
IN
OUT
1
N
OUT
OUT
N.C.
N.C.
IN
IN
OUT
IN
N.C.
2.45MHz
clock
DATA
SET
READY
DATA TERMINAL READY
CLEAR
TO
SEND
REQUEST
TO
SEND
TRANSMITTER
DATA
TRANSMITTER
CLOCK
RECEIVE
DATA
RECEIVER
READY
RECEIVE
CLOCK
READY
CS
PO
(MPER
SUT),
ER
CD
RD
OUT
0 of
8253
SD
To
3iil>CPU
of
8253
OUT
8253
8253
chip
address[0010/xxxx]
IN
#UxH
OUT#|2XH
CLKO
GATED
OUTO
CLK1
GATE1
OUT1
CLK2
GATE
2
OUT 2
IN
IN
OUT
IN
IN
OUT
IN
IN
OUT
2.45MHz
Vcc
To
TXC,
RXC of the
8251
2.45MHz
From OUT2
MUSIC
2.45MHz
Vcc
To
GATE
1
INTO
TO
MAIN
FROM
SUB
POWER
ON
RESET
SOO
-SIW(
IORQ-WR
of
SUB)
fNTR=L(FROM
MAIN)
INTO
H
L
H
INT
TO SUB
FROM
KEY
STK=
(L)
-
77
-
M
7.
3500
7-1. Printer interfacing circuit
7.
PRINTER INTERFACE
AS 4 • AS 5 AS6 • AS 7
RI)
I
ORQ
Al
Z80 AO
SUB
CPU
AR
Chip
I
)fi i >de r
SO3
rs.
-^jp
3C
r-—
•
^
—
°
°^
*-!-
cf^ 1
cjX i—
-J
'arallel
interfacing
signals
"N S1W
^
,
DSO
_
DS1
^
DS2
DS3
DS4
^
DS5
v DS6
^
DS7
CS
8255
PA
RD
PA
PA
WR PA
Al
PA
A° PA
PA
PA
PC
PC
PC
PC
PC
PC
1
L_
~0<xr
LS244
0
1
2
3
4
5
6
7
5
6
7
0
1
2
H/ ©
DA1A2
H^ ©
"A^A3
C|^»
(3)
DAT
16
ts^
i^^ —
CP^»
(g)
DATA?
ol ^^
Op)
D \TA S
rv_
rs_
"v*~i
1 "No
ffi\ STRDRF
^o^l-X}—^^^
ACK
o^l n
EU-
I^J .^ ®
/// ©)
PDTR
*
2,4,6,...
28areGND.
*
Ahnwp
nin
numbers
are of the
model-3
Pin
No.
1
3
5
7
9
11
13
15
17
19
21
23
25
27
Signal
name
STROB
DATA
1
DATA
2
DATA
3
DATA
4
DATA
5
DATA
6
DATA
7
DATA
8
ACK
BUSY
PE
PDTR
SYSRES
IN/OUT
-
PRINTER
-PRINTER
-
PRINTER
•
PRINTER
-
PRINTER
-
PRINTER
-
PRINTER
Function
Data
is
transfered
to
printer when STROB
is
high.
Data
output
to the
printer
Indicates
the end of
character
input
or
function
input
i
When
high,
it
enables
to
receive
data
When
high,
it
indicates
paper
empty
When
high,
it
indicates
the
SELECT
mode
(receive
enabled!.
Reset
signal,
normally
high
-
78
-
7-3. General description
of the
parallel interface
The
8255
is
used
for the LSI to
control
the
parallel inter-
face.
The
8255
can be set in the
following mode.
/PORT
A:
MODE
0
I
PORTB: MODE
1
C:
Output
Because
it is not
possible
to
directly
sense
the ACK
signal
as
it
uses
interrupt
for key
processing
and
RS232C
input,
the
ACK
signal
is
latched
by
means
of the OBF pin
function
74.
Data
transfer
timing
BUSY
ACK
(
8255
A
v
PC-7J
DATA
STROBE
(M1N)l^s(MIN)
PRINTER:
MZ-1P02, MZ-1P03
CE-
330P, 331P, 332P
*
Broken line
in the
above
figure
represents
timing
for the
CE-330Pand331P.
'For detail
of
timing,
refer
to
Manual
provided
with
printer.
7-5. General
description
of
control
software
Set
the 20
second
counter.
STROBE
OUT
Set the 20
second
counter.
-
79
-
M
/
3500
7-6.
I/O
port
map
8255
ON SUB CPU BUS
IN
OUT
8255
chip
address(0011/xxxxj
Group
A:
Mode
1
Group
B:
Mode
0
O
3
PA7
PA6
i'A5
I'A4
I'A3
PA2
PA1
PAO
PC7
PC6
PCS
PC4
PCS
PC 2
PCI
PCO
PB7
PB6
PBS
PB4
PBS
PB2
PB1
PBO
Output
OBF
output
ACK
inputi
1NTR
Output
DATA8
DATA"
DATA6
I)
AT
A
5
DATA4
DATA3
DATA2
DATA1
ACK
T-SET
ACK
STROBE
J
MUS
1C ,
sustain
NOT USE
ACKC
STC
DC
P/M
SRDY
CLK
Printer
Dm
C2
Cl
CO
STRB
Keyboard
CG
selection
Sub CPU
READY
Clock
INPUT
PORTC74LS244
74LS244
port
address[0100/xxxx]
IN
OUT
#4X
CDS7D
CDS6D
CDS5D
CDS43
CDS33
CDS2D
cosn
CDSOD
HLT KEY
STK -i
DK
J
PUTR
PE
BUSY
Reads
the
8255
OBF
(PC7)
output
or
timer output.
Keyboard
Printer
-
80-
M
2
3500
8.
OTHER INTERFACES
8-1.
Clock
circuit
1)
Schematic
T;
10 Ii2 u "
HDH
*
l«"-.r
1
2)
Clock
timing
READ
HOLD
.
READ
mode
mode
[
mode
Cn(CO~C2)
0 X 3 Y~l
STB
/ \ /
^Ones digit
of
seconds
Tens
digit
of
seconds
WRITE
HOLD
mode mode
Tens
digit
of
month
'
SET
i
HOLD
mode
I
mode
DIN
Don't
care
X
CLK
DOUT
Tens
digit
of
seconds
Tens
digit
of
month*
-
8)
-
MZ3500
3)
^PD1990AC
Block
diagram
OK
O
Command specification
C2 C1 CO
000
0 0 1
0 1 0
0 1 1
Command
Register
hold
Register
shift
Time
set
Time
read
Description
Holds
40-bit
S/R
Data
input/output
Data
of the
40-bit
S/R is
preset
to the
time counter.
Data
in the
time
counter
is
read
to the
40-bit
S/R.
DOUT
1Hz
[LSB]
Output
of LSB
ILSB]
Output
[LSB]
Output
Data
Shift
Not
possible
Possible
Not
possible
Not
possible
Note
Data
retention
Shifts
in
synchronization
with
the
clock
Input/output
format
Example:
In the
case
of 10
o'clock,
25
minutes,
49
seconds,
July
30th.
(LSB)
«-
Seconds—'
L(\/|jnutes—I
Lnoure_)
L_
Dey—I
(MSB)
9
4
5
2
0
1
0
3
7
Won
!OnthJ
-
82
-
8-2.
Voice input/output circuit
Music
output
waveform
PD8255
•
Tonal signal
OUT1
•
Sustain
PC4
•
2SC458
emitter
•
•
2SC458
collector
Speaker
output
»
GETE1
J
mmmil
u
-Tlj
1
-
83
-
M/3500
83.
Expansion
and
interrupt
(See
3-(2)-4
for
interrupt)
1)
Options
and
expansion
units
Options
not
requiring expansion
unit
MZ
1K01
1001
1D02
•1D03
-1S01
-1S02
•1X02
-1P02
-1P03
-1P04
CE-330P
-333P
-33
1M
-330X
MZ-1F02
-1F03
-1R03
-1R05
JIS
keyboard
14"
medium resolution color
CRT
12"
high resolution
green
CRT
1
2"
high resolution color
CRT
14" CRT
tilt
stand
12" CRT
tilt
stand
Light
pen
80-character
pnnte
Color
injket
printer
80-character
printer
136-character
printer
Optional
MFD
drive
unit
Plotter
Optional
MFD
drive
unit
Optional
MFD
drive
unit
(single deck)
Graphic
board
MZ-1E01 RS232C
1/F (7)
-1E02
GP I/O ©
•1E03
SFD 1/F
-1F05
SFD
unit
-1R06
RAM
2)
Expansion
unit
Signal
assignment
by
slot
Main
CPU
bus
line
BASIC(
SFD
CONTROL
•
VOICE
DRAM
control
signal
32K
mask
ROM
8K
mask
ROM
ROM1
ROM2
ROMS
ROM4
INT1
INT2
I
NTS
INT4
SLOT1
SLOT2
SLOTS
SLOT4
L
-84-
M
7
3500
8 4
System
SW1
(DIP
SW)
(User
operative
through
the
cabinet
bottom)
No
1
2
3
4
5
6
7
8
9
10
Signal
name
SW1
SW2
SW3
SW4
SW5
SW6
SW7
FD1
(SW8)
P/M
(SW9)
Function
Printer
select
CRT
select
Choice
of
decimal
point output
format
RS232C
assign
Key
shift mode
setup
Choice
of CG
for
display
Position
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
Polarity
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
Description
SW2 SW1
ON ON
CE332P
OFF
ON
MZ1P02
ON OFF
IO2824
OFF
OFF
High
resolution
CRT
(MZ1D02. MZ1D03)
Medium
resolution
CRT
(MZ1D01, MZ1D06)
A
period
is
output
for a
decimal point
A
comma
is
outputted
for a
decimal point
Low
state
or
open
ER
signal
during data output
will
result
in an
error
The
signal
ER
becomes
invalid
CD is
high
as
long
as
power
is on to the
main
unit
CD
goes
high only during
data
output
However,
it
would
not go
high
if the
echo
back
function
is
on the
host
side
An
error
is
cause
when
the PO
signal
is
high
during
data
output
Polarity
is
inverted
for the
above
Normally
in
capital
letter,
but in
small letter
when
shifted
Normally
small
leter
and in
capital letter when
shifted
3500
CG
will
be
assigned
when
the 200
raster
CRT is in use
2000
CG
will
be
assigned
when
the 200
raster
CRT is in use
^=—
=T
#47 pin of MMR
£48 pin of MMR
#51 pin of MMR
#52
pin of MMR
ToCTS,
DSR
of
the
8251
ToCTS
of the
8251
#54
pin of MMR
(FDD
P/M
signal
(To A3 CG)
NC
Dip
switches
(A) and (B)
located
on the PWB are
used
for
servicing
the MFD or for
other
machine
service
and
there
fore
the
user
is not
supposed
to use
these
switches
In
addition,
these
switch
must
be
used
when
either
the CE
330M
or
331M
is
used
as the
expansion
MFD
DIPSW(A)
No
1
2
3
4
Signal name
SEC
(SW1A)
FD2
(SW2A)
FD3
(SW3A)
SRQ
(SW4A)
44 pin of MMR
56
pin of MMR
58
pin of MMR
Bus
request
to
sub-CPU
DIPSW
(B)
No
1
2
Signal
name
SRES
(SW1B)
SW2B
SUB CPU
reset
signal
SUB CPU BUS
select
signal
t
1
OFF
ON
OFF
ON
OFF
ON
OFF
ON
2
OFF
OFF
ON
ON
OFF
OFF
ON
ON
3
OFF
OFF
OFF
OFF
ON
ON
ON
ON
WhenSH
in use
When
DH in use
—
—
Use
of the
CE330M
as an
expansion
unit
Use
of the
CE331M
as an
expansion
unit
Check
mode
*1
Check
mode
*2
*1
Test
program
is
loaded
and
executed
\
*2
Provided
for the
test
of the MFD
interface
The
read/write
test
is
carried
out for the
expansion
unit
Used
for an
individual
test
of the CPU PWB
When these
three switches
are
turned
off
altogether,
it
makes
the
sub
CPU
operated
independently
To be
used
in th ON
condition
under
a
normal
situation
MZ3500
DIP
SW(A)
1
OFF
ON
OFF
ON
OFF
ON
2
OFF
OFF
OFF
OFF
ON
ON
X
3
OFF
OFF
ON
ON
ON
ON
><^
4
ON
ON
ON
ON
ON
ON
OFF
DIPSW(B)
1
ON
ON
ON
ON
ON
ON
OFF
2
ON
ON
ON
ON
ON
ON
OFF
•
Switches
are set in
this manner before shipment
of
machines this
us the
single-sided
minifloppy
disk drive.
Switches
are set in
this manner before shipment
of ,
My-it^n
Pn^41
machines
that
use the
double-sided
minifloppy
(
11/171540'
vv"=/n
disk drive.
' '
Switches
are set in
this manner when
the SH is
used
for the
optional
MFD
Switches
are set in
this manner when
the DH is
used
for the
optional
MFD
Test
mode
* 1
Test
mode
"2
Individual
CPU PWB
test
\(f Can be in
either state
-
86
-
MZ3500
9,
POWER
CIRCUIT
DESCRIPTION
1.
BLOCK
DIAGRAM
(Block
diagram)
A.
+5V and
+12V
supplies
1.
Functions
a.
Supply
voltage
is
first
rectified
in the
rectifier
circuit
and
sent
out to the
switching
regulator
via the
over-
current
detector
provided
in the
overcurrent
protect
circuit.
b.
Next,
the
voltage
is
converted
to the
+5/+12V
output
in the
switching regulator
and
sent
out to the
noise
•
Nfilter.
c.
Change
in the
switching
regulator
output
voltage
is
sensed
by the
control
circuit
and is fed
back
to the
switching regulator after being
amplified
in the
amplifier
located
in the
control
circuit,
for
maintaining
the
output
voltage
to a
constant level.
d. The
signal
from
the
oscillator
is
supplied
to the
switch-
ing
regulator
through
the
control
circuit
for
driving
the
switching regulator.
e.
For
prevention
of
overcurrent,
the
protect
circuit
is
used
for
stopping
the
oscillator when
an
overcurrent
is
met,
and
it
makes
the
switching regulator
to
halt
in
order
to
shut
off
+12V/+5V
supply.
2.
Description
of
each
block
a.
Overcutrent protect (control/protect)
circuit
When
an
overcurrent
is met in the
+5V/+12V
circuit,
it
causes
to
increase
the
voltage
at
both
ends
of the
over-
current
detector
resistor
R1,
which
in
turn
causes
to
increase
the Q3
collector current, for, there
arises
larger
voltage difference between
the
emitter
and
base
of the
transistor
Q3.
This
makes
the
gate voltage
of the
thyns-
tor
increased
owing
to
activation
of SR.
Witr,
jctivation
of SR it
makes
the
oscillator
voltage dropped
to the
GND
level
at the
point
"a" to
stop oscillation,
which
also
makes
the
switching
regulator stopped
by the de-
activation
of the
transistor
Q5
oscillation.
This
causes
the
transistor
Q5
inactive,
and it
shuts
off the
+5V/
+ 12V
supply,
b.
Oscillation
circuit
As
the Q1
emitter
voltage
is at
almost
GND
level
whe-
the
transistor
Q1 is
active,
the Q2
base
voltage tem-
porarily
drops
close
to the GND
level
by
means
of C6,
which
in
turn
makes
Q2
inactive
and the Q2
emittei
voltage increases.
Then,
the Q2
base
voltage comes
to
rise
as C6
begins
to
be
charged
through
R6, and the
transistor
Q2
starts
to
activate again.
With
activation
of the
transistor
Q2, the
Q2
emitter
voltage starts
to
drop
and the Q1
base
voltage
is
temporarily
dropped
by
means
of C5, to
shut
off the
transistor
Ql,
which
causes
to
increase
the
transistor
Q1
emitter
voltage.
Next,
as C5 is
charged
by R5, it
makes
the Q1
base
voltage
increased
which
puts
the
transistor
Ql
into
activation.
In
this manner,
transistors
Q1 and O2 are
alternately
turned
on and off to
keep oscillating.
C5 and C6 are
charged
through
R5 and R6 by
on/off
action
of the Q1 and Q2, and
discharged
through
Ql and
Q2.
M
7,3500
Switching
regulator
Q5
+
5V
or
(Switching
regulator
and
constant
voltage
control
circuit)
« VR is
the+5V or+12V adjusting
VR.
• D3 is
provided
to
discharge
current from
Cj
after power off.
-
88-
M23500
c.
Power
switching
circuit
As
the
signal
from
the
oscillator
is
amplified
through
Q7
to Q6 to
change
current
to the
transformer
T2. it
causes
voltage
to
appear
on the
base
of Q5
(one
of
components
is
cut by
D1),
so
that
the
transistor
Q5
begins
to
per-
form switching operation
in
synchronization
with
the
oscillation
frequency.
As Q2 is
switched,
current
is
supplied
to the
emitter
side
of the
transistor
Q5,
which
produces
smoothed
voltage
through
the
capacitor
C1
and the
coil
L2. The
circuit
composed
of D4 and VR1 is
the
reference
voltage
for the +5 or + 12V
supply,
which
is
used
to
control
the
emitter
current
flowing
to the
transistor
Q9. The
current
supplied
from
Q9 is
used
to
create
Tr3
inactive
by the
delayed
C1 and C2
voltages
which
supplied from Tr1-R2-VR1-D3.
It
goes
high
with
deactivation
of
Tr3.
3.
Alarm circuit
(Alarm generation
circuit)
When power
turns
off,
the
voltage
accumulated
in C1
and
C2 are
supplied
to the
base
of Tr2 via Tr1 ... and
D3, so
that
Tr2 is
kept
active
and Tr3
inactive
for
some-
times
after
power
off.
Timing chart
SW
+ 5V
PFD
-89
-
10-2.
Key
search
timing
Single
key
entry
Key
/
STROBE
Bounding
n n n n n n n
1
Strobe
*~5.5ms
M 5ms -»
RETURN
cvcle
n n n n n
15ms
MZS500
n
n
n
DATA
OUT
Two key
entry
Key
1
/A"
Key
2
STROBE
n
n n n n
RET
n
n n n
n
-5.5ms—M—•6.5ms —M—5ms
—W
15ms
M
15ms
n n n
DATA
(1)
OUT
DATA
(2)
OUT
-
10-3.
Key
serial
transmission
procedure
1)
Data format
Key
-» CPU
2s
2s
DATA
22 21 2°
Parity
All
nine
bits
Command
Key
AM
4
bits
Parity
-
91
-
10-4.
Keyboard
controller
basic
flow
M?3500
Power
ON
Timer
START
(5mS)
-
93
-
MZ3500
10-5. keyboard
controller
signal description
PIN
No
1
2
3
4
5
6
7
8
9
10
11
12
19
20
21
22
23
24
25
26
27
30
31
32
34
35
36
38
39
40
Porality
signal
name
TO
XTAL1
XTAL2
RESET
SS
INT
EA
RD
PSEN
WR
ALE
DBO
DB7
GND
P20
P21
P22
P23
PROG
VDO
P10
P13
P14
P15
P17
P24
P25
P27
T1
Vcc
IN/OUT
IN
IN
IN
IN
IN
IN
IN
-
-
-
-
IN
IN
OUT
OUT
IN
-
IN
OUT
-
OUT
IN
IN
IN
IN
Function
Output
data signal
from
the sub CPU
(D(O)
Internal clock oscillator
crystal
input
Internal
clock oscillator crystal
input
Processor
initialize
+
5V
Strove
of
D(C) that also
is
used
for
interrupt
to the
keyboard
side
(ST(O)
GND
NC
NC
NC
NC
RETURN
signal
from
the
keyboard
is
input
when
a key is
pushed
during
key
search
0V
supply
Output
data
signal
from
key
(D(K))
Strobe
of
D(K)
which
also
is
used
for
interrupt
to the CPU
side
(ST(K))
Not
used
NC
+
5V
Strobe
to the
keyboard
unit
by
which
a
hexadecimal
code
is
sent
out for
generation
shift
pulses
to
terminals XOX15ofthe4515
decorder
during
key
search
NC
Pins
used
to
activate
the
keytop
embeded
LED
#32 pin
Alphabets
and
symbols
(LOCK)
#33 and #34 are not
used
Not
used
Keyboard
type
identifier
pin
Keyboard
type
is
identified
by
mears
of
KSO, KS1,
KS2 of
KUC1
an
KUS2.
whether
it is GND or NC
Acknowledge
input
from
the CPU
(ACK(O)
Sent
only
when
the CPU
receives
a
correct
data
+
5V
supply
11.
SELF
CHECK
FUNCTIONS
The
-3500
performs self-check test during
initial
program
loading
of the
ROM. 11-1.
Test
regarding
the
main
CPU
1) MFD
I/F.
128KB
RAM. 16KB
ROM
(for
ROM
based
machine)
checks
[Procedure]
1.
Turn
on all dip
switches
of the 4 bit
switch (located
in
the
middle
of the
front
side
of the
board)
and
turn
on
all
dip
switches
of the 2 bit
unit
on the
front
side
of the
board.
2.
Insert
a
floppy
disk
into
drive
unit
No 2
(the
third
drive
unit)
3.
Turn
the
power
on
4. The LED
flickers
for a
moment then
the
test
program
starts
During
execution
of the
test program,
the LED
stays
unlit
About
four
seconds
later
the
result
is
mdicsted
(DISPLAY)
(1) LED
comes
activated after normal ending
of the
test
(2)
LED
flickers after
abnormal
ending
of the
test
The
kind
of
error
can be
known
by how the LED is
activat
ed and
flickered
LED
(fof id«niific«Tion
of
GO/NO
GO)
Type
of
error
0) MDF 1/F
error
ON OFF
1sec.
4sec.
(2.1
SDO
read/write
error
(3)
SDO
bank
alternation
error
® AD2
bank alternation
error
© AD3
bank alternation error
CD
ROM
sum-check
error
©
Option
RAM
read/write
error
(Indicated
even
when
the
option
RAM is not in
use)
/s~.
Option
RAM
bank alternation
error
NOTES:
1. The MFD I/F
will
not be
tested,
if
there
is no MFD I/F
connected
or
when
the
diskette
was not
inserted
in the
slot
of the
drive
unit
No.2.
2. ROM
test
will
not be
performed,
unless
it is a ROM
based
machine.
2)
Loacing
check program
The
test program
is
loaded
from
the
specified track
and
sector
to
start
executing
the
test.
[Procedure]
(1)
Set dip
switches
on of the 4 bit
unit
located
in
middle
of the
front
side
of the
board
as
illustrated
at the
right.
No.
POSITION
1
OFF
2
ON
3
ON
4
ON
,2) Set dip
switches
on of the 2 bit
unit
located
on the
front
side
of the
board.
(3)
Insert
the
media
into
a
slot
of any
diskette
drive
unit.
(4)
Turn
the
power
on
(5)
Load
the
program
from
the
specified
track
and
sector,
to
start
execution
of the
test
program.
[Conditions
required
for the
drive
unit
and
media]
(1)
Use the
FD-55B
for the
diskette drive
unit.
(2)
Program
may
exist
in any
sector
of any
track, provided
that
it is
written
in
continuous sector
within
a
same
track.
(Max.
256
bytes
x 16
sectors
= 4K
bytes)
(3)
Data
descrived
next should
have
been
written
on
Sector
1 of
Track
0.
(4)
Program
loading
address
must
be
4800H
and
higher
MZ
3500
Sector
1,
Track
0
information
0
10
15
AAH
1CH
TRACK
SIDE
SECTOR
N
NO. OF
SECTOR
I
i
i
i
t
i
1
TRACK
SIDE
SECTORSECTOR
N
\
Represent
the
Drive
unit
system
media
specification
Load
address Start address
Test
program
20
50
NO. OF
SECTOR
NO. OF
SECTOR
NO. OF
SECTOR
SUB-IOCS
-H the end
SIDE
-i!
Single
dencity
(Track
0)
Double
density
(other
than
Track
0)
SIDE
0
(front
side)
SIDE
1
(reverse
side)
No
of
data
transfers
= INT
[IOCS
capacity/1
K] + 1
•
Sub-IOCS
can be
divided
into
eight
blocks.
If
divided
to
less
than
eight
blocks,
the
block
following
to the
final
block
mut be
traced
by
"FFH".
11-2. Sub-CPU side
[Test items]
Memory,
VRAM,
GDC
peripheral,
clock,
speaker,
printer
interface,
light
pen.
and
RS232C interface.
GO/NO
GO of the
test must
be
confirmed
on the
video
screen.
Moving
from
test
to
test
is
done
by
depressing
the
HALT
key.
[Procedure]
(1)
Turn
OFF all dip
switch
of the 4
bits
unit
located
in
the
middle
of the
front
side
of the
board
and
turn
OFF
all
dip
switches
of the 2
bits
unit.
(2)
Set the
system
dip
switch
levers
(10
bits)
located
on
the
reverse
side
of the
board
to the
foil
owing
positions.
No.
POSITION
1
OFF
2
ON
3
ON
4
ON
5
ON
6
OFF
7
OFF
8
ON
9
ON
10
ON
(3)
Turn
power
on
while pushing
the
HALT
siwtch
to
start
the
test program.
Then,
push
the
HALT
switch
to
step
to
each
test
phase.
Result
of
GO/NO
GO
will
appears
on the
video screen,
except
for the CRT
interface
and
speaker tests.
-96-
1)
Memory
test
Sub-IOCS
RAM
(4000H-5FFF)
Shared
RAM
(2003H-23FFH)
Shared
RAM
(2440H-27FFH)
Above
are
tested.
[Display]
(1)
Normal test ending
RA
OK:
SUB-IOCS
RAM
RA
OK
RA
OK
Above
information
are
displayed
on
three display
lines.
(2)
Abnormal
test
ending
RA ER
Shared
RAM
2)
VRAM
check
Proceed
to
test
for
ASCI!
and
atnbute
VRAM
[Display]
During
test penode, display
shows
under following.
(1)
Display
reviced
"U" for
entire
screen
Irom
top
side.
(2)
Display blinking
"I''
with under!
ne for
entire
screen.
(3)
Display entire
screen
by
space.
Test
end
1.
Normal
VR OK
2.
Abnormal
VR ER
3)
CRT
inter
face test
Performance
of the CRT is
tested.
To
move
into
each
test
phase,
push
the
HALT
switch.
Test
No.1-No.8
test
the
400-raster CRT,
and
test
No.9-No.16
test
the 200
rasters
CRT.
'Procedure
and
display]
(TestNo.1)
Confirm
all
patterns
on the
display screen
of 40
digits
and
20
lines.
20
1
234567890
2
3
4
5
i
(All
patterns)
I
I
5
6
7
8
9
0
C
*7 '
O
/ I
ASCII
00-FF
(Test
No.2)
Confirm
all
patterns
on the
display
screen
of 80
digits
and
25
lines.
25
1234567890-
2
3
4
5
-567890
(All
patterns)
(Test
No.3)
(1)
Confirm
that
an
entire
screen
is
Filled
with
"H".
(2)
Confirm
that
attributes
are
shown
as
illustrated.
Vertical line
Horizontal line
Highlight
Blink
-
97
-
MZ3500
(
Check
No. 4 )
Border
in
black
!•
"H" in whi
(
Check
No. 5 )
Kff
"H" in red
"H" in
green
"H" in
white
(
Check
No. 6 )
(
Check
No. 7 )
(
Check
No. 8 )
Backroung
in red
Back
ground
in
green
Back
ground
in
black
L "H" in
blue
L "H" in
green
[•
"H" in
white
4)
Speaker
test
Performance
of the
speaker
and the
volume
control
are
tested.
Listen
carefully
to
detect
any
abnormal sound
or
mulfunction.
Adjust
the
volume
control
to a
suitable
listen-
ing
level.
5)
Printer interface test
Performance
of the
printer
interface signal lines
and
action
of the
8255
are
tested.
[Dispaly]
(1)
Normal test ending
PR
OK
(2)
Abnormal test ending
PR
ER
6)
Light
pen
interface
test
Performance
of
light
pen
interface
signal
lines
and the
action
of the GDC are
tested.
[Display]
On the
upper
left
corner
of the
screen
is
displayed character
and
line.
(1)
Normal test ending
LP
OK
(2)
Abnormal
test
ending
LP ER
7)
RS232C
interface test
Performance
of
RS232C
interface
signal
lines
and the
action
of the
8251
are
tested.
[Display]
(1)
Normal
test
ending
RS
OK
(2)
Abnormal
test
ending
RS ER
L-
"H" in
blue
"H" in red
"H" in
white
R
S
2
3
2
C
C/
^n
c
*^
CD
DR
N
PO
Ready
O
_
O
_
"
O
.
O
M
O
.
O
.
O
.
H
O
rt
M
1
5
2
7
9
10
8
6
4
3
}
}
}
}
•
H'
H'
H'
H'
in
blue
in red
in
green
' in
white
It
will
need
wiring connection
as
illustrated
in the
figure
in
order
to
test
the
RS232C
interface.
Pins
of the
RS232C
interface
edge
connector must
be
wired
in the
following
manner:
Front
side
/
*
7531
-
98
-
8)
ROM-IPL
MAIN
CPU
CHECKER FLOW CHART
1/2
MZ3500
(
MAIN
CUP
A
CHECKERSTAHT
]
c
Write
"66"
»nd~Of~
on
Tracki
0.20.»^3
NOTE
lnclud«
SEEK etroi
and
RECALIBRANTE
NOTE
tr»c1i>d« SEEK
error
and
RECALIBRATE
-
99-
MZ3500
MAIN
CPU
CHECKER FLOW CHART
M?
Option
HAM
read/write
check
Change
bank
of
the
option
RAM
Error
on
display
C
HALT
-
100
-
M
7*500
SUB CPU
CHECKER FLOW CHART
1/3
(
SUB
CPU
^
CHECKER
START
I
CRTm
t*f
face
t«t
SeiGDCto«00<amr.
-
101
-
MZ3500
SUB CPU
CHECKER
FLOW
CHART
2/3
SUB
CPU
CHECKER
FLOW CHART
3/3
Sei
59
Oc
th»
timer
to 23
hourt.
minuiei.
58
**corxii
*mb«r
3
III
Printer
int
M»c*
tt»t
11-3.
Keyboard
unit
test
functions
1)
Keyboard
controller
ROM
test
(1)
After power
on in a
normal
condition,
it
starts
to
carry
out the ROM
self-test.
If the
alpha/symbol (LOCK)
LED
were
to
turn
on, it
indicates
a
failure
in
KBC.
If
not,
KBC is
satisfactory.
t
Key
self
check
functional specification
(simplified
check)
2)
Keyboard
test
(1)
As the
power
is
turned
on
with
the
"DEB"
in
depres-
sion,
it
goes
into
the
keyboard
self-test
mode.
(2)
Depress
key in a
given
sequence.
If key is
depressed
in
a
correct sequence,
it
makes
the
alpha/symbol (LOCK)
LED
activated
each
time
a key is
pushed.
If the key was
pushed
in a
wrong
sequence
or
when
a
failure
is met in the
key,
it
makes
the LED
blinked.-
(3)
It
returns
to the
normal mode upon
completion
of
testing
all
keys.
With
this,
the LED
goes
out.
(4)
Observe
the
following
key-in
sequence
to
test.
i)
Turn
the
OP/PRO
siwtch
to the OP
side.
ii)
Turn
on
power
while pushing
the
"DEB" key.
iii) Turn
the
PO/PRO
which
to the PRO
side.
iv)
Push
a key one at a
time
in
accordance
with
the
given
sequence.
-
102
-
MZ3500
12. IPL
FLOW
CHART
12-1.
MAIN
CPU IPL
FLOW CHART
1/2
(
MAIN
CPU
^
(PL
START
J
Transfer
the
program
m
1000E-J0400E-.
B
Jump
to
400EH
ROM/RAM
test S**ect
memory
location
SUM
IPL
START
Check
MFD
Index
itgnal
Contents
of
parameter
sector
1.
Kind
of MFD
Single-side
double-dene
ity or
double
side
double
dencity.
2.
Track
and
sector
where IOCS
is
stored, Loadi
vj '.
and
Truch
Number
of
sectors
Note'
The sub
loader
is
contained
m the
leading sector.
-
103
-
MZ3500
MAIN
CPU IPL
FLOW
CHART
2/2
I
Check
if
IOCS program
area
is
smaller than
RAM
volume.
YES
LOAD
IOCS
SEEK& READ
Transfer
the
IOCS
program
to
shared
RAM
8000H~-»-F800H~
-
LOAD BOOT
LOAD
BOOT
SSEK&
READ
NO
•SEEK,
READ
ERROR
c
I/O
SYSTEM
LOAD
ERROR
transfer
HALT
CPU
STOP
ERROR
\^
tran:
I/O-SYSTEM
LOAD
ERROR
isfer
BOOT:
Program used
to
start
the
system.
C
HALT
CPU
STOP
Position
of
boostrap
program
on the
media:
Sector
2
thru
5 of
Track
0.
ERROR
ret
rys
^
—
JUMP
^\
BOOT ADDRESS
)
1
C
BOOTERROR
*
on
disp.
1
(
HALT
CPU
STOP
-
104
-
122.
SUB CPU IPL
FLOW CHART
(
POWER
ON A
SUB
CPU
IPL
J
MZ-3500
T,m«,
In
A
C
1
t,alize8255
Mode
0.8
Mode
1.
OUT
1
SUB CPU
READY
OFF
1
Rest
GDC
1
Check
ROM sum
Initialize
GDC and
check
G
VRAM
Set
the
custom
LSI
CSPI
and
CSP2
control
boards
Initialize GDCagatr
C-GDC, G-GDC
command
transfer
IPL ROM is
broke
u
indicated
on
display
HALT
CUP
STOP
\
I
-
105
-
13-18.
PIN
CONFIGURATION
OF 1C & LSI
Mz-roo
74
LS 00
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OUTPUTS
m
I
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L
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4
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16
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3500
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S
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2
3
4
5
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7
8
9
10
12
13
14
15
16
17
18
19
20
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28
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35
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7
8
9
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11
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26
25
24
23
22
21
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19
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MZ-35OO
PARTS GUIDE
LI
oe
IE--or
ooss-zw
MZ-3500
[2] PWB &
Fixing angles
NO
1
2
3J
4
5
6
7
8
9
11
12
13
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
31
32
33
34
35
PARTS
CODE
JKNBM0004PAZZ
LANGS1
006AC2Z
LANGK1007ACZZ
OCNCW1
008AC02
Q
SW-K
1 0 0 7 ACZ Z
R
V R-A 5 4 5 2 QCZ Z
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DUNTK
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DUNTK 060ACZZ
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003ACZZ
GFTAR
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LHLDZ 001ACZZ
QCNW—
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QCNW-
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047ACZZ
QCNW-
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PRICE
RANK
AC
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NEW
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N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
PART
RANK
C
C
C
C
B
B
C
C
E
E
E
E
D
D
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
DESCRIPTION
Knob
for V R
Fixing
angle
for
speaker
Fixing
angle
for
speaker
Connector
HALT
switch
Variable resistor
Speaker
Screw
CPU
PWB
unit
(Model
3541)
CPU
PWB
unitiModel
3530)
CPU
PWB
unit
(Model
3540)
MFD
I/F PWB
unit
Cover
for
RS232C
I/O
slot
Cover
for I/O
slot
Guide
for
PWB
!
Connector
for
light
pen
Connector
for key
board
Connector
for
CRT-1
Connector
for CRT
—
2
Screw
Screw
Screw
Screw
Connector
"A"
angle
Connector
"B"
angle
Cushion
for PWB
Insulator
for MFD
Connector
Connector
(18pm)
Screw
Screw
Nut
Rubber
cushion
Nut
Holder
Rubber
cushion
for PWB
(1-22)--
32
M2-3500
13.
Connector
NO
1
T1
3
4
6
9
10
11
12
13
14
1&1
17
18
19
20
21
26
PARTS CODE
OCNCP604 1QCZZ
QCNCP4841QCZZ
QCNCW1001ACZZ
QCNCM1 004ACZZ
QC N W- 1 0 0 7 AC Z Z
QCN CWO 2 0 7 HC Z Z
QCNCM1009ACZH
QCNCM1
009ACZ
i
QCNCM1009ACZB
QCNCM1009ACZG
QCNCM1009ACZE
QCNCW
1 0 0 8 AC 0 1
QC NCW 1 0 0 8 AC 0 2
QC NW— 1 0 4 7 AC Z Z
QC NW— 1 0 4 4 AC Z Z
QCNW-1004ACZZ
QCNW-1
0 0 3 ACZ Z
LHLDF6648RCZZ
PRICE
RANK
AW
AT
AZ
AQ
AX
AK
AC
AC
A A
AC
AB
AC
AF
AM
AM
AM
AK
AB
NEW
MARK
N
N
N
N
N
PART
RANK
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
DESCRIPTION
Connector
Connector
Connector
Connector
Connector
Connector
Connector
Connector
Connector
Connector
Connector
Connector
Connector
Connector
for
CRT
-2
Connector
for
CRT—
1
Connector
for key
board
Connector
for
light
pen
Holder
18
15
20
21
MZ-3500
[41
Others
NO.
1
9
10
13
PARTS
CODE
RMEMR1004AC07
UBNDA1
008CCZZ
SPAKA1003ACZZ
SSAKH3002KCZZ
PRICE
RANK
B A
A A
A
Z
A
D
NEW
MARK
N
PART
RANK
D
D
D
D
DESCRIPTION
Master
media
AC
Cord band
Packing
cushion
Plastic
bag
CPU PWB
NO.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
PARTS
CODE
LANGQ1004ACZZ
LHLDF6648RCZZ
QCNCW0207HCZZ
QCNCW
1 0 0 1 AC Z Z
QCNCM1 009ACZB
QCNCM1009ACZE
QCNCM1009ACZG
QCNCM1009ACZH
QCNCM1009ACZi
QCNCP484
1QCZZ
QCNCP604 1QCZZ
QSOCZ6414ACZZ
QSOCZ6416ACZZ
Q
SC-CZ
6 4 2 4 ACZ Z
QSOCZ6428ACZZ
QSOCZ6440ACZZ
QSW-Z1002SCZZ
QSW-Z2005SCZZ
Q
SW-Z
9660KCZZ
RC-KZ
1 0 1 8 CCZ Z
RCRS-1001ACZZ
RCRS-1002ACZZ
RCRS—
1
003ACZZ
RCRSP1
003CCZZ
RMPTC4333QCKB
RMPTC4682QCKB
RMPTC8333QCKB
UBATN1001ACZZ
VCCSPU1HL100D
VCCSPU1HL330J
VCCSPU1HL470J
VC E A A A 1 CW 1 0 6 Q
VC E A A A 1 CW 1 0 7M
VCEAAA1CW336M
VCEAAA1EW106M
VCEAAA1EW107M
VCEAAA1EW227M
VC E A A A 1 HW 1 0 5 M
VCEAAA
HW335M
VC E A A A HW4 7 5M
VCKYPA
HB681K
VCKYPA HB681K
VCKYPU
HB221K
VCKYPU1HB56
IK
VCTYPA1NX104M
VCTYPA1NX104M
VCTYPU1EX103M
VHDDS1588L1-1
VH
HM472114-1
VH
HM6 1 1 6 P 3-1
VH
LH0080
A/— 1
VH
M58725P-15
VH
M74LSOO/-1
VH
M74LS02
/- 1
VH
M74LS03
/- 1
VH
M74LS04
/— 1
VH
M74LS08
/— 1
VH
M74LS10/-1
VH M 7 4 L S 1 2 5-1
VH
M74LS138-1
VH
M74LS139-1
VH
M74LS14
/— 1
VH M 7 4 1 S 1 5 7— 1
VH
M74LS166-1
VH
M74LS244-1
VH
M74LS245-1
VH
M74LS273—
1
VH
M74LS3
2/— 1
PRICE
RANK
AH
AB
A
K
AZ
A A
AB
AC
AC
AC
A
T
AW
A
D
AD
A
E
A
E
AG
A
Z
AK
AR
A
E
AU
AU
AU
AT
AC
AC
AD
A
S
A
A
A A
A A
AB
AB
AB
AB
AC
AC
AB
AB
AB
A
A
A
A
A
B
A A
AB
A
B
AB
AD
AU
BN
A
X
A
Z
A
E
A
E
A
E
A
E
A
E
A E
A
H
A
K
A
L
AM
A
K
A
L
AM
AR
AP
A
F
NEW
MARK
N
N
L
N
N
N
PART
RANK
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
B
B
B
C
B
B
B
B
C
C
B
A
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
DESCRIPTION
Connector
"A"
angle
Holder
Connector
Connector
Connector
Connector
Connector
Connector
Connector
Connector
Connector
1C
socket (14pm)
1C
socket (16pm)
1C
socket
(24pm)
1C
socket (28pm)
1C
socket
(40pm)
DipSW
Dip SW
DipSW
Capacitor
X-Tal
(3932MHz)
X-Tal
(32MHz)
X-Tal
(245MHz)
X-Tal
(32KHz)
Block resistor (1/8W 33KOX4)
Block
resistor (1/8W
68KOX4)
Block resistor (33KQX
8
1/8W ±10%)
Battery
Capacitor (50V 10PF)
Capacitor (50WV 33PF)
Capacitor (50V 47PF)
Capacitor (16WV
10,,
F)
Capacitor (16WV lOO^F)
Capacitor (16WV 33WF)
Capacitor (25WV
10j.F)
Capacitor (25WV 100,uF)
Capacitor
(25WV
220,/F)
Capacitor
(50WV
1
O^F)
Capacitor (50WV
33^F)
Capacitor (50WV
4
7^F)
Capacitor (50WV
680PF)
Capacitor (50WV 680PF)
Capacitor (50WV 220PF)
Capacitor (50WV
560PF)
Capacitor
(12WV
0
10,,
F)
Capacitor
(1 2WV
OlO^F)
Capacitor (25WV OOIO^F)
Diode
(1S1588L1)
1C
1C
1C
1C
1C
1C
1C
1C
1C
1C
1C
1C
1C
1C
1C
1C
1C
1C
1C
1C
MZ-3500
,5!
CPU PWB
NO
69
70
71
72
74
75
76
77
78
79
80
81
82
83
84
85
86
87
89
90
91
92
93
94
95
%
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
PARTS
CODE
VH
M74LS367-1
VH
M74LS373—
1
VH
M74LS7
4/- 1
VH
M74LS7
5/— 1
V
H M 7 4 L S 9 3/- 1
VH
SN7404
N/- 1
VH S N 7 4 0 6 N/- 1
VH
SN74157N-1
VH
SN75188N-1
VH
SN75189A—
1
VH
SP6102C002
VH
SP6102C003
VH
SP6102R001
VH
TA7313AP—
1
VH
TC4049
P/— 1
VH
UP01990ACC
VH
UPD7220D—
1
VH
UPD8255/-1
V
H 276 4
//AC
0 1
VH
2764
//AC02
VH
276 4
//AC
0 3
V
H 276 4
//AC
0 4
VH
4164— 150—
H
V
H 8 2 5 1 A
C//—
1
V
H
8253
////—
1
VHPGL3PR
2//—
1
VRD-ST2EY331J
V
R D — S T 2 E Y 4 7 0 J
VRD-RV2EYOOOJ
V
RD-ST
2 E Y 1 0 1 J
VRD-ST2EY102J
V
RD-S
T 2 E Y 1 0 3 J
V
R
D-ST
2 E Y 1 0 4 J
VRD-ST2EY222J
VRD-ST2EY331J
VRD-ST2EY332J
VRD-ST2EY333J
VRD-ST2EY561J
VRD—
RV2EY682J
VRD-SU2EY152J
VRD-SU2EY470J
VRD-SU2EY681J
VRD-SU2EY821J
VRD—
SU2EY822J
VS2SC458
KC/-1
XBPSD30P06KSO
XBPSD30P08000
PRICE
RANK
A
H
AQ
AG
A
E
A
K
A
F
AG
AM
AM
A
P
BG
BG
BP
A
L
AN
AT
B S
A Y
LM
LM
LM
L
M
A2
A
Y
B A
A
E
A A
A A
A A
A A
A
A
A A
A A
A A
A A
A
A
A
A
A A
A A
A
A
A A
A A
A A
A A
AD
A
A
A A
NEW
MARK
PART
RANK
B
B
B
B
B
B
B
B
L B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
B
C
C
DESCRIPTION
1C
1C
1C
1C
1C
1C
1C
1C
1C
1C
1C
1C
1C
1C
1C
1C
1C
1C
LSI
PROM-IPL
LSI
PROM-CG
(English)
LSI
PROM-CG (Germany)
LSI
PROM-CG
(French)
1C
1C
1C
Photo
transistor
GL3PR2
Resistor
(1/4W
3300
J)
Resistor
(EX
110V.220V
onjy) (1/4W
47O
±5%)
Resistor
(1/4W ±5%)
Resistor
(1/4W
lOOO
±5%)
Resistor
(1/4W 1KO)
Resistor
(1/4W 10KO)
Resistor
(1/4W 100KQ ±5%)
Resistor
(Japan
only) (1/4W
2 2KD
±5%)
Resistor
(1/4W 330(1
J)
Resistor
(1/4W 33KD ±5%)
Resistor
(1/4W 33KO)
Resistor
(1/4W 5600
J)
Resistor
(1/4W
6
8K(1 ±5%I
Resistor
(1/4W
1
5Kfl
J)
Resistor
(47fi)
Resistor
(1/4W 680(1
J)
Resistor
(1/4W
8200
±5%)
Resistor
(1/4W
8
2KO
±5%)
Transistor
Screw
Screw
[6]
Power
supply
unit
NO
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
PARTS
CODE
OAE3021690
4
//
OAE30263025
//
OAE30263025
//
OAE30109066
//
OAE30109066
//
OAE30258784
//
OAE30221517
//
OAE30221520
//
OAE30263025
//
OAE30362052
//
OAE30263025
//
OAE30263025
//
OAE30263025
//
JDAE30109066
//
OAE30109066//
OAE30279844
//
OAE30167370
//
OAE30221546
//
OAE30263025
//
OAE30269430
//
OAE30261658//
OAE30121947
//
OAE30499831//
OAE30362081//
PRICE
RANK
A
S
A
D
A
F
A
E
A
E
A X
A
L
AH
A
D
AD
AD
AD
AD
A
E
A
E
A
H
A
T
A
H
A
D
A Y
A
D
A
F
1_J\D
A
D
NEW
MARK
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
PART
RANK
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
DESCRIPTION
1C
(UPC78M12H)
[M001]
Transistor
(2SC1815-Y)
[Q001]
Transistor
(2SC1815-Y) [Q002]
Transistor
(2SA733-Q) [Q003]
Transistor
(2SA733-Q)
[0004]
Transistor
(2SC2750-L)
[Q005]
Transistor
(2SA965-Y) [Q006]
Transistor
(2SC1 627-
Y)
[0007]
Transistor
(2SC1815-Y) [Q008]
Transistor
(2SA1015-Y) [Q009]
Transistor
(2SC1815-Y)
[Q010]
Transistor
(2SC1815-Y) [Q011]
Transistor
(2SC1815-Y) [Q012]
Transistor
(2SA733-Q) [Q013]
Transistor
(2SA733-Q) [Q014]
Transistor (2SA1
020-
Y)
[Q015J
Transistor
(2SC2334-L) [Q016]
Transistor
(2SC2655-Y) [Q017]
Transistor
(2SC1815-Y) [Q018]
Transistor
(SI
OSC4M)
[DU001]
Zener
diode
(H29L-A1) [D001]
Diode (1S234-8H)
[D002]
Zener
diode
(HZ11L-B1) [D003]
Zener
diode
(HZ7L-C2)
[D004]
MZ-3500
[6j
Power supply
unit
NO.
25
26
27
28
29
30
31
32
33
34
35
36
37
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
PARTS
CODE
OAE30121921XX
OAE30121921
//
OAE30379029//
OAE30121921//
OAE30121921
//
OAE30200774
//
OAE30200774
//
OAE30379029XX
OAE30250326
//
OAE30121921XX
OAE30159870
//
OAE30121866//
OAE30165262
//
OAE30511353
//
OAE30272391
//
OAE30509721
//
OAE30509721
//
OAE30523370
//
OAE30143572
//
OAE30143572
XX
OAE30120650
//
OAE30169653
//
OAE30227236
//
OAE30120524
//
OAE30129460
//
OAE30129460
//
OAE30129460XX
OAE30280671
XX
OAE30165576
//
OAE30165576
XX
OAE30169653XX
OAE30169653XX
OAE30120524
XX
OAE30164409
XX
OAE30120456XX
OAE30
29460
XX
OAE30
20456
XX
OAE30
70008
XX
OAE30
70008
XX
OAE30
13525
XX
OAE30
95258
XX
OAE30
20524
XX
OAE30
20524
XX
OAE30
64409
XX
OAE30
16729
XX
OAE30
1672
9XX
V
R S — P T 3 A B 1 0 2 J
VR
S-PT3
DB 1 5 2 K
V
RD-ST
2 E Y 1 5 2 J
V
RD-ST
2 E Y 3 3 3 J
V
RD-ST
2 E Y 3 3 3 J
V
R D — S T 2 E Y 1 5 2 J
OAE30491169
XX
VRD-ST
2 E Y 1 0 0 J
VRD-ST
2 E Y 1 0 2 J
OAE30508049
XX
VRD-ST2EY4R7J
OAE30501868
XX
OAE30143284
XX
VRD-ST
2 E Y 3 3 1 J
V
R
S-PT
3 AB 1 0 0 J
V
RD-ST
2 E Y 2 7 2 J
V
RD-ST
2 E Y 1 0 2 J
VRD-ST2EY391J
VRD-ST
2 E Y 4 7 1 J
VRD-ST
2 E Y 3 3 1 J
VRD-ST
2 E Y 1 8 2 J
VRD-ST
2 E Y 1 5 2 J
VRD-ST
2 E Y 2 2 2 J
VRD-ST
2 E Y 1 0 2 J
V
RD-ST
2 E Y 2 2 2 J
VRD-ST
2 E Y 6 8 1 J
VRD-ST
2 E Y 2 2 0 J
VRD—
ST2EY1
02J
VRD-ST
2 E Y 1 0 2 J
VRD-ST2EY331J
VRD—
ST2EY33
1J
OAE30490940
XX
VRD—
ST2EY390J
V
RD-S
' 2 E Y 1 5 1 J
PRICE
RANK
AC
AC
AD
AC
AC
AG
AG
AD
AG
AC
AY
AN
AH
AP
AP
AG
AG
AP
AC
AC
AG
AC
AD
AC
AC
AC
AC
A
E
AG
AG
AD
AD
AC
AC
AC
AC
AC
AG
AG
AG
AG
AC
AC
AC
AK
AK
AC
AB
A
A
A
A
A A
A A
A E
A A
A
A
AG
AB
AC
AC
A
A
AB
AA
A A
A A
A
A
A
A
A
A
A
A
A A
A
A
A A
A A
A A
A A
A A
A A
A A
A
E
A A
A A
NEW
MARK
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
PART
RANK
B
B
B
B
B
B
B
B
B
B
B
B
B
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
DESCRIPTION
Diode (1S2076A-FEC)
[D005]
Diode (1S2076A-FEC)
[D006]
Zener
diode
(HZ7L-
62)
[D0071
Diode
(1S2076A-FECJ [D008J
Diode (1S2076A-FEC)
[D'.'09j
Diode
I30DF-1)
[D010]
DiodeI30DF
-_1)
[D011]
Zener
diode
(HZ7L-
32}
[D012]
Diode
{10DF-_1J
[D013]
Diode (1S2076A-FEC)
[0014]
Diode
(SI
OVBIQ}
[RC001]
Diode
QB4B1)
[RC002]
Thyristorip3P05M)
[TH001]
Capacitor
(0
22^,F 250V) [C001
]
Capacitor
(O.ljiF
125V)
[C001]
Capacitor (DE1107E222M250VAC)
[C0021
Capacitor (DE1107E222M250VAC)
[C003]
Capacitor (KM50VRSN10000HR)
[C004J
Capacitor (50F2S102K)
[COOS]
Capacitor (50F2S102K)
[C006]
Capacitor (50F2S154K)
[C007]
Capacitor
(50ULB10-M)
[COOS]
Capacitor
(10ULB220-M)
[C009]
Capacitor (50F2S223K)
[C011]
Capacitor
(50F2S103K)
[C012]
Capacitor (50F2S103K) C013]
Capacitor (50F2S103K) C014]
Capacitor
£35ULB33-M)
[C015]
Capacitor
(10ULB1000-M)
[C016]
Capacitor
(10ULB1000-M)
C017]
Capacitor
(50ULB10-M)
.0018]
Capacitor
(50ULB10-M)
C019]
Capacitor
(50F2S223K)
[C020]
Capacitor
(50F2S332K) [C021
.
Capacitor (50F2S472K)
[C022.
Capacitor (50F2S103K)
[C023.
Capacitor
(50F2S472K)
[C024.
Capacitor
(25ULB330-M)
[C025]
Capacitor
(25ULB330-M)
C026.
Capacitor
(35ULB220-M)
C027!
Capacitor
(25ULB220-M)
:C028!
Capacitor (50F2S223K)
C029]
Capacitor (50F2S223K)
[C030]
Capacitor
(50F2S332K)
[C031]
Resistorr (TMIOK(PVB)B
2Kfl)
[RV001]
Resistorr (TMIOK(PVB)B 2KQ) [RV002]
Resistorr
(RSI
FB
IKOJ)
[R001]
Resistorr
(RS2FB 1.5KOJ)
.R002]
Resistorr (CR25 1.5KOJJ
R003]
Resistorr (CR25
33KOI)
[R004]
Resistorr
(CR25 33KHJ)
[R005]
Resistorr
(CR25 1.5KHJ)
[R006]
Wire
resistor
[R007]
Resistor
(CR25
lOflJ
FJ
[R008]
Resistor
(CR25 1KOJ)
[R009]
Resistor
(MDS
05N
5.6fl)
[R010]
Resistor
(CR37
4.7OJ)
[R012]
Resistor
(RS1FB
63OI)
[R013]
Resistor (MR25 47DG)
[R014]
Resistor (CR25
330OJ
F)
[R015J
Resistor
{RSI
FB
lOflJ)
[R016
Resistor
(CR25
2.7KHJ
F)
[R01
7
Resistor
(CR25
IKflJ
F)
[R018
Resistor
(CR25
390HJ
F)
[R019]
Resistor (CR25
470fU)
[R020]
Resistor
(CR25
330flJ
F}
[R021
]
Resistor [CR25 1.8KOJ
F)
[R022]
Resistor (CR25 1.5KOJ
F)
[R023]
Resistor
(CR25
2.2KC2J
F)
[R024]
Resistor (CR25 1KOI
F)
[R025]
Resistor
(CR25
2.2KfiJ
F)
[R026]
Resistor
(CR25
680HJ)
[R027]
Resistor
(CR25
22OI)
[R028]
Resistor
(CR25 1KOJ
F)
[R029]
Resistor
(CR25 1KOJ)
[R030]
Resistor
(CR25
330nj)
[R031
Resistor
(CR25 330OJ)
[R032]
Wire
resistor [R033]
ResistoriCR25 39DJ
F)
[R034]
Resistor
(CR25
150OJ
F)
[R035]
M2-3500
J9,
MZ1K02,1K03,1K04,1K05 (Key unit)
19
19
i
<,
MZ-3500
PARTS CODE
VH
i 4 1
64-1 50-H
//
VH
i
825
1
AC//-1
VH
i
8253////-1
VHPGL3PR2//-1
VHPGL9PR2//-1
//
VRO-RV2EYOO
0 J
VRD-RV2EY
1 0 1 J
VRD-RV2EY682
J
VRO-ST2EY
100 J
H
VRD-ST2EY
1 0 1 J
//
//
//
VRD-ST2EY1
02 J
//
//
//
//
//
VRD-ST2EY1
03 J
//
//
VRO-ST2EY
1 04 J
//
VRO-ST2EY1
51 J
VRD-ST2EY152
J
//
II
VRD-ST2EY1
82 J
VRD-ST2EY220
J
//
VRD-ST2EY222
J
//
ii
H
VRO-ST2EY2
72 J
VRD-ST2EY33
1 J
//
//
//
//
//
//
//
//
VRD—
ST2EY332
J
H
ii
ti
VRD-ST2EY333
J
//
//
//
VRD-ST2EY390J
//
VRD-ST2EY391
J
VRD-ST2EY392
J
VRD-ST2EY4R7
j
VRD-ST2EY4
70 J
VRD-ST2EY47
1 J
n
VRD-ST2EY472J
//
VRD-ST2EY56
1 J
VRD-ST2EY68
1 J
ii
II
H
VRD-SU2EY
1 0 1 J
VRD-SU2EY1
52 J
VRD-SU2EY39
1 j
VRD-SU2EY470
J
//
VRD-SU2EY68
1 J
VRD-SU2EY8
2 1 J
VRD-SU2EY8
2 2 J
//
NO
5- 89
11- 11
5- 90
5- 91
5- 92
1-
8
9- 6
5- 95
11- 12
5- 105
6- 77
6- 105
5-
%
8- 45
9- 126
10- 27
5- 97
6- 78
6- 86
6- 93
6- 97
6- 98
5- 98
9- 127
10- 28
5- 99
9- 128
6- 103
6- 72
6- 75
6- 91
6- 90
6-
%
6- 114
5- 100
6- 92
6- 94
9- 129
6- 85
5- 93
5- 101
6- 83
6- 89
6- 99
6- 100
6- 106
8- 46
10- 29
5- 102
8- 47
9- 130
10- 30
5- 103
6- 73
6- 74
9- 131
6- 102
6- 113
6- 87
6- 115
6- 80
5- 94
6- 88
9- 132
6- 107
8- 48
5- 104
6- 95
6- 109
6- 110
9- 133
8- 49
5- 106
8- 50
5- 107
10- 31
5- 108
5- 109
5- 110
8- 51
PRICE
RANK
AZ
A2
AY
BA
ft
AC
AC'
A A
A A
A A
AA
A
A
A
A
A A
A A
A A
A
A
A
A
A A
A A
A A
A A
A
A
A
A
A
A
A A
A A
A A
A A
A A
A A
A A
A A
A A
AA
AA
A A
AA
A A
AA
AA
A A
A A
A A
A A
A A
A A
A A
A
A
A
A
A A
A A
A A
A A
A
A
A
A
A
A
A A
A A
A A
AB
A
A
A A
AA
AA
AA
AA
A A
A A
A
A
A A
A
A
A A
A A
A A
A
A
A A
A
A
A
A
A A
NEW
MARK
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
PART
RANK
B
B
B
B
B
B
B
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
c
[_
1
PARTS
CODE
VRD-SU2
E Y8 24 J
VRN-RT2
EK 1 0 2 F
VRN-RT2EK
1 05F
VRN-RT2
EK 1 2 3F
VRN-RT
2 EK2 2 2F
VRN-RT
2EK4
7 2F
VRN-RT2EK9
1 2F
VRS-PT3AB1
00 J
//
VRS-PT3AB1
02 J
VRS-PT3DB1
02 J
VRS-PT3DB1
52K
VRS-PT3DB680K
VRS-PT3LB330
J
VSP0080P-608N
VS2SA673-C/-1
VS2SA673-D1-1
VS2SC4
58KC/-1
[X]
XBBSC26P04000
XBBSC30P06000
XBPSD30P06KSO
//
//
XBPSD3
OPO
6KOO
//
XBPSD30P08KSO
XBPSD30P08000
XBPSD30P1
0000
II
XBPSD30P30KSO
XBPSD40P06KSO
XBPSD40P06KOO
XBPSD40P06000
XBPSD4
OP08KSO
XBPSF3
OP06KOO
XBTSC4
OP06000
XBTSD30P04000
XBTSF40P08000
XCPSD40P12000
XNESD30-24000
n
II
XUPSC26P06000
XUPSC30P08000
XUPSD26P06000
[0 1
OAE1
0447
1
OO//
OAE10447
1
13//
OAE104803
87//
OAE105006
23//
OAE1050491
7//
OAE1
0504933//
OAE1
0507778//
OAE1050778
I//
OAE
105 1 84 8 2//
OAE
10526940//
OAE1
052 798 I//
OAE
1 053
1087//
OAE
1
0538909//
OAE
1
05389
1 2//
OAE1054348
6//
OAE2049044
5//
OAE205
10574//
OAE205
1
2336/X
OAE2052
1
194//
OAE20527978//
OAE22830579//
OAE
2 2 83
1688//
OAE
2 3 594
924//
OAE3010906
6//
n
II
n
OAE
30 1 1 67
29//
u
OAE301204
56//
//
OAE
30 1
20524//
//
NO
B-
52
6- 111
8 53
8-
54
6-
112
8-
55
8-
56
6-
84
6-
108
6-
70
6-
104
6- 71
10-
32
1-
39
2-
7
8-
57
10-
33
5- 111
2-
20
2- 21
2-
22
5-
112
9- 12
2-
8
9-
134
1-
27
5- 113
2-
30
8-
58
1-
38
1-
28
1-
30
10-
4
2-
30
1-
16
1-
31
10-
34
1-
32
1-
33
2- 31
2-
33
8-
59
9- 21
9-
22
2-
23
6-
125
6-
126
6-
127
6-
129
6-
138
6-
139
6-
130
6- 131
6-
128
6- 133
6-
132
6-
140
6-
147
6-
148
6-
134
6- 142
6-
137
6-
145
6- 141
6-
144
6-
136
6-
143
6-
146
6-
4
6-
5
6-
14
6- 15
6-
68
6-
69
6-
58
6-
60
6-
47
6-
56
PRICE
RANK
A
A
AB
A
A
AB
AB
AB
AC
AB
AB
AC
AB
AB
AB
AC
AN
AE
AC
AD
AA
AA
AA
AA
AA
AA
A A
A A
A
A
AA
A A
AA
AA
AA
AA
A A
A A
A
A
AA
A A
A A
AA
AA
A
A
AA
AA
AA
AF
AD
AF
AM
AR
AW
BQ
AQ
AV
BM
AX
AQ
AW
AW
AY
AC
AC
AM
A A
AG
AC
AR
AC
AE
AE
AE
AE
AK
AK
AC
AC
AC
AC
NEW
MARK
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
PART
ANK
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
B
B
B
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
c
c
c
c
c
c
c
c
c
c
c
c
c
c
c
c
c
c
c
c
c
c
c
c
c
c
c
c
c
c
c
c
c
B
B
B
B
C
C
c
c
c
c
17
MZ-3500
PARTS
CODE
OAE30
1
20524//
//
OAE30
1 206 5 O//
OAE3012186
6//
OAE30121921//
//
//
//
//
OAE3012194
7//
OAE30
1
29460//
//
//
//
OAE30
143284//
OAE3014357
2//
//
OAE30
1
59870//
OAE30
164409//
//
OAE30
1
6526
2//
OAE301655
7 6//
//
OAE30
1
67370//
OAE30
1
69653/7
//
;/
OAE3
0 1 7
0008//
//
OAE30
1
95258/7
OAE30200774//
//
OAE302
13525//
OAE302
1 69 0 4//
OAE3022151
7//
OAE30221520//
OAE3
02 2 1
546//
OAE30227236//
OAE30250326//
OAE30258784//
OAE3026
1
658//
OAE3026302
5//
//
//
//
//
//
//
OAE3026943
O//
OAE30272391//
OAE30279844//
OAE3028067
I//
OAE30362052//
OAE30362081//
OAE30379029//
//
OAE30490940//
OAE3
049 1 1
69//
OAE3049983
I//
OAE30500979//
OAE30500982//
OAE3050
1868//
OAE3050804
9//
OAE30508528//
OAE3050853
I//
OAE30508557//
OAE30
50856
O//
//
OAE30509721//
//
OAE30509941//
OAE305
1 1 3
53//
OAE305
1 54 6 9//
OAE305233
7 O//
OAE30
564
740//
OAE30566353//
OOPA7KF09
5C//
OOPA7KF10
2B//
0
OPA7KF
1
03B//
NO
6-
65
6-
66
6-
44
6-
36
6-
25
6-
26
6-
28
6-
29
6-
34
6-
22
6-
48
6-
49
6-
50
6-
59
6-
82
6-
42
6-
43
6-
35
6-
57
6-
67
6-
37
6-
52
6-
53
6-
17
6-
45
6-
54
6-
55
6- 61
6-
62
6-
64
6-
30
6- 31
6-
63
6- 1
6-
7
6-
8
6-
18
6-
46
6-
33
6-
6
6- 21
6-
2
6-
3
6-
9
6- 11
6- 12
6- 13
6- 19
6-
20
6-
38
6- 16
6- 51
6- 10
6-
24
6-
27
6-
32
6- 101
6- 76
6-
23
6- 116
6- 117
6- 81
6-
79
6-
118
6- 118
6-
120
6- 121
6-
123
6-
39
6-
40
6- 116
6-
38
6- 119
6-
41
6-
124
6 122
9-
51
9- 51
9- 51
PRICE
RANK
AC
AC
AG
AN
AC
AC
AC
AC
AC
AF
AC
AC
AC
AC
AC
AC
AC
AY
AC
AC
AH
AG
AG
AT
AC
AD
AD
AG
AG
AG
AG
AG
AG
AS
A L
AH
AH
AD
AG
AX
AD
AD
AF
AD
AD
AD
AD
AD
AY
AP
AH
AE
AD
AD
AD
AD
AE
AE
AD
AH
AW
AC
AG
BP
BY
AX
AL
AX
AG
AG
AG
AP
AR
AP
A
P
AX
BX
BX
BX
OOPA7KF104
B// 9 51 B X
NEW
MARK
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
PART
RANK
C
C
C
B
B
B
B
B
B
B
C
C
C
C
C
C
C
B
C
C
B
C
C
B
C
C
C
C
C
C
B
B
C
B
B
B
B
C
B
B
B
B
B
B
B
B
B
B
B
C
B
C
B
B
B
B
C
B
A
B
C
C
B
B
C
C
C
C
C
A
C
B
C
C
C
C
C
C
C
PARTS
CODE
OOPA8KF
1 1 5 A//
OOPCH52203
A//
OOPKCC
1090
1-Z
OOPKFL10901-Z
OOPKFL1
1 90 1-Z
OOP08KF018
B//
OOP16KF005
A//
0
0 P 1 9 K F 0 0 5 A//
0
0 P 1 9 K F 0 0 7 A//
OOP21KF008
A//
OOP21KF009
A//
0
0 P 2 1 K F 0 1 3 A//
0
0 P 2 1 K F 0 1 4 A//
OOP23KF001
A//
OOP23KF011
B//
OOP23KF014
A//
OOP25KF006
B//
OOP25KF007
A//
OOP25KF008
A//
0
0 P 2 7 K F 0 2 1 A//
OOP29KF006
B//
OOP29KF007
B//
OOP80D9E43000
OOP85Y2K56000
OOP85Y2K60000
NO
9- 50
9- 39
9- 27
9- 25
9- 26
9- 28
9- 37
9- 35
9- 36
9- 31
9- 33
9- 32
9- 34
9- 46
9- 29
9- 47
9- 30
9- 48
9- 49
9- 38
9- 44
9- 45
9- 42
9- 40
9- 41
PRICE
RANK
AT
AC
AG
AG
AH
AN
AC
AC
AC
AD
AF
AD
AC
AC
AL
AC
AM
AC
AC
AC
AK
AH
AQ
AH
AH
NEW
MARK
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
PART
RANK
C
C
B
B
B
C
C
C
C
C
C
C
C
C
C
C
C
C
C
B
C
C
C
C
C
-
18-
SHARP
CORPORATION
Industrial
Instruments Group
Reliability
&
Quality Control Department
Yamatokoriyama,
Nara
639-11,
Japan
1983
January
Printed
in
Japan
s

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