Siemens Simatic S7 300 Cpu 31Xc And 31X Users Manual 31x, Technical Data

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2015-02-05

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Preface

SIMATIC
S7-300
CPU 31xC and CPU 31x,
Technical data
Manual

This manual is part of the documentation package
with the order number: 6ES7398-8FA10-8BA0

Edition 08/2004
A5E00105475-05

Guide to the S7-300
documentation

Operating and display
elements

Communication

Memory concept

Cycle and reaction times

Technical data of CPU 31xC

Technical data of CPU 31x

Appendix

Safety Guidelines
This manual contains notices which you should observe to ensure your own personal safety as well as to avoid
property damage. The notices referring to your personal safety are highlighted in the manual by a safety alert
symbol, notices referring to property damage only have no safety alert symbol.

Danger
indicates an imminently hazardous situation which, if not avoided, will result in death or serious injury.
Warning
indicates a potentially hazardous situation which, if not avoided, could result in death or serious injury.
Caution
used with the safety alert symbol indicates a potentially hazardous situation which, if not avoided, may
result in minor or moderate injury.
Caution
used without safety alert symbol indicates a potentially hazardous situation which, if not avoided, may
result in property damage.
Notice
used without the safety alert symbol indicates a potential situation which, if not avoided, may result in
an undesirable result or state.
When several danger levels apply, the notices of the highest level (lower number) are always displayed. If a
notice refers to personal damages with the safety alert symbol, then another notice may be added warning of
property damage.

Qualified Personnel
The device/system may only be set up and operated in conjunction with this documentation. Only qualified
personnel should be allowed to install and work on the equipment. Qualified persons are defined as persons who
are authorized to commission, to earth, and to tag circuits, equipment and systems in accordance with
established safety practices and standards.

Intended Use
Please note the following:

Warning
This device and its components may only be used for the applications described in the catalog or
technical description, and only in connection with devices or components from other manufacturers
approved or recommended by Siemens.
This product can only function correctly and safely if it is transported, stored, set up and installed
correctly, and operated and maintained as recommended.
Trademarks
All designations marked with ® are registered trademarks of Siemens AG. Other designations in this
documentation might be trademarks which, if used by third parties for their purposes, might infringe upon the
rights of the proprietors.

Copyright Siemens AG ,2004.All rights reserved
Reproduction, transmission or use of this document or its contents is not permitted without
express written authority. Offenders will be liable for damages. All rights, including rights
created by patent grant or registration of a utility model or design, are reserved.

Disclaimer of Liability
We have checked the contents of this manual for agreement with the hardware and
software described. Since deviations cannot be precluded entirely, we cannot guarantee
full agreement. However, the data in the manual are reviewed regularly, and any
necessary corrections will be included in subsequent editions. Suggestions for
improvement are welcomed.

Siemens AG
Automation and Drives Group
P.O. Box 4848, D-90327 Nuremberg (Germany)

Siemens AG 2004
Technical data subject to change

Siemens Aktiengesellschaft

Order No. A5E00105475-05

Preface
Purpose of the Manual
This manual contains all the information you will need concerning the configuration,
communication, memory concept, cycle, response times and technical data for the CPUs.
You will then learn the points to consider when upgrading to one of the CPUs discussed in
this manual.

Required basic knowledge
• To understand this manual, you require a general knowledge of automation engineering.
• You should also be accustomed to working with STEP 7 basic software.

Area of application
Table 1-1

Application area covered by this manual

CPU
CPU 312C

Convention:
CPU designations:

Order number

CPU 31xC

6ES7312-5BD01-0AB0

as of version
Firmware

Hardware

V2.0.0

CPU 313C

6ES7313-5BE01-0AB0

V2.0.0

CPU 313C-2 PtP

6ES7313-6BE01-0AB0

V2.0.0

CPU 313C-2 DP

6ES7313-6CE01-0AB0

V2.0.0

CPU 314C-2 PtP

6ES7314-6BF01-0AB0

V2.0.0

CPU 314C-2 DP

6ES7314-6CF01-0AB0

V2.0.0

CPU 312

CPU 31x

6ES7312-1AD10-0AB0

V2.0.0

CPU 314

6ES7314-1AF10-0AB0

V2.0.0

CPU 315-2 DP

6ES7315-2AG10-0AB0

V2.0.0

CPU 315-2 PN/DP

6ES7315-2EG10-0AB0

V2.3.0

CPU 317-2 DP

6ES7317-2AJ10-0AB0

V2.1.0

CPU 317-2 PN/DP

6ES7317-2EJ10-0AB0

V2.3.0

Note
The special features of the CPU 315F-2 DP (6ES7 315-6FF00-0AB0) and CPU 317F-2 DP
(6ES7 317-6FF00-0AB0) are described in their Product Information, available on the Internet
at
http://www.siemens.com/automation/service&support, article ID 17015818.

CPU 31xC and CPU 31x, Technical data
Manual, Edition 08/2004, A5E00105475-05

iii

Preface

Note
There you can obtain the descriptions of all current modules. For new modules, or modules
of a more recent version, we reserve the right to include a Product Information containing
latest information.

Approvals
The SIMATIC S7-300 product series has the following approvals:
• Underwriters Laboratories, Inc.: UL 508 (Industrial Control Equipment)
• Canadian Standards Association: CSA C22.2 No. 142, (Process Control Equipment)
• Factory Mutual Research: Approval Standard Class Number 3611

CE label
The SIMATIC S7-300 product series satisfies the requirements and safety specifications of
the following
EC Directives:
• EC Directive 73/23/EEC "Low-voltage directive"
• EC Directive 89/336/EEC "EMC directive"

C tick mark
The SIMATIC S7-300 product series is compliant with AS/NZS 2064 (Australia).

Standards
The SIMATIC S7-300 product series is compliant with IEC 61131-2.

CPU 31xC and CPU 31x, Technical data
Manual, Edition 08/2004, A5E00105475-05

Preface

Documentation classification
This manual is part of the S7-300 documentation package.
Name of the manual

Description

YOU ARE READING the Manual
• CPU 31xC and CPU 31x, Technical data

Control and display elements, communication,
memory concept, cycle and response times,
technical data

Reference Manual
• CPU data: CPU 312 IFM – 318-2 DP

Control and display elements, communication,
memory concept, cycle and response times,
technical data

Operating Instructions
• S7-300, CPU 31xC and CPU 31x: Installation

Configuration, installation, wiring, addressing,
commissioning, maintenance and the test
functions, diagnostics and troubleshooting.

Installation Manual
• S7-300 Automation System: Installation: CPU
312 IFM – 318-2 DP

Configuration, installation, wiring, addressing,
commissioning, maintenance and the test
functions, diagnostics and troubleshooting.

System Manual

Basic information on PROFINET:

PROFINET System Description

Network components, data exchange and
communication, PROFINET I/O, Component
based Automation, application example of
PROFINET I/O and Component based
Automation

Programming Manual

Guideline for the migration from PROFIBUS DP
to PROFINET I/O.

From PROFIBUS DP to PROFINET IO
Manual
• CPU 31xC: Technological functions
• Examples

Description of the individual technological
functions Positioning, Counting. PtP
communication, rules

Reference Manual
• S7-300 Automation System: Module data

Descriptions of the functions and technical data
of signal modules, power supply modules and
interface modules.

Instruction List
• CPU 312 IFM – 318-2 DP
• CPU 31xC and CPU 31x

List of CPU instruction resources and the
relevant execution times. List of executable
blocks.

Getting Started

The example used in this Getting Started
guides you through the various steps in
commissioning required to obtain a fully
functional application.

The following Getting Started editions are available
as a collective volume:
• CPU 31x: Commissioning
• CPU 31xC: Commissioning
• CPU 31xC: Positioning with analog output
• CPU 31xC: Positioning with digital output
• CPU 31xC: Counting
• CPU 31xC: Rules
• CPU 31xC: PtP communication
• CPU 31x-2 PN/DP: Commissioning a
PROFINET IO subnet

CPU 31xC and CPU 31x, Technical data
Manual, Edition 08/2004, A5E00105475-05

The CD contains examples of the technological
functions

Preface
Additional information required:
Name of the manual

Description

Reference Manual

Description of the SFCs, SFBs and OBs.

System software for S7-300/400 system and standard
functions

This manual is part of the STEP 7
documentation package. For further
information, refer to the STEP 7 Online
Help.

Manual

Description of Industrial Ethernet
networks, network configuration,
components, installation guidelines for
networked automation systems in
buildings, etc.

SIMATIC NET: Twisted Pair and Fiber-Optic Networks

Manual
Component-based Automation: Configuring systems with
SIMATIC iMap
Manual

Description of the engineering software
iMAP
Programming with STEP 7

Programming with STEP 7 V5.3
Manual
SIMATIC communication

Basics, services, networks,
communication functions, connecting
PGs/OPs, engineering and configuring in
STEP 7.

Recycling and Disposal
The devices described in this manual can be recycled, due to their ecologically compatible
components. For environment-friendly recycling and disposal of your old equipment, contact
a certified disposal facility for electronic scrap.

CPU 31xC and CPU 31x, Technical data
Manual, Edition 08/2004, A5E00105475-05

Table of contents
Preface ...................................................................................................................................................... iii
1

Guide to the S7-300 documentation ....................................................................................................... 1-1

Operating and display elements ............................................................................................................. 2-1

2.1
2.1.1

Operating and display elements: CPU 31xC ............................................................................. 2-1
Status and Error Indicators: CPU 31xC ..................................................................................... 2-4

2.2
2.2.1
2.2.2
2.2.3
2.2.4

Operating and display elements: CPU 31x................................................................................ 2-5
Operating and display elements: CPU 312, 314, 315-2 DP: ..................................................... 2-5
Operating and display elements: CPU 317-2 DP ...................................................................... 2-7
Operating and display elements: CPU 31x-2 PN/DP ................................................................ 2-9
Status and error displays of the CPU 31x................................................................................ 2-11

Communication....................................................................................................................................... 3-1
3.1
3.1.1
3.1.2
3.1.3
3.1.4

Interfaces ................................................................................................................................... 3-1
Multi-Point Interface (MPI) ......................................................................................................... 3-1
PROFIBUS DP........................................................................................................................... 3-2
PROFINET (PN)......................................................................................................................... 3-3
Point to Point (PtP) .................................................................................................................... 3-5

3.2
3.2.1
3.2.2
3.2.3
3.2.4
3.2.5
3.2.6
3.2.7
3.2.8
3.2.9
3.2.10
3.2.10.1
3.2.10.2
3.2.10.3
3.2.10.4
3.2.10.5

Communication services............................................................................................................ 3-6
Overview of communication services ........................................................................................ 3-6
PG communication..................................................................................................................... 3-7
OP communication..................................................................................................................... 3-7
Data exchanged by means of S7 basic communication............................................................ 3-7
S7 communication ..................................................................................................................... 3-8
Global data communication (MPI only)...................................................................................... 3-9
Routing..................................................................................................................................... 3-10
PtP communication .................................................................................................................. 3-15
Data consistency...................................................................................................................... 3-16
Communication via PROFINET (only CPU 31x-2 PN/DP) ...................................................... 3-16
PROFINET IO System ............................................................................................................. 3-19
Blocks in PROFINET IO........................................................................................................... 3-20
System status lists (SSLs) in PROFINET IO ........................................................................... 3-23
Open communication via Industrial Ethernet ........................................................................... 3-24
SNMP communication service ................................................................................................. 3-26

3.3
3.3.1
3.3.2
3.3.3
3.3.4

S7 connections ........................................................................................................................ 3-26
S7 connection as communication path .................................................................................... 3-26
Assignment of S7 connections................................................................................................. 3-27
Distribution and availability of S7 connection resources ......................................................... 3-29
Connection resources for routing............................................................................................. 3-31

3.4

DPV1........................................................................................................................................ 3-32

CPU 31xC and CPU 31x, Technical data
Manual, Edition 08/2004, A5E00105475-05

vii

Table of contents
4

viii

Memory concept ..................................................................................................................................... 4-1
4.1
4.1.1
4.1.2
4.1.3
4.1.4
4.1.5

Memory areas and retentivity..................................................................................................... 4-1
CPU memory areas.................................................................................................................... 4-1
Retentivity of the load memory, system memory and RAM....................................................... 4-2
Retentivity of memory objects .................................................................................................... 4-3
Address areas of system memory ............................................................................................. 4-5
Properties of the Micro Memory Card (MMC) ............................................................................ 4-9

4.2
4.2.1
4.2.2
4.2.3
4.2.3.1
4.2.3.2
4.2.3.3
4.2.3.4
4.2.3.5
4.2.4
4.2.5
4.2.6
4.2.7

Memory functions..................................................................................................................... 4-11
General: Memory functions ...................................................................................................... 4-11
Loading user program from Micro Memory Card (MMC) to the CPU ...................................... 4-11
Handling with modules ............................................................................................................. 4-12
Download of new blocks or delta downloads ........................................................................... 4-12
Uploading blocks...................................................................................................................... 4-12
Deleting blocks......................................................................................................................... 4-13
Compressing blocks................................................................................................................. 4-13
Promming (RAM to ROM) ........................................................................................................ 4-13
CPU memory reset and restart ................................................................................................ 4-13
Recipes .................................................................................................................................... 4-15
Measured value log files .......................................................................................................... 4-17
Backup of project data to a Micro Memory Card (MMC) ......................................................... 4-19

Cycle and reaction times......................................................................................................................... 5-1
5.1

Overview .................................................................................................................................... 5-1

5.2
5.2.1
5.2.2
5.2.3
5.2.4
5.2.5
5.2.6

Cycle time................................................................................................................................... 5-2
Overview .................................................................................................................................... 5-2
Calculating the cycle time .......................................................................................................... 5-5
Different cycle times................................................................................................................... 5-8
Communication load .................................................................................................................. 5-9
Cycle time extension as a result of testing and commissioning functions ............................... 5-11
Cycle extension through component-based automation (CBA)............................................... 5-11

5.3
5.3.1
5.3.2
5.3.3
5.3.4

Response time ......................................................................................................................... 5-14
Overview .................................................................................................................................. 5-14
Shortest response time ............................................................................................................ 5-16
Longest response time............................................................................................................. 5-17
Reducing the response time with direct I/O access................................................................. 5-18

5.4

Calculating method for calculating the cycle/response time .................................................... 5-19

5.5
5.5.1
5.5.2

Interrupt response time ............................................................................................................ 5-21
Overview .................................................................................................................................. 5-21
Reproducibility of delay interrupts and watchdog interrupts .................................................... 5-23

5.6
5.6.1
5.6.2
5.6.3

Sample calculations ................................................................................................................. 5-24
Example of cycle time calculation ............................................................................................ 5-24
Sample of response time calculation ....................................................................................... 5-25
Example of interrupt response time calculation ....................................................................... 5-27

Technical data of CPU 31xC................................................................................................................... 6-1
6.1
6.1.1
6.1.2

General technical data ............................................................................................................... 6-1
Dimensions of CPU 31xC .......................................................................................................... 6-1
Technical data of the Micro Memory Card (MMC) ..................................................................... 6-2

6.2

CPU 312C .................................................................................................................................. 6-3

6.3

CPU 313C .................................................................................................................................. 6-8

6.4

CPU 313C-2 PtP and CPU 313C-2 DP ................................................................................... 6-14

CPU 31xC and CPU 31x, Technical data
Manual, Edition 08/2004, A5E00105475-05

Table of contents

6.5

CPU 314C-2 PtP and CPU 314C-2 DP ................................................................................... 6-21

6.6
6.6.1
6.6.2
6.6.3
6.6.4
6.6.5
6.6.6
6.6.7
6.6.8
6.6.9

Technical data of the integrated I/O......................................................................................... 6-28
Arrangement and usage of integrated I/Os.............................................................................. 6-28
Analog I/O ................................................................................................................................ 6-34
Configuration............................................................................................................................ 6-39
Interrupts .................................................................................................................................. 6-45
Diagnostics............................................................................................................................... 6-46
Digital inputs............................................................................................................................. 6-46
Digital outputs .......................................................................................................................... 6-48
Analog inputs ........................................................................................................................... 6-51
Analog outputs ......................................................................................................................... 6-53

Technical data of CPU 31x ..................................................................................................................... 7-1
7.1
7.1.1
7.1.2

General technical data ............................................................................................................... 7-1
Dimensions of CPU 31x............................................................................................................. 7-1
Technical data of the Micro Memory Card (MMC)..................................................................... 7-2

7.2

CPU 312..................................................................................................................................... 7-3

7.3

CPU 314..................................................................................................................................... 7-8

7.4

CPU 315-2 DP ......................................................................................................................... 7-13

7.5

CPU 315-2 PN/DP ................................................................................................................... 7-19

7.6

CPU 317-2 DP ......................................................................................................................... 7-26

7.7

CPU 317-2 PN/DP ................................................................................................................... 7-33

Appendix.................................................................................................................................................A-1
A.1
A.1.1
A.1.2
A.1.3
A.1.4
A.1.5
A.1.6
A.1.7
A.1.8
A.1.9
A.1.10
A.1.11
A.1.12
A.1.13
A.1.14

Information about upgrading to a CPU 31xC or CPU 31x ......................................................... A-1
Area of applicability.................................................................................................................... A-1
Changed behavior of certain SFCs............................................................................................ A-2
Interrupt events from distributed I/Os while the CPU status is in STOP ................................... A-4
Runtimes that change while the program is running ................................................................. A-5
Converting the diagnostic addresses of DP slaves ................................................................... A-5
Reusing existing hardware configurations ................................................................................. A-6
Replacing a CPU 31xC/31x ....................................................................................................... A-6
Using consistent data areas in the process image of a DP slave system ................................. A-7
Load memory concept for the CPU 31xC/31x ........................................................................... A-8
PG/OP functions ........................................................................................................................ A-8
Routing for the CPU 31xC/31x as an intelligent slave............................................................... A-8
Changed retentive behavior for CPUs with firmware >= V2.1.0 ................................................ A-9
FMs/CPs with separate MPI address in the central rack of a CPU 315-2 PN/DP / CPU 317 ... A-9
Using loadable blocks for S7 communication for the integrated PROFINET interface ........... A-10

Glossary ..................................................................................................................................... Glossary-1
Index................................................................................................................................................ Index-1

CPU 31xC and CPU 31x, Technical data
Manual, Edition 08/2004, A5E00105475-05

Table of contents
Tables
Table 1-1

Application area covered by this manual ...................................................................................... iii

Table 1-1

Ambient influence on the automation system (AS).................................................................... 1-1

Table 1-2

Galvanic isolation ....................................................................................................................... 1-1

Table 1-3

Communication between sensors/actuators and the PLC......................................................... 1-2

Table 1-4

The use of local and distributed I/O ........................................................................................... 1-2

Table 1-5

Configuration consisting of the Central Unit (CU) and Expansion Modules (EMs).................... 1-2

Table 1-6

CPU performance ...................................................................................................................... 1-3

Table 1-7

Communication .......................................................................................................................... 1-3

Table 1-8

Software ..................................................................................................................................... 1-3

Table 1-9

Supplementary features ............................................................................................................. 1-4

Table 2-1

Positions of the mode selector switch........................................................................................ 2-3

Table 2-2

Differences of the CPUs 31xC ................................................................................................... 2-3

Table 2-3

Positions of the mode selector switch........................................................................................ 2-6

Table 2-4

Positions of the mode selector switch........................................................................................ 2-8

Table 2-5

Positions of the mode selector switch...................................................................................... 2-10

Table 2-6

General status and error displays of the CPU 31x .................................................................. 2-11

Table 2-7

Bus error displays of CPU 31x................................................................................................. 2-11

Table 3-1

Operating modes for CPUs with two DP interfaces ................................................................... 3-2

Table 3-2

Communication services of the CPUs ....................................................................................... 3-6

Table 3-3

Client and server in S7 communication, using connections with unilateral /
bilateral configuration ................................................................................................................. 3-8

Table 3-4

GD resources of the CPUs....................................................................................................... 3-10

Table 3-5

Number of routing connections for DP CPUs .......................................................................... 3-12

Table 3-6

New System Standard Functions of PROFINET IO and PROFIBUS DP and
Those That Must Be Replaced................................................................................................. 3-21

Table 3-7

System and Standard Functions in PROFIBUS DP that must be Implemented with
Different Functions in PROFINET IO ....................................................................................... 3-22

Table 3-8

OBs in PROFINET IO and PROFIBUS DP.............................................................................. 3-22

Table 3-9

Comparison of the System Status Lists of PROFINET and PROFIBUS ................................. 3-23

Table 3-10

Distribution of connections ....................................................................................................... 3-29

Table 3-11

Availability of connection resources......................................................................................... 3-30

Table 3-12

Number of routing connection resources (for DP/PN CPUs)................................................... 3-31

Table 3-13

Interrupt blocks with DPV1 functionality................................................................................... 3-33

Table 3-14

System function blocks with DPV1 functionality ...................................................................... 3-33

CPU 31xC and CPU 31x, Technical data
Manual, Edition 08/2004, A5E00105475-05

Table of contents
Table 4-1

Retentivity of the RAM ............................................................................................................... 4-2

Table 4-2

Retentive behavior of memory objects (applies to all CPUs with DP/MPI-SS (31x-2 PN/DP) .. 4-3

Table 4-3

Retentive behavior of DBs for CPUs with firmware >= V2.1.0 .................................................. 4-4

Table 4-4

Address areas of system memory ............................................................................................. 4-5

Table 5-1

Cyclic program processing......................................................................................................... 5-3

Table 5-2

Formula for calculating the process image (PI) transfer time .................................................... 5-5

Table 5-3

CPU 31xC: Data for calculating the process image (PI) transfer time....................................... 5-5

Table 5-4

CPU 31x: Data for calculating the process image (PI) transfer time ......................................... 5-6

Table 5-5

Extending the user program processing time ............................................................................ 5-6

Table 5-6

Operating system processing time at the scan cycle checkpoint .............................................. 5-7

Table 5-7

Extended cycle time due to nested interrupts............................................................................ 5-7

Table 5-8

Cycle time extension as a result of errors.................................................................................. 5-8

Table 5-9

Cycle time extension as a result of testing and commissioning functions............................... 5-11

Table 5-10

Formula: Shortest response time............................................................................................. 5-16

Table 5-11

Formula: Longest response time ............................................................................................. 5-18

Table 5-12

Calculating the response time.................................................................................................. 5-20

Table 5-13

Process/diagnostic interrupt response times ........................................................................... 5-21

Table 5-14

Process/diagnostic interrupt response times ........................................................................... 5-22

Table 6-1

Available MMCs ......................................................................................................................... 6-2

Table 6-2

Maximum number of loadable blocks on the MMC.................................................................... 6-2

Table 6-3

Technical data of CPU 312C ..................................................................................................... 6-3

Table 6-4

Technical data of CPU 313C ..................................................................................................... 6-8

Table 6-5

Technical data for CPU 313C-2 PtP/ CPU 313C-2 DP............................................................ 6-14

Table 6-6

Technical data of CPU 314C-2 PtP and CPU 314C-2 DP....................................................... 6-21

Table 6-7

Parameters of standard DI....................................................................................................... 6-39

Table 6-8

Parameters of the interrupt inputs............................................................................................ 6-39

Table 6-9

Parameters of standard AI ....................................................................................................... 6-41

Table 6-10

Parameters of standard AO ..................................................................................................... 6-42

Table 6-11

Start information for OB40, relating to the interrupt inputs of the integrated I/O ..................... 6-45

Table 6-12

Technical data of digital inputs................................................................................................. 6-47

Table 6-13

Technical data of digital outputs .............................................................................................. 6-49

Table 6-14

Technical data of analog inputs ............................................................................................... 6-51

Table 6-15

Technical data of analog outputs ............................................................................................. 6-53

CPU 31xC and CPU 31x, Technical data
Manual, Edition 08/2004, A5E00105475-05

Table of contents
Table 7-1

Available MMCs ......................................................................................................................... 7-2

Table 7-2

Maximum number of loadable blocks on the MMC.................................................................... 7-2

Table 7-3

Technical data for the CPU 312................................................................................................. 7-3

Table 7-4

Technical data for the CPU 314................................................................................................. 7-8

Table 7-5

Technical data for the CPU 315-2 DP...................................................................................... 7-13

Table 7-6

Technical data for the CPU 315-2 PN/DP................................................................................ 7-19

Table 7-7

Technical data for the CPU 317-2 DP...................................................................................... 7-26

Table 7-8

Technical data for the CPU 317-2 PN/DP................................................................................ 7-33

Table A-1

Consistent data ..........................................................................................................................A-7

xii

CPU 31xC and CPU 31x, Technical data
Manual, Edition 08/2004, A5E00105475-05

Guide to the S7-300 documentation

Overview
There you find a guide leading you through the S7-300 documentation.

Selecting and configuring
Table 1-1

Ambient influence on the automation system (AS)

Information on..

is available in ...

What provisions do I have to make for AS installation
space?

S7-300, CPU 31xC and CPU 31x operating instructions:
Installation: Configuring - Component dimensions
S7-300, CPU 31xC and CPU 31x operating instructions:
Installation: Mounting - Installing the mounting rail

How do environmental conditions influence the AS?

Table 1-2

S7-300, CPU 31xC and CPU 31x operating instructions:
Installation: Appendix

Galvanic isolation

Information on..

is available in ...

Which modules can I use if electrical isolation is required
between sensors/actuators?

S7-300, CPU 31xC and CPU 31x operating instructions:
Installation: Configuring – Electrical assembly, protective
measures and grounding
Module Data Manual

Under what conditions do I have to isolate the modules
electrically?
How do I wire that?

S7-300, CPU 31xC and CPU 31x operating instructions:
Installation: Configuring – Electrical assembly, protective
measures and grounding

Under which conditions do I have to isolate stations
electrically?

S7-300, CPU 31xC and CPU 31x operating instructions:
Installation – Configuring – Configuring subnets

CPU 31xC and CPU 31x operating instructions: Installation:
Wiring

How do I wire that?

CPU 31xC and CPU 31x, Technical data
Manual, Edition 08/2004, A5E00105475-05

1-1

Guide to the S7-300 documentation

Table 1-3

Communication between sensors/actuators and the PLC

Information on..

is available in ...

Which module is suitable for my sensor/actuator?

For CPU: CPU 31xC and CPU 31x Manual, Technical Data
For signal modules: Reference manual of your signal
module

How many sensors/actuators can I connect to the module?

For CPU: CPU 31xC and CPU 31x Manual, technical data
of signal modules: Reference manual of your signal module

To connect my sensors/actuators to the PLC, how do I wire
the front connector ?

S7-300, CPU 31xC and CPU 31x operating instructions:
Installation: Wiring – Wiring the front connector

When do I need expansion modules (EM) and how do I
connect them?

S7-300, CPU 31xC and CPU 31x operating instructions:
Installation: Configuring – Distribution of modules to several
racks

How to mount modules on racks / mounting rails

S7-300, CPU 31xC and CPU 31x operating instructions:
Installation: Assembly – Installing modules on the mounting
rail

Table 1-4

The use of local and distributed I/O

Information on..

is available in ...

Which range of modules do I want to use?

For local I/O and expansion devices: Module Data reference
manual
For distributed I/O and PROFIBUS DP: Manual of the
relevant I/O device

Table 1-5

Configuration consisting of the Central Unit (CU) and Expansion Modules (EMs)

Information on..

is available in ...

Which rack / mounting rail is most suitable for my
application?

S7-300, CPU 31xC and CPU 31x operating instructions:
Installation: Configuring

Which interface modules (IM) do I need to connect the EMs
to the CU?

S7-300, CPU 31xC and CPU 31x operating instructions:
Installation: Configuring – Distribution of modules to several
racks

What is the right power supply (PS) for my application?

S7-300, CPU 31xC and CPU 31x operating instructions:
Installation: Configuring

1-2

CPU 31xC and CPU 31x, Technical data
Manual, Edition 08/2004, A5E00105475-05

Guide to the S7-300 documentation

Table 1-6

CPU performance

Information on..

is available in ...

Which memory concept is best suited to my application?

CPU 31xC and CPU 31x Manual, Technical Data

How do I insert and remove Micro Memory Cards?

S7-300, CPU 31xC and CPU 31x operating instructions:
Installation: Commissioning – Commissioning modules –
Removing / inserting a Micro Memory Card (MMC)

Which CPU meets my demands on performance?

S7-300 instruction list: CPU 31xC and CPU 31x

Length of the CPU response / execution times

CPU 31xC and CPU 31x Manual, Technical Data

Which technological functions are implemented?

Technological Functions Manual

How can I use these technological functions?

Technological Functions Manual

Table 1-7

Communication

Information on..

is available in ...

Which principles do I have to take into account?

Communication with SIMATIC Manual
PROFINET System Manual, System Description

Options and resources of the CPU

CPU 31xC and CPU 31x Manual, Technical Data

How to use communication processors (CPs) to optimize
communication

CP Manual

Which type of communication network is best suited to my
application?

S7-300, CPU 31xC and CPU 31x operating instructions:
Installation: Configuring – Configuring subnets

How to network the various components

S7-300, CPU 31xC and CPU 31x operating instructions:
Installation: Configuring – Configuring subnets

What to take into account when configuring PROFINET
networks

SIMATIC NET Manual, Twisted-Pair and Fiber Optic
Networks (6GK1970-1BA10-0AA0) – Network Configuration
PROFINET System Manual, System Description –
Installation and Commissioning

Table 1-8

Software

Information on..

is available in ...

Software requirements of my S7-300 system

CPU 31xC and CPU 31x Manual, Technical Data –
Technical Data

CPU 31xC and CPU 31x, Technical data
Manual, Edition 08/2004, A5E00105475-05

1-3

Guide to the S7-300 documentation

Table 1-9

Supplementary features

Information on..

is available in ...

How to implement monitor and modify functions

For text-based displays: The relevant Manual

(Human Machine Interface)

For Operator Panels: The relevant Manual
For WinCC: The relevant Manual

How to integrate process control modules

For PCS7: The relevant Manual

What options are offered by redundant and fail-safe
systems?

S7-400H Manual – Redundant Systems
Fail-Safe Systems Manual

Information to be observed when migrating from PROFIBUS Programming Manual: From PROFIBUS DP to PROFINET
DP to PROFINET IO
IO

1-4

CPU 31xC and CPU 31x, Technical data
Manual, Edition 08/2004, A5E00105475-05

Operating and display elements
2.1

Operating and display elements: CPU 31xC

Operating and display elements of CPU 31xC
1

SF
BF

MMC

DC5V

FRCE
RUN
STOP
RUN
STOP
MRES

X2
X11

X12

4
The figures show

the following CPU elements

(1)

Status and error displays

(2)

Slot for the Micro Memory Card (MMC), incl. the ejector

(3)

Connections of the integrated I/O.

(4)

Power supply connection

(5)

2. Interface X2 (PtP or DP)

(6)

1. Interface X1 (MPI)

(7)

Mode selector switch

CPU 31xC and CPU 31x, Technical data
Manual, Edition 08/2004, A5E00105475-05

2-1

Operating and display elements
2.1 Operating and display elements: CPU 31xC
The figure below illustrates the integrated digital and analog I/Os of the CPU with open front
covers.
X12

X11
SF
BF
DC5V
FRCE
RUN
STOP

RUN
STOP
MRES

Figure 2-1

Integrated I/Os of CPU 31xC (CPU 314C-2 PtP, for example)

The figure shows

the following integrated I/Os

(1)

Analog I/Os

(2)

each with 8 digital inputs

(3)

each with 8 digital outputs

Slot for the SIMATIC Micro Memory Card (MMC)
A SIMATIC micro memory card (MMC) is used as memory module. You can use MMCs as
load memory and as portable storage medium.

Note
These CPUs do not have an integrated load memory and thus require an MMC for
operation.

2-2

CPU 31xC and CPU 31x, Technical data
Manual, Edition 08/2004, A5E00105475-05

Operating and display elements
2.1 Operating and display elements: CPU 31xC

Mode selector switch
Use the mode selector switch to set the CPU operating mode.
Table 2-1

Positions of the mode selector switch

Position

Meaning

Description

RUN

RUN mode

The CPU executes the user program.

STOP

STOP mode

The CPU does not execute a user program.

MRES

CPU memory
reset

Mode selector switch position with pushbutton function for CPU
memory reset. A CPU memory reset by means of mode selector
switch requires a specific sequence of operation.

Reference
• CPU operating modes: STEP 7 Online Help.
• Information on CPU memory reset: Operating instructions CPU 31xC and CPU31x,

Commissioning, Commissioning Modules, CPU Memory Reset by means of Mode
Selector Switch

• Evaluation of the LEDs upon error or diagnostic event: Operating Instructions CPU 31xC

and CPU 31x, Test Functions, Diagnostics and Troubleshooting, Diagnostics with the
help of Status and Error LEDs

Power supply connection
Each CPU is equipped with a double-pole power supply socket. The connector with screw
terminals is inserted into this socket when the CPU is delivered.

Differences between the CPUs
Table 2-2

Differences of the CPUs 31xC

Element

CPU
312C

CPU
313C

CPU
CPU
313C-2 DP 313C-2 PtP

CPU
314C-2 DP

CPU
314C-2 PtP

9-pole DP
interface (X2)

–

15-pole PtP
interface (X2)

–

Digital inputs

Digital outputs

Analog inputs

–

4+1

–

4+1

Analog outputs –

–

Technological
functions

3 counters

4 counters

1 channel for
positioning

1 channel
for
positioning

CPU 31xC and CPU 31x, Technical data
Manual, Edition 08/2004, A5E00105475-05

2 counters

2-3

Operating and display elements
2.1 Operating and display elements: CPU 31xC

2.1.1

Status and Error Indicators: CPU 31xC
LED designation

Color

Meaning

red

Hardware or software error

BF (for CPUs with DP red
interface only)

Bus error

DC5V

green

5-V power for CPU and S7-300 bus is OK

FRCE

yellow

Force job is active

RUN

green

CPU in RUN
The LED flashes during STARTUP at a rate of 2 Hz, and in HOLD
state at 0.5 Hz.

STOP

yellow

CPU in STOP and HOLD or STARTUP
The LED flashes at 0.5 Hz when the CPU requests a memory reset,
and during the reset at 2 Hz.

Reference
• CPU operating modes: STEP 7 Online Help.
• Information on CPU memory reset: Operating instructions CPU 31xC and CPU31x,

Commissioning, Commissioning Modules, CPU Memory Reset by means of Mode
Selector SwitchEvaluation of the LEDs upon error or diagnostic event: Operating
Instructions CPU 31xC and CPU 31x, Test Functions, Diagnostics and Troubleshooting,
Diagnostics with the help of Status and Error LEDs

2-4

CPU 31xC and CPU 31x, Technical data
Manual, Edition 08/2004, A5E00105475-05

Operating and display elements
2.2 Operating and display elements: CPU 31x

2.2

Operating and display elements: CPU 31x

2.2.1

Operating and display elements: CPU 312, 314, 315-2 DP:

Operating and display elements
1

MMC

DC5V
FRCE

RUN
STOP
RUN
STOP
MRES

The figures show

the following CPU elements

(1)

Slot for the Micro Memory Card (MMC), incl. the ejector

(2)

2. Interface X2 (only for CPU 315-2 DP)

(3)

Power supply connection

(4)

1. Interface X1 (MPI)

(5)

Mode selector switch

(6)

Status and error displays

CPU 31xC and CPU 31x, Technical data
Manual, Edition 08/2004, A5E00105475-05

2-5

Operating and display elements
2.2 Operating and display elements: CPU 31x

Slot for the SIMATIC Micro Memory Card (MMC)
A SIMATIC Micro Memory Card (MMC) is used as memory module. You can use MMCs as
load memory and as portable storage medium.

Note
These CPUs do not have an integrated load memory and thus require an MMC for
operation.

Mode selector switch
The mode selector switch is used to set the CPU operating mode.
Table 2-3

Positions of the mode selector switch

Position

Meaning

Description

RUN

RUN mode

The CPU executes the user program.

STOP

STOP mode

The CPU does not execute a user program.

MRES

CPU memory reset

Mode selector switch position with pushbutton function for CPU
memory reset. A CPU memory reset by means of mode
selector switch requires a specific sequence of operation.

Reference
• CPU operating modes: STEP 7 Online Help.
• Information on CPU memory reset: Operating instructions CPU 31xC and CPU31x,

Commissioning, Commissioning Modules, CP Memory Reset by means of Mode Selector
Switch

• Evaluation of the LEDs upon error or diagnostic event: Operating Instructions CPU 31xC

and CPU 31x, Test Functions, Diagnostics and Troubleshooting, Diagnostics with the
help of Status and Error LEDs

Power supply connection
Each CPU is equipped with a double-pole power supply socket. The connector with screw
terminals is inserted into this socket when the CPU is delivered.

2-6

CPU 31xC and CPU 31x, Technical data
Manual, Edition 08/2004, A5E00105475-05

Operating and display elements
2.2 Operating and display elements: CPU 31x

2.2.2

Operating and display elements: CPU 317-2 DP

Operating and display elements
1

BF1

BF2
DC5V

MMC

FRCE
RUN
STOP

4
RUN
STOP
MRES

7
6

The figures show

the following CPU elements

(1)

Bus error indicator

(2)

Status and error displays

(3)

Slot for the Micro Memory Card (MMC), incl. the ejector

(4)

Mode selector switch

(5)

Power supply connection

(6)

1. Interface X1 (MPI/DP)

(7)

2. Interface X2 (DP)

CPU 31xC and CPU 31x, Technical data
Manual, Edition 08/2004, A5E00105475-05

2-7

Operating and display elements
2.2 Operating and display elements: CPU 31x

Slot for the SIMATIC Micro Memory Card (MMC)
A SIMATIC Micro Memory Card (MMC) is used as memory module. You can use MMCs as
load memory and as portable storage medium.

Note
These CPUs do not have an integrated load memory and thus require an MMC for
operation.

Mode selector switch
Use the mode selector switch to set the CPU operating mode.
Table 2-4

Positions of the mode selector switch

Position

Meaning

Description

RUN

RUN mode

The CPU executes the user program.

STOP

STOP mode

The CPU does not execute a user program.

MRES

CPU memory reset

Mode selector switch position with pushbutton function for CPU
memory reset. A CPU memory reset by means of mode
selector switch requires a specific sequence of operation.

Reference
• CPU operating modes: STEP 7 Online Help.
• Information on CPU memory reset: Operating instructions CPU 31xC and CPU31x,

Commissioning, Commissioning Modules, CP Memory Reset by means of Mode Selector
Switch

• Evaluation of the LEDs upon error or diagnostic event: Operating Instructions CPU 31xC

and CPU 31x, Test Functions, Diagnostics and Troubleshooting, Diagnostics with the
help of Status and Error LEDs

Power supply connection
Each CPU is equipped with a double-pole power supply socket. The connector with screw
terminals is inserted into this socket when the CPU is delivered.

2-8

CPU 31xC and CPU 31x, Technical data
Manual, Edition 08/2004, A5E00105475-05

Operating and display elements
2.2 Operating and display elements: CPU 31x

2.2.3

Operating and display elements: CPU 31x-2 PN/DP

Operating and display elements
1

BF1

BF2

MMC

DC5V
FRCE
RUN
STOP

4
RUN
STOP

MRES

8
LINK
RX / TX

MAC-ADD.:
X1-X2-X3
X4-X5-X6

6
X1
X2

The figures show

the following CPU elements

(1)

Bus error indicators

(2)

Status and error displays

(3)

Slot for the Micro Memory Card (MMC), incl. the ejector

(4)

Mode selector switch

(5)

Status display of 2nd interface (X2)

(6)

2. Interface X2 (PN)

(7)

Power supply connection

(8)

1. Interface X1 (MPI/DP)

CPU 31xC and CPU 31x, Technical data
Manual, Edition 08/2004, A5E00105475-05

2-9

Operating and display elements
2.2 Operating and display elements: CPU 31x

Slot for the SIMATIC Micro Memory Card (MMC)
A SIMATIC Micro Memory Card (MMC) is used as memory module. You can use MMCs as
load memory and as portable storage medium.

Note
These CPUs do not have an integrated load memory and thus require an MMC for
operation.

Mode selector switch
Use the mode selector switch to set the CPU operating mode.
Table 2-5

Positions of the mode selector switch

Position

Meaning

Description

RUN

RUN mode

The CPU executes the user program.

STOP

STOP mode

The CPU does not execute a user program.

MRES

CPU memory reset Mode selector switch position with pushbutton function for CPU
memory reset. A CPU memory reset by means of mode selector
switch requires a specific sequence of operation.

Reference
• CPU operating modes: STEP 7 Online Help.
• Information on CPU memory reset: Operating instructions CPU 31xC and CPU31x,

Commissioning, Commissioning Modules, CP Memory Reset by means of Mode Selector
Switch

• Evaluation of the LEDs upon error or diagnostic event: Operating Instructions CPU 31xC

and CPU 31x, Test Functions, Diagnostics and Troubleshooting, Diagnostics with the
help of Status and Error LEDs

Power supply connection
Each CPU is equipped with a double-pole power supply socket. The connector with screw
terminals is inserted into this socket when the CPU is delivered.

2-10

CPU 31xC and CPU 31x, Technical data
Manual, Edition 08/2004, A5E00105475-05

Operating and display elements
2.2 Operating and display elements: CPU 31x

2.2.4

Status and error displays of the CPU 31x

General status and error displays
Table 2-6

General status and error displays of the CPU 31x

LED designation

Color

Meaning

red

Hardware or software error.

DC5V

green

5-V power for the CPU and the S7-300 bus

FRCE

yellow

LED is lit: Active force job
LED flashes at 2 Hz: Node flash test function (only CPUs with
firmware V2.2.0 or higher)

RUN

green

CPU in RUN
The LED flashes during STARTUP at a rate of 2 Hz, and in HOLD
state at 0.5 Hz.

STOP

yellow

CPU in STOP, or HOLD, or STARTUP
The LED flashes at 0.5 Hz when the CPU requests a memory reset,
and during the reset at 2 Hz.

Displays for the X1 and X2 interfaces
Table 2-7

Bus error displays of CPU 31x

CPU

LED designation

Color

Meaning

315-2 DP

red

Bus error at DP interface (X2)

317-2 DP
31x-2 PN/DP

BF1

red

Bus error at interface 1 (X1)

BF2

red

Bus error at interface 2 (X1)

BF1

red

Bus error at interface 1 (X1)

BF2

red

Bus error at interface 2 (X1)

LINK

green

Active communication at interface 2 (X2).

RX/TX

yellow

Receive / Transmit data at interface 2 (X2)

Reference
• CPU operating modes: STEP 7 Online Help.
• Information on CPU memory reset: Operating instructions CPU 31xC and CPU31x,

Commissioning, Commissioning Modules, CP Memory Reset by means of Mode Selector
Switch

• Evaluation of the LEDs upon error or diagnostic event: Operating Instructions CPU 31xC

and CPU 31x, Test Functions, Diagnostics and Troubleshooting, Diagnostics with the
help of Status and Error LEDs

CPU 31xC and CPU 31x, Technical data
Manual, Edition 08/2004, A5E00105475-05

2-11

Operating and display elements
2.2 Operating and display elements: CPU 31x

2-12

CPU 31xC and CPU 31x, Technical data
Manual, Edition 08/2004, A5E00105475-05

Communication
3.1

Interfaces

3.1.1

Multi-Point Interface (MPI)

Availability
All CPUs described in this manual are equipped with an MPI interface X1.
A CPU equipped with an MPI/DP interface is configured and supplied as MPI. To use the
DP interface, set DP interface mode in STEP 7.

Properties
The MPI (Multi-Point Interface) represents the CPU interface for PG/OP connections, or for
communication on an MPI subnet.
The typical (default) transmission rate of all CPUs is 187.5 kbps. You can also set 19.2 kbps
for communication with an S7-200. The 315-2 PN/DP and 317 CPUs support transmission
rates up to 12 Mbps.
The CPU automatically broadcasts its bus configuration via the MPI interface (the
transmission rate, for example). A PG, for example, can thus receive the correct parameters
and automatically connect to a MPI subnet.

Note
You may only connect PGs to an MPI subnet which is in RUN.
Other stations (for example, OP, TP, ...) should not be connected to the MPI subnet while
the system is in RUN. Otherwise, transferred data might be corrupted as a result
interference, or global data packages may be lost.

CPU 31xC and CPU 31x, Technical data
Manual, Edition 08/2004, A5E00105475-05

3-1

Communication
3.1 Interfaces

Devices capable of MPI communication
• PG/PC
• OP/TP
• S7-300 / S7-400 with MPI interface
• S7-200 (19.2 kbps only)

3.1.2

PROFIBUS DP

Availability
CPUs with “DP“ name suffix are equipped at least with a DP X2 interface.
The 315-2 PN/DP and 317 CPUs are equipped with an MPI/DP X1 interface. A CPU with
MPI/DP interface is supplied with a default MPI configuration. You need to set DP mode in
STEP 7 if you want to use the DP interface.

Operating modes for CPUs with two DP interfaces
Table 3-1

Operating modes for CPUs with two DP interfaces

MPI/DP interface (X1)
•
•
•
1

MPI
DP master
DP slave 1

PROFIBUS DP interface (X2)
•
•
•

not configured
DP master
DP slave 1

simultaneous operation of the DP slave on both interfaces is excluded

Properties
The PROFIBUS DP interface is mainly used to connect distributed I/O. PROFIBUS DP
allows you to create large subnets, for example.
The PROFIBUS DP interface can be set for operation in master or slave mode, and supports
transmission rates up to 12 Mbps.
The CPU broadcasts its bus parameters (transmission rate, for example) via the
PROFIBUS DP interface when master mode is set. A PG, for example, can thus receive the
correct parameters and automatically connect to a PROFIBUS subnet. In your configuration
you can specify to disable bus parameter broadcasting.

3-2

CPU 31xC and CPU 31x, Technical data
Manual, Edition 08/2004, A5E00105475-05

Communication
3.1 Interfaces

Note
(for DP interface in slave mode only)
When you disable the Commissioning / Debug mode / Routing check box in the DP interface
properties dialog in STEP 7, all user-specific transmission rate settings will be ignored, and
the transmission rate of the master is automatically set instead. This disables the routing
function at this interface.

Devices capable of PROFIBUS DP communication
• PG/PC
• OP/TP
• DP slaves
• DP masters
• Actuators/Sensors
• S7-300/S7-400 with PROFIBUS DP interface

Reference
Further information on PROFIBUS: http://www.profibus.com

3.1.3

PROFINET (PN)

Availability
CPUs with a “PtP“ name suffix are equipped with a PtP X2 interface. X2.

Connecting to Industrial Ethernet
You can use the integrated PROFINET interface of the CPU to establish a connection to
Industrial Ethernet.
The integrated PROFINET interface of the CPU can be configured via MPI or PROFINET.

Requirements
• CPUs with FW 2.3.0 or higher (for example CPU 315-2 PN/DP)
• STEP 7 V5.3 + Servicepack 1 or higher

CPU 31xC and CPU 31x, Technical data
Manual, Edition 08/2004, A5E00105475-05

3-3

Communication
3.1 Interfaces

Devices capable of PROFINET (PN) communication
• PROFINET IO components (for example, interface module IM 151-3 PN in an ET 200S)
• S7-300 / S7-400 with PROFINET interface (for example, CPU 317-2 PN/DP or
CP 343-1 PN)
• Active network components (a switch, for example)
• PG/PC with network card

Properties of PROFINET interface X2
Properties
IEEE standard

802.3

Connector design

RJ45

Transmission speed

Max. 100 Mbps

Media

Twisted Pair Cat5 (100BASE-TX)

Note
Networking PROFINET components
The use of switches, rather than hubs, for networking PROFINET components brings about
a substantial improvement in decoupling bus traffic, and improves runtime performance
under higher bus load. PROFINET CBA with cyclic PROFINET interconnections requires the
use of switches in order to maintain compliance with performance specifications. Full duplex
mode at 100 Mbps is mandatory for cyclic PROFINET interconnections.
PROFINET IO also requires the use of switches and 100 Mbps full duplex mode.

Reference
• For information on how to configure the integrated PROFINET interface of the CPU, refer
to the S7-300, CPU 31xC and CPU 31x Installation operating manual.
• For details on PROFINET, refer to the PROFINET System Description
• For detailed information on Ethernet networks, network configuration and network
components refer to the SIMATIC NET Manual: Twisted Pair and Fiber Optic Networks,
available under article ID 8763736 on the Internet URL
http://www.siemens.com/automation/service&support
• Tutorial: Commissioning Component-Based Automation Systems, article ID 14142554
• Further information on PROFINET: http://www.profibus.com

See also
Overview (Page 5-1)

5.5.2

Reproducibility of delay interrupts and watchdog interrupts

Definition of "Reproducibility"
Delay interrupt:
The period that expires between the call of the first instruction in the interrupt OB and the
programmed time of interrupt.
Watchdog interrupt:
The fluctuation width of the interval between two successive calls, measured between the
respective initial instructions of the interrupt OBs.

Reproducibility
The following times apply for the CPUs described in this manual:
• Delay interrupt: +/- 200 μs
• Watchdog interrupt: +/- 200 μs
These times only apply if the interrupt can actually be executed at this time and if not
interrupted, for example, by higher-priority interrupts or queued interrupts of equal priority.

CPU 31xC and CPU 31x, Technical data
Manual, Edition 08/2004, A5E00105475-05

5-23

Cycle and reaction times
5.6 Sample calculations

5.6

Sample calculations

5.6.1

Example of cycle time calculation

Installation
You have configured an S7300 and equipped it with following modules in rack "0":
• a CPU 314C-2
• 2 digital input modules SM 321; DI 32 x 24 VDC (4 bytes each in the PI)
• 2 digital output modules SM 322; DO 32 x 24 VDC/0.5 A (4 bytes each in the PI)

User program
According to the Instruction List, the user program runtime is 5 ms. There is no active
communication.

Calculating the cycle time
In this example, the cycle time is equivalent to the sum of the following times:
• User program execution time:
approx. 5 ms x CPU-specific factor 1.10 = approx. 5.5 ms
• Process image transfer time
Process image of inputs: 100 μs + 8 Byte x 37 μs = approx. 0.4 ms
Process image of outputs: 100 μs + 8 Byte x 37 μs = approx. 0.4 ms
• Operating system runtime at the scan cycle checkpoint:
approx. 0.5 ms
Cycle time = 5.5 ms + 0.4 ms + 0.4 ms + 0.5 ms = 6.8 ms.

Calculating the physical cycle time
• There is no active communication.
• Interrupts are not processed.
Hence, the physical cycle time is 6 ms.

5-24

CPU 31xC and CPU 31x, Technical data
Manual, Edition 08/2004, A5E00105475-05

Cycle and reaction times
5.6 Sample calculations

Calculating the longest response time
Longest response time:
6.8 ms x 2 = 13.6 ms.
• I/O delay can be neglected.
• Neither PROFIBUS DP, nor PROFINET IO are being used, so you do not have to make
allowances for any DP cycle times on PROFIBUS DP or for PROFINET IO update times.
• Interrupts are not processed.

5.6.2

Sample of response time calculation

Installation
You have configured an S7300 and equipped it with the following modules in two racks:
• a CPU 314C-2
Configuring the cycle load as a result of communication: 40 %
• 4 digital input modules SM 321; DI 32 x 24 VDC (4 bytes each in the PI)
• 3 digital output modules SM 322; DO 16 x 24 VDC/0.5 A (2 bytes each in the PI)
• 2 analog input modules SM 331; AI 8 x 12-bit (not in the PI)
• 2 analog output modules SM 332; AO 4 x 12 bit (not in the PI)

User program
According to the instruction list, the user program runtime is 10.0 ms.

Calculating the cycle time
In this example, the cycle time is equivalent to the sum of the following times:
• User program execution time:
approx. 10 ms x CPU-specific factor 1.10 = approx. 11 ms
• Process image transfer time
Process image of inputs: 100 μs + 16 bytes x 37 μs = approx. 0.7 ms
Process image of outputs: 100 μs + 6 bytes x 37 μs = approx. 0.3 ms
• Operating system runtime at the scan cycle checkpoint:
approx. 0.5 ms
The sum of the listed times is equivalent to the cycle time:
Cycle time = 11.0 ms + 0.7 ms + 0.3 ms + 0.5 ms = 12.5 ms.

CPU 31xC and CPU 31x, Technical data
Manual, Edition 08/2004, A5E00105475-05

5-25

Cycle and reaction times
5.6 Sample calculations

Calculating the physical cycle time
Under consideration of communication load:
12.5 ms * 100 / (100-40) = 20.8 ms.
Thus, under consideration of time-sharing factors, the actual cycle time is 21 ms.

Calculation of the longest response time
• Longest response time = 21 ms * 2 = 42 ms.
• I/O delay
– The maximum delay of the input digital module SM 321; DI 32 x 24 VDC is 4.8 ms per
channel.
– The output delay of the digital output module SM 322; DO 16 x 24 VDC/0.5 A can be
neglected.
– The analog input module SM 331; AI 8 x 12 bit was configured for an interference
suppression at 50 Hz. The result is a conversion time of 22 ms per channel. With the
eight active channels, the result is a cycle time of 176 ms for the analog input module.
– The analog output module SM 332; AO 4 x 12-bit was programmed for the measuring
range of 0 ...10 Hz. This gives a conversion time of 0.8 ms per channel. Since
4 channels are active, the result is a cycle time of 3.2 ms. A settling time of 0.1 ms for
a resistive load must be added to this value. The result is a response time of 3.3 ms
for an analog output.
• Neither PROFIBUS DP, nor PROFINET IO are being used, so you do not have to make
allowances for any DP cycle times on PROFIBUS DP or for PROFINET IO update times.
• Response times plus I/O delay:
– Case 1: An output channel of the digital output module is set when a signal is received
at the digital input. The result is a response time of:
Response time = 42 ms + 4.8 ms = 46.8 ms.
– Case 2: An analog value is fetched, and an analog value is output. The result is a
response time of:
Longest response time = 42 ms + 176 ms + 3.3 ms = 221.3 ms.

5-26

CPU 31xC and CPU 31x, Technical data
Manual, Edition 08/2004, A5E00105475-05

Cycle and reaction times
5.6 Sample calculations

5.6.3

Example of interrupt response time calculation

Installation
You have assembled an S7-300, consisting of one CPU 314C-2 and four digital modules in
the CPU rack. One of the digital input modules is an SM 321; DI 16 x 24 VDC; with
process/diagnostic interrupt function.
You have enabled only the process interrupt in your CPU and SM parameter configuration.
You decided not to use time-controlled processing, diagnostics or error handling. You have
configured a 20% communication load on the cycle.
You have configured a delay of 0.5 ms for the inputs of the DI module.
No activities are required at the scan cycle checkpoint.

Calculation
In this example, the process interrupt response time is based on following time factors:
• Process interrupt response time of CPU 314C-2: approx. 0,7 ms
• Extension by communication according to the formula:
200 μs + 1000 μs x 20 % = 400 μs = 0.4 ms
• Process interrupt response time of SM 321; DI 16 x 24 VDC:
– Internal interrupt preparation time: 0.25 ms
– Input delay: 0.5 ms
• Neither PROFIBUS DP, nor PROFINET IO are being used, so you do not have to make
allowances for any DP cycle times on PROFIBUS DP or for PROFINET IO update times.
The process interrupt response time is equivalent to the sum of the listed time factors:
Process interrupt response time = 0.7 ms + 0.4 ms + 0.25 ms + 0.5 ms = approx. 1.85 ms.
This calculated process interrupt response time expires between the time a signal is
received at the digital input and the call of the first instruction in OB40.

CPU 31xC and CPU 31x, Technical data
Manual, Edition 08/2004, A5E00105475-05

5-27

Cycle and reaction times
5.6 Sample calculations

5-28

CPU 31xC and CPU 31x, Technical data
Manual, Edition 08/2004, A5E00105475-05

Technical data of CPU 31xC
6.1

General technical data

6.1.1

Dimensions of CPU 31xC

Each CPU features the same height and depth, only the width dimensions differ.
• Height: 125 mm
• Depth: 115 mm, or 180 mm with opened front cover.

Width of CPU
CPU

Width

CPU 312C

80 mm

CPU 313C

120 mm

CPU 313C-2 PtP

120 mm

CPU 313C-2 DP

120 mm

CPU 314C-2 PtP

120 mm

CPU 314C-2 DP

120 mm

CPU 31xC and CPU 31x, Technical data
Manual, Edition 08/2004, A5E00105475-05

6-1

Technical data of CPU 31xC
6.1 General technical data

6.1.2

Technical data of the Micro Memory Card (MMC)

Plug-in SIMATIC Micro Memory Cards
The following memory modules are available:
Table 6-1

Available MMCs

Type

Order number

Required for a firmware update via MMC

MMC 64k

6ES7 953-8LFxx-0AA0

–

MMC 128k

6ES7 953-8LGxx-0AA0

–

MMC 512k

6ES7 953-8LJxx-0AA0

–

MMC 2M

6ES7 953-8LLxx-0AA0

Minimum requirement for CPUs without DP interface

MMC 4M

6ES7 953-8LMxx-0AA0

Minimum requirement for CPUs with DP interface

MMC 8M 1

6ES7 953-8LPxx-0AA0

–

This MMC cannot be used together with CPU 312C or CPU 312.

Maximum number of loadable blocks in the MMC
The number of blocks that can be stored on the MMC depends on the capacity of the MMC
being used. The maximum number of blocks that can be loaded is therefore limited by the
capacity of your MMC (including blocks generated with the "CREATE DB" SFC):
Table 6-2
Size of MMC

Maximum number of blocks that can be loaded

64 KB

768

128 KB

1024

512 KB

Here the maximum number of blocks that can be loaded for the
specific CPU is less than the number of blocks that can be stored on
the MMC.

2 MB
4 MB
8 MB

6-2

Maximum number of loadable blocks on the MMC

Refer to the corresponding specifications of a specific CPU to
determine the maximum number of blocks that can be loaded.

CPU 31xC and CPU 31x, Technical data
Manual, Edition 08/2004, A5E00105475-05

Technical data of CPU 31xC
6.2 CPU 312C

6.2

CPU 312C

Technical data
Table 6-3

Technical data of CPU 312C

Technical data
CPU and version
Order number

6ES7 312-5BD01-0AB0

•

Hardware version

•

Firmware version

V2.0

•

Associated programming package

STEP 7 as of V 5.2 + SP 1
(please use previous CPU for STEP 7 V 5.1 +
SP 3 or later)

Memory
RAM
•

Integrated

16 KB

•

Expandable

Load memory

Plugged in with MMC (max. 4 MB)

Data storage life on the MMC
(following final programming)

At least 10 years

Buffering

Guaranteed by MMC (maintenance-free)

Execution times
Processing times of
•

Bit operations

Min. 0.2 μs

•

Word instructions

Min. 0.4 μs

•

Fixed-point arithmetic

Min. 5 μs

•

Floating-point arithmetic

Min. 6 μs

Timers/counters and their retentivity
S7 counters

128

•

Retentive memory

Configurable

•

Default

from C0 to C7

•

Counting range

IEC Counters

0 to 999
Yes

•

Type

SFB

•

Number

unlimited (limited only by RAM size)

S7 timers

128

•

Retentive memory

Configurable

•

Default

Not retentive

•

Timer range

10 ms to 9990 s

CPU 31xC and CPU 31x, Technical data
Manual, Edition 08/2004, A5E00105475-05

6-3

Technical data of CPU 31xC
6.2 CPU 312C
Technical data
IEC Timers

Yes

•

Type

SFB

•

Number

unlimited (limited only by RAM size)

Data areas and their retentivity
Flag bits

128 bytes

•

Retentive memory

Configurable

•

Default retentivity

MB0 to MB15

Clock flag bits

8 (1 byte per flag bit)

Data blocks

Max. 511
(DB 1 to DB 511)

•

Length

Local data per priority class

max. 16 KB
max. 256 bytes

Blocks
Total

1024 (DBs, FCs, FBs)
The maximum number of blocks that can be
loaded may be reduced if you are using another
MMC.

OBs
•

Length

see the Instruction List
max. 16 KB

Nesting depth
•

Per priority class

•

additional within an error OB

FBs

8
4
Max. 512
(FB 0 to FB 511)

•

Length

FCs

max. 16 KB
Max. 512
(FC 0 to FC 511)

•

Length

max. 16 KB

Address areas (I/O)

6-4

Total I/O address area

max. 1024 bytes/1024 bytes
(can be freely addressed)

I/O process image

128 bytes/128 bytes

Digital channels

Max. 256

•

of those local

Max. 256

•

Integrated channels

10 DI / 6 DO

Analog channels

Max. 64

•

of those local

Max. 64

•

Integrated channels

None

CPU 31xC and CPU 31x, Technical data
Manual, Edition 08/2004, A5E00105475-05

Technical data of CPU 31xC
6.2 CPU 312C
Technical data
Assembly
Racks

Max. 1

Modules per rack

Max. 8

Number of DP masters
•

Integrated

None

•

Via CP

Max. 1

Number of function modules and communication
processors you can operate
•

Max. 8

•

CP (PtP)

Max. 8

•

CP (LAN)

Max. 4

Time-of-day
Real-time clock

Yes (SW clock)

•

Buffered

•

Accuracy

Deviation per day < 10 s

•

Behavior of the realtime clock after POWER
OFF

The clock keeps running, continuing at the timeof-day it had when power was switched off.

Operating hours counter

•

Number

•

Value range

2 31 hours
(if SFC 101 is used)

•

Granularity

1 hour

•

Retentive

Yes; must be manually restarted after every
restart

Clock synchronization

Yes

•

In the PLC

Master

•

On MPI

Master/slave

S7 signaling functions
Number of stations that can be logged on for
signaling functions

max. 6
(depends on the number of connections
configured for PG / OP and S7 basic
communication)

Process diagnostics messages

Yes

•

Simultaneously enabled interrupt S blocks

Max. 20

Testing and commissioning functions
Status/control variables

Yes

•

Variables

Inputs, outputs, memory bits, DBs, timers,
counters

•

Number of variables
– Of those as status variable
– Of those as control variable

Max. 30

Forcing

Max. 30
Max. 14
Yes

•

Variables

Inputs, outputs

•

Number of variables

Max. 10

CPU 31xC and CPU 31x, Technical data
Manual, Edition 08/2004, A5E00105475-05

6-5

Technical data of CPU 31xC
6.2 CPU 312C
Technical data
Block status

Yes

Single step

Yes

Breakpoints

Diagnostic buffer

Yes

•

Number of entries (not configurable)

Max. 100

Communication functions
PG/OP communication

Yes

Global data communication

Yes

•

Number of GD circuits

•

Number of GD packets
– Sending stations
– Receiving stations

Max. 4

Length of GD packets
– Consistent data

max. 22 bytes

•

S7 basic communication
•
•

User data per request
Consistent data

Max. 4
Max. 4
22 bytes
Yes
max. 76 bytes
76 bytes (for X_SEND or X_RCV)
64 bytes (for X_PUT or X_GET as the server)

S7 communication
•

As server

Yes

•

User data per request
– Consistent data

max. 180 bytes (with PUT/GET)

S5-compatible communication

Yes (via CP and loadable FCs)

Number of connections

Max. 6

64 bytes

can be used for
•

•

PG communication
– Reserved (default)
– Configurable

Max. 5

OP communication
– Reserved (default)
– Configurable

Max. 5

S7-based communication
– Reserved (default)
– Configurable

Max. 2

Routing

1
from 1 to 5
1
from 1 to 5
2
from 0 to 2
No

Interfaces
1st interface
Type of interface

6-6

Integrated RS485 interface

Physics

RS 485

electrically isolated

Interface power supply
(15 to 30 VDC)

Max. 200 mA

CPU 31xC and CPU 31x, Technical data
Manual, Edition 08/2004, A5E00105475-05

Technical data of CPU 31xC
6.2 CPU 312C
Technical data
Functionality
•

MPI

Yes

•

PROFIBUS DP

•

Point-to-point communication

MPI
Services
•

PG/OP communication

Yes

•

Routing

•

Global data communication

Yes

•

S7 basic communication

Yes

•

S7 communication
– As server
– As client

Yes
No

•

Transmission rates

max. 187.5 kbps

Programming
Programming language

LAD/FBD/STL

Available instructions

see the Instruction List

Nesting levels

System functions (SFCs)

see the Instruction List

System function blocks (SFBs)

see the Instruction List

User program security

Yes

Integrated I/O
•

Default addresses of the integrated
– Digital inputs
– Digital outputs

124.0 to 125.1
124.0 to 124.5

Integrated functions
Counters

2 channels (see the Manual Technological
Functions)

Frequency counters

2 channels, max. 10 kHz (see the Manual
Technological Functions)

Pulse outputs

2 channels for pulse width modulation, max.
2.5 kHz (see the Manual Technological
Functions)

Controlled positioning

Integrated "Controlling" SFB

Dimensions
Mounting dimensions W x H x D (mm)

80 x 125 x 130

Weight

409 g

Voltages and currents
Power supply (rated value)
•

Permitted range

24 VDC
20.4 V to 28.8 V

Current consumption (no-load operation)

Typically 60 mA

Inrush current

Typically 11 A

Power consumption (nominal value)

500 mA

CPU 31xC and CPU 31x, Technical data
Manual, Edition 08/2004, A5E00105475-05

6-7

Technical data of CPU 31xC
6.3 CPU 313C
Technical data
I2t

0.7 A2s

External fusing of power supply lines
(recommended)

LS switch Type C min. 2 A,
LS switch Type B min. 4 A

Power loss

Typically 6 W

Reference
In Chapter Specifications of the integrated I/O you can find
• the specifications of integrated I/Os under Digital inputs of CPUs 31xC and Digital outputs
of CPUs 31xC.
• the block diagrams of the integrated I/Os under Arrangement and usage of integrated
I/Os.

6.3

CPU 313C

Technical data
Table 6-4

Technical data of CPU 313C

Technical data
CPU and version
Order number

6ES7 313-5BE01-0AB0

•

Hardware version

•

Firmware version

V2.0.0

•

Associated programming package

STEP 7 as of V 5.2 + SP 1
(please use previous CPU for STEP 7 V 5.1 +
SP 3 or later)

Memory
RAM
•

Integrated

32 KB

•

Expandable

Load memory

Plugged in with MMC (max. 8 MB)

Data storage life on the MMC
(following final programming)

At least 10 years

Buffering

Guaranteed by MMC (maintenance-free)

Execution times
Processing times of

6-8

•

Bit operations

min. 0.1 μs

•

Word instructions

min. 0.2 μs

•

Fixed-point arithmetic

min. 2 μs

•

Floating-point arithmetic

min. 6 μs

CPU 31xC and CPU 31x, Technical data
Manual, Edition 08/2004, A5E00105475-05

Technical data of CPU 31xC
6.3 CPU 313C
Technical data
Timers/counters and their retentivity
S7 counters

256

•

Retentive memory

Configurable

•

Default

from C0 to C7

•

Counting range

0 to 999

IEC Counters
•

Type

•

Number

S7 timers

Yes
SFB
unlimited (limited only by RAM size)
256

•

Retentive memory

Configurable

•

Default

Not retentive

•

Timer range

10 ms to 9990 s

IEC Timers

Yes

•

Type

SFB

•

Number

unlimited (limited only by RAM size)

Data areas and their retentivity
Flag bits
•

Retentive memory

•

Default retentivity

256 bytes
Configurable
MB0 to MB15

Clock flag bits

8 (1 byte per flag bit)

Data blocks

Max. 511
(DB 1 to DB 511)

•

Length

Local data per priority class

max. 16 KB
max. 510 bytes

Blocks
Total

1024 (DBs, FCs, FBs)
The maximum number of blocks that can be
loaded may be reduced if you are using another
MMC.

OBs
•

Length

see the Instruction List
max. 16 KB

Nesting depth
•

Per priority class

•

additional within an error OB

FBs

Max. 512
(FB 0 to FB 511)

•

Length

FCs

max. 16 KB
Max. 512
(FC 0 to FC 511)

•

Length

CPU 31xC and CPU 31x, Technical data
Manual, Edition 08/2004, A5E00105475-05

max. 16 KB

6-9

Technical data of CPU 31xC
6.3 CPU 313C
Technical data
Address areas (I/O)
Total I/O address area

max. 1024 bytes/1024 bytes
(can be freely addressed)

I/O process image

128 bytes/128 bytes

Digital channels

Max. 1016

•

of those local

Max. 992

•

Integrated channels

24 DI / 16 DO

Analog channels

Max. 253

•

of those local

Max. 248

•

Integrated channels

4 + 1 AI / 2 AO

Assembly
Racks

Max. 4

Modules per rack

max. 8; max. 7 in rack 3

Number of DP masters
•

Integrated

None

•

via CP

Max. 2

Number of function modules and communication
processors you can operate
•

Max. 8

•

CP (PtP)

Max. 8

•

CP (LAN)

Max. 6

Time-of-day
Real-time clock

Yes (HW clock)

•

Buffered

Yes

•

Buffered period

Typically 6 weeks (at an ambient temperature of
40 °C)

•

Behavior of the clock on expiration of the
buffered period

The clock keeps running, continuing at the timeof-day it had when power was switched off.

•

Accuracy

Deviation per day < 10 s

Operating hours counter

•

Number

•

Value range

2 31 hours

•

Granularity

1 hour

•

Retentive

Yes; must be manually restarted after every
restart

(if SFC 101 is used)

Clock synchronization

Yes

•

In the PLC

Master

•

On MPI

Master/slave

S7 signaling functions
Number of stations that can be logged on for
signaling functions

6-10

Max. 8
(depends on the number of connections
configured for PG / OP and S7 basic
communication)

CPU 31xC and CPU 31x, Technical data
Manual, Edition 08/2004, A5E00105475-05

Technical data of CPU 31xC
6.3 CPU 313C
Technical data
Process diagnostics messages
•

Simultaneously enabled interrupt S blocks

Yes
Max. 20

Testing and commissioning functions
Status/control variables

Yes

•

Variables

Inputs, outputs, memory bits, DBs, timers,
counters

•

Number of variables
– of those as status variable
– of those as control variable

Max. 30

Forcing

Max. 30
Max. 14
Yes

•

Variables

Inputs, outputs

•

Number of variables

Max. 10

Block status

Yes

Single step

Yes

Breakpoints

Diagnostic buffer

Yes

•

Number of entries (not configurable)

Max. 100

Communication functions
PG/OP communication

Yes

Global data communication

Yes

•

Number of GD circuits

•

Number of GD packets
– Sending stations
– Receiving stations

Max. 4

Length of GD packets
– Consistent data

max. 22 bytes

•

S7 basic communication
•

User data per request
– Consistent data

Max. 4
Max. 4
22 bytes
Yes
max. 76 bytes
76 bytes (for X_SEND or X_RCV)
64 bytes (for X_PUT or X_GET as the server)

S7 communication
•

As server

Yes

•

as client

Yes (via CP and loadable FBs)

•

User data per request
– Consistent data

max. 180 bytes (with PUT/GET)

S5-compatible communication

Yes (via CP and loadable FCs)

Number of connections

Max. 8

CPU 31xC and CPU 31x, Technical data
Manual, Edition 08/2004, A5E00105475-05

64 bytes

6-11

Technical data of CPU 31xC
6.3 CPU 313C
Technical data
can be used for
•

•

PG communication
– Reserved (default)
– Configurable

Max. 7

OP communication
– Reserved (default)
– Configurable

Max. 7

S7 basic communication
– Reserved (default)
– Configurable

Max. 4

Routing

1
from 1 to 7
1
from 1 to 7
4
from 0 to 4
No

Interfaces
1st interface
Type of interface

Integrated RS485 interface

Physics

RS 485

electrically isolated

Interface power supply
(15 to 30 VDC)

Max. 200 mA

Functionality
•

MPI

Yes

•

PROFIBUS DP

•

PtP communication

MPI
Services
•

PG/OP communication

Yes

•

Routing

•

Global data communication

Yes

•

S7 basic communication

Yes

•

S7 communication
– As server
– As client

Yes
No (but via CP and loadable FBs)

•

Transmission rates

max. 187.5 kbps

Programming

6-12

Programming language

LAD/FBD/STL

Available instructions

see the Instruction List

Nesting levels

System functions (SFCs)

see the Instruction List

System function blocks (SFBs)

see the Instruction List

User program security

Yes

CPU 31xC and CPU 31x, Technical data
Manual, Edition 08/2004, A5E00105475-05

Technical data of CPU 31xC
6.3 CPU 313C
Technical data
Integrated I/O
•

Default addresses of the integrated
– Digital inputs
– Digital outputs
– Analog inputs
– Analog outputs

124.0 to 126.7
124.0 to 125.7
752 to 761
752 to 755

Integrated functions
Counters

3 channels (see the Manual Technological
Functions)

Frequency counters

3 channels, max. 30 kHz (see the Manual
Technological Functions)

Pulse outputs

3 channels for pulse width modulation, max. 2.5
kHz (see the Manual Technological Functions)

Controlled positioning

Integrated "Controlling" SFB

PID controller (see the Manual Technological
Functions)

Dimensions
Mounting dimensions W x H x D (mm)

120 x 125 x 130

Weight

660 g

Voltages and currents
Power supply (rated value)
•

Permitted range

24 VDC
20.4 V to 28.8 V

Current consumption (no-load operation)

Typically 150 mA

Inrush current

Typically 11 A

Power consumption (nominal value)

700 mA

I2t

0.7 A2s

External fusing of power supply lines
(recommended)

LS switch Type C min. 2 A,

Power loss

Typically 14 W

LS switch Type B min. 4 A,

Reference
In Chapter Specifications of the integrated I/O you can find
• the specifications of integrated I/O under Digital inputs of CPUs 31xC, Digital outputs of
CPUs 31xC, Analog inputs of CPUs 31xC and Analog outputs of CPUs 31xC.
• the block diagrams of the integrated I/Os under Arrangement and usage of integrated
I/Os.

CPU 31xC and CPU 31x, Technical data
Manual, Edition 08/2004, A5E00105475-05

6-13

Technical data of CPU 31xC
6.4 CPU 313C-2 PtP and CPU 313C-2 DP

6.4

CPU 313C-2 PtP and CPU 313C-2 DP

Technical data
Table 6-5

Technical data for CPU 313C-2 PtP/ CPU 313C-2 DP

Technical data
CPU 313C-2 PtP

CPU 313C-2 DP

CPU and version

CPU 313C-2 PtP

CPU 313C-2 DP

Order number

6ES7 313-6BE01-0AB0

6ES7 313-6CE01-0AB0

•

Hardware version

•

Firmware version

V2.0.0

Associated programming package

Memory

STEP 7 as of V 5.2 + SP 1

(please use previous CPU for STEP7
V 5.1 + SP 3 or later)

(please use previous CPU for STEP 7
V 5.1 + SP 3 or later)

CPU 313C-2 PtP

CPU 313C-2 DP

RAM
•

Integrated

32 KB

•

Expandable

Load memory

Plugged in with MMC (max. 8 MB)

Data storage life on the MMC
(following final programming)

At least 10 years

Buffering

Guaranteed by MMC (maintenance-free)

Execution times

CPU 313C-2 PtP

CPU 313C-2 DP

Processing times of
•

Bit operations

min. 0.1 μs

•

Word instructions

min. 0.2 μs

•

Fixed-point arithmetic

min. 2 μs

•

Floating-point arithmetic

min. 6 μs

Timers/counters and their retentivity

CPU 313C-2 PtP

S7 counters

256

•

Retentive memory

Configurable

•

Default

from C0 to C7

•

Counting range

0 to 999

IEC Counters
•

Type

•

Number

S7 timers

Yes
SFB
unlimited (limited only by RAM size)
256

•

Retentive memory

Configurable

•

Default

Not retentive

•

Timer range

10 ms to 9990 s

IEC Timers

Yes

•

Type

SFB

•

Number

unlimited (limited only by RAM size)

6-14

CPU 313C-2 DP

CPU 31xC and CPU 31x, Technical data
Manual, Edition 08/2004, A5E00105475-05

Technical data of CPU 31xC
6.4 CPU 313C-2 PtP and CPU 313C-2 DP
Technical data
CPU 313C-2 PtP

CPU 313C-2 DP

Data areas and their retentivity

CPU 313C-2 PtP

CPU 313C-2 DP

Flag bits

256 bytes

•

Retentive memory

•

Default retentivity

Configurable
MB0 to MB15

Clock flag bits

8 (1 byte per flag bit)

Data blocks

Max. 511
(DB 1 to DB 511)

•

Length

max. 16 KB

Local data per priority class

max. 510 bytes

Blocks

CPU 313C-2 PtP

Total

1024 (DBs, FCs, FBs)

CPU 313C-2 DP

The maximum number of blocks that can be loaded may be reduced if you are
using another MMC.
OBs
•

Length

see the Instruction List
max. 16 KB

Nesting depth
•

Per priority class

•

additional within an error OB

FBs

Max. 512
(FB 0 to FB 511)

•

Length

FCs

max. 16 KB
Max. 512
(FC 0 to FC 511)

•

Length

max. 16 KB

Address areas (I/O)

CPU 313C-2 PtP

CPU 313C-2 DP

Total I/O address area

max. 1024 bytes/1024 bytes
(can be freely addressed)

None

max. 1008 bytes

I/O process image

128 bytes/128 bytes

Digital channels

•

Distributed

Max. 1008

Max. 8192

•

of those local

Max. 992

•

Integrated channels

16 DI / 16 DO

Analog channels

Max. 248

Max. 512

•

of those local

Max. 248

•

Integrated channels

None

Assembly

CPU 313C-2 PtP

CPU 313C-2 DP

Racks

Max. 4

Modules per rack

max. 8; max. 7 in rack 3

Number of DP masters
•

Integrated

•

via CP

Max. 1

CPU 31xC and CPU 31x, Technical data
Manual, Edition 08/2004, A5E00105475-05

6-15

Technical data of CPU 31xC
6.4 CPU 313C-2 PtP and CPU 313C-2 DP
Technical data
CPU 313C-2 PtP

CPU 313C-2 DP

Number of function modules and
communication processors you can
operate
•

Max. 8

•

CP (PtP)

Max. 8

•

CP (LAN)

Max. 6

Time-of-day
Real-time clock

CPU 313C-2 PtP

CPU 313C-2 DP

Yes (HW clock)

•

Buffered

Yes

•

Buffered period

Typically 6 weeks (at an ambient temperature of 40 °C)

•

Behavior of the clock on expiration of
the buffered period

The clock keeps running, continuing at the time-of-day it had when power was
switched off.

•

Accuracy

Operating hours counter

Deviation per day < 10 s
1

•

Number

•

Value range

2 31 hours
(if SFC 101 is used)

•

Granularity

1 hour

•

Retentive

Yes; must be manually restarted after every restart

Clock synchronization

Yes

•

In the PLC

Master

•

On MPI

Master/slave

S7 signaling functions

CPU 313C-2 PtP

Number of stations that can log in for
signaling functions (e.g. OS)

Max. 8

Process diagnostics messages

Yes

•

Simultaneously enabled interrupt S
blocks

CPU 313C-2 DP

(depends on the number of connections configured for PG / OP and S7 basic
communication)
Max. 20

Testing and commissioning functions

CPU 313C-2 PtP

Status/control variables

Yes

CPU 313C-2 DP

•

Variables

Inputs, outputs, memory bits, DBs, timers, counters

•

Number of variables
– Of those as status variable
– Of those as control variable

Max. 30

Forcing
•

Variables

•

Number of variables

Max. 30
Max. 14
Yes
Inputs, outputs
Max. 10

Block status

Yes

Single step

Yes

Breakpoints

Diagnostic buffer

Yes

•

Number of entries (not configurable)

6-16

Max. 100

CPU 31xC and CPU 31x, Technical data
Manual, Edition 08/2004, A5E00105475-05

Technical data of CPU 31xC
6.4 CPU 313C-2 PtP and CPU 313C-2 DP
Technical data
CPU 313C-2 PtP

CPU 313C-2 DP

Communication functions

CPU 313C-2 PtP

CPU 313C-2 DP

PG/OP communication

Yes

Global data communication

Yes

•

Number of GD circuits

•

Number of GD packets
– Sending stations
– Receiving stations

Max. 4

Length of GD packets
– Consistent data

max. 22 bytes

•

S7 basic communication
•

User data per request
– Consistent data

Max. 4
Max. 4
22 bytes
Yes (server)
max. 76 bytes
76 bytes (for X_SEND or X_RCV)
64 bytes (for X_PUT or X_GET as the server)

S7 communication
•

As server

Yes

•

as client

Yes (via CP and loadable FBs)

•

User data per request
– Consistent data

max. 180 bytes (with PUT/GET)

S5-compatible communication

Yes (via CP and loadable FCs)

Number of connections

Max. 8

64 bytes

can be used for
•

•

PG communication
– Reserved (default)
– Configurable

Max. 7

OP communication
– Reserved (default)
– Configurable

Max. 7

S7-based communication
– Reserved (default)
– Configurable

Max. 4

1
from 1 to 7
1
from 1 to 7
4
from 0 to 4

Routing

Max. 4

Interfaces

CPU 313C-2 PtP

CPU 313C-2 DP

1st interface
Type of interface

Integrated RS485 interface

Physics

RS 485

electrically isolated

Interface power supply (15 to 30 VDC)

Max. 200 mA

Functionality
•

MPI

Yes

•

PROFIBUS DP

•

Point-to-point communication

CPU 31xC and CPU 31x, Technical data
Manual, Edition 08/2004, A5E00105475-05

6-17

Technical data of CPU 31xC
6.4 CPU 313C-2 PtP and CPU 313C-2 DP
Technical data
CPU 313C-2 PtP

CPU 313C-2 DP

MPI
Services
•

PG/OP communication

Yes

•

Routing

•

Global data communication

Yes

•

S7 basic communication

Yes

•

S7 communication
– As server
– As client

•
•
•

Yes

Yes
No (but via CP and loadable FBs)

Type of interface

Integrated RS422/RS485 interface

Integrated RS485 interface

Physics

RS 422/485

RS 485

electrically isolated

Yes

Interface power supply (15 to 30 VDC)

Max. 200 mA

Number of connections

None

Functionality
•

MPI

•

PROFIBUS DP

Yes

•

Point-to-point communication

Yes

–

8
Yes

DP master
Number of connections
Services
•

PG/OP communication

–

•

Routing

–

Yes

•

Global data communication

–

•

S7 basic communication

–

•

S7 communication

–

•

Constant bus cycle time

–

Yes

•

SYNC/FREEZE

–

Yes

•

Enable/disable DP slaves

–

Yes

•

DPV1

–

Yes

•

Transmission rates

–

Up to 12 Mbps

•

Number of DP slaves per station

–

Max. 32

•

Address area

–

Max. 1 KB I / 1 KB O

•

User data per DP slave

–

Max. 244 bytes I / 244 bytes O

6-18

CPU 31xC and CPU 31x, Technical data
Manual, Edition 08/2004, A5E00105475-05

Technical data of CPU 31xC
6.4 CPU 313C-2 PtP and CPU 313C-2 DP
Technical data
CPU 313C-2 PtP

CPU 313C-2 DP

–

DP slave
Number of connections
Services
•

PG/OP communication

–

Yes

•

Routing

–

Yes (only if interface is active)

•

Global data communication

–

•

S7 basic communication

–

•

S7 communication

–

•

Direct data exchange

–

Yes

•

Transmission rates

–

Up to 12 Mbps

•

Automatic baud rate search

–

Yes (only if interface is passive)

•

Intermediate memory

–

244 bytes I / 244 bytes O

•

Address areas

–

Max. 32, with max. 32 bytes each

•

DPV1

–

The latest GSD file is available at:

GSD file

http://www.ad.siemens.de/support
in the Product Support area
Point-to-point communication
•

Transmission rates

38.4 kbps half duplex
19.2 kbps full duplex

–

•

Cable length

Max. 1200 m

–

•

User program can control the interface Yes

–

•

The interface can trigger a break or an Yes (message with break ID)
interrupt in the user program

–

•

Protocol driver

3964(R); ASCII

–

CPU 313C-2 PtP

CPU 313C-2 DP

Programming
Programming language

LAD/FBD/STL

Available instructions

see the Instruction List

Nesting levels

System functions (SFCs)

see the Instruction List

System function blocks (SFBs)

see the Instruction List

User program security

Yes

Integrated I/O

CPU 313C-2 PtP

•

Default addresses of the integrated
– Digital inputs
– Digital outputs

CPU 31xC and CPU 31x, Technical data
Manual, Edition 08/2004, A5E00105475-05

CPU 313C-2 DP

124.0 to 125.7
124.0 to 125.7

6-19

Technical data of CPU 31xC
6.4 CPU 313C-2 PtP and CPU 313C-2 DP
Technical data
CPU 313C-2 PtP

CPU 313C-2 DP

Integrated functions
Counters

3 channels (see the Manual Technological Functions)

Frequency counters

3 channels, max. 30 kHz (see the Manual Technological Functions)

Pulse outputs

3 channels for pulse width modulation, max. 2.5 kHz (see the Manual
Technological Functions)

Controlled positioning

Integrated "Controlling" SFB

PID controller (see the Manual Technological Functions)

Dimensions

CPU 313C-2 PtP

Mounting dimensions W x H x D (mm)

120 x 125 x 130

Weight

approx. 566 g

Voltages and currents

CPU 313C-2 PtP

Power supply (rated value)

24 VDC

•

Permitted range

CPU 313C-2 DP

20.4 V to 28.8 V

Current consumption (no-load operation)

Typically 100 mA

Inrush current

Typically 11 A

Power consumption (nominal value)

700 mA

900 mA

I2t

A2s

0.7

External fusing of power supply lines
(recommended)

LS switch type B: min. 4 A, type C: min. 2 A

Power loss

Typically 10 W

Reference
In Chapter Specifications of the integrated I/O are found
• under Digital inputs of CPUs 31xC and Digital outputs of CPUs 31xC the technical data of
integrated I/Os.
• the block diagrams of the integrated I/Os under Arrangement and usage of integrated
I/Os.

6-20

CPU 31xC and CPU 31x, Technical data
Manual, Edition 08/2004, A5E00105475-05

Technical data of CPU 31xC
6.5 CPU 314C-2 PtP and CPU 314C-2 DP

6.5

CPU 314C-2 PtP and CPU 314C-2 DP

Technical data
Table 6-6

Technical data of CPU 314C-2 PtP and CPU 314C-2 DP

Technical data
CPU 314C-2 PtP

CPU 314C-2 DP

CPU and version

CPU 314C-2 PtP

CPU 314C-2 DP

Order number

6ES7 314-6BF01-0AB0

6ES7 314-6CF01-0AB0

•

Hardware version

•

Firmware version

V2.0.0

Associated programming package

Memory

STEP 7 as of V 5.2 + SP 1

(please use previous CPU for STEP 7
V 5.1 + SP 3 or later)

CPU 314C-2 PtP

CPU 314C-2 DP

RAM
•

Integrated

48 KB

•

Expandable

Load memory

Plugged in with MMC (max. 8 MB)

Data storage life on the MMC
(following final programming)

At least 10 years

Buffering

Guaranteed by MMC (maintenance-free)

Execution times

CPU 314C-2 PtP

CPU 314C-2 DP

Processing times of
•

Bit operations

Min. 0.1 μs

•

Word instructions

Min. 0.2 μs

•

Fixed-point arithmetic

Min. 2 μs

•

Floating-point arithmetic

Min. 6 μs

Timers/counters and their retentivity

CPU 314C-2 PtP

S7 counters

256

•

Retentive memory

Configurable

•

Default

from C0 to C7

•

Counting range

0 to 999

IEC Counters
•

Type

•

Number

S7 timers

Yes
SFB
unlimited (limited only by RAM size)
256

•

Retentive memory

Configurable

•

Default

Not retentive

•

Timer range

10 ms to 9990 s

IEC Timers

Yes

•

Type

SFB

•

Number

unlimited (limited only by RAM size)

CPU 31xC and CPU 31x, Technical data
Manual, Edition 08/2004, A5E00105475-05

CPU 314C-2 DP

6-21

Technical data of CPU 31xC
6.5 CPU 314C-2 PtP and CPU 314C-2 DP
Technical data
CPU 314C-2 PtP

CPU 314C-2 DP

Data areas and their retentivity

CPU 314C-2 PtP

CPU 314C-2 DP

Flag bits

256 bytes

•

Retentive memory

•

Default retentivity

Configurable
MB0 to MB15

Clock flag bits

8 (1 byte per flag bit)

Data blocks

Max. 511
(DB 1 to DB 511)

•

Length

max. 16 KB

Local data per priority class

max. 510 bytes

Blocks

CPU 314C-2 PtP

Total

1024 (DBs, FCs, FBs)

CPU 314C-2 DP

The maximum number of blocks that can be loaded may be reduced if you are
using another MMC.
OBs
•

Length

See the Instruction List
max. 16 KB

Nesting depth
•

Per priority class

•

additional within an error OB

FBs

Max. 512
(FB 0 to FB 511)

•

Length

FCs

max. 16 KB
Max. 512
(FC 0 to FC 511)

•

Length

max. 16 KB

Address areas (I/O)

CPU 314C-2 PtP

CPU 314C-2 DP

Total I/O address area

max. 1024 bytes/1024 bytes
(can be freely addressed)

None

max. 1000 bytes

I/O process image

128 bytes/128 bytes

Digital channels

•

Distributed

Max. 1016

Max. 8192

•

of those local

Max. 992

•

Integrated channels

24 DI / 16 DO

Analog channels

Max. 253

Max. 512

•

of those local

Max. 248

•

Integrated channels

4 + 1 AI / 2 AO

Assembly

CPU 314C-2 PtP

CPU 314C-2 DP

Racks

Max. 4

Modules per rack

max. 8; max. 7 in rack 3

Number of DP masters
•

Integrated

•

via CP

Max. 1

6-22

CPU 31xC and CPU 31x, Technical data
Manual, Edition 08/2004, A5E00105475-05

Technical data of CPU 31xC
6.5 CPU 314C-2 PtP and CPU 314C-2 DP
Technical data
CPU 314C-2 PtP

CPU 314C-2 DP

Number of function modules and
communication processors you can
operate
•

Max. 8

•

CP (PtP)

Max. 8

•

CP (LAN)

Max. 10

Time-of-day
Real-time clock

CPU 314C-2 PtP

CPU 314C-2 DP

Yes (HW clock)

•

Buffered

Yes

•

Buffered period

Typically 6 weeks (at an ambient temperature of 40 °C)

•

Behavior of the clock on expiration
of the buffered period

The clock keeps running, continuing at the time-of-day it had when power was
switched off.

•

Accuracy

Operating hours counter

Deviation per day < 10 s
1

•

Number

•

Value range

2 31 hours
(if SFC 101 is used)

•

Granularity

1 hour

•

Retentive

Yes; must be manually restarted after every restart

Clock synchronization

Yes

•

In the PLC

Master

•

On MPI

Master/slave

S7 signaling functions

CPU 314C-2 PtP

Number of stations that can log in for
signaling functions (e.g. OS)

Max. 12

Process diagnostics messages
•

Simultaneously enabled interrupt S
blocks

CPU 314C-2 DP

(depends on the number of connections configured for PG / OP and S7 basic
communication)
Yes
Max. 40

Testing and commissioning functions

CPU 314C-2 PtP

Status/control variables

Yes

CPU 314C-2 DP

•

Variables

Inputs, outputs, memory bits, DBs, timers, counters

•

Number of variables
– of those as status variable
– of those as control variable

Max. 30

Forcing
•

Variables

•

Number of variables

Max. 30
Max. 14
Yes
Inputs, outputs
Max. 10

Block status

Yes

Single step

Yes

Breakpoints

Diagnostic buffer

Yes

•

Number of entries (not configurable) Max. 100

CPU 31xC and CPU 31x, Technical data
Manual, Edition 08/2004, A5E00105475-05

6-23

Technical data of CPU 31xC
6.5 CPU 314C-2 PtP and CPU 314C-2 DP
Technical data
CPU 314C-2 PtP

CPU 314C-2 DP

Communication functions

CPU 314C-2 PtP

CPU 314C-2 DP

PG/OP communication

Yes

Global data communication

Yes

•

Number of GD circuits

•

Number of GD packets
– Sending stations
– Receiving stations

Max. 4

Length of GD packets
– Consistent data

max. 22 bytes

•

S7 basic communication
•

User data per request
– Consistent data

Max. 4
Max. 4
22 bytes
Yes
max. 76 bytes
76 bytes (for X_SEND or X_RCV)
64 bytes (for X_PUT or X_GET as the server)

S7 communication
•

As server

Yes

•

as client

Yes (via CP and loadable FBs)

•

User data per request
– Consistent data

max. 180 bytes (with PUT/GET)

S5-compatible communication

Yes (via CP and loadable FCs)

Number of connections

Max. 12

64 bytes

can be used for
•

•

PG communication
– Reserved (default)
– Configurable

Max. 11

OP communication
– Reserved (default)
– Configurable

Max. 11

S7-based communication
– Reserved (default)
– Configurable

Max. 8

1
from 1 to 11
1
from 1 to 11
8
from 0 to 8

Routing

Max. 4

Interfaces

CPU 314C-2 PtP

CPU 314C-2 DP

1st interface
Type of interface

Integrated RS485 interface

Physics

RS 485

electrically isolated

Interface power supply (15 to 30 VDC)

Max. 200 mA

Functionality
•

MPI

Yes

•

PROFIBUS DP

•

Point-to-point communication

6-24

CPU 31xC and CPU 31x, Technical data
Manual, Edition 08/2004, A5E00105475-05

Technical data of CPU 31xC
6.5 CPU 314C-2 PtP and CPU 314C-2 DP
Technical data
CPU 314C-2 PtP

CPU 314C-2 DP

MPI
Number of connections

Services
•

PG/OP communication

Yes

•

Routing

•

Global data communication

Yes

•

S7 basic communication

Yes

•

S7 communication
– As server
– As client

Yes

Transmission rates

max. 187.5 kbps

•

Yes

No (but via CP and loadable FBs)

2nd interface

CPU 314C-2 PtP

CPU 314C-2 DP

Type of interface

Integrated RS422/RS485 interface

Integrated RS485 interface

Physics

RS 422/485

RS 485

electrically isolated

Yes

Interface power supply (15 to 30 VDC)

Max. 200 mA

Number of connections

None

Functionality
•

MPI

•

PROFIBUS DP

Yes

•

Point-to-point communication

Yes

–

DP master
Number of connections
Services
•

PG/OP communication

–

Yes

•

Routing

–

Yes

•

Global data communication

–

•

S7 basic communication

–

•

S7 communication

–

•

Constant bus cycle time

–

Yes

•

SYNC/FREEZE

–

Yes

•

Enable/disable DP slaves

–

Yes

•

DPV1

–

Yes

•

Transmission rates

–

Up to 12 Mbps

•

Number of DP slaves per station

–

Max. 32

•

Address area

–

Max. 1 KB I / 1 KB O

•

User data per DP slave

–

max. 244 bytes I / 244 bytes O

CPU 31xC and CPU 31x, Technical data
Manual, Edition 08/2004, A5E00105475-05

6-25

Technical data of CPU 31xC
6.5 CPU 314C-2 PtP and CPU 314C-2 DP
Technical data
CPU 314C-2 PtP

CPU 314C-2 DP

–

DP slave
Number of connections
Services
•

PG/OP communication

–

Yes

•

Routing

–

Yes (only if interface is active)

•

Global data communication

–

•

S7 basic communication

–

•

S7 communication

–

•

Direct data exchange

–

Yes

•

Transmission rates

–

Up to 12 Mbps

•

Intermediate memory

–

244 bytes I / 244 bytes O

•

Automatic baud rate search

–

Yes (only if interface is passive)

•

Address areas

•

DPV1

GSD file

Max. 32, with max. 32 bytes each
–

–

The latest GSD file is available at:
http://www.ad.siemens.de/support
in the Product Support area

Point-to-point communication
•

Transmission rates

38.4 kbps half duplex
19.2 kbps full duplex

–

•

Cable length

Max. 1200 m

–

•

User program can control the
interface

Yes

–

•

The interface can trigger a break or
an interrupt in the user program

Yes (message with break ID)

–

•

Protocol driver

3964 (R); ASCII and RK512

–

Programming

CPU 314C-2 PtP

CPU 314C-2 DP

Programming language

LAD/FBD/STL

Available instructions

see the Instruction List

Nesting levels

System functions (SFCs)

see the Instruction List

System function blocks (SFBs)

see the Instruction List

User program security

Yes

Integrated I/O

CPU 314C-2 PtP

•

Default addresses of the integrated
– Digital inputs
– Digital outputs
– Analog inputs
– Analog outputs

6-26

CPU 314C-2 DP

124.0 to 126.7
124.0 to 125.7
752 to 761
752 to 755

CPU 31xC and CPU 31x, Technical data
Manual, Edition 08/2004, A5E00105475-05

Technical data of CPU 31xC
6.5 CPU 314C-2 PtP and CPU 314C-2 DP
Technical data
CPU 314C-2 PtP

CPU 314C-2 DP

Integrated functions
Counters

4 channels (see the Manual Technological Functions)

Frequency counters

4 channels, max. 60 kHz (see the Manual Technological Functions)

Pulse outputs

4 channels for pulse width modulation, max. 2.5 kHz (see the Manual
Technological Functions)

Controlled positioning

1 channel (see the Manual Technological Functions)

Integrated "Controlling" SFB

PID controller (see the Manual Technological Functions)

Dimensions

CPU 314C-2 PtP

Mounting dimensions W x H x D (mm)

120 x 125 x 130

Weight

approx. 676 g

Voltages and currents

CPU 314C-2 PtP

Power supply (rated value)

24 VDC

•

Permitted range

CPU 314C-2 DP

20.4 V to 28.8 V

Current consumption (no-load
operation)

Typically 150 mA

Inrush current

Typically 11 A

Power consumption (nominal value)

800 mA

I2t

0.7

External fusing of power supply lines
(recommended)

LS switch type C min. 2 A,
LS switch type B min. 4 A

Power loss

Typically 14 W

CPU 31xC and CPU 31x, Technical data
Manual, Edition 08/2004, A5E00105475-05

CPU 314C-2 DP

1000 mA

A2s

6-27

Technical data of CPU 31xC
6.6 Technical data of the integrated I/O

6.6

Technical data of the integrated I/O

6.6.1

Arrangement and usage of integrated I/Os

Introduction
Integrated I/Os of CPUs 31xC can be used for technological functions or as standard I/O.
The figures below illustrate possible usage of I/Os integrated in the CPUs.

Reference
Further information on integrated I/O is found in the Manual Technical Functions.

CPU 312C: Pin-out of the integrated DI/DO (connector X11)
Standard

Interrupt
input

DI
DI
DI
DI
DI
DI
DI
DI
DI
DI

X
X
X
X
X
X
X
X
X
X

DO
DO
DO
DO
DO
DO

Zn
A, B
Vn
X
HW gate
Latch

6-28

X11

Count
Z0 (A)
Z0 (B)
Z0 (HW gate)
Z1 (A)
Z1 (B)
Z1 (HW gate)
Latch 0
Latch 1

V0
V1

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

DI+0.0
DI+0.1
DI+0.2
DI+0.3
DI+0.4
DI+0.5
DI+0.6
DI+0.7

DI+1.0
DI+1.1
2M
1L+
DO+0.0
DO+0.1
DO+0.2
DO+0.3
DO+0.4
DO+0.5
1M

Counter n
Encoder signals
Comparator n
Pin usable if not assigned to technology functions
Gate control
Store counter distance

CPU 31xC and CPU 31x, Technical data
Manual, Edition 08/2004, A5E00105475-05

Technical data of CPU 31xC
6.6 Technical data of the integrated I/O

Block diagram of the integrated digital I/O
1
2
3
4
5
6
7

9
10

CPU interface

12
2M
1L+

13
14
15
16
17
18
19
20

CPU 31xC and CPU 31x, Technical data
Manual, Edition 08/2004, A5E00105475-05

6-29

Technical data of CPU 31xC
6.6 Technical data of the integrated I/O

CPU 313C, CPU 313C-2 DP/PtP, CPU 314C-2 DP/PtP: DI/DO (connectors X11 and X12)
X11 of CPU 313C-2 PtP/DP
X12 of CPU 314C-2 PtP/DP

Standard Interrupt
Count
input
DI
Z0 (A)
X
X
Z0 (B)
X
X
Z0 (HW gate)
X
X
Z1 (A)
X
X
Z1(B)
X
X
Z1 (HW gate)
X
X
Z2 (A)
X
X
Z2 (B)
X
X
X
X
X
X
X
X
X
X

Zn
A, B
HW gate
Latch
Vn
Prob 0
Bero 0
R+, RRapid
Creep
CONV_EN
CONV_DIR
X

X
X
X
X
X
X
X
X

1)
Positioning
A0
B0
N0
Prob 0
Bero 0

Z2 (HW gate)
Z3 (A)
Z3 (B)
1)
Z3 (HW gate)
Z0 (Latch)
Z1 (Latch)
Z2 (Latch)
Z3 (Latch) 1)

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

1L+
DI+0.0
DI+0.1
DI+0.2
DI+0.3
DI+0.4
DI+0.5
DI+0.6
DI+0.7

2L+
DO+0.0
DO+0.1
DO+0.2
DO+0.3
DO+0.4
DO+0.5
DO+0.6
DO+0.7
2M
3L+

DI+1.0

DO+1.0

DI+1.1
DI+1.2
DI+1.3
DI+1.4
DI+1.5
DI+1.6
DI+1.7
1M

DO+1.1
DO+1.2
DO+1.3
DO+1.4
DO+1.5
DO+1.6
DO+1.7
3M

21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40

1) Count Standard
Positioning
DO
Digital Analog
V0
V1
V2
V3 1)
CONV_EN
CONV_DIR

R+
RRapid
Creep

X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X

Counter n
Encoder signals
Gate control
Store counter distance
Comparator n
Measuring probe 0
Reference point switch 0
Directional signal
Rapid traverse
Creep speed
Power section enable
Directional signal (only with control type "voltage 0 to 10 V or current from 0 to 10 mA and directional signal")
Pin usable if not assigned to technology functions

1) CPU 314C-2 only

Reference
Details are found in the Manual Technical Functions under Counting, Frequency

Measurement and Pulse Width Modulation

6-30

CPU 31xC and CPU 31x, Technical data
Manual, Edition 08/2004, A5E00105475-05

Technical data of CPU 31xC
6.6 Technical data of the integrated I/O

Block diagram of integrated digital I/O of CPUs 313C/313C-2/314C-2

11
12

CPU interface

1L+

2M
31
32

CPU 31xC and CPU 31x, Technical data
Manual, Edition 08/2004, A5E00105475-05

2L+

3L+

6-31

Technical data of CPU 31xC
6.6 Technical data of the integrated I/O

CPU 313C/314C-2: Pin-out of the integrated AI/AO and DI (connector X11)
X11
1)
Positioning

Standard
V
I
C
V
I
C
V
I
C
V
I
C

AI (Ch0)

AI (Ch1)

AI (Ch2)
AI (Ch3)
PT 100 (Ch4)
AO (Ch0)
AO (Ch1)

V
A
V
A

Control
output 0

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

PEWx+0

PEWx+2
PEWx+4

DI+2.0
DI+2.1
DI+2.2
DI+2.3
DI+2.4
DI+2.5
DI+2.6
DI+2.7
4M

PEWx+6
PEWx+8
PAW x+0
PAW x+2
MANA

21 Standard DI
22
X
23
X
24
X
25
X
26
X
27
X
28
X
29
X
30
31
32
33
34
35
36
37
38
39
40

Interrupt input
X
X
X
X
X
X
X
X

1) CPU 314C-2 only

Block diagram of integrated digital/analog I/O of CPUs 313C/314C-2
AI/A0

8DI

2
3

4
AI0
V

7
AI1
V
A

CH0

5
6

22
AI

25
AI
CH1

8
9

CH2

CPU interface

26
27
28
29
30

AI2

4M
11

13
AI3 14

AO0

15
AI4 16
V 17

AO1

A 18
V 19
A 20

31
AI

CH3

AI
PT100
U A0
I CH0
U A0
I CH1

Controller

35
36
37
38
39
40

MANA

6-32

CPU 31xC and CPU 31x, Technical data
Manual, Edition 08/2004, A5E00105475-05

Technical data of CPU 31xC
6.6 Technical data of the integrated I/O

Simultaneous usage of technological functions and standard I/O
Technological functions and standard I/O can be used simultaneously with appropriate
hardware. For example, you can use all digital inputs not used for counting functions as
standard DI.
Read access to inputs used by technological functions is possible. Write access to outputs
used by technological functions is not possible.

See also
CPU 312C (Page 6-3)
CPU 313C (Page 6-8)
CPU 313C-2 PtP and CPU 313C-2 DP (Page 6-14)
CPU 314C-2 PtP and CPU 314C-2 DP (Page 6-21)

CPU 31xC and CPU 31x, Technical data
Manual, Edition 08/2004, A5E00105475-05

6-33

Technical data of CPU 31xC
6.6 Technical data of the integrated I/O

6.6.2

Analog I/O

Wiring of the current/voltage inputs
The figure below shows the wiring diagram of the current/voltage inputs operated with
2-/4-wire measuring transducers.
Al0: Pin 2 to 4

+
2-wire
signal converter
-

AI2u

AI2I

AI2c

AI1: Pin 5 to 7
Al2: Pin 8 to 10

+ 24 V

Al3: Pin 11 to 13

MANA

We recommend connecting AIxC with MANA using a bridge.

Figure 6-1

Connection of a 2-wire measuring transducer to an analog current/voltage input of
CPU 313C/314C-2

L+
8

AI2I

AI2c

AI3u

AI3I

AI3c

6-34

4-wire
- signal converter

AI2 : Pin 8 to 10
AI3 : Pin 11 to 13

Figure 6-2

AI0 : Pin 2 to 4
AI1 : Pin 5 to 7

AI2u

MANA

Short-circuit non-wired input channels
and connect AlxC with MANA.
We recommend connecting AlxC with MANA
when using the 4-wire signal converter.

Connection of a 4-wire measuring transducer to an analog current/voltage input of
CPU 313C/314C-2

CPU 31xC and CPU 31x, Technical data
Manual, Edition 08/2004, A5E00105475-05

Technical data of CPU 31xC
6.6 Technical data of the integrated I/O

Measurement principle
31xC CPUs use the measurement principle of actual value encoding. Here, they operate
with a sampling rate of 1 kHz. That is, a new value is available at the peripheral input word
register once every millisecond. This value can then be read via user program (e.g. L PEW).
The "previous" value is read again if access times are shorter than 1 ms.

Integrated hardware low-pass filter
An integrated low-pass filter attenuates analog input signals of channel 0 to 3. They are
attenuated according to the trend in the figure below.

Attenuation
<1%
Internal
signal level

Attenuation
<10%

strong
attenuation

100 %

63 %

Inadmissible
input frequency

50 Hz

Figure 6-3

200 Hz

400 Hz

Input frequency

Low-pass characteristics of the integrated filter

Note
The maximum frequency of the input signal is 400 Hz.

CPU 31xC and CPU 31x, Technical data
Manual, Edition 08/2004, A5E00105475-05

6-35

Technical data of CPU 31xC
6.6 Technical data of the integrated I/O

Input filters (software filter)
The current / voltage inputs have a software filter for the input signals which can be
programmed with STEP 7. It filters the configured interference frequency (50/60 Hz) and
multiples thereof.
The selected interference suppression also determines the integration time.
At an interference suppression of 50 Hz the software filter forms the average based on the
last 20 measurements and saves the result as a measurement value.
You can suppress interference frequencies (50 Hz or 60 Hz) according to the parameters set
in STEP 7. A setting of 400 Hz will not suppress interference.
An integrated low-pass filter attenuates analog input signals of channel 0 to 3.
Selection in STEP 7
(Software filter)
50-Hz configuration
(mean value filter)

60-Hz configuration
(mean value filter)

A/D converter

400-Hz configuration

AIx

Hardware low-pass filter
(RC circuit)

Figure 6-4

6-36

Principle of interference suppression with STEP 7

CPU 31xC and CPU 31x, Technical data
Manual, Edition 08/2004, A5E00105475-05

Technical data of CPU 31xC
6.6 Technical data of the integrated I/O
In the two graphics below we illustrate how the 50 Hz and 60 Hz interference suppression
work

Example of a 50-Hz parasitic frequency suppression (integration time corresponds to 20 ms)

1.05 ms

Value
1

Value
2

Value
3

Cycle 1

...

1.05 ms

Value
19

Value
20

1 averaged measured value

1.05 ms

Value
1

Value
2

Value
3

Cycle 2

...

1.05 ms

Value
19

Value
20

1 averaged measured value

Figure 6-5

50 Hz interference suppression

CPU 31xC and CPU 31x, Technical data
Manual, Edition 08/2004, A5E00105475-05

6-37

Technical data of CPU 31xC
6.6 Technical data of the integrated I/O

Example of a 60-Hz parasitic frequency suppression (integration time corresponds to 16.7 ms)

1.05 ms

Value
1

Value
2

Value
3

Cycle 1

...

1.05 ms

Value
16

Value
17

1 averaged measured value

1.05 ms

Value
1

Value
2

Value
3

Cycle 2

...

1.05 ms

Value
16

Value
17

1 averaged measured value

Figure 6-6

60 Hz interference suppression

Note
If the interference frequency is not 50/60 Hz or a multiple thereof, the input signal must be
filtered externally.
In this case, 400 Hz frequency suppression must be configured for the respective input. This
is equivalent to a "Deactivation" of the software filter.

Inputs not connected

The three inputs of a current/voltage analog output channel that is not connected should be
bypasses and connected to MANA (pin 20 of the front connector). This ensures maximum
interference resistance for these analog inputs.

Outputs not connected

In order to disconnect unused analog outputs from power, you must disable and leave them
open during parameter assignment with STEP 7.

Reference

6-38

Details (visualization and processing of analog values, for example) are found in chapter 4 of
the Module Data Reference Manual.
CPU 31xC and CPU 31x, Technical data
Manual, Edition 08/2004, A5E00105475-05

Technical data of CPU 31xC
6.6 Technical data of the integrated I/O

6.6.3

Configuration

Introduction
You configure the integrated I/O of CPU 31xC with STEP 7. Always make these settings
when the CPU is in STOP. The generated parameters are downloaded from the PG to the
S7-300 and written to CPU memory .
You can also choose to change the parameters at SFC 55 in the user program (see the
Reference Manual System and Standard Functions). Refer to the structure of record 1 for
the respective parameters.

Parameters of standard DI
The table below gives you an overview of the parameters for standard digital inputs.
Table 6-7

Parameters of standard DI

Parameters

Value range

Default

Range of efficiency

Input delay (ms)

0,1/0,5/3/15

Channel group

The table below gives you an overview of the parameters when using digital inputs as
interrupt inputs.
Table 6-8

Parameters of the interrupt inputs

Parameters

Value range

Default

Range of efficiency

Interrupt input

Disabled /
positive edge

disabled

digital input

Interrupt input

Disabled/
negative edge

disabled

digital input

CPU 31xC and CPU 31x, Technical data
Manual, Edition 08/2004, A5E00105475-05

6-39

Technical data of CPU 31xC
6.6 Technical data of the integrated I/O

Byte 0

Bit-Nr.

Interrupt input DI +0.0
Interrupt input DI +0.1
Interrupt input DI +0.7

Byte 1

Bit-Nr.

Interrupt input DI +1.0
Interrupt input DI +1.1
Interrupt input DI +1.7

Byte 2

Bit-Nr.

Interrupt input DI +2.0
Interrupt input DI +2.1
Interrupt input DI +2.7
0: deactivated
1: rising edge
Default setting:

Byte 3 reserved
Byte 4

Bit-Nr.

Interrupt input DI +0.0
Interrupt input DI +0.1
Interrupt input

Byte 5

Bit-Nr.

Interrupt input DI +1.0
Interrupt input DI +1.1
Interrupt input DI +1.7

Byte 6

Bit-Nr.

Interrupt input DI +2.0
Interrupt input DI +2.1
Interrupt input DI +2.7
0:
deactivated
1:
rising edge
Default setting:

Byte 7 reserved
Byte 8

Bit-Nr.

Input delay DI +0.0 to DI +0.3
Input delay DI +0.4 to DI +0.7
Input delay DI +1.0 to DI +1.3
Input delay DI +1.4 to DI +1.7

Byte 9

reserved

Bit-Nr.

Input delay DI +2.0 to DI +2.3
Input delay DI +2.4 to DI +2.7

00B:
01B:
10B:
11B :

3 ms
0,1 ms
0,5 ms
15 ms

Default setting:

Figure 6-7

6-40

00B

Structure of record 1 for standard DI and interrupt inputs (length of 10 bytes)

CPU 31xC and CPU 31x, Technical data
Manual, Edition 08/2004, A5E00105475-05

Technical data of CPU 31xC
6.6 Technical data of the integrated I/O

Parameters of standard DO
There are no parameters for standard digital outputs.

Parameters of standard AI
The table below gives you an overview of the parameters for standard analog inputs.
Table 6-9

Parameters of standard AI

Parameters

Value range

Default

Range of efficiency

Integration time (ms)

2,5/16,6/20

Channel

Interference suppression
(Hz)

400/60/50

Channel

Disabled/
+/- 20 mA/
0 ... 20 mA/
4 ... 20 mA/
+/- 10 V/
0 ... 10 V

+/- 10 V

Channel

Disabled/
V voltage/
I current

U voltage

Channel

Celsius/Fahrenheit/
Kelvin

Celsius

Channel

(channel 4)
Measurement range
(Pt 100 input; channel 4)

Disabled/
Pt 100/600 Ω

600 Ω

Channel

Type of measurement
(Pt 100 input; channel 4)

Disabled/
resistor/
thermocouple

Resistance

Channel

(channel 0 to 3)
Measurement range
(channel 0 to 3)

Type of measurement
(channel 0 to 3)
Unit of measurement

Reference
See also Chapter 4.3 in the Module Data Reference Manual.

CPU 31xC and CPU 31x, Technical data
Manual, Edition 08/2004, A5E00105475-05

6-41

Technical data of CPU 31xC
6.6 Technical data of the integrated I/O

Parameters of standard AO
The table below gives you an overview of standard analog output parameters (see also
Chapter 4.3 in the Module Data Reference Manual).
Table 6-10

Parameters of standard AO

Parameters

Value range

Default

Range of efficiency

Output range

Disabled/
+/- 20 mA/
0 ... 20 mA/
4 ... 20 mA/
+/- 10 V/
0 ... 10 V

+/- 10 V

Channel

Disabled/
V voltage/
I current

U voltage

Channel

(channel 0 to 1)

Type of output
(channel 0 to 1)

6-42

CPU 31xC and CPU 31x, Technical data
Manual, Edition 08/2004, A5E00105475-05

Technical data of CPU 31xC
6.6 Technical data of the integrated I/O

%\WH

%LW1U

reserved

%\WH

%LW1U

Parasitic frequency suppression integration time of channel AI 0
Parasitic frequency suppression integration time of channel AI 1
Parasitic frequency suppression integration time of channel AI 2
Parasitic frequency suppression integration time of channel AI 3
%
PV +]
% PV +]
% PV +]
%
Default setting:
0 Bit no.

%\WH
%\WH

Unit of measure

% Celsius
% Fahrenheit
% Kelvin
Default setting:
%

%LW1U

Measuring range of channel AI 0 (settings see byte 6)
Measurement type of channel AI 0 (settings see byte 6)

%\WH

%LW1U

Measuring range of channel AI 1 (settings see byte 6)
Measurement type of channel AI 1 (settings see byte 6)

%\WH

%LW1U

Measuring range of channel AI 2 (settings see byte 6)
Measurement type of channel AI 2 (settings see byte 6)

%\WH

%LW1U

Measuring range of channel AI 3
deactivated
+
Measurement type of channel AI 3 + ಹ P$
+ ಹ P$
+ deactivated
+ P$
+ V voltage
+ ಹ 9

I
current
+
+ 9
+ I current
Default setting:
+
+
Default setting:

%\WH

%LW1U

Measuring range of channel AI 3
+
deactivated
Measurement type of channel AI 4 + 2KP
+ 3W
+ deactivated
Default setting:
+
+ resistance

thermal
resistance
+
+
Default setting:

%\WHELV

CPU 31xC and CPU 31x, Technical data
Manual, Edition 08/2004, A5E00105475-05

reserved

6-43

Technical data of CPU 31xC
6.6 Technical data of the integrated I/O

%\WH

%LW1U

Output range of channel AO 0
(setting see byte 12)
Output range of channel AO 0
(setting see byte 12)

%\WH

%LW1U

Output range of channel AO 1
0H:
deactivated
2H:
0 … 20 mA
3H:
4 … 20 mA
4H:
+/- 20 mA
0 … 10 V
8H:
+/- 10 V
9H:
9H
Default setting:
Output range of channel AO 1
0H:
deactivated
1H:
V voltage
I current
3H:
Default setting:
9H

Figure 6-8

Structure of record 1 for standard AI/AO (length of 13 bytes)

Parameter for technological functions
The parameters for the respective function are found in the Manual Technological Functions.

6-44

CPU 31xC and CPU 31x, Technical data
Manual, Edition 08/2004, A5E00105475-05

Technical data of CPU 31xC
6.6 Technical data of the integrated I/O

6.6.4

Interrupts

Interrupt inputs
All digital inputs of the on-board I/O of CPUs 31xC can be used as interrupt inputs.
You can specify interrupt behavior for each individual input in your parameter declaration.
Options are:
• no interrupt
• Interrupt at the positive edge
• Interrupt at the negative edge
• Interrupt at the positive and negative edge

Note
Every channel will hold one event if the rate of incoming interrupts exceeds the handling
capacity of OB40. Further events (interrupts) will be lost, without diagnostics or explicit
message.

Start information for OB40
The table below shows the relevant temporary variables (TEMP) of OB40 for the interrupt
inputs of 31xC CPUs. A description of process interrupt OB 40 is found in the Reference
Manual System and Standard Functions.
Table 6-11

Start information for OB40, relating to the interrupt inputs of the integrated I/O

Byte

Variables

Data type

6/7

OB40_MDL_ADDR

WORD

B#16#7C

Address of the interrupttriggering module (here: default
addresses of the digital inputs)

8 on

OB40_POINT_ADDR

DWORD

see the figure
below

Displaying the interrupttriggering integrated inputs

CPU 31xC and CPU 31x, Technical data
Manual, Edition 08/2004, A5E00105475-05

Description

6-45

Technical data of CPU 31xC
6.6 Technical data of the integrated I/O

31 30 29 28 27 26 25 24 23 …

16 15

…

8 7 6 5 4 3 2 1

Bit no.

reserved

PRAL from E124.0
PRAL from E124.7
PRAL from E125.0
PRAL from E125.7
PRAL from E126.0
PRAL from E126.7

PRAL: process interrupt
Inputs are designated with default addresses.

Figure 6-9

Displaying the statuses of CPU 31xC interrupt inputs

PRAL: process interrupt
The inputs are assigned default addresses.

6.6.5

Diagnostics

Standard I/O
Diagnostic data is not available for integrated I/O which is operated as standard I/O (see also
the Reference Manual Module Data).

Technological functions
Diagnostics options for the respective technological function are found in the Manual
Technological Functions.

6.6.6

Digital inputs

Introduction
This section provides the specifications for the digital inputs of CPUs 31xC.
The table includes the following CPUs:
• under CPU 313C-2, the CPU 313C-2 DP and CPU 313C-2 PtP
• under CPU 314C-2, the CPU 314C-2 DP and CPU 314C-2 PtP

6-46

CPU 31xC and CPU 31x, Technical data
Manual, Edition 08/2004, A5E00105475-05

Technical data of CPU 31xC
6.6 Technical data of the integrated I/O

Technical data
Table 6-12

Technical data of digital inputs

Technical data
CPU 312C

CPU 313C

CPU 313C-2

CPU 314C-2

Module-specific data

CPU 312C

CPU 313C

CPU 313C-2

CPU 314C-2

Number of inputs

•

Number of these inputs which can be used
for technological functions

Cable length
•

Unshielded

•

Shielded

For standard DI: Max. 600 m
For technological functions: No
For standard DI: Max. 1000 m
For technological function at max. counting frequency
100 m

100 m

50 m

Voltage, currents, potentials

CPU 312C

CPU 313C

CPU 313C-2

CPU 314C-2

Rated load voltage L+

24 VDC

•

Polarity reversal protection

Yes

Number of inputs which can be controlled
simultaneously
•

•

Horizontal assembly
– up to 104 °F
– up to 60 °C
Vertical assembly
– up to 104 °F

Electrical isolation
•

Between channels and the backplane bus

Yes

•

Between the channels

Permitted potential difference
•

Between different circuits

Insulation test voltage

75 VDC / 60 VAC
500 VDC

Current consumption
On load voltage L+ (no-load)

–

Max. 70 mA

Status, interrupts, diagnostics

CPU 312C

CPU 313C

CPU 313C-2

CPU 314C-2

Status display

green LED per channel

Interrupts

•
•

Yes, if the corresponding channel is configured as interrupt input
For using technological functions, please refer to the Technological
Functions Manual.

Diagnostics functions

•
•

no diagnostics when operated as standard I/O
For using technological functions, please refer to the Technological
Functions Manual.

•

CPU 31xC and CPU 31x, Technical data
Manual, Edition 08/2004, A5E00105475-05

6-47

Technical data of CPU 31xC
6.6 Technical data of the integrated I/O
Technical data
Data for the selection of an encoder for
standard DI

CPU 312C

CPU 313C

CPU 313C-2

CPU 314C-2

CPU 312C

CPU 313C

CPU 313C-2

CPU 314C-2

Input voltage
•

Rated value

24 VDC

•

For signal "1"

15 V to 30 V

•

For signal "0"

-3 V to 5 V

Input current
•

For signal "1"

Typically 9 mA

Delay of standard inputs
•

Configurable

Yes (0.1 / 0.5 / 3 / 15 ms)
You can reconfigure the input delay of the standard inputs during program
runtime. Please note that your newly set filter time may only take effect
after the previously set filter time has expired.

•

Rated value

3 ms

For using technological functions:

48 μs

16 μs

8 μs

"Minimum pulse width/ minimum pause
between pulses at maximum counting
frequency"
Input characteristics curve

to IEC 1131, type 1

Connection of 2wire BEROs

Possible

•

Permitted quiescent current

6.6.7

Max. 1,5 mA

Digital outputs

Introduction
This chapter contains the specifications for the digital outputs of CPUs 31xC.
The table includes the following CPUs:
• under CPU 313C-2, the CPU 313C-2 DP and CPU 313C-2 PtP
• under CPU 314C-2, the CPU 314C-2 DP and CPU 314C-2 PtP

Fast digital outputs
Technological functions use fast digital outputs.

6-48

CPU 31xC and CPU 31x, Technical data
Manual, Edition 08/2004, A5E00105475-05

Technical data of CPU 31xC
6.6 Technical data of the integrated I/O

Technical data
Table 6-13

Technical data of digital outputs

Technical data
CPU 312C

CPU 313C

CPU 313C-2

CPU 314C-2

Module-specific data

CPU 312C

CPU 313C

CPU 313C-2

CPU 314C-2

Number of outputs

•

Of those are fast outputs

Caution:
You cannot connect the high-speed outputs of your CPU in parallel.
Cable length
•

Unshielded

•

Shielded

Max. 600 m
Max. 1000 m

Voltage, currents, potentials

CPU 312C

Rated load voltage L+

24 VDC

•

Polarity reversal protection

CPU 313C

CPU 313C-2

CPU 314C-2

Total current of outputs (per group)
•

•

Horizontal assembly
– up to 104 °F
– up to 60 °C

Max. 2.0 A

Max. 3,0 A

Max. 1,5 A

Max. 2.0 A

Vertical assembly
– up to 104 °F

Max. 1,5 A

Max. 2.0 A

Electrical isolation
•

Between channels and the backplane bus

Yes

•

Between the channels
– In groups of

Yes

–

Permitted potential difference
•

Between different circuits

Insulation test voltage

75 VDC / 60 VAC
500 VDC

Current consumption
with load voltage L+

Max. 50 mA

Max. 100 mA

Status, interrupts, diagnostics

CPU 312C

CPU 313C

CPU 313C-2

CPU 314C-2

Status display

green LED per channel

Interrupts

•
•

no interrupts when operated as standard I/O
For using technological functions, please refer to the Technological
Functions Manual.

Diagnostics functions

•
•

no diagnostics when operated as standard I/O
For using technological functions, please refer to the Technological
Functions Manual.

•

CPU 31xC and CPU 31x, Technical data
Manual, Edition 08/2004, A5E00105475-05

6-49

Technical data of CPU 31xC
6.6 Technical data of the integrated I/O
Technical data
Data for the selection of an actuator for
standard DI

CPU 312C

CPU 313C

CPU 313C-2

CPU 314C-2

CPU 312C

CPU 313C

CPU 313C-2

CPU 314C-2

Output voltage
•

For signal "1"

Min. L+ (-0.8 V)

Output current
•

•

For signal "1"
– Rated value
– Permitted range

0,5 A

For signal "0" (residual current)

Max. 0.5 mA

5 mA to 600 mA

Load impedance range

48 Ω to 4 kΩ

Lamp load

Max. 5 W

Parallel connection of 2 outputs
•

for redundant load control

Possible

•

for performance increase

Not possible

Controlling of digital inputs

Possible

Switching frequency
•

under resistive load

Max. 100 Hz

•

For inductive load to IEC 947-5, DC13

Max. 0.5 Hz

•

under lamp load

Max. 100 Hz

•

fast outputs under resistive load

Max. 2.5 kHz

Inductive breaking voltage limited internally to

Typically (L+) - 48 V

Short-circuit protection of the output

Yes, electronic

•

Response threshold

6-50

Typically 1 A

CPU 31xC and CPU 31x, Technical data
Manual, Edition 08/2004, A5E00105475-05

Technical data of CPU 31xC
6.6 Technical data of the integrated I/O

6.6.8

Analog inputs

Introduction
This chapter contains the specifications for analog outputs of CPUs 31xC.
The table includes the following CPUs:
• CPU 313C
• CPU 314C-2 DP
• CPU 314C-2 PtP

Technical data
Table 6-14

Technical data of analog inputs

Technical data
Module-specific data
Number of inputs

4 channels with current/voltage input
1 channel with resistance input

Cable length
•

Shielded

Max. 100 m

Voltage, currents, potentials
Resistance input
•

No-load voltage

Typically 2.5 V

•

Measurement current

Typically 1.8 mA to 3.3 mA

Electrical isolation
•

Between channels and the backplane bus

Yes

•

Between the channels

Permitted potential difference
•

Between inputs (AIC) and MANA (UCM)

8.0 VDC

•

between MANA and Minternal (UISO)

75 VDC / 60 VAC

Insulation test voltage

600 VDC

Analog value generation
Measurement principle

Actual value encoding (successive
approximation)

Integration time/conversion time/resolution (per channel)
•

Configurable

Yes

•

Integration time in ms

2,5 / 16,6 / 20

•

Permitted input frequency

Max. 400 Hz

•

Resolution (including overdrive)

11 bits + signed bit

•

Suppression of interference frequency f1

400 / 60 / 50 Hz

CPU 31xC and CPU 31x, Technical data
Manual, Edition 08/2004, A5E00105475-05

6-51

Technical data of CPU 31xC
6.6 Technical data of the integrated I/O
Technical data
Time constant of the input filter

0,38 ms

Basic processing time

1 ms

Interference suppression, error limits
Interference voltage suppression for f = nx (f1 ± 1 %), (f1 = interference
frequency), n = 1, 2
•

Commonmode interference (UCM < 1.0 V)

> 40 dB

•

Feedback interference (peak value of the interference < rated value of
the input range)

> 30 dB

Crosstalk between the inputs

> 60 dB

Operational error limits (across the temperature range, in relation to input
range)
•

Voltage/current

<1%

•

Resistance

<5%

Basic error limit (operational limit at 25 °C, in relation to input range)
•

Voltage/current

•

Resistance

< 0,7 %
<3%

Temperature error (in relation to input range)

± 0,006 %/K

Linearity error (referred to input range)

± 0,06 %

Repeat accuracy (in transient state at 25 °C, in relation to input range)

± 0,06 %

Status, interrupts, diagnostics
Interrupts

•

no interrupts when operated as standard
I/O

Diagnostics functions

•

no diagnostics when operated as
standard I/O
For using technological functions, please
refer to the Technological Functions
Manual.

•

Encoder selection data
Input ranges (rated value)/input resistance
•

Voltage

± 10 V/100 kΩ
0 V to 10 V/100 kΩ

•

Current

± 20 mA/50 Ω
0 mA to 20 mA/50 Ω
4 mA to 20 mA/50 Ω

•

Resistance

0 Ω to 600 Ω/10 MΩ

•

Resistance thermometer

Pt 100/10 MΩ

Permitted continuous input voltage (destruction limit)
•

For voltage inputs

Max. 30 V

•

For current inputs

Max. 2.5 V

Permitted continuous input current (destruction limit)
•

For voltage inputs

Max. 0,5 mA;

•

For current inputs

Max. 50 mA;

6-52

CPU 31xC and CPU 31x, Technical data
Manual, Edition 08/2004, A5E00105475-05

Technical data of CPU 31xC
6.6 Technical data of the integrated I/O
Technical data
Connection of signal generators
•

For voltage measurement

Possible

•

For current measurement
– as 2-wire measuring transducer
– as 4-wire measuring transducer

Possible, with external power supply

•

for measuring resistance
– with 2-wire connection
–
–

with 3-wire connection
with 4-wire connection

Linearization of the characteristics trend
•

For resistance thermometers

Possible
Possible, without compensation of
cable resistance
Not possible
Not possible
By software
Pt 100

Temperature compensation

Technical unit for temperature measurement

Degrees Celsius/Fahrenheit/Kelvin

6.6.9

Analog outputs

Introduction
This chapter contains the specifications for digital outputs of CPUs 31xC.
The table includes the following CPUs:
• CPU 313C
• CPU 314C-2 DP
• CPU 314C-2 PtP

Technical data
Table 6-15

Technical data of analog outputs

Technical data
Module-specific data
Number of outputs

Cable length
•

Shielded

Max. 200 m

Voltage, currents, potentials
Rated load voltage L+
•

Polarity reversal protection

24 VDC
Yes

Electrical isolation
•

Between channels and the backplane bus

Yes

•

Between the channels

CPU 31xC and CPU 31x, Technical data
Manual, Edition 08/2004, A5E00105475-05

6-53

Technical data of CPU 31xC
6.6 Technical data of the integrated I/O
Technical data
Permitted potential difference
•

between MANA and Minternal (UISO)

Insulation test voltage

75 VDC / 60 VAC
600 VDC

Analog value generation
Resolution (including overdrive)

11 bits + signed bit

Conversion time (per channel)

1 ms

Settling time
•

with resistive load

0,6 ms

•

With capacitive load

1,0 ms

•

With inductive load

0.5 ms

Interference suppression, error limits
Crosstalk between the outputs

> 60 dB

Operational error limits (across the temperature range, in relation to output
range)
•

Voltage/current

±1%

Basic error limit (operational limit at 25 °C, in relation to output range)
•

Voltage/current

± 0,7 %

Temperature error (in relation to output range)

± 0.01 %/K

Linearity error (in relation to output range)

± 0,15 %

Repeat accuracy (in transient state at 25 °C, in relation to output range)

± 0,06 %

Output ripple; bandwidth 0 to 50 kHz (in relation to output range)

± 0,1 %

Status, interrupts, diagnostics
Interrupts

•
•

Diagnostics functions

•
•

no interrupts when operated as standard
I/O
For using technological functions, please
refer to the Technological Functions
Manual.
no diagnostics when operated as
standard I/O
For using technological functions, please
refer to the Technological Functions
Manual.

Actuator selection data
Output range (rated values)
•

Voltage

± 10 V
0 V to 10 V

•

Current

± 20 mA
0 mA to 20 mA
4 mA to 20 mA

Load resistance (within output rating)
•

For voltage outputs
– Capacitive load

min. 1 kΩ

•

For current outputs
– Inductive load

max. 300 Ω

6-54

max. 0.1 μF
0.1 mH

CPU 31xC and CPU 31x, Technical data
Manual, Edition 08/2004, A5E00105475-05

Technical data of CPU 31xC
6.6 Technical data of the integrated I/O
Technical data
Voltage output
•

Short-circuit protection

Yes

•

Short-circuit current

Typically 55 mA

Current output
•

No-load voltage

Typically 17 V

Destruction limit for externally applied voltages/currents
•

Voltage measured between the outputs and MANA

Max. 16 V

•

Current

Max. 50 mA;

Connection of actuators
•

For voltage outputs
– wire connection
–

•

wire connection (test lead)

For current outputs
– wire connection

CPU 31xC and CPU 31x, Technical data
Manual, Edition 08/2004, A5E00105475-05

Possible, without compensation of
cable resistance
Not possible
Possible

6-55

Technical data of CPU 31xC
6.6 Technical data of the integrated I/O

6-56

CPU 31xC and CPU 31x, Technical data
Manual, Edition 08/2004, A5E00105475-05

Technical data of CPU 31x
7.1

General technical data

7.1.1

Dimensions of CPU 31x
Each CPU features the same height and depth, only the width dimensions differ.
• Height: 125 mm
• Depth: 115 mm, or 180 mm with opened front cover.

115

125

Figure 7-1

Dimensions of CPU 31x

Width of CPU
CPU

Width

CPU 312

40 mm

CPU 314

40 mm

CPU 315-2 DP

40 mm

CPU 315-2 PN/DP

80 mm

CPU 317

80 mm

CPU 31xC and CPU 31x, Technical data
Manual, Edition 08/2004, A5E00105475-05

7-1

Technical data of CPU 31x
7.1 General technical data

7.1.2

Technical data of the Micro Memory Card (MMC)

Plug-in SIMATIC Micro Memory Cards
The following memory modules are available:
Table 7-1

Available MMCs

Type

Order number

Required for a firmware update via MMC

MMC 64k

6ES7 953-8LFxx-0AA0

–

MMC 128k

6ES7 953-8LGxx-0AA0

–

MMC 512k

6ES7 953-8LJxx-0AA0

–

MMC 2M

6ES7 953-8LLxx-0AA0

Minimum requirement for CPUs without DP interface

MMC 4M

6ES7 953-8LMxx-0AA0

Minimum requirement for CPUs with DP interface

MMC 8M 1

6ES7 953-8LPxx-0AA0

–

This MMC cannot be used together with CPU 312C or CPU 312.

Maximum number of blocks that can be loaded

64 KB

768

128 KB

1024

512 KB

Here the maximum number of blocks that can be loaded for the
specific CPU is less than the number of blocks that can be stored on
the MMC.

2 MB
4 MB
8 MB

7-2

Maximum number of loadable blocks on the MMC

Refer to the corresponding specifications of a specific CPU to
determine the maximum number of blocks that can be loaded.

CPU 31xC and CPU 31x, Technical data
Manual, Edition 08/2004, A5E00105475-05

Technical data of CPU 31x
7.2 CPU 312

7.2

CPU 312

Technical data
Table 7-3

Technical data for the CPU 312

Technical data
CPU and version
Order number

6ES7312-1AD10-0AB0

•

Hardware version

•

Firmware version

V2.0.0

•

Associated programming package

STEP 7 as of V 5.1 + SP 4

Memory
RAM
•

Integrated

16 KB

•

Expandable

Load memory

Plugged in with MMC (max. 4 MB)

Data storage life on the MMC
(following final programming)

At least 10 years

Buffering

Guaranteed by MMC (maintenance-free)

Execution times
Processing times of
•

Bit operations

Min. 0.2 μs

•

Word instructions

Min. 0.4 μs

•

Fixed-point arithmetic

Min. 5 μs

•

Floating-point arithmetic

Min. 6 μs

Timers/counters and their retentivity
S7 counters

128

•

Retentive memory

Configurable

•

Default

from C0 to C7

•

Counting range

0 to 999

IEC Counters

Yes

•

Type

SFB

•

Number

unlimited (limited only by RAM size)

S7 timers

128

•

Retentive memory

Configurable

•

Default

Not retentive

•

Timer range

10 ms to 9990 s

IEC Timers

Yes

•

Type

SFB

•

Number

unlimited (limited only by RAM size)

CPU 31xC and CPU 31x, Technical data
Manual, Edition 08/2004, A5E00105475-05

7-3

Technical data of CPU 31x
7.2 CPU 312
Technical data
Data areas and their retentivity
Flag bits

128 bytes

•

Retentive memory

Yes

•

Default retentivity

MB0 to MB15

Clock flag bits

8 (1 byte per flag bit)

Data blocks

511
(DB 1 to DB 511)

•

Length

Local data per priority class

16 KB
max. 256 bytes

Blocks
Total

1024 (DBs, FCs, FBs)
The maximum number of blocks that can be
loaded may be reduced if you are using another
MMC.

OBs
•

Length

See the Instruction List
max. 16 KB

Nesting depth
•

Per priority class

•

additional within an error OB

FBs

8
4
Max. 512
(FB 0 to FB 511)

•

Length

FCs

max. 16 KB
Max. 512
(FC 0 to FC 511

•

Length

max. 16 KB

Address areas (I/O)
Total I/O address area

1024 bytes /1024 bytes
(can be freely addressed)

I/O process image

128 bytes/128 bytes

Digital channels

Max. 256

of those local

Max. 256

Analog channels

Max. 64

of those local

Max. 64

Assembly
Racks

Max. 1

Modules per rack

Max. 8

Number of DP masters

7-4

•

Integrated

None

•

Via CP

CPU 31xC and CPU 31x, Technical data
Manual, Edition 08/2004, A5E00105475-05

Technical data of CPU 31x
7.2 CPU 312
Technical data
Number of function modules and communication
processors you can operate
•

Max. 8

•

CP (PtP)

Max. 8

•

CP (LAN)

Max. 4

Time-of-day
Real-time clock

Yes (SW clock)

•

Buffered

•

Accuracy

Deviation per day < 15 s

•

Behavior of the realtime clock after POWER
ON

The clock keeps running, continuing at the timeof-day it had when power was switched off.

Operating hours counter

•

Number

•

Value range

2 31
(if SFC 101 is used)

•

Granularity

1 hour

•

Retentive

Yes; must be manually restarted after every
restart

Clock synchronization

Yes

•

In the PLC

Master

•

On MPI

Master/slave

S7 signaling functions
Number of stations that can be logged on for
signaling functions

Process diagnostics messages

Yes

•

Simultaneously enabled interrupt S blocks

(depends on the number of connections
configured for PG / OP and S7 basic
communication)
Max. 20

Testing and commissioning functions
Status/control variables

Yes

•

Variables

Inputs, outputs, memory bits, DBs, timers,
counters

•

Number of variables
– Of those as status variable
– Of those as control variable

Forcing

30
14
Yes

•

Variables

Inputs, outputs

•

Number of variables

Max. 10

Block status

Yes

Single step

Yes

Breakpoints

Diagnostic buffer

Yes

•

Number of entries (not configurable)

CPU 31xC and CPU 31x, Technical data
Manual, Edition 08/2004, A5E00105475-05

Max. 100

7-5

Technical data of CPU 31x
7.2 CPU 312
Technical data
Communication functions
PG/OP communication

Yes

Global data communication

Yes

•

Number of GD circuits

•

Number of GD packets
– Sending stations
– Receiving stations

Max. 4

Length of GD packets
– Consistent data

max. 22 bytes

•

S7 basic communication
•

User data per request
– Consistent data

Max. 4
Max. 4
22 bytes
Yes
max. 76 bytes
76 bytes (for X_SEND or X_RCV)
64 bytes (for X_PUT or X_GET as the server)

S7 communication
•

As server

Yes

•

User data per request
– Consistent data

Max. 180 bytes (with PUT/GET)

S5-compatible communication

Yes (via CP and loadable FCs)

Number of connections

Max. 6

64 bytes

can be used for
•

•

PG communication
– Reserved (default)
– Configurable

Max. 5

OP communication
– Reserved (default)
– Configurable

Max. 5

S7-based communication
– Reserved (default)
– Configurable

Max. 2

Routing

1
from 1 to 5
1
from 1 to 5
2
from 0 to 2
No

Interfaces
1st interface
Type of interface

Integrated RS485 interface

Physics

RS 485

electrically isolated

Interface power supply
(15 to 30 VDC)

max. 200 mA

Functionality

7-6

•

MPI

Yes

•

PROFIBUS DP

•

Point-to-point communication

CPU 31xC and CPU 31x, Technical data
Manual, Edition 08/2004, A5E00105475-05

Technical data of CPU 31x
7.2 CPU 312
Technical data
MPI
Services
•

PG/OP communication

Yes

•

Routing

•

Global data communication

Yes

•

S7 basic communication

Yes

•

S7 communication
– As server
– As client

Yes
No

•

Transmission rates

187.5 kbps

Programming
Programming language

LAD/FBD/STL

Available instructions

See the Instruction List

Nesting levels

System functions (SFCs)

See the Instruction List

System function blocks (SFBs)

See the Instruction List

User program security

Yes

Dimensions
Mounting dimensions W x H x D (mm)

40 x 125 x 130

Weight

270 g

Voltages and currents
Power supply (rated value)
•

Permitted range

24 VDC
20.4 V to 28.8 V

Current consumption (no-load operation)

Typically 60 mA

Inrush current

Typically 2.5 A

Power consumption (nominal value)

0,6 A

I2t

0.5 A2s

External fusing of power supply lines
(recommended)

min. 2 A

Power loss

Typically 2,5 W

CPU 31xC and CPU 31x, Technical data
Manual, Edition 08/2004, A5E00105475-05

7-7

Technical data of CPU 31x
7.3 CPU 314

7.3

CPU 314

Technical data for the CPU 314
Table 7-4

Technical data for the CPU 314

Technical data
CPU and version
Order number

6ES7314-1AF10-0AB0

•

Hardware version

•

Firmware version

V 2.0.0

•

Associated programming package

STEP 7 as of V 5.1 + SP 4

Memory
RAM
•

Integrated

48 KB

•

Expandable

Load memory

Plugged in with MMC (max. 8 MB)

Data storage life on the MMC
(following final programming)

At least 10 years

Buffering

Guaranteed by MMC (maintenance-free)

Execution times
Processing times of
•

Bit operations

Min. 0.1 μs

•

Word instructions

Min. 0.2 μs

•

Fixed-point arithmetic

Min. 2.0 μs

•

Floating-point arithmetic

Min. 6 μs

Timers/counters and their retentivity
S7 counters
Retentive memory

Configurable

•

Default

from C0 to C7

•

Counting range

0 to 999

IEC Counters

Yes

•

Type

SFB

•

Number

unlimited (limited only by RAM size)

S7 timers

7-8

256

•

256

•

Retentive memory

Configurable

•

Default

Not retentive

•

Timer range

10 ms to 9990 s

IEC Timers

Yes

•

Type

SFB

•

Number

unlimited (limited only by RAM size)

CPU 31xC and CPU 31x, Technical data
Manual, Edition 08/2004, A5E00105475-05

Technical data of CPU 31x
7.3 CPU 314
Technical data
Data areas and their retentivity
Flag bits

256 bytes

•

Retentive memory

Yes

•

Default retentivity

MB0 to MB15

Clock flag bits

8 (1 byte per flag bit)

Data blocks
•

Number

•

Length

511
(DB 1 to DB 511)

Local data per priority class

16 KB
Max. 510

Blocks
Total

1024 (DBs, FCs, FBs)
The maximum number of blocks that can be
loaded may be reduced if you are using another
MMC.

OBs
•

Length

See the Instruction List
16 KB

Nesting depth
•

Per priority class

•

additional within an error OB

FBs
•

Number

See the Instruction List
512
(FB 0 to FB 511)

•

Length

FCs
•

Number

16 KB
See the Instruction List
512
(FC 0 to FC 511)

•

Length

16 KB

Address areas (I/O)
Total I/O address area

Max. 1024 bytes/1024 bytes (can be freely
addressed)

I/O process image

128 bytes/128 bytes

Digital channels

Max. 1024

of those local

Max. 1024

Analog channels

Max. 256

of those local

Max. 256

Assembly
Racks

Max. 4

Modules per rack

Number of DP masters
•

Integrated

None

•

via CP

Max. 1

CPU 31xC and CPU 31x, Technical data
Manual, Edition 08/2004, A5E00105475-05

7-9

Technical data of CPU 31x
7.3 CPU 314
Technical data
Number of function modules and communication
processors you can operate
•

Max. 8

•

CP (PtP)

Max. 8

•

CP (LAN)

Max. 10

Time-of-day
Real-time clock

Yes (HW clock)

•

Buffered

Yes

•

Buffered period

Typically 6 weeks (at an ambient temperature of
104 °F)

•

Behavior of the clock on expiration of the
buffered period

The clock keeps running, continuing at the timeof-day it had when power was switched off.

•

Accuracy

Deviation per day: < 10 s

Operating hours counter

•

Number

•

Value range

2 31 hours

•

Granularity

1 hour

•

Retentive

yes; must be manually restarted after every
restart

(if SFC 101 is used)

Clock synchronization

Yes

•

In the PLC

Master

•

On MPI

Master/slave

S7 signaling functions
Number of stations that can log in for signaling
functions (e.g. OS)

Process diagnostics messages

Yes

•

Simultaneously enabled interrupt S blocks

(depends on the number of connections
configured for PG / OP and S7 basic
communication)
Max. 40

Testing and commissioning functions
Status/control variables
•

Variables

Inputs, outputs, memory bits, DBs, timers,
counters

•

Number of variables
– Of those as status variable
– Of those as control variable

Forcing

7-10

Yes

30
14
Yes

•

Variables

Inputs/Outputs

•

Number of variables

Max. 10

Block status

Yes

Single step

Yes

Breakpoints

Diagnostic buffer

Yes

CPU 31xC and CPU 31x, Technical data
Manual, Edition 08/2004, A5E00105475-05

Technical data of CPU 31x
7.3 CPU 314
Technical data
•

Number of entries (not configurable)

Max. 100

Communication functions
PG/OP communication

Yes

Global data communication

Yes

•

Number of GD circuits

•

Number of GD packets
– Sending stations
– Receiving stations

Max. 4

Length of GD packets
– Consistent data

max. 22 bytes

•

S7 basic communication
•

User data per request
– Consistent data

Max. 4
Max. 4
22 bytes
Yes
max. 76 bytes
76 bytes (for X_SEND or X_RCV)
64 bytes (for X_PUT or X_GET as the server)

S7 communication

Yes

•

As server

Yes

•

as client

Yes (via CP and loadable FBs)

•

User data per request
– Consistent data

Max. 180 (for PUT/GET)
64 bytes

S5-compatible communication

Yes (via CP and loadable FCs)

Number of connections

can be used for
•

•

PG communication
– Reserved (default)
– Configurable

Max. 11

OP communication
– Reserved (default)
– Configurable

Max. 11

S7-based communication
– Reserved (default)
– Configurable

Max. 8

Routing

1
1 to 11
1
1 to 11
8
0 to 8
No

Interfaces
1st interface
Type of interface

Integrated RS485 interface

Physics

RS 485

electrically isolated

Interface power supply
(15 to 30 VDC)

max. 200 mA

Functionality
•

MPI

Yes

•

PROFIBUS DP

•

Point-to-point communication

CPU 31xC and CPU 31x, Technical data
Manual, Edition 08/2004, A5E00105475-05

7-11

Technical data of CPU 31x
7.3 CPU 314
Technical data
MPI
Services
•

PG/OP communication

Yes

•

Routing

•

Global data communication

Yes

•

S7 basic communication

Yes

•

S7 communication
– As server
– As client

Yes

Transmission rates

187.5 kbps

•

Yes
No (but via CP and loadable FBs)

Programming
Programming language

LAD/FBD/STL

Available instructions

See the Instruction List

Nesting levels

System functions (SFCs)

See the Instruction List

System function blocks (SFBs)

See the Instruction List

User program security

Yes

Dimensions
Mounting dimensions W x H x D (mm)

40 x 125 x 130

Weight

280 g

Voltages and currents
Power supply (rated value)
•

7-12

Permitted range

24 VDC
20.4 V to 28.8 V

Current consumption (no-load operation)

Typically 60 mA

Inrush current

Typically 2.5 A

Power consumption (nominal value)

0,6 A

I2t

0.5 A2s

External fusing of power supply lines
(recommended)

min. 2 A

Power loss

Typically 2.5 W

CPU 31xC and CPU 31x, Technical data
Manual, Edition 08/2004, A5E00105475-05

Technical data of CPU 31x
7.4 CPU 315-2 DP

7.4

CPU 315-2 DP

Technical data
Table 7-5

Technical data for the CPU 315-2 DP

Technical data
CPU and version
Order number

6ES7315-2AG10-0AB0

•

Hardware version

•

Firmware version

V 2.0.0

•

Associated programming package

STEP 7 as of V 5.1 + SP 4

Memory
RAM
•

Integrated

128 KB

•

Expandable

Load memory

Plugged in with MMC (max. 8 MB)

Data storage life on the MMC
(following final programming)

At least 10 years

Buffering

Guaranteed by MMC (maintenance-free)

Execution times
Processing times of
•

Bit operations

Min. 0.1 μs

•

Word instructions

Min. 0.2 μs

•

Fixed-point arithmetic

Min. 2.0 μs

•

Floating-point arithmetic

Min. 6 μs

Timers/counters and their retentivity
S7 counters

256

•

Retentive memory

Configurable

•

Default

from C0 to C7

•

Counting range

0 to 999

IEC Counters

Yes

•

Type

SFB

•

Number

unlimited (limited only by RAM size)

S7 timers

256

•

Retentive memory

Configurable

•

Default

Not retentive

•

Timer range

10 ms to 9990 s

IEC Timers

Yes

•

Type

SFB

•

Number

unlimited (limited only by RAM size)

CPU 31xC and CPU 31x, Technical data
Manual, Edition 08/2004, A5E00105475-05

7-13

Technical data of CPU 31x
7.4 CPU 315-2 DP
Technical data
Data areas and their retentivity
Flag bits

2048 bytes

•

Retentive memory

Yes

•

Default retentivity

MB0 to MB15

Clock flag bits

8 (1 byte per flag bit)

Data blocks
•

Number

•

Length

1023
(DB 1 to DB 1023)

Local data capacity

16 KB
Max. 1024 bytes per task/510 per block

Blocks
Total

1024 (DBs, FCs, FBs)
The maximum number of blocks that can be
loaded may be reduced if you are using another
MMC.

OBs
•

Length

See the Instruction List
16 KB

Nesting depth
•

Per priority class

•

additional within an error OB

FBs
•

Number

See the Instruction List
2048
(FB 0 to FB 2047)

•

Length

FCs
•

Number

16 KB
See the Instruction List
2048
(FC 0 to FC 2047)

•

Length

16 KB

Address areas (I/O)
Total I/O address area

max. 2048 bytes/2048 bytes
(can be freely addressed)

Distributed

Max. 2000

I/O process image

128/128

Digital channels

Max. 16384

of those local

Max. 1024

Analog channels

Max. 1024

of those local

Max. 256

Assembly
Racks

Max. 4

Modules per rack

Number of DP masters

7-14

•

Integrated

•

via CP

CPU 31xC and CPU 31x, Technical data
Manual, Edition 08/2004, A5E00105475-05

Technical data of CPU 31x
7.4 CPU 315-2 DP
Technical data
Number of function modules and communication
processors you can operate
•

Max. 8

•

CP (PtP)

Max. 8

•

CP (LAN)

Max. 10

Time-of-day
Real-time clock

Yes (HW clock)

•

Buffered

Yes

•

Buffered period

Typically 6 weeks (at an ambient temperature of
104 °F)

•

Behavior of the clock on expiration of the
buffered period

The clock keeps running, continuing at the timeof-day it had when power was switched off.

•

Accuracy

Deviation per day: < 10 s

Operating hours counter

•

Number

•

Value range

2 31 hours

•

Granularity

1 hour

•

Retentive

yes; must be manually restarted after every
restart

(if SFC 101 is used)

Clock synchronization

Yes

•

In the PLC

Master

•

On MPI

Master/slave

S7 signaling functions
Number of stations that can log in for signaling
functions (e.g. OS)

Process diagnostics messages

Yes

•

Simultaneously enabled interrupt S blocks

(depends on the number of connections
configured for PG / OP and S7 basic
communication)
40

Testing and commissioning functions
Status/control variables

Yes

•

Variables

Inputs, outputs, memory bits, DBs, timers,
counters

•

Number of variables
– Of those as status variable
– Of those as control variable

30
30
14

Forcing
•

Variables

Inputs/Outputs

•

Number of variables

Max. 10

Block status

Yes

Single step

Yes

Breakpoints

CPU 31xC and CPU 31x, Technical data
Manual, Edition 08/2004, A5E00105475-05

7-15

Technical data of CPU 31x
7.4 CPU 315-2 DP
Technical data
Diagnostic buffer
•

Number of entries (not configurable)

Yes
Max. 100

Communication functions
PG/OP communication

Yes

Global data communication

Yes

•

Number of GD circuits

•

Number of GD packets
– Sending stations
– Receiving stations

Max. 8

Length of GD packets
– Consistent data

max. 22 bytes

•

S7 basic communication
•

User data per request
– Consistent data

Max. 8
Max. 8
22 bytes
Yes
max. 76 bytes
76 bytes (for X_SEND or X_RCV)
64 bytes (for X_PUT or X_GET as the server)

S7 communication

Yes

•

As server

Yes

•

as client

Yes (via CP and loadable FBs)

•

User data per request
– Consistent data

Max. 180 bytes (with PUT/GET)

S5-compatible communication

Yes (via CP and loadable FCs)

Number of connections

64 byte (as the server)

can be used for
•

•

PG communication
– Reserved (default)
– Configurable

Max. 15

OP communication
– Reserved (default)
– Configurable

Max. 15

S7-based communication
– Reserved (default)
– Configurable

Max. 12

Routing

1
1 to 15
1
1 to 15
12
0 to 12
Yes (max. 4)

Interfaces
1st interface

7-16

Type of interface

Integrated RS485 interface

Physics

RS 485

electrically isolated

Interface power supply
(15 to 30 VDC)

max. 200 mA

CPU 31xC and CPU 31x, Technical data
Manual, Edition 08/2004, A5E00105475-05

Technical data of CPU 31x
7.4 CPU 315-2 DP
Technical data
Functionality
•

MPI

Yes

•

PROFIBUS DP

•

Point-to-point communication

MPI
Services
•

PG/OP communication

Yes

•

Routing

Yes

•

Global data communication

Yes

•

S7 basic communication

Yes

•

S7 communication
– As server
– As client

Yes

Transmission rates

187.5 kbps

•

Yes
No (but via CP and loadable FBs)

2nd interface
Type of interface

Integrated RS485 interface

Physics

RS 485

electrically isolated

Yes

Type of interface

Integrated RS485 interface

Interface power supply (15 to 30 VDC)

max. 200 mA

Functionality
MPI

PROFIBUS DP

Yes

Point-to-point communication

DP master
Services
•

PG/OP communication

Yes

•

Routing

Yes

•

Global data communication

•

S7 basic communication

•

S7 communication

•

Constant bus cycle time

Yes

•

SYNC/FREEZE

Yes

•

DPV1

Yes

Transmission speed

Up to 12 Mbps

Number of DP slaves per station

124

Address area

max. 244 bytes

CPU 31xC and CPU 31x, Technical data
Manual, Edition 08/2004, A5E00105475-05

7-17

Technical data of CPU 31x
7.4 CPU 315-2 DP
Technical data
DP slave
Services
•

PG/OP communication

Yes

•

Routing

Yes (only if interface is active)

•

Global data communication

•

S7 basic communication

•

S7 communication

•

Direct data exchange

Yes

•

Transmission rates

Up to 12 Mbps

•

Automatic baud rate search

Yes (only if interface is passive)

•

Intermediate memory

244 bytes I / 244 bytes O

•

Address areas

max. 32 with max. 32 bytes each

•

DPV1

GSD file

The latest GSD file is available at:
http://www.ad.siemens.de/support
in the Product Support area

Programming
Programming language

LAD/FBD/STL

Available instructions

See the Instruction List

Nesting levels

System functions (SFCs)

See the Instruction List

System function blocks (SFBs)

See the Instruction List

User program security

Yes

Dimensions
Mounting dimensions W x H x D (mm)

40 x 125 x 130

Weight

290 g

Voltages and currents
Power supply (rated value)
•

7-18

Permitted range

24 VDC
20.4 V to 28.8 V

Current consumption (no-load operation)

Typically 60 mA

Inrush current

Typically 2.5 A

Power consumption (nominal value)

0.8 A

I2t

0.5 A2s

External fusing of power supply lines
(recommended)

min. 2 A

Power loss

Typically 2,5 W

CPU 31xC and CPU 31x, Technical data
Manual, Edition 08/2004, A5E00105475-05

Technical data of CPU 31x
7.5 CPU 315-2 PN/DP

7.5

CPU 315-2 PN/DP

Technical data
Table 7-6

Technical data for the CPU 315-2 PN/DP

Technical data
CPU and version
Order number

6ES7315-2EG10-0AB0

•

Hardware version

•

Firmware version

V 2.3.0

•

Associated programming package

STEP 7 as of V 5.3 + SP 1

Memory
RAM
•

RAM

128 KB

•

Expandable

Capacity of the retentive memory for retentive
data blocks

128 KB

Load memory

Plugged in with MMC (max. 8 MB)

Buffering

Guaranteed by MMC (maintenance-free)

Data storage life on the MMC
(following final programming)

At least 10 years

Execution times
Processing times of
•

Bit operations

0.1 μs

•

Word instructions

0.2 μs

•

Fixed-point arithmetic

2 μs

•

Floating-point arithmetic

6 μs

Timers/counters and their retentivity
S7 counters

256

•

Retentive memory

Configurable

•

Default

from C0 to C7

•

Counting range

IEC Counters

0 to 999
Yes

•

Type

SFB

•

Number

Unlimited
(limited only by RAM size)

S7 timers

256

•

Retentive memory

Configurable

•

Default

Not retentive

•

Timer range

10 ms to 9990 s

CPU 31xC and CPU 31x, Technical data
Manual, Edition 08/2004, A5E00105475-05

7-19

Technical data of CPU 31x
7.5 CPU 315-2 PN/DP
Technical data
IEC Timers

Yes

•

Type

SFB

•

Number

Unlimited
(limited only by RAM size)

Data areas and their retentivity
Flag bits
•

Retentive memory

•

Default retentivity

Clock flag bits

2048 bytes
Configurable
From MB0 to MB15
8 (1 byte per flag bit)

Data blocks
•

Number

1023
(DB 1 to DB 1023)

•

Length

16 KB

•

Non-Retain support (configured retention)

Yes

Local data per priority class

Max. 1024 bytes per run level / 510 bytes per
block

Blocks
Total

1024 (DBs, FCs, FBs)
The maximum number of blocks that can be
loaded may be reduced if you are using another
MMC.

OBs
•

Length

See the Instruction List
16 KB

Nesting depth
•

Per priority class

•

additional within an error OB

FBs
•

Number

•

Length

See the Instruction List
2048
(FB 0 to FB 2047)

FCs
•

Number

16 KB
See the Instruction List
2048
(FC 0 to FC 2047)

•

Length

16 KB

Address areas (I/O)

7-20

Total I/O address area

max. 2048 bytes/2048 bytes
(can be freely addressed)

Distributed

max. 2000 bytes

I/O process image

128/128

Digital channels

16384/16384

of those local

Max. 1024

Analog channels

1024/1024

of those local

Max. 256

CPU 31xC and CPU 31x, Technical data
Manual, Edition 08/2004, A5E00105475-05

Technical data of CPU 31x
7.5 CPU 315-2 PN/DP
Technical data
Assembly
Racks

Max. 4

Modules per rack

Number of DP masters
•

Integrated

•

via CP

Number of function modules and communication processors you can operate
•

Max. 8

•

CP (PtP)

Max. 8

•

CP (LAN)

Max. 10

Time-of-day
Real-time clock

Yes (hardware clock)

•

Factory setting

DT#1994-01-01-00:00:00

•

Buffered

Yes

•

Buffered period

Typically 6 weeks (at an ambient temperature of
104 °F)

•

Behavior of the clock on expiration of the
buffered period

The clock keeps running, continuing at the timeof-day it had when power was switched off.

•

Behavior of the realtime clock after POWER
ON

The clock continues running after POWER OFF.

•

Accuracy

Deviation per day: < 10 s

Operating hours counter

•

Number

•

Value range

2 31 hours
(if SFC 101 is used)

•

Granularity

1 hour

•

Retentive

yes; must be manually restarted after every
restart

Clock synchronization

Yes

•

In the PLC

Master/slave

•

On MPI

Master/slave

S7 signaling functions
Number of stations that can be logged on for
signaling functions

Process diagnostics messages

Yes

•

Simultaneously enabled interrupt S blocks

(depends on the number of connections
configured for PG / OP and S7 basic
communication)
40

Testing and commissioning functions
Status/control variables
•

Variables

CPU 31xC and CPU 31x, Technical data
Manual, Edition 08/2004, A5E00105475-05

Yes
Inputs, outputs, memory bits, DBs, timers,
counters

7-21

Technical data of CPU 31x
7.5 CPU 315-2 PN/DP
Technical data
•

Number of variables
– Of those as status variable
– Of those as control variable

30
Max. 30
Max. 14

Forcing
•

Variables

Inputs/Outputs

•

Number of variables

Max. 10

Block status

Yes

Single step

Yes

Breakpoints

Diagnostic buffer

Yes

•

Number of entries (not configurable)

Max. 100

Communication functions
Open IE communication via TCP/IP

Yes (via integrated PROFINET interface and
loadable FBs, max. 8 connections)

PG/OP communication

Yes

Global data communication

Yes

•

Number of GD circuits

•

Number of GD packets
– Sending stations
– Receiving stations

Max. 8

Length of GD packets
– Consistent data

max. 22 bytes

•

S7 basic communication
•

User data per request
– Consistent data

S7 communication

Max. 8
Max. 8
22 bytes
Yes
max. 76 bytes
76 bytes
Yes

•

As server

Yes

•

as client

Yes (via integrated PN interface and loadable
FBs, or even via CP and loadable FBs)

•

User data per request
– Consistent data

See the STEP 7 Online Help, Common

parameters of SFBs/FBs and SFC/FC of the S7
communication)

S5-compatible communication

Yes (via CP and loadable FCs)

Number of connections

can be used for
•

•

7-22

PG communication
– Reserved (default)
– Configurable

Max. 15

OP communication
– Reserved (default)
– Configurable

Max. 15

S7-based communication
– Reserved (default)
– Configurable

Max. 14

1
1 to 15
1
1 to 15
0
0 to 14

CPU 31xC and CPU 31x, Technical data
Manual, Edition 08/2004, A5E00105475-05

Technical data of CPU 31x
7.5 CPU 315-2 PN/DP
Technical data
Routing
• Interface X1 configured as
– MPI
– DP master
– DP slave (active)
• Interface X2 configured as PROFINET

Yes
Max. 10
Max. 24
Max. 14
Max. 24

CBA (at 50 % communication load)
Maximum data length for arrays and
structures between two partners
– Acyclic PROFINET interconnections
– Cyclic PROFINET interconnections
– Local interconnections

1400 bytes

•

Number of coupled PROFIBUS devices

•

Total of all master/slave connections

1000

•

Number of device-internal and PROFIBUS
interconnections

500

•

Number of remote interconnecting partners

•

450 bytes
Slave-dependent

Remote interconnections with acyclical transmission
Scan rate: Minimum scan interval

500 ms

Number of incoming interconnections

100

Number of outgoing interconnections

100

Remote interconnections with cyclical transmission
Scan rate: Minimum scan interval

10 ms

Number of incoming interconnections

200

Number of outgoing interconnections

200

HMI interconnections via PROFINET (acyclic)
HMI interconnections

500 ms

Number of HMI variables

200

Sum of all interconnections

4000 bytes input/4000 bytes output

Interfaces
1st interface
Type of interface

Integrated RS485 interface

Physics

RS 485

electrically isolated

Yes

Interface power supply
(15 to 30 VDC)

max. 200 mA

Functionality
•

MPI

Yes

•

PROFIBUS DP

Yes

•

Point-to-point communication

•

PROFINET

CPU 31xC and CPU 31x, Technical data
Manual, Edition 08/2004, A5E00105475-05

7-23

Technical data of CPU 31x
7.5 CPU 315-2 PN/DP
Technical data
MPI
Services
•

PG/OP communication

Yes

•

Routing

Yes

•

Global data communication

Yes

•

S7 basic communication

Yes

•

S7 communication
– As server
– As client

Yes

Transmission rates

Max. 12 Mbps

•

Yes
No (but via CP and loadable FBs)

DP master
Services
•

PG/OP communication

Yes

•

Routing

Yes

•

Global data communication

•

S7 basic communication

•

S7 communication

•

Constant bus cycle time

Yes

•

SYNC/FREEZE

Yes

•

DPV1

Yes

Transmission speed

Up to 12 Mbps

Number of DP slaves

124

DP slave
Services
•

Routing

Yes (only if interface is active)

•

Global data communication

•

S7 basic communication

•

S7 communication

•

Direct data exchange

Yes

•

Transmission rates

Up to 12 Mbps

•

Automatic baud rate search

Yes (only if interface is passive)

•

Intermediate memory

244 bytes I / 244 bytes O

•

Address areas

max. 32 with max. 32 bytes each

•

DPV1

2nd interface
Type of interface

7-24

PROFINET

Physics

Ethernet

electrically isolated

Yes

Autosensing (10/100 Mbps)

Yes

CPU 31xC and CPU 31x, Technical data
Manual, Edition 08/2004, A5E00105475-05

Technical data of CPU 31x
7.5 CPU 315-2 PN/DP
Technical data
Functionality
•

PROFINET

Yes

•

MPI

•

PROFIBUS DP

•

Point-to-point communication

Services
•

PG communication

Yes

•

OP communication

Yes

•

S7 communication
– Max. configurable interconnections

Yes (with loadable FBs)

•

Routing

Yes

•

PROFINET IO

Yes

•

PROFINET CBA

Yes

PROFINET IO
Number of integrated PROFINET IO controllers

Number of connectable PROFINET IO devices

128

Max. user data consistency with PROFINET IO

256 bytes

Update Time

1 ms to 512 ms
The minimum value is determined by the set
communication portion for PROFINET IO, the
number of IO devices and the amount of
configured user data.

Routing

Yes

S7 protocol functions
•

PG functions

Yes

•

OP functions

Yes

•

Open IE communication via TCP/IP

GSD file

Yes
The latest GSD file is available at:
http://www.ad.siemens.de/support
in the Product Support area

Programming
Programming language

LAD/FBD/STL

Available instructions

See the Instruction List

Nesting levels

System functions (SFCs)

See the Instruction List

System function blocks (SFBs)

See the Instruction List

User program security

Yes

Dimensions
Mounting dimensions W x H x D (mm)

80 x 125 x 130

Weight

460 g

CPU 31xC and CPU 31x, Technical data
Manual, Edition 08/2004, A5E00105475-05

7-25

Technical data of CPU 31x
7.6 CPU 317-2 DP
Technical data
Voltages and currents
Power supply (rated value)
•

7.6

Permitted range

24 VDC
20.4 V to 28.8 V

Current consumption (no-load operation)

100 mA

Inrush current

Typically 2.5 A

I2t

Min. 1 A2s

External fusing of power supply lines
(recommended)

min. 2 A

Power loss

Typically 3.5 W

CPU 317-2 DP

Technical data
Table 7-7

Technical data for the CPU 317-2 DP

Technical data
CPU and version
Order number

6ES7317-2AJ10-0AB0

•

Hardware version

•

Firmware version

V 2.1.0

•

Associated programming package

STEP 7 as of V 5.2 + SP 1

Memory
RAM
•

Integrated

512 KB

•

Expandable

Capacity of the retentive memory for retentive
data blocks

max. 256 KB

Load memory

Plugged in with MMC (max. 8 MB)

Buffering

Guaranteed by MMC (maintenance-free)

Data storage life on the MMC
(following final programming)

At least 10 years

Execution times
Processing times of

7-26

•

Bit operations

0.05 μs

•

Word instructions

0.2 μs

•

Fixed-point arithmetic

0.2 μs

•

Floating-point arithmetic

1.0 μs

CPU 31xC and CPU 31x, Technical data
Manual, Edition 08/2004, A5E00105475-05

Technical data of CPU 31x
7.6 CPU 317-2 DP
Technical data
Timers/counters and their retentivity
S7 counters

512

•

Retentive memory

Configurable

•

Default

from C0 to C7

•

Counting range

0 to 999

IEC Counters

Yes

•

Type

SFB

•

Number

Unlimited
(limited only by RAM size)

S7 timers

512

•

Retentive memory

Configurable

•

Default

Not retentive

•

Timer range

10 ms to 9990 s

IEC Timers

Yes

•

Type

SFB

•

Number

Unlimited
(limited only by RAM size)

Data areas and their retentivity
Flag bits
•

Retentive memory

•

Default retentivity

Clock flag bits

4096 bytes
Configurable
From MB0 to MB15
8 (1 byte per flag bit)

Data blocks
•

Number

2047
(DB 1 to DB 2047)

•

Length

64 KB

•

Non-Retain support (configured retention)

Yes

Local data per priority class

max. 1024 bytes

Blocks
Total

2048 (DBs, FCs, FBs)
The maximum number of blocks that can be
loaded may be reduced if you are using another
MMC.

OBs
•

Length

See the Instruction List
64 KB

Nesting depth
•

Per priority class

•

additional within an error OB

FBs
•

Number

•

Length

See the Instruction List
2048
(FB 0 to FB 2047)

CPU 31xC and CPU 31x, Technical data
Manual, Edition 08/2004, A5E00105475-05

64 KB

7-27

Technical data of CPU 31x
7.6 CPU 317-2 DP
Technical data
FCs
•

Number

•

Length

See the Instruction List
2048
(FC 0 to FC 2047)
64 KB

Address areas (I/O)
Total I/O address area

max. 8192 bytes/8192 bytes
(can be freely addressed)

Distributed

max. 8192 bytes

I/O process image

256/256

Digital channels

65536/65536

of those local

Max. 1024

Analog channels

4096/4096

of those local

256/256

Assembly
Racks

Max. 4

Modules per rack

Number of DP masters
•

Integrated

•

via CP

Number of function modules and communication processors you can operate
•

Max. 8

•

CP (PtP)

Max. 8

•

CP (LAN)

Max. 10

Time-of-day
Real-time clock

Yes (HW clock)

•

Buffered

Yes

•

Buffered period

Typically 6 weeks (at an ambient temperature of
104 °F)

•

Behavior of the clock on expiration of the
buffered period

The clock keeps running, continuing at the timeof-day it had when power was switched off.

•

Accuracy

Deviation per day: < 10 s

Operating hours counter

•

Number

0 to 3

•

Value range

2 31 hours

•

Granularity

1 hour

•

Retentive

yes; must be manually restarted after every
restart

(if SFC 101 is used)

Clock synchronization

7-28

Yes

•

In the PLC

Master/slave

•

On MPI

Master/slave

CPU 31xC and CPU 31x, Technical data
Manual, Edition 08/2004, A5E00105475-05

Technical data of CPU 31x
7.6 CPU 317-2 DP
Technical data
S7 signaling functions
Number of stations that can be logged on for
signaling functions

Process diagnostics messages

Yes

•

Simultaneously enabled interrupt S blocks

(depends on the number of connections
configured for PG / OP and S7 basic
communication)
60

Testing and commissioning functions
Status/control variables

Yes

•

Variables

Inputs, outputs, memory bits, DBs, timers,
counters

•

Number of variables
– Of those as status variable
– Of those as control variable

30
Max. 30
Max. 14

Forcing
•

Variables

Inputs/Outputs

•

Number of variables

Max. 10

Block status

Yes

Single step

Yes

Breakpoints

Diagnostic buffer

Yes

•

Number of entries (not configurable)

Max. 100

Communication functions
PG/OP communication

Yes

Global data communication

Yes

•

Number of GD circuits

•

Number of GD packets
– Sending stations
– Receiving stations

Max. 8

Length of GD packets
– Consistent data

max. 22 bytes

•

S7 basic communication
•

User data per request
– Consistent data

Max. 8
Max. 8
22 bytes
Yes
max. 76 bytes
76 bytes (for X_SEND or X_RCV)
76 bytes (for X_PUT or X_GET as the server)

S7 communication

Yes

•

As server

Yes

•

as client

Yes (via CP and loadable FBs)

•

User data per request
– Consistent data

Max. 180 bytes (with PUT/GET)

S5-compatible communication

Yes (via CP and loadable FCs)

CPU 31xC and CPU 31x, Technical data
Manual, Edition 08/2004, A5E00105475-05

160 byte (as the server)

7-29

Technical data of CPU 31x
7.6 CPU 317-2 DP
Technical data
Number of connections

can be used for
•

•

PG communication
– Reserved (default)
– Configurable

Max. 31

OP communication
– Reserved (default)
– Configurable

Max. 31

S7-based communication
– Reserved (default)
– Configurable

Max. 30

Routing

1
1 to 31
1
1 to 31
0
0 to 30
Yes (max. 8)

Interfaces
1st interface
Type of interface

Integrated RS485 interface

Physics

RS 485

electrically isolated

Yes

Interface power supply
(15 to 30 VDC)

max. 200 mA

Functionality
•

MPI

Yes

•

PROFIBUS DP

Yes

•

Point-to-point communication

MPI
Services
•

PG/OP communication

Yes

•

Routing

Yes

•

Global data communication

Yes

•

S7 basic communication

Yes

•

S7 communication
– As server
– As client

Yes

Transmission rates

Max. 12 Mbps

•

No (but via CP and loadable FBs)

DP master
Services

7-30

•

PG/OP communication

Yes

•

Routing

Yes

•

Global data communication

•

S7 basic communication

•

S7 communication

•

Constant bus cycle time

Yes

•

SYNC/FREEZE

Yes

•

DPV1

Yes

CPU 31xC and CPU 31x, Technical data
Manual, Edition 08/2004, A5E00105475-05

Technical data of CPU 31x
7.6 CPU 317-2 DP
Technical data
Transmission speed

Up to 12 Mbps

Number of DP slaves

124

Address range per DP slave

max. 244 bytes

DP slave
(except for DP slave at both interfaces)
Services
•

Routing

Yes (only if interface is active)

•

Global data communication

•

S7 basic communication

•

S7 communication

•

Direct data exchange

Yes

•

Transmission rates

Up to 12 Mbps

•

Automatic baud rate search

Yes (only if interface is passive)

•

Intermediate memory

244 bytes I / 244 bytes O

•

Address areas

max. 32 with max. 32 bytes each

•

DPV1

2nd interface
Type of interface

Integrated RS485 interface

Physics

RS 485

electrically isolated

Yes

Type of interface

Integrated RS485 interface

Interface power supply (15 to 30 VDC)

max. 200 mA

Functionality
MPI

PROFIBUS DP

Yes

Point-to-point communication

DP master
Services
•

PG/OP communication

Yes

•

Routing

Yes

•

Global data communication

•

S7 basic communication

•

S7 communication

•

Constant bus cycle time

Yes

•

SYNC/FREEZE

Yes

•

DPV1

Yes

Transmission speed

Up to 12 Mbps

Number of DP slaves

124

Address area

max. 244 bytes

CPU 31xC and CPU 31x, Technical data
Manual, Edition 08/2004, A5E00105475-05

7-31

Technical data of CPU 31x
7.6 CPU 317-2 DP
Technical data
DP slave
(except for DP slave at both interfaces)
Services
•

PG/OP communication

Yes

•

Routing

Yes (only if interface is active)

•

Global data communication

•

S7 basic communication

•

S7 communication

•

Direct data exchange

Yes

•

Transmission rates

Up to 12 Mbps

•

Automatic baud rate search

Yes (only if interface is passive)

•

Intermediate memory

244 bytes I / 244 bytes O

•

Address areas

max. 32 with max. 32 bytes each

•

DPV1

GSD file

The latest GSD file is available at:
http://www.ad.siemens.de/support
in the Product Support area

Programming
Programming language

LAD/FBD/STL

Available instructions

See the Instruction List

Nesting levels

System functions (SFCs)

See the Instruction List

System function blocks (SFBs)

See the Instruction List

User program security

Yes

Dimensions
Mounting dimensions W x H x D (mm)

80 x 125 x 130

Weight

460 g

Voltages and currents
Power supply (rated value)
•

7-32

Permitted range

24 VDC
20.4 V to 28.8 V

Current consumption (no-load operation)

Typically 100 mA

Inrush current

Typically 2.5 A

I2t

1 A2 s

External fusing of power supply lines
(recommended)

min. 2 A

Power loss

Typically 4 W

CPU 31xC and CPU 31x, Technical data
Manual, Edition 08/2004, A5E00105475-05

Technical data of CPU 31x
7.7 CPU 317-2 PN/DP

7.7

CPU 317-2 PN/DP

Technical data
Table 7-8

Technical data for the CPU 317-2 PN/DP

Technical data
CPU and version
Order number

6ES7317-2EJ10-0AB0

•

Hardware version

•

Firmware version

V 2.3.0

•

Associated programming package

STEP 7 as of V 5.3 + SP 1

Memory
RAM
•

RAM

512 KB

•

Expandable

Capacity of the retentive memory for retentive
data blocks

256 KB

Load memory

Plugged in with MMC (max. 8 MB)

Buffering

Guaranteed by MMC (maintenance-free)

Data storage life on the MMC
(following final programming)

At least 10 years

Execution times
Processing times of
•

Bit operations

0.05 μs

•

Word instructions

0.2 μs

•

Fixed-point arithmetic

0.2 μs

•

Floating-point arithmetic

1.0 μs

Timers/counters and their retentivity
S7 counters

512

•

Retentive memory

Configurable

•

Default

from C0 to C7

•

Counting range

IEC Counters

0 to 999
Yes

•

Type

SFB

•

Number

Unlimited
(limited only by RAM size)

S7 timers

512

•

Retentive memory

Configurable

•

Default

Not retentive

•

Timer range

10 ms to 9990 s

CPU 31xC and CPU 31x, Technical data
Manual, Edition 08/2004, A5E00105475-05

7-33

Technical data of CPU 31x
7.7 CPU 317-2 PN/DP
Technical data
IEC Timers

Yes

•

Type

SFB

•

Number

Unlimited
(limited only by RAM size)

Data areas and their retentivity
Flag bits
•

Retentive memory

•

Default retentivity

Clock flag bits

4096 bytes
Configurable
From MB0 to MB15
8 (1 byte per flag bit)

Data blocks
•

Number

2047
(DB 1 to DB 2047)

•

Length

64 KB

•

Non-Retain support (configured retention)

Yes

Local data per priority class

max. 1024 bytes

Blocks
Total

2048 (DBs, FCs, FBs)
The maximum number of blocks that can be
loaded may be reduced if you are using another
MMC.

OBs
•

Length

See the Instruction List
64 KB

Nesting depth
•

Per priority class

•

additional within an error OB

FBs
•

Number

•

Length

See the Instruction List
2048
(FB 0 to FB 2047)

FCs
•

Number

64 KB
See the Instruction List
2048
(FC 0 to FC 2047)

•

Length

64 KB

Address areas (I/O)
Total I/O address area

max. 8192 bytes/8192 bytes
(can be freely addressed)

Distributed

max. 8192 bytes

I/O process image

7-34

•

Configurable

2048/2048

•

Default

256/256

Digital channels

65536/65536

of those local

Max. 1024

CPU 31xC and CPU 31x, Technical data
Manual, Edition 08/2004, A5E00105475-05

Technical data of CPU 31x
7.7 CPU 317-2 PN/DP
Technical data
Analog channels

4096/4096

of those local

256/256

Assembly
Racks

Max. 4

Modules per rack

Number of DP masters
•

Integrated

•

via CP

Number of function modules and communication processors you can operate
•

Max. 8

•

CP (PtP)

Max. 8

•

CP (LAN)

Max. 10

Time-of-day
Real-time clock

Yes (hardware clock)

•

Factory setting

DT#1994-01-01-00:00:00

•

Buffered

Yes

•

Buffered period

Typically 6 weeks (at an ambient temperature of
104 °F)

•

Behavior of the clock on expiration of the
buffered period

The clock keeps running, continuing at the timeof-day it had when power was switched off.

•

Behavior of the realtime clock after POWER
ON

The clock continues running after POWER OFF.

•

Accuracy

Deviation per day: < 10 s

Operating hours counter

•

Number

0 to 3

•

Value range

2 31 hours
(if SFC 101 is used)

•

Granularity

1 hour

•

Retentive

yes; must be manually restarted after every
restart

Clock synchronization

Yes

•

In the PLC

Master/slave

•

On MPI

Master/slave

S7 signaling functions
Number of stations that can be logged on for
signaling functions

Process diagnostics messages

Yes

•

Simultaneously enabled interrupt S blocks

(depends on the number of connections
configured for PG / OP and S7 basic
communication)
60

Testing and commissioning functions
Status/control variables
•

Variables

CPU 31xC and CPU 31x, Technical data
Manual, Edition 08/2004, A5E00105475-05

Yes
Inputs, outputs, memory bits, DBs, timers,
counters

7-35

Technical data of CPU 31x
7.7 CPU 317-2 PN/DP
Technical data
•

Number of variables
– Of those as status variable
– Of those as control variable

30
Max. 30
Max. 14

Forcing
•

Variables

Inputs/Outputs

•

Number of variables

Max. 10

Block status

Yes

Single step

Yes

Breakpoints

Diagnostic buffer

Yes

•

Number of entries (not configurable)

Max. 100

Communication functions
Open IE communication via TCP/IP

Yes (via integrated PROFINET interface and
loadable FBs, max. 8 connections)

PG/OP communication
Global data communication

Yes

•

Number of GD circuits

•

Number of GD packets
– Sending stations
– Receiving stations

Max. 8

Length of GD packets
– Consistent data

max. 22 bytes

•

S7 basic communication
•

User data per request
– Consistent data

S7 communication

Max. 8
Max. 8
22 bytes
Yes
max. 76 bytes
76 bytes
Yes

•

As server

Yes

•

as client

Yes (via integrated PN interface and loadable
FBs, or even via CP and loadable FBs)

•

User data per request
– Consistent data

See the STEP 7 Online Help, Common

parameters of SFBs/FBs and SFC/FC of the S7
communication)

S5-compatible communication

Yes (via CP and loadable FCs)

Number of connections

can be used for
•

•

7-36

PG communication
– Reserved (default)
– Configurable

Max. 31

OP communication
– Reserved (default)
– Configurable

Max. 31

S7-based communication
– Reserved (default)
– Configurable

Max. 30

1
1 to 31
1
1 to 31
0
0 to 30

CPU 31xC and CPU 31x, Technical data
Manual, Edition 08/2004, A5E00105475-05

Technical data of CPU 31x
7.7 CPU 317-2 PN/DP
Technical data
Routing
• Interface X1 configured as
– MPI
– DP master
– DP slave (active)
• Interface X2 configured as
– PROFINET

Yes
Max. 10
Max. 24
Max. 14
Max. 24

1400 bytes

•

Number of coupled PROFIBUS devices

•

Total of all master/slave connections

1000

•

Number of device-internal and PROFIBUS
interconnections

500

•

Number of remote interconnecting partners

•

450 bytes
Slave-dependent

Remote interconnections with acyclical transmission
Scan rate: Minimum scan interval

500 ms

Number of incoming interconnections

100

Number of outgoing interconnections

100

Remote interconnections with cyclical transmission
Scan rate: Minimum scan interval

10 ms

Number of incoming interconnections

200

Number of outgoing interconnections

200

HMI interconnections via PROFINET (acyclic)
HMI interconnections

500 ms

Number of HMI variables

200

Sum of all interconnections

4000 bytes input/4000 bytes output

Interfaces
1st interface
Type of interface

Integrated RS485 interface

Physics

RS 485

electrically isolated

Yes

Interface power supply
(15 to 30 VDC)

max. 200 mA

Functionality
•

MPI

Yes

•

PROFIBUS DP

Yes

•

Point-to-point communication

•

PROFINET

CPU 31xC and CPU 31x, Technical data
Manual, Edition 08/2004, A5E00105475-05

7-37

Technical data of CPU 31x
7.7 CPU 317-2 PN/DP
Technical data
MPI
Services
•

PG/OP communication

Yes

•

Routing

Yes

•

Global data communication

Yes

•

S7 basic communication

Yes

•

S7 communication
– As server
– As client

Yes

Transmission rates

Max. 12 Mbps

•

Yes
No (but via CP and loadable FBs)

DP master
Services
•

PG/OP communication

Yes

•

Routing

Yes

•

Global data communication

•

S7 basic communication

•

S7 communication

•

Constant bus cycle time

Yes

•

SYNC/FREEZE

Yes

•

DPV1

Yes

Transmission speed

Up to 12 Mbps

Number of DP slaves

124

DP slave
Services
•

Routing

Yes (only if interface is active)

•

Global data communication

•

S7 basic communication

•

S7 communication

•

Direct data exchange

Yes

•

Transmission rates

Up to 12 Mbps

•

Automatic baud rate search

Yes (only if interface is passive)

•

Intermediate memory

244 bytes I / 244 bytes O

•

Address areas

max. 32 with max. 32 bytes each

•

DPV1

2nd interface
Type of interface

7-38

PROFINET

Physics

Ethernet

electrically isolated

Yes

Autosensing (10/100 Mbps)

Yes

CPU 31xC and CPU 31x, Technical data
Manual, Edition 08/2004, A5E00105475-05

Technical data of CPU 31x
7.7 CPU 317-2 PN/DP
Technical data
Functionality
•

PROFINET

Yes

•

MPI

•

PROFIBUS DP

•

Point-to-point communication

Services
•

PG communication

Yes

•

OP communication

Yes

•

S7 communication
– Max. configurable interconnections

Yes (with loadable FBs)
16

•

Routing

Yes

•

PROFINET IO

Yes

•

PROFINET CBA

Yes

PROFINET IO
Number of integrated PROFINET IO controllers

Number of connectable PROFINET IO devices

128

Max. user data consistency with PROFINET IO

256 bytes

Update Time

1 ms to 512 ms
The minimum value is determined by the set
communication portion for PROFINET IO, the
number of IO devices and the amount of
configured user data.

S7 protocol functions
•

PG functions

Yes

•

OP functions

Yes

•

Open IE communication via TCP/IP

GSD file

Yes
The latest GSD file is available at:
http://www.ad.siemens.de/support
in the Product Support area

Programming
Programming language

LAD/FBD/STL

Available instructions

See the Instruction List

Nesting levels

System functions (SFCs)

See the Instruction List

System function blocks (SFBs)

See the Instruction List

User program security

Yes

Dimensions
Mounting dimensions W x H x D (mm)

80 x 125 x 130

Weight

460 g

CPU 31xC and CPU 31x, Technical data
Manual, Edition 08/2004, A5E00105475-05

7-39

Technical data of CPU 31x
7.7 CPU 317-2 PN/DP
Technical data
Voltages and currents
Power supply (rated value)
•

7-40

Permitted range

24 VDC
20.4 V to 28.8 V

Current consumption (no-load operation)

100 mA

Inrush current

Typically 2.5 A

I2t

Min. 1 A2s

External fusing of power supply lines
(recommended)

min. 2 A

Power loss

Typically 3.5 W

CPU 31xC and CPU 31x, Technical data
Manual, Edition 08/2004, A5E00105475-05

Appendix
A.1

Information about upgrading to a CPU 31xC or CPU 31x

A.1.1

Area of applicability

Who should read this information?
You are already using a CPU from the SIEMENS S7-300 series and now want to upgrade to
a new device.
Please note that problems may occur while downloading your user program to the "new"
CPU.

If you have used one of the following CPUs in the past ...
CPU

Order number

CPU 312 IFM

6ES7 312-5AC02-0AB0

as of version
Firmware

Hardware

1.0.0

6ES7 312-5AC82-0AB0
CPU 313

6ES7 313-1AD03-0AB0

1.0.0

CPU 314

6ES7 314-1AE04-0AB0

1.0.0

CPU 314 IFM

6ES7 314-5AE03-0AB0

1.0.0

CPU 314 IFM

6ES7 314-5AE83-0AB0

1.0.0

CPU 315

6ES7 315-1AF03-0AB0

1.0.0

CPU 315-2 DP

6ES7 315-2AF03-0AB0

1.0.0

CPU 316-2 DP

6ES7 316-2AG00-0AB0

1.0.0

CPU 318-2 DP

6ES7 318-2AJ00-0AB0

V3.0.0

6ES7 314-1AE84-0AB0

6ES7 315-2AF83-0AB0

CPU 31xC and CPU 31x, Technical data
Manual, Edition 08/2004, A5E00105475-05

A-1

Appendix
A.1 Information about upgrading to a CPU 31xC or CPU 31x

... then please note if you upgrade to one of the following CPUs
CPU

Order number

From version

Hereafter called

Firmware

Hardware

312

6ES7312-1AD10-0AB0

V2.0.0

312C

6ES7312-5BD01-0AB0

V2.0.0

313C

6ES7313-5BE01-0AB0

V2.0.0

313C-2 PtP

6ES7313-6BE01-0AB0

V2.0.0

313C-2 DP

6ES7313-6CE01-0AB0

V2.0.0

314

6ES7314-1AF10-0AB0

V2.0.0

314C-2 PtP

6ES7314-6BF01-0AB0

V2.0.0

314C-2 DP

6ES7314-6CF01-0AB0

V2.0.0

315-2 DP

6ES7315-2AG10-0AB0

V2.0.0

315-2 PN/DP

6ES7315-2EG10-0AB0

V2.3.0

317-2 DP

6ES7317-2AJ10-0AB0

V2.1.0

317-2 PN/DP

6ES7317-2EJ10-0AB0

V2.3.0

CPU 31xC/31x

Reference
If you intend to migrate from PROFIBUS DP to PROFINET, we also recommend the
following manual: Guide: From PROFIBUS DP to PROFINET IO

Siemens Simatic S7 300 Cpu 31Xc And 31X Users Manual 31x, Technical Data

S7-300 to the manual f531312e-6de6-4209-b2fb-a63a795f637b

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