Silicon Laboratories Finland WF111 IEEE 802.11b/g/n Wi-Fi module WF111 User Manual WF111 Datasheet
Silicon Laboratories Finland Oy IEEE 802.11b/g/n Wi-Fi module WF111 WF111 Datasheet
Contents
- 1. User Manual and Installations
- 2. User Manual
User Manual and Installations







![Bluegiga Technologies Oy Page 8 of 47 3 Pinout and terminal descriptions 20PIO[3]19VDD_PADS18PIO[4]17VDD_REGIN16PIO[2]15VDD_SDIO21GND22PIO[0]23REGEN24PIO[1]25RST26SPI_CS27PIO[5]28VDD_PA29GND14 GND13 SPI_MOSI12 SPI_CLK11 SPI_MISO10 VDD_ANA9BT8GND7SDIO_CMD6SDIO_CLK5SDIO_DAT[3]4SDIO_DAT[2]3SDIO_DAT[1]2SDIO_DAT[0]1GND33 GND_PAD30 GND31 ANT32 GND Figure 2: WF111 pinout](https://usermanual.wiki/Silicon-Laboratories-Finland/WF111.User-Manual-and-Installations/User-Guide-1801708-Page-8.png)
![Bluegiga Technologies Oy Page 9 of 47 POWER SUPPLIES PIN NUMBER DESCRIPTION VDD_REGIN 17 Input for the internal regulators REGEN 23 Pull high to enable internal voltage regulators (2.0V max) GND 1, 8, 14, 21, 29, 30, 32 Ground GND_PAD 33 Thermal pad, on bottom of WF111 VDD_ANA 10 Positive supply for PA control VDD_PADS 19 Positive supply for the digital interfaces VDD_SDIO 15 Positive supply for the SDIO interface VDD_PA 28 Positive supply for the power amplifier Table 1: Supply Terminal Descriptions PIO PORT PIN NUMBER PAD TYPE DESCRIPTION PIO[0] 22 Bi-directional, programmable strength internal pull-down/pull-up Programmable input/output line. Can be used for Bluetooth co-existence. PIO[1] 24 PIO[2] 16 PIO[3] 20 PIO[4] 18 PIO[5] 27 Table 2: GPIO Terminal Descriptions](https://usermanual.wiki/Silicon-Laboratories-Finland/WF111.User-Manual-and-Installations/User-Guide-1801708-Page-9.png)
![Bluegiga Technologies Oy Page 10 of 47 SDIO/CSPI Interfaces PIN NUMBER PAD TYPE DESCRIPTION SDIO_DATA[0] 2 Bi-directional, tri-state, weak internal pull-up Synchronous data input/output SDIO_SPI_DI SDIO SPI data output CSPI_MISO CSPI data output SDIO_DATA[1] 3 Synchronous data input/output SDIO_SPI_INT SDIO SPI interrupt output CSPI_INT CSPI data input SDIO_DATA[2] 4 Synchronous data input/output SDIO_DATA[3] 5 Bi-directional, weak/strong internal pull-up Synchronous data input/output SDIO_SPI_CS# SDIO SPI chip select, active low CSPI_CS# CSPI chip select, active low SDIO_CLK 6 Input, weak internal pull-up SDIO clock SDIO_SPI_SCLK SDIO SPI clock CSPI_CLK CSPI clock SDIO_CMD 7 Bi-directional, weak internal pull-up SDIO data input SDIO_SPI_MOSI SDIO SPI data input CSPI_MOSI CSPI data input Table 3: Host Interface Terminal Descriptions](https://usermanual.wiki/Silicon-Laboratories-Finland/WF111.User-Manual-and-Installations/User-Guide-1801708-Page-10.png)





![Bluegiga Technologies Oy Page 16 of 47 4.1.5 CCCR and CIS register defaults AddressBitsFieldnameValue0x00 3-0 CCRx: CCCR format version number 0x2(a); CCCR/FBR version 1.20 7-4 SDIOx: SDIO spec. version 0x3(a); SDIO 2.00 0x01 3-0 SDx: SD format version number 0x1; SD Physical Specification 1.10 0x07 6 SCSI: Support continuous SPI interrupt supported 0x1 0x08 0 SDC: Card supports direct commands during data transfer 0x1; IO_RW_DIRECT can be executed while transfer in progress 1 SMB: Card supports multiblock 0x1; IO_RW_EXTENDED can be executed in block mode 2 SRW: Card supports read wait 0x1; Wait signal is supported on SDIO_DAT[2] 3 SBS: Card supports suspend/resume 0x0; Operations can't be suspended 4 S4MI: Supports interrupt between data blocks in 4-bit SD 0x0; Block interrupts not supported in 4-bit multi-block transfer 6 LSC: Card is a low-speed card 0x0; Full-speed card 7 4BLS: 4-bit support for low-speed cards 0x0; Full-speed card 0x09-0x0B 23-0 Pointer to card's common CIS 0x001000; Pointer to the start of Card Information Structure 0x12 0 SMPC: Support master power control 0x1; Total card current may exceed 200mA (EMPC, SPS and EPS are available) 0x13 0 SHS: Support high-speed 0x1(a); High speed mode supported (enabled by the host via the EHS bit) Table 7: SDIO CCCR values, (a) can be modified by software](https://usermanual.wiki/Silicon-Laboratories-Finland/WF111.User-Manual-and-Installations/User-Guide-1801708-Page-16.png)




![Bluegiga Technologies Oy Page 21 of 47 The required MIB values for the coexistence scheme in Figure 7 are: unifiCoexScheme ::= 3 unifiCoexPTABTStatusPIO ::= 3 unifiCoexPTABTInbandPIO ::= -1 unifiCoexPTABTActivePIO ::= 5 unifiCoexPTAWLANDenyPIO ::= 4 unifiCoexPeriodicPIO ::= 2 The corresponding PSKEYs for the WT21 are: PSKEY_LC_COMBO_DISABLE_PIO_MASK (0x0028) = 0x0200 0x0000 0x0000 PSKEY_LC_COMBO_DOT11_CHANNEL_PIO_BASE (0x002A) = 0x0011 PSKEY_LC_COMBO_DOT11_ESCO_RTX_PRIORITY ( 0x0050) = 0x0001 PSKEY_LC_COMBO_DOT11_PULL_DISABLE_MASK (0x005A) = 0x0200 PSKEY_LC_COMBO_DOT11_PERIODIC_PIO_MASK (0x005C) = 0x0010 0x0000 PSKEY_LC_COMBO_DOT11_T1 (0x005E) = 0x0043 PSKEY_LC_COMBO_DOT11_T2 (0x005F) = 0x000A PSKEY_TXRX_PIO_CONTROL (0x0209) = 0x0001 For other coexistence schemes, please contact Bluegiga technical support. 4.2.3 Configurable I/O pads A number of programmable bi-directional input/outputs (I/O) are provided. PIO[0:5] logic levels are referred to the VDD_PADS supply line. PIO lines can be configured through software to implement various automated functions or as generic inputs or outputs. As inputs the lines can be configured to have either weak or strong pull-ups or pull-downs. All PIO lines are configured as inputs with weak pull-downs at reset. In addition to the coexistence functions, any of the PIO lines can be configured as interrupt request lines, wake-up lines from sleep modes, status led drivers with multiple internally generated modes, general I/O pins controlled by the host, or as a 32.768 kHz sleep clock input. For further information, please contact Bluegiga technical support. Note: All unused signals can be left floating.](https://usermanual.wiki/Silicon-Laboratories-Finland/WF111.User-Manual-and-Installations/User-Guide-1801708-Page-21.png)




![Bluegiga Technologies Oy Page 26 of 47 7 Example Application Schematic SDIO bus3.3V1.5/1.8Vregulator20PIO[3]19VDD_PADS18PIO[4]17VDD_REGIN16PIO[2]15VDD_SDIO21GND22PIO[0]23REGEN24PIO[1]25RST26SPI_CS27PIO[5]28VDD_PA29GND14 GND13 SPI_MOSI12 SPI_CLK11 SPI_MISO10 VDD_ANA9BT8GND7SDIO_CMD6SDIO_CLK5SDIO_DAT[3]4SDIO_DAT[2]3SDIO_DAT[1]2SDIO_DAT[0]1GND33 GND_PAD30 GND31 ANT32 GND100uF3VIN 2VOUT1GNDCMDCLKDAT[3]DAT[2]DAT[1]DAT[0]RESET+3.3V Figure 9: An example application circuit with SDIO host connection, 3.3V level host logic and 1.5/1.8V core supply, REGEN hard wired to the core supply and RST pad used to reset the module (Note: with N-variant ANT-pad and associated grounds would also be connected)](https://usermanual.wiki/Silicon-Laboratories-Finland/WF111.User-Manual-and-Installations/User-Guide-1801708-Page-26.png)
![Bluegiga Technologies Oy Page 27 of 47 SDIO bus20PIO[3]19VDD_PADS18PIO[4]17VDD_REGIN16PIO[2]15VDD_SDIO21GND22PIO[0]23REGEN24PIO[1]25RST26SPI_CS27PIO[5]28VDD_PA29GND14 GND13 SPI_MOSI12 SPI_CLK11 SPI_MISO10 VDD_ANA9BT8GND7SDIO_CMD6SDIO_CLK5SDIO_DAT[3]4SDIO_DAT[2]3SDIO_DAT[1]2SDIO_DAT[0]1GND33 GND_PAD30 GND31 ANT32 GND100uFCMDCLKDAT[3]DAT[2]DAT[1]DAT[0]+1.8V2.7-4.8VREGEN Figure 10: An example application circuit with SDIO host connection, 1.8V level host logic and a separate power amplifier supply, RST hard wired to the core supply and REGEN pad used to power off and reset the module (Note: with N-variant ANT-pad and associated grounds would also be connected)(Note: engineering samples will require VDD_ANA to be 2.7-3.6V)](https://usermanual.wiki/Silicon-Laboratories-Finland/WF111.User-Manual-and-Installations/User-Guide-1801708-Page-27.png)



















