Silicon Laboratories Si5316 Users Manual Si53xx Family Reference
SI5367 to the manual e1c4a9ea-276d-4966-b940-1eb9f2b53e6d
2015-02-02
: Silicon-Laboratories Silicon-Laboratories-Si5316-Users-Manual-491667 silicon-laboratories-si5316-users-manual-491667 silicon-laboratories pdf
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- 1. Any-Frequency Precision Clock Product Family Overview
- 2. Narrowband vs. Wideband Overview
- 3. Any-Frequency Clock Family Members
- 4. Device Specifications
- 5. DSPLL (All Devices)
- 6. Pin Control Parts (Si5316, Si5322, Si5323, Si5365, Si5366)
- 6.1. Clock Multiplication (Si5316, Si5322, Si5323, Si5365, Si5366)
- 6.1.1. Clock Multiplication (Si5316)
- 6.1.2. Clock Multiplication (Si5322, Si5323, Si5365, Si5366)
- 6.1.3. CKOUT3 and CKOUT4 (Si5365 and Si5366)
- 6.1.4. Loop bandwidth (Si5316, Si5322, Si5323, Si5365, Si5366)
- 6.1.5. Jitter Tolerance (Si5316, Si5323, Si5366)
- 6.1.6. Narrowband Performance (Si5316, Si5323, Si5366)
- 6.1.7. Input-to-Output Skew (Si5316, Si5323, Si5366)
- 6.1.8. Wideband Performance (Si5322 and Si5365)
- 6.1.9. Lock Detect (Si5322 and Si5365)
- 6.1.10. Input-to-Output Skew (Si5322 and Si5365)
- 6.2. PLL Self-Calibration
- 6.3. Pin Control Input Clock Control
- 6.4. Digital Hold/VCO Freeze
- 6.5. Frame Synchronization (Si5366)
- 6.6. Output Phase Adjust (Si5323, Si5366)
- 6.7. Output Clock Drivers
- 6.8. PLL Bypass Mode
- 6.9. Alarms
- 6.10. Device Reset
- 6.11. DSPLLsim Configuration Software
- 6.1. Clock Multiplication (Si5316, Si5322, Si5323, Si5365, Si5366)
- 7. Microprocessor Controlled Parts (Si5319, Si5324, Si5325, Si5326, Si5327, Si5367, Si5368, Si5369, Si5374, Si5375)
- 7.1. Clock Multiplication
- 7.1.1. Jitter Tolerance (Si5319, Si5324, Si5325, Si5326, Si5327, Si5368, Si5369, Si5374 and Si5375)
- 7.1.2. Wideband Parts (Si5325, Si5367)
- 7.1.3. Narrowband Parts (Si5319, Si5324, Si5326, Si5327, Si5368, Si5369, Si5374, Si5375)
- 7.1.4. Loop Bandwidth (Si5319, Si5326, Si5368, Si5375)
- 7.1.5. Lock Detect (Si5319, Si5326, Si5327, Si5368, Si5369, Si5374, Si5375)
- 7.2. PLL Self-Calibration
- 7.2.1. Initiating Internal Self-Calibration
- 7.2.2. Input Clock Stability during Internal Self-Calibration
- 7.2.3. Self-Calibration Caused by Changes in Input Frequency
- 7.2.4. Narrowband Input-to-Output Skew (Si5319, Si5324, Si5326, Si5327, Si5368, Si5369, Si5374, Si5375)
- 7.2.5. Clock Output Behavior Before and During ICAL
- 7.3. Input Clock Configurations (Si5367 and Si5368)
- 7.4. Input Clock Control
- 7.5. Si5319, Si5324, Si5326, Si5327, Si5368, Si5369, Si5374 and Si5375 Free Run Mode
- 7.6. Digital Hold
- 7.6.1. Narrowband Digital Hold (Si5316, Si5324, Si5326, Si5368, Si5369, Si5374)
- 7.6.2. History Settings for Low Bandwidth Devices (Si5324, Si5327, Si5369, Si5374)
- 7.6.3. Recovery from Digital Hold (Si5319, Si5324, Si5326, Si5327, Si5368, Si5369, Si5374)
- 7.6.4. VCO Freeze (Si5319, Si5325, Si5367, Si5375)
- 7.6.5. Digital Hold versus VCO Freeze
- 7.7. Output Phase Adjust (Si5326, Si5368)
- 7.8. Frame Synchronization Realignment (Si5368 and CK_CONFIG_REG = 1)
- 7.9. Output Clock Drivers (Si5319, Si5324, Si5325, Si5326, Si5327, Si5367, Si5368, Si5369, Si5374, Si5375)
- 7.10. PLL Bypass Mode (Si5319, Si5324, Si5325, Si5326, Si5327, Si5367, Si5368, Si5369, Si5374, Si5375)
- 7.11. Alarms (Si5319, Si5324, Si5325, Si5326, Si5327, Si5367, Si5368, Si5369, Si5374, Si5375)
- 7.11.1. Loss-of-Signal Alarms (Si5319, Si5324, Si5325, Si5326, Si5327, Si5367, Si5368, Si5369, Si5374, Si5375)
- 7.11.2. FOS Algorithm (Si5324, Si5325, Si5326, Si5368, Si5369, Si5374)
- 7.11.3. C1B, C2B (Si5319, Si5324, Si5325, Si5326, Si5327, Si5374, Si5375)
- 7.11.4. LOS (Si5319, Si5375)
- 7.11.5. C1B, C2B, C3B, ALRMOUT (Si5367, Si5368, Si5369 [CK_CONFIG_REG = 0])
- 7.11.6. C1B, C2B, C3B, ALRMOUT (Si5368 [CK_CONFIG_REG = 1])
- 7.11.7. LOS Algorithm for Reference Clock Input (Si5319, Si5324, Si5326, Si5327, Si5368, Si5369, Si5374, Si5375)
- 7.11.8. LOL (Si5319, Si5324, Si5326, Si5327, Si5368, Si5369, Si5374, Si5375)
- 7.11.9. Device Interrupts
- 7.12. Device Reset
- 7.13. I2C Serial Microprocessor Interface
- 7.14. Serial Microprocessor Interface (SPI)
- 7.15. Register Descriptions
- 7.16. DSPLLsim Configuration Software
- 7.1. Clock Multiplication
- 8. High-Speed I/O
- 8.1. Input Clock Buffers
- 8.2. Output Clock Drivers
- 8.3. Typical Scope Shots for SFOUT Options
- 8.4. Crystal/Reference Clock Interfaces (Si5316, Si5319, Si5323, Si5324, Si5326, Si5327, Si5366, Si5368, Si5369, Si5374, and Si5375)
- 8.5. Three-Level (3L) Input Pins (No External Resistors)
- 8.6. Three-Level (3L) Input Pins (With External Resistors)
- 9. Power Supply
- 10. Packages and Ordering Guide
- Appendix A—Narrowband References
- Appendix B—Frequency Plans and Jitter Performance (Si5316, Si5319, Si5323, Si5324, Si5326, Si5327, Si5366, Si5368, Si5369, Si5374, Si5375)
- Appendix C—Typical Phase Noise Plots
- Appendix D—Alarm Structure
- Appendix E—Internal Pullup, Pulldown by Pin
- Appendix F—Typical Performance: Bypass Mode, PSRR, Crosstalk, Output Format Jitter
- Appendix G—Near Integer Ratios
- Appendix H—Jitter Attenuation and Loop BW
- Appendix I—Si5374 and Si5375 PCB Layout Recommendations
- Appendix J—Si5374 and Si5375 Crosstalk
- Document Change List
- Contact Information