TCL Technoly Electronics 06 Bluetooth Module User Manual BM63 Rev2
TCL Technoly Electronics (Huizhou) Co., Ltd. Bluetooth Module BM63 Rev2
Contents
- 1. BM63 user manual
- 2. BM63 User Manual_Rev2
BM63 User Manual_Rev2
BM63SPKA1MGA BM63SPKA1MGA Bluetooth 3.0 Digital Audio Output Module 5F, No.5, Industry E. Rd. VII, Hsinchu Science Park, Hsinchu city 30077, Taiwan, R.O.C Phone: 886-3-577-8385 Fax: 886-3-577-8501 Version:1.2 10/15/2014 BM63SPKA1MGA Product Description The ISSC BM63SPKA1MGA is a highly integrated Bluetooth 3.0 digital audio output module, designed for high data rate, short-range wireless communication in the 2.4 GHz ISM band. With the built-in ISSC Bluetooth stack, profiles and digital audio interface, the ISSC BM63SPKA1MGA can combine the external DSP and codec to provide high performance Bluetooth audio. Features Main Chip: ISSC IS2063GM(Flash version) Bluetooth 3.0 compliant Max. +4dBm Class 2 output power Receiver Sensitivity: GFSK typical -89dBm, π/4 PSK typical -90dBm, 8DPSK typical -83dBm Piconet and Scatter net support CVSD, A-law, -law, mSBC CODEC algorithms for voice applications Support SONY new feature SBC/AAC decode for Bluetooth audio streaming Microphone input and audio line-in support Built-in four language voice prompt (Chinese/English/Spanish/French) Support PCM and I2S digital audio interface Built-in 350mAH Li-ion battery charger HSP 1.2, HFP 1.6, A2DP 1.2, AVRCP 1.5,SPP 1.0 profiles supported Support USB 1.1 DFU and BC1.2/Apple charger detection USB BC1.2 charger detection for DCP/CDP/SDP Apple Charger: 2.5W, 5W, 10W, 12.5W 3.3V operating voltage Built-in program ROM and 64Kb EEPROM 51 pins for SMT module Size: 15mmx32mm Built-in PCB Antenna RoHS compliant ISSC Confidential (Version: 1.2) -2- 10/15/2014 BM63SPKA1MGA Module Pin Out Diagram BM63SPKA1MGA DR0 RFS0 SCLK0 DT0 AOHPR AOHPM AOHPL MICN1 MICP1 MICBIAS AIR AIL P12 P13 RST_N P01 P24 P04 P15 GND P05 P30 P27 P20 P02 P31 P33 P36 DP DM EAN P03 P00 P35 P37 GND LED1 LED2 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 20 21 22 23 24 25 26 27 28 29 10 11 12 13 14 15 16 17 18 19 ANT1 ANT2 ANT3 HCI_RXD HCI_TXD CODEC_VO VDD_IO ADAP_IN BAT_IN AMB_DET SYS_PWR PWR(MFB) LED3 49 50 51 ISSC Confidential (Version: 1.2) -3- 10/15/2014 BM63SPKA1MGA Pin Definition for Flash module Pin No. Pin type Name Description DR0 I2S interface: Digital Left/Right Data from ADC RFS0 I2S interface: DAC Left/Right Clock SCLK0 DT0 AOHPR R-channel analog headphone output AOHPM Headphone common mode output/sense input. AOHPL L-channel analog headphone output MICN1 MIC 1 mono differential analog negative input MICP1 MIC 1 mono differential analog positive input 10 MICBIAS Electric microphone biasing voltage 11 AIR R-channel single-ended analog input 12 AIL 13 I/O P12 14 I/O P13 15 RST_N 16 I/O P01 17 I/O P24 18 I/O P04 L-channel single-ended analog input GPIO, default pull-high input 1. KEY PIN for FT Test 2. EEPROM clock SCL GPIO, default pull-high input 1. KEY PIN for FT Test 2. EEPROM data SDA KEY PIN for FT Test System Reset Pin (Low active) GPIO, default pull-high input BAT_CHK_EN GPIO, default pull-high input 1. KEY PIN for FT Test 2. System Configuration: H: Boot Mode L: Boot Mode with P2_0 low combination GPIO, default pull-high input. 19 I/O P15 20 21 22 23 I2S interface: Bit Clock I2S interface: Digital Left/Right Data to DAC GPIO, default pull-high input KEY PIN for FT Test HCI_RXD 1-bit serial data received from MCU through UART KEY PIN for FT Test HCI_TXD 1-bit serial data transmitted to MCU through UART CODEC_VO 3.1V LDO output for CODEC power VDD_IO I/O power supply input ISSC Confidential (Version: 1.2) -4- 10/15/2014 BM63SPKA1MGA Pin No. Pin type Name Description 24 ADAP_IN 25 BAT_IN 26 AMB_DET ADC analog input 1 27 SYS_PWR 28 PWR(MFB) Multi-Function Push Button key 29 LED3 LED Driver 3 30 LED2 LED Driver 2 31 LED1 LED Driver 1 32 GND Ground Pin 33 I/O P37 34 I/O P35 35 I/O P00 36 I/O P03 37 EAN 38 I/O DM 39 I/O DP 40 I/O P36 41 I/O P33 42 I/O P31 43 I/O P02 44 I/O P20 45 I/O P27 GPIO, default pull-high input GPIO, default pull-high input (LF/ES samples) Default pull-low input (CS/MP samples) Charger Enable GPIO, default pull-high input UART TX_IND signal to wake up MCU GPIO, default pull-high input UART RX_IND signal to wake up BT (Note: HCI_RXD can also be used to wake up BT) Embedded ROM/External Flash enable H: Embedded; L: External Flash USB Differential data bus Data USB Differential data bus Data + GPIO, default pull-high input GPIO, default pull-high input ICHG1 GPIO, default pull-high input ICHG0 GPIO, default pull-high input GPIO, default pull-high input 1. KEY PIN for FT Test 2. System Configuration, H: Application L: Baseband(IBDK Mode) GPIO, default pull-high input 46 I/O P30 GPIO, default pull-high input Power adaptor input Battery input System Power Output ISSC Confidential (Version: 1.2) -5- 10/15/2014 BM63SPKA1MGA Pin No. Pin type Name Description 47 I/O P05 48 GND Line-in Detector GPIO, default pull-high input Charger Status Ground Pin 49 ANT1 Antenna modification point 50 ANT2 Antenna modification point 51 ANT3 Antenna modification point Block Diagram BT 3.0 Transceiver Synthesizer RF Transmitter RF Receiver XTAL + POR I2S/PCM Module BUS PMU BT 3.0 Digital Core Power Switch Interrupts Modem + MAC Battery Charger BUCK LDO ROM LED Driver * 2 MCU Core SAR_ADC DSP Core Misc. PMU logic DSP ROM/RAM External MCU HCI/UART Audio Codec Common RAM Audio Digital Core DMA Controller Stereo DAC Memory Controller Stereo ADC RAM GPIOs (Buttons) Anti-Pop Flash I2C (GPIOs or H/W) ISSC Confidential (Version: 1.2) -6- SPI ULPC 32KHz Buttons EEPROM 10/15/2014 BM63SPKA1MGA Digital Audio Interface Support I2S and PCM interface Sampling Rate : 8K, 16K, 44.1K, 48K, 88.2K, 96K Word Length: 16 bits, 24 bits 4 application modes ISSC Confidential (Version: 1.2) -7- 10/15/2014 BM63SPKA1MGA Mode 1: I2S Master BM63 External CODEC/DSP BCLK ADCLRC DACLRC ADCDAT ADC DACDAT Slave SCLK0 A2DP/SCO RFS0 SCO TFS0 DR0 LineIn ADC DT0 Master DAC 1/fs SCLK0 Left Channel RFS0 DR0/DT0 Bn-1 Bn-2 Right Channel B1 B0 Bn-1 Bn-2 B1 B0 Word Length or Solutions with mic and line-in analog input with I2S audio output Mic for Bluetooth SCO link Line-in for external audio playback(for high SNR requirement) External CODEC/DSP DAC LineIn BM63 BCLK ADCLRC DACLRC ADCDAT DACDAT SCLK0 RFS0 TFS0 DR0 DT0 Slave ISSC Confidential (Version: 1.2) A2DP/SCO SCO Master -8- 10/15/2014 BM63SPKA1MGA Mode 2: I2S Slave BM63 External CODEC/DSP BCLK ADCLRC DACLRC ADCDAT ADC DACDAT Master SCLK0 A2DP/SCO RFS0 SCO TFS0 DR0 LineIn ADC DT0 Slave DAC 1/fs SCLK0 Left Channel RFS0 DR0/DT0 Bn-1 Bn-2 Right Channel B1 B0 Bn-1 Bn-2 B1 B0 Word Length or Solutions with mic and line-in analog input with I2S audio output Mic for Bluetooth SCO link Line-in for external audio playback(for high SNR requirement) External CODEC/DSP DAC LineIn BM63 BCLK ADCLRC DACLRC ADCDAT DACDAT SCLK0 RFS0 TFS0 DR0 DT0 Master ISSC Confidential (Version: 1.2) A2DP/SCO SCO Slave -9- 10/15/2014 BM63SPKA1MGA Mode 3: PCM master BM63 External CODEC/DSP BCLK ADCLRC DACLRC ADCDAT ADC DACDAT Slave SCLK0 A2DP/SCO RFS0 SCO TFS0 DR0 LineIn ADC DT0 Master DAC 1/fs SCLK0 RFS0 Left Channel DR0/DT0 Bn-1 Bn-2 Right Channel B1 B0 Bn-1 Bn-2 B1 B0 Word Length ISSC Confidential (Version: 1.2) - 10 - 10/15/2014 BM63SPKA1MGA Mode 4: PCM slave BM63 External CODEC/DSP BCLK ADCLRC DACLRC ADCDAT ADC DACDAT Master SCLK0 A2DP/SCO RFS0 SCO TFS0 DR0 LineIn ADC DT0 Slave DAC 1/fs SCLK0 RFS0 Left Channel DR0/DT0 Bn-1 Bn-2 Right Channel B1 B0 Bn-1 Bn-2 B1 B0 Word Length ISSC Confidential (Version: 1.2) - 11 - 10/15/2014 BM63SPKA1MGA Outline Dimension (Module Foot print) ISSC Confidential (Version: 1.2) - 12 - 10/15/2014 BM63SPKA1MGA ISSC Confidential (Version: 1.2) - 13 - 10/15/2014 BM63SPKA1MGA Electrical Characteristics Table 1: Absolute Maximum Voltages Min Max +85ºC ESD: Human Body Mode -40ºC ±2KV ESD: Machine Mode ±200V ESD: Charge Device Mode ±200V Core supply voltage VDD_CORE, AVDD_PLL 1.14V 1.26V RF supply voltage VCC_RF 1.22V 1.34V SAR supply voltage AVDD_SAR 1.62V 1.98V Codec supply voltage VDD_AUDIO 2.7V 3.0V I/O voltage VDD_IO 3.6V BK_VDD 4.5V 3V1_VIN 4.5V Storage Temperature Supply voltage BAT_IN 3.0 4.5V ADAP_IN 4.5 7.0V LED 5.1V Power switch 7.0V Table 2: Recommended Operating Conditions Storage Temperature Min Typ Max -10ºC +25ºC +60ºC Core supply voltage VDD_CORE, AVDD_PLL 1.14V 1.2V 1.26V RF supply voltage VCC_RF 1.22V 1.28V 1.34V SAR supply voltage AVDD_SAR 1.62V 1.8V 1.98V Codec supply voltage VDD_AUDIO 2.7V I/O voltage VDD_IO 2.7V BK_VDD 3V 4.3V 3V1_VIN 3V 4.3V BAT_IN 3V 4.3V 4.5V 6.0V Supply voltage ADAP_IN LED 3.0V 4.3V Power switch ISSC Confidential (Version: 1.2) 3.0V 1.8V - 14 - 3.3V 5.0V 6.0V 10/15/2014 BM63SPKA1MGA Table 3: BUCK switching regulator Normal Operation Min Operation Temperature -40 Input Voltage (VIN) 3.0 Output Voltage (VOUT) (ILOAD=70mA, VIN=4V) 1.7 Typ Max 85 Unit ℃ 3.8 4.5 1.80 2.05 Output Voltage Accuracy ±5 Output Voltage Adjustable Step 50 mV/Step Output Adjustment Range -0.1 Output Ripple 10 Average Load Current (ILOAD) Settling Time (start-up time) Conversion efficiency @BAT=3.8V ILOAD = 50mA 88 ILOAD ≥ 10mA (PWM) 70 ILOAD ≥ 10mA (PFM) 80 ILOAD ≥ 250μA (PFM) 65 Switching Frequency PWM/PFM Switching Point Start-up Current Limit mVRMS ms 70 800 KHz by F/W mA 210 mA ILOAD = 10mA 400 mA PWM 1000 PFM 50 30 Output Current (Peak) 40 200 Load Regulation (ILOAD = 10 ~ 100mA) Line Regulation (3.2V < VIN < 4.2V) EN threshold 15 mA 1.2 Quiescent Current 120 EN or VIN to VOUT Start-up Inrush Current +0.25 Logic Low Voltage (VIL) mA mV/mA 0.03 %/V (30) (mV/V) 0.4 Logic High Voltage (VIH) 1.62 10 Shutdown Current <1 - 15 - EN current ISSC Confidential (Version: 1.2) μA nA μA 10/15/2014 BM63SPKA1MGA Table 4: Low Drop Regulation Min Operation Temperature -40 85 Unit ℃ Input Voltage (VIN) 3.0 4.5 Output Voltage (VOUT) (1) VOUT_CODEC (2) VOUT_IO VOUT = 2.9V (2.4~3.4V) 2.9 VOUT = 1.8V (1.3~2.3V) 1.8 Max Accuracy (VIN=3.7V, ILOAD=100mA, 27’C) Output Voltage Adjustable Step 67 Output Adjustment Range Start-up Inrush Current Typ ILOAD=10mA Settling Time (start-up time) EN or VIN to VOUT ±5 100 ±0.5 mV/Step 200 400 mA 250 500 μs Output Current (Average) VOUT 100 mA Output Current (Peak) VOUT 150 mA 300 mV Drop-Out Voltage (ILOAD = maximum output current) Quiescent Current (excluding load, ILOAD < 1mA) Quiescent Current (excluding load, ILOAD < 100μA) Load Regulation (Iload = 0mA to 100mA), ΔVOUT Note: 0.4(mV/mA) * (100mA-0mA)=40mV Line Regulation (VOUT+0.3V0.7V (ADAP_IN=5V) Headroom = 0.3V (ADAP_IN=4.5V) Maximum Battery Fast Charge Current Note: ENX2=1 Headroom > 0.7V (ADAP_IN=5V) Headroom = 0.3V (ADAP_IN=4.5V) mA 170 200 240 mA 160 180 240 mA 330 370 420 mA 180 220 270 mA Minimum Step mA Trickle Charge Voltage Threshold Float Voltage 4.158 Battery Charge Termination Current, % of Fast Charge Current 4.2 4.242 10 Standby Mode (BAT_IN falling from 4.2V) Supply current to charger only Battery Current -1 μA 0.25C mA Battery Recharge Current Note: C Battery Capacity (*1) ISSC Confidential (Version: 1.2) - 17 - mA 10/15/2014 BM63SPKA1MGA Table 6: Audio codec ADC Conditions Temperature Min Typ Max -40 25 85 Unit ℃ 16 Bits 48 KHz Resolution Input sample rate, Fsample 8KHz for MIC 44.1/48KHz for Line-in fin=1KHz Signal to Noise Ratio (SNR @MIC or Line-in mode) 8KHz B/W=20~20KHz (A-weighted) 44.1/ THD+N < 1% 48KHz 90 92 dB 90 92 2.26Vpp input Digital Gain -54 Digital Gain Resolution 4.85 2~6 MIC Boost Gain dB dB 20 PGA Analog Gain -6 26 Analog Gain step Input full-scale at maximum gain (differential) dB dB mVRMS (AVDD=2.8V) Input full-scale at minimum Note: 800 gain (differential) Input VPP=0.8*AVDD 3dB bandwidth Microphone mode input impedance mVRMS (AVDD=2.8V) 20 KHz Input impedance Input capacitance 10 KΩ 20 pF THD+N (microphone input) @30mVRMS input 0.02 THD+N (line input) 0.04 ADC channels Analog supply voltage 2.6 2.8 3.0 Digital supply voltage 1.08 1.2 1.32 42 45 48 dB Crosstalk @line-in mode ISSC Confidential (Version: 1.2) - 18 - 10/15/2014 BM63SPKA1MGA MIC Boost Gain and PGA Gain are controlled by DSP F/W AIL MICP1 MICN1 MIC AMP LINE AMP MIC Boost Gain 0dB or 20dB 1-bit SD ADC Digital Codec DSP Core ADC Digital Gain DSP Digital Gain -54 ~ 4.85dB -96 ~ 0dB in 6dB step Fixed in 0dB now Fixed in 0dB now PGA Analog Gain -6 ~ 26dB in 1dB step System Gain = MIC Boost Gain + PGA Analog Gain + ADC Digital Gain + DSP Digital Gain (1) MIC mode: (a) There are 16 gain levels: 46/43/40/37/34/31/28/25/22/19/16/13/10/7/4/0 dB (b) 46/43/40/37 dB gain levels are normally used for MIC mode (2) Line-in mode: (a) MIC boost gain = 0 dB (b) PGA analog gain = 0 dB (c) ADC digital gain = 0 dB (d) DSP digital gain = 0 dB (e) Gain control for line-in mode is recommended to be done by DAC side Note: For I2S digital audio output, no gain control in BM63 so far and it is controlled by external DAC SCO up link BT RF/MAC Line-in mode UART AIL MICP1 MICN1 External MCU I2C MIC AMP LINE AMP MIC Boost Gain 0dB or 20dB 1-bit SD ADC ADC Digital Gain -54 ~ 4.85dB Fixed in 0dB now PGA Analog Gain -6 ~ 26dB in 1dB step ISSC Confidential (Version: 1.2) Digital Codec - 19 - DSP Core I2S A2DP down link SCO down link External DSP/DAC (YDA174) DSP Digital Gain Digital/Analog -96 ~ 0dB in 6dB step Gain Control Fixed in 0dB now 10/15/2014 BM63SPKA1MGA Table 7: Transmitter section for BDR (25℃) Typ Max Bluetooth specification Unit Maximum RF transmit power 2.0* 5.0 -6 to 4 dBm RF power variation over temperature range with compensation disabled ±2.0 Min RF power control range dB ≥16 18 RF power range control resolution ±0.5 20dB bandwidth for modulated carrier 925 dB dB ≤1000 KHz ACP F = F0±2MHz -42 -40 ≤-20 dBm Note: F0=2441MHz F = F0±3MHz -49 -48 ≤-40 dBm F = F0±>3MHz -57 -53 ≤-40 dBm 175 140<∆f1avg<175 KHz 140 ≥115 KHz ∆f1avg maximum modulation 145 ∆f2max maximum modulation 120 135 ∆f2avg/∆f1avg 0.9 0.95 ICFT 4.5 10.5 ±75 Drift rate 3.3 7.0 ≤20 ≥0.80 KHz KHz/50 us Drift (single slot packet) 12 ≤40 KHz 2nd harmonic content -42 ≤-30 dBm 3rd harmonic content -45 ≤-30 dBm * The transmit power is calibrated in MP. ISSC Confidential (Version: 1.2) - 20 - 10/15/2014 BM63SPKA1MGA Table 8 Transmitter section for EDR (25℃) Min Relative transmit power π/4 DQPSK max carrier frequency stability 8DPSK max carrier frequency stability Typ Max -1.2 Bluetooth specification Unit -4 to 1 dB |ωo| freq. error 2.5 ≤10 for all blocks KHz |ωi| initial freq. error 2.5 ≤75 for all blocks KHz 10 ≤75 for all blocks KHz |ωo| freq. error 2.5 ≤10 for all blocks KHz |ωi| initial freq. error 2.5 ≤75 for all blocks KHz 10 ≤75 for all blocks KHz 12.2 ≤20 ≤30 ≤35 |ωo+ωi| block freq. error |ωo+ωi| block freq. error π/4 DQPSK RMS DEVM modulation accuracy 99% DEVM PASS 8DQPSK modulation accuracy RMS DEVM ≤13 99% DEVM PASS ≤20 ≤25 In-band spurious emissions Note: F0=2441MHz Peak DEVM 25 Peak DEVM 20 F > F0+3MHz <-52 ≤-40 dBm F < F0-3MHz <-53 ≤-40 dBm F = F0-3MHz -46 ≤-40 dBm F = F0-2MHz -34 ≤-20 dBm F = F0-1MHz -34 ≤-26 dBm F = F0+1MHz -37 ≤-26 dBm F = F0+2MHz -34 ≤-20 dBm F = F0+3MHz -46 ≤-40 dBm 100 ≥99 EDR differential phase encoding ISSC Confidential (Version: 1.2) - 21 - 10/15/2014 BM63SPKA1MGA Table 9 Receiver section for BDR (25℃) Frequency (GHz) Sensitivity at 0.1% BER for all basic rate packet types Min Typ 2.402 -89 2.441 -89 2.480 -89 Max Bluetooth specification Unit ≤-70 dBm dBm Maximum received signal at 0.1% BER ≥-20 Continuous power required to block Bluetooth reception (for input power of -67dBm with 0.1% BER) measured at the unbalanced port of the balun 0.030–2.000 -7 -10 2.000-2.400 -10 -27 2.500-3.000 -11 -27 dBm 3.000-12.75 -7 -10 ≤11 dB F = F0+1MHz -6 ≤0 dB F = F0-1MHz -6.5 ≤0 dB F = F0+2MHz -36 ≤-30 dB F = F0-2MHz -28 ≤-9 dB F = F0-3MHz -31 ≤-20 dB F = F0+5MHz -48 ≤-40 dB F = Fimage -28 ≤-9 dB Maximum level of inter-modulation interferers -37 ≥-39 dBm Spurious output level N/A C/I co-channel Adjacent channel selectivity C/I Note: F0=2441MHz ISSC Confidential (Version: 1.2) - 22 - dBm/Hz 10/15/2014 BM63SPKA1MGA Table 10: Receiver section for EDR (25℃) Sensitivity at 0.01% BER Frequency (GHz) Modulation 2.402 π/4 DQPSK -90 2.441 π/4 DQPSK -90 2.480 π/4 DQPSK -90 2.402 8DPSK -83 2.441 8DPSK -83 2.480 8DPSK -82 π/4 DQPSK -10 ≥-20 8DPSK -10 ≥-20 π/4 DQPSK 10 ≤13 dB 8DPSK 16 ≤21 dB π/4 DQPSK -11 ≤0 dB 8DPSK -5 ≤5 dB π/4 DQPSK -8 ≤0 dB 8DPSK -4 ≤5 dB π/4 DQPSK -38.5 ≤-30 dB 8DPSK -33.5 ≤-25 dB π/4 DQPSK -29 ≤-7 dB 8DPSK -25 ≤0 dB -32.5 ≤-20 dB -27 ≤-13 dB π/4 DQPSK -49.5 ≤-40 dB 8DPSK -43.5 ≤-33 dB π/4 DQPSK -29 ≤-7 dB 8DPSK -25 ≤0 dB Maximum received signal at 0.1% BER C/I co-channel at 0.1% BER F= F0+1MHz F= F0-1MHz Adjacent channel selectivity C/I Note: F0=2441MHz F= F0+2MHz F= F0-2MHz F= F0-3MHz F= F0+5MHz F= Fimage Min π/4 DQPSK 8DPSK ISSC Confidential (Version: 1.2) - 23 - Typ Max Bluetooth Unit specification ≤-70 dBm ≤-70 dBm dBm 10/15/2014 BM63SPKA1MGA Reflow profile ISSC Confidential (Version: 1.2) - 24 - 10/15/2014 BM63SPKA1MGA QR code label information Label Size:15±1.5 *6±1.5 mm Device Name: BM63SPKA1MGA MAC ID: xxxxxxxxxx Customer ID Name: Cxxxxx Date Code: 13xx Module Weight (Test condition: module with QR label) TBD ISSC Confidential (Version: 1.2) - 25 - 10/15/2014 BM63SPKA1MGA Storage standard 1. Calculated shelf life in sealed bag: 12 months at < 40 ℃ and <90% relative humidity (RH) 2. After bag is opened, devices that will be subjected to reflow solder or other high temperature process must be Mounted within 168 hours of factory conditions <30℃/60% RH ISSC Confidential (Version: 1.2) - 26 - 10/15/2014 BM63SPKA1MGA Ordering Information Module Device Size Shipment Method 32*15 mm2 Tray Order Number BM63SPKA1MGA Bluetooth 3.0 digital audio Module Note: Minimum Order Quantity is 630pcs Tray. ISSC Confidential (Version: 1.2) - 27 - 10/15/2014 BM63SPKA1MGA Packing Information Tray Dimensions Packing Method ISSC Confidential (Version: 1.2) - 28 - 10/15/2014 BM63SPKA1MGA Inner box: Q’ty (630 Pcs) Dimensions: 36*16*9.5 cm Bar Code Label P/N: Device name C/N: Customer name Lot No: Lot ID Q’ty: Box or Carton Module’s Q’ty Carton: Q’ty (3780 Pcs) Dimensions: 38*35*30 cm ISSC Confidential (Version: 1.2) - 29 - 10/15/2014 1. BM63 module contain PCB antenna 2. The gain of PCB antenna is 2.4dBi 1. Every module has 48 pin 2. Fix BT module on main board by its 8 pin 3. Every pin is fixed on the main board by tin 1.Main board plug in the plastic enclose inside. Main board + SRS‐X55 + FCC statement This device complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) this device may not cause harmful interference, and (2)this device must accept any interference received, including interference that may cause undesired operation. IC statement This device complies with Industry Canada licence-exempt RSS standard(s). Operation is subject to the following two conditions: (1) this device may not cause interference, and (2) this device must accept any interference, including interference that may cause undesired operation of the device Le présent appareil est conforme aux CNR d'Industrie Canada applicables aux appareils radio exempts de licence. L'exploitation est autorisée aux deux conditions suivantes : (1) l'appareil ne doit pas produire de brouillage, et (2) l'utilisateur de l'appareil doit accepter tout brouillage radioélectrique subi, même si le brouillage est susceptible d'en compromettre le fonctionnement.
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