Telecom Design TD1508 TD1508 SIGFOX Modem for ITU Region 2 User Manual TD1508 Datasheet rev1 4
Telecom Design S.A. TD1508 SIGFOX Modem for ITU Region 2 TD1508 Datasheet rev1 4
User manual
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| Document ID | 3057411 |
| Application ID | beKbemfsx49eh27EpcM5hQ== |
| Document Description | User manual |
| Short Term Confidential | No |
| Permanent Confidential | No |
| Supercede | No |
| Document Type | User Manual |
| Display Format | Adobe Acrobat PDF - pdf |
| Filesize | 51.87kB (648398 bits) |
| Date Submitted | 2016-07-11 00:00:00 |
| Date Available | 2016-07-11 00:00:00 |
| Creation Date | 2016-07-05 09:41:18 |
| Producing Software | PDFCreator 2.1.2.0 |
| Document Lastmod | 2016-07-05 09:41:18 |
| Document Title | TD1508 Datasheet rev1.4 |
| Document Creator | PDFCreator 2.1.2.0 |
| Document Author: | Michel Stempin |
TD1508
HIGH-PERFORMANCE, LOW-CURRENT US SIGFOX™ GATEWAY
Features
SIGFOX Ready™
Frequency range = ITU Region 2 ISM Band (Americas, 902~928 MHz)
Receive sensitivity =-127 dBm
Modulation
•
•
(G)FSK, 4(G)FSK, GMSK
OOK
Max output power
•
+24 dBm
Low active radio power consumption
•
•
21 mA RX
Pin Assignments
230 mA TX @ +23 dBm
Power supply = 2.3 to 3.6 V
LGA25 (25.4×12.7×3.81mm, 1”×0.5”×0.15”) Land Grid Array package
25 RF_GND
24 RF
23 RF_GND
Available in several conditioning methods
Applications
GND
GND
Reserved
USR4
DB3
DB2
SDA
SCL
VDD
USR2
GND
SIGFOX™ transceiver (fully certified)
Sensor network
Health monitors
Remote control
Home security and alarm
Telemetry
10
11
22
21
20
19
18
17
16
15
14
13
12
GND
TIM2
ADC0
RX
TX
USR1
USR0
DAC0
RST
USR3
GND
Industrial control
Description
TD next’s TD1508 devices are high performance, low current SIGFOX™
gateways. The combination of a powerful radio transceiver and a state-of-theart ARM Cortex M3 baseband processor achieves extremely high performance
while maintaining ultra-low active and standby current consumption. The
TD1508 device offers an outstanding RF sensitivity of -127 dBm while
providing an exceptional output power of up to +23 dBm with unmatched TX
efficiency. The TD1508 device versatility provides the gateway function from a
local Narrow Band ISM network to the long-distance Ultra Narrow Band
SIGFOX™ network at no additional cost. The broad range of analog and digital
interfaces available in the TD1508 module allows any application to
interconnect easily to the SIGFOX™ network. The LVTTL low-energy UART,
the I2C and SPI buses, the multiple timers with pulse count input/quadrature
decoding/PWM output capabilities, the high-resolution/high-speed ADC and
DAC, along with the numerous GPIOs can control any kind of external sensors
or activators. Featuring an AES encryption engine and a DMA controller, the
powerful 32-bit ARM Cortex-M3 baseband processor can implement highly
complex and secure protocols in an efficient environmental and very low
consumption way.
Rev 1.4 (07/16)
Patents pending
TD1508
Disclaimer: The information in this document is provided in connection with Telecom Design products. No license,
express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in
connection with the sale of Telecom Design products.
TELECOM DESIGN ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR
STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
IN NO EVENT SHALL TELECOM DESIGN BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL,
PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS
OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR
INABILITY TO USE THIS DOCUMENT, EVEN IF TELECOM DESIGN HAS BEEN ADVISED OF THE POSSIBILITY
OF SUCH DAMAGES.
Telecom Design makes no representations or warranties with respect to the accuracy or completeness of the
contents of this document and reserves the right to make changes to specifications and product descriptions at any
time without notice. Telecom Design does not make any commitment to update the information contained herein.
Unless specifically provided otherwise, Telecom Design products are not suitable for, and shall not be used in,
automotive applications. Telecom Design products are not intended, authorized, or warranted for use as
components in applications intended to support or sustain life.
© 2015-2016 Telecom Design S.A. All rights reserved. Telecom Design®, logo and combinations thereof, are
registered trademarks of Telecom Design S.A. SIGFOX™ is a trademark of SigFox S.A. ARM®, the ARM Powered®
logo and others are the registered trademarks or trademarks of ARM Ltd. I2C™ is a trademark of Koninklijke Philips
Electronics NV. Other terms and product names may be trademarks of others.
Rev 1.4 (07/16)
TD1508
DB2
DB3
VDD
GND
Functional Block Diagram
TD1508
32 kHz
XTAL
26 MHz
TCXO
MCU / RF
Debug
I/F
Clock
Mgt
Flash
128K
RAM
32KB
Energy
Mgt
DMA
Ctrl
Watch
dog
AES
2x
USART
GPIO
DAC
Timer
X4
2x I2C
2x
LowPo
w UART
ADC0
DAC0
TIM2
RX
TX
ADC
SDA
SCL
INT
RST
USR0
USR1
USR2
USR3
USR4
32-bit Bus
PA
LNA
MODEM
FIFO
Packet
Handler
PA
LNA
RF
RF GND
ADC
Logic
RF
Front
End
Reserved
ARM Cortex-M3
CPU
Frac-N
PLL
Rev 1.4 (07/16)
TD1508
TABLE OF CONTENTS
Section
Page
Electrical Specifications ................................................................................................... 6
1.1
Definition of Test Conditions.................................................................................................................15
Functional Description .................................................................................................... 16
Module Interface .............................................................................................................. 18
3.1
Low-Power UART (Universal Asynchronous Receiver/Transmitter) .................................................18
3.2
USART (Universal Synchronous/Asynchronous Receiver/Transmitter) ..........................................18
3.3
I2C bus ......................................................................................................................................................18
3.4
Timer/Counter .........................................................................................................................................19
3.5
ADC (Analog to Digital Converter) ........................................................................................................19
3.6
DAC (Digital to Analog Converter) ........................................................................................................19
3.7
GPIO (General Purpose Input/Output) ..................................................................................................20
3.8
RST (Reset)..............................................................................................................................................20
3.9
Debug .......................................................................................................................................................20
3.10
RF Antenna ..............................................................................................................................................20
3.11
VDD & GND ..............................................................................................................................................20
Bootloader ........................................................................................................................ 21
Pin Descriptions .............................................................................................................. 22
I/O alternate functionalities............................................................................................. 24
Ordering Information ....................................................................................................... 26
Package Outline ............................................................................................................... 27
PCB Land Pattern ............................................................................................................ 28
10 Soldering Information ..................................................................................................... 29
10.1
Solder Stencil ..........................................................................................................................................29
10.2
Reflow soldering profile .........................................................................................................................29
11 Board Mounting Recommendation ................................................................................ 30
11.1
Electrical Environment ...........................................................................................................................30
11.2
Power Supply Decoupling .....................................................................................................................30
11.3
RF Layout Considerations .....................................................................................................................30
11.4
Host Antenna Circuit Trace Design ......................................................................................................30
12 Conformity Assessment Issues / FCC Regulatory Notices ......................................... 35
12.1
Modification Statement ..........................................................................................................................35
12.2
Interference Statement ...........................................................................................................................35
Rev 1.4 (07/16)
TD1508
12.3
Wireless Notice .......................................................................................................................................35
12.4
FCC Class B Digital Device Notice........................................................................................................35
12.5
Labelling Requirements for the Host Device .......................................................................................35
Rev 1.4 (07/16)
TD1508
1 Electrical Specifications
Table 1. Absolute Maximum Ratings
Parameter
Value
Units
VDD to GND
0 to +3.6
Instantaneous VRF-peak to GND on RF Pin
-0.3 to +8.0
Sustained VRF-peak to GND on RF Pin
-0.3 to +6.5
Voltage on Digital Inputs
0 to VDD
Voltage on Analog Inputs
0 to VDD
RX Input Power
+10
dBm
Operating Ambient Temperature Range TA
-30 to +75
°C
Storage Temperature Range TSTG
–40 to +125
°C
Maximum soldering Temperature
260
°C
Note:
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
These are stress ratings only and functional operation of the device at or beyond these ratings in the operational
sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability. Power Amplifier may be damaged if switched on without proper load or
termination connected. TX matching network design will influence TX VRF-peak on RF pin. Caution: ESD sensitive
device.
Rev 1.4 (07/16)
TD1508
Table 2- DC Power Supply Characteristics1
Parameter
Supply
Voltage
Range2
Power Saving Mode2
Symbol
VDD
Conditions
Min
2.3
Typ
3.0
Max
3.6
Units
ISleep
1.5
1.8
3.5
µA
Active CPU Mode
Active CPU Mode +
RX Mode Current2
Active CPU Mode +
TX Mode Current2
IActive
IRX
Sleep current using the 32 kHz crystal
@ 25°C
CPU performing active loop @ 14 MHz
2.55
—
3.0
13
3.45
16
mA
mA
—
—
—
—
—
240
230
200
180
135
—
—
—
—
—
mA
mA
mA
mA
mA
ITX_+24
ITX_+23
ITX_+22
ITX_+20
ITX_+15
+24 dBm
+23 dBm
+22 dBm
+20 dBm
+15 dBm
output power, 902.8 MHz, 3.3 V
output power, 902.8 MHz, 3.3 V
output power, 902.8 MHz, 3.3 V
output power, 902.8 MHz, 3.3 V
output power, 902.8 MHz, 3.3 V
Notes:
1. All specifications guaranteed by production test unless otherwise noted. Production test conditions and max
limits are listed in the “Production Test Conditions” section in “1.1. Definition of Test Conditions” on page 5.
2. Guaranteed by qualification. Qualification test conditions are listed in the “Qualification Test Conditions”
section in “1.1. Definition of Test Conditions” on page 14.
Rev 1.4 (07/16)
TD1508
Table 3. Transmitter RF Characteristics1
Parameter
TX Frequency Range2
Modulation Deviation
Range3
Modulation Deviation
Resolution3
Frequency Error2
Symbol
FTX
∆f
Conditions
902.0-928.0 MHz
Min
902.0
—
Typ
—
1.5
Max
928
—
Units
MHz
MHz
FRES
902.0-928.0 MHz
—
28.6
—
Hz
FERR_25
FERR_M20
FERR_55
PAVCDP
902.0-928.0 MHz, 25°C, 3.3 V
902.0-928.0 MHz, -20°C, 3.3 V
902.0-928.0 MHz, 55°C, 3.3 V
-20°C to 55°C, 902.0-928.0 MHz, 3.3 V
—
—
—
—
±2
±3
±3
—
—
—
—
+25
kHz
kHz
kHz
dBm
Average Conducted
Power2
Notes:
3. All specifications guaranteed by production test unless otherwise noted. Production test conditions and
max limits are listed in the “Production Test Conditions” section of “1.1. Definition of Test Conditions” on
page 5.
4. Guaranteed by qualification. Qualification test conditions are listed in the “Qualification Test Conditions”
section in “1.1. Definition of Test Conditions” on page 14.
5. Guaranteed by component specification.
Rev 1.4 (07/16)
TD1508
Table 4. Receiver RF Characteristics1
Parameter
RX Frequency Range2
Synthesizer
Frequency
Resolution3
Blocking2,4
Symbol
FRX
FRES
1MBLOCK
8MBLOCK
Spurious Emissions2
POB_RX1
POB_RX2
RX Sensitivity3
PRX_0.5
PRX_40
PRX_100
PRX_125
PRX_500
PRX_9.6
PRX_1M
PRX_OOK
Conditions
902.0-928.0 MHz
Frequency offset ± 1 MHz, 902.0-928.0
MHz, 25°C, 3.3 V
Frequency offset ± 10 MHz, 902.0-928.0
MHz, 25°C, 3.3 V
From 9 kHz to 1 GHz, 902.0-928.0 MHz,
25°C, 3.3 V
From 1 GHz to 6 GHz, 902.0-928.0
MHz, 25°C, 3.3 V
(BER < 0.1%)
(500 bps, GFSK, BT = 0.5, ∆f = ±250
Hz)
(BER < 0.1%)
(40 kbps, GFSK, BT = 0.5, ∆f = ±20 kHz)
(BER < 0.1%)
(100 kbps, GFSK, BT = 0.5, ∆f = ±50
kHz)
(BER < 0.1%)
(125 kbps, GFSK, BT = 0.5, ∆f = ±62.5
kHz)
(BER < 0.1%)
(500 kbps, GFSK, BT = 0.5, ∆f = ±250
kHz)
(BER < 0.1%)
(9.6 kbps, GFSK, BT = 0.5, ∆f = ±2.4
kHz)
(BER < 0.1%)
(1 Mbps, GFSK, BT = 0.5, ∆f = ±1.25
kHz)
(BER < 0.1%, 4.8 kbps, 350 kHz BW,
OOK, PN15 data)
(BER < 0.1%, 40 kbps, 350 kHz BW,
OOK, PN15 data)
(BER < 0.1%, 120 kbps, 350 kHz BW,
OOK, PN15 data)
Min
902.0
—
Typ
—
28.6
Max
928.0
—
Units
MHz
Hz
—
-79
-68
dB
—
-86
-75
dB
—
-84
—
dBm
—
-70
—
dBm
—
-127
—
dBm
—
-110
—
dBm
—
-104
-102
dBm
—
-105
—
dBm
—
-97
-92
dBm
—
-110
—
dBm
—
-88
—
dBm
—
-108
-104
dBm
—
-101
-97
dB
—
-96
-91
dBm
RSSI Resolution3
RESRSSI
—
±0.5
—
dB
Notes:
1. All specifications guaranteed by production test unless otherwise noted. Production test conditions and
max limits are listed in the “Production Test Conditions” section of “1.1. Definition of Test Conditions” on
page 5.
2. Guaranteed by qualification. Qualification test conditions are listed in the “Qualification Test Conditions”
section in “1.1. Definition of Test Conditions” on page 14.
3. Guaranteed by component specification.
4. The typical blocking values were obtained while seeking for EN 300-220 Category 2 compliance only.
The typical value specified in the component datasheet are -75 dB and -84 dB at 1 and 8 MHz
respectively, with desired reference signal 3 dB above sensitivity, BER = 0.1%, interferer is CW, and
desired is modulated with 2.4 kbps, ∆F = 1.2 kHz GFSK with BT = 0.5, RX channel BW = 4.8 kHz. The
RF component manufacturer provides a reference design featuring a SAW filter which is EN 300-220
Category 1 compliant. Please contact Telecom Design for more information on EN 300-220 Category 1
compliance.
Rev 1.4 (07/16)
TD1508
Table 5. All Digital I/O (except DB1) DC & AC Characteristics1
Parameter
Input Low Voltage2
Input High Voltage2
Output
High
Voltage2
Output Low Voltage2
Input
Leakage
Current2
I/O
Pin
Pull-Up
Resistor2
I/O Pin Pull-Down
Resistor2
Internal ESD Series
Resistor2
Pulse
Width
of
Pulses to be
removed by the
Glitch Suppression
Filter2
Output Fall Time2
Symbol
VIOIL
VIOIH
VIOOH
Min
—
0.7VDD
0.85VDD
Typ
—
—
—
Max
0.3VDD
—
—
Units
0.8VDD
—
—
—
—
0.20VDD
—
—
0.25VDD
—
±0.1
±100
nA
RPU
—
40
—
kΩ
RPD
—
40
—
kΩ
RIOESD
—
200
—
Ω
tIOGLITCH
10
—
—
ns
20+0.1CL
—
250
ns
20+0.1CL
—
250
ns
VIOOL
IIOLEAK
tIOOF
Conditions
Sourcing 6 mA, VDD = 3.0V,
Standard Drive Strength
Sourcing 20 mA, VDD = 3.0V,
High Drive Strength
Sinking 6 mA, VDD=3.0V,
Standard Drive Strength
Sinking 20 mA, VDD=3.0V,
High Drive Strength
High Impedance I/O connected to
GND or VDD
0.5 mA Drive Strength and Load
Capacitance CL = 12.5 to 25 pF
2 mA Drive Strength and Load
Capacitance CL = 350 to 600 pF
VDD = 2.3 to 3.3 V
I/O Pin Hysteresis
VIOHYST
0.1VDD
—
—
(VIOTHR+ - VIOTHR-)2
Notes:
1. All specifications guaranteed by production test unless otherwise noted. Production test conditions and
max limits are listed in the “Production Test Conditions” section of “1.1. Definition of Test Conditions” on
page 14.
2. Guaranteed by component specification.
10
Rev 1.4 (07/16)
TD1508
Table 6. DB1 Digital I/O DC & AC Characteristics1
Parameter
Input Low Voltage2
Input High Voltage2
Output
High
Voltage2
Output Low Voltage2
Symbol
VDB1IL
VDB1IH
VDB1OH
Input
Leakage
Current2
Input Capacitance2
Output Rise Time2
IDB1LEAK
Output Fall Time2
VDB1OL
CDB1IN
tDB1OR
tDB1OF
Conditions
Sourcing 7.4 mA, VDD = 3.3V,
Drive Strength = HL
Sinking 8.5 mA, VDD = 3.3V,
Drive Strength = HL
High Impedance I/O connected to
GND or VDD
0.1VDD to 0.9 VDD, CL= 10 pF,
Drive Strength = LL
0.9VDD to 0.1 VDD, CL= 10 pF,
Drive Strength = LL
Min
—
0.7VDD
0.8VDD
Typ
—
—
—
Max
0.3VDD
—
—
Units
—
—
0.2VDD
—
—
µA
—
—
2.3
—
—
pF
ns
—
—
ns
Notes:
1. All specifications guaranteed by production test unless otherwise noted. Production test conditions and
max limits are listed in the “Production Test Conditions” section of “1.1. Definition of Test Conditions” on
page 14.
2. Guaranteed by component specification.
Rev 1.4 (07/16)
11
TD1508
Table 7. ADC DC & AC Characteristics1
Parameter
Input
Voltage
Range2
Common Mode Input
Range2
Input Current2
Analog
Input
Common
Mode
Rejection
Ratio2
Average
Active
Current2
Current
Consumption
of
Internal
Voltage
Reference2
Input Capacitance2
Input
ON
Resistance2
Input
RC
Filter
Resistance2
Input
RC
Filter/Decoupling
Capacitance2
ADC
Clock
Frequency2
Conversion Time2
Acquisition Time2
Symbol
VADCIN
Conditions
Single Ended
Differential
Min
-VREF/2
Typ
—
—
—
Max
VREF
VREF/2
VDD
Units
IADCIN
CMRRADC
2 pF Sampling Capacitors
—
—
<100
65
—
—
nA
dB
IADC
10 ksps/s 12 bit, Internal
1.25 V Reference, Warmup Mode =
—
67
—
µA
10 ksps/s 12 bit, Internal
1.25 V Reference, Warmup Mode =
—
63
—
µA
10 ksps/s 12 bit, Internal
1.25 V Reference, Warmup Mode =
—
64
—
µA
IADCREF
—
65
—
µA
CADCIN
RADCIN
—
—
—
—
pF
MΩ
RADCFILT
—
10
—
kΩ
CADCFILT
—
250
—
fF
fADCCLK
—
—
13
MHz
6 bit
—
—
10 bit
11
—
—
12 bit
13
—
—
Programmable
—
256
ADC
CLK
Cycles
ADC
CLK
Cycles
ADC
CLK
Cycles
ADC
CLK
Cycles
µs
VADCCMIN
tADCCONV
tADCACQ
Required Acquisition tADCACQVDD3
—
—
Time
for
VDD/3
Reference2
Notes:
1. All specifications guaranteed by production test unless otherwise noted. Production test conditions and
max limits are listed in the “Production Test Conditions” section of “1.1. Definition of Test Conditions” on
page 14.
2. Guaranteed by component specification.
12
Rev 1.4 (07/16)
TD1508
Table 7. ADC DC & AC Characteristics1 (continued)
Parameter
Startup
Time
of
Reference Generator
and ADC Core in
NORMAL Mode2
Startup
Time
of
Reference Generator
and ADC Core in
KEEPADCWARM
Mode2
Offset Voltage2
Symbol
tADCSTART
VADCOFFSET
Conditions
After calibration, single ended
After calibration, differential
Min
—
Typ
Max
—
Units
µs
—
—
µs
0.3
0.3
-1.92
-6.3
—
—
—
Thermometer Output
Gradient2
TGRADAD
CTH
-3.5
—
—
—
Differential
NonLinearity (DNL) 2
Integral
NonLinearity (INL),
End Point Method2
No Missing Codes2
Gain Error Drift2
DNLADC
—
±0.7
—
mV
mV
mV/°C
ADC
Codes
/ °C
LSB
INLADC
—
±1.2
—
LSB
MCADC
GAINED
1.25V Reference
2.5V Reference
1.25V Reference
11.9993
—
—
—
12
0.014
0.014
0.24
—
0.0335
0.035
0.075
2.5V Reference
—
0.24
0.625
bits
%/°C
%/°C
LSB/°
LSB/°
Notes:
1. All specifications guaranteed by production test unless otherwise noted. Production test conditions and max
limits are listed in the “Production Test Conditions” section of “1.1. Definition of Test Conditions” on page
14.
2. Guaranteed by component specification.
3. On the average every ADC will have one missing code, most likely to appear around 2048 +/- n*512 where
n can be a value in the set {-3, -2, -1, 1, 2, 3}. There will be no missing code around 2048, and in spite of
the missing code the ADC will be monotonic at all times so that a response to a slowly increasing input will
always be a slowly increasing output. Around the one code that is missing, the neighbor codes will look
wider in the DNL plot. The spectra will show spurs on the level of -78dBc for a full scale input for chips that
have the missing code issue.
4. Typical numbers given by abs(Mean) / (85 - 25).
5. Max number given by (abs(Mean) + 3x stddev) / (85 - 25).
Rev 1.4 (07/16)
13
TD1508
Table 8. DAC DC & AC Characteristics1
Parameter
Output
Voltage
Range2
Output
Common
Mode
Voltage
Range2
Active
Current
Including
References for 2
Channels 2
Sample Rate2
DAC
Clock
Frequency2
Clock Cycles
Conversion 2
per
Conversion Time2
Settling Time2
Signal to Noise
Ratio (SNR)2
Symbol
VDACOUT
Conditions
VDD voltage reference, Single
Ended
Min
Typ
—
Max
VDD
Units
—
VDD
—
—
—
400
200
17
—
—
—
µA
µA
µA
—
—
—
—
CYCDACCONV
—
500
1000
250
250
—
tDACCONV
tDACSETTLE
SNRDAC
—
—
—
58
—
—
—
ksps
kHz
kHz
kHz
DAC
CLK
Cycles
µs
µs
dB
—
59
—
dB
—
57
—
dB
—
54
—
dB
—
62
—
dB
—
56
—
dB
VDACCM
IDAC
SRDAC
fDAC
Signal to NoisePulse
Distortion
Ratio (SNDR)2
SNDRDAC
Spurious-Free
Dynamic
Range(SFDR)2
SFDRDAC
500 ksps/s 12 bit
500 ksps/s 12 bit
1 ksps/s 12 bit NORMAL
Continuous Mode
Sample/Hold Mode
Sample/Off Mode
500 ksps, 12 bit, single ended,
internal 1.25V reference
500 ksps, 12 bit, single ended,
internal 2.5V reference
500 ksps, 12 bit, single ended,
internal 1.25V reference
500 ksps, 12 bit, single ended,
internal 2.5V reference
500 ksps, 12 bit, single ended,
internal 1.25V reference
500 ksps, 12 bit, single ended,
internal 2.5V reference
After calibration, single ended
Offset Voltage2
VDACOFFSET
—
mV
Differential
Non—
±1
—
LSB
DNLDAC
Linearity2
Integral
NonINLDAC
—
±5
—
LSB
Linearity2
No Missing Codes2
MCDAC
—
12
—
bits
Notes:
1. All specifications guaranteed by production test unless otherwise noted. Production test conditions and
max limits are listed in the “Production Test Conditions” section of “1.1. Definition of Test Conditions” on
page 14.
2. Guaranteed by component specification.
14
Rev 1.4 (07/16)
TD1508
1.1
1.1.1
Definition of Test Conditions
Production Test Conditions:
TA = + 25°C
VDD = +3.3 VDC
Production test schematics (unless noted otherwise)
All RF input and output levels referred to the pins of the TD1508 module
1.1.2
Qualification Test Conditions:
TA = -30 to +75°C (Typical TA = 25°C)
VDD = +2.3 to 3.6 VDC (Typical VDD = 3.0 VDC)
Using TX/RX Split Antenna reference design or production test schematic
All RF input and output levels referred to the pins of the TD1508 module
Rev 1.4 (07/16)
15
TD1508
2 Functional Description
The TD1508 devices are high-performance, low-current, wireless SIGFOX™ gateways. The wide operating voltage
range of 2.3–3.3 V and low current consumption make the TD1508 an ideal solution for battery powered
applications. The TD1508 operates as a time division duplexing (TDD) transceiver where the device alternately
transmits and receives data packets. The device uses a single-conversion mixer to downconvert the 2-level
FSK/GFSK or OOK/ASK modulated receive signal to a low IF frequency. Following a programmable gain amplifier
(PGA) the signal is converted to the digital domain by a high performance ∆Σ ADC allowing filtering, demodulation,
slicing, and packet handling to be performed in the built-in DSP increasing the receiver’s performance and flexibility
versus analog based architectures. The demodulated signal is output to the baseband CPU by reading the 64-byte
RX FIFO.
A single high precision local oscillator (LO) is used for both transmit and receive modes since the transmitter and
receiver do not operate at the same time. The LO is generated by an integrated VCO and ∆Σ Fractional-N PLL
synthesizer. The synthesizer is designed to support configurable data rates from 100bps to 1 Mbps. The TD1508
operates in the frequency bands of 902.0–928.0 MHz with a maximum frequency accuracy step size of 28.6 Hz.
The transmit FSK data is modulated directly into the ∆Σ data stream and can be shaped by a Gaussian low-pass
filter to reduce unwanted spectral content.
The power amplifier (PA) supports output power up to +24 dBm with very high efficiency, consuming only 190 mA
at +23 dBm. The integrated power amplifier can also be used to compensate for the reduced performance of a
lower cost, lower performance antenna or antenna with size constraints due to a small form-factor. The PA is singleended to allow for easy antenna matching and low BOM cost. The PA incorporates automatic ramp-up and rampdown control to reduce unwanted spectral spreading. A highly configurable packet handler allows for autonomous
encoding/decoding of nearly any packet structure.
As both the local Narrow Band ISM network and the long-distance Ultra Narrow Band SIGFOX™ network can be
addressed seamlessly, the TD1508 device provides a natural gateway function at no additional cost. Thus, the
same TD1508 module can be used both for local RF communication with peer modules, and also connect to the
wide-area SIGFOX™ RF network.
The broad range of analog and digital interfaces available in the TD1508 module allows any application to
interconnect easily to the SIGFOX™ network. The LVTTL low-energy UART, the I2C and SPI buses, the multiple
timers with pulse count input/quadrature decoding/PWM output capabilities, the high-resolution/high-speed ADC
and DAC, along with the numerous GPIOs can control any kind of external sensors or activators. Featuring an AES
encryption engine and a DMA controller, the powerful 32-bit ARM Cortex-M3 baseband processor can implement
highly complex and secure protocols in an efficient environmental and very low consumption way. This unique
combination of a powerful 32-bit ARM Cortex-M3 CPU including innovative low energy techniques, short wake-up
time from energy saving modes, and a wide selection of intelligent peripherals allows any application to connect to
the SIGFOX™ network.
The application shown in Figure 1 shows the minimum interconnection required to operate the TD1508 module.
Basically, only the 5 GND, 2 RF_GND, VDD, TX, RX and RF antenna pin connections are necessary. The RST
(reset) pin connection is not mandatory and this pin can be left floating if not used.
A 10 µF/6.3V decoupling capacitor must be added as close as possible to the VDD pin.
The TX/RX pins are LVTTL-compatible and feature internal pull-up resistors.
A 50 Ω matched RF antenna must be connected to the RF pin, with a low-capacitance (< 0.5 pF) TVS diode to
protect the RF input from ESD transients.
The connection of a super-blue LED with series current-limiting resistor of 220 Ω on pin TIM2 is recommended in
order to display the bootloader status at boot time.
16
Rev 1.4 (07/16)
TD1508
50Ω Antenna
RF_GND 25
RF 24
RF_GND 23
Recommended for Bootloader status display
220 Ω
VDD
10 µF/6V3
GND
GND
Reserved
USR4
DB3
DB2
SDA
SCL
9 VDD
10 USR2
11 GND
TD1508
TVS
Diode
GND 22
TIM2 21
ADC0 20
RX 19
TX 18
USR1 17
USR0 16
DAC0 15
RST 14
USR3 13
GND 12
Blue
LED
RX
TX
Figure 1. Typical Application
Note: The TVS diode used for protecting the RF input against ESD must be of low-capacitance (0.5 pF typical) type,
e.g. ESD9R3.3ST5G (On Semiconductor), for example.
Rev 1.4 (07/16)
17
TD1508
3 Module Interface
3.1
Low-Power UART (Universal Asynchronous Receiver/Transmitter)
The TD1508 communicates with the host MCU over a standard asynchronous serial interface consisting of only 2
pins: TX and RX. The TX pin is used to send data from the TD1508 module to the host MCU, and the RX pin is
used to receive data into the TD1508 module coming from the host MCU.
This interface allows two-way UART communication to be performed in low energy modes, using only a few µA
during active communication and only 150 nA when waiting for incoming data.
This serial interface is designed to operate using the following serial protocol parameters:
LVTTL electrical level
9600 bps
8 data bits
1 stop bit
No parity
No hardware/software flow control
This interface operates using LVTTL signal levels to satisfy the common interface to a low power host MCU. If an
EIA RS232-compliant interface voltage level is required, an RS232 level translator circuit must be used. It is also
possible to use a common USB/UART interface chip to connect to an USB bus.
Over this serial interface, the TD1508 device provides a standard Hayes “AT” command set used to control the
module using ASCII readable commands and get answers, as well as to send or receive data.
The list of available commands with their corresponding arguments and return values, a description of their
operation and some examples are detailed into the “TD1508 Reference Manual”.
3.2
USART (Universal Synchronous/Asynchronous Receiver/Transmitter)
The TD1508 provides an interface to an integrated USART capable of both asynchronous (UART and SmartCard)
or synchronous (SPI and I2S) communications. All modes benefit from 2-level buffers with additional separate shift
registers, configurable number of data bits and programmable bit endianess and baudrate.
Asynchronous mode allows both full and half-duplex operation with parity check/generation, parity and framing error
detection and Break condition detection. Synchronous mode is capable of acting as an SPI master or slave,
supporting all 4 SPI clock polarity/phase configurations.
The USART is available on pins USR1, USR2, USR3 and USR4. When not used for timer/counter operation, these
pins can be configured to perform other functions using “AT” configuration commands, please refer to the “TD1508
Reference Manual” for details.
3.3
I2C bus
As a convenience, the TD1508 module is equipped with a popular I2C serial bus controller that enables
communication with a number of external devices using only two I/O pins: SCL and SDA (alternatively, the DB2 and
DB3 pins can be configured as SCL and SDA, resprectively). The SCL pin is used to interface with the I2C clock
signal, and the SDA pin to the I2C data signal, respectively. When not used for I2C bus, these 2 pins can be
configured to perform other functions using “AT” configuration commands, please refer to the “TD1508 Reference
Manual” for details.
The TD1508 module is capable of acting as both a master and a slave, and supports multi-master buses. Both
standard-mode (Sm), fast-mode (Fm) and fast-mode plus (Fm+) speeds are supported, allowing transmission rates
all the way from 10 kbit/s up to 1 Mbit/s. Slave arbitration and timeouts are also provided to allow implementation
18
Rev 1.4 (07/16)
TD1508
of an SMBus compliant system. Both 7-bit and 10-bit addresses are supported, along with extensive error handling
capabilities (clock low/high timeouts, arbitration lost, bus error detection).
The operation of this interface is controlled by the mean of Hayes “AT” commands sent over the UART interface.
To obtain a list of the available commands with their corresponding arguments and return values, a description of
their operation and some examples, please refer to the “TD1508 Reference Manual”.
3.4
Timer/Counter
The TD1508 provides an interface to an integrated low-power timer/counter using the TIM2 pin. This pin can be
configured as either a capture input or a compare/PWM output to the 16-bit internal timer/counter. When not used
for timer/counter operation, this pin can be configured to perform other functions using “AT” configuration
commands, please refer to the “TD1508 Reference Manual” for details.
The low-power timer consists in a counter that can be configured to up-count, down-count, up/down-count
(continuous or one-shot).
The low-power timer also contains 2 output channels, that can be configured as either an output compare or
single/double slope PWM (Pulse-Width Modulation) outputs routed to the TIM2 pin.
The operation of this interface is controlled by the mean of Hayes “AT” commands sent over the UART interface.
To obtain a list of the available commands with their corresponding arguments and return values, a description of
their operation and some examples, please refer to the “TD1508 Reference Manual”.
3.5
ADC (Analog to Digital Converter)
The TD1508 provides an interface to an integrated low-power SAR (Successive Approximation Register) ADC,
capable of a resolution of up to 12 bits at up to 1 Msps or 6 bits at up to 1.86 Msps. The ADC0 pin provides the
external interface to the ADC. When not used for ADC operation, this pin can be configured to perform other
functions using “AT” configuration commands, please refer to the “TD1508 Reference Manual” for details.
Along with the ADC0 analog input channel, the ADC also provides an internal temperature, VDD, and GND input
channel that may be used to get a digital representation of analog temperature or voltage values. It is also possible
to loopback the analog output of the integrated DAC (see section 3.6, “DAC (Digital to Analog Converter)”).
The internal ADC provides an optional input filter consisting of an internal low-pass RC filter or simple internal
decoupling capacitor. The resistance and capacitance values are given in the electrical characteristics for the
device, named RADCFILT and CADCFILT respectively.
The reference voltage used by the ADC can be selected from several sources, including a 1.25 V internal bandgap,
a 2.5 V internal bandgap, VDD, a 5 V internal differential bandgap or unbuffered 2VDD.
Additionally, to achieve higher accuracy, hardware oversampling can be enabled. With oversampling, each selected
input is sampled a number of times, and the results are filtered by a first order accumulate and dump filter to form
the end result. Using 16x oversampling minimum, it is thus possible to achieve result resolution of upt to 16 bits.
The operation of this interface is controlled by the mean of Hayes “AT” commands sent over the UART interface.
To obtain a list of the available commands with their corresponding arguments and return values, a description of
their operation and some examples, please refer to the “TD1508 Reference Manual”.
3.6
DAC (Digital to Analog Converter)
The TD1508 provides an interface to an integrated DAC that can convert a digital value to a fully rail-to-rail analog
output voltage with 12-bit resolution at up to 500 ksps. The DAC may be used for a number of different applications
such as sensor interfaces or sound output. The analog DAC output is routed to the DAC0 pin. When not used for
ADC operation, this pin can be configured to perform other functions using “AT” configuration commands, please
refer to the “TD1508 Reference Manual” for details.
Rev 1.4 (07/16)
19
TD1508
The reference voltage used by the DAC can be selected from several sources, including a 1.25 V internal bandgap,
a 2.5 V internal bandgap, or VDD.
The internal DAC provides support for offset and gain calibration, and contains an automatic sine generation mode
as well as a loopback output to the ADC (see section 3.5, “ADC (Analog to Digital Converter)”).
3.7
GPIO (General Purpose Input/Output)
Apart from the TX and RX UART pins, and the RF pins, all signal pins are available as general-purpose
inputs/outputs. This includes of course the generic USR0, USR1, USR2, US3 and USR4 pins, but also the ADC0,
TIM2, DAC0, SCL, SDA, DB2, DB3 pins when not used for their main function. This configuration can be performed
using “AT” commands, please refer to the “TD1508 Reference Manual” for details.
All the USR0, USR1, USR2, USR3, USR4, ADC0, TIM2, DAC0, SCL, SDA, DB2, DB3 pins can be configured
individually as tristate (default reset state), push-pull, open-drain, with/without pull-up or pull-down resistor, and with
a programmable drive strength (0.5 mA/2 mA/6 mA/20 mA).
When configured as inputs, these pins feature an optional glitch suppression filter and full (rising, falling or both
edges) interrupt with wake-up from low-power mode capabilities. Of course, the pin configuration is retained even
when using these low-power modes.
The operation of the GPIOs is controlled by the mean of Hayes “AT” commands sent over the UART interface. To
obtain a list of the available commands with their corresponding arguments and return values, a description of their
operation and some examples, please refer to the “TD1508 Reference Manual”.
3.8
RST (Reset)
The TD1508 module features an active-low RST pin. This pin is held high by an internal pull-up resistor, so when
not used, this pin can be left floating.
3.9
Debug
The TD1508 module devices include hardware debug support through a 2-pin serial-wire debug interface. The 2
pins DB2 and DB3 are used for this purpose. The DB2 pin is the ARM Cortex-M3’s SWDIO Serial Wire data
Input/Output. This pin is enabled after a reset and has a built in pull-up. The DB3 pin is the ARM Cortex-M3’s
SWCLK Serial Wire Clock input. This pin is enabled after reset and has a built-in pull down. When not used for
debug operation, these 2 pins can be configured to perform other functions using “AT” configuration commands,
please refer to the “TD1508 Reference Manual” for details.
Additionally, the USR0, USR1 or USR2 pins can be used as the ARM Cortex-M3’s SWO Serial Wire viewer Output.
Note that this function is not enabled after reset, and must be enabled by software to be used.
Although the ARM Cortex-M3 supports advanced debugging features, the TD1508 devices only use two port pins
for debugging or programming. The systems internal and external state can be examined with debug extensions
supporting instruction or data access break- and watch points.
For more information on how to enable the debug pin outputs/inputs the reader is referred to Section 28.3.4.1 (p.
457), the ARM Cortex-M3 Technical Reference Manual and the ARM CoreSight™ Technical Reference Manual.
3.10 RF Antenna
The TD1508 support a single-ended RF pin with 50 Ω characteristic impedance for connecting a matchedimpedance external antenna. This pin is physically surrounded by 2 RF GND pins for better noise immunity.
3.11 VDD & GND
The TD1508 provides 5 GND pins and 2 RF_GND pins: all of them must be connected to a good ground plane.
A 10 µF/6.3 V decoupling capacitor should be placed as closed as possible to the single VDD pin.
20
Rev 1.4 (07/16)
TD1508
4 Bootloader
The TD1508 module contains an integrated bootloader which allows reflashing the module firmware either over the
RX/TX UART connection, or over the air using the built-in RF transceiver.
The bootloader is automatically activated upon module reset. Once activated, the bootloader will monitor the
UART/RF activity for a 200 ms period, and detect an incoming update condition.
If the update condition is met, the TD1508 will automatically proceed to flash the new firmware with safe retry
mechanisms, or falls back to normal operation.
Rev 1.4 (07/16)
21
TD1508
5 Pin Descriptions
25 RF_GND
24 RF
23 RF_GND
GND 1
GND 2
Reserved 3
USR4 4
DB3 5
DB2 6
SDA 7
SCL 8
VDD 9
USR2 10
GND 11
22
22
21
20
19
18
17
16
15
14
13
12
GND
TIM2
ADC0
RX
TX
USR1
USR0
DAC0
RST
USR3
GND
Pin
Pin Name
GND
I/O
GND
Description
Connect to PCB ground
GND
GND
Connect to PCB ground
Reserved
I/O
USR4
I/O
DB3
DB2
I/O
SDA
I/O
SCL
I/O
VDD
VDD
10
USR2
I/O
11
GND
GND
12
GND
GND
13
USR3
I/O
14
RST
15
DAC0
I/O
16
USR0
I/O
17
USR1
I/O
Reserved pin – Do not connect
General Purpose Low-Power Digital I/O
This pin may be configured to perform various functions.
SWDCLK (SWD Clock) Signal
This signal provides the SWD clock signal to the integrated TD1508
ARM® CPU.
This pin may be configured to perform various functions.
SWDIO (SWD Data I/O) Signal
This signal provides the SWD programming/debugging signal interface to
the integrated TD1508 ARM® CPU.
This pin may be configured to perform various functions.
General Purpose Low-Power Digital I/O
This pin may be configured to perform various functions, including the I2C
DATA (SDA) function.
General Purpose Low-Power Digital I/O
This pin may be configured to perform various functions, including the I2C
clock (SCL) function.
+2.3 to +3.3 V Supply Voltage Input
The recommended VDD supply voltage is +3.0V.
Connect a 10 µF capacitor as close as possible to this input.
General Purpose Low-Power Digital I/O
This pin may be configured to perform various functions.
Connect to PCB ground
Connect to PCB ground
General Purpose Low-Power Digital I/O
This pin may be configured to perform various functions.
Active Low RESET input signal
This signal resets the TD1508 module to its initial state.
If not used, this signal can be left floating, as it is internally pulled up by
an integrated resistor.
General Purpose Low-Power Digital I/O
This pin may be configured to perform various functions, including the
DAC analog output #0 function.
General Purpose Low-Power Digital I/O
This pin may be configured to perform various functions.
General Purpose Low-Power Digital I/O
Rev 1.4 (07/16)
TD1508
This pin may be configured to perform various functions.
18
TX
19
RX
20
ADC0
I/O
21
TIM2
I/O
22
GND
GND
Low-Power UART Data Transmit Signal
This signal provides the UART data going from the TD1508 module out
to the host application processor.
This signal is internally pulled up by an integrated resistor.
Low-Power UART Data Receive Signal
This signal provides the UART data coming from the host application
processor going to the TD1508 module.
This signal is internally pulled up by an integrated resistor.
General Purpose Low-Power Digital I/O
This pin may be configured to perform various functions, including the
ADC input #6 function.
General Purpose Low-Power Digital I/O
This pin may be configured to perform various functions, including the
timer input capture / output compare #2 function.
Connect to PCB ground
23
RF_GND
GND
Connect to PCB ground
24
RF
RF
25
RF_GND
GND
50 Ω Antenna Connection
Connect to PCB ground
Rev 1.4 (07/16)
23
TD1508
6 I/O alternate functionalities
Pin Name
24
Location
Port
Bit
TX
RX
DAC0
12
USR0
15
USR4
USR2
USR1
USR3
ADC0
Description
LEUART0 TX function.
Analog Comparator ACMP0, channel 6.
I2C bus 1 DATA (SDA) function.
LESENSE Channel 6.
LEUART0 RX function.
Analog Comparator ACMP0, channel 7.
I2C bus 1 CLOCK (SCL) function.
LESENSE Channel 7.
Digital to Analog Converter DAC0 output.
Analog comparator ACMP1, channel 4.
Operational Amplifier 1 alternate output.
UART 1 TX function.
Analog Comparator ACMP1, channel 7.
Digital to Analog Converter DAC0 alternate output.
Operational Amplifier 1 alternate output.
Timer 1 Capture Compare input / output channel 2.
UART 0 RX function.
LESENSE Channel 15.
Debug-interface Serial Wire viewer output.
Note that this function is not enabled after reset, and
must be enabled by software to be used
Analog to digital converter ADC0, input channel number 0.
Operational Amplifier 2 output.
Pulse Counter 2, input 0.
USART1 TX (MOSI) function.
Analog to digital converter ADC0, input channel number 1.
Digital to Analog Converter DAC0 alternate output.
Operational Amplifier 1 alternate output.
Timer 0, input/output 0.
Pulse Counter 2, input 1.
USART1 RX (MISO) function.
Debug-interface Serial Wire viewer output.
Note that this function is not enabled after reset, and
must be enabled by software to be used
Analog to digital converter ADC0, input channel number 2.
Timer 0, input/output 1.
USART1 Clock (CLK) function.
Debug-interface Serial Wire viewer output.
Note that this function is not enabled after reset, and
must be enabled by software to be used
Analog to digital converter ADC0, input channel number 3.
Timer 0, input/output 2.
USART1 Chip Select (CS) function.
Debug-interface Serial Wire viewer output.
Note that this function is not enabled after reset, and
must be enabled by software to be used
Analog to digital converter ADC0, input channel number 6.
Operational Amplifier 1 positive input.
Timer 1, input/output 0.
LETIMER0, output 0.
Pulse Counter 0, input 0.
USART1 RX function.
I2C bus 0 DATA (SDA) function.
LESENSE Alternate Excite Channel 0.
Analog Comparator ACMP0 output.
Rev 1.4 (07/16)
TD1508
TIM2
SDA
SCL
DB3
DB2
LETIMER0, output 1.
Analog to digital converter ADC0, input channel number 7.
Operational Amplifier 1 negative input.
Timer 1, input/output 1.
Pulse Counter 0, input 1.
USART1 TX function.
I2C bus 0 CLOCK (SCL) function.
CMU Clock output number 0.
LESENSE Alternate Excite Channel 1.
Analog Comparator ACMP1 output.
I2C bus 0 DATA (SDA) function.
Timer 3, input/output 0.
Pulse Counter 0, input 0.
I2C bus 0 CLOCK (SCL) function.
Timer 3, input/output 1.
Pulse Counter 0, input 1.
Debug-interface Serial Wire clock input.
Note that this function is enabled to pin out of reset, and has a
built-in pull-down
Timer 0, input/output 0.
LETIMER0 output number 0.
USART1 Clock (CLK) function.
LEUART0 TX function.
I2C bus 0 DATA (SDA) function.
Debug-interface Serial Wire data input / output.
Note that this function is enabled to pin out of reset, and has a
built-in pull up
Timer 0, input/output 1.
LETIMER0 output number 1.
USART1 Chip Select (CS) function.
LEUART0 RX function.
I2C bus 0 CLOCK (SCL) function.
Wake-up from EM4, pin number 3.
Rev 1.4 (07/16)
25
TD1508
7 Ordering Information
Part
Number
TD1508-US
Description
Package Type
US ISM SIGFOX™ gateway 128K
Flash/32KRAM TCXO
LGA25
Pb-free
The TD1508-US ISM SIGFOX™ gateway module is available in several conditionings.
Please contact Telecom Design for more information.
26
Rev 1.4 (07/16)
Operating
Temperature
-30° to +75°C
TD1508
8 Package Outline
Figure 2 illustrates the package details for the TD1508.
Bottom View
Top View
Figure 2. 25-Pin Land Grid Array (LGA)
Notes:
1. All dimensions are shown in millimeters (mm) unless otherwise noted.
Rev 1.4 (07/16)
27
TD1508
9 PCB Land Pattern
Figure 3 illustrates the PB land pattern details for the TD1508.
Figure 3. PCB Land Pattern
Notes:
1. All dimensions are shown in millimeters (mm) unless otherwise noted.
28
Rev 1.4 (07/16)
TD1508
10 Soldering Information
10.1 Solder Stencil
The TD1508 module is designed for RoHS reflow process surface mounting.
For proper module assembly, the solder paste must be applied on the receiving PCB using a metallic stencil with a
recommended 0.150 µm thickness.
10.2 Reflow soldering profile
The recommendation for lead-free solder reflow from IPC/JEDEC J-STD-020D Standard should be followed.
Below are typical reflow soldering profiles for a medium-size board:
Setpoints
Top (°C)
145
155
165
Bottom (°C)
145
155
165
Notes: Conveyor Speed is 65.00 cm / min
175
175
185
185
195
195
230
230
250
250
250
250
Temperature (°C)
200
150
100
50
Z1
Z2
Z3
50
Z4
Z5
Z6
100
150
Z7
Z8
Z9
200
Time (seconds)
250
300
350
Figure 4 - Reflow Soldering Profile
Run
Preheat (s)
40-130°C
Soak Time (s)
130-217°C
Reflow Time
(s) / 217°C
Peak Temp
(°C)
56.04
56.93
55.34
55.92
58.12
122.40
123.72
124.25
122.53
123.38
58.66
59.45
57.34
61.46
57.89
239.00
243.93
239.45
244.00
239.84
Max. Slope1
(°C / s)
(40-130°C)
1.53
1.56
1.54
1.57
1.53
Max. Slope2
(°C / s)
(250-150°C)
-2.78
-2.79
-2.87
-2.77
-2.73
For more information on reflow soldering process profiling, please visit the http://kicthermal.com/ website.
Rev 1.4 (07/16)
29
TD1508
11 Board Mounting Recommendation
11.1 Electrical Environment
The best TD1508 module performances are obtained in a “noise free” environment. Some basic recommendations
must be followed:
•
Noisy electronic components (serial RS232, DC/DC Converter, Display, Ram, bus…) must be placed as far
as possible from the TD1508 module.
CAUTION – A particular attention must be put on switching power supply DC/DC converter, due to switching
frequency that generates spurious into the receiver band, as it can strongly decrease module
performances. Therefore it is recommended to put a metallic shield covering the DC/DC conversion
function.
•
Switching component circuits (especially RS-232/TTL interface circuit power supply) must be decoupled
with a 100 µF low ESR tantalum capacitor. The decoupling capacitor must be placed as close as possible
to the noisy chip.
11.2 Power Supply Decoupling
The power supply of the TD1508 module must be closely decoupled. An LC filter is strongly recommended in case
of a switching DC/DC power supply converter. It must be placed as close as possible to the TD1508 module power
supply pin VDD.
Figure 5- Power supply decoupling
For example:
Symbol
L1
C1
C2
Reference
LQH32CN1R0M33
GRM31CF51A226ZE01
Ceramic CMS 25V
Value
1 µH
22 µF
100 nF
Manufacturer
Murata
Murata
Multiple
11.3 RF Layout Considerations
Basic recommendations must be followed to achieve a good RF layout:
•
•
•
It is recommended to fill all unused PCB area around the module with ground plane
The radio module ground pins must be connected to a solid ground plane
If the ground plane is on the bottom side, a via (metal hole) must be used in front of each ground pad.
Especially pins 23 and 25 (RF_GND) pins should be grounded via several holes to be located right next to
the pins, thus minimizing inductance and preventing mismatch and losses
11.4 Host Antenna Circuit Trace Design
11.4.1 Filter and Matching
This block has 2 purposes:
1. Filter the RF signal, especially harmonic 2 (H2) in transmit mode
2. Match antenna impedance to 50 Ω
30
Rev 1.4 (07/16)
TD1508
Figure 7 - Proposed filter architecture
Figure 6 - Classic filter architecture
The proposed filter network is designed in order to match and filter with optimal performances while requiring the
minimum number of passive components (Figure 7).
For an example antenna featuring a (50+j*40) Ω impedance that must be filtered and matched to the 50 Ω TD1508
module impedance, the tables and graphics below summarize the component values used in order to present a
(50-j*40)Ω impedance at antenna connection with a good H2 rejection and the corresponding transmission gains:
Component
Value
C1
4.7pF
S21 (dB)
@ 868MHz
@1736MHz
L1
9.1nH
C2
4.7pF
L2
8.2nH
C3
3.3pF
Solution 1
-0.37
-23.7
CF1
3pF
CF2
1pF
LF1
8.2nH
CF3
4.7pF
Solution 2
-0.32
-42.8
11.4.2 RF Reference Layout
In order to get the best performance while meeting the electromagnetic interference standard requirements, the RF
trace geometric characteristics and passive component placement must be controlled, such that the RF signal
traces are surrounded by a solid ground plane and the RF signal traces matched to the 50 Ω impedance.
The 2 most common trace topologies used are the Microstrip and Coplanar Waveguide with lower ground
configurations, which are illustrated in figures 8 and 9 below:
Rev 1.4 (07/16)
31
TD1508
Figure 8- Microstrip Line (MS)
Figure 9 Lower Ground Waveguide (CPWG)
The table below provides the recommended trace width to obtain 50 Ω impedance for RF traces on an PCB stack
up (Prepreg) having an εr = 4.5. For the CPWG solution, the proposed clearance between the RF signal and
ground is chosen to be 0.21 mm.
H (µm)
150
250
350
450
550
1200
1600
MS
W (mm)
0.254
0.43
0.6
0.81
2.21
2.97
CPWG (G=0.21mm)
W (mm)
0.254
0.38
0.5
0.59
0.67
0.98
1.07
Figure 10 provides more details on the required trace width relative to the Epoxy thickness (H):
Figure 10- RF trace width relative to Epoxy stackup thickness
As can be observed, the MS trace width is wider and more dependent on H than the CPWG trace width:
However, because of the increasing demand to downscale circuits, the MS solution allows to increase the
component and trace density, see Figure 11 below:
32
Rev 1.4 (07/16)
TD1508
a) Example matching network schematic
b) CPWG layout
c) MS layout
Figure 11- Impact of RF trace topology choice on board real-estate
Nevertheless, several RF matching network components must be connected to GND, creating a parasitic CPWG
area in the MS configuration (e.g. gray area in MS layout). In order to limit the influence of this area, H must be kept
thin (< 400µm), such that the width of MS and CPWG traces are similar and achieve the same 50 Ω impedance (cf.
Figure 10). It is also possible to update the RF signal to GND clearance value (G) for CPWG in order to get the
same impedance with the same trace width between MS and CPWG configurations.
The quality of the ground plane is essential for a good RF performance. Several vias must be placed in order to
connect together (“stitch”) the grounds (top layer and internal layer) and to avoid a parasitic antenna phenomenon
or voltage level differences over the overall circuit ground. However, too numerous via holes may weaken the FR4
mechanical properties, so there should not be too many of them in order to avoid any side effects and decrease the
circuit reliability.
Rev 1.4 (07/16)
33
TD1508
11.4.3 Proposed PCB Stack-Up for combined MS / CPWG RF Traces
The proposed PCB stack-up is depicted in Figure 12. This stack-up is made up of 4 copper layers with a total
thickness of about 1.6 mm. The core FR4 thickness can be modified in order to reach a total thickness of 1.2 mm.
Figure 12- Proposed PCB stack-up
The width (W) of RF traces is fixed to 0.6 mm (matching 0402 component footprints), with a clearance (G) of 0.35
mm. These values allow to cancel the 0402 footprint impact on the RF matching. The table below provides the
expected minimum and maximum RF trace impedances relative to the PREPREG tolerances:
2xPREPREG 7628
(-40 µm) => 350 µm
(+0 µm) => 390 µm
(+40 µm) => 430 µm
34
Impedance of MS (Ω)
51.3
54.6
57.6
Rev 1.4 (07/16)
Impedance of CPWG (Ω)
48.9
51.3
53.3
TD1508
12 Conformity Assessment Issues / FCC Regulatory Notices
12.1 Modification Statement
Telecom Design S.A. does not approve any changes or modifications to this device by the user. Any changes or
modifications could void the user’s authority to operate the equipment.
12.2 Interference Statement
This device complies with Part 15 of the FCC Rules.
Operation is subject to the following two conditions:
(1) This device may not cause harmful interference, and
(2) This device must accept any interference received, including interference that may cause undesired
operation.
12.3 Wireless Notice
This equipment complies with FCC radiation exposure limits set forth for an uncontrolled environment. This
equipment should be installed and operated with a minimum distance of 20 cm between the radiator and your
body.
Antenna gain and type must be:
Type
λ/2 dipole antenna
Maximum Gain
2 dBi
This transmitter must not be co-located or operating in conjunction with any other antenna or transmitter.
12.4 FCC Class B Digital Device Notice
This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to Part 15
of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a
residential installation. This equipment generates, uses and can radiate radio frequency energy and, if not installed
and used in accordance with the instructions, may cause harmful interference to radio communications. However,
there is no guarantee that interference will not occur in a particular installation. If this equipment does cause harmful
interference to radio or television reception, which can be determined by turning the equipment off and on, the user
is encouraged to try to correct the interference by one or more of the following measures:
•
•
•
Reorient or relocate the receiving antenna.
Increase the separation between the equipment and receiver.
Connect the equipment into an outlet on a circuit different from that to which the receiver is connected.
Consult the dealer or an experienced radio/TV technician for help.
12.5 Labelling Requirements for the Host Device
The host device shall be properly labelled to identify the modules within the host device. The certification label of
the module shall be clearly visible at all times when installed in the host device, otherwise the host device must be
labelled to display the FCC ID of the module, preceded by the words "Contains transmitter module", or the word
"Contains", or similar wording expressing the same meaning, as follows:
Contains FCC ID: 2AGMK-TD1508
Rev 1.4 (07/16)
35
TD1508
D OCUMENT C HANGE L IST
Revision 1.0
First Release
Revision 1.1
Remove the 25dBm output configuration
Change TX power consumption
Revision 1.2
Added FCC and IC warning statements
Revision 1.3
Removed IC warning statements
Added Board Mounting Recommendation
Added Conformity Assessment Issues / FCC Regulatory Notices
Revision 1.4
Corrected minimal distance unit
36
Rev 1.4 (07/16)
TD1508
N OTES :
Rev 1.4 (07/16)
37
TD1508
C ONTACT I NFORMATION
Telecom Design S.A.
Zone Actipolis II — 2 bis rue Nully de Harcourt
33610 CANEJAN, France
Tel: +33 5 57 35 63 70
Fax: +33 5 57 35 63 71
Please visit the Telecom Design web page:
http://www.telecomdesign.fr/
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice.
Telecom Design assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use
of information included herein. Additionally, Telecom Design assumes no responsibility for the functioning of undescribed features or parameters.
Telecom Design reserves the right to make changes without further notice. Telecom Design makes no warranty, representation or guarantee
regarding the suitability of its products for any particular purpose, nor does Telecom Design assume any liability arising out of the application or
use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages.
Telecom Design products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other
application in which the failure of the Telecom Design product could create a situation where personal injury or death may occur. Should Buyer
purchase or use Telecom Design products for any such unintended or unauthorized application, Buyer shall indemnify and hold Telecom Design
harmless against all claims and damages.
Telecom Design is a trademark of Telecom Design S.A.
SIGFOX™ is a trademark of SigFox S.A.
Other products or brand names mentioned herein are trademarks or registered trademarks of their respective holders.
38
Rev 1.4 (07/16)
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