Telit Communications S p A UE910N3 3G Module User Manual 11

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UE910 3G HARDWARE USER GUIDE 1vv0301171 Rev.3 • 2015-04-17 1 of 78

UE910 3G HARDWARE USER

GUIDE

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APPLICABILITY TABLE

PRODUCTS

UE910-N3G

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DISCLAIMER

LEGAL NOTICE

These Specifications are general guidelines pertaining to product selection and application and may

not be appropriate for your particular project. Telit (which hereinafter shall include, its agents, licensors

and affiliated companies) makes no representation as to the particular products identified in this

document and makes no endorsement of any product. Telit disclaims any warranties, expressed or

implied, relating to these specifications, including without limitation, warranties or merchantability,

fitness for a particular purpose or satisfactory quality. Without limitation, Telit reserves the right to

make changes to any products described herein and to remove any product, without notice.

It is possible that this document may contain references to, or information about Telit products,

services and programs, that are not available in your region. Such references or information must not

be construed to mean that Telit intends to make available such products, services and programs in

your area.

USE AND INTELLECTUAL PROPERTY RIGHTS

These Specifications (and the products and services contained herein) are proprietary to Telit and its

licensors and constitute the intellectual property of Telit (and its licensors). All title and intellectual

property rights in and to the Specifications (and the products and services contained herein) is owned

exclusively by Telit and its licensors. Other than as expressly set forth herein, no license or other

rights in or to the Specifications and intellectual property rights related thereto are granted to you.

Nothing in these Specifications shall, or shall be deemed to, convey license or any other right under

Telit’s patents, copyright, mask work or other intellectual property rights or the rights of others.

You may not, without the express written permission of Telit: (i) copy, reproduce, create derivative

works of, reverse engineer, disassemble, decompile, distribute, merge or modify in any manner these

Specifications or the products and components described herein; (ii) separate any component part of

the products described herein, or separately use any component part thereof on any equipment,

machinery, hardware or system; (iii) remove or destroy any proprietary marking or legends placed

upon or contained within the products or their components or these Specifications; (iv) develop

methods to enable unauthorized parties to use the products or their components; and (v) attempt to

reconstruct or discover any source code, underlying ideas, algorithms, file formats or programming or

interoperability interfaces of the products or their components by any means whatsoever. No part of

these Specifications or any products or components described herein may be reproduced, transmitted,

transcribed, stored in a retrieval system, or translated into any language or computer language, in any

form or by any means, without the prior express written permission of Telit.

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HIGH RISK MATERIALS

Components, units, or third-party products contained or used with the products described herein

are NOT fault-tolerant and are NOT designed, manufactured, or intended for use as on-line control

equipment in the following hazardous environments requiring fail-safe controls: the operation of

Nuclear Facilities, Aircraft Navigation or Aircraft Communication Systems, Air Traffic Control, Life

Support, or Weapons Systems (“High Risk Activities"). Telit, its licensors and its supplier(s) specifically

disclaim any expressed or implied warranty of fitness for such High Risk Activities.

TRADEMARKS

You may not and may not allow others to use Telit or its third party licensors’ trademarks. To the

extent that any portion of the products, components and any accompanying documents contain

proprietary and confidential notices or legends, you will not remove such notices or legends.

THIRD PARTY RIGHTS

The software may include Third Party Right software. In this case you agree to comply with all terms

and conditions imposed on you in respect of such separate software. In addition to Third Party Terms,

the disclaimer of warranty and limitation of liability provisions in this License shall apply to the Third

Party Right software.

TELIT HEREBY DISCLAIMS ANY AND ALL WARRANTIES EXPRESS OR IMPLIED FROM ANY

THIRD PARTIES REGARDING ANY SEPARATE FILES, ANY THIRD PARTY MATERIALS

INCLUDED IN THE SOFTWARE, ANY THIRD PARTY MATERIALS FROM WHICH THE SOFTWARE

IS DERIVED (COLLECTIVELY “OTHER CODE”), AND THE USE OF ANY OR ALL THE OTHER

CODE IN CONNECTION WITH THE SOFTWARE, INCLUDING (WITHOUT LIMITATION) ANY

WARRANTIES OF SATISFACTORY QUALITY OR FITNESS FOR A PARTICULAR PURPOSE.

NO THIRD PARTY LICENSORS OF OTHER CODE SHALL HAVE ANY LIABILITY FOR ANY

DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES

(INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND WHETHER

MADE UNDER CONTRACT, TORT OR OTHER LEGAL THEORY, ARISING IN ANY WAY OUT OF

THE USE OR DISTRIBUTION OF THE OTHER CODE OR THE EXERCISE OF ANY RIGHTS

GRANTED UNDER EITHER OR BOTH THIS LICENSE AND THE LEGAL TERMS APPLICABLE TO

ANY SEPARATE FILES, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.

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CONTENTS

1 Introduction 8

1.1 Scope 8

1.2 Audience 8

1.3 Contact Information, Support 8

1.4 List of acronyms 9

1.5 Text Conventions 10

1.6. Related Documents 10

2 Overview 11

3 Pins Allocation 12

3.1 Pin-out 12

LGA Pads Layout 19

4 Power Supply 20

4.1 Power Supply Requirements 20

4.2 Power Consumption 21

4.3 General Design Rules 22

Electrical Design Guidelines 22

+5V Source Power Supply Design Guidelines 22

+ 12V input Source Power Supply Design Guidelines 23

Battery Source Power Supply Design Guidelines 24

Thermal Design Guidelines 25

Power Supply PCB layout Guidelines 26

4.4 RTC Bypass out 27

4.5 VAUX Power Output 27

5 Digital Section 28

5.1 Logic Levels Specification 28

5.2 Power on 29

5.3 Power off 34

5.4 Unconditional Shutdown 36

5.5 Communication ports 39

USB 2.0 HS 39

USB HSIC 40

SPI 41

SPI Connections 41

Serial Ports 42

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MODEM SERIAL PORT 1 (USIF0) 42

MODEM SERIAL PORT 2 (USIF1) 44

RS232 LEVEL TRANSLATION 45

5.6 General Purpose I/O 46

Using a GPIO as INPUT 47

Using a GPIO as OUTPUT 47

Indication of network service availability 48

5.7 External SIM Holder 49

5.8 ADC Converter 49

6 RF Section 50

6.1 Bands Variants 50

6.2 TX Output Power 50

6.3 RX Sensitivity 50

6.4 Antenna Requirements 51

PCB design guidelines 51

PCB Guidelines in case of FCC Certification 53

Transmission line design 53

Transmission Line Measurements 54

Antenna Installation Guidelines 56

7 Audio Section 57

7.1 Overview 57

7.2 Analog Voice Interface 57

MIC connection 58

LINE IN Connection 60

EAR Connection 61

7.3 Digital Voice Interface 62

CODEC Examples 62

8 Mechanical Design 63

8.1 Drawing 63

9 Application Design 64

9.1 Footprint 64

9.2 PCB pad design 65

9.3 PCB pad dimensions 65

9.4 Stencil 67

9.5 Solder paste 67

9.6 Solder reflow 67

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10 Packaging 69

10.1 Tray 69

10.2 Reel 70

Carrier Tape Detail 70

Reel Detail 71

Reel Box Detail 72

10.3 Moisture sensitivity 72

11 SAFETY RECOMMANDATIONS 73

12 FCC/IC Regulatory notices 74

13 Document History 77

13.1 Revisions 77

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1 INTRODUCTION

1.1 Scope

The aim of this document is the description of some hardware solutions useful for developing a product

with the Telit UE910 module.

1.2 Audience

This document is intended for Telit customers, who are integrators, about to implement their applications

using our UE910 modules.

1.3 Contact Information, Support

For general contact, technical support services, technical questions and report documentation errors

contact Telit Technical Support at:

TS-EMEA@telit.com

TS-AMERICAS@telit.com

TS-APAC@telit.com

Alternatively, use:

http://www.telit.com/support

For detailed information about where you can buy the Telit modules or for recommendations on

accessories and components visit:

http://www.telit.com

Our aim is to make this guide as helpful as possible. Keep us informed of your comments and

suggestions for improvements.

Telit appreciates feedback from the users of our information.

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1.4 List of acronyms

Acronym

Description

TTSC

Telit Technical Support Centre

USB

Universal Serial Bus

High Speed

DTE

Data Terminal Equipment

UMTS

Universal Mobile Telecommunication System

WCDMA

Wideband Code Division Multiple Access

HSDPA

High Speed Downlink Packet Access

HSUPA

High Speed Uplink Packet Access

UART

Universal Asynchronous Receiver Transmitter

HSIC

High Speed Inter Chip

SIM

Subscriber Identification Module

SPI

Serial Peripheral Interface

ADC

Analog – Digital Converter

DAC

Digital – Analog Converter

I/O

Input Output

GPIO

General Purpose Input Output

CMOS

Complementary Metal – Oxide Semiconductor

MOSI

Master Output – Slave Input

MISO

Master Input – Slave Output

CLK

Clock

MRDY

Master Ready

SRDY

Slave Ready

Chip Select

RTC

Real Time Clock

PCB

Printed Circuit Board

ESR

Equivalent Series Resistance

VSWR

Voltage Standing Wave Radio

VNA

Vector Network Analyzer

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1.5 Text Conventions

Danger – This information MUST be followed or catastrophic equipment failure

or bodily injury may occur.

Caution or Warning – Alerts the user to important points about integrating the

module, if these points are not followed, the module and end user equipment

may fail or malfunction.

Tip or Information – Provides advice and suggestions that may be useful when

integrating the module.

All dates are in ISO 8601 format, i.e. YYYY-MM-DD.

1.6. Related Documents

 Digital Voice Interface Application Note 80000NT10050A

 SPI Port Application Note 80000NT10053A

 SIM Holder Design Guides 80000NT10001a

 USB HSIC Port Application Note 80000NT10071A

 AT Commands Reference Guide 80378ST10091A

 Telit EVK2 User Guide 1vv0300704

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2 OVERVIEW

The aim of this document is the description of some hardware solutions useful for developing a product

with the Telit UE910 3G module.

In this document all the basic functions of a mobile phone will be taken into account; for each one of

them a proper hardware solution will be suggested and eventually the wrong solutions and common

errors to be avoided will be evidenced. Obviously this document cannot embrace the whole hardware

solutions and products that may be designed. The wrong solutions to be avoided shall be considered

as mandatory, while the suggested hardware configurations shall not be considered mandatory, instead

the information given shall be used as a guide and a starting point for properly developing your product

with the Telit UE910 module. For further hardware details that may not be explained in this document

refer to the Telit UE910 Product Description document where all the hardware information is reported.

NOTICE:

(EN) The integration of the WCDMA UE910 cellular module within user

application shall be done according to the design rules described in this

manual.

(IT) L’integrazione del modulo cellulare WCDMA UE910 all’interno

dell’applicazione dell’utente dovrà rispettare le indicazioni progettuali descritte

in questo manuale.

(DE) Die Integration des UE910 WCDMA Mobilfunk-Moduls in ein Gerät muß

gemäß der in diesem Dokument beschriebenen Kunstruktionsregeln erfolgen.

(SL) Integracija WCDMA UE910 modula v uporabniški aplikaciji bo morala

upoštevati projektna navodila, opisana v tem priročniku.

(SP) La utilización del modulo WCDMA UE910 debe ser conforme a los usos

para los cuales ha sido deseñado descritos en este manual del usuario.

(FR) L’intégration du module cellulaire WCDMA UE910 dans l’application de

l’utilisateur sera faite selon les règles de conception décrites dans ce manuel.

(HE)

The information presented in this document is believed to be accurate and reliable. However, no

responsibility is assumed by Telit Communications S.p.A. for its use, nor any infringement of patents or

other rights of third parties which may result from its use. No license is granted by implication or

otherwise under any patent rights of Telit Communications S.p.A. other than for circuitry embodied in

Telit products. This document is subject to change without notice.

UE910

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3 PINS ALLOCATION

3.1 Pin-out

Signal

I/O

Function

Type

Comment

USB HS 2.0 COMMUNICATION PORT

B15

USB_D+

I/O

USB differential Data (+)

C15

USB_D-

I/O

USB differential Data (-)

A13

VUSB

Power sense for the

internal USB transceiver.

Asynchronous Serial Port (USIF0) - Prog. / Data + HW Flow Control

N15

C103/TXD

Serial data input from DTE

CMOS 1.8V

M15

C104/RXD

Serial data output to DTE

CMOS 1.8V

M14

C108/DTR

Input for (DTR) from DTE

CMOS 1.8V

L14

C105/RTS

Input for Request to send

signal (RTS) from DTE

CMOS 1.8V

P15

C106/CTS

Output for Clear to Send

signal (CTS) to DTE

CMOS 1.8V

N14

C109/DCD

Output for (DCD) to DTE

CMOS 1.8V

P14

C107/DSR

Output for (DSR) to DTE

CMOS 1.8V

R14

C125/RING

Output for Ring (RI) to

DTE

CMOS 1.8V

Asynchronous Auxiliary Serial Port (USIF1)

D15

TX_AUX

Auxiliary UART (TX Data

to DTE)

CMOS 1.8V

E15

RX_AUX

Auxiliary UART (RX Data

from DTE)

CMOS 1.8V

USB HSIC

A12

HSIC_USB_DATA

I/O

USB HSIC data signal

CMOS 1.2V

A11

HSIC_USB_STRB

I/O

USB HSIC strobe signal

CMOS 1.2V

H15

HSIC_SLAVE_WAKEUP

Slave Wake Up

CMOS 1.8V

Shared with SPI_MRDY

F15

HSIC_HOST_WAKEUP

Host Wake Up

CMOS 1.8V

Shared with SPI CLK

K15

HSIC_SUSPEND_REQUEST

Slave Suspend Request

CMOS 1.8V

Shared with GPIO08

J15

HSIC_HOST_ACTIVE

Active Host Indication

CMOS 1.8V

Shared with SPI_SRDY

SIM card interface

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SIMCLK

External SIM signal –

Clock

1.8 / 3V

SIMRST

External SIM signal –

Reset

1.8 / 3V

SIMIO

I/O

External SIM signal – Data

I/O

1.8 / 3V

SIMIN

External SIM signal –

Presence (active low)

CMOS 1.8

SIMVCC

External SIM signal –

Power supply for the SIM

1.8 / 3V

Analog Audio

EAR+

Analog Audio Interface

(EAR+)

EAR-

Analog Audio Interface

(EAR-)

MIC+

Analog Audio Interface

(MIC+)

MIC-

Analog Audio Interface

(MIC-)

Digital Voice Interface (DVI)

DVI_WA0

I/O

Digital Audio Interface

(WA0)

CMOS 1.8V

DVI_RX

I/O

Digital Audio Interface

(RX)

CMOS 1.8V

DVI_TX

I/O

Digital Audio Interface

(TX)

CMOS 1.8V

DVI_CLK

I/O

Digital Audio Interface

(CLK)

CMOS 1.8V

SPI

D15

SPI_MOSI

SPI MOSI

CMOS 1.8V

Shared with TX_AUX

E15

SPI_MISO

CMOS 1.8V

Shared with RX_AUX

F15

SPI_CLK

SPI Clock

CMOS 1.8V

H15

SPI_MRDY

CMOS 1.8V

J15

SPI_SRDY

CMOS 1.8V

DIGITAL IO

GPIO_01

I/O

GPIO_01 /STAT LED

CMOS 1.8V

Alternate Function STAT LED

GPIO_02

I/O

GPIO_02

CMOS 1.8V

C10

GPIO_03

I/O

GPIO_03

CMOS 1.8V

C11

GPIO_04

I/O

GPIO_04

CMOS 1.8V

B14

GPIO_05

I/O

GPIO_05

CMOS 1.8V

C12

GPIO_06

I/O

GPIO_06

CMOS 1.8V

C13

GPIO_07

I/O

GPIO_07

CMOS 1.8V

K15

GPIO_08

I/O

GPIO_08

CMOS 1.8V

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L15

GPIO_09

I/O

GPIO_09

CMOS 1.8V

G15

GPIO_10

I/O

GPIO_10

CMOS 1.8V

ADC

ADC_IN1

Analog / Digital converter

input

A/D

Accepted values 0 to 1.2V DC

RF SECTION

ANTENNA

I/O

WCDMA Antenna

(50 ohm)

Miscellaneous Functions

R13

HW_SHUTDOWN*

HW Unconditional

Shutdown

CMOS 1.8V

Active low

R12

ON_OFF*

Input command for power

CMOS 1.8V

Active low

C14

VRTC

VRTC Backup capacitor

Power

backup for the embedded RTC

supply

R11

VAUX/PWRMON

Supply Output for external

accessories / Power ON

Monitor

1.8V

Power Supply

VBATT

Main power supply

(Baseband)

Power

VBATT

Main power supply

(Baseband)

Power

VBATT_PA

Main power supply (Radio

PA)

Power

VBATT_PA

Main power supply (Radio

PA)

Power

VBATT_PA

Main power supply (Radio

PA)

Power

VBATT_PA

Main power supply (Radio

PA)

Power

GND

Ground

Power

GND

Ground

Power

GND

Ground

Power

GND

Ground

Power

GND

Ground

Power

GND

Ground

Power

GND

Ground

Power

GND

Ground

Power

GND

Ground

Power

GND

Ground

Power

GND

Ground

Power

GND

Ground

Power

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GND

Ground

Power

GND

Ground

Power

GND

Ground

Power

GND

Ground

Power

GND

Ground

Power

GND

Ground

Power

GND

Ground

Power

GND

Ground

Power

GND

Ground

Power

GND

Ground

Power

GND

Ground

Power

GND

Ground

Power

GND

Ground

Power

GND

Ground

Power

GND

Ground

Power

GND

Ground

Power

GND

Ground

Power

GND

Ground

Power

GND

Ground

Power

GND

Ground

Power

P10

GND

Ground

Power

R10

GND

Ground

Power

M12

GND

Ground

Power

B13

GND

Ground

Power

P13

GND

Ground

Power

E14

GND

Ground

Power

RESERVED

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RESERVED

A10

RESERVED

N10

RESERVED

N11

RESERVED

B12

RESERVED

D12

RESERVED

N12

RESERVED

P12

RESERVED

F14

RESERVED

G14

RESERVED

H14

RESERVED

J14

RESERVED

K14

RESERVED

N13

RESERVED

L13

RESERVED

J13

RESERVED

M13

RESERVED

K13

RESERVED

H13

RESERVED

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WARNING:

Reserved pins must not be connected

G13

RESERVED

F13

RESERVED

B11

RESERVED

B10

RESERVED

D14

RESERVED

A14

RESERVED

D13

RESERVED

E13

RESERVED

P11

RESERVED

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If not used, almost all pins should be left disconnected. The only exceptions are the following pins:

PAD

Signal

Note

M1,M2,N1,N2,P1,P2

VBATT & VBATT_PA

E1, G1, H1, J1, L1, A2, E2, F2, G2, H2

J2,K2,L2,R2,M3,N3,P3,R3,D4,M4,

N4,P4,R4,N5,P5,R5,N6,P6,R6,P8,

R8,P9,P10,R10,M12,B13,P13,E14

GND

R12

ON/OFF*

R13

HW_SHUTDOWN*

B15

USB_D+

If not used should be connected to a

Test Point or an USB connector

C15

USB_D-

If not used should be connected to a

Test Point or an USB connector

A13

VUSB

If not used should be connected to a

Test Point or an USB connector

N15

C103/TXD

If not used should be connected to a

Test Point

M15

C104/RXD

If not used should be connected to a

Test Point

L14

C105/RTS

If the flow control is not used it should

be connected to GND

P15

C106/CTS

If not used should be connected to a

Test Point

D15

TXD_AUX

If not used should be connected to a

Test Point

E15

RXD_AUX

If not used should be connected to a

Test Point

MAIN ANTENNA

SIMCLK

SIMRST

SIMIO

SIMIN

RTS pin should be connected to the GND (on the module side) if flow control is not used.

The above pins are also necessary to debug the application when the module is assembled on it so

we recommend connecting them also to dedicated test point.

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LGA Pads Layout

TOP VIEW

RES

GND

RES

GND

ANT

GND

VBATT

_PA

VBATT

_PA

GND

SPK+

RES

GND

VBATT

_PA

VBATT

_PA

GND

SIMVC

SPK -

RES

GND

SIMIN

MIC+

RES

GND

SIMIO

MIC -

RES

GND

SIMCL

DVI_RX

RES

GND

SIMRS

DVI_TX

RES

DVI_CLK

GPIO_0

RES

GND

RES

DVI_WA

GPIO_0

RES

GND

RES

GPIO_0

RES

GND

HSIC_

USB_S

TRB

RES

GPIO_0

RES

VAUX/

PWRM

HSIC_

USB_D

ATA

RES

GPIO_0

RES

GND

RES

ON_OF

VUSB

GND

GPIO_0

RES

GND

HW_SH

UTDO

WN*

RES

GPIO_05

VRTC

RES

GND

RES

C105/R

C108/D

C109/D

C107/D

C125/R

ING

USB_D+

USB_D

TX AUX

AUX

SPI_CL

GPIO_1

SPI_M

RDY

SPI_SR

GPIO_0

C104/R

C103/T

C106/C

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4 POWER SUPPLY

The power supply circuitry and board layout are a very important part in the full product design and

they strongly reflect on the product overall performances, hence read carefully the requirements and

the guidelines that will follow for a proper design.

4.1 Power Supply Requirements

The external power supply must be connected to VBATT & VBATT_PA signals and must fulfil the

following requirements:

Power Supply

Value

Nominal Supply Voltage

3.8V

Normal Operating Voltage Range

3.40 V÷ 4.20 V

Extended Operating Voltage Range

3.10 V÷ 4.50 V

NOTE:

The Operating Voltage Range MUST never be exceeded; care must be taken

when designing the application’s power supply section to avoid having an

excessive voltage drop.

If the voltage drop is exceeding the limits it could cause a Power Off of the

module.

The Power supply must be higher than 3.22 V to power on the module

Overshoot voltage (regarding MAX Extended Operating Voltage) and drop in

voltage (regarding MIN Extended Operating Voltage) MUST never be

exceeded;

The “Extended Operating Voltage Range” can be used only with completely

assumption and application of the HW User guide suggestions.

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4.2 Power Consumption

Mode

Average (mA)

Mode Description

Switched Off

180 uA

Module supplied but switched off

AT+CFUN=5

1.6

Disabled TX and RX; DRX7

WCDMA Voice

170

WCDMA voice call (TX = 10dBm)

WCDMA HSDPA (22dBm)

538

WCDMA data call (Cat 8, TX = 22dBm)

NOTE:

The electrical design for the Power supply should be made ensuring it will be

capable of a peak current output of at least 1 A.

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4.3 General Design Rules

The principal guidelines for the Power Supply Design embrace three different design steps:

 the electrical design

 the thermal design

 the PCB layout.

Electrical Design Guidelines

The electrical design of the power supply depends strongly from the power source where this power is

drained. We will distinguish them into three categories:

 +5V input (typically PC internal regulator output)

 +12V input (typically automotive)

 Battery

+5V Source Power Supply Design Guidelines

 The desired output for the power supply is 3.8V, hence there's not a big difference between the

input source and the desired output and a linear regulator can be used. A switching power

supply will not be suited because of the low drop out requirements.

 When using a linear regulator, a proper heat sink shall be provided in order to dissipate the

power generated.

 A Bypass low ESR capacitor of adequate capacity must be provided in order to cut the current

absorption peaks close to the Module, a 100μF capacitor is usually suited.

 Make sure the low ESR capacitor on the power supply output rated at least 10V.

An example of linear regulator with 5V input is:

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+ 12V input Source Power Supply Design

Guidelines

 The desired output for the power supply is 3.8V, hence due to the big difference between the

input source and the desired output, a linear regulator is not suited and shall not be used. A

switching power supply will be preferable because of its better efficiency.

 When using a switching regulator, a 500kHz or more switching frequency regulator is preferable

because of its smaller inductor size and its faster transient response. This allows the regulator

to respond quickly to the current peaks absorption.

 In any case the frequency and Switching design selection is related to the application to be

developed due to the fact the switching frequency could also generate EMC interferences.

 For car PB battery the input voltage can rise up to 15,8V and this should be kept in mind when

choosing components: all components in the power supply must withstand this voltage.

 A Bypass low ESR capacitor of adequate capacity must be provided in order to cut the current

absorption peaks, a 100μF capacitor is usually suited.

 Make sure the low ESR capacitor on the power supply output is rated at least 10V.

 For Car applications a spike protection diode should be inserted close to the power input, in

order to clean the supply from spikes.

An example of switching regulator with 12V input is in the below schematic:

UE910 3G HARDWARE USER GUIDE 1vv0301171 Rev.3 • 2015-04-17 24 of 78

Battery Source Power Supply Design Guidelines

The desired nominal output for the power supply is 3.8V and the maximum voltage allowed is 4.2V,

hence a single 3.7V Li-Ion cell battery type is suited for supplying the power to the Telit UE910 module.

 A Bypass low ESR capacitor of adequate capacity must be provided in order to cut the current

absorption peaks, a 100μF tantalum capacitor is usually suited.

 Make sure the low ESR capacitor (usually a tantalum one) is rated at least 10V.

 A protection diode should be inserted close to the power input, in order to save the UE910 from

power polarity inversion. Otherwise the battery connector should be done in a way to avoid

polarity inversions when connecting the battery.

 The battery capacity must be at least 500mAh in order to withstand the current peaks of 2A;

the suggested capacity is from 500mAh to 1000mAh.

WARNING:

The three cells Ni/Cd or Ni/MH 3,6 V Nom. battery types or 4V PB types MUST

NOT BE USED DIRECTLY since their maximum voltage can rise over the

absolute maximum voltage for the UE910 and damage it.

NOTE:

DON'T USE any Ni-Cd, Ni-MH, and Pb battery types directly connected with

UE910. Their use can lead to overvoltage on the UE910 and damage it. USE

ONLY Li-Ion battery types.

UE910 3G HARDWARE USER GUIDE 1vv0301171 Rev.3 • 2015-04-17 25 of 78

Thermal Design Guidelines

The thermal design for the power supply heat sink should be done with the following specifications:

 Average current consumption during HSDPA transmission @PWR level max : 700 mA

 Average current during idle: 1.8 mA

Considering the very low current during idle, especially if Power Saving function is enabled, it is possible

to consider from the thermal point of view that the device absorbs current significantly only during calls.

If we assume that the device stays into transmission for short periods of time (let's say few minutes) and

then remains for a quite long time in idle (let's say one hour), then the power supply has always the time

to cool down between the calls and the heat sink could be smaller than the calculated one for 700mA

maximum RMS current, or even could be the simple chip package (no heat sink).

Moreover in the average network conditions the device is requested to transmit at a lower power level

than the maximum and hence the current consumption will be less than the 700mA, being usually around

150mA.

For these reasons the thermal design is rarely a concern and the simple ground plane where the power

supply chip is placed can be enough to ensure a good thermal condition and avoid overheating.

The generated heat will be mostly conducted to the ground plane under the UE910; you must ensure

that your application can dissipate it.

NOTE:

The average consumption during transmissions depends on the power level at

which the device is requested to transmit by the network. The average current

consumption hence varies significantly.

UE910 3G HARDWARE USER GUIDE 1vv0301171 Rev.3 • 2015-04-17 26 of 78

Power Supply PCB layout Guidelines

As seen on the electrical design guidelines the power supply shall have a low ESR capacitor on the

output to cut the current peaks on the input to protect the supply from spikes The placement of this

component is crucial for the correct working of the circuitry. A misplaced component can be useless or

can even decrease the power supply performances.

 The Bypass low ESR capacitor must be placed close to the Telit UE910 power input pads or in

the case the power supply is a switching type it can be placed close to the inductor to cut the

ripple provided the PCB trace from the capacitor to the UE910 is wide enough to ensure a

dropless connection even during an 1A current peak.

 The protection diode must be placed close to the input connector where the power source is

drained.

 The PCB traces from the input connector to the power regulator IC must be wide enough to

ensure no voltage drops occur when an 1A current peak is absorbed.

 The PCB traces to the UE910 and the Bypass capacitor must be wide enough to ensure no

significant voltage drops occur. This is for the same reason as previous point. Try to keep this

trace as short as possible.

 To reduce the EMI due to switching, it is important to keep very small the mesh involved; thus

the input capacitor, the output diode (if not embodied in the IC) and the regulator have to form

a very small loop.This is done in order to reduce the radiated field (noise) at the switching

frequency (100-500 kHz usually).

 A dedicated ground for the Switching regulator separated by the common ground plane is

suggested.

 The placement of the power supply on the board should be done in such a way to guarantee

that the high current return paths in the ground plane are not overlapped to any noise sensitive

circuitry as the microphone amplifier/buffer or earphone amplifier.

 The power supply input cables should be kept separate from noise sensitive lines such as

microphone/earphone cables.

 The insertion of EMI filter on VBATT pins is suggested in those designs where antenna is

placed close to battery or supply lines.

A ferrite bead like Murata BLM18EG101TN1 or Taiyo Yuden P/N FBMH1608HM101 can be

used for this purpose.

The below figure shows the recommended circuit:

UE910 3G HARDWARE USER GUIDE 1vv0301171 Rev.3 • 2015-04-17 27 of 78

4.4 RTC Bypass out

The VRTC pin brings out the Real Time Clock supply, which is separate from the rest of the digital

part, allowing having only RTC going on when all the other parts of the device are off.

To this power output a backup capacitor can be added in order to increase the RTC autonomy during

power off of the battery. NO Devices must be powered from this pin.

In order to keep the RTC active when VBATT is not supplied it is possible to back up the RTC section

connecting a backup circuit to the related VRTC signal (pad C14 on module’s Pinout).

For additional details on the Backup solutions please refer to the related application note (xE910 RTC

Backup Application Note)

4.5 VAUX Power Output

A regulated power supply output is provided in order to supply small devices from the module. The

signal is present on Pad R11 and it is in common with the PWRMON (module powered ON indication)

function.

This output is always active when the module is powered ON.

The operating range characteristics of the supply are:

Item

Min

Typical

Max

Output voltage

1.78V

1.80V

1.82V

Output current

60mA

Output bypass

capacitor

(inside the module)

1uF

UE910 3G HARDWARE USER GUIDE 1vv0301171 Rev.3 • 2015-04-17 28 of 78

5 DIGITAL SECTION

5.1 Logic Levels Specification

ABSOLUTE MAXIMUM RATINGS – NOT FUNCTIONAL:

OPERATING RANGE - INTERFACE LEVELS (1.8V CMOS):

Parameter

Min

Max

Input high level

1.5V

1.9V

Input low level

0.35V

Output high level

1.6V

1.9V

Output low level

0.2V

OPERATING RANGE - INTERFACE LEVELS (1.2V CMOS):

Parameter

Min

Max

Input high level

0.9V

1.3V

Input low level

0.3V

Output high level

1.3V

Output low level

0.1V

CURRENT CHARACTERISTICS:

Parameter

AVG

Output Current

1mA

Input Current

1uA

Parameter

Min

Max

Input level on any digital pin (CMOS 1.8) with respect to ground

-0.3V

2.1V

Input level on any digital pin (CMOS 1.2) with respect to ground

-0.3V

1.4V

UE910 3G HARDWARE USER GUIDE 1vv0301171 Rev.3 • 2015-04-17 29 of 78

5.2 Power on

To turn on the UE910 the pad ON_OFF* must be tied low for at least 5 seconds and then released.

The maximum current that can be drained from the ON_OFF* pad is 0,1 mA.

A simple circuit to do it is:

NOTE:

Don't use any pull up resistor on the ON_OFF* line, it is internally pulled up.

Using pull up resistor may bring to latch up problems on the UE910 power

regulator and improper power on/off of the module. The line ON_OFF* must be

connected only in open collector or open drain configuration.

In this document all the lines that are inverted, hence have active low signals

are labelled with a name that ends with”#",”*” or with a bar over the name.

To check if the device has powered on, the hardware line PWRMON should be

monitored.

It is mandatory to avoid sending data to the serial ports during the first 200ms

of the module start-up.

UE910 3G HARDWARE USER GUIDE 1vv0301171 Rev.3 • 2015-04-17 30 of 78

A flow chart showing the proper turn on procedure is displayed below:

“Modem ON Proc”

START

VBATT > 3.22V

ON_OFF* = LOW

PWRMON=ON

Delay = 5 sec

ON_OFF* = HIGH

GO TO

“HW Shutdown

Unconditional”

PWRMON=ON

Delay = 1 sec

GO TO

“Start AT Commands””

“Modem ON Proc”

END

UE910 3G HARDWARE USER GUIDE 1vv0301171 Rev.3 • 2015-04-17 31 of 78

A flow chart showing the AT commands managing procedure is displayed

below:

NOTE:

In order to avoid a back powering effect it is recommended to avoid having any

HIGH logic level signal applied to the digital pins of the UE910 when the

module is powered off or during an ON/OFF transition.

“Start AT CMD”

START

Delay = 300 msec

Enter AT <CR>

GO TO

“HW Shutdown

Unconditional”

AT answer in

1 sec ?

GO TO

“Modem ON Proc.”

“Start AT CMD”

END

UE910 3G HARDWARE USER GUIDE 1vv0301171 Rev.3 • 2015-04-17 32 of 78

For example:

1- Let's assume you need to drive the ON_OFF* pad with a totem pole output of a +3/5 V microcontroller

(uP_OUT1):

2- Let's assume you need to drive the ON_OFF* pad directly with an ON/OFF button:

WARNING:

It is recommended to set the ON_OFF* line LOW to power on the module only

after VBATT is higher than 3.22V.

In case this condition it is not satisfied you could use the HW_SHUTDOWN*

line to recover it and then restart the power on activity using the ON_OFF *

line.

An example of this is described in the following diagram.

UE910 3G HARDWARE USER GUIDE 1vv0301171 Rev.3 • 2015-04-17 33 of 78

Power ON diagram:

After HW_SHUTSDOWN* is released you could again use the ON_OFF* line to power on the module.

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5.3 Power off

Turning off the device can be done in two ways:

 via AT command (see UE910 Software User Guide, AT#SHDN)

 by tying low pin ON_OFF*

Either ways, the device issues a detach request to network informing that the device will not be

reachable any more.

To turn OFF the UE910 the pad ON_OFF* must be tied low for at least 3 seconds and then released.

NOTE:

To check if the device has been powered off, the hardware line PWRMON

must be monitored. The device is powered off when PWRMON goes low.

In order to avoid a back powering effect it is recommended to avoid having any

HIGH logic level signal applied to the digital pins of the UE910 when the

module is powered off or during an ON/OFF transition.

UE910 3G HARDWARE USER GUIDE 1vv0301171 Rev.3 • 2015-04-17 35 of 78

The following flow chart shows the proper turn off procedure:

“Modem OFF Proc.”

START

ON_OFF* = LOW

PWRMON=ON?

Delay >= 3 sec

ON_OFF* = HIGH

PWRMON=ON?

GO TO

“HW SHUTDOWN

Unconditional”

“Modem OFF Proc.”

END

OFF Mode

AT#SHDN

Looping for more

than 15s?

Key

UE910 3G HARDWARE USER GUIDE 1vv0301171 Rev.3 • 2015-04-17 36 of 78

5.4 Unconditional Shutdown

HW_SHUTDOWN* is used to unconditionally shutdown the UE910. Whenever this signal is pulled low,

the UE910 is reset. When the device is reset it stops any operation. After the release of the line, the

UE910 is unconditionally shut down, without doing any detach operation from the network where it is

registered. This behaviour is not a proper shut down because any WCDMA device is requested to

issue a detach request on turn off. The HW_SHUTDOWN* is internally controlled on start-up to

achieve always a proper power-on reset sequence, so there's no need to control this pin on start-up.

To unconditionally shutdown the UE910, the pad HW_SHUTDOWN* must be tied low for at least 200

milliseconds and then released.

The signal is internally pulled up so the pin can be left floating if not used.

If used, then it must always be connected with an open collector transistor, to permit to the

internal circuitry the power on reset and under voltage lockout functions.

PIN DESCRIPTION

Signal

Function

I/O

PAD

HW_SHUTDOWN*

Unconditional Shutdown of the Module

R13

OPERATING LEVELS

Signal Status

Min

Max

HW_SHUTDOWN* Input high

1.5V

1.9V

HW_SHUTDOWN* Input Low

0.35V

WARNING:

The hardware unconditional Shutdown must not be used during normal

operation of the device since it does not detach the device from the network. It

shall be kept as an emergency exit procedure.

UE910 3G HARDWARE USER GUIDE 1vv0301171 Rev.3 • 2015-04-17 37 of 78

A typical circuit is the following:

For example:

Let us assume you need to drive the HW_SHUTDOWN* pad with a totem pole output of a +3/5 V

microcontroller (uP_OUT2):

NOTE:

In order to avoid a back powering effect it is recommended to avoid having any

HIGH logic level signal applied to the digital pins of the UE910 when the

module is powered off or during an ON/OFF transition.

UE910 3G HARDWARE USER GUIDE 1vv0301171 Rev.3 • 2015-04-17 38 of 78

In the following flow chart is detailed the proper restart procedure:

NOTE:

Do not use any pull up resistor on the HW_SHUTDOWN* line nor any totem

pole digital output. Using pull up resistor may bring to latch up problems on the

UE910 power regulator and improper functioning of the module.

To proper power on again the module please refer to the related paragraph

(“Power ON”)

The unconditional hardware shutdown must always be implemented on the

boards and should be used only as an emergency exit procedure.

“HW SHUTDOWN

Unconditional”

START

HW_SHUTDOWN* = LOW

Delay = 200ms

PWRMON = ON

Disconnect

VBATT

“HW SHUTDOWN

Unconditional”

END

HW_SHUTDOWN* = HIGH

Delay = 1s

UE910 3G HARDWARE USER GUIDE 1vv0301171 Rev.3 • 2015-04-17 39 of 78

5.5 Communication ports

USB 2.0 HS

The UE910 includes one integrated universal serial bus (USB 2.0 HS) transceiver.

The following table is listing the available signals:

PAD

Signal

I/O

Function

Type

NOTE

B15

USB_D+

I/O

USB differential Data (+)

3.3V

C15

USB_D-

I/O

USB differential Data (-)

3.3V

A13

VUSB

Power sense for the internal USB

transceiver.

Accepted range:

4.4V to 5.25V

The USB_DPLUS and USB_DMINUS signals have a clock rate of 480 MHz.

The signal traces should be routed carefully. Trace lengths, number of vias and capacitive loading

should be minimized. The characteristic impedance value should be as close as possible to 90 Ohms

differential.

In case there is a need to add an ESD protection, the suggested connection is the following:

NOTE:

VUSB pin should be disconnected before activating the Power Saving Mode.

UE910 3G HARDWARE USER GUIDE 1vv0301171 Rev.3 • 2015-04-17 40 of 78

USB HSIC

The UE910 Module is provided by one USB HSIC interface.

The USB HSIC (High Speed Inter Processor) Interface allows supporting the inter-processor

communication between an application processor (AP) – the host, and the modem processor

(CP) – the UE910.

The following table is listing the available signals:

PAD

Signal

I/O

Function

Type

NOTE

A12

HSIC_USB_DATA

I/O

USB HSIC data signal

CMOS

1.2V

A11

HSIC_USB_STRB

I/O

USB HSIC strobe

signal

CMOS

1.2V

H15

HSIC_SLAVE_WAKEUP

Slave Wake Up

CMOS

1.8V

Shared with

SPI_MRDY

F15

HSIC_HOST_WAKEUP

Host Wake Up

CMOS

1.8V

Shared with

SPI CLK

K15

HSIC_SUSPEND_REQUEST

Slave Suspend

Request

CMOS

1.8V

Shared with

GPIO08

J15

HSIC_HOST_ACTIVE

Active Host Indication

CMOS

1.8V

Shared with

SPI_SRDY

For the detailed use of USB HSIC port please refer to the related Application Note.

NOTE:

Due to the shared functions, when the USB_HSIC port is used, it is not

possible to use the SPI and GPIO_08.

The USB_HSIC is not active by default but it has to be enabled using the

AT#PORTCFG command (refer to the AT user guide for the detailed syntax

description).

UE910 3G HARDWARE USER GUIDE 1vv0301171 Rev.3 • 2015-04-17 41 of 78

SPI

The UE910 Module is provided by one SPI interface.

The SPI interface defines two handshake lines for flow control and mutual wake-up of the modem and

the Application Processor: SRDY (slave ready) and MRDY (master ready).

The AP has the master role, that is, it supplies the clock.

The following table is listing the available signals:

PAD

Signal

I/O

Function

Type

NOTE

D15

SPI_MOSI

SPI MOSI

CMOS 1.8V

Shared with TX_AUX

E15

SPI_MISO

SPI MISO

CMOS 1.8V

Shared with RX_AUX

F15

SPI_CLK

SPI Clock

CMOS 1.8V

H15

SPI_MRDY

CMOS 1.8V

J15

SPI_SRDY

CMOS 1.8V

NOTE:

Due to the shared functions, when the SPI port is used, it is not possible to use

the AUX_UART port.

SPI Connections

SPI_MISO

SPI_MOSI

SPI_CLK

SPI_MRDY

SPI_SRDY

E15

D15

F15

H15

J15

UE910 AP

UE910 3G HARDWARE USER GUIDE 1vv0301171 Rev.3 • 2015-04-17 42 of 78

Serial Ports

The UE910 module is provided with by 2 Asynchronous serial ports:

 MODEM SERIAL PORT 1 (Main)

 MODEM SERIAL PORT 2 (Auxiliary)

Several configurations can be designed for the serial port on the OEM hardware, but the most common

are:

 RS232 PC com port

 microcontroller UART @ 1.8V (Universal Asynchronous Receive Transmit)

 microcontroller UART @ 5V or other voltages different from 1.8V

Depending from the type of serial port on the OEM hardware a level translator circuit may be needed to

make the system work.

On the UE910 the ports are CMOS 1.8.

MODEM SERIAL PORT 1 (USIF0)

The serial port 1 on the UE910 is a +1.8V UART with all the 7 RS232 signals.

It differs from the PC-RS232 in the signal polarity (RS232 is reversed) and levels.

The following table is listing the available signals:

RS232

Signal

Pad

Name

Usage

C109/DCD

N14

Data Carrier Detect

Output from the UE910 that indicates

the carrier presence

C104/RXD

M15

Transmit line *see Note

Output transmit line of UE910 UART

C103/TXD

N15

Receive line *see Note

Input receive of the UE910 UART

C108/DTR

M14

Data Terminal Ready

Input to the UE910 that controls the DTE

READY condition

GND

M12,

B13,

P13,

E14 …

Ground

C107/DSR

P14

Data Set Ready

Output from the UE910 that indicates

the module is ready

C106/CTS

P15

Clear to Send

Output from the UE910 that controls the

Hardware flow control

C105/RTS

L14

Request to Send

Input to the UE910 that controls the

Hardware flow control

C125/RING

R14

Ring Indicator

Output from the UE910 that indicates

the incoming call condition

UE910 3G HARDWARE USER GUIDE 1vv0301171 Rev.3 • 2015-04-17 43 of 78

The following table shows the typical input value of internal pull-up resistors for RTS, DTR and TXD

input lines and in all module states:

STATE

RTS DTR TXD

Pull up tied to

5K to 12K

1V8

OFF

Schottky diode

RESET

Schottky diode

POWER SAVING

5K to 12K

1V8

The input line ON_OFF and HW_SHDN state can be treated as in picture below

NOTE:

According to V.24, some signal names are referred to the application side,

therefore on the UE910 side these signal are on the opposite direction:

TXD on the application side will be connected to the receive line (here named

C103/TXD)

RXD on the application side will be connected to the transmit line (here named

C104/RXD)

For a minimum implementation, only the TXD, RXD lines can be connected,

the other lines can be left open provided a software flow control is

implemented.

In order to avoid a back powering effect it is recommended to avoid having any

HIGH logic level signal applied to the digital pins of the UE910 when the

module is powered off or during an ON/OFF transition.

UE910 3G HARDWARE USER GUIDE 1vv0301171 Rev.3 • 2015-04-17 44 of 78

MODEM SERIAL PORT 2 (USIF1)

The secondary serial port on the UE910 is a CMOS1.8V with only the RX and TX signals.

The signals of the UE910 serial port are:

PAD

Signal

I/O

Function

Type

NOTE

D15

TX_AUX

Auxiliary UART (TX Data to

DTE)

CMOS 1.8V

Shared with SPI_MOSI

E15

RX_AUX

Auxiliary UART (RX Data

from DTE)

CMOS 1.8V

Shared with SPI_MISO

NOTE:

Due to the shared pins, when the Modem Serial port is used, it is not possible

to use the SPI functions.

In order to avoid a back powering effect it is recommended to avoid having any

HIGH logic level signal applied to the digital pins of the UE910 when the

module is powered off or during an ON/OFF transition.

UE910 3G HARDWARE USER GUIDE 1vv0301171 Rev.3 • 2015-04-17 45 of 78

RS232 LEVEL TRANSLATION

In order to interface the UE910 with a PC com port or a RS232 (EIA/TIA-232) application a level

translator is required. This level translator must:

 invert the electrical signal in both directions;

 Change the level from 0/1.8V to +15/-15V.

Actually, the RS232 UART 16450, 16550, 16650 & 16750 chipsets accept signals with lower levels on

the RS232 side (EIA/TIA-562), allowing a lower voltage-multiplying ratio on the level translator. Note

that the negative signal voltage must be less than 0V and hence some sort of level translation is always

required.

The simplest way to translate the levels and invert the signal is by using a single chip level translator.

There are a multitude of them, differing in the number of drivers and receivers and in the levels (be sure

to get a true RS232 level translator not a RS485 or other standards).

By convention the driver is the level translator from the 0-1.8V UART to the RS232 level. The receiver

is the translator from the RS232 level to 0-1.8V UART.

In order to translate the whole set of control lines of the UART you will need:

 5 drivers

 3 receivers

An example of RS232 level adaptation circuitry could be done using a MAXIM transceiver (MAX218)

In this case the chipset is capable to translate directly from 1.8V to the RS232 levels (Example done

on 4 signals only).

The RS232 serial port lines are usually connected to a DB9 connector with the following layout:

UE910 3G HARDWARE USER GUIDE 1vv0301171 Rev.3 • 2015-04-17 46 of 78

5.6 General Purpose I/O

The UE910 module is provided by a set of Configurable Digital Input / Output pins (CMOS 1.8V)

Input pads can only be read; they report the digital value (high or low) present on the pad at the read

time.

Output pads can only be written or queried and set the value of the pad output.

An alternate function pad is internally controlled by the UE910 firmware and acts depending on the

function implemented.

The following table shows the available GPIO on the UE910:

PAD

Signal

I/O

Drive

Strength

Default

State

NOTE

GPIO_01

I/O

1 mA

INPUT

Alternate function STAT LED

GPIO_02

I/O

1 mA

INPUT

C10

GPIO_03

I/O

1 mA

INPUT

C11

GPIO_04

I/O

1 mA

INPUT

B14

GPIO_05

I/O

1 mA

INPUT

C12

GPIO_06

I/O

1 mA

INPUT

C13

GPIO_07

I/O

1 mA

INPUT

K15

GPIO_08

I/O

1 mA

INPUT

L15

GPIO_09

I/O

1 mA

INPUT

G15

GPIO_10

I/O

1 mA

INPUT

UE910 3G HARDWARE USER GUIDE 1vv0301171 Rev.3 • 2015-04-17 47 of 78

Using a GPIO as INPUT

The GPIO pads, when used as inputs, can be connected to a digital output of another device and

report its status, provided this device has interface levels compatible with the 1.8V CMOS levels of the

GPIO.

If the digital output of the device to be connected with the GPIO input pad has interface levels different

from the 1.8V CMOS, then it can be buffered with an open collector transistor with a 47K pull up to

1.8V.

NOTE:

In order to avoid a back powering effect it is recommended to avoid having any

HIGH logic level signal applied to the digital pins of the UE910 when the

module is powered off or during an ON/OFF transition.

Using a GPIO as OUTPUT

The GPIO pads, when used as outputs, can drive 1.8V CMOS digital devices or compatible hardware.

When set as outputs, the pads have a push-pull output and therefore the pull-up resistor may be

omitted.

UE910 3G HARDWARE USER GUIDE 1vv0301171 Rev.3 • 2015-04-17 48 of 78

Indication of network service availability

The STAT_LED pin status shows information on the network service availability and Call status.

The function is available as alternate function of GPIO_01 (to be enabled using the AT#GPIO=1,0,2

command).

In the UE910 modules, the STAT_LED needs an external transistor to drive an external LED.

Therefore, the status indicated in the following table is reversed with respect to the pin status.

Device Status

Led Status

Device off

Permanently off

Not Registered

Permanently on

Registered in idle

Blinking 1sec on + 2 sec off

Registered in idle + power saving

It depends on the event that

triggers the wakeup (In sync with

network paging)

Voice Call Active

Permanently on

Dial-Up

Blinking 1 sec on + 2 sec off

A schematic example could be:

UE910 3G HARDWARE USER GUIDE 1vv0301171 Rev.3 • 2015-04-17 49 of 78

5.7 External SIM Holder

Please refer to the related User Guide (SIM Holder Design Guides, 80000NT10001a).

5.8 ADC Converter

The UE910 is provided by one AD converter. It is able to read a voltage level in the range of 0÷1.2

volts applied on the ADC pin input, store and convert it into 10 bit word.

The input line is named as ADC_IN1 and it is available on Pad B1

The following table is showing the ADC characteristics:

Item

Min

Typical

Max

Unit

Input Voltage range

1.2

Volt

AD conversion

bits

Input Resistance

Mohm

Input Capacitance

The ADC could be controlled using an AT command.

The command is AT#ADC=1,2

The read value is expressed in mV

Refer to SW User Guide or AT Commands Reference Guide for the full description of this function.

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6 RF SECTION

6.1 Bands Variants

The following table is listing the supported Bands:

6.2 TX Output Power

6.3 RX Sensitivity

Product

Supported 3G bands

UE910-N3G

FDD B2, B5

Band

Power Class

FDD B2, B5

Class 3 (0.25W)

Band

Sensitivity

FDD B2, B5

-111dBm

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6.4 Antenna Requirements

The antenna connection and board layout design are the most important aspect in the full product

design as they strongly affect the product overall performances, hence read carefully and follow the

requirements and the guidelines for a proper design.

The antenna and antenna transmission line on PCB for a Telit UE910 device shall fulfil the following

requirements:

PCB design guidelines

When using the UE910, since there's no antenna connector on the module, the antenna must be

connected to the UE910 antenna pad (K1) by means of a transmission line implemented on the PCB.

In the case the antenna is not directly connected at the antenna pad of the UE910, then a PCB line is

needed in order to connect with it or with its connector.

This transmission line shall fulfil the following requirements:

Item

Value

Frequency range

Depending by frequency band(s) provided by the network

operator, the customer shall use the most suitable antenna for

that/those band(s)

Bandwidth

70 MHz in WCDMA Band V

140 MHz in WCDMA Band II

Impedance

50 ohm

Input power

> 24dBm Average power

VSWR absolute max

≤ 10:1 (limit to avoid permanent damage)

VSWR recommended

≤ 2:1 (limit to fulfill all regulatory requirements)

Item

Value

Characteristic Impedance

50 ohm

Max Attenuation

0,3 dB

Coupling

Coupling with other signals shall be avoided

Ground Plane

Cold End (Ground Plane) of antenna shall be equipotential to

the UE910 ground pins

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The transmission line should be designed according to the following guidelines:

 Ensure that the antenna line impedance is 50 ohm;

 Keep the antenna line on the PCB as short as possible, since the antenna line loss shall be

less than 0,3 dB;

 Antenna line must have uniform characteristics, constant cross section; avoid meanders and

abrupt curves;

 Keep, if possible, one layer of the PCB used only for the Ground plane;

 Surround (on the sides, over and under) the antenna line on PCB with Ground, avoid having

other signal tracks facing directly the antenna line track;

 The ground around the antenna line on PCB has to be strictly connected to the Ground Plane

by placing vias every 2mm at least;

 Place EM noisy devices as far as possible from UE910 antenna line;

 Keep the antenna line far away from the UE910 power supply lines;

 If you have EM noisy devices around the PCB hosting the UE910, such as fast switching ICs,

take care of the shielding of the antenna line by burying it inside the layers of PCB and

surround it with Ground planes, or shield it with a metal frame cover.

 If you don't have EM noisy devices around the PCB of UE910, by using a micro strip on the

superficial copper layer for the antenna line, the line attenuation will be lower than a buried

one;

The following image is showing the suggested layout for the Antenna pad connection:

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PCB Guidelines in case of FCC Certification

In the case FCC certification is required for an application using UE910-N3G, according to FCC KDB

996369 for modular approval requirements, the transmission line has to be similar to that implemented

on UE910 interface board and described in the following chapter.

Transmission line design

During the design of the UE910 interface board, the placement of components has been chosen

properly, in order to keep the line length as short as possible, thus leading to lowest power losses

possible. A Grounded Coplanar Waveguide (G-CPW) line has been chosen, since this kind of

transmission line ensures good impedance control and can be implemented in an outer PCB layer as

needed in this case. A SMA female connector has been used to feed the line.

The interface board is realized on a FR4, 4-layers PCB. Substrate material is characterized by relative

permittivity εr = 4.6 ± 0.4 @ 1 GHz, TanD= 0.019 ÷ 0.026 @ 1 GHz.

A characteristic impedance of nearly 50 Ω is achieved using trace width = 1.1 mm, clearance from

coplanar ground plane = 0.3 mm each side. The line uses reference ground plane on layer 3, while

copper is removed from layer 2 underneath the line. Height of trace above ground plane is 1.335 mm.

Calculated characteristic impedance is 51.6 Ω, estimated line loss is less than 0.1 dB. The line

geometry is shown below:

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Transmission Line Measurements

An HP8753E VNA (Full-2-port calibration) has been used in this measurement session.

A calibrated coaxial cable has been soldered at the pad corresponding to RF output; a SMA connector

has been soldered to the board in order to characterize the losses of the transmission line including

the connector itself. During Return Loss / impedance measurements, the transmission line has been

terminated to 50 Ω load.

Return Loss plot of line under test is shown below:

Line input impedance (in Smith Chart format, once the line has been terminated to 50 Ω load) is

shown in the following figure:

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Insertion Loss of G-CPW line plus SMA connector is shown below:

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Antenna Installation Guidelines

Install the antenna in a place covered by the WCDMA signal.

If the device antenna is located farther than 20cm from the human body and there are no co-located

transmitter then the Telit FCC/IC approvals can be re-used by the end product.

If the device antenna is located closer than 20cm from the human body or there are co-located

transmitter then the additional FCC/IC testing may be required for the end product (Telit FCC/IC

approvals cannot be reused).

Antenna shall not be installed inside metal cases.

Antenna shall be installed also according to antenna manufacturer instructions.

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7 AUDIO SECTION

7.1 Overview

The UE910 is provided by two main Audio interfaces:

 Analog Audio Path

 Digital Audio Path

NOTE:

The two Paths could not be used in parallel; If the Analog Voice lines are

selected, the DVI interface is disabled and Vice versa.

7.2 Analog Voice Interface

The Base Band Chip of the UE910 provides one differential input for audio to be transmitted (Uplink)

and a balanced BTL output for audio to be received (downlink).

The Signals are available on the following Pads:

PAD

Signal

I/O

Function

EAR+

Analog Voice Interface (EAR+)

EAR-

Analog Voice Interface (EAR-)

MIC+

Analog Voice Interface (MIC+)

MIC-

Analog Voice Interface (MIC-)

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MIC connection

The bias for the microphone has to be as clean as possible; the first connection (single ended) is

preferable since the Vmic noise and ground noise are fed into the input as common mode and then

rejected. This sounds strange; usually the connection to use in order to reject the common mode is the

balanced one. In this situation we have to recall that the microphone is a sound to current transducer,

so the resistor is the current to tension transducer, so finally the resistor feeds the input in balanced

way even if the configuration, from a microphone point of view, seems to be un-balanced.

The following images show some connection examples:

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If a "balanced way" is anyway desired, much more care has to be taken to Vmic noise and ground

noise; also the 33pF-100Ohm-33pF RF-filter has to be doubled (one each wire).

NOTE:

Since the J-FET transistor inside the microphone acts as RF-detector-amplifier,

ask vendor for a microphone with anti-EMI capacitor (usually a 33pF or a 10pF

capacitor placed across the output terminals inside the case).

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LINE IN Connection

If the audio source is not a mike but a different device, the following connections can be done.

Place 100nF capacitor in series with both inputs, so the DC current is blocked.

Place the 33pF-100Ohm-33pF RF-filter, in order to prevent some EMI field to get into the high

impedance high gain MIC inputs.

Since the input is differential, the common mode voltage noise between the two (different) ground is

rejected, provided that both MIC+ & MIC- are connected directly onto the source.

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EAR Connection

The audio output of the UE910 is balanced, this is helpful to double the level and to reject common

mode (click and pop are common mode and therefore rejected).

These outputs can drive directly a small loudspeaker with electrical impedance not lower than 16

Ohm.

NOTE:

In order to get the maximum audio level at a given output voltage level

(dBspl/Vrms), the following breaking through procedure can be used. Have the

loudspeaker as close as you can to the listener (this simplify also the echo

cancelling); choose the loudspeaker with the higher sensitivity (dBspl per W);

choose loudspeakers with the impedance close to the limit, in order to feed

more power inside the transducer (it increases the W/Vrms ratio). If this were

not enough, an external amplifier should be used.

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7.3 Digital Voice Interface

The UE910 Module is provided by one DVI digital voice interface.

The Signals are available on the following Pads:

PAD

Signal

I/O

Function

DVI_WA0

I/O

Digital Voice Interface (Word Alignment / LRCLK)

DVI_RX

Digital Voice Interface (RX)

DVI_TX

Digital Voice Interface (TX)

DVI_CLK

I/O

Digital Voice Interface (BCLK)

CODEC Examples

Please refer to the Digital Audio Application note.

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8 MECHANICAL DESIGN

8.1 Drawing

Dimensions in mm

PIN B1

Lead Free Alloy:

Surface Finishing Ni/Au for all solder pads

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9 APPLICATION DESIGN

The UE910 modules have been designed in order to be compliant with a standard lead-free SMT

process.

9.1 Footprint

TOP VIEW

In order to easily rework the UE910 is suggested to consider on the application a 1.5 mm placement

inhibit area around the module.

It is also suggested, as common rule for an SMT component, to avoid having a mechanical part of the

application in direct contact with the module.

NOTE:

In the customer application, the region under WIRING INHIBIT (see figure

above) must be clear from signal or ground paths.

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9.2 PCB pad design

Non solder mask defined (NSMD) type is recommended for the solder pads on the PCB.

9.3 PCB pad dimensions

The recommendation for the PCB pads dimensions are described in the following image (dimensions

in mm)

Solder resist openings

PCB

Copper Pad

Solder Mask

SMD

(Solder Mask Defined)

NSMD

(Non Solder Mask Defined)

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It is not recommended to place via or micro-via not covered by solder resist in an area of 0,3 mm

around the pads unless it carries the same signal of the pad itself

(see following figure).

Holes in pad are allowed only for blind holes and not for through holes.

Recommendations for PCB pad surfaces:

Finish

Layer Thickness (um)

Properties

Electro-less Ni / Immersion Au

3 –7 / 0.05 – 0.15

good solder ability protection,

high shear force values

The PCB must be able to resist the higher temperatures which are occurring at the lead-free process.

This issue should be discussed with the PCB-supplier. Generally, the wettability of tin-lead solder

paste on the described surface plating is better compared to lead-free solder paste.

It is not necessary to panel the application’s PCB, however in that case it is suggested to use milled

contours and predrilled board breakouts; scoring or v-cut solutions are not recommended.

Inhibit area for micro-via

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9.4 Stencil

Stencil’s apertures layout can be the same of the recommended footprint (1:1), we suggest a

thickness of stencil foil ≥ 120 µm.

9.5 Solder paste

Item

Lead Free

Solder Paste

Sn/Ag/Cu

We recommend using only “no clean” solder paste in order to avoid the cleaning of the modules after

assembly.

9.6 Solder reflow

Recommended solder reflow profile:

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Profile Feature

Pb-Free Assembly

Average ramp-up rate (TL to TP)

3°C/second max

Preheat

– Temperature Min (Tsmin)

– Temperature Max (Tsmax)

– Time (min to max) (ts)

150°C

200°C

60-180 seconds

Tsmax to TL

– Ramp-up Rate

3°C/second max

Time maintained above:

– Temperature (TL)

– Time (tL)

217°C

60-150 seconds

Peak Temperature (Tp)

245 +0/-5°C

Time within 5°C of actual Peak

Temperature (tp)

10-30 seconds

Ramp-down Rate

6°C/second max.

Time 25°C to Peak Temperature

8 minutes max.

NOTE:

All temperatures refer to topside of the package, measured on the package

body surface

WARNING:

The UE910 module withstands one reflow process only.

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10 PACKAGING

10.1 Tray

The UE910 modules are packaged on trays of 36 pieces each. These trays can be used in SMT

processes for pick & place handling.

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10.2 Reel

The UE910 can be packaged on reels of 200 pieces each.

See figure for module positioning into the carrier.

Carrier Tape Detail

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Reel Detail

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Reel Box Detail

10.3 Moisture sensitivity

The UE910 is a Moisture Sensitive Device level 3, in according with standard IPC/JEDEC J-STD-020,

take care all the relatives requirements for using this kind of components.

Moreover, the customer has to take care of the following conditions:

a) Calculated shelf life in sealed bag: 12 months at <40°C and <90% relative humidity (RH).

b) Environmental condition during the production: 30°C / 60% RH according to IPC/JEDEC J-STD-

033A paragraph 5.

c) The maximum time between the opening of the sealed bag and the reflow process must be 168

hours if condition b) “IPC/JEDEC J-STD-033A paragraph 5.2” is respected

d) Baking is required if conditions b) or c) are not respected

e) Baking is required if the humidity indicator inside the bag indicates 10% RH

or more

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11 SAFETY

RECOMMANDATIONS

READ CAREFULLY

Be sure the use of this product is allowed in the country and in the environment required. The use of

this product may be dangerous and has to be avoided in the following areas:

Where it can interfere with other electronic devices in environments such as hospitals, airports,

aircrafts, etc

Where there is risk of explosion such as gasoline stations, oil refineries, etc

It is responsibility of the user to enforce the country regulation and the specific environment regulation.

Do not disassemble the product; any mark of tampering will compromise the warranty validity.

We recommend following the instructions of the hardware user guides for a correct wiring of the

product. The product has to be supplied with a stabilized voltage source and the wiring has to be

conforming to the security and fire prevention regulations.

The product has to be handled with care, avoiding any contact with the pins because electrostatic

discharges may damage the product itself. Same cautions have to be taken for the SIM, checking

carefully the instruction for its use. Do not insert or remove the SIM when the product is in power

saving mode.

The system integrator is responsible of the functioning of the final product; therefore, care has to be

taken to the external components of the module, as well as of any project or installation issue,

because the risk of disturbing the GSM network or external devices or having impact on the security.

Should there be any doubt, please refer to the technical documentation and the regulations in force.

Every module has to be equipped with a proper antenna with specific characteristics. The antenna has

to be installed with care in order to avoid any interference with other electronic devices and has to

guarantee a minimum distance from the body (20 cm). In case of this requirement cannot be satisfied,

the system integrator has to assess the final product against the SAR regulation.

The European Community provides some Directives for the electronic equipments introduced on the

market. All the relevant information’s are available on the European Community website:

http://europa.eu.int/comm/enterprise/rtte/dir99-5.htm

The text of the Directive 99/05 regarding telecommunication equipments is available, while the

applicable Directives (Low Voltage and EMC) are available at:

http://europa.eu.int/comm/enterprise/electr_equipment/index_en.htm

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12 FCC/IC REGULATORY

NOTICES

Modification statement

Telit has not approved any changes or modifications to this device by the user. Any changes or

modifications could void the user’s authority to operate the equipment.

Telit n’approuve aucune modification apportée à l’appareil par l’utilisateur, quelle qu’en soit la nature.

Tout changement ou modification peuvent annuler le droit d’utilisation de l’appareil par l’utilisateur.

Interference statement

This device complies with Part 15 of the FCC Rules and Industry Canada licence-exempt RSS

standard(s). Operation is subject to the following two conditions: (1) this device may not cause

interference, and (2) this device must accept any interference, including interference that may cause

undesired operation of the device.

Le présent appareil est conforme aux CNR d'Industrie Canada applicables aux appareils radio

exempts de licence. L'exploitation est autorisée aux deux conditions suivantes : (1) l'appareil ne doit

pas produire de brouillage, et (2) l'utilisateur de l'appareil doit accepter tout brouillage radioélectrique

subi, même si le brouillage est susceptible d'en compromettre le fonctionnement.

Wireless notice

This equipment complies with FCC and IC radiation exposure limits set forth for an uncontrolled

environment. The antenna should be installed and operated with minimum distance of 20 cm between

the radiator and your body. Antenna gain must be below:

Frequency Band

Gain

Band II (1900 MHz)

9.01 dBi

Band V (850 MHz)

7.76 dBd

This transmitter must not be co-located or operating in conjunction with any other antenna or

transmitter.

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Cet appareil est conforme aux limites d'exposition aux rayonnements de la IC pour un environnement

non contrôlé. L'antenne doit être installé de façon à garder une distance minimale de 20 centimètres

entre la source de rayonnements et votre corps. Gain de l'antenne doit être ci-dessous:

Bande de fréquence

Gain

Band II (1900 MHz)

9.01 dBi

Band V (850 MHz)

7.76 dBd

L'émetteur ne doit pas être colocalisé ni fonctionner conjointement avec à autre antenne ou autre

émetteur.

FCC Class B digital device notice

This equipment has been tested and found to comply with the limits for a Class B digital device,

pursuant to part 15 of the FCC Rules. These limits are designed to provide reasonable protection

against harmful interference in a residential installation. This equipment generates, uses and can

radiate radio frequency energy and, if not installed and used in accordance with the instructions, may

cause harmful interference to radio communications. However, there is no guarantee that interference

will not occur in a particular installation. If this equipment does cause harmful interference to radio or

television reception, which can be determined by turning the equipment off and on, the user is

encouraged to try to correct the interference by one or more of the following measures:

Reorient or relocate the receiving antenna.

Increase the separation between the equipment and receiver.

Connect the equipment into an outlet on a circuit different from that to which the receiver is connected.

Consult the dealer or an experienced radio/TV technician for help.

Labelling Requirements for the Host device

The host device shall be properly labelled to identify the modules within the host device. The

certification label of the module shall be clearly visible at all times when installed in the host device,

otherwise the host device must be labelled to display the FCC ID and IC of the module, preceded by

the words "Contains transmitter module", or the word "Contains", or similar wording expressing the

same meaning, as follows:

Contains FCC ID: RI7UE910N3

Contains IC: 5131A-UE910N3

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L'appareil hôte doit être étiqueté comme il faut pour permettre l'identification des modules qui s'y

trouvent. L'étiquette de certification du module donné doit être posée sur l'appareil hôte à un endroit

bien en vue en tout temps. En l'absence d'étiquette, l'appareil hôte doit porter une étiquette donnant le

FCC ID et le IC du module, précédé des mots « Contient un module d'émission », du mot « Contient »

ou d'une formulation similaire exprimant le même sens, comme suit :

Contains FCC ID: RI7UE910N3

Contains IC: 5131A-UE910N3

CAN ICES-3 (B) / NMB-3 (B)

This Class B digital apparatus complies with Canadian ICES-003.

Cet appareil numérique de classe B est conforme à la norme canadienne ICES-003.

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13 DOCUMENT HISTORY

13.1 Revisions

Revision

Date

Changes

2014-10-01

Preliminary Version

2015-01-08

Updated document format

2015-03-31

Added RX Sensitivity

Added Third Party Rights

Added FCC/IC Regulatory Notices

Safety Recommendations

Updated Tray Packaging

Updated Chapter 4.2

2015-04-17

Updated Chapter 12

Telit Communications S p A UE910N3 3G Module User Manual 11

Telit Communications S.p.A. 3G Module 11

Contents

11_User Manual

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