Toshiba Tw40F80 Technical Training Manual Toc

TW40F80 to the manual 9d699d9e-c699-44ff-a762-9b3b908906d0

2014-12-13

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NTDPJTV05

TECHNICAL TRAINING MANUAL
N5SS CHASSIS

PROJECTION TELEVISION

TW40F80

Only the different points from the training manual “N5SS chassis” with its file
No. 026-9506 are described on this manual.
For other parts common with “N5SS chassis”, please refer to the original manual
with its file No. 026-9506.

©1997 TOSHIBA AMERICA CONSUMER PRODUCTS, INC.
NATIONAL SERVICE DIVISION
TRAINING DEPARTMENT
1420-B TOSHIBA DRIVE
LEBANON, TENNESSEE 37087
PHONE: (615)449-2360
FAX: (615)444-7520
www.toshiba.com/tacp

Contents Page 1

Contents
SECTION I: OUTLINE ................................................................................................ 6
1. FEATURE.................................................................................................................... 6
2. MERITS OF BUS SYSTEM ...................................................................................... 6
3. SPECIFICATIONS..................................................................................................... 7
4. FRONT VIEW ........................................................................................................... 8
5. REAR VIEW ............................................................................................................... 9
6. REMOTE CONTROL VIEW.................................................................................. 10
7. CHASSIS LAYOUT.................................................................................................. 11
8. CONSTRUCTION OF CHASSIS ........................................................................... 12
SECTION II: TUNER, IF/MTS/S. PRO MODULE ................................................ 13
1. CIRCUIT BLOCK ................................................................................................... 13
2. POP TUNER ............................................................................................................. 17
SECTION III: CHANNEL SELECTION CIRCUIT ............................................... 18
1. OUTLINE OF CHANNEL SELECTION CIRCUIT SYSTEM .......................... 18
2. OPERATION OF CHANNEL SELECTION CIRCUIT ...................................... 18
3. MICROCOMPUTER ............................................................................................... 19
4. MICROCOMPUTER TERMINAL FUNCTION .................................................. 20
5. EEPROM (QA02) ..................................................................................................... 22
6. ON SCREEN FUNCTION ....................................................................................... 22
7. SYSTEM BLOCK DIAGRAM................................................................................ 23
8. LOCAL KEY DETECTION METHOD ................................................................ 24
9. REMOTE CONTROL CODE ASSIGNMENT ..................................................... 25
10. ENTERING TO SERVICE MODE ...................................................................... 28
11. TEST SIGNAL SELECTION ............................................................................... 28
12. SERVICE ADJUSTMENT .................................................................................... 28
13. FAILURE DIAGNOSIS PROCEDURE ............................................................... 29
14. TROUBLESHOOTING CHART .......................................................................... 32
SECTION IV: DVD SWITCH CIRCUIT ................................................................. 35
1. DVD SWITCH BLOCK DIAGRAM ...................................................................... 35
2. OUTLINE .................................................................................................................. 36

Contents Page 2

SECTION V: WAC CIRCUIT .................................................................................... 37
1. OUTLINE .................................................................................................................. 37
2. CIRCUIT OPERATION .......................................................................................... 37
3. BLOCK DIAGRAM ................................................................................................. 42
4. WIDE ASPECT CONVERSION CIRCUIT FAILURE ANALYSIS
PROCEDURES ......................................................................................................... 43
SECTION VI: DUAL CIRCUIT ................................................................................ 45
1. OUTLINE .................................................................................................................. 45
2. PRINCIPLES OF OPERATION ............................................................................. 45
3. SYSTEM COMPONENT DIAGRAM OF DUAL UNIT ...................................... 46
4. CIRCUIT OPERATION .......................................................................................... 47
5. TERMINAL FUNCTION, DESCRIPTION AND BLOCK DIAGRAM OF
MAIN IC.................................................................................................................... 51
SECTION VII: 3-DIMENSION Y/C SEPARATOR CIRCUIT .............................. 58
1. OUTLINE .................................................................................................................. 58
2. CIRCUIT DESCRIPTION ...................................................................................... 58
SECTION VIII: VERTICAL OUTPUT CIRCUIT.................................................. 60
1. OUTLINE .................................................................................................................. 60
2. V OUTPUT CIRCUIT.............................................................................................. 61
3. PROTECTION CIRCUIT FOR V DEFLECTION STOP ................................... 64
4. RASTER POSITION SWITCHING CIRCUIT .................................................... 66
SECTION IX: HORIZONTAL DEFLECTION CIRCUIT .................................... 67
1. OUTLINE .................................................................................................................. 67
2. HORIZONTAL DRIVE CIRCUIT ......................................................................... 67
3. BASIC OPERATION OF HORIZONTAL DRIVE............................................... 67
4. HORIZONTAL OUTPUT CIRCUIT ..................................................................... 69
5. HIGH VOLTAGE GENERATION CIRCUIT ....................................................... 76
6. HIGH VOLTAGE CIRCUIT ................................................................................... 78
7. X-RAY PROTECTION CIRCUIT .......................................................................... 80
8. OVER CURRENT PROTECTION CIRCUIT ...................................................... 81

Contents Page 3

SECTION X: DEFLECTION DISTORTION CORRECTION CIRCUIT
(SIDE DPC CIRCUIT) ............................................................................................... 82
1. DEFLECTION DISTORTION CORRECTION IC (TA8859CP) ....................... 82
2. DIODE MODULATOR CIRCUIT ......................................................................... 83
3. ACTUAL CIRCUIT .................................................................................................. 84
SECTION XI: DIGITAL CONVERGENCE CIRCUIT ......................................... 87
1. OUTLINE .................................................................................................................. 87
2. CIRCUIT DESCRIPTION ...................................................................................... 87
3. PICTURE ADJUSTMENT ...................................................................................... 89
4. CASE STUDY ........................................................................................................... 97
5. TROUBLESHOOTING ........................................................................................... 98
6. CONVERGENCE OUTPUT CIRCUIT ................................................................. 99
7. CONVERGENCE TROUBLESHOOTING CHART ......................................... 101
OVERALL BLOCK DIAGRAM................................................................................102

SECTION I: OUTLINE

1. FEATURE

2. MERITS OF BUS SYSTEM

The TW40F80 is a first PJ-TV with a wide screen aspect
ratio of 16:9 we introduce to North U.S.A. markets.

2-1. Improved Serviceability
Most of the adjustments previously made by resetting variable resistors and/or capacitors can be made on the new chassis by operating the remote control and seeing the results on
the TV screen. This allows seeing adjustments to be made
without removing servicing speed and efficiency.

As the basic chassis N5SS chassis is used.
The future of the model TW40F80 is the use of the N5SS
chassis. This chassis introduces a new bus system, developed by the PHILIPS company, called the I2C (or IIC) bus.
IIC stands for Inter-Integrated Circuit control. This bus coordinates the transfer of data and control between ICs inside
the TV. It is a bi-directional serial bus consisting of two lines,
named SDA (Serial DATA), and SCL (Serial CLOCK). This
bus control system is made possible through the use of digital-to analog converters built into the ICs, allowing them to
be addressed and controlled by strings of digital instructions.

2-2. Reduction of Parts Count
The use of digital-to-analog converters built into the ICs,
allowing them to be controlled by software, has eliminated
or reduced the requirement for many discrete parts such as
potentiometers and trimmers, etc.

The TW40F80 is a first wide TV with a double window system we introduce to North U.S.A. markets.

2-3. Quality Control
This central control of the adjustment data makes it easier to
understand, analyze, and review the data, thus improving
quality of the product.

The size of the main and sub screens separated in left and
right on the screen is the same as each other. So it is possible
to enjoy two programs or video and TV program at the same
time.
The sub screen is equipped wit 9 screen search function and
this is very convenient convenient to search a program you
desire.

Note:

***

Only the different points from the manual
“N5SS Chassis” with its file No. 026-9506
are described on this manual. For other parts
common with “N5SS Chassis”, please refer
to the original manual with its File No. 0269506.

5

3. SPECIFICATIONS
Model

GENERAL

CRT

TW56F80 TW40F80 TP61F90 TP61F80 TP55F80 TP55F81 TP50F90 TP50F60 TP50F61 TP50F50 TP50F51
7"

7"

7"

7"

7"

7"

7"

7"

7"

7"

7"

CRT Source

Hitach

Hitach

Hitach

Hitach

Hitach

Hitach

Hitach

Hitach

Hitach

Hitach

Hitach

Remote H/U

Intell

Univ

Intell

Univ

Univ

Univ

Intell

Univ

Univ.

A-Univ

A-Univ

RMT Keys

52 key

36 key

52 key

36 key

36 key

36 key

52 key

36 key

36 key

42 key

42 key

PIP

2-TN

2-TN

2-TN

2-TN

2-TN

2-TN

2-TN

2-TN

2-TN

1-TN

1-TN

ProLgc

Dy-Sur

Dy-Sur

Dy-Sur

ProLgc

Dolby Surr

ProLgc

Surround

Dsp4Ch

●

Dsp4Ch

Dsp4Ch

Dsp4Ch

Dsp4Ch

Dsp4Ch

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

28W

28W

28W

28W

28W

28W

28W

28W

28W

28W

28W

SAP
SOUND

C-Chassis

Cyclone
SBS
Audio (W)

Center

+20W

20W

Rear

+20W

20W

20W

20W

20W

20W

Comb-Filter

3D-Y/C

3D-Y/C

3D-Y/C

3D-Y/C

DIG

DIG

DIG

DIG

DIG

DIG

DIG

●

●

●

●

Scan-Modul

●

●

●

●

●

●

●

●

●

●

●

VCC

●

●

Black-Expan

●

●

●

●

●

●

●

●

●

●

●

Color-D.E

●

●

●

●

●

●

●

●

●

●

●

Pic-Prefer

●

●

●

●

●

●

●

●

●

●

●

Color-Temp

●

●

●

●

●

●

●

●

●

●

●

Flesh-Tone

●

●

●

●

●

●

●

●

●

●

●

Nois-Reduce

●

●

●

●

●

●

●

●

●

●

●

Hori-Resolu

800

800

800

800

800

800

800

800

800

800

800

Fav-Channel

●

●

●

●

●

●

●

●

●

●

●

Ch-Label

●

●

●

●

●

●

●

●

●

●

●

3-Language

●

●

●

●

●

●

●

●

●

●

●

Clock

●

●

●

●

●

●

●

●

●

●

●

Ch-Lock/Off

●

●

●

●

●

●

●

●

●

●

●

C.Caption

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

OTHERS

PICTURE

DQF

●

TERMINAL

EDS
New-OSD

●

S/Sight

●

●

●

20W

●

●
●

S-Video In

1+1

1+1

1+1

1+1

1+1

1+1

1+1

1+1

1+1

1

1

AV-In/Out

1+2/1

1+2/1

1+2/1

1+2/1

1+2/1

1+2/1

1+2/1

1+2/1

1+2/1

2/1

2/1

Front-Term

●

●

●

●

●

●

●

●

●

A(Var)-Out

●

●

●

●

●

●

●

●

●

●

●

2RF-Term

●

●

●

●

●

●

●

●

●

SPK-Term

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

New

New

New

New

●

PIP Audio
C-Ch-Input

●

ACCE

E/Jack
S/S-Jack

●

IR-B & 75W

●

Adapter

●

●

●
●

●

●

●

●

●

●

●

●

Rod-Antenna
SPK-Box
EZ RMT

*

●

Cabinet

●
●
TW56D90 40W30E

●

●

●

TP61E90 TP61E80 TP55E80 TP55E81

6

New

4. FRONT VIEW

POWER indicator

POWER

POWER button
Press to open
the door.

ANT / VIDEO button **
ENTER button
Behind the door

S-VIDEO

VIDEO

ANT/
VIDEO

AUDIO
L/MCNO

R

IN-VIDEO 3

VOLUME

DEMO

ENTER

MENU

MENU button

VIDEO 3 INPUTS

CHANNEL

CHANNEL
/
/
buttons

DEMO button
VOLUME
/
/
buttons

Fig. 1-1
Note: [No] Owner's manual page.

7

buttons

buttons

5. REAR VIEW

TV front

Behind the door
S-VIDEO

VIDEO

AUDIO
L/MCNO

R

IN-VIDEO 3

VIDEO / AUDIO INPUT jacks (VIDEO 3)

S-VIDEO INPUT jack (VIDEO 3)

Fig. 1-2

S-VIDEO INPUT jack
(VIDEO 1)

TV rear

VARIABLE AUDIO
OUTPUT jacks
ANT (75 ½)
S-VIDEO

AMP

Y

VIDEO
TV
(+)

(+)

(Ð)

(Ð)

C4
L

L
VIDEO
AUDIO
AMP

VIDEO/AUDIO

VIDEO

AUDIO

R
R

EXT SPEAKER
EXT

AMP
L VAR
ACC

R

R

INT

MAIN SPEAKER

VIDEO1 VIDEO2
N

VIDEO / AUDIO
INPUT jacks
(VIDEO 1)

EXTERNAL
SPEAKER
terminal
MAIN
SPEAKER
switch

Fig. 1-3

8

DVD
CUT

VIDEO /
AUDIO
OUTPUT
jacks

VIDEO / AUDIO
INPUT jacks
(VIDEO 2)
DVD INPUT
jacks

6. REMOTE CONTROL VIEW

Aim at the remote sensor on the TV

RECALL* [ 26 ]
TIMER* [ 38, 39 ]
TV / CABLE / VCR switch [ 15 ]
Set to " TV " to control the TV.

PIC -SIZE

TV
CABLE
VCR

TV/VIDEO

RECALL

POWER

MUTE

POWER [ 20 ]
MUTE* [ 26 ]

TV / VIDEO* [ 55 ]

1

2

3

4

5

6

7

8

9

CHANNEL

CH

CH RTN

100
EDS

0

ENT

ADV/
POP CH

VOL

POP CH

MENU

FAV

* [ 40 ]

RESET

FAV

ENTER

EXIT

ADV/
POP CH

RESET * [ 33 ]

STOP SCURCE

REC

CH SEARCH

PLAY POP

TV/VCR

REW

STILL

/

[ 25 ]

MENU [ 18 ]
POP CH

* [ 46 ]

POP functions* [40]
(For " TV " and " CABLE " positions)

VOLUME

¥

ENTER [ 19 ]
FAN

[ 25 ]

CH RTN* [ 26 ]

Channel Number* [ 25 ]

EDS* [ 27 ]

/

/
FAN

/

* [ 40 ]
/

[ 18 ]

* [ 46 ]

EXIT * [ ON ]
Owner's Manual page

FF

SWAP

TOSHIBA

* These function do not have
duplicate locations on the TV.
They can be controlled only by
the Remote Control.

Fig. 1-4
Note: [No] Owner's Manual page.

9

5

10

5

-2 : CRT-D(G)

-3 : CRT-D(B)

10 : DIGITAL
CONVER

5

FOCUS PACK

5 - 5 : FRONT-CON

9 POWER STARSIGHT
(TW56F80 ONLY)

-1 : CRT-D(R)

5 - 6 : SVM

5 - 4 : FRONT-LED

294
294
294

330

6

: POWER 1

-3: CRTÐD(B)
-4: FRONT LED

5
5

6

-2: CRTÐD(G)

5

5

5

F.B.T
J-BOX

Fig. 1-5

1pc

-2: FRONT SURROUND

7

2pcs

: POWER S.S

249

4pcs

: SW DVD

4
- 3 : DPC

-2:
7 FRO.
SURR

2pcs

CONVER

: DIGITAL

242

2pcs

:DUAL

2pcs

:3D Y/C

4pcs

:MAC

12

YCS

FACED

1pcs

:SIARSIGHT

242

CHIP SINGLE FACED

6pcs

:AUDIO LIVE

4 - 1 : A/V

11 - 6
: DUAL

330

2pcs

:DOLBY PRO

7 - 1: NEW OSD

15 : STARSIGHT

TW56F80 ONLY

CHIP DOUBLE FACED

16

242

CHIP DOUBLE FACED

15

14

(chip)

14 : AUTOLIVE
13 :WAC

1 : MAIN

CHIP DOUBLE

13

189

CHIP DOUBLE FACED

12

242

CHIP DOUBLE FACED

11

242

CHIP DOUBLE FACED

10

4 - 2 : SPEAKER

8 : SW DVD

DOLBY
PRO
16

2 : DEFLECTION

TW56F80 ONLY

9

8

249

TW56F80 ONLY

-1: NEW OSD

7

2pcs

: NEW OSD/
FRONT SURROUND

REAR ANP
(TW56F80 ONLY)

7

249

CENTER AMP
(TW56F80 ONLY)

To CRT

-6: SVH

-5: FRONT CON

: POWER 1

249

-1: CRTÐD(R)

CRT-1pcs
D/FRONT/SHV

330

-2: SPEAKER

4

:

-1: A.V

4

1pcs

: AV.EXT SPK

249

5

5

4

To FOCUS
PACK

3 : CONVERTER/POWER 2

1pc

3 : CONV / POWER2

330

1pc

2 : DEFELECTION

330

1pc

1 : MAIN

PC BOARD

165
249
165

165
165
249

160
139
155
139

139
126
113

TUNER DOLBY DSP F.SUR COHB FDS N.OSD STARSIGHT
MODE1
2
TW40F80
3DYC
TW56F80
PRO 4CH
3DYC
2

7. CHASSIS LAYOUT

8. CONSTRUCTION OF CHASSIS
A110

A505
BIDT2
4x12 2pcs

A110B
2pcs

A401
A522
BIDT2
4X12 18pcs

K601
A126
A520
PP 5x18
4pcs
A110A

A101
A517
PBI 4X16
8pcs

A512
BIDT2
4x12 6pcs

A517

A201

A353

A351

Z410

A902

B202
A127

A521
BRT TBS 4x16
2pcs
A502
PMM 4x16
4pcs

A128
W661~
W664

PMM 4x16
A205

A506 2pcs
BRB TBS
4x16 4pcs

A501
BTA 4x16 16pcs

A515
PMM 4X16
4pcs

A106
A508
BIDT2
4x12 2pcs

A516
PMS 3.8x28
3pcs

K511
A523
PMM 4x16
2pcs

A202
A102

A509
BTA 4x16 4pcs
A107

A511
PP4x14
4pcs

K103

A519
BIDT2
4x12
5pcs

L462~
L464

L472~
L474

A503
PMM
4x16
8pcs

A105
A104
A105

A510
BRBTB
5x16
4pcs
A104

A508
BIDT2
4x12
4pcs
A513
BIDT2
4x12

V901R
V902G
V903B

A108

Fig. 1-6

11

SECTION II: TUNER, IF/MTS/S. PRO MODULE
1. CIRCUIT BLOCK
IF/MTS/S.PRO Module MVUS34S
EL466L
Tuner

VIF/SIF
Circuit

SAW
Filter

SIF
output

Sound
Multiplex
Circuit

S.PRO Circuit

RF AGC
C-IN
R-IN L-IN
TP12
Video output

TV
R-OUT

To A/V switch circuit

AFT output

TV
L-OUT
R-OUT

C-OUT
L-OUT (L+R)
-OUT

Fig. 2-1 Block diagram

1-1. Outline
(1)

(2)
(3)
(4)

(5)

(5)

RF signals sent from an antenna are converted into intermediate frequency band signals (video: 45.75 MHz,
audio: 41.25 MHz) in the tuner. (Hereafter, these signals are called IF signals.)
The IF signals are band-limited in passing through a
SAW filter.
The IF signals band-limited are detected in the VIF
circuit to develop video and AFT signals.
The band-limited IF signals are detected in the SIF circuit and the detected output is demodulated by the audio multiplexer, developing R and L channel outputs.
These outputs are fed to the A/V switch circuit.
A sound processor (S.PRO.) is provided.

1-2. Major Features
(1)

The VIF/SIF circuit is fabricated into a small module
by using chip parts considerably.

(2)

As the tuner, EL466L that which contains an integrated
PLL circuit is employed.

(3)

Wide band double SAW filter F1802R used.

(4)

FS (frequency synthesizer) type channel selection system employed.

12

VIF/SIF circuit uses PLL sync detection system to
improve performances shown below:
•

Telop buzz in video over modulation

•

DP, DG characteristics (video high-fidelity reproduction)

•

Cross color characteristic (coloring phenomenon
at color less high frequency signal objects)

(6)

HIC SBX1637A-22 is used in the audio multiplexer
circuit to minimize the size with increased performance.

(7)

As a sound control processor, TA1217N is used. I2Cbus data control the DAC inside the IC to perform
switching of the audio multiplexer modes.

1-3. Audio Multiplex Demodulation Circuit

Then, both are fed to the matrix circuit. At the same time,
each of the stereo pilot signal fH and the SAP pilot signal
5fH is also demodulated to obtain an identification voltage.
With the identification voltage thus obtained and the user
control voltage are used to control the matrix.

The sound multiplex composite signal FM-detected in the
PIF circuit enters pin 12 of HIC (hybrid IC) in passing
through the separation adjustment VR RV2 and amplified.
After the amplification, the signal is split into two: one enters a de-emphasis circuit, and only the main signal with the
L-R signal and a SAP signal removed enters the matrix circuit. At the same time, the other passes through various filters and trap circuits, and the L-R signal is AM-demodulated, and the SAP is FM-demodulated.

The audio signals obtained by demodulating the sound multiplex signal develop at pin 10 and 11 of HIC and develop
the terminals of 12 and 14 of the module.

MVUS34S

MPX
Out
9

Monitor the input
pin for multiplex
sound IC

TV
TV
DAC-out1
R-Out (SURR ON/OFF) L-Out
11

10

Stereo 0V
Other 5V

12

SAP 0V

13

14

DAC-out2
(RFSW)
15

OFF 0V

RF1

0V

ON

RF2

9V

Other 5V

9V

TV waveform detection TV waveform detection
output (R)
output (L)
To AV select circuit

Fig. 2-2 Block diagram of MVUS34S
Note:
Table 2-1 Matrix for broadcasting conditions and
reception mode

Of the mode selection voltages, switching voltages for STE,
SAP, MONO do not output outside the module.

Output
OSD display
Broad- Switching
12 pin 14 pin
casted mode
Stereo SAP
(R)
(L)
Stereo STE
SAP
MONO
Mono STE
SAP
MONO

R
R
L+R
L+R
L+R
L+R

L
L
L+R
L+R
L+R
L+R

Stereo STE
+
SAP
SAP MONO

R
SAP
L+R

L
SAP
L+R

Mono
+
SAP

L+R
SAP
L+R

L+R
SAP
L+R

STE
SAP
MONO

•
•
•
–
–
–

•
•
•
–
–
–

–
–
–
–
–
–

They are used inside the module to control the BUS.

• •
•
•
•
•
•

: Available, – : Not available

13

1-4. A.PRO Section (Audio Processor)

All these processing are carried out according to the BUS
signals sent from a microcomputer.

The S.PRO section has following functions.

Fig. 2-3 shows a block diagram of the A.PRO IC.

(1)

Woofer processing (L+R output)

(2)

High band, low band, balance control

(3)

Sound volume control, cyclone level control

(4)

Cyclone ON/OFF

TA1217N

27 29 22 32 36

1

Lin

30

9

8

34

28

26

L out

25

R out

18

C out

10

W out

BALANCE
Rin
Cin

Win

30

TONE CONTROL
Center
LEVEL

2

3

VOLUME

Woofer
LEVEL

LPF

17
16
I/O

15
14

SDA

13

20
D/A
CONV

2

I C
SCL

21
4

R-in

C-in

From From
A/V Dolby

L-in

From
A/V

5

7

6

SCL

SDA

W-out O-out

31

24

23

22

19

L-out

to Q670 to Q640 to Q670

to Q670

Via QS101

Fig. 2-3 A.PRO block diagram

14

12

SAP Ident.

11

STE Ident.

Configuration of the audio circuit and signal flow are given
in Fig. 2-4

A/V PCB
VIF+MTS+S.PRO
MODULE
R 12
L 14
R

L

VIDEO 1
VIDEO 2
OR
DVD
VIDEO 3
(FRONT INPUT)

R

R

L

L

FOR POP
IF MODULE

ICV01
EQ

6 R

ER

7 L

11 L
13 R
3 L
9 R
15 L
17 R

MOTHER
TV

VIDEO 1

L 29

CHILD
TV

R 31

PIP
OUTPUT

L 2

L

R 1

R

AUDIO
PIP OUT
(AUDIO) (TW40F80 NOT USE)

VIDEO
OUTPUT
TERMINAL

VIDEO 2

VIDEO 3

R OUT 25

R 35

AS

L 37

AR

FRONT
SURROUND
UNIT

R L
VARIABLE
AUDIO OUTPUT
TERMINAL

Q601

VIF+MTS+A.PRO
MODULE

AI
AJ

Fig. 2-4

15

16 R
18 L

R
+

R

2

11

5

7

W OUT 22
L OUT 24

+

L

L

2. POP TUNER
Label
Name
Lot No.

1

TUNER
SECTION

SAW
FILTER

15

VIF/SIF
CIRCUIT

RF AGC

VIDEO
AUDIO
AFT
OUTPUT OUTPUT OUTPUT

Fig. 2-5

2-1. Outline
The POP tuner (EL922L) consists of a tuner and an IF block
integrated into one unit. The tuner receives RF signals induced on an antenna and develops an AFT output, video
output, and audio output.
The tuner has receive channels of 181 as in the tuner for the
main screen and it is also controlled through the I 2C-bus.
As the IC for the IF, a PLL complete sync detection plus
audio inter carrier system are employed.

Terminal No.

Name

1

NC

2

32V

3

S-CLOCK

4

S-DATA

5
6

NC
ADDRESS

7

5V

8

RF AGC

9

9V

10
11

AUDIO
GND

12

AFT

13

NC

14

GND

15

VIDEO

Fig. 2-6 Tuner terminal layout

16

SECTION III: CHANNEL SELECTION CIRCUIT
1. OUTLINE OF CHANNEL SELECTION CIRCUIT SYSTEM
The channel selection circuit in the N5SS chassis employs
a bus system which performs a central control by connecting a channel selection microcomputer to a control IC in
each circuit block through control lines called a bus. In the
bus system which controls each IC, the I2C bus system (two
line bus system) developed by Philips Co. Ltd. in the Netherlands has been employed.

POP and Double Window signal processing (QY03), IC for
closed caption control (QM01), IC for WAC control (QX01),
IC for 3D-YCS (QZ01), IC for AUTOLIVE (QK06).

The ICs controlled by the I2C bus system are: IC for V/C/D
signal processing (Q501), IC for A/V switching (QV01), IC for
non volatile memory (QA02), Main and sub U/V tuners (H001,
HY01), IC for deflection distortion correction (Q302), IC for

2. The microcomputer does not have the closed caption
function, but controls separate IC for closed caption.

Differences from N5SS chassis are as follows;
1. On-screen function inside microcomputer is used. Separate IC is not used for on-screen.

3. The system uses two channels of I2C bus. One is only
for non-volatile memory.

2. OPERATION OF CHANNEL SELECTION CIRCUIT
Toshiba made 8 bit microcomputer TLCS-870 series for TV
receiver, TMP87CS38N-3320 is employed for QA01.

(4)

With this microcomputer, each IC and circuit shown below
are controlled.
(1)

•
•

•

Adjustments for uni-color, brightness, tint, color
gain, sharpness and PIP uni-color

(5)

Setting of adjustment memory values for subbrightness, sub-color and sub-tint, etc.
Setting of memory values for video parameters such
as white balance (RGB cutoff, GB drive) and
gcorrection, etc.

(6)

Setting of video parameters of video modes (Standard, Movie, Memory)

Performs source switching for main screen and sub
screen

Sets adjustment memory value for vertical amplitude, linearity, horizontal amplitude, parabola, corner, trapezoid distortion.

CONTROL OF POP & Double Window SIGNAL PROCESS IC (QY03 Toshiba TC9092AF, QY91 Sony
CXP85116B-514Q)
•

(7)

A desired channel can be tuned by transferring a
channel selection frequency data (divided ratio data)
to the I2C bus type frequency synthesizer equipped
in the tuner, and by setting a band switch data which
selects the UHF or VHF band.

CONTROL OF DEFLECTION DISTORTION CORRECTION IC (Q302 Toshiba TA8859P)
•

CONTROL OF A/V SWITCH IC (QV01 Toshiba
TA1218N)
•

Controls ON/OFF and 9 pictures serch of POP.

CONTROL OF CLOSED CAPTION/EDS (QM01
Motorola XC144144P)
•

Controls Closed Caption/EDS.

Performs source switching for TV and three video
inputs

(8)

CONTROL OF NON-VOLATILE MEMORY IC
(QA02 Microchip 24LC08BI/P)

(9)

•

Memorizes data for video and audio signal adjustment values, volume and woofer adjustment values, external input status, etc.

(10) CONTROL OF VERTICAL AMPLITUDE (QK06
Toshiba TMP87CM36N)

•

Memorizes adjustment data for white balance (RGB
cutoff, GB drive), sub-brightness, sub color, sub
tint, etc.

(11) CONTROL OF OSD (Do not I2C BUS) (QR60 Fujitsu
MB90091)

•

Memorizes deflection distortion correction value
data adjusted for each unit.

•
(3)

•

CONTROL OF VIDEO/CHROMA/DEF SIGNAL
PROCESS IC (Q501 Toshiba TA1222AN)
•

(2)

CONTROL OF U/V TUNER UNIT (H001 Toshiba
ELA12L, HY01 Toshiba EL922L)

CONTROL OF WAC (QX01 Toshiba TC9097F)
•

CONTROL OF 3D-YCS (QZ01 Toshiba TC9086F)
•

•

•

17

Controls Wide Aspect.
Controls ON/OFF of 3 Dimension Y/C separator.

Controls Wide Mode.

Controls of OSD Menu.

3. MICROCOMPUTER
Microcomputer TMP87CS38N-3320 has 60k byte of ROM
capacity and equipped with OSD function inside.
The specification is as follow.

•

Self diagnosis function which utilizes ACK function of
I2C is equipped

•

Function indication is added to service mode.

•

Remote control operation is equipped, and the control
by set no touch is possible. (Bus connector in the conventional bus chassis is deleted.)

•

Substantial self diagnosis function

•

Type name : TMP87CS38N-3320

•

ROM : 60k byte

•

RAM : 2k byte

•

Processing speed : 0.5m s (at 8MHz with Shortest command)

(1) B/W composite video signal generating function
(micom inside, green crossbar added)

•

Package : 42 pin shrink DIP

•

I2C-BUS : two channels

(2) Generating function of audio signal equivalent to
1kHz (micom inside)

•

PWM : 14 bit x 1, 7 bit x 9

•

ADC : 8 bit x 6 (Successive comparison system, Conversion time 20ms)

(3) Detecting function of power protection circuit operation
(4) Detecting function of abnormality in IIC bus line

2

IIC device controls through I C bus. (Timing chart : See Fig.
3-1)
• LED uses big current port for output only.
•

For clock oscillation, 8MHz ceramic oscillator is used.

•

I2C has two channels. One is for EPROM only.

(5) Functions of LED blink indication and OSD indication
(6) Block diagnosis function which uses new VCD and
AV SW

SDA
SCL

1-7
Start
condition

Address

8

9

R/W

Ack

1-7

8
Data

Approx.180µS

9
Ack

8

1-7
DATA

9
Ack

Some device may have no data,
or may have data with several
bytes continuing.

Fig. 3-1

18

Stop
condition

4. MICROCOMPUTER TERMINAL FUNCTION

TMP87CS38N3320 (QA01)

42

VDD

I

41

ACP

P32

I

40

SS VD

P42 (PWM2)

P57

I

39

I 2C STOP

P43 (PWM3)

SDA0

IO

38

SDA1

O

37

SCL1

(TC3)P31

I

36

SYNC AV1

P46 (PWM6)

(RXIN)P30

I

35

RMT IN

O

P47 (PWM7)

P20

I

34

EXT SP

10

I

P50 (PWM8/TC2)

RESET

I

33

RESET

SCL0

11

O

P51 (SCL1)

XOUT

O

32

XOUT

SDA0

12

IO

P52 (SDA1)

XIN

I

31

XIN

SYNC VCD

13

I

P53 (AINO/TC1)

TEST

I

30

GND

PIPRST

14

0

P54 (AIN1)

0SC2

O

29

0SC1

AFT2

15

I

P55 (AIN2)

0SC1

I

28

0SC2

AFT1

16

I

P56 (AIN3)

VD

I

27

VSYNC

KEY-A

17

I

P60 (AIN4)

OSD RESET

0

26

OSD RESET

KEY-B

18

I

P61 (AIN5)

DATA

O

25

DATA

SGV

19

O

P62

BUSY

I

24

BUSY

SGA

20

O

P63

CS

O

23

CS

GND

21

VSS

CLK

O

22

CLK

VDD

GND

GND

1

BAL

2

I

P40 (PWM0)

P57

REM OUT

3

O

P41 (PWM1)

MUTE

4

O

SP MUTE

5

O

NC

6

O

P44 (PWM4)

SCL0

POWER

7

O

P45 (PWM5)

LED

8

O

SSRST

9

DVD CONT
IIC
-BUS

Fig. 3-2

19

IICBUS

<< MICROCOMPUTER TERMINAL NAME AND OPERATION LOGIC >>
No. Terminal Name
Function
In/Out
Logic
1
GND
2
3

BAL
REM OUT

4
5
6
7
8

MUTE
SP MUTE
DEF POW
POWER
LED

9
10
11

INPUT BALANCE
REMOTE CONTROL
SIGNAL OUT
SOUND MUTE OUT
SPEAKER MUTE

Out
Out

PWM out
Remote control output
Sound mute output
In muting = H

POWER ON/OFF OUT
POWER LED OUTPUT

Out
Out
Out
Out
Out

SS RST
DVD CONT
SCL0

STARSIGHT RESET
DVD CONTROL
IIC BUS CLOCK OUT

Out
Out
Out

12
13

SDA0
SYNC VCD

IIC BUS DATA IN/OUT In/Out
H SYNC INPUT
In

IIC bus data input/output 0
Main picture H. sync signal input

14
15
16

PIP RST
AFT2 IN
AFT1

PIP RESET

17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35

KEY A
KEY B
SGV
SGA
VSS
CLK
CS
BUSY
DATA
OSD RESET
VSYNC
OSC1
OSC2
TEST
XIN
XOUT
RESET
EXT SP
RMT IN

Reset = L
Sub tuner AFT S-curve input
Main tuner AFT S-curve
signal input
Local key detection: 0 to 5V
Local key detection: 0 to 5V
Test signal output In normal = L
Test audio output In normal = L
0V: Gounding voltage

36
37
38
39
40
41
42

SYNC AV1
SCL1
SDA1
I2C STP
SS VD
ACP
VDD

UV MAIN S-CURVE
SIGNAL
LOCAL KEY INPUT
LOCAL KEY INPUT
TEST SIGNAL OUT
TEST AUDIO OUT
POWER GROUNDING
CLOCK OSD
CHIP SELECT
BUSY OSD
DATA OSD
RESET OSD
DISPLAY CLOCK
DISPLAY CLOCK
TEST MODE
SYSTEM CLOCK
SYSTEM CLOCK
SYSTEM RESET
EXTERNAL SPEAKER
REMOTE CONTROL
SIGNAL INPUT
HSYNC INPUT
IIC BUS CLOCK OUT
IIC BUS DATA IN/OUT
IIC BUS STOP
STARSIGHT VD
NSYNC INPUT
POWER

Power control In ON = H
Power LED on-control
LED lighting = L
Reset = L
DVD = L, Other = H
IIC bus clock output 0

Out
In
In
In
In
Out
Out
—
Out
Out
In
Out
Out
In
Out
In
In
In
Out
In
In
In

GND fixed
System clock input
System clock output 8MHz
System reset input (In reset = L)
EXTERNAL = L, INT = H
In remote control pulse input = L

In
Out
In/Out
In
In
In
—

External H. sync signal input
IIC bus clock output 1
IIC bus data input/output 1
STOP = L
VSYNC for Starsight
AC pulse input
5V

Reset = L
VSYNC
4.5MHz

20

Remarks
0V

0V
0V

0V
0V
0V
At display on: Pulse
At display on: Pulse
At display on: Pulse
At display on: Pulse
Pulse
Pulse
Pulse
0V
8MHz pulse
8MHz pulse
5V
In reception of
remote pulse
Pulse
Pulse
Pulse
Pulse
5V

5. EEPROM (QA02)
Type name is 24LC08BI/P or ST24C08CB6, and those are
the same in pin allocation and function, and are exchangeable each other. This IC controls through I2C bus. The power
supply of EEPROM and MICOM is common. Pin function
of EEPROM is shown in Fig. 3-3.

EEPROM (Non volatile memory) has function which, in spite
of power-off, memorizes the such condition as channel selecting data, last memory status, user control and digital processor data. The capacity of EEPROM is 8k bits.

EEPROM(QA02)

A0

1

8 Vcc + 5V

A1

2

7 NC

A2

3

6 SCL

Vss

4

5 SDA

Device adress
GND

I2C-BUS line

Fig. 3-3

6. ON SCREEN FUNCTION
QR60 is controlled by the microprocessor QA01 with the
exclusive control signals of CLK, DATA, CS, BUSY, RESET.

The OSD system of TW40F80 employs the external OSD
IC (QR60, MB90091) to obtain high quality OSD.

QA01 Microprocessor

QR60 MB90091

CLK

22

54

SCLK

R OUT

59

CS

23

56

SCS

G OUT

60

BUSY

24

58

TRE

B OUT

61

DATA

25

55

SIN

OSD RESET

26

16

RESET

64

VOB2

VIDEO
(YM)

Fig. 3-4

21

7. SYSTEM BLOCK DIAGRAM
QA01
TMP87CS38N-XXXX
QA02
Memory
24LC08BI/P
SDA SCL
5
6

SDA 1 38
SCL 1 37
RMT 35
11 SCL 0
12 SDA 0

V.sync
pulse

Remote
controller
output

Audio mute
Speaker
mute

HO01
Main U/V tuner
ELA12L
SDA SCL

KEY-A 17
KEY-B 18

40 INT4
27 VSYNC

3

4
5

25
22
23
24
26

RST
VDD
GND
VSS
RMT OUT
POWER
ACP
LED

33
42
1
21
7
41
8

Remote
controller
light
receiving
unit
Key
switch
Power
supply
circuit

QR60
OSD
MB90091
CLK DATA CS BUSY
55
56
58
54
QX01
WAC
TC9097F
SDA SCL
60
59

Q501
VCD
TA1222AN
SDA SCL
27 28
HO02
IF/MPX/A.PRO
MVUS5345
SDA SCL
21 20

MUTE
SP MUTE

DATA
CLK
CS
BUSY
RESET

HY01
Sub U/V tuner
EL922L
SDA SCL

XIN 31
XOUT 32

8MHz
Clock

SGV 19
SGA 20

Signal
output

QV01
AV SW
TA1218N
SDA SCL
24 25

DPC unit
Main screen
SYNC-AV1 36
Sync det.
AFT1 IN 16
AFT det.
Sub screen
SYNC-AV2 13
Sync det.
AFT det.
AFT2 IN 2

DATA CLK

QZ01
YCS
TC9086F
SDA SCL
20 19

QH30
C/C,EDS
XC144144P
SDA SCL
14
15

QY91
DUAL microprocessor
SDA SCL

Q701
CONVER
T7K64
SDA SCL
44
43

QK06
AUTO LIVE
SDA SCL
40 39

Fig. 3-5

22

QY03
POP
TC9092F

8. LOCAL KEY DETECTION METHOD

17

18

SA08

SA01

SA06

SA02

SA05

SA03

SA07

SA04

Local key detection in the N5SS chassis is carried out by
using analog like method which detects a voltage appears at
local key input terminals (pins 17 and 18) of the microcomputer when a key is pushed. With this method using two
local key input terminals (pins 17 and 18), key detection up
to maximum 14 keys will be carried out.
The circuit diagram shown left is the local key circuit. As
can be seen from the diagram, when one of keys among SA01 to SA-08 is pressed, each of two input terminals (pins 17
and 18) developes a voltage VIN corresponding to the key
pressed. (The voltage measurement and key identification
are carried out by an A/D converter inside the microprocessor and the software.

Fig. 3-6 Local key assignment

Table 3-1 Local key assignment
Key No.

Function

Key No.

Function

SA-02

POWER

SA-01

DEMO START/STOP

SA-03

CH UP

SA-04

CH DN

SA-05

VOL UP

SA-06

VOL DN

SA-07

ANT/VIDEO, ADV

SA-08

MENU

23

9. REMOTE CONTROL CODE ASSIGNMENT

Custom codes are 40-BFH (TV set for North U.S.A.)

Custom codes are 40-BFH (TV set for North U.S.A.)
Code

Function

Applicable
to remote
control

Code

Applicable Contito TV set nuity

Function

Applicable
to remote Applicable Contito TV set nuity
control

00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH

0 Channel
1 Channel
2 Channel
3 Channel
4 Channel
5 Channel
6 Channel
6 Channel
8 Channel
8 Channel
100 Channel
ANT 1/2
RESET
AUDIO
PICTURE/FUNC
TV/VIDEO

50H
51H
52H
53H
54H
55H
56H
57H
58H
59H
5AH
5BH
5CH
5DH
5EH
5FH

PIP STILL
PIP ON/OFF
Do not use. Old type core power ON
PIP SWAP
PIC SIZE
DSP F/R
WIDE/SCROLL
CAPTION
EXIT
CYCLONE, SBS
SET UP
OPTION
SUB WOOFER UP
SUB WOOFER DOWN

10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH

MUTE
CHANNEL SEARCH
POWER
MTS
ADD/ERASE
TIMER/CLOCK
AUTO PROGRAM
CHANNEL RETURN
DSP/SUR (TV/CATV)
CONTROL UP
VOLUME UP
CHANNEL UP
RECALL
CONTROL DOWN
VOLUME DOWN
CHANNEL DOWN

80H
81H
82H
83H
84H
85H
86H
87H
88H
89H
8AH
8BH
8CH
8DH
8EH
8FH

MENU
EDS
ADV UP
ADV DWN

40H
41H
42H
43H
44H
45H
46H
47H
48H
49H
4AH
4BH
4CH
4DH
4EH
4FH

PIP LOCATE
PIP LOCATE
PIP LOCATE
PIP LOCATE
CARVER
SURROUND UP
SURROUND DOWN
VOCAL ZOOM
CHANNEL LOCK

90H
91H
92H
93H
94H
95H
96H
97H
98H
99H
9AH
9BH
9CH
9DH
9EH
9FH

PIP CHANNEL UP
PIP CHANNEL DOWN
PIP STILL/RELEASE
PIP ZOOM, ZOOM SIZE
PIP LOCATE (CH SEARCH)
PIP SOURCE

24

GUIDE
THEME
LIST
PIP CONTROL
ENTER/TUNE
PAGE UP
DATA UP
PAGE DN
DATA DN
CANCEL
REC

Do not use. Old type core power ON

NOISE CLEAN

PIP VOLUME UP
PIP CONTROL
PIP VOLUME DOWN

Custom codes are 40-BFH (TV set for North U.S.A.)
Code

Function

A0H
A1H
A2H
A3H
A4H

SUB-BRIGHT ADJUSTMENT
G. DRIVE ADJUSTMENT
B. DRIVE ADJUSTMENT

B0H
B1H
B2H
B3H
B4H
B5H
B6H
B7H

HORIZONTAL ONE LINE: SERVICE
DSP ON/OFF
TEXT-1
TV/PIP VIDEO CHANGE-OVER
CAPTION-1

Custom codes are 40-BFH (TV set for North U.S.A.)

Applicable Contito TV set nuty

Code

D0H
D1H
D2H Do not use. Old type core power ON
D3H
D4H
D5H
D6H
D7H PIP VIDEO ADJ.
D8H STILL, FRAME ADVANCE
D9H
DAH SPEED
DBH
DCH ZOOM
DDH
DEH
DFH

CUTOFF DRIVE 40H INITIALIZING,
HORIZONTAL ONE LINE
A5H R. CUTOFF ADJUSTMENT
A6H G. CUTOFF ADJUSTMENT
A7H B. CUTOFF ADJUSTMENT
A8H MEMORY ALL AREA INITIALIZE
A9H PIP BRIGHT ADJUSTMENT
AAH SUB CONTRAST ADJUSTMENT
ABH HOR, VER PICTURE POSITON ADJUSTMENT
ACH SUB COLOR ADJUSTMENT
ADH SUB TINT ADJUSTMNET
AEH ADJUSTMENT-UP
AFH ADJUSTMENT-DOWN

B8H
B9H
BAH
BBH
BCH

TV/CABLE CHANGE-OVER IN
SAME TIME ON MAN AND SUB
HOTEL SETTING MENU
DATA 4 TIMES SPEED UP
DATA 4 TIMES SPEED DOWN
CHANGE-OVER OF HOTEL/NORMAL
PIP CENTER

BDH
BEH
BFH

M MODE
CAPTON OFF
ALL CHANNEL PRESET

C0H
C1H
C2H
C3H
C4H
C5H
C6H
C7H
C8H
C9H
CAH
CBH
CCH
CDH
CEH
CFH

Function

E0H

PINCUTION/EW CORER (PARA/CNR)

E1H

VERTICAL S-CUVE CORRECTION/
VERTICAL M-CURVE
CORRECTION (VSC/FVC)

E2H
E3H
E4H
E5H
E6H
E7H
E8H
E9H
EAH
EBH
ECH
EDH
EEH
EFH
E0H
E1H
F2H
F3H
F4H
F5H
F6H
F7H
F8H
F9H
FAH
FBH
FCH
FDH
FEH
FFH

DIRECT WIDE 1
DIRECT FULL

25

HORIZONTAL WIDTH (WID/PARA)
TRAPEZOIDE CORRECTION (TRAP)
TEST TONE
DOLBY
3 DIMENTIONAL Y/C SEPARATION
DPC
STANDARD (HEIGHT LINEARITY) (VLIN/HIT)
WIDE (HEIGHT ® LINEARITY) (VLIN)
SCROOL
WIDE 1, 2, 3

Applicable Contito TV set nuty

9-1. Optional Setting for Each Model

D0

HEX

D7

D6

D5

D4

D3

D2

D1

D0

HEX

CN35F90

0

0

0

0

0

0

0

0

0

0

0

0

0

00H

0

0

0

0

0

0

CX35F70

1

0

1

0

1

02H

0

0

0

0

0

0

TW56F80

0

0

0

0

1

02H

0

0

0

1

1

1

TW40F80

1

0

1

0

1

92H

0

0

0

1

1

0

TP61F90

0

0

0

0

1

02H

0

0

0

1

1

1

TP61F80

0

0

1

0

1

12H

0

0

0

1

0

0

TP55F80

0

0

1

0

1

12H

0

0

0

1

0

0

TP55F81

0

0

1

0

1

12H

0

0

0

1

0

0

TP50F90

0

0

0

0

1

02H

0

0

0

1

0

1

TP50F60

1

0

1

0

1

92H

0

0

0

1

0

0

TP50F61

1

0

1

0

1

92H

0

0

0

1

0

0

*
*
*
*
*
*
*
*
*
*
*
*

*
*
*
*
*
*
*
*
*
*
*
*

00H

0

*
*
*
*
*
*
*
*
*
*
*
*

00H

0

*
*
*
*
*
*
*
*
*
*
*
*

0

CN35F95

*
*
*
*
*
*
*
*
*
*
*
*

NON0/DOLBY1

NOT USED

NOT USED

NOT USED

Normal 0/Free run 1

D1

CYC0/SBS1

D2

Normal 0/f0 STOP 1

D3

NOT USED

D4

SS/0 NONSS/1

D5

PP0/MP1

D6

NOT USED

D7

DSP0/SRD1

MODELS

NON0/3DYC

OPT1

NON0/CONV1

OPT0

• When the character generation is changed from
MB90091-107 TO MB90091-108, D5 bit of OPT0 in
the design data should be set to “1”.

26

MODE:
Fixed
Normal00
STD: 01
HRC: 10
1RC: 11

00H
00H
1CH
18H
1CH
18H
10H
10H
14H
10H
10H

10. ENTERING TO SERVICE MODE

12. SERVICE ADJUSTMENT

1. PROCEDURE

1. ADJUSTMENT MENU INDICATION ON/OFF :
MENU key (on TV set)

(1)
(2)

Press once MUTE key of remote hand unit to indicate
MUTE on screen.

2. During display of adjustment menu, the followings are
effective.

Press again MUTE key of remote hand unit to keep
pressing until the next procedure.

(3)

In the status of above (2), wait for disappearing of indication on screen.

(4)

In the status of above (3), press MENU (Channel setting) key on TV set.

a) Selection of adjustment item :
POS UP/DN key (on TV/remote unit)
b) Adjustment of each item :
VOL UP/ DN key (on TV / remote unit)
c) Direct selection of adjustment item

2. Service mode is not memorized as the last-memory.
3. During service mode, indication S is displayed at upper
right corner on screen.

R CUTOFF

:

1 POS (remote unit)

G CUTOFF

:

2 POS (remote unit)

B CUTOFF

:

3 POS (remote unit)

d) Data setting for PC unit adjustment

11.

TEST SIGNAL SELECTION

1. In OFF state of test signal, SGA terminal (Pin 20) and
SGV terminal (Pin 21) are kept “L” condition.

:

SUB COLOR

5 POS (remote unit)

:

SUB TINT

2. The function of VIDEO test signal selection is cyclically
changed with VIDEO key (remote unit).

4 POS (remote unit)

:

6 POS (remote unit)

e) Horizontal line ON/OFF :

VIDEO (on TV set)

f) Test signal selection :

VIDEO (remote unit)

* In service mode, serviceable items are limited.

Table 3-2
Test Signal No.

Name of Pattern

0

Signal OFF

1

All black signal + R single color (OSD)

2

All black signal + G single color (OSD)

3

All black signal + B single color (OSD)

4

All black signal

5

All white signal

6

W/B

7

Black cross bar

8

White cross bar

9

Black cross hatch

10

White cross hatch

11

White cross dot

12

Black cross dot

13

H signal (bright area)

14

H signal (dark area)

15

Black cross + G signal color

(3)

SUB CONTRAST

3. Test audio signal ON / OFF :

8 POS (remote unit)

* Test audio signal : 1 kHz
4. Self check display

:

9 POS (remote unit)

* Cyclic display (including ON/OFF)
5. Initialization of memory :
CALL (remote unit) + POS UP (on TV set)
6. Initialization of self check data :
CALL (remote unit) + POS DN (on TV set)
7. BUS OFF :
CALL (remote unit) + VOL UP (on TV set)

SGA (audio test signal) output should be square wave
of 1 kHz.
27

13. FAILURE DIAGNOSIS PROCEDURE
Model of N5SS chassis is equipped with self diagnosis function inside for trouble shooting.

13-1. Contents to be Confirmed by Customer

Table 3-3

Contents of self diagnosis

Display items and actual operation

A. DISPLAY OF FAILURE INFORMATION IN NO
PICTURE (Condition of display)

Power indicator lamp blinks and picture does not come.

1.

When power protection circuit operates;

1.

Power indicator red lamp blinks. (0.5 seconds interval)

2.

When I2C-BUS line is shorted;

2.

Power indicator red lamp blinks. (1 seconds interval)

If these indication appears, repairing work is required.

13-2. Contents to be Confirmed in Service Work (Check in self diagnosis mode)
Table 3-4
Contents of self diagnosis

Display items and actual operation

Contents of self diagnosis

Display items and actual operation

< Countermeasure in case that phonomenon always arises >

(Example of screen display)

B. Detection of shortage in BUS line.

SELF CHECK

C. Check of comunication status in BUS line.
D. Check of signal line by sync signal detection.
E.

Indication of part code of microcomputer (QA01).

F.

Number of operation of power protection circuit.

NO. 239XXXX
POWER: 000000

Part coce of QA01
Number of operation of
power protection circuit

E
F

BUS LINE: OK

Short check of bus line

B

BUS CONT: OK
BLOCK: UV

Communication check of
busline
V1 V2
QV01, QV01S

C
D

13-3. Executing Self Diagnosis Function
[CAUTION]

13-3-1. Procedure

(1)

(1)

Set to service mode.

(2)

Pressing “9” key on remote unit displays self diagnosis result on screen.

(2)

When executing block diagnosis, get the desired input
mode (U/V BS VIDEO1, 2, 3) screen, and then enter
the self diagnosis mode.
When diagnos other input mode, do again diagnosis
operation.

Every pressing changes mode as below.
SERVICE mode
(3)

28

SELF DIAGNOSIS mode

To exit from service mode, turn power off.

13-4. Understanding Self Diagnosis Indication
In case that phenomenon always arises. See Fig. 3-7 .

(Example of screen display)
SELF CHECK
NO. 239XXXX
POWER: 000000

Part coce of QA01
Number of operation of
power protection circuit

E
F

BUS LINE: OK

Short check of bus line

B

BUS CONT: OK
BLOCK: UV

Communication check of
busline
V1 V2
QV01, QV01S

C
D

Fig. 3-7

Table 3-5
Item
BUS LINE

Contents

Instruction of results

Detection of bus line short

Indication of OK for normal result, NG for abnormal
Indication of OK for normal result
Indication of failure place in abnormality
(Failure place to be indicated)
QA02 NG, H001 NG, Q501 NG, H002 NG, QV01 NG, Q302
NG, QY02 NG, HY01 NG, QD04 NG, QM01 NG, Q701 NG

BUS CONT

Communication state of bus line
Note:
The indication of failure place is only one place though
failure places are plural. When repair of a failure place
finishes, the next failure place is indicated. (The order of
priority of indication is left side.)

BLOCK: UV1
UV2
V1
V2

The sync signal part in each video signal
supplied from each block is detected.
Then by checking the existence or non of sync
part, the result of self diagnosis is displayed
on screen. Besides, when “9” key on remote
unit is pressed, diagnosis operation is first
executed once.

29

* Indication by color
• Normal block
• Non diagnosis block

: Green
: Cyan

13-4-1. Clearing method of self diagnosis result

White
Yellow

In the error count state of screen, press “CHANNEL DOWN”
button on TV set pressing “DISPLAY” button on remote unit.

Cyan
Green
Magenta
Red
Blue

CAUTION:
All ways keep the following caution, in the state of service
mode screen.

(COLOR BAR SIGNAL)
Color elements are positioned in sequence of

• Do not press “CHANNEL UP” button. This will cause
initialization of memory IC. (Replacement of memory
IC is required.)

high brightness.

• Do not initialize self diagnosis result. This will change
user adjusting contents to factory setting value. (Adjustment is required.)
13-4-2.

Method utilizing inner signal

(VIDEO INPUT 1 terminal should be open.)
(1)

With service mode screen, press VIDEO button on remote unit. If inner video signal can be received, QV01
and after are normal.

(2)

With service mode screen, press “8” button on remote
unit. If sound of 1 kHz can be heard, QV01 and after
are normal.

* By utilizing signal of VIDEO input terminal, each circuit
can be checked. (Composite video signal, audio signal)

30

14. TROUBLESHOOTING CHART
14-1. TV does Not Turned ON

TV does not turned on.
YES
Relay sound
NO

NG

Check of voltage at pin 7 of QA01
(DC 5V).
OK
Check power circuit.

8MHz oscillation waveform
at pin 32 of QA01.

NG

OK
Check OSC circuit.
Replace QA01.
NG
Pulse output at pins 37 and 38 of QA01.
OK
Voltage check at pin 32 of QA01
(DC 5V)

NG

OK
Check reset circuit.

Check relay driving circuit.

Replace QA01.

31

14-2. No Acception of KEY-IN

Key on TV

NG

Voltage change at pins 17, 18 of
QA01 (5V to 0V).
OK

Check key-in circuit.

Replace QA01.

Remote unit key

NG

Pulse input at pin 35 of QA01,
When remote unit key is pressed.
OK

Check tuner power circuit.

Replace QA01

14-3. No Picture (Snow Noise)

No picture

NG

Voltage at pins of +5V, and 32V.
OK

Check H001.

Check tuner power circuit.

32

14-4. Memory Circuit Check

Memory circuit check
NG
Voltage check at pin 8 of QA02 (5V).

OK

Check power circuit.

NG
Pulse input at pins 5 and 6 of QA02
in memorizing operation.
OK
Check QA01.
Replace QA02.
Note: Use replacement parts for QA02.

Adjust items of TV set adjustment.

14-5. No Indication On Screen
No indication on screen.
NG
Check of RESET at 5V.
OK
Replace QA01 or QR60 or QR63.
Check of CLK, CS, BUSY, DATA at
pin 22, 23, 24, 25 of QA01.
"H" = 5V or puls?
OK

NG

Replace QA01 or QR60.

Check of character signal at pin 59, 60, 61
of QR60 (5V(p-p)).

NG

OK
Replace QR60.
Check V/C/D circuit.

33

SECTION IV: DVD SWITCH CIRCUIT
1. DVD SWITCH BLOCK DIAGRAM

Q501 VCD
TA1222AN
Y 53
Q 52
I

51

Y

4

DVD SWITCH UNIT
QW01 TC4053BP
WAC UNIT

L

DUAL UNIT

Y

Y

Y

Q (B - Y)

Q

Q

I (R - Y)

I

H
Q 5

L
H

13 C
15 Y

I

6

L
Y C

I

H
ZY01 Y/C SEPARATOR
Sub Y.
Sub V.

Sub C.
"L" = Normal
"H" = DVD

QV01 AV SW
TA1218N

42

MAIN
36 Y

10

DVD CONTROL

Sub V.
2

I C BUS

34 C
21

VIDEO2/ Y, Cr, Cb
DVD

Insertion detection

VIDEO VIDEO
3
1

Fig. 4-1

34

QA01
MAICROPROCESSOR

2

I C BUS

2. OUTLINE
In this model, the DVD input terminals are provided in order to receive the color difference signals (Y, Cr, Cb) output from a DVD player.

The input identification for VIDEO 2 and DVD is carried
out by setting pin 21 of QV01 TA1218N (AV SW IC) from
“L” to “H” when the cable is connected to the Cb input terminal with a switch equipped.

The luminance (Y) signal input for DVD input uses the
VIDEO input terminal in common with the VIDEO 2 input.
The terminals for color difference signal inputs Cr (R – Y)
and Cb (B – Y) are used exclusively.

The main microprocessor QA01 sets pin 10 of QA01 from
“L” to “H” through I2C bus when pin 21 of AW SW IC
develops “H”.

Open : at Cb input
Cb to DVD SW unit
Cb input
RV28 100k
+9v

RV26
75
RV27
10k

21
QV01 TA1218N

Fig. 4-2

35

SECTION V: WAC CIRCUIT
1. OUTLINE
and pass a low pass filter and amplifiers in the same way as the
Y signal, and enter pins 1 and 78 of QX01 respectively.

A wide aspect conversion (hereafter called WAC) process (3/4
compression process in 4:3 mode and 1/2 compression process
on left screen in double window mode) is performed inside the
WAC unit (PB6348) in TW40F80.

The Y , I and Q signals entered are clamped by built-in clamp
circuit, converted into digital signals by the built-in A/D converter. Moreover, their read/write operations are rated up by twice
or 3/4 times to perform a compression process of 1/2 or 3/4
times inside the built-in line memory. And then, a black level
signal is added to the open area (right half, or both sides of
screen). Next, the signal is converted to an analog Y, I, and Q
signals by a built-in D/A converter and output from pins 17, 13,
and 9. Parameters of 1/2, 3/4 phase of the video signal, phase of
the side panel, etc. are controlled through I 2C bus, control signals of which enters from pins 7 and 8 of PX01.

Screen modes for TF40F80 contain THEATER WIDE1, THEATER WIDE 2, THEATER WIDE3, FULL, NORMAL and
DOUBLE WINDOW modes. The video signal compression is
carried out only when either the NORMAL or DOUBLE WINDOW mode is selected. In the modes other than the NORMAL
and DOUBLE WINDOW mode, the video signal input to WAC
unit is output without performing any process.
The screen in the DOUBLE WINDOW mode creates a single
screen by superimposing the left screen processed in the WAC
unit on the right screen processed in the DUAL unit.

Thus processed signals are fed to a low pass filter to remove
high frequency noises generated in QX01 and then fed to the
QX03 switching IC. The compressed signal and a not compressed
signal entered from PX01 are directly fed to QX03, and switched
by a signal showing compression/not compression (NCS = output from pin 61 of QX01 and fed to the receive unit through
pins 5, 6, and 7 of PX02.

On the left screen, the video signal sent is time-compressed to 1/
2 in horizontal direction to fit in the left half of the wide screen
with 16:9 aspect ratio. In this case, a black level of DC is attached on the right half of the screen in this circuit. However,
this is superimposed on the right screen, so nothing is visible on
the screen.

2-2-2. Clock Generation

In the normal screen, the video signal is 3/4 time-compressed
and side panels in the black level are added on sides of the screen.

The system clock for QX01 is generated by QX02 according to
an H reference signal supplied from pin 3 of PX02 and fed to
QX01 through QX19 and QX40. (The frequency is adjusted to
28.7 ± 0.2 MHz with LX18).

2. CIRCUIT OPERATION

The compressing operation is carried out by setting the write
clock to 1/2 or 3/4 times by the built-in VCO with the reading
clock fed to pin 47 of QX01.

2-1. Configuration
The WAC unit consists of a wide aspect conversion IC (QX01,
TC9097F, working as a central device), clock generation IC
(QX02, TA8667F), switch IC (QX03, TC4053BF), and peripheral circuits (LPF, AMP, emitter follower, etc.). The QX01
(TC9097F) contains an A/D converter, D/A converter, clamp circuit, VCO circuit, etc. and performs compression process, etc.
inside the IC for analog video signals entered according to controls through IIC bus, thus providing the signal as an analog signal.

2-2-3. Timing Pulse Generation
Moreover, the WAC unit generates following timing pulses.
(1)

VPout
Reference signal entered through pin 2 of PX02 enters pin
3 of QX01, and outputs at pin 8 of PX02 after delayed by
an amount required. The vertical reference signal is output in modes other than the normal and double window
and fed to the vertical circuit. Accordingly, the raster becomes an horizontal one when the unit is disconnected.

2-2. Operation
(2)
2-2-1. Signal Flow

HVBLK
This pulse is a timing pulse showing a black extension
mask period in the normal and double window modes. It
outputs at pin 1 of PX02 and enters pin 30 of Q501 in the
receive unit.

Fig. 5-1 shows a block diagram of this circuit. A Y signal entered through pin 6 of PX01 passes a low pass filter an a 6 dB
amplifier, and enters pin 3 of QX01. On the other hand, I and Q
signals enter through pin 4 and 5 of PX01,
36

Fig. 5-1 Wide aspect conversion unit block diagram (PB6348)

37
Q
Y

LPF
LX12 etc

AMP
QX06

YSI

60 IBD

3

78 QSI

8

QX11

QX13

ISI

SDA 2

I

LPF
LX13 etc

AMP
QX27

QX15

1

59 IBC

QX10

QX26

LX14 etc

QX29

LPF

7

5

Q IN

QX28

AMP

SCL 2

4

I IN

6

3

GND

PX01

Y IN

2

1

5V-3

9V-2

9

NCS 61

VDP 57

QSO

ISO 13

YSO 17

QX24 LX17 etc

LPF

QX22 LX16 etc

LPF

QX20 LX15 etc

QX21

QX25

QX23

Q TH

I TH

Q WA

I WA

QX03 TC4053BF

13 Y TH

3

1

11

10

9

5

2

12 Y WA

10

11

VMO 52
HRE 51

18

LPF

QX19

QX02 TA8667F

RCK 47

VDI 30

VBL 50

QX01
TC9097F

LX18

QX32

QX31

QX30

ADJ

QX18

PX02

8

7

6

5

4

3

2

1

VP OUT

QD

ID

YD

GND

HD IN

VD IN

HVBLK

• Pin Function

TDI3

TDI4

TDI2

TDI0

TDI1

NC

VSS(DIG)

NC

NC

VRA1

VDD1(AD)

NC

VBM

QSI

VBA

VSS1(AD)

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65

1

ISI

2

VRA2

BCP(TDI5) 64

3

YSI

SE42(TDI6) 62

4

NC

NCS(TDI7) 61

5

VBC

SDA 60

6

VRD2

SCL 59

7

VBD4

ACP(TMO0) 58

8

VDD3(DA2)

VDP(TMO1) 57

9

QSO

NC 63

ISL(TMO2) 56

10 NC

NC 55

11 VBD3

QSL(TMO3) 54

12 VSS3(DA2)

SPT(TMO4) 53

13 ISO

VMO(TMO5) 52

14 VRD1

HRF(TMO6) 51

15 NC

VBL(TMO7) 50

16 VDD2(DA1)

NC 49

17 YSO

HBL(TMO8) 48

18 VBD2

RCK 47

19 VSS2(DA1)

WCK 46

20 VBD1

VDD(DIG) 45

21 VSS4(VCO1)

NC 44

22 VBV

VSS5(VCO2) 43

VSS(DIG)

VDD5(VCO2)

HDF

TST2

NC

TST0

TST1

NC

NC

VDI

RESET

HDI

NC

VDD(DIG)

NC 42

VDD4(VCO1)

24 VFL1

VLM

23 NC

25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

Fig. 5-2 Pin function of TC9097F (QFP 80 pin)

38

VFL2 41

Table 5-1 Names and functions of TC9097F
No.

Name

I/O

1

ISI

I

I color signal input

2

VRA2

–

Reference voltage (low level) for AD1, AD2

3

YSI

I

Y signal input

4

NC

–

–

5

VBC

–

Bias for clamp 1

6

VBD2

–

Reference voltage for DA2, DA3

7

VBD4

–

Bias 2 (high level) for DA2, DA3

8

AVDD

–

Analog power

9

QSO

O

Q color signal output

10

NC

–

–

11

VBD3

–

Bias 2 (low level) for DA2, DA3

12

AGND

–

Analog ground

13

ISO

O

I signal output

14

VRD1

–

Reference voltage for DA1

15

NC

–

–

16

AVDD

–

Analog power

17

YSO

O

Y signal output

18

VBD2

–

Bias 1 (high level) for DA1

19

AGND

–

Analog ground

20

VBD1

–

Bias 2 (high level) for DA1

21

AGND

–

Analog ground

22

NC

–

–

23

VFV

I

Connected to VSS or VDD

24

VFL1

–

Connected to VDD

25

AVDD

–

Analog power

26

VLM

–

1/2 VDD for line memory

27

VDD

–

Digital power

28

HDI

I

Composite sync signal input

29

NC

–

–

30

VD1

I

V sync signal input

31

RESET

I

Reset input (Normally: High level, Reset: Low level)

32

NC

–

–

33

NC

–

–

34

TST0

I

Test mode setting (normally connected to VSS)

35

TST1

I

Test mode setting (normally connected to VSS)

36

TST2

I

Test mode setting (normally connected to VDD)

37

NC

–

–

Function

39

No.

Name

I/O

Function

38

HDF

I

Ext. H sync signal input

39

GND

–

Digital ground

40

AVDD

–

Analog power

41

VFL2

I

Loop filter for VCO2

42

NC

–

–

43

AGND

–

Analog ground

44

CKSEL

–

VDD

45

VDD

–

Digital power

46

WCK

–

Ext. clock input (memory write clock)

47

RCK

O

Ext. clock input (memory read clock)

48

HBL

–

H blanking signal

49

NC

–

50

VBL

–

V blanking signal

51

HRF

O

H AFC reference signal

52

VMO

–

H AFC mask signal

53

SPT

–

Side panel timing signal

54

QSL

–

Q signal select pulse

55

NC

O

–

56

ISL

–

I signal select pulse

57

VDP

–

V drive pulse

58

ACP

–

Later stage clamp pulse

59

SCL

–

I2C SCL signal input

60

SDA

–

I2C SDA signal input/output

61

NCS

I

Prefilter switch signal 1

62

SE42

–

Prefilter switch signal 2

63

NC

–

–

64

BCP

–

Prestage clamp pulse output

65

TD14

–

Test input (normally connected to VSS)

66

TD13

I

Test input (normally connected to VSS)

67

TD12

–

Test input (normally connected to VSS)

68

TD11

I

Test input (normally connected to VSS)

69

TD10

I

Test input (normally connected to VSS)

70

NC

–

–

71

GND

–

Digital ground

72

NC

I

73

NC

I

74

AVDD

I

Analog power

75

VRA1

–

Reference voltage for AD1, AD2

40

PRE
FILTER

Q PRE
FILTER

I

Y PRE
FILTER

CLAMP1

1/456

AD1

VBC

1/2

TIMING
CONTROLER

TDI

DA1

I2 C BUS
DECODER

TST

VSS3(DA2&3)

41

Fig. 5-3 TC9097F system block diagram
SCL

SDA

WCK

RCK

Analog ground

FILTER

–

FILTER

AGND

VFL2

80

VFL1

Bias for AD1, AD2

VSS5(VCO2)

–

VCO2

VBA

VSS4(VCO1)

79

VDD5(VCO2)

Q color signal input

SE42(TDI6)

I

BCP(TDI5)

QSI

1/2

78

VDD4(VCO1)

Bias for MPX, clamp 2

SCL

–

NCS(TDI7)

VBM

1/2

77

VSS(Digital)

–

VDP(TMO1)

–

ACP(TMO0)

NC

VSS(Digital)

76

VDD(Digital)

Q

I

Y

I/O

ISL(TMO2)

QSL(TMO3)

SPT(TMO4)

VMO(TMO5)

POST
FILTER

POST
FILTER

POST
FILTER

Name

VDD(Digital)

TEST
CIRCUIT

QSO
VDD3(DA2&3)

HRF(TMO6)

DA3

VRD2
VBD3

ISO

VDI

1/2

LINE MEMORY (624x8)

VBD2

HBL(TMO8)

1/2

AD2

DA2

YSO

VBL(TMO7)

VCO1

MPX
&
CLAMP2

LINE MEMORY (624x8)

VBD4

VRD1

HDI

VBM

VRA2

VBA

VRA1

LINE MEMORY (1248x8)

VBD1

HDF

QSI

ISI

YSI

VDD2(DA1)
VSS2(DA1)

LINE MEMORY (1248x8)

VSS1(AD)

VLM

VDD1(AD)

No.
Function

3. BLOCK DIAGRAM

4. WIDE ASPECT CONVERSION CIRCUIT FAILURE ANALYSIS
PROCEDURES
4-1. Left Screen Picture Failure in Normal Mode/Double Window Modes
(No Picture, Sync Distributed)

Picture fallure
(Normal/DW mode)

Super live
mode OK?

N

Output at pins 5 , 6 ,
7 of PX02 OK?

Y

Check circuits other
than WAC unit.

N

Y

Check around
of QX03.
LX18 adjustment
OK?

N

Readjustment

Y

I2 C bus pin 7 , 8
of PX01 OK?

N

I2 C bus line check.

Y

Is clock at pin 47
of QX01 OK?

N

Output at pin 3 (HD)
of PX02 OK?

Y

Y

Check around
QX02.

N
Check receive
circuit.

Signals at pins 5 , 6 , Y
7 of PX02 OK?

Receive circuit check.

N

QX01 input / output
OK?

N

Replace
E 2 PROM OK?

Y

Check associated
circuit (Tr.etc).

END

42

Replace QX01.

4-2. Raster Horizontal One

Horizontal one

Output at pin 8
of PX02 OK?

Y

Check V circuit.

N

Output at pin 2
of PX02 OK?

N

Check receive circuit.

Y

Is output OK
at I 2 C bus?

Check I 2 C
bus line.

N

Y

Data initlalization OK?

N

Replace QX01.

Y

END

4-2-1. Adjustment Method
(1)

Disconnect any video inputs

(2)

Open RX-40.

(3)

Connect frequency counter to QX19 emitter.

(4)

Adjust LX18 until frequency reading of “28.7 MHz
± 0.5 MHz” is obtained.

43

SECTION VI: DUAL CIRCUIT

1. OUTLINE
DUAL circuit performs the signal process, etc. on the sub
screen and is composed of the followings as shown in Fig. 61.

• 9-screen multi-search process
The sub screen process IC (TC9092AF) is the IC using the
programmable technology and can realize various functions
such as sub screen 1/2 compression, 9-screen multi-search,
etc. by switching the program.

• Video/color/deflection (V/C/D) process
• On-screen display (OSD) superimposing process
• Sub-screen process, memory

The 9-screen multi-search process is carried out by selecting
the channel on the right half of the wide screen with 16:9
aspect ratio and the picture images received are projected on
the 9 screens from the upper left screen in order.

• Main/Sub screen picture superimposing process
• Sub screen control microprocessor

The search is carried out by approx. every 2 seconds repeatedly. When the next picture image is searched, the picture
image on the previous screen becomes a still picture. When
the 9 screens are finished projecting (to the picture image on
the right bottom screen), the search operation is carried out
repeatedly from the upper left screen.)

2. PRINCIPLES OF OPERATION
DUAL circuit is composed of the following functions.
(1)

Double window sub screen 1/2 compression process

(2)

Sub screen still process

(3)

9-screen multi-search process

(4)

Main/Sub screen superimposing process by YIQ signal.

44

3. SYSTEM COMPONENT DIAGRAM OF DUAL UNIT

2M memory X2
MSM518221-30ZS

Y
From tuner
SY

Video/color/
deflection
process IC
µPC1832GT

SC

R- Y
B- Y

ON-screen
display super
impose
TC4W53F
MC74HC4053F

R- Y

Y

Sub screen
process IC

I

TC9092AF

Q

Main/Sub
picture
superimpose
MC74HC4053F

I2 C BUS

OSD

B- Y
Sub screen
control microprocessor

I
Q

CXP85116B-514Q

Control

Y

I

Q

Y

I

Q

Wide aspect
conversion
TC9097F

I2 C BUS
From main microprocessor

Fig. 6-1

45

Y

I

Q

To CRT
G

From tuner
SY

V/C/D IC

B

SC

TA1222N

R

4. CIRCUIT OPERATION
4-1. Video/Color/Deflection Process Section

Since the sync signal is added to the luminance signal, the
signal is input to pin 39 of QY01 (SYNC SEP IN) and the
sync signals of HD and VD are output to pins 10 and 11 of
QY01. The HD signal is waveshaped by QY42.

The video/color/deflection section is shown in Fig. 6-2.
The luminance signal is supplied from pin Y08 of PY01 and
its frequency bandwidth is limited by the low pass filter (LPF)
and then input to pin 36 of V/C/D IC (VIDEO IN). The Y
signal output from pin 12 of PY01 superimposes the character signal on the video signal by QY49 and QY44, and then
output to the sub screen process section.

The HD signal (WHD1, WHD2) is used as the horizontal
pulse for sub screen write and the VD signal (WVD) is as the
vertical pulse for sub screen write in the sub screen process
section.
In the sub screen microcomputer section, various kinds of
control signals (brightness, density, hue, etc.) are output from
the sub screen control microprocessor QY91 and the signals
are used for the level matching adjustment. So the setting for
the sub screen cannot be made by the user. Furthermore, the
OSD signal for OSD superimposing is output.

QY49 and QY44 work as the analog switches. When the
screen is displayed in DW, the switch operation is not carried out and the same signal as the input signal is output, and
when the 9-screen multi-search process is carried out, the
switch operation is carried out.

The sub screen process IC control program is stored in the
nonvolatile memory of the sub screen control microprocessor QY91 in order to control the sub screen process IC
(TC9092AF), and the data is sent via I2C bus.

The OSD signal superimposes the shade of character signal
by QY49 and the character signal by QY44 on Y signal.
On the other hand, the color signal is supplied from pin Y15
of PY01, limited its frequency bandwidth by the band pass
filter (BPF) and then input to pin 34 of QY01 (COLOR IN).
The color difference signals of the demodulated signal (R –
Y) and ( B – Y) are output from pins 13 and 14 of QY01. In
the same way as the Y signal, the (R – Y) and (B – Y) signals
are superimposed on the character signal with OSD signal
by QY44.
The GBR matrix circuit which converts the Y, R – Y and B –
Y signals into three primary color signal of G, B and R is
used to convert the (R – Y) and (B – Y) signals into I and Q
signals.
In the GBR matrix circuit, each G, B and R output is output
as G – Y, B – Y and R signals when the Y signal is not input.
Then the B – Y signal is converted to Q signal, R – Y to I
signal pseudically by turning the phase by an angle of 33°.
Thus, R – Y and B – Y signals are input to pins 18 and 19 of
QY01, and the output signals from pins 23 and 24 are developed as the I and Q converted signals pseudically. The amplitude of the signals is amplified by 6 dB amplifier of QY23
and the signals are output to the sub screen process section.

46

SCLP 50
Y13
Y14

SCL
SDA

47 SDA2

5
OSD
superimpose

QY01 µPC1832GT

49 SCL2 SDAP 48
BLK 46

V/C/D IC

QY44
MC74HC4053F

QY49
TC4W53F

Y OUT 12

7

9
1

12

B 43
COL 53
TIN 54

20 COLOR

R-Y OUT 13

5

21 TINT

B-Y OUT 14

2

CON 52

38 CONTRAST

fsc SEL 62

41 fsc SELECT
42 PAL/NTSC

PAL/NTSC 61

PIP VIDEO

L.P.F

Y

4
15

R-Y IN 18
B-Y IN 19
QY22 MM1031XMR

Control

Sub screen control
microprocessor

Y08

14

37 SUB COL.

S.COL 51

3.58 2

11

39 SYNC SEPA
IN
36 VIDEO IN

R OUT(I) 23

3

6dB. Amp

1

B OUT(Q) 24

3

6dB. Amp

1

I
Q

QY23 MM1031XMR
QY42 TC74HC123AF

Y15

PIP C

B.P.F

34 CHROMA IN

HD OUT 10

VD OUT 11

Fig. 6-2

47

1 1A

Waveform
shape

1Q 13
2Q 5

WHD2
WHD1
WVD

To Sub screen process section

PY01

OSD
OSD

QY91 CXP85116B-514Q

OSD
superimpose

Signal reception
circuit

I2 C BUS(SCL,SDA)

Sub screen microprocessor section

4-2. Sub Screen Process Section
The horizontal sync signal RHD for reading-out and the vertical sync signal RVD for reading out input to pins 75 and 77
of QY03 trigger the reading at 18.0 MHz which is created
by 2/3-multiplying 27.0 MHz developed in LY101and then
output as the analog signal.

The sub screen process section is shown in Fig. 6-3.
The Y, I and Q signals from the video/color/deflection process section are limited in their frequency bandwidth by the
LPF in the prceeding stage and input to pins 6, 13 and 15 of
QY03.

The Y, I and Q signals converted for the sub screen are output from pins 95, 100 and 97 of QY03. The output signals
are used for the input signals compressed by 1/2 in the horizontal direction in the double window mode and for the input signal compressed by 1/6 in the horizontal direction and
by 1/3 in the vertical direction in 9-screen multi-search mode.

The frequency of 18.5 MHz generated by LY102 is multiplied by 1/2 inside QY03. The Y signal is sampled by 9.25
MHz and the I and Q signals are sampled by 4.63 MHz (1/2
frequency to multiplex) and then the signals are converted
into 8-bit digital signals.
The horizontal sync signal WHD (the signal mixed with
WHD1 and WHD2 by QY43) for writing input to pins 21
and 20 of QY03 and the vertical sync signal WVD for trigger writing on the field memory QY10 and QY11.

Then the signals are smoothed by the LPF in the next stage
then input to the main/sub screen superimposing section.

QY03 TC9092AF
Sub screen process IC

Video/color/deflection process section

I
Q

L.P.F

6

L.P.F
L.P.F

I2 C BUS (SCL, SDA)

Y OUT 95

L.P.F

13 R-Y IN

R-Y OUT(I) 100

L.P.F

15 B-Y IN

B-Y OUT(Q) 97

L.P.F

Y IN

80 SDA
QY10, QY11
MSM518221-30ZS
WVD
WHD2
WHD1

1
2

OR
circuit

4

WHD

QY43
TC7S32F

20 FVS

MWD 0 48

21 FHS

MWD15 32

25 OSCSO
MRD 0 51
Date out

77 FVM
MRD15 65
75 FHM

Signal reception circuit

PY01

Y11
Y12

72 OSCMI

RVD
RHD

2M
memory
Date in

24 OSCSI
LY102

73 OSCMO
LY101

YS
Y01

Fig. 6-3 Sub screen process section

48

I
Q

YS

YS OUT 70

79 SCL

Y

To Main/Sub pictore superimposing
process section

Y

4-3. Main/Sub Screen Superimposing Section
The main/sub screen superimposing section is shown in Fig.
6-4.

In normal mode (with only the main screen picture displayed),
the YS signal voltage always goes low and the Y, I and Q
signals from the digital unit are developed at pins 15, 4 and
14 of QY48.

The sub screen Y, I and Q signals sent from the sub screen
process section and the main screen Y, I and Q signals sent
from the digital unit through the receive circuit and etnered
pins 3, 2, and 1 of PY02 are clamped at a same electrical
potential and the former are fed to pins 1, 3, 13 and the latter
fed to pins 2, 5 and 12 of QY48.

The Y, I and Q signals for the main/sub screens superimposed are developed at pins Y05, Y06 and Y04 of PY01 and
then supplied to the receive circuit.

QY48 MC74HC4053

From Sub screen
process section

Clump capacitor
Y

CY231

I

CY230

Q

CY232

1 IY (Y IN)
3 IZ (I IN)

YS

11 A Y COM (Y OUT) 15
10 B Z -COM (I OUT)
Clump capacitor

PY02

Signal reception
circuit

3
2
1

4

PY01

13 IX (Q IN)

YD

CY239

ID

CY240

QD

CY238

SCP

QY46
TC74HC4066AF

Waveform
shape

2 OY (Y IN)
5 OZ (I IN)
12 OX (Q IN)

QY47
TC74HC4066AF

4

3

4

9 Analog
SW
1

8

9 Analog
SW
1

8

5

6 13

4

9 C X-COM (Q OUT) 14

3

2

YOUT

5

Main/Sub picture
superimpose

2

6 13

Clump
pulse

Constant voltage
source E

Fig. 6-4 Main/Sub screen superimposing section

49

I
Q

Y05
Y06
Y04

Q501
TA1222N
Y
I
Q

53

43

51

42

52

41

R
G
B

To CRT

QY48 is an analog switch to feed the Y, I and Q signals for
either sub screen or main screen to pins 15, 4 and 14 by the
YS signal voltage fed to pins 9, 10 and 11. When the YS
signal develops high, QY48 selects the signals for the sub
screen and when low, QY48 selects the signals for the main
screen. Consequently, the signals for both the main and sub
screens are superimposed each other.

Signal reception
circuit

The Y, I and Q signals for the main/sub screens superimposed inside the receive circuit are entered to pins 53, 51 and
52 of Q501 (TA1222N) and then fed to CRT. The video
signal is processed in Q501 without distinguishing the signals for main and sub screens, so the high picture quality can
be obtained equally for both the screens.

The clamp circuit contains a clamp pulse waveshaping SCP
at pin 4 of PY02, analog switches for ever-voltage source E,
QY46 and QY47 and clamp capacitors CY230 ~ CY232,
CY238 ~ CY240.

3.58 / 4.43
PAL / NTSC

220pF

41

50

1

Fig. 6-5 QY01 mPC1832GT internal block diagram

820pF

2.2kΩ

2

1

4.7µF

2.7kΩ

8.2kΩ

5

6

+
22µF

35

Vcc

34

7

Vcc

Delay

fsc BPF

BLK

9

HD

10

HD, VD, blanking pulse,
killer output

Killer det.

8

0.22µF
33

32

1MΩ
1µF

VD

11

Contrast
control

Separate / Composite SW,
ACC amp., Sub color control

0.1µF

22µF

+

1000pF

Separate
/ color

Separate / composite SW

Separate / composite SW

50 / 60
0.1µF

AFC wave
form det.

500pF

4
0.015µF

H / V count

3

36

fsc
trap

+

330Ω

37

20kΩ
0.22µF

V. filter

38

20kΩ

Clamp

100Ω

0.1µF
0.1µF
Contrast Sub color
control control
Vcc
Vcc

Sync. sepa.

39

180kΩ

H. sync det.

40

+

321H VCO

Mode SW

42

43kΩ

+

1500pF 4.7µF

CVBS

4700pF

Y

12

LPF

B-Y

14

15

26

1MΩ

RGB output

+

0.1µF

0.22µF

17

20kΩ

24

G

20kΩ

Tint control

Color control

R

20

23

0.22µF 0.22µF
R-Y
B-Y

18

19

Color control

Tint control

PAL / NTSC
matrix

25

B

Y, R-Y, B-Y input clamp

22µF

Vcc

16

APC killer wave form det.
IDENT D det.

R-Y

13

27

3.58MHz / 4.43MHz
VCXO. PAL SW

29

1.8 KΩ 0.22µF

28

18
pF
1.8 KΩ

R-Y, B-Y
demodulation

30

18pF

4.43MHz 3.58MHz

Y, R-Y, B-Y output

Filter
fH Adj.

31

+

0.47µF
+ 6.8KΩ

0.1µF

21

22

0.1µF

Clamp pulse

5. TERMINAL FUNCTION, DESCRIPTION AND BLOCK DIAGRAM OF
MAIN IC

1

42

PAL/NTSC SW

32f m VCO felter 1

2

41

fsc SW

32f m VCO felter 1

3

40

H. sync det. filter

H.AFC filter

4

39

Sync sepa input

GND (sync)

5

38

Contrast control

fv 50/60 SW

6

37

Sab color control

Power supply (sync)

7

36

Composite video signal input

Color killer output

8

35

Power supply (color)

Blanking pulse output

9

34

Separati color input

HD pulse output 10

33

GND (color)

32

ACC filter

Y output 12

31

Io . filter

R-Y output 13

30

Color APC filter

B-Y output 14

29

fsc VCO input (4.43MHz)

GND (video) 15

28

fsc VCO input (3.58MHz)

Y input 16

27

fsc VCO output

Power supply (video) 17

26

Color killer filter

R-Y input 18

25

B output

B-Y input 19

24

G output

Color control 20

23

R output

Tint control 21

22

Clamp pulse input

VD pulse output 11

µPC1832GT

32f m VCO felter 1

Fig. 6-6 QY01 mPC1832GT pin layout

51

52

I2 C

H, V (Sub)

LC

B-Y

R-Y

Y

Sub screen
video input

AD

AD

CLAMP

Fig. 6-7 QY03 TC9092AF internal block diagram

DATA
REARRANGE
MENT
(W)

I2 C
INTERFACE

CLOCK
GENERATION
(SUB)

MPX

PICTURE
MEMORY
(2M BIT)

DATA
REARRANGE
MENT
(R)

CU
(CONTROL UNIT)

SUB SAMPLE PIT FILLING (C)

DELAY ADJUSTMENT (DAJB)

FRAME
SIGNAL
MULTIPLEX
SW

FRAME SIGNAL
GENERATION
(WAKU)

DA

YC DELAY
ADJUSTMENT
BETWEEN Y/C
(DAJA)

CLOCK GENERATION
(MAIN)

VERTICAL FOLDED
ELIMINATION
INTERPORATION FILTER
(1H MEMORY (12BIT)) (V)

TELTEXT DETECTION (J)
1H MEMORY (11BIT)

HORIZONTAL
FOLD SIGNAL
ELIMINATING
FILTER (HFA)

PROGRAM DATA MEMORY
(16k BIT + 3k BIT)

HORIZONTAL
INTERPORATION
FILTER (HFB)

FILTER FACTOR OPERATION/
GENERATION (KGEN)

B-Y

R-Y

Y

Ys

H, V (Main)

LC

RSTW

MWD15

MWD14

MWD13

MWD12

MWD11

MWD9

MWD10

VSS

MWD8

MWD7

MWD6

MWD5

MWD4

MWD3

MWD2

MWD1

VDD

MWD0

MRD0

50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31

WE 30
IE 29

51 MRD1
52 MRD2

CKW 28
VDD 27

53 MRD3
54 MRD4

VSS 26
OSCSO 25
OSCSI 24

55 MRD5
56 MRD6
57 MRD7

VDD 23
NFHS 22
FHS 21

58 MRD8
59 MRD9
60 MRD10

FVS 20
VDD 19
VSS 18

61 RMD11
62 RMD12
63 MRD13

ADDVSS 17
ADDVDD 16
RYIN 15

64 MRD14
TC9092AF

65 MRD15

(TOP VIEW)

66 RE

ADBIAS 14
RYIN 13

67 RSTR
68 CKR

ADVREFC 12
ADVDD 11

69 CKRI
70 YSOUT

CLAMPC 10
ADVSS 9

71 VSS
72 OSCMI

CLAMPY 8
ADVSS 7

73 OSCMO
74 VDD

YIN 6
ADVREFY 5
ADVDD 4

75 FHM
76 HFHM
77 FVM

DABIAS2 3
DABIAS3 2

80 SDA

DAVSS 1

DAVDD

DAVREFC

RYOUT

DAVSS

YOUT

DAVDD

DABIAS1

DAVREFY

NC

VDD

TESTAD

TEST1

RESET

ME

PROMRES

PROMCK

PROMDI

VSS

SDAINO

BYOUT

79 SCL

78 VSS

81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100

Fig. 6-8 QY03 TC9092AF pin layout

53

Table 6-1 QY03 TC9092AF pin list (No. 1)

No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50

Pin name
DAVSS
DABIAS3
DABIAS2
ADVDD
ADVREFY
YIN
ADVSS
CLAMPY
ADVSS
CLAMPY
ADVDD
ADVREFC
RYIN
ADBIAS
BYIN
ADDVDD
ADDVSS
VSS
VDD
FVS
FHS
NFHS
VDD
OSCSI
OSCSO
VSS
VDD
CKW
IE
WE
RSTW
MWD15
MWD14
MWD13
MWD12
MWD11
MWD10
MWD9
MWD8
VSS
MWD7
MWD6
MWD5
MWD4
MWD3
MWD2
MWD1
MWD0
VDD
MRD0

I/O

I
I

I
I
I

I
I
I
I
O

O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I

Pin function
D/A GND
D/A bias condenser connection terminal
D/A bias condenser connection terminal
A/D power supply
A/D Y reference condenser connection terminal
A/D Y input terminal
A/D GND
Y clamp bias condenser connection terminal
A/D GND
C clamp bias condenser connection terminal
A/D power supply
A/D reference condenser connection terminal
A/D R – Y input terminal
A/D bias condenser connection terminal
A/D B– Y input terminal
A/D digital power supply
A/D digital GND
Digital GND
Digital power supply
Sub screen vertical sync signal input
Sub screen horizontal sync signal input
Sub screen horizontal sync signal reversing input
Digital power supply
Oscillator connection terminal sub input
Oscillator connection terminal sub output
Digital GND
Digital power supply
Serial write clock output terminal
Input enable output terminal
Write enable output terminal
Reset write output terminal
Data output terminal
Data output terminal
Data output terminal
Data output terminal
Data output terminal
Data output terminal
Data output terminal
Data output terminal
Digital GND
Data output terminal
Data output terminal
Data output terminal
Data output terminal
Data output terminal
Data output terminal
Data output terminal
Data output terminal
Digital power supply
Data input terminal
54

Table 6-2 QY03 TC9092AF pin list (No. 2)

No.
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100

Pin name
MRD1
MRD2
MRD3
MRD4
MRD5
MRD6
MRD7
MRD8
MRD9
MRD10
MRD11
MRD12
MRD13
MRD14
MRD15
RE
RSTR
CKR
CKRI
YSOUT
VSS
OSCMI
OSCMO
VDD
FHM
NFHM
FVM
VSS
SCL
SDA
SDAINO
VSS
PROMDI
PROMCK
PROMRES
ME
RESET
TEST1
TESTAD
VDD
NC
DAVREFY
DABIAS1
DAVDD
YOUT
DAVSS
RYOUT
DAVREFC
DAVDD
BYOUT

I/O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
O
O
O
I
O
I
O
I
I
I
I
BID
O
I
O
O
I
I
I
I

I

O
O
I
O

Pin function
Data input terminal
Data input terminal
Data input terminal
Data input terminal
Data input terminal
Data input terminal
Data input terminal
Data input terminal
Data input terminal
Data input terminal
Data input terminal
Data input terminal
Data input terminal
Data input terminal
Data input terminal
Read enable output terminal
Read reset output terminal
Serial read clock output terminal
Memory read clock input
Ys signal output terminal
Digital GND
Oscillator connection terminal main input
Oscillator connection terminal main output
Digital power supply
Main screen horizontal sync signal input
Main screen horizontal sync signal reversing input
Main screen vertical sync signal input
Digital GND
I2C CK input terminal
I2C data I/O terminal
I2C data direction output terminal, Test output terminal
Digital GND
ROM data input terminal
ROM clock output terminal
ROM RESET output terminal
MEMORY polarity control input terminal
RESET input terminal
TEST input terminal
AD/DA TEST input terminal
Digital power supply
D/A Y reference voltage input terminal (4V)
D/A bias condenser connection terminal
D/A power supply
D/A Y output terminal
D/A GND
D/A R – Y output terminal
D/A C reference voltage input terminal (3V)
D/A power supply
D/A B – Y output terminal
55

Dout (X8)

OE

RE

Data - out
buffer (X8)

Serial

Read

RSTR

SRCK

Controller

512 Word serial read register (X8)
Read line buffer
Low-Half (X8)

Read line buffer
High-Half (X8)

256 (X8)

256 (X8)

71 Word
Sub-register (X8)
256K (X8)
Memory
Array

71Word
Sub-register (X8)

X
Decoder

256 (X8)
Write line buffer
Low-Half (X8)

Read/Write
and refresh
controller

Clock
oscillator

256 (X8)

Write line buffer
High-Half (X8)

512 Word serial write register (X8)

Data - in
Buffer (X8)

Serial

Write

Controller

Din (X8)

IE

WE

RSTW SWCK

VB3
Generator

Fig. 6-9 QY10/QY11 M518221-30ZS internal block diagram

WE
Din0
Din2

1

Din5

9

Din7

11

NC

Din1

SRCK

Serial read clock

6

Din3

WE

Write enable

8

Din4

RE

Read enable

10

Din6

IE

Input enable

12

RSTW

OE

Output enable

RSTW

Reset write

14

NC

RSTR

Reset read

16

RE

Din 0 – 7

Data input

18

Dout7

Dout 0 – 7

Data output

20

Dout5

VCC

Power supply (+5V)

Vss

VSS

Ground (0V)

22

NC

Not connected

24

Dout2

26

Dout0

28

SRCK

SWCK

13
15

OE

17

Dout6

19

Dout4

21

Dout3

4
5
7

23

Dout1

25

RSTR

27

Function

IE

3

Vcc

SWCK

Terminal name

2

28PIN ZIP

Fig. 6-10 QY10/QY11 M518221-30ZS pin layout
56

Serial write clock

SECTION VII: 3-DIMENSION Y/C SEPARATOR CIRCUIT
1. OUTLINE
The 3D YC separation circuit uses a comb filter with a frame
memory and ideally separates the Y (luminance) and color
signal for still parts of a picture, thus providing a clean picture without:
(1)
(2)

2-2. Circuit Description
Fig. 7-1 shows a block diagram of the YCS circuit.

Dot interference causing at border areas of color pictures.

(1)

A video signal sent through the AV switching circuit
passes the input terminal (DG) and enters the YCS unit.

(2)

The video signal entered is limited in its band width in
passing through an aliasing distortion elimination LPF
consisting of LZ22, etc. , and then enters pin 56 of
QZ01.

(3)

At the same time, a fsc (3.58 MHz) signal being oscillated in the video signal color IC (Q501, AN1222AN)
is fed to pin 28 of QZ01 and converted into a 4fsc
(14.32 MHz), a drive clock frequency inside the IC.

(4)

The video signal entered pin 56 of QZ01 is processed
inside the IC and a luminance (Y) signal is developed
at pin 48 of QZ01 and the color signal at the pin 51.

(5)

The Y signal developed at pin 48 of QZ01 passes a
LPF (LZ20, etc.) which eliminates the clock signal
component, amplified by a 6dB amplifier QZ21, etc.
and comes out from the DC terminal as the Y signal.

(6)

At the same time, the color signal developed at pin 51
of QZ01 passes a LPF (LZ21, etc.) which eliminates
the clock component, amplified by 6dB by QZ23, etc.
and comes out from DD terminal through a buffer of
QZ24 as the C signal.

(7)

QZ04 is generating a clock signal used to read and
write the digital data between QZ03 and QZ04 based
on the video signal.

Excess color in vertical direction.

However in a moving picture, as the picture moves between
the first and second frames, good separation is not obtained.
To prevent this, a motion detection is carried out in the 3D
YC separation (hereafter called YCS) unit (PB6347). When
a picture moving is detected a 2D YC separation using a
line memory is switched in and when not detected or for a
still picture 3D YC separation is switched in, thereby correcting defects both the systems have and performing the
ideal YC separation. The motion detection accuracy and
smoothness of the switching, etc. are controlled through the
IIC bus.
After completion of the Y and S signal separation, a vertical
contour correction is carried out for the Y signal.

2. CIRCUIT DESCRIPTION
2-1. Configuration
The YCS unit consists of a YC separation IC (QZ01,
TC9086F) which plays major roles, 2 Mbyte field memory
(QZ02, QZ03), clock generation IC (QZ04, TA8667F), and
peripheral circuits (LPF, AMP,emitter followers, etc.).

(QZ16 emitter: 28.6 MHz ± 0.2 MHz, adjusted by
LZ25.)

Of the above circuit blocks, QZ01 (TC9086F) includes an
A/D converter, D/A converter, clamp circuit, 4fsc PLL circuit, 1 line dot countermeasure circuit, vertical contour correction logic circuit, etc. and provides a high separation with
less variations.

57

• Terminal description (PZ01)

No.

Signal name

Voltage

DH

Comb through

DC

Y-Comb

DE

9V

DD

C-Comb

DB

GND

GND

DG

V-AV

2V(p-p)

DA

5V

+5V ± 0.5V

DF

fsc

0.4V(p-p), 3.58 MHz

DI

SDA1

IIC bus data, 5V

DJ

SCL1

IIC bus clock, 5V

Comb through pulse for ED2 ID signal period (V frequency), 5V
2V(p-p)
+9V ± 0.5V
0.6V(p-p) at burst

PZ01

QZ01 TC9090N
36 KILL

DH
DC

AMP
QZ22

QZ21

48 YOUT

LPF
LZ20 etc

DE
AMP

DD
QZ24

QZ23

QZ06

LZ23 etc

51 COUT

LPF
LZ21 etc

DB
56 CVIN

LPF

DG

QZ07
8

DA

FS2N

28 FSC

DF
QZ05
DI

20 DATA

DJ

19 SLK
QZ04 TA8667F

64
QZ16

QZ14
LZ25
28.6MHz

Fig. 7-1 3-dimension Y/C separator unit block diagram

58

100
QZ02
QZ03

SECTION VIII: VERTICAL OUTPUT CIRCUIT
1. OUTLINE
Q301 (LA7833S) contains the pump up circuit and the output
circuit. V screen position switching function which lowers
the V raster position by flowing an opposite DC current into
the deflection yoke. This circuit is used selecting SUBTITLE
and CINEMA MODE.

The sync separation circuit, V pulse circuit, and blanking
circuit are provided inside Q501 (TA1222AN). The saw tooth
wave generation circuit and amplifier (V driver circuit) are
provided inside Q302 (TA8859AP).

WAC
PULSE DELAY

Q302 TA8859AP

Q301 LA7833S

SAWTOOTH
WAVE
GENERATOR

PUMP UP
CIRCUIT

AMP

OUTPUT

( I 2 C BUS)

DEFLECTION
YOKE

FEEDBACK

MICROPROCESSOR

CONTROL CIRCUIT

( I 2 C BUS)
Q501 TA1222AN
V/C/D LSI

V-RASTER SHIFT
CIRCUIT

SYNC SEP.V PULSE/
BLANKING

AUTO LIVE
MICROPROCESSOR
V-BLK

Fig. 8-1

1-1. Theory of Operation
This voltage is applied to (+) input (non-inverted input) of
an differential amplifier, A. As the amplification factor of A
is sufficiently high, a deflection current flows so that the
voltage V2 at point c becomes equal to the voltage at point

The purpose of the V output circuit is to provide a sawtooth
wave signal with good linearity in V period to the deflection
yoke.
When a switch S is opened, an electric charge charged up to
a reference voltage VP discharges in an constant current rate,
and a reference sawtooth voltage generates at point a .

a.

S: Switch

Vp

Differential
amplifier
L
A

a

C2
V1

R1

C2

c
V2

R2
R3

Fig. 8-2
59

2. V OUTPUT CIRCUIT
2-1. Actual Circuit
D309

C322
+9V

R308

C308

D308
15

R329

+35V

3

D301
R303

3
14

Q501
31

Q302

Q301

4

6

C313

6

7

L301

R336

2

C321
R320

C307

5

1

R307

R301
13

8

L462+L463+L464

R306
C309

C314

C311
C306

R313
R330
C305
R304

C319

R305

Fig. 8-3

2-2. Sawtooth Waveform Generation
2-2-1. Circuit Operation
The pulse generation circuit also works to fix the V ramp
voltage at a reference voltage when the trigger pulse enters,
so it can prevent the sawtooth wave start voltage from
variations by horizontal components, thus improving
interlacing characteristics.

The sawtooth waveform generation circuit consists of as
shown in Fig. 8-4. When a trigger pulse enters pin 13, it is
differentiated in the waveform shape circuit and only the
falling part is detected by the trigger detection circuit, to the
waveform generation circuit is not susceptible to variations
of input pulse width.

13
5Vp

WAVEFORM
SHAPE

TRIGGER
DET.

PULSE
GAIN

V. LAMP

AGC

14

15

16

DC=0V

R329

C321

C322
+
+9V

Fig. 8-4
60

C323

2-3. V Output
2-3-1. Circuit Operation
Q3 turns on for first half of the scanning period and
allows a positive current to flow into the deflection
yoke (Q3 ® DY ® C306 ® R305 ® GND), and Q4
turns on for last half of the scanning period and allows
a negative current to flow into the deflection yoke
(R305 ® C306 ® DY ® Q4). These operations are
shown in Fig. 8-5.

The V output circuit consists of a V driver circuit Q302,
Pump-up circuit and output circuit Q301, and external circuit
components.
(1)

Q2 amplifies its input fed from pin 4 of Q301, Q3, Q4
output stage connected in a SEPP amplifies the current and supplies a sawtooth waveform current to a
deflection yoke.

+35V
D301

C308

63V
V3

D308

35V

Q301
6

3

GND
D309

Q3

R308

V7

35V

7

GND

BIAS
CIRCUIT

V2

63V

2

Q2
Q4

4

DY
+
C306

GND
Q3 ON

R305

GND
1
Q4 ON

Fig. 8-5
(2)

In Fig. 8-6 (a), the power Vcc is expressed as a fixed
level, and the positive and negative current flowing
into the deflection yoke is a current (d) = current (b) +
(c) in Fig. 8-6, and the emitter voltage of Q3 and Q4 is
expressed as (e).

(3)

Q3 collector loss is i1 x Vce1 and the value is equal to
multiplication of Fig. 8-6 (b) and slanted section of
Fig. 8-6 (e), and Q4 collector loss is equal to multiplication of Fig. 8-6 (c) and dotted section of Fig. 8-6
(e).

Power Vcc
GND (b) Q3 Collector current i1
Q3
GND (c) Q4 Collector current i2
i1

Vce 1

Q4
GND (d) Deflection yoke current i1+i2
Q2
i2
Vp
Vcc
1/2 Vcc
GND
(a) Basic circuit

Fig. 8-6

61

(e)

(4)

To decrease the collector loss of Q3, the power supply
voltage is decreased during scanning period as shown
in Fig. 8-7, and VCE1 decreases and the collector loss
of Q3 also decreases.
Q3 Collector loss decreases
by amount of this area

(6)

Since pin 7 of a transistor switch inside Q301 is connected to the ground for the scanning period, the power
supply (pin 3) of the output stage shows a voltage of
(VCC – VF), and C308 is charged up to a voltage of
(VCC – VF – VR) for this period.

(7)

First half of flyback period
Current flows into L462 + L465 + L464 ® D1 ® C308
® D308 ® VCC (+35V) ® GND ® R305 ® C306
® L462 + L463 + L464 in this order, and the voltage
across these is:

Power supply
for flyback period (Vp)
Power supply
for scanning period
(Vcc)

VP = VCC + VF + (VCC – VF – VR) + VF about 63V
is applied to pin 3. In this case, D301 is cut off.
Scanning period

(8)

Current flows into VCC ® switch ® D309 ® C308
® Q301 (pin 3) ® Q3 ® L462 + L463 + L464 ®
C306 ® R305 in this order, and a voltage of

Flyback period

Fig. 8-7 Output stage power supply voltage

(5)

Last half of flyback period

VP = VCC – VCE (sat) – VF + (VCC – VF – VR) –
VCE (sat), about 56V is applied to pin 3.
(9) In this way, a power supply voltage of about 35V is
applied to the output stage for the scanning period and
about 63V for flyback period.

In this way, the circuit which switches power supply
circuit during scanning period and flyback period is
called a pump-up circuit. The purpose of the pump-up
circuit is to return the deflection yoke current rapidly
for a short period (within the flyback period) by applying a high voltage for the flyback period. The basic
operation is shown in Fig. 8-8.

D301

D301

C308

C308

D308

D308
Q301

6

Q301

3
D309

6

3

R308

D309

7

Q3

VR

Switch

Switch

7

Q3
D1

D1

First half

L462+L463+L464

L462+L463+L464
2
Q4

R308

2

+
C306

Q4

+
C306
R305

R305

Last half
(a) Scanning period

(b) Flyback period

Fig. 8-8
62

2-4. V Linearity Characteristic Correction
2-4-1. S-character Correction
(Up-and Down-ward Extension Correction)

2-4-2. Up-and Down-ward Linearity Balance
A voltage developed at pin 2 of Q301 is divided with resistors
R307 and R303, and the voltage is applied to pin 6 of Q301
to improve the linearity balance characteristic.

A parabola component developed across C306 is integrated
by R306 and C305, and the voltage is applied to pin 6 of
Q302 to perform S-character correction.

3. PROTECTION CIRCUIT FOR V DEFLECTION STOP
Q301

2

R352
12V 9V

D350
L462+L463+L464

R354

R351
C306

Q350

C350

Q351

D354

BLANKING
CIRCUIT

Q353

R350
R305

D353

Fig. 8-9

When the deflection current is not supplied to the deflection
coils, one horizontal line appears on the screen. If this
condition is not continued for a long time, no trouble will
occur in a conventional TV. But in the projection TV, all the
electron beams are directly concentrated at the fluorescent
screen because of no shadow mask used, and burns out the
screen instantly.

Next, when the V deflection stops, the voltage across (R305)
does not develop, so Q350 turns off, and both the Q351 and
Q353 are turned off. Then, the picture blanking terminal
pin 13 of ICA05 is set to high through R354 and D354
connected to 90V power line, BLANKING CIRCUIT ON
thus cutting off the projection tubes.

To prevent this, the stop of the V deflection is detected when
the horizontal one line occurs, and the video signals are
blanked out so that the electron beams are not emitted.

Volttage Across
R305

When the V deflection circuit is operating normally, a
sawtooth wave voltage is obtained across (R305), so Q350
repeats on-off operation in cycle of V sync. In this case, the
collector voltage of Q35 is set to develop less than (12VVBE (Q351)) with R352 and C350 as shown in Fig. 8-9.
Accordingly, Q351 and Q353 are continuously turned on.
As a result, diode D354 is turned off, giving no influence on
the blanking operation.

Q340 VBE

Q350 BASE

12V-VBE (Q341)
Q351 Collector

Fig. 8-10

63

3-1. +35V Over Current Protection Circuit
When the voltage increases across R370. and the voltage
developed across R371 becomes higher than the Vbs of
Q370, Q370 turns on and a voltage develops across R374
due to the collector current flowing. When this voltage
increases to a value higher than about 7V, Z801 operates,
thus cutting off the power relay. When the circuit operates, a
power LED provided will turn on and off in red.

The over current protection circuit cuts off the power supply
relay when it detects abnormal current increased in the +35V
power line due to failure of the vertical deflection circuit.
3-1-1. Theory of Operation
Fig. 8-11 shows the circuit diagram of the over current
protection circuit. When the load current of the +35V line
increases, the voltage across a resistor of T370 will also
increase.

C303
R370

R327
+35V
C310

R372

D302

FBT
pin 6

R371

C370
D421
UZ22BSD

Q370
2SA933SQ

D370
UZ11BSB

R373

R375
C371
R374

Fig. 8-11

64

To pin 14 (GATE)
of Z801

4. RASTER POSITION SWITCHING CIRCUIT
4-1. Outline

So, adjust the center of the picture to the center of the screen
in advance under the output V sync delayed.

When the vertical screen position adjustment is carried out
on the projection TV, DC current is directly flown in the
vertical deflection yoke and the raster cannot be moved up
and down. (Because the raster is moved, the color distortion
may occur.) Accordingly, the vertical screen position
adjustment is carried out by the following method. (Only in
CINEMA and SUBTITLE mode)

To do this, lower the raster position by flowing a DC current
to the deflection yoke in the CINEMA and SUBTITLE
mode.
The operation above is carried out by the vertical screen
position SW circuit.

V sync pulse output from Q501 sync. separation circuit is
once input to WAC, delayed and then output. The deflection
circuit operates with the delayed sync signal. The screen
upper side position moves up and down by varying the delay
time. When the vertical position adjustment is carried out
by WAC, the followings must be considered.

4-2. Operation
When CINEMA and SUBTITLE are selected in the screen
mode, a zoom signal is input to the base of Q362 from the
autolive circuit and Q362 turns on. Then, Q363 turns off
and the base of Q364 develops H and Q364 turns on. The
inverted DC current flows into the vertical deflection yoke
from +35V power supply line.V power supply line and then
the raster moves down.

WAC becomes “through” except for CINEMA and
SUBTITLE mode.
The phase of the output V sync must not advance from that
of WAC input V sync. If it advances, Vertical jitter may occur
when performing the search operation and the vertical
position adjustment of a VTR.

Fig. 8-12

Q362
RN1204

R363
2R
220

R362
1R5.6K

R360
33K

R361
12K

R364
KETSU
R365
R366
1R5.6K 33K

Q364
2SC2023

R367
12K
Q367
2SC2023

Q363
2SC1815Y

Q366
RN1204

Q365
2SC1815Y

D361
S5965G
+35V
+12V
P360

Fig. 8-13
Screen
mask
position

Screen
mask
position

Raster position

Nomal mode (4:3, Full, Dramatic Wide)

Mode in which the opposite current
flows into D Y (Cinema)

65

SECTION IX: HORIZONTAL DEFLECTION CIRCUIT
1. OUTLINE

2-1. Theory of Operation

The H deflection circuit works to deflect a beam from left to
right by flowing a sawtooth waveform of 15.625 kHz/15.735
kHz into the DY H deflection coil.

(1)

When the power switch is on, the main power supply
of 125V starts to rise. At the same time, AF power supply 38V also rises.

(2)

With 38V line risen, Q430 base voltage which is created by dividing the audio power with R433 and D430
also rises. Then, the transistor Q430 turns on and the
H VCC is applied from the audio power line through
R432 and D431 to pin 22 of Q501.

2. HORIZONTAL DRIVE CIRCUIT
The H drive circuit works to start the H output circuit by
applying H VCC (Q501 DEF power source) to pin 22 of
Q501 (TA1222N) and a bias to the H drive transistor Q402
at the main power on.
R432

Q430

D431

35V

Q501

R433

D430

BB81
81

81

22 H Vcc

L400

BB80

SIGNAL

C431

C430

Fig. 9-1 H drive circuit block diagram

3. BASIC OPERATION OF HORIZONTAL DRIVE
A sufficient current must flow into base of the horizontal
output transistor to rapidly make it into a saturated (ON)
condition or a cut off (OFF) condition. For this purpose, a
drive amplifier is provided between the oscillator circuit and
the output circuit to amplify and to waveshape the pulse voltage.

3-1. Theory of Operation
(1)

The horizontal drive circuit works as a so called switching circuit which applies a pulse voltage to the output
transistor base and makes the transistor on when the
voltage swings in forward direction and off in reverse
direction.

66

(2)

To turn on the output transistor completely and to make
the internal impedance low, a sufficiently high, forward drive voltage must be applied to the base and
heavy base current ib must be flown. On the contrary,
to completely turn off the transistor, a sufficiently high,
reverse voltage must be applied to the base.

(3)

When the transistor is on (collector current is maximum) condition with the sufficiently high forward voltage applied to the base, the transistor can not be turned
off immediately, if a reverse base bias is applied to the
base because minority carriers storaged in the base can
not be reduced to zero instantly. That is, a reverse current flows through an external circuit and gradually
reduces to zero. The time lag required for the base current to disappear is called a storage time and falling
time.

(4)

To shorten the storage time and the falling time, a sufficiently high reverse bias voltage must be applied to
allow a heavy reverse current to flow. This operation
also stabilizes operation of the horizontal output transistor.

On period

OFF period

+
t Input waveform (b)

0

+

Forward
current

ib

t Base current (c)

0
Reverse
current

V

-

Falling
time

(a)
Storage
time

Fig. 9-2

3-2. Circuit Description
(2)

In the N5SS chassis, the off drive system is employed.
(1)

When Q1 inside Q501 is turned on, Q402 base is forward biased through 9V ® pin 22 of Q501 (H. VCC)
® pin 23 of Q501 (H. Out) ® R411/R410 resistor divider, and then, Q402 collector current flows through
125V ® R416 ® T401. In this case, the H output transistor Q404 turns on with the base-emitter reverse biased because of the off drive system employed.

The voltage is stepped down and Q404 is forward biased with this voltage, thus turning on Q404.
(3)

Q501

22

On the contrary, when Q1 inside IC501 is off (pin 8 is
0V), base-emitter bias of Q402 becomes 0V and Q402
turns off, and a collector pulse as shown in Fig. 9-3
develops at the collector.

In this way, by stepping down the voltage developed at
primary winding of the drive transformer and by applying it to Q404, a sufficient base current flows into
Q404 base, thereby switching the Q404.

H. Vcc
T401
H drive
transistor
C417

C431

1

3

R415

Q1

R411
23
2

R410

4

Q404
H output
transistor

C413
Q402
H drive
transistor

V1

+

V2

R416

0V
C416
+125V

9V

VCP

Fig. 9-3

0V
Q402
OFF

67

Q402
ON

4. HORIZONTAL OUTPUT CIRCUIT

10

The horizontal output circuit applies a 15.625 kHz/15.734
kHz sawtooth wave current to the deflection coil with mutual action of the horizontal output transistor and the damper
diode, and deflects the electron beam from left to right in
horizontal direction.

5

HV

T461
FBT

2

S-charactor
capacitor

3

Q404
H output
(With damper diode)

T401
H drive
transformer

IC501
R415

Deflection yoke
(H coil)

8

1
C440

L462 L463

C343

C444

H. out

C418

TP-33
Q402
H drive

D461

C423

R441

BB81
Q1

23

H
linearity
coil

C463

83
R411
R410

C417

C467
L441

D443
L461

C413

To High Voltage
Regulator Circuit

+
C416

L464

D444

C464
+

R416
Resonat
capacitor

To DPC output
SIGNAL

DEF/POWER PCB

125V
Diode modulator circuit

Fig. 9-4

4-1. Theory of Operation
(a)

4-1-1. Operation of Basic Circuit
(1)

(2)

To perform the horizontal scanning, a 15.625 kHz/
15.735 kHz sawtooth wave current must be flown into
the horizontal deflection coil. Theoretically speaking,
this operation can be made with the circuit shown in
Fig. 9-5 (a) and (b).

H output basic circuit
H output
transistor

D
Damper
diode

As the switching operation of the circuit can be replaced with switching operation of a transistor and a
diode, the basic circuit of the horizontal output can be
expressed by the circuit shown in Fig. 9-5 (a). That is,
the transistor can be turned on or off by applying a
pulse across the base emitter. A forward switching current flows for on-period, and a reverse switching current flows through the diode for off-period. This switching is automatically carried out. The diode used for
this purpose is called a damper diode.

Co

L
Deflection
yoke

Resonant
capacitor

Vcc
(b)

H output equivalent circuit

SW1

SW2

Co

Vcc

Fig. 9-5
68

L

Description of the basic circuit
1. t1~t2:

6. t4~t6:

A positive pulse is applied to base of the output transistor
from the drive circuit, and a forward base current is flowing.
The output transistor is turned on in sufficient saturation area.
As a result, the collector voltage is almost equal to the ground
voltage and the deflection current increases from zero to a
value in proportionally. (The current reaches maximum at
t2, and a right half of picture is scanned up to this period.)

For this period. C0 is charged with the deflection current
having opposite polarity to that of the deflection current
stated in "3.", and when the resonant capacitor voltage exceeds VCC, the damper diode D conducts. The deflection
current decreases along to an exponential function (approximately linear) curve and reaches zero at t6. Here, operation
returns to the state described under "1.", and the one period
of the horizontal scanning completes. For this period a left
half of the screen is scanned.

2. t2:
The base drive voltage rapidly changes to negative at t2 and
the base current becomes zero. The output transistor turns
off, collector current reduces to zero, and the deflection current stops to increase.

In this way, in the horizontal deflection scanning, a current
flowing through the damper diode scans the left half of the
screen; the current developed by the horizontal output transistor scans the right half of the screen; and for the flyback
period, both the damper diode and the output transistor are
cut off and the oscillation current of the circuit is used. Using the oscillation current improves efficiency of the circuit.
That is, about a half of deflection current (one fourth in terms
of power) is sufficient for the horizontal output transistor.

3. t2~t3:
The drive voltage turns off at t2, but the deflection current
can not reduce to zero immediately because of inherent nature of the coil and continues to flow, gradually decreasing
by charging the resonant capacitor C0. At the same time, the
capacitor voltage or the collector voltage is gradually increases, and reaches maximum voltage when the deflection
current reaches zero at t3. Under this condition, all electromagnetic energy in the deflection coil at t2 is transferred to
the resonant capacitor in a form of electrostatic energy.

t1

4. t3~t4:
Since the charged energy in the resonant capacitor discharges
through the deflection coil, the deflection current increases
in reverse direction, and voltage at the capacitor gradually
reduces. That is, the electrostatic energy in the resonant capacitor is converted into a electromagnetic energy in this
process.
5. t4:
When the discharge is completed, the voltage reduces to zero,
and the deflection current reaches maximum value in reverse direction. The t2~t4 is the horizontal flyback period,
and the electron beam is returned from right end to the left
end on the screen by the deflection current stated above.
The operation for this period is equivalent to a half cycle of
the resonant phenomenon with L and C0, and the flyback
period is determined by L and C0.

A

TR
base voltage

0

B

TR
base current

0

C

TR
collector
current

D

D
damper
current (SW2)

E

Switch
current
(TR, SW1)

F

G

H

t2 t3 t4 t5

0
0

0

Resonant
capacitor
current (Co)

0

Deflection
current (Lo)

0

TR
collector
voltage

0

Fig. 9-6
69

t6

Amplitude Correction
To vary horizontal amplitude, it is necessary to vary a
sawtooth wave current flowing into the deflection coil. These
are two methods to vary the current; a method which varies
LH by connecting a variable inductance L in series with the
deflection yoke, and a method which varies power supply
voltage (across S-character capacitor) for the deflection yoke.
As the DPC circuits is used in the this chassis, the later
method which varies the deflection yoke power supply voltage by modifying the bus data is used.

t2

t1

θ2

θ1

t2 = t1
θ2 < θ1

(a) S-character correction

t1

θ2

θ1

(b)

Fig. 9-7

4-1-2. Linearity Correction (LIN)
(1)

t2

S-curve Correction (S Capacitor)
Pictures are expanded at left and right ends of the screen
even if a sawtooth current with good linearity flows in
the deflection coil when deflection angle of a picture
tube increases. This is because projected image sizes
on the screen are different at screen center area and
the circumference area as shown in Fig. 9-7. To suppress this expansion at the screen circumference, it is
necessary to set the deflection angle q1 to a large value
(rapidly deflecting the electron beam) at the screen
center area, and to set the deflection angle q2 to a small
value (scanning the electron beam slowly) at the circumference area as shown in Fig. 9-7.

Cs

TR

D

Co
LH
Deflection coil
Vcc

(a) H output circuit

In the horizontal output circuit shown in Fig. 9-8, capacitor CS connected in series with the deflection coil
LH is to block DC current. By properly selecting the
value of CS and by generating a parabolic voltage developed by integrating the deflection coild current
across the S capacitor, and by varying the deflection
yoke voltage with the voltage, the scanning speed is
decreased at beginning and end of the scanning, and
increased at center area of the screen. The S curve correction is carried out in this way, thereby obtaining
pictures with good linearity.

(b) Sawtooth wave current

(c) Voltage across LH
Fast deflection

Slow deflection
(d) Synthesized current

Fig. 9-8

70

t2 > t1
θ2 = θ1

(2)

Left-right Asymmetrical Correction (LIN coil)

When a horizontal linearity coil L1 with a current characteristic as shown in Fig. 9-9 (c) is used, left side picture will be compressed and right side picture will be
expanded because the inductance is high at the left side
on the screen and low at the right side. The left-right
asymmetrical correction is carried out in this way, and
pictures with good linearity in total are obtained.

In the circuit shown in Fig. 9-9 (a), the deflection coil
current iH does not flow straight as shown by a dotted
line in the Fig. 9-9 (b) if the linearity coil does not
exist, by flows as shown by the solid line because of
effect of the diode for a first scanning (screen left side)
and effect of resistance of the deflection coil for later
half period of scanning (screen right side). That is, the
deflection current becomes a sawtooth current with bad
linearity, resulting in reproducing of asymmetrical pictures at left and right sides of the screen (left side expanded, right side compressed).

(a)

LH
TR

D

Co

(a)

LI
L
TR

D

LH
Deflection
coil

Co

iH

Li

Cs

FBT

C

Vcc

Cs
S-character
capacitor

(b) Sawtooth wave current

(b) Deflection coil current
Deflection coil current

Fig. 9-10

(iH)
Resistance of LH
Characteristic of D

0
(Left)

(Right)

(c) Linearity coil characteristic
Linearity coil characteristic
Inductance
(µH)

(Left)

(Right)
Current (A)

Fig. 9-9 Linearity coil

71

4-2. White Peak Bending Correction Circuit
4-2-1. Outline

4-2-2. Operation Theory

White peak area in screen picture may sometimes cause bending in picture. See figure below.

Fig. 9-11 shows circuit diagram. Video ripple in video output circuit power supply 200V suffers DC cut by C475, and
is inverted in Q470, then input to pin 24 of Q501 via C481.
Pin 24 of Q501 is a bending correction terminal. The voltage which is applied to this terminal, controls phase of video
signal to correct white peak bending.

In TP48E60 series, correction signal which video ripple in
video output circuit power supply 200V is input to pin 24
(Bending correction terminal) of Q501. This corrects white
peak bending.

Q501
R379
24
EHT
Bending correction
terminal

C415

BB91
93

Receiving Board
Power, Def board

9V
R481

200V

R483

D406

R478

C481 Inversion

3 T416
C475

Q470
D470

R482

R484

White peak
Bending by white peak

Fig. 9-11 White peak bending correction circuit

72

D474

C466

4-3. H Blanking

4-3-2. Theory of Operation
The H blanking circuit determines the flyback period precisely from the AFC pulse in the FBT and applies the period
to emitter of the video output stage transistor on the CRT-D
PC board.

4-3-1. Outline
The H blanking circuit applies a blanking precisely for the
horizontal flyback period so that undesirable pictures folding does not appear at screen ends.
This unit allows the users to adjust an horizontal amplitude
adjustment, so, picture quality at screen ends will be improved. This is one of the purposes of the blanking circuit.

4-3-3. Circuit Operation
As can be seen from Fig. 9-12, the flyback period of the
AFC pulse in the FBT starts at a negative side from 0V. To
detects this, the DC component is cut with C493. This is,
C493 is always charged through D487 with a negative side
(about –17V) of the AFC pulse. As a result, a voltage at point
A in the waveform rises from the ground level. This waveform is sliced in a circuit (R486, D486) to detect the flyback
period. Thus obtained voltage is applied to Q901, Q911, and
Q921 through D904, D914, D927 and cuts off them thereby
blanking the resters.

Q487
ON period

Q921

D486
Slice level

0V
Approx.
-17V

D927

10

Waveform at
point

AFC Pulse

BLUE
CRT/D

10
Q911

Fig. 9-12
D914

+35V

GREEN
CRT/D

10
10
Q901
R906

Point A
T461 (FBT)
AFC

Q487

C493

10
L410

6
7

R486
D486

R417

R409

D904

RED
CRT/D

P904
CRT-D DCB
P903

Deflection/Power PCB

Q489

D487
R438

Q488
V blanking

Fig. 9-13

73

4-4. 200V Low Voltage Protection

4-4-2. Theory of Operation
Fig. 9-14 shows a connection diagram.

4-4-1. Outline

Under a normal condition Q340 is always on because of about
210V supplied from the 200V line. Accordingly Q340 collector is kept at about 6.2V or the zener voltage of D341 and
Q341 is turned off.

When the video output power supply 200V is stopped by
some abnormality occurence, the current inside CPT increases abnormally. So the CPT may be damaged. To prevents this, a 200V low voltage protection circuit is provided.

If some abnormality occurs and 200V line voltage lowers
by less than about 160V. Q340 turns off and its collector
voltage rises. So Q341 turns on. With Q341 turned on the
voltage at pin 14 of Z801 (expander) exceeds a threshold
voltage and pin 16 of Z80 is high level and makes the power
relay turn off.

1

1

2

2

-12V
P350

P301

P405
200V

DPC circuit

Deflection circuit

CRT-D Circuit

R389

R390

Q340

R436
8

8

17

17

Q341
D340

R391
D341 R392

R879

Z801
D315
14 GATE

PROTECTOR
16

C894

Fig. 9-14

74

R346

C340

5. HIGH VOLTAGE GENERATION CIRCUIT
The high voltage generation circuit develops an anode voltage for the picture tube, focus, screen, CRT heater, video
output (210V) and so on by stepping up the pulse voltage
developed for flyback period of the horizontal output circuit with the FBT, and supplies the power to various circuit.

5-1. Theory of Operation

AFC
blanking

9

Heater
+12V-1
R448

C303
Auxiliary
winding

CRT
anode

10

+35V

4

C447
D408

D302

C310

7

R327
6
C460

D460

R469

-27.5V
D406

R443

+210V
Primary
winding

Focus pack

5
3
C446

+125V

2

R444
C448

1
Q404

C440

ABL

C443 C444

T401

1040V(p-p)

C463
C418

C467

L441

H deflection coil
L462/L463/L464

R441
C423

HIGH VOLTAGE
REGULATOR
CIRCUIT

DPC CIRCUIT

Fig. 9-15

75

1H
(15.625kHz)

5-1-1. +210V
For the flyback period, pulses are stacked up to DC +125V
with FBT, and the voltage is rectified by D406 and filtered
by C446.

+125V

5-1-2. +35V, 12V
0

Pin 4 of the FBT is grounded and the shaded area of negative pulse developed for opposite period of the flyback period is rectified, thus developing better regulation power
supply.

Fig. 9-16

0

10

5-1-3. –27V
As a power for the DPC circuit, a negative pulse signal is
rectified by D460 and filtered with C460, thus developing
the –27V.

4

5-1-4. High Voltage

6 For +12V

Singular rectification system which uses a harmonics nonresonant type FBT is employed and a better high voltage
regulation is obtained, so amplitude variation of pictures
becomes low.

2

0

1

Fig. 9-17

G

F

Picture
tube anode

E

Picture
tube capacitor

Primary

G

Pulse

E

F

EH

D

D

C

Stacked
pulse of
4 block

C

EO
B
Auxiliary

0

7 +35V

B
A

A

1H
15.735KHz

ABL

Fig. 9-18

5-2. Operation Theory of the Harmonic Non-Resonant System and Tuned Waveforms
The high voltage coil is of film multi-layer winding type
and the coils are isolated into seven blocks. Each block is
connected through a diode.

Moreover, a capacitance between the internal and external
coatings of the picture tube works as a smoothing capacitor.
Focus voltage is obtained at point EO.

The basic operation is described in the case of 4 blocks construction for simplification. Positive or negative pulse determined by stray capacitance of each coil develops at terminal
points ( A , B , C , D , E , F , G ) of each coil as shown in Fig. 918, and these pulses are stacked as shown, thus developing
the high voltage.

76

6. HIGH VOLTAGE CIRCUIT

VCP1 =

C2
V
C1 + C2 CP

1

VCP2 =

C2
V
C1 + C2 CP

2

VCP

C2
V
C1 + C2 CP2

3

6-1. High Voltage Regulator
6-1-1. Outline
Generally, four kinds of methods exist to stabilize a high
voltage in high voltage output circuits using the FBT:
(1)

Stabilization by varying the power supply voltage.

(2)

Stabilization by varying L value with a saturable reactance connected in series with the primary winding of
the FBT.

(3)

Stabilization by varying equivalent capacitance of the
resonant capacitor C0.

(4)

Stabilization by superimposing a DC or pulse (this
varies the high voltage) on a lower voltage side of the
high voltage winding of the FBT.

The VCP2 developed across C2 is DC-clamped with a diode
D1 and the resultant voltage is smoothed with a diode D2
and a capacitor C3. Thus processed voltage is obtained at
the point B . This voltage is used to provide a base current
for the transistor Q1 or to flow the collector current. The
voltage at the point B decreases with the circuit impedance
and finally lowers up to a VCE saturation voltage of Q1.
Then, VCP2 is not clamped by D2 with the voltage at the
point B . Since the VCP is expressed as a sum of VCP1 and
VCP2 as shown by equation 3 , VCP decreases by amount
the VCP2 is decreased. This varies the high voltage.

In this unit, pulse transformer is eliminated and the regulator circuit using the method (3) is employed. The block diagram is shown in Fig. 9-19.

Q1 collector current is controlled by Q1 base current which
is an output of the comparison inverted amplifier. That is,
the Q1 base current is controlled by a voltage obtained by
comparing a detection voltage of the top breeder of the FBT
(9.1V) and a DC voltage of 9V.

Z450
CR-BLOCK
T461
FBT
Hotizonal
output

ANODE

DY

=

Horizontal
output

125V

C1 LH

FBT
LP

PW output
+B

CS
D1

-27V

C2

B
D2

C3

High voltage Reg.

Q1

V.
Ref.

Fig. 9-19 Basic circuit for high voltage regulator
emplyed in the unit

High voltage
Reg.
output amp

Fig. 9-20

6-1-2. Theory of Operation
Fig. 9-20 shows a basic circuit of the high voltage regulator
used in the unit.

VCP = VCP1 + VCP2

The high voltage regulator circuit splits a resonant capacitor
C0 to C1 and C2. thereby dividing the collector voltage (VCP)
of the H output transistor with C1 and C2.

VCP 1

Here, assume each voltage developed across C1 and C2 as
VCP1 and VCP1, respectively,
VCP 2

each relation can be expressed by the above equations
1 ~ 3.
77

Fig. 9-21

6-1-3. Actual
As a result, Q480 collector current increases and Q480 collector voltage (at the point B ) decreases. Then, a peak value
of VCP2 across C418 is clamped by the diode D443 at the
collector voltage lowered, and the collector voltage VCP of
Q404 (H output transistor) obtained as a sum of the voltage
VCP1 across C443 and VCP2 across L418 decreases. Then,
the high voltage also decreases.

Fig. 9-22 shows the actual circuit used in the unit.
A resonant capacitor C0 is also split into two capacitors C443
and C444 in this circuit. The high voltage regulator cirucits
is structured by splitting the C443 to two capacitors of C443
and C448.
Here, assume a high voltage increases and the detection voltage ED' obtained by dividing the high voltage also increases
in proportional to the high voltage. This makes the voltage
ED increase at pin 7. (The voltage is impedance transformed
by a voltage follower circuit consisting of op amplifier Q483
at pin 7.)

When the high voltage lowers, the corrective operation is
carried out in reverse order.
* Resustors R451, R452, R453 and R455 are used to correct undersirable influence (H amplitude increase at minimum IH) by the H amplidude regulator.

The voltage ED and a 9V reference voltage developed by a
3-terminal regulator Q420 are compared. When the E D increases, the voltage at pin 2 of Q483 differential amplifier
also increases, and the base current IB of the high voltage
transistor Q480 increases.

CR-BLOCK EH

FBT
Horizontal
output

Q404

L462
L463
L464

C443

C444

C440
-27V

CS
R460

125V

R466
C467
D461

Q462

R461/R469

L461
R463

R455

ED'
R435

Q460
C482

Q483

C464

R454

D443

ED

B

R451

6

8

R453

7

R452
R489

D444
C418
C419

Q480

R434

4

2

R431

R492

R450

3
R488

R490
Q420

C483

R494

R439

R487

Fig. 9-22 Actual high voltage regulator circuit

78

9V-1

7. X-RAY PROTECTION CIRCUIT
7-1. Outline
In case picture tube using high voltage, when high voltage
rises abnormally due to components failure and circuit malfunction, there is possible danger that X-RAY leakage increases to affect human body. To prevent it, X-RAY protection circuit is equipped.

7-2. Operation
Then Q463 turns on. By this Tr6 and Tr6 turn on to make
ON/OFF pulse at pin 7of QA01 in low level, Q846 and Q845
turns off, then relay SR81 turns off. Tr6 and Tr7 are in thyristor-connection, and 5V of power holds protection operation until main power switch is turned off. During circuit
operation, power LED near main power switch blinks turn
on and off in red.

Figure 9-23 shows the circuit diagram. Supposing high voltage rises abnormally due to some reason, pulse at pin 9 of
T461 also rises, and detection voltage ED rectified by D471
and C471 in X-RAY protection circuit rises. When ED rises,
emitter voltage of Q464 divided by R459 and R462 becomes
higher than [zener voltage (6.2V) of D458 + Q464 VBE ].
This causes Q464 turns on to supply base current to Q463.

Caution:
• To restart TV set, repair failure first.

5V

Z801
15

R9
R10

12V
ED

Tr7
Q463
R19
Q846
RELAY
SR80

Tr6
16

C894

R12

R459

R472

T461
9

C1

D459
R879

Tr5
R11

Q845

Q464

14

R462

R468
D458

R467
C459

17

Fig. 9-23 X-RAY protection circuit

79

C458

R458

D471
C471

8. OVER CURRENT PROTECTION CIRCUIT
8-1. Outline
If main power (125V) current increases abnormally due to
components failure, there is possible danger of the secondary damage like failure getting involved in other part failure, and abnormal heating. To prevent this, over current protection circuit is equipped, which detects current of main B
line to turn off power relay in abnormal situation.

8-2. Operation
Fig. 9-24 shows over current protection circuit. When the
current of main B line increases abnormally due to the
shortage in load of main B line, voltage drop arises across
R470. By this voltage drop, when base-emitter voltage of Tr8
in protector module (Z801) becomes approx. 0.7V or more,
Tr8 turns on, and the voltage by divided ratio of R15 and R16
is applied to cathode of ZD4. When this voltage becomes
higher than zener voltage of ZD4, ZD4 turns on to supply base
current to base of Tr6 via R14. This causes Tr5 ON and
voltage at pin 16 of Z801 becomes low.

Therefore, QB30 and Q843 turns off to set SR81 OFF. Tr6
and Tr7 in Z801 are in thyristor-connection, and power 5V1 supplied at pin 15 keeps protection operation for standby
power until main power switch is turned off. During circuit
operation, power LED near main power switch blinks in red.
Caution:
• To restart TV set, repair failure first.

F470

R470
MAIN B

To T461
R471

R479

5V
C472
15
MICON
QA01#7

2

R9
ZD4
R10

RELAY
SR80
16

R16

Tr7
R14

Q845

1

R15

D1

Tr8

Tr6

Q846

R12

C1

Tr5
R11
Z801
PROTECTOR MODULE
17

Fig. 9-24 Over current protection circuit

80

SECTION X: DEFLECTION DISTORTION CORRECTION CIRCUIT
(SIDE DPC CIRCUIT)
1. DEFLECTION DISTORTION CORRECTION IC (TA8859CP)
1-1. Outline
The deflection distortion correction IC (TA8859CP), in combination with a V/C/D IC (TA1222AN) which has a V pulse
output, performs correction for various deflection distortions
and V output through the I2C bus control. All the I2C bus
controls are carried out by a microcomputer and can be controlled with the remote control.

1-2. Functions and Features
The IC has functions of V RAMP voltage generation, V
amplitude automatic switching (50/60 Hz), V linearity correction, V amplification, EHT correction, side pincushion
correction, I2C bus interface, etc. and controls following
items through the I2C bus lines.

(4)

V picture position (neutral voltage setting)

(5)

V M-character correction

(6)

V EHT correction

(7)

H amplitude

(8)

L and R pin-cushion distortion correction I (entire area)
– Not used for this model.

(9)

L and R pin-cushion distortion correction II (corner
portions at top and bottom) – Not used for this model.

(10) H trapezoid distortion correction – Not used for this
model.
(11) H EHT correction
(12) V AGC time constant switching

(1)

V amplitude

(2)

V linearity

1-3. Block Diagram

(3)

V S-character correction

Fig. 10-1 shows a block diagram of the basic circuit.
+9V

V. Trigger-in

13

Waveform
shape

Trigger
det

V. M-Character
correction

14

15

16

Puise
Gen.

V. Rame

AGC

V. S-character
correction

V. linearity
correction

(Bus Control Signal)
SDA SCL

9

3

V. AGC time
constant SW

control through
bus

H. trapezoid distortion
correction
L-R pincushion
distortion correction I
L-R pincushion
distortion correction II
(Top & bottom comer section)

V. Amplitude
Adj.

10

5

Logic
V. screen
position

12

H.EHT
input

V. EHT
correction

H.EHT
correction
H. Amplitude
Adj.

8
V drive

6
V. feedback

1

4

EHT INPUT

EW feedback

Fig. 10-1
81

2 EW-drive

2. DIODE MODULATOR CIRCUIT
In N5SS, the distortion correction is carried out by the ditigal
convergence circuit. So the component of the diode modulator circuit is the same as that of conventional television,
because it is used only for the horizontal oscillation adjustment.

When the negative pulse developed at the point B is integrated with Lm and Csm, its average value appears at Csm
as a negative voltage.
By modulating this voltage with Q460, a waveform of Vm is
obtained as shown in Fig. 10-3 b). As a result, the voltage
VS which is the sum of the power supply voltage V B and the
Vm is applied across the S-curve capacitor C S. The VS becomes as a power source for the deflection yoke as shown in
Fig. 10-4, is applied to the horizontal deflection yoke.

Fig. 10-2 shows a basic circuit of the diode modulator used
in the N5SS.
A key point in the modulation circuit shown in Fig. 10-2 is
to develop a negative pulse at point B .
In this circuit, a current loop of the resonant circuit for flyback
period is shown by an arrow, and the energy stored in LDY is
transferred to resonant capacitors Cr, Crm in passing through
Cr, Crm, CS when the scanning completes. As a result, a
positive, horizontal pulse as shown in Fig.
10-3 a) will appear at Cr, and the current flows into Crm
with the direction as shown. Then a pulse as shown in Fig.
10-3 b) develops at the point B .
On the other hand, since constant amplitude pulses across
Cr, as shown in Fig. 10-3, are applied to the primary winding, the high voltage of FBT also develops a constant voltage.

0
a) Waveform at point A
0

b) Waveform at point B
A

Fig. 10-3

FBT
LDY
H
OUT

DD

Cr
VB

Cs Vs

VB

B Lm
Q460 Vm

DM
Crm

VS

Csm

0

Fig. 10-2
Fig. 10-4

82

3. ACTUAL CIRCUIT
In the actual circuit, the resonant capacitor is split into two
as shown in Fig. 10-7. One, C440, is inserted between the
collector of the H. OUT transistor and ground and another
C444 inserted between the collector and emitter. In Fig. 105, C440 is expressed as C1 and C444 as C2, and the resonant
current path for the flyback period is shown by arrows.

FBT

IP2

IP1
C1

IH

In a conventional circuit, when brightness of a picture tube
varies, high voltage current varies and the high voltage also
varies. As a result, horizontal amplitude also varies.

LDY

H.
OUT
IY1

IY2
IY

However, in this circuit, the horizontal amplitude variation
can be suppressed to near zero if the high voltage current
varies with variation of the high voltage.

CS

IP

VS

C2
VB
Lm

When the scanning period completes, the energy stored in
the deflection yoke L DY is transferred to the resonant capacitor in a form of current I Y. In this case, the current is
split into two; IY1 passing through C1, C3 and IY2 passing
through C2. In the same way, the energy stored in the primary winding of the FBT is transferred to the resonant capacitor in the form of IP. In this case, the current (path) is
also split into two; I P1 passing through C1 and IP2 passing
through C2, C3. Concequently, the current differences between IY1 and IP2 (IY1-IP2) passes through C3.

C3

IP2

Csm

IY1

Fig. 10-5

When the high voltage current IH reduces with a dark picture, the current IP in the primary circuit decreases, so IP1
and IP2 also decrease. However, a current flowing into (IY1IP2) increases as IP2 decreases. As a result, the pulse developing at the point B increases and the voltage Vm at Csm
also increases as shown in Fig. 10-8. That is, when a dark
picture appears, the voltage across S-curve capacitor CS increases as shown in Fig. 10-8, the high voltage rises, and the
horizontal amplitude is going to decrease. But, as VS increases, the deflection yoke current increases and this works
to increase the horizontal amplitude. Accordingly, if the
brightness of picture changes, the horizontal amplitude is
maintained at a constant value. This is one of the fine features the circuit has.

VB

VS

0
Vm

Fig. 10-6

83

Vm

3-1. Basic Operation and Current Path
3-1-1. Later Half Scanning Period

3-1-2. First Half Scanning Period

When the power is turned on, the power supply voltage VB
is applied to CS and Csm, and the CS acts as a power source
for a later half of the scanning period for which the H. OUT
transistor is turned on, and the deflection current IY flows in
the path as shown below.

When the base drive current decreases and the H. OUT transistor is turned off, each energy stored in LDY, Lm, LP of
FTB is transferred to C1, C2 and C3, respectively, and the
resonant current becomes zero at a center of the flyback period. Then, VA and VB pulses show a maximum amplitude.
VA
FBT

VA

LDY
FBT

IP1

C1

C2

LDY
IP2
H.OUT

IY2

Cs

lP

IY

lP

IY

+
Cs
IM
VB

CSM

LM
IDC

DM
+

CSM

Fig. 10-9

Fig. 10-7
Voltage & current waveform in H period.

IY

VA

LM
IDC

VB
IM

VB

VB

IY

0

VA

0

IM

0
IDC

0

0

0

IM

0
IDC

VB

VB

0

C1
C2

0

C3

0

C1: IY1+IP1
C2: IY2+IP2

Fig. 10-8
C3: IP2-IY1-IM

Fig. 10-10
84

3-1-3. Later Half of Flyback Period

3-1-4. First Half of Scanning Period

All energy in the coil has been transferred to the resonant
capacitors at the center of the flyback period, and the voltage shows the maximum value. However, during next half
of the flyback period, the energy of the resonat capacitor is
discharged as a reverse current through respective coil. When
the discharge has been completed, VA and VB becomes zero,
and the deflection current in reverse direction becomes the
VA
maximum.

When the flyback period completes, the damper diode DD
and the modulation diode DM turn on, and the IY and IM
proportionally decrease from the maximum value to zero.
The H. OUT transistor is turned on just preceding at the center
of the scanning period, and repeats the steps 3-1-1 through
3-1-4 stated above.
VA

L.O.P.T
LDY

IP2
IP1

FBT

IY

LDY

IP

C2

C1

IY

DD

CS

CS

IY2

IY1

VB
C3
IM

VB

VB

LM

IM

DM

IDC

VB

LM
IM

CSM

CSM

Fig. 10-11

Fig. 10-13
Voltage & current waveform in H period.

Iy

0

IY

VA

0

IM

0
IDC

VB

C1
C2

VA

0

0

IM

0
IDC

VB

0

0

0

C1: IY1+IP1
C2: IY2+IP2

Fig. 10-14

C3

0

C3: IP2-Iy1-IM.

Fig. 10-12
85

SECTION XI: DIGITAL CONVERGENCE CIRCUIT
1. OUTLINE

2. CIRCUIT DESCRIPTION

The digital convergence circuit develops outputs to correct
screen distortion and perform color matching. The digital
convergence circuit used is of an all digital type and allows
good adjustments in comprise with a conventional analog type
circuit.

2-1. Configuration
Fig. 11-1 shows a block diagram. The digital convergence
unit consists of Q701 T7K64 which plays a major role, Q707
PLL circuit which locks a sync entered, Q713 E2PROM to
store the data, and Q703-5 D/A converter which develops a
correction wave form.

Followings are features of the digital convergence circuit.
1)

No adjustment controls (volumes)

2)

Registration accuracy increased.

3)

Space saved

4)

Adjustment by a remote control

The output signal from the Q703 – 705 D/A converter is
amplified and wave form shaped by Q715, Q717 and Q719,
and comes out from the unit.
The clock signal for the PLL is adjusted by L719 to a reference frequency of 32 ± 0.1MHz under no input status.

The data adjusted are classed into 4 screens for each screen
mode. These data are stored on E2PROMs inside the unit.
The memory size used in this case is 4 Kbits per one screen.

A test pattern generator is also built inside Q701 and develops R, G, B signals and a Ys switching signal.

Each screen adjustment is carried out by calling the adjustment screen with the remote control unit supplied and the
adjustment is carried out according to the dimensions specified for each screen. The control of the unit is carried out in
the I2C format.

2-2. Circuit Description

86

(1)

With the power turned on, the unit is reset and enters
an operation standby status. And a sync signal of the
unit enters external Q707 and Q701. The signal entered Q707 is counted down by a counter inside the
Q701 and this is used as the reference clock. Q701
works in synchronization with the reference clock signal and the sync signal.

(2)

A command is sent from the microcomputer in the unit
and Q701 is set up to load the data in Q713 to the internal RAM. (8 (horizontal) x 7 (vertical) x 3 (color))

(3)

Q701 transfers a serial data specified to Q703 – 705
according to the RAM data. In this case, interpolation
for the RAM data is automatically carried out by a built
-in digital filter inside Q701.

(4)

The serial data sent from Q701 are digital-analog converted by Q703 – 705, thus developing the analog type
wave form.

(5)

The signals sent from Q703 – 705 are amplified Q715,
Q717, Q719, respectively, and then filtered in the next
stage to smooth and shape the wave form. Thus processed signals are used as H and V correction wave
forms for R, G, and B signals.

Fig. 11-1 Block diagram

87

Save

M-CON

Q767

CLK

Main bus line

RESET

R716, C711

Load

E 2PROM
MEMORY

Q713

Q719

Q707
PLL

32MHz

Counter

RAM (8 ∗8∗12bit) ∗3

Q701 T7K64

DATA

VD

HD

Q705

Q704

Q703

Ys

B

G

R

D/A

D/A

D/A

Q719

Q717

Q715

Test pattern

Filter

Filter

Filter

Filter

Filter

Filter

BV

BH

GV

GH

RV

RH

3. PICTURE ADJUSTMENT
The data adjusted manually through the screen by displaying
the adjusting screen on the display is once written on RAM
inside Q701. Adjust each adjusting point and store the modified total data on RAM as correct one into Q713 E2PROM.

Four screens for Normal/Full, Theater wide 1, Theater Wide
2, Theater Wide 3 are provided for the adjustments. When
making the adjustments, receive the U/VHF or CABLE
broadcasting signal or the built-in pattern signal of the microprocessor to make a synchronization with the frequency
of the adjusting screen with the unit..

The adjustment is carried out for each screen mode, and its
order is as follows; Normal/Full ® Theater Wide 1 ® theater Wide 2 ® Theater Wide 3. (When the adjustment value
is saved after adjusting Normal/Full, the microprocessor calculates the adjustment values for Theater Wide 1, 2 and 3
based on the adjustment value of Normal/Full mode and sets
the values for Theater Wide 1, 2 and 3 to the closed values to
require minimum adjustment.)

This adjustment program is prepared as the microprocessor
function of the set and it is possible to adjust by the remote
controller attached.

3-1. Outline of the Modification Process of
the Storing Adjustment Data
Set the convergence adjustment screen.
The adjusted data is stored in the memory inside Q713
E2CPROM which is a non-volatile memory.
The RAM data inside Q701 is lost when the power turns
off. So the initial operation status is set by the software command from the microprocessor QA01 every time when the
unit turns on.

Normal full distortion
modification
(G screen)

Theater wide 2
distortion modification
(G screen)

Normal full
color matching
(R, B screen)

Theater wide 1
distortion modification
(G screen)

Theater wide 1
color matching
(R, B screen)

1. Push "7" key of the remote
controller to save.

1. Push "7" key of the remote
controller to save.

2. turn "PIC-SIZE" key of the
remote controller ON

2. turn "PIC-SIZE" key of the
remote controller ON

Theater wide 2
color matching
(R, B screen)

Theater wide 3
distortion modification
(G screen)

Theater wide 3
color matching
(R, B screen)

1. Push "7" key of the remote
controller to save.

1. Push "7" key of the remote
controller to save.

2. turn "PIC-SIZE" key of the
remote controller ON

2. turn "PIC-SIZE" key of the
remote controller ON

Fig. 11-2

88

END

3-2. Service Mode
3-2-1. Outline

3-2-2. Entering/Exiting Mode

The service mode, one of the functions this unit provides, is
controlled by the microprocessor QA01 and .

When the “MUTE” key on the remote controller is pressed,
the screen display appears. Pushing the “MUTE” key again
disappears the screen display.

This mode is set by the special operation to avoid the easy
operation by the user. Move the cursor to between the adjustment points of 8*7/each color and modify the data directly.
Before entering the service mode, perform the center adjustment using the color unmatching adjustment in the user menu.

In this status, when the “MENU” key on the set console is
pushed while pushing the “MUTE” key, S is displayed on
the upper right of the screen. When the “MENU” key is
pressed again, the service data is displayed on the upper left
on the screen.
When “7” key on the remote controller is pressed in this status, the screen changes to display the cross hatch screen (the
first screen described later) and the convergence adjustment
screen appears.
When “7” key is pressed again, the data storing operation is
automatically carried out and the cross hatch + data display
screen (the second screen described later) appears.
When “7” key is pressed furthermore, the display returns to
the initial screen.

X + X + MENU
Service data display
(original picture)

The first picture
Remote
"7" key

The second picture

Remote "7" key
+automatic save

Fig. 11-3

Note:
When changing the convergence correction data, always be
sure to perform the automatic storing operation. If the power
turns off without carrying out the automatic storing operation, the modified data is lost.

89

Remote
"7" key

3-2-3. Initial screen
The screen mode is Normal/Full screen mode.
Correction point: Vertical 8 * Horizontal 7 (® and - marks
are the adjusting points.)
Primary screen

Secandary screen
Cursor (Red) (Blinking)

Y
1
2

Data display

3

4
X:3
Y:2
C:R
S:FULL

5
6
7

X 1

2

3

4

5

Adjusting point display
X : Horizontal position display
Y : Vertical position display
C : Color display
S : Screen mode display

6

7

8

Screen Center

Screen frame

Fig. 11-4
(1)

First screen:

(2)

The initial cross hatch screen appears. The pattern colors are displayed with 3 colors. The cursor color is red
and left blinking.

When changing from the first screen to second screen, the
convergence correction waveform is mute for 1 second. The
modified data for this period is sent to Q713 E2PROM from
Q071 RAM and then stored.

When the modification is carried out, the last memory
status is displayed.

The second screen is displayed upper left of the first screen,
so the convergence adjustment cannot be carried out when
the second screen is displayed.

Cursor mode:
Lighting:

Data modification mode

Blinking:

Cursor move mode

Second screen

Note:
• The adjusted data is automatically stored when the display changes from the first screen to the second screen.
So be sure to perform this operation after adjustment completes.

The display color shows the color which can modify
the data.

• Adjustment should be carried out with a corresponding
signal received.

90

3-2-4. Key function of remote control unit

PIC

TV
CABLE
VCR

SIZE RECALL

TV/VIDEO

POWER

MUTE

9

6

1

2

3

4

5

6

7

8

Blue test pattern ON/OFF

Key

Cursor shift/data change

5 8

Key

Cursor down/adjusting point down

6 2

Key

Cursor UP/adjusting point UP

7 6

Key

Cursor right/adjusting point right

8 4

Key

Cursor left/adjusting point left

9 3

Key

Cursor color change

10 7

Key

Data save

7

mode chang over

9
CH RTN

1

100

2
EDS

FAV

0

ENT

VOL

5

¥
3

ADV/
PCB CH

MENU

ENTER

FAV

RESET

EXIT

ADV/
POP CH
STOP SCURCE

REC

CH SEARCH

TV/VCR

Green test pattern ON/OFF

Key

4 5

4
10

Red test pattern ON/OFF

2 0

3 ENT Key
CH

8

1 100 Key

PLAY PCP

REW

STILL

FF

SWAP

TOSHIBA

Fig. 11-5

91

3-2-5. Operation procedure
(1)

Set the screen to Normal or Full mode using the PICSIZE key on the remote controller.

(2)

Set the unit to the service mode with MUTE + MUTE
+ MENU keys pressed. (Entering to S mode.)

(8)

When the adjusting position is determined, press “5”
key on the remote controller to enter the cursor blinking status.

(9)

(3)

Set the unit to the convergence adjusting mode by pressing the “7” key on the remote controller. (Fist screen)

Set the cursor to the adjusting position by pressing “2”,
“8”, “4” and “6”, and perform the pattern distortion
correction and color matching adjustments.

(4)

Select the pattern to display by pressing 100, 0, ENT
on the remote controller.

(10) Press “5” key again and move the cursor. Perform the
adjustment in the same way as described above.

(Red adjustment; 100 ... ON, 0 ... ON, ENT... OFF)

(11) After the adjustment completes, perform the automatic
storing operation by pressing “7” key.

(Green adjustment; 100 ... OFF, 0 ... ON, ENT... ON)

(12) In the same way as described above, adjust WIDE 1,
WIDE 2 and WIDE 3 screens using PIC-SIZE key.

(Blue adjustment; 100 ... ON, 0 ... OFF, ENT... ON)
(5)

Select the color to adjust by pressing “3” key on the
remote controller.

(6)

Confirm that the cursor is in the movable status (the
cursor blinking status).

(7)

Select the adjusting position by pressing “8”, “4” and
“6”.

(13) When all of the screen mode adjustment complete,
perform the automatic storing operation by pressing
“7” key.

3-3. Each Screen Adjustment Method

14xB

B
2

B
2

3-3-1. Normal/Full

12xA
2mm

2mm
Screen frame
40 inches 16:9 Screen size: Horizontal 885mm x Vertical 498mm
Dimension A: 73.5mm Dimension B: 33.2mm

Fig. 11-6
92

3-3-2. Theater Wide1

249
213

103.5
Screen
center
0
7.5

115

217.5

428.5

351

205

66.5

0

66.5

205

351

428.5

249

40 inches 16:9 Screen size: Horizontal 885mm x Vertical 498mm

Fig. 11-7
348.5
298

144
Screen
center
0
10

159

303

56 inches 16:9 Screen size: Horizontal 1239mm x Vertical 697mm

Fig. 11-8
93

605

495.5

289.5

93.5

0

93.5

289.5

495.5

605

348.5

3-3-3. Theater Wide 2

298.9
256.2

128.1
Screen
center
0

128.1

256.2

435

362.5

217.5

72.5

0

72.5

217.5

362.5

435

298.9

40 inches 16:9 Screen size: Horizontal 885mm x Vertical 498mm

Fig. 11-9

361.8
301.5

180.9
Screen
center

0

180.9

301.5

56 inches 16:9 Screen size: Horizontal 1239mm x Vertical 697mm

Fig. 11-10

94

618

515

309

103

0

103

309

515

618

361.8

3-3-4. Theater Wide 3

269.5
231

115.5
Screen
center

0

115.5

362.5

435

515

618

217.5

72.5

0

72.5

217.5

362.5

435

231
269.5

40 inches 16:9 Screen size: Horizontal 885mm x Vertical 498mm

Fig. 11-11

379.2
325

162.5
Screen
center

0

162.5

325

309

103

0

103

309

515

618

379.2

56 inches 16:9 Screen size: Horizontal 1239mm x Vertical 697mm

Fig. 11-12

95

4. CASE STUDY
4-2. When Convergence Unit is Replaced

In many cases, a color deviation will be corrected by returning the HIT and WID data for the main deflection side to the
initial values.

When replacing the convergence units, all screens must be
adjusted basically. However, performing the adjustment as
shown below will reduce the procedures considerably.

Followings are cases which need readjustment of the convergence by all means.

(1)

Replace the memory (Q713) for the new unit with the
memory (Q713) for the failure unit. Mount the convergence unit on the set and the screen status before
replacement will be directly reproduced.

(2)

Mount the new unit with the old memory installed in
combination on the set, and turn on the set. A screen as
if it is moving vertically or horizontally will appear.

(3)

Adjust each center of green, red, and blue with the centering magnets again.

(4)

Check to see color deviation and screen size deviation
among the colors. If deviated, perform the adjustment
for the main deflection and the color matching for the
convergence.

4-1. When CRT is Replaced.
When the CRT is replaced, readjustment of the main deflection and color matching will be necessary. Perform the adjustments as follows.
(1)

Replace two CRTs, blue and red.

(2)

Perform horizontal adjustments for blue and red yokes
to the green CRT. Mount the yokes and velocity modulation coils + alignments so that they closely touches
the CRT without any clearance.

(3)

Adjust the red and blue alignments. (refer to item Detailed adjustments for alignments)

(4)

Perform the center adjustment for the blue CRT center
and the red CRT center to the green CRT center with
the centering magnets.

(5)

Adjust the HIT, WID data to obtain the data which gives
the most precision to the green.

(6)

Perform the color matching in terms of the convergence
for each screen. In this case, do not move the green.

(7)

After completion of the convergence adjustment for
each screen, replace the green CRT. For the green CRT,
repeat the steps 2-5 to make the color matching in terms
of the convergence by using the red and blue as the
reference.

96

5. TROUBLESHOOTING
5-1. Adjusting Procedure in Replacing CRT

Cut off

User convergence enter check

Lens focus

Centering

Electrical focus

Convergence adjustment

Yoke horizontal

White balance

End

5-2. Adjusting Procedure in Replacing Convergence Unit/Main Def

User convergence enter check

Centering

Convergence adjustment

End

97

6. CONVERGENCE OUTPUT CIRCUIT
6-1. Outline

6-2-4. CONV-OUT mute

This circuit current-amplifies digital convergence correction
signal at output circuit, and drives by convergence yoke to
perform picture adjustment.

In power-on operation, transistors Q765 and Q766 are made
turned ON, and –15V is applied to pin 3 of CONV-OUT IC.
These cause mute operation on CONV-OUT.

Digital convergence output signal 6ch adjustment is done.

6-2-5. Operation of IC

(H-R/G/B)

1) Q764 (TC74HC4050AP)

(V-R/G/B)

Sync signal which is input from P711 1 VD, 2 HD, is,
through buffer, supplied to digital convergence P708.

6-2. Circuit Description

2) 3-terminal source
6-2-1. Signal flow

Q754 (+5V) Q755 (+9V) Q756 (-9V)

Signal which is corrected by digital convergence, is output to
P708 (V, H R/G/B);

Source for digital convergence
3) Q767 (TC4066BP)

is input to Q751 (V) R/G/B, and is output to P713, P714 and
P715;

P711 4 SDAM, 5 SCLM : microcomputer. Busline, through
Q767, is input to Digital Convergence P709, and is controlled.

is input to Q752 (H) R/G/B, and is output to P713, P714 and
P715.

4) To adjust from outside of digital convergence :
Put adjusting jig into 6P socket of P720. Iscs turns from H to
L, switch of Q767 is changed over. Then busline from microcomputer is cut off.

6-2-2. Over current protection circuit
All currents of Power supply, -15V, +15V and +30V are detected to protect CONV-OUT IC from damage due to output
short of CONV-OUT.
Current value:

P720 3 SCLU, 4 SDAU
Controlled by external adjusting jig.

Normal ± 15V approx. 700mA
+30V approx. 200mA
Detecting curren ±15V approx. 1.8A
or more
+30V approx. 700mA or more
protecting operation

6-2-3. Pump-up source
CONV-OUT IC Q752 (H)
Pin 10 (+15V/H, PV)
Pin 5 (+30V)
By HD input signal, pump-up is done only in horizontal retracing time.
Pump-up
Pump-up source waveform
Horizontal correction wafeform
+30V

+30V

+15V

+15V

0V
0V

-15V

-15V
Horizontal correction waveform

Fig. 11-13
98

P708

Fig. 11-14

99

SCLM
SDAM

TC4066BP

Q767

(HD)

+30V

+
C7765

+
C7766

(HD)

C7771

P

I2CS
SCLV
SDAU

R
G
B

HD
VD

TC74HC4050

Q764

1
2
3
4
5

+9V
-9V
+5V

RH
GH
BH

-9V

Q756

+9V

Q755

MUTE

Q765

5

Q766

3

B-H

5

3

B-V

MUTE

Q769

Q770

Q771

1
2
3

RV
GV
BV

DIGITAL CONVER

8

9

G-V
12

4

8

9

G-H
12

CONV-OUT
(+1501
(H)
10 H.PU)

4

10

5V-1

CONV-OUT

+15V

(PUMP UP)

D7702

D7701 Q757

P712

+5V

+5V-1
RESET
POWER
AC PULSE
GND

Q754

+12V
NC
PROTECT

(REGULATER)

(PROTECTOR)

-15V

11

11

17

R-H
17

Q752
STK392-110

R-V

Q751
STK392-110

18

18

0.39Ω

R7765

0.33Ω

R7750

0.82Ω

R7782

H

V

H

V

H

V

P715
GREEN

P714
BLUE

P713
RED

CONVER
YOKE

(-15V)

(+15V)

(+30V)

6-3. Convergence Block Diagram

P711
1
2
3
4
5
6
7

1
2
3
4
5
6

VD
HD
I2 CS
SDAM
SCLM
GND
DFAI

P720

GND
INCS
SCLU
SDAU
GND
GND

7. CONVERGENCE TROUBLESHOOTING CHART

Relay turns on
once but immediately
turns off.

Reray OFF

Relay operation sound
at power on.

Reray ON

No Convergence
correction wave.

OK

Check screen modes
of picture.
Convergence PCB,
pull out of P712.

Protect 1

Reray ON
Reray ON
Check power
supply circuit.

Reray OFF

Check Q751, Q752
and repair.

Reray OFF

Reray OFF
Check P708 R/G/B
correction wave.

Proceed to "protection
circuit diagnosis procedures".

OK

Check voltage at
±15V+30V pump up.

Convergence output signals correction wave

NG

Check power supply
circuit.

OK

Pump-up
NG

Are output signals
applied to H, Vblk of P711.

Check DEF PC13.

+30V
OK

Check voltage across
±9V+5V Q754, Q755, Q756.

0V

OK

-15V
Vertical
Q751
(R/G/B)

Horizontal
Q752
(R/G/B)

Check signals of all IC
and associated cirduits.

Fig. 11-6

100

NG

Check Q754, Q755,
Q756 and repair.

A/V UNIT

QV01 A\V SW

MAIN UNIT

VIDEO2(Y,L,R or DVD (L,R)

V2

TV2
SCL

HY01

DVD (Y, Cr, Cb) DVD (Y)

ANT2

ANT1

SDA

TV1-V, L, R

TUNER/IF

H003

VIDEO1 (V, Y, C, L, R)
VIDEO2
(V.L.R) or
DVD (Y,L,R)
DVD (Y.L.R)

TA1218N V 1

SCL SDA

TV1
(V.L.R)

TV2-V

ATF2

RF
SW

CVD (Cr, Cb)
DVD IN

SYNC-AV1

H001
TUNER

FRONT
SURROUND
UNIT

TUNER

SCL SDA

ATF1 RWL

L RS C LS D A

L

FRONT
LAMP

V-AV
QS101

LA4282

+

L
L
S U R R O U N DR
R
SW

R

MONITOR OUT (V, L, R)

L.R
V3(V.Y.C.L.R)
PIP-V
Y.C

Q601

H002

VARI OUT (L,R)

V-AV
Y.C

R
+38V

W(SBS)

+

L

QS101

S601
EXT

MUTE

L, R

SCL

C

BUSY
DATA
OSD RST

B
HD

VD

SUB
V

Y/C
SEP.

Y
C

HD
RMT OUT
VD
RMT
RESET
+5V-1
POWER

Y

Y

Q

Q

DVD SW
I
UNIT
CSP

S.V.M
UNIT
V.S.M
+125V DRIVE
+12V
RETURN

B

ABL

I

SCL
SDA
Y
C

I

DUAL
UNIT
SCP

Y

HEATER
+200V
BLK

VIDEO/
CHROMA
TA1222AN

Y

V.M. COIL
L472 L473 L474
(R)
(G)
(B)

V901
ORT DRIVE
(RED)
UNIT

PICTURE
TUBE (RED)
30.7kV

Q
OSD Y5

I

V902

OSD R
OSD G

Q

TO CRT
FOCUS
(G4)

Q830

SCP

SDA

B

G

BLK

R
G
B

+5V-3
Q832

PICTURE
TUBE (GREEN)
30.7kV
V903

TO CRT R
SCREEN G
(G2)
B
DOF
Eo

Q831
+9V

R
HD-OUT

+5V-2
S C PAUTO LIVE
SCL
UNIT

ORT DRIVE
(GREEN)
UNIT

Z410 FUCAS PACK

H-OUT

OSD B

FRONT
UNIT

POWER
SWITCH

G

VP-OUT

FRONT
KEYS

SYNC IN
C-IN

FBP

VIDEO 3
INPUT

BUFFER

ZY01 CFM113

SUPER
LIVE
NORMAL
WIDE

FRONT
UNIT

DATA
OSD RST

I
Q

VD

C S OSD/EDS/
CC/RGB SW R
BUSY
G
UNITCP

YSW Y Cr Cd

Y
SCL
WAC
I
SDA
UNIT
VP
Q
HDY I Q BLK

V-AV
YS

VD
HD

S C LS D A
CLK

CLK
CS

KEY A
KEY B

Y-IN

BUFFER

R

R

BUFFER

S Y N C O U TV . S . M .

TMP87CS38N
-3320

ACP

SDA

FRONT SP
OR CENTER SP

EXT
SPEAKER
UNIT

S

SDA

I 2 C STOP
DVD SW
SYNC VCD

INT

Y

SCL
Y

C

SCL 0
SDA 0

FRONT

Ym/Power off

3D. Y/C
SEPA.
UNIT
Y

SCL
SDA

24LC088 I/PS D A 0
+5V-1

Q501

Y . C VIDEO

I 2 C STOP

MEMORY
EEPROM S C L 0

L

FRONT

YS/YM
MUTE
INT/EXT
SYNC-AV1

QA02

EXT SP (R) FRONT

EXT SP

QA01
MICROCOMPUTER
AFT2
AFT1

EXT SP (L) FRONT

ORT DRIVE
(BULE)
UNIT

PICTURE
TUBE (BULE)
30.7kV

+9V-2

PHOTO
DIODE

V
H

REMOTE
SENSOR

DEF YORK
L462, L463, K464
SUPER LIVE

OVER CURRENT
PROTECT

PLL

RELAY
DRIVE

DC12VTV-8

Q705

F851 125V5A

DAC

BH

L462
BLUE
CONVER
YOKE

Q719
BH

+30V

POWER1
UNIT

Q755
+15V

+9V
Q754

-15V

+5V
Q756
-9V

DIGITAL
CONNER
T7064

Q704
GH

L462
GREEN
CONVER
YOKE

DAC

Q701

GH

Q713

WIDE
WIDE
V-SHIFT

F860
125V5A

D801

Z801

PHOTO COUPLER
TLP621 (GR-L)

PROTECTION
HIC1019

POWER

AMP

STK392-110

4
+12V
+35V
-27V

F870
250V2A
+125V

+125V
+125V

7

Q401

HOR.
OUT
2SC2253FA

FOCLS

6
5

Z450 CR BLOCK
TPA5007

2
3
1

Q402
HOR.
DRIVE

Q404

Q752
RH
BH
GH

+9V-1
Q420

F889
125V5A
+38V

2SC1589
PROTECT

Q717

+12V

OVER
VOLTAGE
PROTECT

HV

AFC
10
HEATER
9

F890
125V5A

Q862

Q801

Z862
TPW3330AM

POWER
RELAY
SR81

F850
125V3.15A

T888

CONVERTER TRANS

Q802
D802-D805

L462
RED
CONVER
YOKE

RH

LOW VOLTAGE
PROTECT

WF
CIRCUIT

NORMAL

T400

STK392-110
RH

DAC

OVER VOLTAGE
PROTECT

H-5
CORECTION

ABL SELECT

BLANKING

Q301
V-BLK OUT
IN V E R T I C A L
LA78335

X-TAL

DIGITAL CONVERGENCE LNIT
Q707
Q703
Q715

QB43 QB30

STR57041

AC120V
60Hz

LINE
FILTER
TRF3205M

VOLTAGE REG.

F801
125V7A

D840
S1WA20

SCL
SDA +9V
V D-27V+ 3 5 V

RESET

CONVERTER
TRANS TPW3332A5

T840
TPW1459AZ
T801
T802

STB5V

STR-Z23201

L78MR05

VOLTAGE REG.

STANDBY
+5V REGU

DPC
UNIT D P C WF

RV
C O N V E R O U T P U TB V
AMP
GV

DQF

Q487, Q488, Q489
BLK
V-BLK
V-STOP H-BLK

Q751

8

ABL

HV REGU.
CIRCUIT
Q483, Q480

T461 FBT
TFB3078AD

DEF H.V UNIT

Source Exif Data:

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PDF Version                     : 1.3
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Create Date                     : 1997:04:14 15:36:14
Producer                        : Acrobat Distiller 3.0 for Windows
Subject                         : toc
Author                          : John Swendiman
Creator                         : Adobe PageMaker 6.5
Title                           : toc
Modify Date                     : 2001:02:05 09:24:37-06:00
Page Count                      : 101
Page Mode                       : UseOutlines
Has XFA                         : No

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Toshiba Tw40F80 Technical Training Manual Toc

TW40F80 to the manual 9d699d9e-c699-44ff-a762-9b3b908906d0

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