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Never stop thinking.Product Overview T3130-8XV10PO5-7600Jan 2007 PBA 31308Bluetooth QD ID: B012097/B012098UniStoneBlueMoon Universal Platform

Edition 2007-01-31Published by Infineon Technologies AG81726 Munich, Germany© Infineon Technologies AG 2007.All Rights Reserved.Attention please!The information herein is given to describe certain components and shall not be considered as warranted characteristics.Terms of delivery and rights to technical change reserved.We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein.Infineon Technologies is an approved CECC manufacturer.InformationFor further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide (see address list).WarningsDue to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office.Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.

UniStoneProduct Overview 4 T3130-8XV10PO5-7600, 2007-01-31 PBA 31308 Revision History: 2007-01-31 T3130-8XV10PO5-7600Previous Version:Section Subjects (major changes since last revision)

UniStoneProduct Overview 5 T3130-8XV10PO5-7600, 2007-01-31 1 General Device Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81.3 Pin Configuration LGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91.4 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91.5 System Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121.6 FW version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Basic Operating Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142.1 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142.2 Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153.1 HCI / UART Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153.1.1 Supported Transport Layers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153.1.2 UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153.1.2.1 Baud Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163.2 PCM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173.2.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183.3 WLAN Coexistence Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 General Device Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204.1 HCI+ and Bluetooth Device Data (BD_DATA) . . . . . . . . . . . . . . . . . . . . . . 204.2 Manufacturer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204.3 Firmware ROM Patching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204.3.1 Patch Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 Bluetooth Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225.1 Supported Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225.2 UniStone Specifics and Extensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225.2.1 During Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225.2.1.1 Scatternet and Piconet Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . 225.2.1.2 Role Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225.2.1.3 Dynamic Polling Strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235.2.1.4 Adaptive Frequency Hopping (AFH) . . . . . . . . . . . . . . . . . . . . . . . . . 235.2.1.5 Channel Quality Driven Data Rate Change (CQDDR) . . . . . . . . . . . 235.2.2 Synchronous Links . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235.2.2.1 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245.2.2.2 Voice Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245.2.3 RSSI and Output Power Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245.2.3.1 Received Signal Strength Indication (RSSI) . . . . . . . . . . . . . . . . . . . 245.2.3.2 Output Power Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245.2.3.3 Ultra Low Transmit Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

UniStoneProduct Overview 6 T3130-8XV10PO5-7600, 2007-01-31 6.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266.2 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276.3 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286.3.1 Pad Driver and Input Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286.3.2 Pull-ups and Pull-downs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316.3.3 Protection Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316.4 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336.4.1 Characteristics of 32.768 kHz Clock Signal . . . . . . . . . . . . . . . . . . . . . . 336.5 RF Part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336.5.1 Characteristics RF Part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336.5.1.1 Bluetooth Related Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387.1 Package marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387.2 Production Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387.2.1 Pin mark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398 Acronyms & Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

UniStoneGeneral Device OverviewProduct Overview 7 T3130-8XV10PO5-7600, 2007-01-31 1 General Device Overview1.1 FeaturesGeneral• Complete Bluetooth 2.0 + EDR solution• Ultra low power design in 0.13 µm CMOS• Temperature range from -40°C to 85°C• Integrates ARM7TDMI, RAM and patchable ROM• On-module voltage regulators. External supply 2.9-4.1V• On-module EEPROM with configureable data• Reference clock included• Low power clock from internal oscillator or external low power clock (e.g. 32.768 kHz)• Dynamic low power mode switchingInterfaces• 3.25 MBaud UART with transport layer detection (HCI UART, HCI Three-Wire UART)• PCM/I2S interface for digital audio• WLAN coexistence interface• General purpose I/Os with interrupt capabilities. JTAG for boundary scan and debug RF• Transmit power programmable from -45 dBm to 4.5 dBm• Transmit power typ. 2.5 dBm (default settings)• Receiver sensitivity typ. -86 dBm• Integrated antenna switch, balun and antenna filter• Integrated LNA with excellent blocking and intermodulation performance• No external components except antenna• Digital demodulation for optimum sensitivity and co-/adjacent channel performanceBluetooth• Piconet with seven slaves. Scatternet with two slave roles while still being visible• SCO and eSCO with hardware accelerated audio signal processing• Power control and RSSI. Hold, Park and Sniff.• Adaptive Frequency Hopping, Quality of Service, Channel Quality Driven Data Rate• Bluetooth security features: Authentication, Pairing and Encryption• Bluetooth test mode and Infineon’s active Bluetooth tester mode

UniStoneGeneral Device OverviewProduct Overview 8 T3130-8XV10PO5-7600, 2007-01-31 1.2 Block DiagramFigure 1-1 Simplified block diagram of UniStone.UniStonePMB8753BlueMoonUniCellularEEPROMVoltageRegulatorCrystal26 MHzBalun FilterI2CVsupplyLow Power Clock(Optional)32.768 kHzPCM1UART - HCIVDD_UARTVDD_PCM

UniStoneGeneral Device OverviewProduct Overview 9 T3130-8XV10PO5-7600, 2007-01-31 1.3 Pin Configuration LGAFigure 1-2 Pin Configuration for UniStone in Top View (footprint)1.4 Pin DescriptionThe non-shaded cells indicate pins that will be fixed for the product lifetime. Shaded cellsindicate that the pin might be removed/changed in future variants. All pins not listedbelow shall be not connected.0,6A2 A3 A4 A5 A6 A7 A8 A9B1 B2 B3 B4 B5 B6 B7 B8 B9C1 C2 C3 C4 C5 C6 C7 C8 C9D1 D2 D3 D4 D5 D6 D7 D8 D9E1 E2 E3 E4 E5 E6 E7 E8 E9F1 F2 F3 F4 F5 F6 F7 F8 F9A11,2 1,01,0 0,61,21,351,3511,68,7

UniStoneGeneral Device OverviewProduct Overview 10 T3130-8XV10PO5-7600, 2007-01-31 . Pin No. Symbol Input/OutputSupply voltageDuringResetAfterResetFunctionA2 P1.6 I/O/OD Internal1 Z Z Port 1.6A3 RESET# AI Internal1 Input Input Hardware ResetA8 P1.5/CLK32I/O/OD Internal1 Input Input Port 1.5 orLPM clock input (e.g. 32.768kHz)B1 P1.7/WAKEUP_BTI/O/OD Internal1 PD/ InputPD/ InputPort 1.7 orBluetooth wake-up signalB2 P1.8/WAKEUP_HOSTI/O/OD Internal1 PD PD Port 1.8 orHost wake-up signalB3 P1.0/TMSI/O/OD Internal2 PU1) PU1) Port 1.0 orJTAG interfaceB4 P1.4/RTCKI/O/OD Internal2 Z Z Port 1.4 orJTAG interfaceB5 ONOFF I - - Turns off module completelyB9 SLEEPX I/O VDDUART PD H Sleep indication signalC2 P0.9 I/O/OD Internal2 Z Z Port 0.9C3 JTAG# IInternal2 PU PU Mode selection Port 1:0: JTAG1: PortC4 TRST# IInternal2 PD PD JTAG interfaceD1 P0.10 I/O/OD Internal2 Z Z Port 0.10 D2 P0.8 I/O/OD Internal2 PD PD Port 0.8D3 P1.1/TCKI/O/OD Internal2 PU1) PU1) Port 1.1 orJTAG interfaceD4 P0.3/PCMOUTI/O/OD VDDPCM Conf.PD def.Conf.PD def.Port 0.3 orPCM data outD5 P0.2/PCMINI/O/OD VDDPCM Z Z Port 0.2 orPCM data inD9 ANTENNA AI/AO inactive inactive RF input/output single endedE1 P0.12/SDA0I/O/OD Internal2 PU PU Port 0.12 orI2C data signalE2 P0.13/SCL0I/O/OD Internal2 PU PU Port 0.13 orI2C clock signalE3 P1.3/TDO/SLOT_STATEI/O/OD Internal2 Z Z Port 1.3 orJTAG interface orWLAN coexistence interfaceE4 P0.0/PCMFR1I/O/OD VDDPCM PD PD Port 0.0 orPCM frame signal 1E5 P0.1/PCMCLKI/O/OD VDDPCM PD PD Port 0.1 orPCM clock

UniStoneGeneral Device OverviewProduct Overview 11 T3130-8XV10PO5-7600, 2007-01-31 1) Fixed pull-up/pull-down if JTAG interface is selected, not affected by any chip reset.If JTAG interface is not selected the port is tristate.Descriptions of acronyms used in the pin list:E6 P0.5/UARTRXDI/O/OD VDDUART Z Z Port 0.5 orUART receive data F2 P1.2/TDI/RF_ACTIVEI/O/OD Internal2 PU1) PU1) Port 1.2 orJTAG interface orWLAN coexistence interface F3 P0.11/TX_CONFI/O/OD Internal2 Z Z Port 0.11orWLAN coexistence interfaceF4 P0.14/TX_CONFI/O VDDUART Z Z Port 0.14 orWLAN coexistence interfaceF5 P0.7/UARTCTSI/O/OD VDDUART Z Z Port 0.7 orUART CTS flow controlF7 P0.4/UARTTXDI/O/OD VDDUART PU PU Port 0.4 orUART transmit dataF8 P0.6/UARTRTSI/O/OD VDDUART PU PU Port 0.6 orUART RTS flow controlA4, A5, A6 VSUPPLY SI - - Power supplyC1 VREG SO - - Regulated Power supplyF6 VDDUART SI - - UART interface Power supplyC5 VDDPCM SI - - PCM interface Power supplyA1, A7, A9, C8, C9, D7, D8, E8, E9, F1, F9VSS - - GroundAcronym DescriptionI InputO OutputOD Output with open drain capabilityZ TristatePU Pull-upPD Pull-downA Analog (e.g. AI means analog input)S Supply (e.g. SO means supply output)Pin No. Symbol Input/OutputSupply voltageDuringResetAfterResetFunction

UniStoneGeneral Device OverviewProduct Overview 12 T3130-8XV10PO5-7600, 2007-01-31 1.5 System IntegrationUniStone is optimized for a low bill of material (BOM) and a small PCB size. Figure 1-3shows a typical application example.The UART interface is used for Bluetooth HCI communication between the host andUniStone. When the HCI UART transport layer is used, four interface lines are needed:two for data (UARTTXD and UARTRXD) and two for hardware flow control (UARTRTSand UARTCTS). When the HCI Three-Wire UART transport layer is used the hardwareflow control lines are optional. In addition to the standard Bluetooth HCI commands,UniStone supports a set of Infineon specific commands called HCI+.Digital audio can either be sent over the HCI interface or over the dedicated PCM/I2Sinterface. The PCM/I2S interface is highly configurable.Low power mode control of UniStone and the host can be implemented in different ways,either using the dedicated WAKEUP_HOST and WAKEUP_BT signals or usingsignaling over the HCI interface. The host can reset UniStone via the RESET# signal.A low power clock can be connected to CLK32 or generated internally by a low poweroscillator. Power is supplied to a single VSUPPLY input from which internal regulatorscan generate all required voltages. The UART and the PCM interfaces have separatesupply voltages so that they can comply with host signaling.Figure 1-3 Example Bluetooth SystemUniStoneUARTRTSUARTTXDUARTRXDUARTCTSPCMCLKPCMFR1PCMINPCMOUTWAKEUP_HOSTWAKEUP_BTRESET#CLK32HOSTUARTPCM / I2SANTENNARF_ACTIVETX_CONFSLOT_STATEWLANSubsystemVDDSUPPowerSupply OptionalVDDUARTVDDPCM

UniStoneGeneral Device OverviewProduct Overview 13 T3130-8XV10PO5-7600, 2007-01-31 If a WLAN subsystem is collocated with UniStone the WLAN coexistence interfaceshould be used to enhance Bluetooth and WLAN performance. To coexist with externalWLAN devices UniStone supports adaptive frequency hopping.1.6 FW versionUniStone is available in different versions. Please check corresponding releasedocuments for latest information.

UniStoneBasic Operating InformationProduct Overview 14 T3130-8XV10PO5-7600, 2007-01-31 2 Basic Operating Information2.1 Power SupplyBlueMoon UniCellular is supplied from a single supply voltage VSUPPLY. This supplyvoltage must always be present. The Bluemoon UniCellular chip is supplied from aninternally generated 2.5 V supply voltage. This voltage can be accessed from the VREGpin. This voltage may not be used for supplying other components in the host system butcan be used for referencing the host interfaces.The PCM interface and the UART interface are supplied with dedicated, independent,reference levels via the VDDPCM and VDDUART pins. All other digital I/O pins aresupplied internally by either 2.5 V (Internal2) or 1.5 V(Internal1). Section 1.4 provides amapping between pins and supply voltages. The I/O power domains (VDDPCM and VDDUART) are completely separated from theother power domains and can stay present also in low power modes.2.2 ClockingBlueMoon UniCellular has one clock input CLK32 that is optional. If used this 32.768 kHzclock must always be present to assist BlueMoon UniCellular to keep the time in lowpower modes.The low power clock can be generated internally by the crystal oscillator and/or the lowpower oscillator or provided externally.

UniStoneInterfacesProduct Overview 15 T3130-8XV10PO5-7600, 2007-01-31 3 Interfaces3.1 HCI / UART InterfaceThe HCI/UART interface is the main communication interface between the host andUniStone. The standard HCI commands are supported together with an Infineon specificset of commands called HCI+.The interface consists of four UART signals and two wake-up signals as shown inFigure 3-1. Depending on which HCI transport layer that is used, some or all of thesignals are needed. 3.1.1 Supported Transport LayersUniStone supports the HCI Three-Wire UART transport layer and two derivatives of theHCI UART transport layer (HCI UART-4W and HCI-UART-6W) where the only differenceis how low power modes are handled. UniStone automatically detects which transportlayer that is used by the host.3.1.2 UARTThe on-chip UART (Universal Asynchronous Receiver and Transmitter) is compatiblewith standard UARTs and is optimized for Bluetooth communication. Hardware supportfor SLIP1) framing and 16-bit CRC calculation enhances performance with the HCIThree-Wire UART transport layer. A separate supply voltage, VDDUART, makes it easyto connect the UART interface to any system.1) See http://www.ietf.org/rfc/rfc1055.txt for information about SLIP.Figure 3-1 HCI/UART InterfaceUARTTXDUARTRXDUARTRTSUARTCTSWAKEUP_BTWAKEUP_HOSTUARTTXDUARTRXDUARTRTSUARTCTSWAKEUP_BTWAKEUP_HOSTHost UniStone

UniStoneInterfacesProduct Overview 16 T3130-8XV10PO5-7600, 2007-01-31 3.1.2.1 Baud Rates The supported baud rates are listed in Table 3-1 together with the small deviation errorthat results from the internal clock generation. The default baud rate is 115200 Baud.Table 3-1 UART Baud RatesWanted Baud Rate Real Baud Rate Deviation Error (%)9600 9615 0.1619200 19230 0.1638400 38461 0.1657600 57522 -0.14115200 115044 -0.14230400 230088 -0.14460800 464285 0.76921600 928571 0.761843200 1857142 0.763250000 3250000 0

UniStoneInterfacesProduct Overview 17 T3130-8XV10PO5-7600, 2007-01-31 3.2 PCM InterfaceThe PCM interface is used to exchange synchronous data (usually audio) betweenUniStone and the host as well as to connect e.g. an external audio codec or an externalDSP to UniStone. It can be configured as an industry standard PCM interface supportinglong and short frame synchronization, as an I2S interface1) or as an IOM-2 interface interminal mode with reduced capabilities.The main features of the PCM interface are:• Two bidirectional PCM channels• Separate supply voltage (VDDPCM) for easy interfacing to other systems• Support for all sample types defined in the Bluetooth specification (Up to 16-bit linear samples and 8-bit A-law/µ-law compressed samples)2)• 8x32-bit FIFOs for each channel• Programmable frame length• Programmable frame signal length• Programmable channel start positions• Programmable idle level on PCMOUT• Programmable low-power/inactive levels on all PCM pins• Data word LSB justified or MSB justified with respect to frame signal• Clock master/slave mode• Frame master/slave mode• Fractional divider for PCM clock generation1) Does not support variable word length. Hardware supports 16 or 24 bits. Current firmware supports 16 bits.2) The hardware supports data word lengths of up to 24 bits.

$UniStoneInterfacesProduct Overview 18 T3130-8XV10PO5-7600, 2007-01-31 3.2.1 OverviewThe PCM interface consists of four signals as shown in Figure 3-2 belowThe clock signal PCMCLK is the timing base for the other signals in the PCM interface.In clock master mode, UniStone generates PCMCLK from the internal system clockusing a fractional divider. In clock slave mode PCMCLK is an input to UniStone and hasto be supplied by an external source. The maximum PCMCLK frequency (in both modes)is 1/8 of the internal system clock frequency.The PCM interface supports up to two bidirectional channels. Data is transmitted onPCMOUT and received on PCMIN, always with the most significant bit first. Thehardware supports a Data Word Length of 16 or 24 bits. The firmware always uses 16bits since that is the maximum audio sample size (linear samples can be up to 16 bits,A-law or µ-law compressed samples are always 8 bits).The samples are organized in frames such that each frame contains one sample in eachdirection of each active channel. The frame rate (i.e. sample rate) is controlled by thePCMCLK frequency and the programmable Frame Length. In the firmware the samplerate has been fixed to 8 kHz. This means that the PCMCLK frequency can be calculatedfrom Frame Length and does not have to be specified.Channel 1 has a frame signal (PCMFR1) that indicates where in the frame the channelstarts. The Frame Signal Length is programmable. In frame master mode, UniStone generates PCMFR1. In frame slave mode the signalPCMFR1 is an input to UniStone and has to be supplied externally. Figure 3-2 PCM Signals OverviewPCMCLKPCMINPCMFR1PCMOUT MSB1413121110987654321LSBMSB1413121110987654321LSBMSB1413121110987654321LSBMSB1413121110987654321LSBMSB141312MSB141312IDLE IDLEDon’t Care Don’t CareChannel 2 Start PositionFrame Signal LengthData Word LengthFrame Length$