UBS Axcera 840A 10,000-watt UHF solid state television transmitter User Manual Chapter 4

UBS-Axcera 10,000-watt UHF solid state television transmitter Chapter 4

Chapter 4

10-kW UHF Transmitter with Chapter 4, CircuitFeedforward Drive Descriptions840A, Rev. 0 4-1Chapter 4Circuit Descriptions4.1. (A1) Dual 250-WattDriver/Amplifier Assembly(1094334; Appendix A)4.1.1 (A1-A4) UHF Exciter Tray(1094019; Appendix A)4.1.1.1 (A4) Aural IF Synthesizer Board,4.5 MHz (1265-1303; Appendix B)The aural IF synthesizer board amplifieseach of the three possible audio inputsand the amplifier circuits that supply thesingle audio output. The balanced audioor the composite audio input is connectedto the board while the subcarrier audio(SCA) input can be connected at thesame time as either of the other twoinputs. The board has the 4.5-MHzvoltage-controlled oscillator (VCO) andthe aural modulation circuitry thatproduces the modulated 4.5-MHz output.The board also contains a phase lock loop(PLL) circuit that maintains the precise4.5-MHz separation between the aural(41.25 MHz) and the visual (45.75 MHz)IF frequencies.Balanced Audio InputThe first of the three possible basebandinputs to the board is a 600Ω-balancedaudio input (+10 dBm) that entersthrough jack J2, pins 1 (+), 2 (GND), and3 (-), and is buffered by U1B and U1C.Diodes CR1 to CR4 protect the inputstages of U1B and U1C if an excessivesignal level is present on the input leadsof jack J2. The outputs of U1B and U1Care applied to differential amplifier U1A;U1A eliminates the common modesignals (hum) on its input leads. Apre-emphasis of 75 ms is provided byR11, C11, and R10 and can be eliminatedby removing jumper W5 on J5. The signalis then applied to amplifier U1D whosegain is controlled by jumper W3 on J11.Jumper W3 on jack J11 is positionedaccording to the input level of the audiosignal (0 or +10 dBm). If the input levelis approximately 0 dBm, the mini-jumpershould be in the high gain positionbetween pins 1 and 2 of jack J11. If theinput level is approximately +10 dBm,the mini-jumper should be in low gainposition between pins 2 and 3 of jackJ11. The balanced audio is thenconnected to buffer amplifier U2A whoseinput level is determined by the setting ofbalanced audio gain pot R13. The outputof the amplifier stage is wired to thesumming point at U2D, pin 13.Composite Audio InputThe second possible audio input to theboard is the composite audio (stereo)input at BNC jacks J3 and J13. The twojacks are loop-through connected; as aresult, the audio can be used in anotherapplication by connecting the unusedjack and removing W4 from J12. JumperW4 on jack J12 provides a 75Ω-inputimpedance when the jumper is betweenpins 1 and 2 of jack J12 and a highimpedance when it is between pins 2 and3. Diodes CR9 to CR12 protect the inputstages of U6A and U6B if an excessivesignal level is applied to the board. Theoutputs of U6A and U6B are applied todifferential amplifier U2C, whicheliminates common mode signals (hum)on its input leads. The composite inputsignal is then applied to amplifier U2B;the gain of this amplifier is controlled bycomposite audio gain pot R17. Thecomposite audio signal is connected tothe summing point at U2D, pin 13.Subcarrier Audio InputThe third possible input to the board isthe SCA input at BNC jack J4. The SCAinput has an input impedance of 75Ω thatcan be eliminated by removing jumperW2 from pins 1 and 2 of J14. The SCAinput is bandpass filtered by C66, C14,R22, C15, C67, and R23 and is fed to
10-kW UHF Transmitter with Chapter 4, CircuitFeedforward Drive Descriptions840A, Rev. 0 4-2buffer amplifier U3A. The amplified signalis then applied though SCA gain pot R24to the summing point at pin 13 of U2D.Audio Modulation of the VCOThe balanced audio, or the compositeaudio and/or the SCA-buffered audiosignals, are fed to the common junctionof resistors R14, R20, and R27 thatconnect to pin 13 of amplifier U2D. Theoutput audio signal at pin 14 of U2D istypically .8 Vpk-pk at a ±25-kHzdeviation for balanced or .8 Vpk-pk at±75-kHz deviation for composite asmeasured at TP1. This signal is applied toVCO U10. A sample of the deviation levelis amplified, detected by U7A and U7B,and connected to J10 on the board. Thisaudio-deviation level is connected to thefront panel meter through the transmittercontrol board.The audio is connected to CR13 to CR16;these are varactor diodes that frequencymodulate the audio signal onto thegenerated 4.5-MHz signal in U10. U10 isthe 4.5-MHz VCO that generates the 4.5-MHz continuous wave (CW) signal. Theoutput frequency of this signal ismaintained and controlled by thecorrection voltage output of U5 PLL IC.The audio-modulated, 4.5-MHz signal isfed to amplifiers U11A and U11B. Theoutput of U11B is connected to the 4.5-MHz output jacks at J7 and J8.Phase Lock Loop (PLL) CircuitA sample of the signal from the 4.5-MHzaural VCO at the output of U11A isapplied to PLL IC U5 at the Finconnection. In U5, the signal is divideddown to 50 kHz and is compared to a 50-kHz reference signal. The referencesignal is a divided-down sample of thevisual IF, 45.75-MHz signal that isapplied to the oscillator-in connection onthe PLL chip through jack J6 on theboard. These two 50-kHz signals arecompared in the IC and the fV, and fR isapplied to the differential amplifier U3B.The output of U3B is fed back throughCR17 to the 4.5-MHz VCO IC U10; thissets up a PLL circuit. The 4.5-MHz VCOwill maintain the extremely accurate 4.5-MHz separation between the visual andaural IF signals; any change in frequencywill be corrected by the AFC errorvoltage.PLL chip U5 also contains an internal lockdetector that indicates the status of thePLL circuit. When U5 is in a "locked"state, pin 28 goes high and causes thegreen LED DS1 to illuminate. If the 4.5-MHz VCO and the 45.75-MHz oscillatorbecome "unlocked," out of the capturerange of the PLL circuit, pin 28 of U5 willgo to a logic low and cause the red LEDDS2 to light. A mute output signal fromQ3 (unlock mute) will be applied to jackJ9. This mute is connected to thetransmitter control board.Voltage RequirementsThe ±12 VDC needed for the operation ofthe board enters through jack J1. The+12 VDC is connected to J1-3 andfiltered by L2, C3, and C4 before it isconnected to the rest of the board. The -12 VDC is connected to J1-5 and filteredby L1, C1, and C2 before it is connectedto the rest of the board. +12 VDC isconnected to U8 and U9; these are 5-voltregulator ICs that provide the voltage tothe U10 and U5 ICs.4.1.1.2 (A5) Sync Tip Clamp/ModulatorBoard (1265-1302; Appendix B)The sync tip clamp/modulator board canbe divided into five circuits: the mainvideo circuit, the sync tip clamp circuit,the visual modulator circuit, the aural IFmixer circuit, and the diplexer circuit.The sync tip clamp/modulator boardtakes the baseband video or 4.5-MHzcomposite input that is connected to thevideo input jack (either J1 or J2, whichare loop-through connected), andproduces a modulated visual IF + auralIF output at output jack J20 on theboard. The clamp portion of the board
10-kW UHF Transmitter with Chapter 4, CircuitFeedforward Drive Descriptions840A, Rev. 0 4-3maintains a constant peak of sync levelover varying average picture levels(APL). The modulator portion of theboard contains the circuitry thatgenerates an amplitude-modulatedvestigial sideband visual IF signal outputthat is made up of the baseband videoinput signal (1 Vpk-pk) modulated ontoan externally generated 45.75-MHz IFcarrier frequency. The visual IF signaland the aural IF signal are thencombined in the diplexer circuit toproduce the visual IF + aural IF outputthat is connected to J20, the IF outputjack of the board.Main Video Signal Path (Part 1 of 2)The baseband video or the 4.5-MHzcomposite input connects to the board atJ2. J2 is loop-through connected to J1and terminated to 75 watts if jumper W4is on jack J3. With jumper W4 removed,the input can be connected to anothertransmitter through J1; J1 is loop-through connected to J2.Test point TP1 is provided to monitor thelevel of the input. The input is fed to thenon-inverting and inverting inputs ofU1A, a differential amplifier thatminimizes any common-mode hum thatmay be present on the incoming signal.Diodes CR1 to CR4 form a voltage-limiternetwork in which, if the input voltagesexceed the supply voltages for U1A, thediodes conduct, preventing damage toU1A. CR1 and CR3 conduct if the inputvoltage exceeds the negative supply andCR2 and CR4 conduct if the input voltageexceeds the positive supply voltage.The video output of U1A is connected toJ22 on the board. Normally, the video atJ22 is jumpered to J27 on the board. Ifthe 4.5-MHz composite input kit ispurchased, the 4.5-MHz composite signalat J22 connects to the external composite4.5-MHz filter board and the 4.5-MHzbandpass filter board. These two boardsprovide the video-only signal to J27 andthe 4.5-MHz intercarrier signal to J28from the 4.5-MHz composite input. Thevideo through the video gain pot R12(adjusted for 1 Vpk-pk at TP2) connectsto amplifier U1B.The output of U1B, if the delay equalizerboard is present in the tray, connects thevideo from J6, pin 2, to the externaldelay equalizer board and back to thesync tip clamp/modulator board at J6,pin 4. If the delay equalizer is notpresent, the video connects throughjumper W1 on J5, pins 1 and 2. Thedelay equalizer board plugs directly to J6on the sync tip clamp/modulator board.The video from J6, pin 4, is thenconnected through jumper W1 on J5,pins 2 and 3, to the amplifier Q1. Theoutput of Q1 connects to Q2; the basevoltage of Q2 is set by the DC offsetvoltage output of the sync tip clampcircuit.Sync Tip Clamp CircuitThe automatic sync tip clamp circuit ismade up of U4A, Q7, U3B, andassociated components. The circuitbegins with a sample of the clampedvideo that is split off from the main videopath at the emitter of Q3. The videosample is buffered by U3A and connectedto U4A. The level at which the tip of syncis clamped, approximately -1.04 VDC asmeasured at TP2, is set by the voltage-divider network connected to U4A. If thevideo level changes, the sample appliedto U4A changes. If jumper W7 on J4 is inthe Clamp-On position, the voltage fromthe clamp circuit that is applied to thesumming circuit at the base of Q2 willchange; this will bring the sync tip levelback to approximately -1.04 VDC. Q7 willbe turned off and on according to thepeak of sync voltage level that is appliedto U4A. The capacitors C14, C51, C77,and C41 will charge or discharge to thenew voltage level, which biases U3Bmore or less, through jumper W7 on J4in the Auto Clamp-On position. U3 willincrease or decrease its output, asneeded, to bring the peak of sync back tothe correct level as set by R152 and R12.This voltage level is applied through U3B
10-kW UHF Transmitter with Chapter 4, CircuitFeedforward Drive Descriptions840A, Rev. 0 4-4to Q2. In the Manual position, jumper W7on J4 is in the Clamp-Off position,between pins 1 and 2, and adjustableresistor R41 provides the manual clampbias adjustment for the video thatconnects to Q2.Jumper W6 on jack J35 must be in theNormal position, between pins 2 and 3,for the clamp circuit to operate with anormal non-scrambled signal. If ascrambled signal is used, the tray isoperated with jumper W6 in the Encodedposition, connected between pins 1 and2. The clamp circuit is set by adjustingdepth of modulation pot R152 for thecorrect depth of modulation as measuredat TP2.Depending on the input video level, thewaveform as measured at TP2 may notbe 1 Vpk-pk. If W7 on J4 is moved to theClamp-Off (Manual) position, betweenpins 1 and 2, the clamp level is adjustedby R41 and will not automatically beclamped to the set level. The output ofbuffer amplifier U3A drives the sync tipclamp circuit consisting of differentialamplifier U4A, FET Q7, and bufferamplifier U3B. U4A is biased by R124,R125, R184, R152, and R126 so that theclamped voltage level at peak of sync isapproximately -1.04 VDC as measured atTP2.Main Video Signal Path (Part 2 of 2)The clamped video from Q2 is connectedto white clipper circuit Q3. Q3 is adjustedwith R20 and set to prevent videotransients from overmodulating the videocarrier. The clamped video is connectedto sync clipper circuit Q4 (adjusted byR24); Q4 limits the sync to -40 IRE units.The corrected video connects to emitterfollower Q4 whose output is wired tounity gain amplifier U2A and provides alow-impedance, clamped video output atpin 1.Visual Modulator CircuitThe clamped video signal from U2A issplit. One part connects to a meteringcircuit, consisting of U20 and associatedcomponents, that produces a videooutput sample at J8-6 and connectsthrough the transmitter control board tothe front panel meter for monitoring. Theother clamped video path from U2A isthrough a sync-stretch circuit thatconsists of Q5 and Q6. The sync-stretchcircuit contains R48; R48 adjusts thesync stretch magnitude (amount) andR45 adjusts the cut-in. This sync-stretchadjustment should not be used to correctfor output sync problems, but it can beused for video input sync problems. Theoutput of the sync-stretch circuitconnects to pin 5, the I input of mixerZ1.The video signal is heterodyned in mixerZ1 with the visual IF CW signal (45.75MHz). The visual IF CW signal enters theboard at jack J15 and is connected to U9,where it is amplified and wired to pin 1,the L input of mixer Z1. The adjustablecapacitor C78 and resistor R53 are set upto add a small amount of incidentalcarrier phase modulation (ICPM)correction to the output of the mixerstage to compensate for any non-linearities generated by the mixer.The modulated 45.75-MHz RF output ofmixer Z1 is amplified by U5 and is fed todouble-sideband visual IF output jackJ18. The level of this output jack isadjusted by R70. J18 is the visual IFloop-through output jack that is normallyjumpered to J19 on the board. If theoptional visual IF loop-through kit ispurchased, the visual is connected out ofthe board to any external IF processortrays.After any external processing, themodulated visual IF, double-sidebandsignal re-enters the board through J19.The visual IF from J19 is amplified byU10 and U11 and routed through thevestigial sideband filter network,
10-kW UHF Transmitter with Chapter 4, CircuitFeedforward Drive Descriptions840A, Rev. 0 4-5consisting of T1, FL1, and T2, andproduces a vestigial sideband visual IFsignal output. The filtered vestigialsideband visual IF is amplified by U7 andconnected to a T-type attenuator. R62can be adjusted to set the visual IF gain;this is the amount of visual IF signal thatis coupled to amplifier IC U8. R63 andC30 are adjusted for the best VSBFfrequency response. The amplified IFsignal is fed to the input of the diplexercircuit that consists of R76, L13, and L12.A detected voltage sample of the visualIF is available at test point TP5.41.25-MHz Aural IF CircuitOn this board, the 41.25-MHz aural IF iscreated by mixing the modulated 4.5-MHz aural intercarrier signal, producedby the aural IF synthesizer board or fromthe composite 4.5-MHz filter board, withthe 45.75-MHz CW signal produced bythe 45.75-MHz IF carrier oven oscillatorboard. The modulated 4.5-MHz auralintercarrier signal enters the board at J14or J28 and is connected to IF relay K1.Jumper W3 on J7 determines whetherthe 4.5-MHz used by the board isinternally generated or from an externalsource. With jumper W3 connectedbetween pins 2 and 3, the 4.5 MHz fromthe aural IF synthesizer board or fromthe 4.5-MHz composite input isconnected to mixer Z2. If an external4.5-MHz signal is used, it enters theboard at J12 and is fed through gain potR88 to amplifier IC U13A. The amplified4.5 MHz is then connected to J7 and, ifjumper W3 is between pins 1 and 2, the4.5-MHz signal from the external sourceis connected to the mixer. Mixer Z2heterodynes the aural-modulated, 4.5-MHz signal with the 45.75-MHz CW signalto produce the modulated 41.25-MHzaural IF signal.The output of the mixer is fed to abandpass filter that is tuned to pass onlythe modulated 41.25-MHz aural IF signalthat is fed to jack J16, the 41.25-MHzloop-through out jack of the board.For normal operation, the 41.25-MHzsignal is jumpered by a coaxial cablefrom J16 to J17 on the board. If the(optional) aural IF loop-through kit ispurchased, the 41.25-MHz signal isconnected to the rear of the tray, towhich any processing trays can beconnected, and then back to jack J17 onthe board. The modulated 41.25-MHzaural IF signal from J17 is connectedthrough amplifier ICs U15 and U16. Theamplified output is connected to theattenuator-matching circuit that isadjusted by R85. R85 increases ordecreases the level of the 41.25 MHz thatsets the A/V ratio for the diplexer circuit.The diplexer circuit takes the modulated45.75-MHz visual IF and the modulatedaural IF and combines them to producethe 45.75-MHz + 41.25-MHz IF output.The combined 45.75-MHz + 41.25-MHzIF signal is amplified by U12 andconnected to combined IF output jackJ20 on the board. A sample of thecombined IF output is provided at J21 onthe board. If a NICAM input is used, itconnects to J36 on the board. The levelof the NICAM signal is set by R109 beforeit is fed to the diplexer circuit consistingof L28, L29, and R115. This circuitcombines the NICAM signal with the45.75-MHz visual IF + 41.25-MHz auralIF signal.Operational VoltagesThe +12 VDC needed to operate thetransmitter control board enters theboard at J23, pin 3, and is filtered byL26, L33, and C73 before it is fed to therest of the board.The -12 VDC needed to operate theboard enters the board at J23, pin 5, andis filtered by L27 and C74 before beingfed to the rest of the board.4.1.1.3 (A6) Delay Equalizer Board(1227-1204; Appendix B)The delay equalizer board provides adelay to the video signal, correction to
10-kW UHF Transmitter with Chapter 4, CircuitFeedforward Drive Descriptions840A, Rev. 0 4-6the frequency response, andamplification of the video signal.The video signal enters the board at J1-2and is connected to a pi-type, low-passfilter consisting of C16, L7, and C17. Thisfilter eliminates any unwanted higherfrequencies from entering the board. Theoutput of the filter is connected toamplifier stage U1; the gain is controlledby R29. The video output of the amplifierstage is wired to the first of four delay-equalizing circuits that shape the videosignal to the FCC specification for delayequalization or to the desired shapeneeded for the system. The board hasbeen factory-adjusted to this FCCspecification and should not bereadjusted without the properequipment.Resistors R7, R12, R17, and R22 adjustthe sharpness of the response curvewhile inductors L1, L2, L3, and L4 adjustthe position of the curve. With a delayequalizer test generator signal or a sinex/x video test pattern input, the resistorsand inductors can be adjusted, whilemonitoring a Tektronix VM700 testmeasurement set, until the desired FCCdelay equalization curve or system curveis attained. The delay-equalized videosignal is connected to J1-4, the videooutput of the board. A sample of thedelayed video signal is connected to J2on the board and can be used for testingpurposes.The ±12 VDC needed to operate theboard enters the board at J1. The +12VDC connects to J1-9, which is filtered byL5 and C11 before it is directed to therest of the board. The -12 VDC connectsto J1-6, which is filtered by L6 and C12before it is directed to the rest of theboard.4.1.1.4 (A7) IF Carrier Oven OscillatorBoard (1191-1404; Appendix B)The IF carrier oven oscillator boardgenerates the visual IF CW signal at45.75 MHz for NTSC system "M" usage.The +12 VDC is applied through jack J10to crystal oven HR1; HR1 is preset tooperate at 60° C. The oven enclosescrystal Y1 and stabilizes the crystaltemperature. The crystal is the primarydevice that determines the operatingfrequency and is the most sensitive interms of temperature stability.Crystal Y1 is operating in an oscillatorcircuit consisting of transistor Q1 and itsassociated components. Feedback isprovided through a capacitor-voltagedivider, consisting of C5 and C6, thatoperates the crystal in a common-baseamplifier configuration using Q1. Theoperating frequency of the oscillator canbe adjusted by variable capacitor C17.The oscillator circuit around Q1 has aseparately regulated voltage, 6.8 VDC,which is produced by a combination ofdropping resistor R4 and zener diodeVR1. The output of the oscillator at thecollector of Q1 is capacitively coupledthrough C8 to the base of Q2. The smallvalue of C8, 10 pF, keeps the oscillatorfrom being loaded down by Q2.Q2 is operated as a common-emitteramplifier stage whose bias is providedthrough R8 from the +12 VDC line. Theoutput of Q2, at its collector, is splitbetween two emitter-follower transistorstages, Q3 and Q4. The output of Q3 istaken from its emitter through R11 toestablish an approximately 50-ohmsource impedance through C11 to mainoutput jack J3. This 45.75-MHz signal isat a power level of approximately +5dBm. In most systems this output iseither directed to a visual modulatorboard or to some splitting and amplifyingarrangement that distributes the visual IFcarrier for other needs. The secondoutput from the collector of Q2 is fed tothe base of emitter-follower transistorQ4.
10-kW UHF Transmitter with Chapter 4, CircuitFeedforward Drive Descriptions840A, Rev. 0 4-7Q4 drives two different output circuits.One output is directed through voltagedivider R14 and R15 to jack J2 and is fedto a frequency counter. While monitoringJ2, the oscillator can be set exactly onthe operating frequency (45.75 MHz) byadjusting C17. The output at J2 is at apower level of approximately -2 dBm,which is sufficient to drive mostfrequency counters. The other output ofQ4 connects to U1, a prescaler chip thatdivides the signal by 15. The output ofU1 is applied to U2, a programmabledivider IC. U2 is programmed throughpins 11 to 20 to divide by 61. This resultsin a 50-kHz signal at pin 9 that isavailable as an output at J1. The outputof 50 kHz is generally used in systemswhere the visual IF carrier oven VCXO isused as the reference for a PLL circuit. Anexample of this is a PLL circuit used onthe aural IF synthesizer board, the auralVCO, or the precise frequency controltray. The 50-kHz CMOS output at jack J1is not capable of providing enough drivelevel for a long coaxial cable length; as aresult, when a long coaxial cable isneeded, the output at jack J5 is utilized.The push-pull transistor stage Q5 andQ6, along with emitter resistor R18,provides a large-load output capability atJ5.The stages U1, U2, Q5, and Q6 arepowered by +5.1 VDC. The +5.1 VDC isobtained by using the +12 VDC linevoltage and voltage-dropping resistorR16 and zener diode VR2.The +12 VDC power is applied to theboard through jack J4, pin 3, and isisolated from RF signals that may occurin the +12 VDC line through the use ofRF choke L2 and filter capacitor C10.4.1.1.5 (A8) ALC Board, NTSC (1265-1305; Appendix B)The automatic level control (ALC) boardprovides the ALC and amplitude linearitycorrection of the IF signal. The ALCadjusts the level of the IF signal throughthe board to control the output power ofthe transmitter.The visual + aural IF input (0 dBm)signal from the modulator enters theboard at modulator IF input jack J32. Ifthe (optional) receiver tray is present,the visual + aural IF input (0 dBm) fromthe receiver tray connects to receiver IFinput jack J1. The modulator IF inputconnects to relay K3 and the receiver IFinput connects to relay K4. The tworelays are controlled by the ModulatorSelect command that is connected to J30on the board. Modulator selectenable/disable jumper W11 on J29controls whether the Modulator Selectcommand at J30 controls the operation ofthe relays or not. With jumper W11 onJ29, pins 1 and 2, the Modulator Selectcommand at J30 controls the operation ofthe relays; with jumper W11 on J29, pins2 and 3, the modulator is selected all ofthe time.Modulator SelectedWith the modulator selected, J11-10 andJ11-28 on the rear of the UHF excitertray are connected together; this makesJ30 low and causes relays K3 and K4 tode-energize. When K4 is de-energized, itconnects the receiver IF input at J1, ifpresent, to 50 watts. When K3 is de-energized, it connects the modulator IFinput at J32 to the rest of the board;Modulator Enable LED DS5 will beilluminated.Receiver SelectedWith the receiver selected, which is J11-10 and J11-28 on the rear of the UHFexciter tray (connected to J30 on theboard) not connected together, relays K3and K4 are energized. When K4 isenergized, it connects the receiver IFinput at J1, if present, to the rest of theboard. When K3 is energized, it connectsto the modulator IF input at J32 to 50watts; Modulator Enable LED DS5 will beilluminated.
10-kW UHF Transmitter with Chapter 4, CircuitFeedforward Drive Descriptions840A, Rev. 0 4-8Main IF Signal Path (Part 1 of 3)The selected visual + aural IF input (0dBm) signal is split, with one half of thesignal entering a bandpass filter thatconsists of L3, L4, C4, L5, and L6. Thisbandpass filter can be tuned with C4 andis substantially broader than the IF signalbandwidth. It is used to slightly steer thefrequency response of the IF to make upfor any small discrepancies in thefrequency response in the stages thatprecede this point. The filter also servesthe additional function of rejectingunwanted frequencies that may occur ifthe tray cover is off and the tray is in ahigh RF environment (if this is the case,the transmitter will have to be servicedwith the tray cover off in spite of thepresence of other RF signals). Thefiltered IF signal is fed through a pi-typematching pad consisting of R2, R3, andR4 to the pin-diode attenuator circuitconsisting of CR1, CR2, and CR3.Input Level Detector CircuitThe other part of the split IF input isconnected through L2 and C44 to U7; U7is an IC amplifier that is the input to theinput level detector circuit. The amplifiedIF is fed to T4; T4 is a step-uptransformer that feeds diode detectorCR14. The positive-going detected signalis then low-pass filtered by C49, L18, andC50. This allows only the video withpositive sync to be applied throughemitter follower Q1. The signal is thenconnected to detector CR15 to produce apeak-sync voltage that is applied to op-amp U9A. There is a test point at TP3that provides a voltage reference checkof the input level. The detector servesthe dual function of providing a referencethat determines the input IF signal levelto the board and also serves as an inputthreshold detector.The input threshold detector prevents theautomatic level control from reducing theattenuation of the pin-diode attenuator tominimum (the maximum signal) if the IFinput to the board is removed. The ALC,video loss cutback, and the thresholddetector circuits will only operate whenjumper W3 on jack J6 is in the Autoposition, between pins 1 and 2. Withoutthe threshold detector, and with the pin-diode attenuator at minimum, when thesignal is restored it will overdrive thestages following this board.As part of the threshold detectoroperation, the minimum IF input level atTP3 is fed through detector CR15 to op-amp IC U9A, pin 2. The reference voltagefor the op-amp is determined by thevoltage divider that consists of R50 andR51 (off the +12 VDC line). When thedetected-input signal level at U9A, pin 2,falls below this reference threshold(approximately 10 dB below the normalinput level), the output of U9A at pin 1goes to the +12 VDC rail. This high isconnected to the base of Q2. At thispoint, Q2 is forward biased and creates acurrent path from the -12 VDC line andthrough red LED DS1, the input levelfault indicator, which becomes lit, resistorR54, and transistor Q2 to +12 VDC. Thehigh from U9A also connects throughdiode CR16 to U9B, pin 5, whose outputat pin 7 goes high. The high connectsthrough range adjust pot R74 to J20,which connects to the front panel-mounted power adjust pot. This highconnects to U10A, pin 2, and causes it togo low at output U10A, pin 1. The low isapplied through jumper W3 on J6 to thepin-diode attenuator circuit that cutsback the IF level and, therefore, theoutput power level, to 0. When the inputsignal level increases above the thresholdlevel, the output power will raise, as theinput level increases, until normal outputpower is reached.The video input level at TP3 is also fed toa sync-separator circuit, consisting of ICU8, CR17, Q3, and associatedcomponents, and then to a comparatorcircuit made up of U9C and U9D. Thereference voltage for the comparators isdetermined by a voltage dividerconsisting of R129, R64, R65, R66, andR130 (off the -12 VDC line). When the
10-kW UHF Transmitter with Chapter 4, CircuitFeedforward Drive Descriptions840A, Rev. 0 4-9input signal level to the detector at TP3falls below this reference threshold,which acts as a loss of sync detectorcircuit, the output of U9C and U9D goestowards the -12 VDC rail and is split, withone part biasing on transistor Q5. Acurrent path is then established from the+12 VDC line through Q5, the resistorsR69, R137, and the red LED DS3 (videoloss indicator), which becomes lit. WhenQ5 is on, it applies a high to the gates ofQ6 and Q7. This causes them to conductand apply video loss fault pull-downoutputs to J18, pins 5 and 2.The other low output of U9C and U9D isconnected through CR20 to jack J5.Jumper W2 on J5, in the Cutback Enableposition (between pins 2 and 3),connects the low to the base of theforward-biased Q4. If jumper W2 is inthe Disable position, between pins 1 and2, the auto cutback will not operate. WithQ4 biased on, a level determined by thesetting of cutback level pot R71, which isset at the factory to cut back the outputto approximately 25%, is applied to U9B,pin 5. The output of U9B at pin 7 goeslow and is applied through the poweradjust pot to U10A, pin 2, whose outputgoes low. This low is applied to the pin-diode attenuator to cut back the level ofthe output to approximately 25%.Pin-Diode Attenuator CircuitThe input IF signal is fed to a pin-diodeattenuator circuit that consists of CR1 toCR3. Each of the pin diodes contain awide intrinsic region; this makes thediodes function as voltage-variableresistors at this intermediate frequency.The value of the resistance is controlledby the DC bias supplied to the diode. Thepin diodes are configured in a pi-typeattenuator configuration where CR1 isthe first shunt element, CR3 is the serieselement, and CR2 is the second shuntelement. The control voltage, which canbe measured at TP1, originates eitherfrom the ALC circuit when jumper W3 onJ6 is in the ALC Auto position, betweenpins 1 and 2, or from pot R87 when thejumper is in the Manual Gain position.On the pin-diode attenuator circuit, acurrent path exists from J6 through R6and then through the diodes of the pinattenuator. Changing the amount ofcurrent through the diodes by forwardbiasing them changes the IF output levelof the board. There are two extremes ofattenuation ranges for the pin-diodeattenuators. In the minimum attenuationcase, the voltage, measured at TP1,approaches the +12 VDC line. There is acurrent path created through R6, throughseries diode CR3, and finally through R9to ground. This path forward biases CR3and causes it to act as a relatively low-value resistor. In addition, the largercurrent flow increases the voltage dropacross R9 that tends to turn off diodesCR1 and CR2 and causes them to act ashigh-value resistors. In this case, theshunt elements act as a high resistanceand the series element acts as a lowresistance to represent the minimum losscondition of the attenuator (maximumsignal output). The other extreme caseoccurs as the voltage at TP1 is reducedand goes towards ground or even slightlynegative. This tends to turn off (reversebias) diode CR3, the series element,causing it to act as a high-value resistor.An existing fixed current path from the+12 VDC line, and through R5, CR1,CR2, and R9, biases series element CR3off and shunt elements, diodes CR1 andCR2 on, causing them to act as relativelylow-value resistors. This represents themaximum attenuation case of the pinattenuator (minimum signal output). Bycontrolling the value of the voltageapplied to the pin diodes, the IF signallevel is maintained at the set level.Main IF Signal Path (Part 2 of 3)When the IF signal passes out of the pin-diode attenuator through C11, it isapplied to modular amplifier U1. Thisdevice includes within it the biasing andimpedance matching circuits that makesit operate as a wide-band IF amplifier.
10-kW UHF Transmitter with Chapter 4, CircuitFeedforward Drive Descriptions840A, Rev. 0 4-10The output of U1 is available, as asample of the pre-correction IF fortroubleshooting purposes and systemsetup, at jack J2. The IF signal is thenconnected to the linearity correctorportion of the board.Linearity Corrector CircuitsThe linearity corrector circuits use threestages of correction to correct for anyamplitude non-linearities of the IF signal.Each stage has a variable thresholdcontrol adjustment, R34, R37, or R40,and a variable magnitude controladjustment, R13, R18, or R23. Thethreshold control determines the point atwhich the gain is changed and themagnitude control determines theamount of gain change that occurs oncethe breakpoint is reached. Two referencevoltages are needed for the operation ofthe corrector circuits. Zener diode VR1,with R33 and R135, provides a +6.8 VDCreference and the diodes CR11 and CR12provide a .9 VDC reference thattemperature compensates for the twodiodes in each corrector stage.For the linearity correctors to operate, anIF signal is applied to transformer T1,which doubles the voltage swing bymeans of a 1:4 impedancetransformation. Resistors R14, R15, andR16 form an L-pad that lowers the levelof the signal. The amount that the levelis lowered is adjusted by adding more orless resistance, using R13, in parallelwith the L-pad resistors. R13 is only inparallel when the signal reaches a levellarge enough to turn on the diodes CR4and CR5. When the diodes turn on,current flows through R13, putting it inparallel with the L-pad.When R13 is put in parallel with theresistors, the attenuation through theL-pad is lowered, causing signal stretch(the amount determined by theadjustment of R13). The signal is nextapplied to amplifier U2 to compensate forthe loss through the L-pad. Thebreakpoint, or cut-in point, for the firstcorrector is set by controlling where CR4and CR5 turn on. This is accomplished byadjusting cut-in resistor R34; R34 formsa voltage-divider network from +6.8 VDCto ground. The voltage at the wiper armof R34 is buffered by unity-gain amplifierU5D. This reference voltage is thenapplied to R35, R36, and C39 throughL12 to the CR4 diode. C39 keeps thereference from sagging during thevertical interval. The .9 VDC referencecreated by CR11 and CR12 is applied tounity-gain amplifier U5B. The referencevoltage is then connected to diode CR5through choke L11. The two chokes L11and L12 form a high impedance for RFthat serves to isolate the op-amp ICsfrom the IF.After the signal is amplified by U2, it isapplied to the second corrector stagethrough T2. This corrector and the thirdcorrector operate in the same fashion asthe first. All three corrector stages areindependent and do not interact witheach other.The correctors can be disabled by movingjumper W1 on J4 to the Disable position,between pins 2 and 3; this moves all ofthe breakpoints past the tip of sync sothat they will have no affect. The IFsignal exits the board at IF output jack J3after passing through the three correctorstages and is normally connected to anexternal IF phase corrector board.Main IF Signal Path (Part 3 of 3)After the IF signal passes through theexternal IF phase corrector board, itreturns to the ALC board at IF input jackJ7. The IF then passes through abandpass filter consisting of L20, C97,C62, L21, C63, L22, L23, C64, and C99.This bandpass filter is identical in bothform and function to the one described inSection 4.3 of this chapter. In this case,the filter is intended to make up for smallerrors in frequency response that areincurred by the signal while beingprocessed through the linearity andincidental phase correction circuits.
10-kW UHF Transmitter with Chapter 4, CircuitFeedforward Drive Descriptions840A, Rev. 0 4-11Following the bandpass filter, the signalis split using L24, L25, and R89. Thesignal passing through L24 is the main IFpath through the board. A sample of thecorrected IF signal is split off andconnected to J10, the IF sample jack.The IF connects to jacks J27 and J28.These jacks control whether a 6-dB padis included in the circuit by thepositioning of jumpers W9 and W10. The6-dB pad-in is when jumpers W9 andW10 are connected between pins 2 and 3on J27 and J28. The 6-dB pad-out iswhen jumpers W9 and W10 areconnected between pins 1 and 2 on J27and J28. Normally, the pad is out. The IFsignal is then applied to a two-stage,frequency-response corrector circuit thatis adjusted as needed.Variable resistors R103 and R106 adjustthe depth and gain of the notches andvariable caps C71 and C72 adjust thefrequency position of the notches. The IFsignal is amplified by U13 and U14 beforeit is connected to J12, the IF output jackof the board. R99 is an output leveladjustment that is set to provideapproximately 0 dBm of IF output at J12.A sample of the IF is fed to J11 toprovide an IF sample point that can bemonitored without breaking the signalpath and gives an indication of the IFsignal after the linearity and thefrequency-response correction takesplace.ALC CircuitThe other path of the corrected IF signalis used in the ALC circuit. The IF is wiredout of the splitter through L25 andconnects to op-amp U12. The output ofU12 is wired to jacks J8 and J9 on whichjumpers W4 and W8 control the normalor encoded operation of the ALC circuitry.For normal operation, jumper W4 on J8 isbetween pins 1 and 2 and jumper W8 onJ9 is between pins 1 and 2. The IF signalis applied to transformer T5; T5 doublesthe voltage swing by means of a 1:4impedance transformation before it isconnected to the ALC detector circuit onthe board and amplified by U10B.For normal operation, jumper W7 on J26is between pins 1 and 2 and jumper W5on J21 is between pins 1 and 2. Thedetected ALC voltage is wired to U10A,pin 2, where it is summed with the frontpanel power control setting. The outputpower adjustment for the transmitter isachieved, if the (optional) remote powerraise/lower kit (1227-1039) is purchased,by R75, a motor-driven pot controlled byswitch S1 on the board, or screwdriveradjust pot R1 on the front panel of theUHF exciter tray. An external powerraise/lower switch can be used byconnecting it to jack J10, at J10-11power raise, J10-13 power raise/lowerreturn, and J10-12 power lower, on therear of the UHF exciter tray. S1, or theremote switch, controls relays K1 and K2,which control motor M1 that movesvariable resistor R75. If the (optional)remote power raise/lower kit is notpurchased, the ALC voltage is controlledonly by screwdriver adjust pot R1 on thefront panel of the UHF exciter tray. TheALC voltage is set for .8 VDC at TP4 witha 0 dBm output at J12 of the board. Asample of the ALC at J19, pin 2, is wiredto the transmitter control board where itis used on the front panel meter and inthe AGC circuits.This ALC voltage, and the DC levelcorresponding to the IF level after signalcorrection, are fed to U10A, pin 2, whoseoutput at pin 1 connects to the ALC pin-diode attenuator circuit. If there is a lossof gain somewhere in an IF circuit, theoutput power of the transmitter will drop.The ALC circuit senses this drop at U10Aand automatically lowers the loss of thepin-diode attenuator circuit tocompensate by increasing the gain.The ALC action starts with the ALCdetector level that is monitored at TP4.The detector output at TP4 is nominally+.8 VDC and is applied through resistorR77 to a summing point at op-ampU10A, pin 2. The current available from
10-kW UHF Transmitter with Chapter 4, CircuitFeedforward Drive Descriptions840A, Rev. 0 4-12the ALC detector is offset, orcomplemented, by current taken awayfrom the summing junction. In normaloperation, U10A, pin 2, is at 0 VDC whenthe loop is satisfied. If the recovered orpeak-detected IF signal at IF input jackJ7 of this board should drop in level,which normally means that the outputpower is decreasing, the null conditionwould no longer occur at U10A, pin 2.When the level drops, the output ofU10A, pin 1, will go more positive. Ifjumper W3 on J6 is in the Automaticposition, it will cause the ALC pin-diodeattenuators CR1, CR2, and CR3 to haveless attenuation and increase the IFlevel; this will act to compensate for thedecrease in level. If the ALC cannotincrease the input level enough to satisfythe ALC loop, due to there not beingenough range, an ALC fault will occur.The fault is generated because U10D, pin12, increases above the trip point set byR84 and R83 until it conducts. Thismakes U10D, pin 14, high and causes thered ALC Fault LED DS2 to light.Scrambled Operation with EncodingFor encoded, scrambled operation,jumper W4 on J8 must be connectedbetween pins 2 and 3, jumper W8 on J9must be between pins 3 and 2, jumperW7 on J26 must be between pins 2 and3, and jumper W5 on J21 must bebetween pins 2 and 3. The IF isconnected through W4 on J8 to the syncregeneration circuits.If this board is operated with scrambling,using suppressed sync, the ALC circuitoperates differently than described abovebecause there is no peak of sync presenton the IF input. A timing pulse from thescrambling encoder connects to theboard at J24. This timing pulse isconverted to sync pulses by U17A andU17B, which control the operation of Q8.The sync amplitude is controlled by R149and is then applied to U15A, where it isadded to the detected IF signal toproduce a peak of sync level. The outputof U15A is peak detected by CR26 andfed to U15B. If necessary, intercarriernotch L39 can be placed in the circuit byplacing W6 on J22. The intercarrier notchis adjusted to filter any aural and 4.5-MHz intercarrier frequencies. The peak ofsync signal is fed through R162, the ALCcalibration control, to amplifier U15C. Theamplified peak of sync output isconnected through J21, pins 2 and 3, toU10A, where it is used as the referencefor the ALC circuit and the AGC referenceto the transmitter control board. VoltageTP4 should be the same in either thenormal or the encoded video mode.Monitor J9, pins 3 and 4, with a spectrumanalyzer, check that the board is in theAGC mode, and tune C103 to notch-outthe aural IF carrier.Fault CommandThe ALC board also has circuitry for anexternal mute fault input at J19, pin 6.This is a Mute command and, in mostsystems, it is involved in the protectionof the circuits of high-gain outputamplifier devices. The Mute command isintended to protect the amplifier devicesagainst VSWR faults. In this case, theaction should occur faster than justpulling the ALC reference down. Twodifferent mechanisms are employed: oneis a very fast-acting circuit to increasethe attenuation of the pin-diodeattenuator, CR3, CR1, and CR2, and thesecond is the reference voltage beingpulled away from the ALC amplifierdevice. An external Mute is a pull-downapplied to J19, pin 6, to provide a currentpath from the +12 VDC line through R78and R139, the LED DS4 (Mute indicator),and the LED section of opto-isolator U11.These actions turn on the transistorsection of U11 that applies -12 VDCthrough CR21 to U10A, pin 3, and pullsdown the reference voltage. This is afairly slow action that is kept at this paceby the low-pass filter function of R81 andC61. When the transistor section of U11is on, -12 VDC is also connected throughCR22 to the pin-diode attenuator circuit.This establishes a very fast muting
10-kW UHF Transmitter with Chapter 4, CircuitFeedforward Drive Descriptions840A, Rev. 0 4-13action, by reverse biasing CR3, in theevent of an external VSWR fault.±12 VDC Needed to Operate the BoardThe ±12 VDC connects to the board atJ14. The +12 VDC connects to J14-3 andis filtered by L30, L41, and C80 before itis applied to the rest of the board. The-12 VDC connects to J14-5 and is filteredby L31 and C81 before it is applied to therest of the board.The +12 VDC also connects to U16, a 5-VDC regulator IC, that produces the +5VDC needed to operate timing IC U17.4.1.1.6 (A9) IF Phase Corrector Board(1227-1250; Appendix B)The IF phase corrector board hasadjustments that pre-correct for any IFphase modulation distortion that mayoccur in output amplifier devices such asKlystron power tubes and solid-stateamplifiers. Two separate, adjustable IFpaths are on the board: a quadrature IFpath and an in-phase IF path. Thequadrature IF is 90° out of phase andmuch larger in amplitude than the in-phase IF. When they are combined in Z1,it provides the required adjustable phasecorrection to the IF signal.The IF input signal enters at J1 and is ACcoupled to U1. U1 amplifies the IF beforeit is connected to Z1, a splitter thatcreates two equal IF outputs: IF output 1is connected to J2 and IF output 2 isconnected to J3. The IF output 1 at J2 isjumpered through coaxial cable W4 tojack J6, the quadrature input, on theboard. The IF output 2 at J3 is jumperedthrough coaxial cable W5 to jack J7, thein-phase input, on the board.Phase Corrector CircuitThe phase corrector circuit corrects forany amplitude nonlinearities of the IFsignal. It is designed to work at IF andhas three stages of correction. Eachstage has a variable threshold andmagnitude control. The threshold controldetermines the point at which the gain ischanged and the magnitude controldetermines the gain change once thebreakpoint is reached. The second stagehas a jumper that determines thedirection of correction, so that the gaincan increased either above or below thethreshold, and either black or whitestretch can be achieved.In the phase corrector circuit, the IFsignal from J6 is applied to transformerT1; T1 doubles the voltage swing using a1:4 impedance transformation. ResistorsR8, R61, R9, and R48 form an L-pad thatattenuates the signal. This attenuation isadjusted by adding R7, a variableresistor, in parallel with the L-pad. R7 isonly in parallel when the signal reaches alevel large enough to bias on CR1 andCR2 and allow current to flow throughR7. When R7 is put in parallel with the L-pad, the attenuation through the L-pad islowered, causing black stretch.Two reference voltages are utilized in thecorrector stages and both are derivedfrom the +12 VDC line. Zener diode VR1,with R46 as a dropping resistor, provides+6.8 VDC from the +12 VDC line. DiodesCR11 and CR12 provide a .9 VDCreference to temperature compensatethe corrector circuits from the effects ofthe two diodes in each corrector stage.The threshold for the first corrector stageis set by controlling where CR1 and CR2turn on. This is accomplished byadjusting R3 to form a voltage dividerfrom +6.8 VDC to ground. The voltage atthe wiper of R3 is buffered by U9C, aunity-gain amplifier, and applied to CR1.The .9 VDC reference is connected toU9D, a unity-gain amplifier, whoseoutput is wired to CR2. These tworeferences are connected to diodes CR1and CR2 through chokes L2 and L3. Thetwo chokes form a high impedance for RFto isolate the op-amps from the RF. Theadjusted signal is next applied toamplifier U2 to compensate for the lossthrough the L-pad. U2 is powered
10-kW UHF Transmitter with Chapter 4, CircuitFeedforward Drive Descriptions840A, Rev. 0 4-14through L4 and R10 from the +12 VDCline. After the signal is amplified by U2, itis applied to the second corrector stagethrough T2 and then to a third correctorstage through T3. The other twocorrector stages operate in the samemanner as the first; they areindependent and do not interact witheach other.When jumper W1 on J8 is connectedfrom center to ground, R15 is put inseries with ground. In this configuration,black stretch (white compression) isapplied to the IF signal by controlling theattenuation through the path. When W1is connected from the center pin to theend that connects to T2, R15 is put inparallel with the L-pad. In thisconfiguration, black compression (whitestretch) is applied to the IF signal bycontrolling the attenuation through thepath.The phase correctors can be bypassed bymoving jumper W2 on J9 to the Disableposition. This action will move all of thethreshold points past sync tip so thatthey will have no effect. R68 can beadjusted and set for the correction rangethat is needed. TP2 is a test point thatgives the operator a place to measurethe level of the quadrature IF signal thatis connected to pin 6 on combiner Z2.Amplitude Corrector CircuitThe amplitude corrector circuit uses onestage of correction to correct for anyamplitude nonlinearities of the IF signal.The stage has a variable thresholdcontrol, R31, and a variable magnitudecontrol, R35. The threshold controldetermines the point at which the gain ischanged and the magnitude controldetermines the amount of gain changeonce the breakpoint is reached.Two reference voltages are needed forthe operation of the corrector circuit.Zener diode VR1 with R46 provides +6.8VDC and the diodes CR11 and CR12provide a .9 VDC reference voltage totemperature compensate for the twodiodes in the corrector stage. In theamplitude corrector circuit, the IF signalfrom J7 is applied to transformer T4 todouble the voltage swing by means of a1:4 impedance transformation. ResistorsR36, R55, R56, and R37 form an L-padthat lowers the level of the signal. Theamount that the level is lowered isadjusted by adding more, or less,resistance, using R35 in parallel with theL-pad resistors. R35 is only in parallelwhen the signal reaches a level largeenough to turn on diodes CR8 and CR9.When the diodes turn on, current flowsthrough R35 and puts it in parallel withthe L-pad. When R35 is in parallel withthe resistors, the attenuation through theL-pad is lowered, causing signal stretch(the amount of stretch determined by theadjustment of R35).The signal is next applied to amplifier U5to compensate for the loss in levelthrough the L-pad. The breakpoint, orcut-in point, for the corrector stage is setby controlling where CR8 and CR9 turnon. This is achieved by adjusting cut-inresistor R31 to form a voltage dividerfrom +6.8 VDC to ground. The voltage atthe wiper arm of R31 is buffered byunity-gain amplifier U8B. This voltage isthen applied to R34 through L11 to theCR9 diode. The .9 VDC reference createdby CR11 and CR12 is applied to unity-gain amplifier U8A. C36 keeps thereference from sagging during thevertical interval. The reference voltage isthen connected to diode CR8 throughchoke L12. The two chokes L11 and L12form a high impedance for RF to isolatethe op-amp ICs from the IF.After the signal is amplified by U5, it isapplied to a second stage through T5.The transformer doubles the voltageswing by means of a 1:4 impedancetransformation. Resistors R39, R57, R58,and R40 form an L-pad that lowers thelevel of the signal. The signal is appliedto amplifier U6 to compensate for theloss in level through the L-pad. After thesignal is amplified by U6, it is applied to a
10-kW UHF Transmitter with Chapter 4, CircuitFeedforward Drive Descriptions840A, Rev. 0 4-15third stage through T6. The transformerdoubles the voltage swing by means of a1:4 impedance transformation. ResistorsR42, R59, R60, and R43 form an L-pad tolower the level of the signal. The signal isapplied to amplifier U7 to compensate forthe loss in level through the L-pad. TP1 isa test point that gives the operator aplace to measure the level of the in-phase IF signal that is connected tomixer stage Z2. The amplitude correctorcan be disabled by moving jumper W3 onJ10 to the Disable position; this will movethe breakpoint past sync tip and will haveno effect on the signal.Output CircuitThe phase-corrected signal from pin 1 oncombiner Z2 exits the board at IF outputjack J4 after passing through a matchingnetwork consisting of six resistors.4.1.1.7 (A11) UHF Upconverter Board(1265-1310; Appendix B)The UHF upconverter board providesupconversion for the transmitter bymixing the IF and local oscillator (LO)signals in mixer Z1 to produce thedesired RF frequency output. The RFoutput is connected through J3 to anexternal filter and applied back to theboard at J4 where the gain is set by R10.The RF is amplified and connected to theRF output jack of the board at J5.The IF signal (0 dBm) enters the board atJ1, an SMA connector, and is appliedthrough a filter circuit (L10 and C25 toC28) to a matching pad that consists ofR1, R2, and R3. The matching padpresents a relatively good sourceimpedance to the I input of mixer Z1,which is made up of pins 3 and 4. The LOsignal (+13 dBm) from the x8 multiplierconnects to the board at jack J2, an SMAconnector, through a UHF channel filterand is connected directly to pin 8, the Linput of the mixer. The frequency of theLO is the sum of the IF frequency abovethe desired visual carrier. For instance, insystem M, the IF visual frequency is at45.75 MHz and the relative location ofthe aural would be 4.5 MHz lower (41.25MHz). By choosing the local oscillator tobe 45.75 MHz above the visual carrier, aconversion in frequency occurs with theselection of the difference product. Thedifference product, which is the localoscillator minus the IF, will be at thechosen visual carrier frequency output.There will also be other signals present atRF output connector J3 at a lower level.These are the sum conversion product,the LO, and the IF frequencies. Usually,the output product that is selected by thetuning of the external filter is thedifference product (LO minus the 45.75-MHz IF). The difference product has thesidebands flipped so that the visualcarrier is lower in frequency than theaural carrier.If a bad reactive load is connected to themixer, the LO signal fed through it can beincreased because the mixer no longerserves as a double-balanced mixer. Themixer suppresses signals that may leakfrom one input port to any of the otherports. This activity is enhanced by havinginputs and outputs of the mixer at a 50Ωimpedance.The reactive filter, which is externallyconnected to J3 of the board, does notappear as a good 50Ω-load at allfrequencies. The pad, in the output lineof the board, consists of R5, R4, R6, andR7. It buffers the bad effects of thereactive filter load and makes it appearas a 50Ω impedance. The RF signal isamplified by U1, a modular amplifier thatcontains biasing and impedance matchingnetworks that make U1 act as awideband RF amplifier device. Thisamplifier, in a 50Ω system, hasapproximately 12 dB of gain. U1 ispowered from the +12 VDC line throughRF decoupling components R27, R28,C30, R8, and L1. The inductor L1 is abroadband RF choke, resonance freethrough the UHF band. The amplified RFconnects to SMA RF output jack J3 whichis cabled to the external filter.
10-kW UHF Transmitter with Chapter 4, CircuitFeedforward Drive Descriptions840A, Rev. 0 4-16The RF input signal from the externalfilter re-enters the board at J4 (-11 to -14 dBm) and is capacitively coupled tothe pin-diode attenuator circuit thatconsists of CR1, CR2, and CR5. The pin-diode attenuator acts as a voltage-variable attenuator in which each pindiode functions as a voltage-variableresistor and depends on the DC biassupplied to the diode for the resistancevalue. The pin diodes, because of a large,intrinsic region, cannot rectify signals atthis RF frequency; they act as a linearvoltage-variable resistor. The pin diodesare configured in a shunt configurationwhere CR1 is the first shunt element,CR2 is the second shunt element, andCR5 is the series element. In most cases,the manual gain AGC, W1 on J10between pins 1 and 2, is used. Thecontrol voltage from manual gain pot R10sets up a current path through R11 andthe diodes in the pin attenuator.The level-controlled RF signal from thepin-diode attenuator circuit is amplifiedby wideband-hybrid amplifier IC U2; U2is configured in the same way as U1. TheRF signal is buffered by Q1 and applied tothe push-pull class A amplifier circuit thatconsists of Q2 and Q3. At the input to thetransistors, the RF is converted to abalanced dual feed by a balun L4 madefrom a short length of UT-141 coaxialcable. Capacitors C12 and C13 provideDC blocking for the input signal to theamplifier devices. The RF outputs at thecollectors of the transistors are appliedthrough C19 and C20, which provide DCblocking for the output signals. The RFsignals connect to L7, which consists ofUT-141 coaxial cable, that combines theRF back to a single RF output at a 50Ωimpedance to L8; L8 provides a sampleof the RF.The main path through L10 is to J5, theRF output jack of the board (+10 to +20dBm). The sample of the RF connects toa splitter that provides a sample output(0 dBm) at J6 of the board. The otheroutput of the splitter connects to a peak-detector circuit, consisting of CR3 andU3, that provides a DC level at J7representing the RF output of the UHFexciter to the front panel meter. R29 setsup the calibration of the front panelmeter for 100% in the UHF exciterposition when the output power of theexciter is at +17 dBm peak visual.The upconverter board is powered by±12 VDC that is produced by an externalpower supply. +12 VDC enters throughJ8, pin 3, and is filtered and isolated byRF choke L9 and shunt capacitors C24and C33. This circuit isolates the RFsignals of the board from those of otherdevices connected to the same +12 VDCline external to the upconverter board.The +12 VDC is then applied to the restof the board.4.1.1.8 (A15) x8 Multiplier Board (1227-1002; Appendix B)The x8 multiplier board multiplies thefrequency of an RF input signal by afactor of eight. The board is made up ofthree identical x2 broadband frequencydoublers.The input signal (+5 dBm) at thefundamental frequency enters throughSMA jack J1 and is fed through a 3-dBmatching pad, consisting of R1, R2, andR3, to amplifier IC U1. The output of theamplifier stage is directed through abandpass filter, consisting of L2 and C4,which is tuned to the fundamentalfrequency (87 to 114 MHz). The voltagemeasured at TP1 is typically +.6 VDC.The first doubler stage consists of Z1with bandpass filter L3 and C6 tuned tothe second harmonic (174 to 228 MHz).The harmonic is amplified by U2 andagain bandpass filtered at the secondharmonic frequency by C10 and L5 (174to 228 MHz). The voltage measured atTP2 is typically +1.2 VDC.The next doubler stage consists of Z2with bandpass filter C12 and L6 tuned tothe fourth harmonic of the fundamentalfrequency (348 to 456 MHz). The fourth
10-kW UHF Transmitter with Chapter 4, CircuitFeedforward Drive Descriptions840A, Rev. 0 4-17harmonic is then amplified by U3 and fedthrough another bandpass filter tuned tothe fourth harmonic consisting of L11 andC18 (348 to 456 MHz). The voltagemeasured at TP3 is typically +2.0 VDC.The final doubler stage consists of Z3with bandpass filter C20 and L12 tunedto the eighth harmonic of thefundamental frequency (696 to 912MHz). The signal is amplified by U4, U5,and U6 to a typical value of from +2 to+4 VDC as measured at test point TP4.The amplified eighth harmonic is then fedto the SMA output jack of the board atJ2.The typical LO signal output level is +15dBm nominal. The detected sample ofthe output of the x8 multiplier board atTP4 is also fed to the base of Q1, whichforward biases it and lights the greenLED DS1 on the board to indicate thatthe LO signal is present.The +12 VDC for the board entersthrough jack J3-3 and is filtered by L7and C16 before being distributed to thecircuits on the board.4.1.1.9 (A17) Transmitter Control Board(1293-1221; Appendix B)The transmitter control board (1293-1221) provides the system controlfunctions and the operational LEDindications that can be viewed on thefront panel of the transmitter. The maincontrol functions of the board are forOperate/Standby and Auto/Manualselection. When the transmitter isswitched to Operate, the board suppliesthe enables to any external amplifiertrays. The board also performs theautomatic switching of the transmitter toStandby upon the loss of the video inputwhen the transmitter is in Auto. Theboard contains a VSWR cutback circuitwhich, if the VSWR of the transmitterincreases above 12.5%, will cut back theoutput level of the transmitter, asneeded, to maintain a maximum of12.5% VSWR. An interlock (low) must bepresent at J8-24 for the transmitter to beswitched to Operate and, when theinterlock is present, the green InterlockLED DS5 will be lit.Operate/Standby Switch S1K1 is a magnetic latching relay thatcontrols the switching of the transmitterfrom Operate to Standby. When theOperate/Standby switch S1 on the frontpanel of the tray is moved to Operate,one coil of relay K1 energizes and causesthe contacts to close and apply a low toU4B-9. If the transmitter interlock ispresent, and there is no overtemperaturefault, lows will also be applied to U4B-10,U4B-11, and U4B-12. With all the inputsto U4B low, the output at U4B-13 willalso be low. The low biases off Q1, whichturns off the amber Standby LED DS1 onthe front panel, and applies a high to Q2.This action turns on and lights the greenOperate LED DS2 on the front panel.When Q2 is biased on, it connects a lowto Q12 and biases it off. This allows theALC to be applied to J1, which connectsto any external amplifier trays. The lowfrom U4B-13 is also applied to Q4 andQ24, which are biased off, and removesthe disables from J1-4 and J18-1. Thelow from U4B-13 connects to Q10, whichis biased on, and to Q6, Q7, Q8, and Q9,which are also biased on. In addition, itapplies -12 VDC enables at J8-2, J8-3,J8-4, and J8-5 that connect to anyexternal amplifier trays. The high appliedto Q2 is connected to Q5 and Q26, whichare biased on, and applies a low enableto J1-3, which can connect to a remoteoperate indicator. The transmitter is nowin the Operate mode.When the Operate/Standby switch S1 ismoved to Standby, the other coil of relayK1 energizes; this causes the contacts toopen and a high, +12 VDC, to be appliedto U4B-9. The high at the input causesthe output at U4B-13 to go high. Thehigh biases on Q1 and applies a low tothe amber Standby LED DS1 on the frontpanel. The indicator turns on and applies
10-kW UHF Transmitter with Chapter 4, CircuitFeedforward Drive Descriptions840A, Rev. 0 4-18a low to Q2, which turns off andextinguishes the green Operate LED DS2.In addition, Q12 is biased on; it connectsto U2C, whose output goes low and pullsthe ALC voltages at J1 low, lowering thegain of the external amplifier trays. Thehigh from U4B-13 is also applied to Q4and Q24, which are biased on and applydisables at J1-4 and J18-1. The high fromU4B-13 connects to Q10, which is biasedoff. Q10 Off removes the high from Q6,Q7, Q8, and Q9, which are biased off,and removes the -12 VDC enables at J8-2, J8-3, J8-4, and J8-5 that connect tothe external amplifier trays. The lowapplied to Q2 is connected to Q5 andQ26, which are biased off, and removesthe remote enable at J1-3. Thetransmitter is now in the Standby mode.Automatic/Manual Switch S2K2 is a magnetic latching relay thatswitches the operation of the transmitterto Automatic or Manual by usingAuto/Manual switch S2 on the front panelof the tray.When the S2 switch is set to the Autoposition, the operation of the transmitteris controlled by the fault circuits and willstay in Operate even if Operate/Standbyswitch S1 is moved to Standby. With theS2 switch in Auto, a low is applied to onecoil in the relay; this energizes and closesthe contacts. The closed contacts apply alow to the green Automatic LED DS3,causing it to illuminate. The low from therelay connects to U5A, pin 2; U5D, pin13; Q21; and Q23. Q21 and Q23 arebiased off, which causes their outputs togo high. The high from Q21 connects tothe amber Manual LED DS4 on the frontpanel, biasing it off, and to Q22, biasingit on. The drain of Q22 goes low and isapplied to J8-7, which will enable anyremote auto indicator connected to it.The low to Q23 biases it off and removesthe enable to any remote manualindicator connected to J8-6.When the S2 switch is set to the Manualposition, the operation of the transmitteris no longer controlled by the faultcircuits and is controlled byOperate/Standby switch S1. With the S2switch in Manual, a low is applied to theother coil in the relay to energize andopen the contacts. The open contactsremove the low from the greenAutomatic LED DS3 on the front paneland cause it to not light. The highconnects to U5A, pin 2; U5D, pin 13;Q21; and Q23. Q21 and Q23 are biasedon, which causes their outputs to go low.The low from Q21 connects to the amberManual LED DS4 on the front panel,biasing it on, and to Q22, biasing it off.The drain of Q22 goes high and the highis applied to J8-7, which will disable anyremote auto indicator connected to it.Q23 is biased on, which applies a lowenable to any remote manual indicatorconnected to J8-6.Automatic Turning On and Off of theTransmitterThe transmitter control board also allowsthe transmitter to be turned on and offby the presence of video when thetransmitter is in Auto. When a video faultoccurs due to the loss of video, J7-5 goeslow. The low is applied through W1 onJ10 to Q16, which is biased off, and tothe red Video Loss Fault LED DS9 on thefront panel, which will light. The drain ofQ16 goes high and connects to U5B, pin5, causing the output at pin 4 to go low.The low connects to Q18, which is biasedoff, and causes the drain of Q18 to gohigh. The high connects to U3D, pin 12,whose output at pin 14 goes high. Thehigh connects to U5C, pins 8 and 9,which causes its output at pin 10 to golow, and to U5A, pin 1, which causes itsoutput at pin 3 to go low. With switch S2set to Automatic, a low is applied to U5A,pin 2, and to U5D, pin 13. When U5A, pin1, is high and U5A, pin 2, is low, itcauses the output at pin 3 to go low.When U5D, pin 12, is low and U5D, pin13, is low, it causes the output to gohigh. When U5A, pin 3, is low, it biasesoff Q20, which removes any pulldown tothe Operate switch. A high at U5D, pin
10-kW UHF Transmitter with Chapter 4, CircuitFeedforward Drive Descriptions840A, Rev. 0 4-1911, biases on Q19, which applies a lowenable to the Standby switch; this placesthe transmitter in the Standby mode.When the video is returned, J7-5 goeshigh. The high is applied to Q16, which isbiased on, and to the red Video Fault LEDDS9, which is extinguished. The output ofQ16 goes low and connects to U5B, pin5. If there is no receiver ALC fault, U5B,pin 6, is also low, which causes theoutput at pin 4 to go high. The highconnects to Q18, which is biased on,causing the drain of Q18 to go low. Thelow connects to U3D, pin 12, whoseoutput at pin 14 goes low. The lowconnects to U5C, pins 8 and 9, whichcauses its output at pin 10 to go high,and to U5A, pin 1. With Auto/Manualswitch S2 in Auto, a low is applied toU5A, pin 2, and to U5D, pin 13. WithU5A, pins 1 and 2, low, its output at pin3 goes high. With pin 12 of U5D high,the output of U5D at pin 11 goes low.With U5A, pin 3, high, it biases on Q20,which applies a pulldown enable to theOperate switch. A low at U5D, pin 11,biases off Q19, which removes anypulldown to the Standby switch. Thetransmitter is switched to Operate.FaultsThere are four possible faults that mayoccur in the transmitter and are appliedto the transmitter control board: videoloss fault, VSWR cutback fault,overtemperature fault, and ALC fault.There will be no faults to the boardduring normal transmitter operations.The receiver ALC fault circuit will onlyfunction if a receiver tray is part of thesystem.Video Loss Fault. If a video loss occurs,the transmitter, while in Auto, will go toStandby after a few seconds, until thevideo is returned; at that point it willimmediately revert to Operate. A videoloss fault applies a low from the ALCboard to the video fault input at J7-5 onthe board.With jumper W1 in place on J10, thevideo fault is connected to the red VideoLoss Fault LED DS9 and to Q16. The LEDDS9 on the front panel will light and Q16will be biased off, causing its drain to gohigh. The high is wired to U5B, pin 5,whose output at U5B, pin 4, goes low.The low is wired to Q18, which is biasedoff; this causes the drain to go high. Thehigh is connected to U3D, pin 12, whichcauses its output at U3D, pin 14, to gohigh. The high connects to U5A, pin 1,and, if the transmitter is in Auto, pin 2 ofU5A is low. With pin 1 high and pin 2low, the output of U5A goes low andreverse biases Q20, shutting it off. Thehigh at U5C, pins 8 and 9, causes itsoutput at pin 10 to go low. This low isconnected to U5D, pin 12, and, if thetransmitter is in Auto, pin 13 of U5D isalso low. The lows on pins 12 and 13cause the output to go high, whichforward biases Q19. The drain of Q19goes low and connects the coil in relayK1, causing it to switch to Standby.When the video returns, the video lossfault is removed from the video faultinput at J7-5. With jumper W1 in placeon J10, the base of Q16 goes high. Thered Video Loss Fault LED DS9 on thefront panel will go out. Q16 is biased on,causing its drain to go low. The low iswired to U5B, pin 5, and U5B, pin 6, willbe low if no ALC fault occurs. The twolows at the inputs make the output atU5B, pin 4, go high. The high is wired toQ18, which is biased on and causes thedrain to go low. The low is connected toU3D, pin 12, which causes its output atU3D, pin 14, to go low. The low connectsto U5A, pin 1, and, if the transmitter is inAuto, pin 2 of U5A is also low. With bothinputs low, the output of U5A at pin 3goes high. The high forward biases Q20and causes its drain to go low. The lowconnects to the operate coil on relay K1that switches the transmitter to Operate.The low at U5C, pins 8 and 9, causes theoutput at pin 10 to go high. This high isconnected to U5D, pin 12, and, if thetransmitter is in Auto, pin 13 of U5D islow. The high on pin 12 causes the
10-kW UHF Transmitter with Chapter 4, CircuitFeedforward Drive Descriptions840A, Rev. 0 4-20output of U5D to go low and reverse biasQ19. The drain of Q19 goes high andremoves the low from the standby coil inrelay K1.VSWR Cutback Fault. The reflectedpower sample of the RF output of thediacrode transmitter is connected to J2,pin 9, of the board. The sample connectsto op-amp U1B, pin 5, which buffers thesignal. The remote reflected sampleconnects to U2B, pin 5. If the reflectedsample level increases above the levelset by R22, the VSWR cutback pot, theoutput of U2B at pin 7 goes high. Thehigh is connected to Q11 through CR11,which is biased on and makes U2C, pin10, low; this causes U2C, pin 8, to golow. This low is split and fed out of thetray at J1-6, J1-7, J1-8, and J1-9. Theseare ALC outputs to the amplifier traysthat cut back the output power of thosetrays. The low from U2C, pin 8, is alsofed through the coaxial jumper W2 onJ13 and J14 to R73. R73 is a bias adjustpot that sets the level of the pinattenuator bias that is available as anoutput at J16.The high at U2B, pin 7, is fed to the baseof Q14 and Q13, which are forwardbiased, and produces a low at the drains.The low connects to the front panelamber VSWR Cutback LED DS7, causingit to light and indicate that the tray is incutback, and to output jack J8-37 for theconnection to a remote VSWR cutbackindicator.MeteringThe front panel meter connects to J3-1(-) and J3-2 (+) on the board; these arethe outputs of Front Panel Meter switchS3. The front panel meter has sixmetering positions that are controlled byS3: Audio, Video, % Aural Power, %Visual Power, % Exciter, and ALC.The video sample connects to the boardat J5-4 and is connected through R20,the video calibration pot, to position 6 ofswitch S3. The audio sample enters theboard at J5-6 and is connected throughR19, the audio calibration pot, to position7 of switch S3. The visual sampleconnects to the board at J2-5 and isconnected through buffer amplifier U1Dand 100Ω resistor R86 to position 4 ofswitch S3. The aural sample connects tothe board at J2-7 and is connectedthrough buffer amplifier U1C and 100Wresistor R85 to position 5 of switch S3.The exciter sample connects to the boardat J2-3 and is connected through bufferamplifier U1A and 100Ω resistor R87 toposition 2 of switch S3. The ALC sampleconnects to the board at J6-1 and isconnected through buffer amplifier U2C,and R15, the ALC calibration pot, whichadjusts the output of U2A, pin 1, througha 100Ω resistor R18 to position 1 onswitch S3.Typical readings on the meter are:• Video = 1 Vpk-pk at white• % Visual Power = 60% to 90%• % Aural Power = 60% to 90%• % Exciter = The level on the meterneeded to attain 100% output powerfrom the transmitterRefer to the test specifications sheet forthe transmitter for the actual reading:• ALC = .8 VDC• Audio = ±25 kHz with a balancedaudio input or ±75 kHz with acomposite audio inputSamples of the exciter at J1-10, thevisual at J8-26, the aural at J8-27, andthe reflected at J1-5 are provided forremote metering.U6 is a temperature-sensor IC that givesthe operator the ability to measure thetemperature inside the tray by measuringthe voltage at TP1. The sensor is set upfor +10 mV equals 1° F (for example,750 mV equals 75° F.)
10-kW UHF Transmitter with Chapter 4, CircuitFeedforward Drive Descriptions840A, Rev. 0 4-21Operational VoltagesThe +12 VDC needed for the operation ofthe transmitter control board enters theboard at jack J4, pin 3. C28, L1, and L3are for the filtering and isolation of the+12 VDC before it is split and applied tothe rest of the board. The -12 VDCneeded for the operation of the boardenters the board at jack J4, pin 5. C29and L2 are for the filtering and isolationof the -12 VDC before it is split andapplied to the rest of the board.When the +12 VDC is connected to theboard, it is split; four of the +12 VDCoutputs are fed out of the board at J8-16,J8-17, J8-18, and J8-19 through diodeCR7, CR8, CR9, or CR10 and resistorR50, R51, R52, or R53 to any externalamplifier trays for use in their logiccircuits. The resistors are for currentlimiting and the diodes are to preventvoltage feedback from the externalamplifier trays.4.1.1.10 (A19) Visual/Aural MeteringBoard (1265-1309; Appendix B)The visual/aural metering board providesdetected outputs of the visual and auraloutput samples that are used formonitoring on the front panel meter. Theboard also provides adjustments for thecalibration of the readings on the meter.These readings are attained fromsamples of the forward power andreflected power outputs of the tray.A forward power sample, visual + aural,is applied to SMA jack J1 on the board.The input signal is split, with one pathconnected to forward power sample SMAjack J2 for monitoring purposes. Theother path is connected through C1 toCR2, R4, R5, R6, C4, and CR1, whichmake up a detector circuit. The detectedvisual + aural signal is amplified by U6Band its output is split. One amplifiedoutput of U6B connects to the aural levelcircuit and the other output connects tothe visual level circuit.Aural Level CircuitOne of the detected visual + aural leveloutputs of U6B connects through C6 tothe intercarrier filter circuit that consistsof R13, R14, L1, C7, and C8; C8 and L1,the intercarrier filter, can be adjusted fora maximum aural reading. The filternotches out the video + aural and onlyleaves the 4.5-MHz difference frequencybetween the visual and aural, which is agood representation of the aural level.The 4.5-MHz signal is fed to bufferamplifier U6A. The output of U6A isdetected by diode detector CR3 and U1Aand then fed through aural calibrationcontrol R20 to amplifier U2D. Theamplified output of U2D is split, with themain output connected through R21 toJ6, pin 1, which supplies the aural leveloutput to the front panel meter formonitoring. The other output of U2D isconnected to aural null adjust R51 andoffset null adjust R48, which are adjustedto set up the visual power calibration.Visual Level CircuitThe other detected visual + aural leveloutput from U6B is connected to U1Cand, if there is no scrambling, connectsdirectly to intercarrier notch L3, which isadjusted to filter out the aural and the4.5-MHz intercarrier frequencies, leavingonly a visual-with-sync output. Thevisual-with-sync output is fed to a peak-detector circuit consisting of CR5 andU2A. The signal is then fed through visualcalibration control R28, which is adjustedfor a 100% visual reading with no aural,to amplifier U2B. The amplified visualpeak of sync output is connected tocomparator U2C. The other input to U2Cis the level set by aural null adjust R51,which is adjusted for 100% visual powerafter the aural is added and the peakpower is adjusted back to the referencelevel. Inputs to U2C also come fromoffset null adjust R48, which is adjustedfor 0% visual power with the transmitterin Standby. The adjusted output isamplified by U3D and connected to theother input of U2C. The output of U2C
10-kW UHF Transmitter with Chapter 4, CircuitFeedforward Drive Descriptions840A, Rev. 0 4-22connects to J6, pins 2 and 3, whichsupply the peak of sync visual leveloutput to the front panel meter formonitoring.If this board is operated with scrambling,using suppressed sync, the visual levelcircuit operates differently than describedabove because there is no peak of syncpresent on the forward sample input. Forthe board to operate properly, a timingpulse from the scrambling encoder mustconnect to the board at J4. This timingpulse is converted to sync pulses by U4Aand U4B, which control the operation ofQ2. Intercarrier notch L2 is tuned toremove any visual + aural signal thatmay remain.The sync amplitude is controlled by gateamplitude adjust R25 and then applied tothe minus input of U1C. At this point, it isinserted into the visual + aural signalthat is connected to the plus input ofU1C, producing a peak of sync in thesignal. The output of U1C is connected tointercarrier notch L3, which is adjusted tofilter out the aural and the 4.5-MHzintercarrier frequencies. The visual-with-sync output is fed to a peak-detectorcircuit, consisting of CR5 and U2A, andthen fed through visual calibration controlR28 to amplifier U2B. The amplifiedvisual peak of sync output is connectedto J6, pins 2 and 3, that supply the peakof sync visual level output to the frontpanel meter for monitoring. R32 movesthe pulse to where the sync should beand R25 sets the visual meteringcalibration with no sync present.Voltages for Circuit OperationThe ±12 VDC is applied to the board atJ5. The +12 VDC is connected to J5, pin3, and is isolated and filtered by L4 andC34 before it is connected to the rest ofthe board. The +12 VDC also connects toU5, a 5-VDC regulator that provides thevoltage needed to operate U4. The -12VDC is applied to J5, pin 1, and isisolated and filtered by L5 and C35before it is connected to the rest of theboard.4.1.1.11 (A4-A14) Channel OscillatorAssembly, Dual Oven (1145-1202;Appendix B)The channel oscillator assembly containsthe channel oscillator board (1145-1201)that generates a stable frequency-reference signal of approximately 100MHz. The channel oscillator assembly isan enclosure that provides temperaturestability for the crystal oscillator. An SMAoutput at jack J1 and an RF sample atBNC connector jack J2 are also part ofthe assembly.Adjustments can be made through accessholes in the top cover of the assembly.These adjustments are set at the factoryand should not be tampered with unlessit is absolutely necessary and the proper,calibrated equipment is available. R1 isthe temperature adjustment; C11 is thecourse-frequency adjustment; and C6,C18, L2, and L4 are adjusted for themaximum output of the frequency asmeasured at jack J1. C9 is the fine-frequency adjustment.The +12 VDC for the assembly entersthrough FL1 and the circuit-groundconnection is made at E1.4.1.2 (A1-A9) 3-Watt UHF AmplifierTray (1068203; Appendix A)The modulated RF carrier signal (+8dBm) from the 3-watt UHF amplifierenters through J1 and is filtered by (A1)a bandpass filter (1007-1101). The signal(+7 dBm) is then fed to (A2) the AGCboard (1007-1201). The AGC boardcontrols the overall gain of the amplifiertray by comparing a sample of the outputsignal from the dual peak detector boardthrough the AGC control board. An AGCreference voltage is generated eitherexternally or internally depending on thesystem operation and the position of thejumper on J7. The jumper should be
10-kW UHF Transmitter with Chapter 4, CircuitFeedforward Drive Descriptions840A, Rev. 0 4-23between J7-1 and J7-2 for the operationof the diacrode (external reference).The (A25) AGC control board (1137-1201) compares a sample of the outputof the diacrode with a sample of the 3-watt tray. The front panel gain control R2adjusts the overall gain of the tray. Theoutput voltage of the comparator drives apin attenuator circuit that corrects fordrift by maintaining a constant outputeven though temperatures, thereforegain, of the amplifier devices in A3, A5,or A7 may vary.The AGC board also contains circuitrythat monitors the AGC level and providesfor an AGC override detector. If the final3-watt amplifier stage is overdriven, theAGC override LED DS2 on the front panelwill light to indicate a cutback of the AGCthat cuts the gain of the tray. The AGCoverride detector is also used as thesystem Mute (Standby, VSWR fault, andother faults). There is also a ramp controlsignal input to the AGC control board.When the 3-watt amplifier is externallyenabled, the drive output of the amplifierramps up over a time frame of severalseconds. The output of the pin attenuatoris amplified to approximately 0 dBm andfed to output jack J2 of the board.The RF from the AGC board is fed to(A27) the UHF phase shifter board(1142-1315). The phase-corrected signalis then amplified by (A3) the UHFamplifier/regulator board (1007-1204)that has a nominal gain of +17 dB. Next,the signal (+17 dBm typical) is amplifiedby (A5) the 3-watt amplifier board #1(1007-1211) that has a nominal gain of+9 dB. The operating drive current, noRF input, for the 3-watt amplifier board#1 is set by the (A6) opto-bias board(1002-1109). The signal (+26 dBmtypical) is amplified further by (A7) the3-watt amplifier board #2 (1007-1211)that also has a nominal gain of +9 dB.The operating drive current for the 3-watt amplifier board #2 is set by (A8) theopto-bias board (1002-1109).The output (typically +35 dBm) of thesecond 3-watt amplifier board is fed to(A29) the overdrive protection board(1142-1626). The signal enters the boardat J4 and is connected directly out of theboard at J5. A sample of the RF signal iscoupled off the input and fed to adetector circuit to set up the AGCoverride level. If the RF output level ofthe transmitter increases to 120%, theoverride circuit will cut back the output ofthe 3-watt tray to prevent damage to theamplifier devices.The output of the overdrive protectionboard is fed to (A9) a dual couplerassembly (1007-1208) that supplies aforward and reverse power sample to(A10) the dual peak detector board(1137-1510). The dual peak detectordrives the front panel meter for a %Reflected Power reading and alsoprovides a forward power sample (innerloop AGC) to (A25) the AGC controlboard (1137-1201). The AGC controlboard provides an output to the frontpanel meter for the % Forward Powerreading and also provides an output tothe AGC board that is used as the AGCsample of the output. If an outer loopAGC is used from an external amplifiertray, it is fed to the AGC control boardthrough J5 on the rear of the tray. Theoutput from the dual coupler is directedto the RF output jack J2 on the rear ofthe tray (+35 dBm).Two power supplies are used in the tray.The (A16) +24V power supply board(1007-1207) supplies power for theamplifier devices through the opto-biasboards in the 3-watt amplifiers and theUHF amplifier/regulator board. The (A22)general purpose ±12V power supplyboard (1062-1013) supplies voltage tothe rest of the boards in the tray.AC is applied to the tray through J4 onthe rear panel and is connected toterminal block TB2. MOVs VR1 and VR2are provided as protection fromtransients or surges on the AC input line.When CB1, the 2.5-amp circuit breaker,
10-kW UHF Transmitter with Chapter 4, CircuitFeedforward Drive Descriptions840A, Rev. 0 4-24is switched on, AC is applied to fans A19and A20 and also to (A21) the step-downtransformer for the ±12V power supply.The stepped-down AC is applied to (A22)the ±12V power supply board (1062-1013) that supplies the regulated ±12Vto the rest of the boards in the tray. LEDsDS1 for +12V and DS2 for -12V on theboard will light to indicate that the powersupply is operational.Even with the circuit breaker switchedon, the +24V power supply will not turnon until the power supply enable controlline J3-8 is taken Low (Enabled). Thisoccurs by jumpering J3-8 to J3-7 or byan external pull-down, which is normallyprovided by the power supply Enablefrom the metering control panel.With the pull-down present, (A11) thepower supply control board (1007-1202)will energize (A12) the isolation relayboard (1002-1108). The 120 VAC is thenapplied to (A13) the toroid and then to(A14) the full-wave bridge rectifiernetwork that supplies approximately 40volts to the +24 volt power supply board.4.1.3 (A1-A6 and A1-A7) 250-WattAmplifier Trays (1044027, lowband/1044028, mid band/1044029,high band; Appendix A)The 250-watt amplifier tray, with an RFinput of +24 dBm peak visual and 10%aural, provides an average output powerlevel of +54 dBm peak visual. Theamplifier utilizes feedforward circuitry tominimize distortion and increase output.RF PathThe input to the 250-watt amplifier trayat the BNC-type connector jack J1 is thediplexed on-channel visual + aural signal.The input RF is connected to J1 of (A1-A1) the single stage amplifier assemblythat is mounted on (A1) the amplifierenclosure. The (A1-A1) single stageamplifier assembly, which contains ageneric single stage amplifier board(1265-1415) and the required frequencydetermining kit, is a class A amplifiersupplying 11.5 dBm of gain at J2. Theoutput is fed to (A1-A3) the striplinecoupler board. The coupler boardsupplies a –10 dB sample for (A3) thephase/gain adjust module at J3. Thissample is the linear portion of thefeedforward signal. The output of thestripline coupler board is fed to (A1-A5)the single stage amplifier assembly, classAB. The single stage amplifier assemblyis mounted on (A1) the amplifierenclosure and consists of a generic singlestage amplifier board, class AB (1286-1234), with the required frequencydetermining kit. This assembly has aminimum gain of approximately 8 dB.The (A1-A5) amplifier assembly output isconnected to (A19-A6) the splitter board.The splitter board is a two-way wilkinsonsplitter that feeds the inputs of (A19-A7,A19-A8) the dual output power amplifierassemblies, class AB. The dual outputpower amplifier assembly, class AB, ismade using a generic dual stageamplifier board, class AB (1265-1404),and the appropriate frequency dependentkit. The two assemblies, A1-A7 and A1-A8, are identical. The dual output poweramplifier board uses two PTB20101transistors in parallel-biased class AB toamplify the signal. The bias adjust R106sets the operating current for Q101 andthe bias adjust R206 sets the operatingcurrent for Q201. The output of bothassemblies is soldered directly to (A19-A9) the 2-way combiner board. The totalgain through the splitter board, amplifierassemblies, and combiner board is aminimum of 8 dB.The (A19-A9) 2-way combiner board isfrequency dependent for low-band,middle-band, and high-band. Thecombiner board also has a –40 dBcoupler for forward and reflected powersamples. The forward port J1 is cabled to(A5) the dual stripline coupler board as asample for the feedforward circuit. This isthe non-linear portion of the feedforwardsignal and is used as a reference to
10-kW UHF Transmitter with Chapter 4, CircuitFeedforward Drive Descriptions840A, Rev. 0 4-25cancel any remaining non-lineardistortion at the output.The reflected port is terminated into a 1-watt, 50Ω load (A19-A10). After thelinear and non-linear samples have beenmatched for gain and delay, and theirphases have been adjusted to a 180°difference, they are summed together inthe (A5) dual stripline coupler board.From A5-J2, the mixed signals are fed tothe (A20) correction phase/gainenclosure at J1. The (A20-A1) erroramplifier phase/gain module is used tomatch the gain of the correction path tothe output level of the main amplifier atthe RF O/P part of the (A7) 7 dB coupler.The phase/gain module also sets the180° phase imbalance between the twosignals. These two signals, whencombined, cancel most of the distortionin the signal at the RF output connection.The A20 module is terminated in thereject load (A19-A18) in (A19) theamplifier enclosure. The RF output fromthe coupler output is fed to the input, J1,of (A8) the UHF coupler assembly. J3,the forward sample on the coupler board,is fed to J1 of (A17) the peak detectorboard. The reflected sample at J4 isterminated into a 1-watt, 50Ω load. Theoutput, J2, is fed to (A10) the circulator,which protects the tray from high-reflected power, to the output of the trayat the N-type connector J2. Any reflectedpower at J2 is fed to (A2-A6) the rejectload/coupler board mounted inside (A1)the correction amplifier enclosure.Feedforward CorrectionThe feedforward correction circuitsconsist of phase and gain adjustmentboards, delay lines, and amplifiers tosample and cancel any non-lineardistortions introduced into the RF signalby the power amplifiers. A sample of thelinear RF signal sampled at (A19-A3) thestripline coupler board is adjusted andamplified to be of equal gain and 180°out of phase with the non-linear samplefrom the (A19-A9) 2-way combinerboard. The linear sample is phaseadjusted through the use of C1 and C2on the (A3) phase/gain adjust module.The gain for the module is set by R22 onthe (A16) amplifier control board. Thislinear signal is combined with the non-linear signal at (A5) the stripline couplerboard. The combined out-of-phase non-linear and in-phase linear signal isamplified and then combined with the RFsignal at the 7-dB coupler board. Thegain of the combined signals is controlledon the amplifier control board by R20 andthey are phase adjusted by R29 on thesame board. The resulting output signalwill have a 20 dB cancellation of non-linearities.Amplifier Control BoardThe (A16) amplifier control boardprovides output level sample inputs to(A12) the meter and protection of thetray against overheating. The (A8) UHFcoupler board and (A2-A6) the rejectload/coupler board supply forward and areflected output power samples to (A17)the dual peak detector board. The dualpeak detector board takes the forwardand reflected output power samples andprovides peak-detected DC levels to theamplifier control board and uses them formetering purposes. If anovertemperature fault occurs becauseone of (A1-A13 or A1-A14) the thermalswitches closes due to the overheating ofthe output amplifier heatsink, the +5VDC inhibit to the switching power supplywill be applied. This will disable theswitching power supply. The amplifiercontrol board can be adjusted to set thecalibration of the front panel meter forthe Forward, Reflected, and PowerSupply positions.Operation of the TrayThe 220 VAC input needed to operate thetray connects to the tray at J3 and issupplied to the rest of the tray when thecircuit breaker, CB1, is switched on. Theinput AC connects to (A11) a+26.5V/1500W switching power supply
10-kW UHF Transmitter with Chapter 4, CircuitFeedforward Drive Descriptions840A, Rev. 0 4-26that provides the +26.5 VDC to the twocooling fans and, when the tray isenabled, through the amplifier protectionboard to the rest of the boards in thetray. The enable is applied to the tray atJ4-5 on the back of the tray. The outputof the switching power supply isconnected to (A15) the amplifierprotection board and also to (A13 andA14), which are two fans used for coolingthe tray. The amplifier protection boardprovides 7-amp fused protection of the+26.5 VDC outputs before they aredistributed to the amplifier boards in thetray. An external +12 VDC needed forthe operation of the status LEDs mountedon the amplifier control board is appliedto the 250-watt amplifier tray, from theUHF upconverter tray, through J4-7. The+12 VDC is present when the main AC isapplied to the UHF upconverter tray.4.2 (A2) 10-kW Diacrode Amplifier(1299-1100; Appendix A)4.2.1 10-kW Bias Power SupplyBoard, 230 VAC Input (1181- 1001;Appendix B)The 10-kW bias power supply boardprovides the -80 VDC bias voltage,typical setting, that is applied to thecontrol grid of the TH610 diacrode powertube. This tube is mounted in theTH18610 cavity assembly in the 10-kWamplifier assembly.The bias power supply board (1181-1001) has a 230 VAC input that isapplied to J1, pins 1 and 4, when the biascircuit breaker on the AC distributionpanel is switched on, and (A3) theisolation relay board, part of the controland bias power supply assembly, isenergized. The 230 VAC is applied to afull-wave bridge network, consisting ofCR1 to CR4, that rectifies the AC. Theoutput of the full-wave bridge is filteredby capacitors C1 and C10 and applied toa shunt-regulator circuit that utilizescomparator IC U1. The shunt pathincludes VR1, Q1, and U1; R10 is thebias adjust that applies the controlvoltage to the (+) terminal of U1 at pin12. The negative output of IC U1 at pin14 connects to the base of Q1 and setsup the biasing for the transistor. Theamount of forward bias that is applied tothe transistor determines the voltagedrop across the transistor. The value ofthe output voltage, as measured acrosszener diode VR1 and Q1, is variablebecause of the changes in the voltagedrop across the transistor. The biasvoltage output of the board at J3, pins 1and 2, is typically adjusted for -80 VDC.The supply voltages to U1 are set atapproximately -1 VDC and -11 VDC byzener diode VR2. The main current pathto the tube is from ground through R4,R17, and R8 to the tube.VR8 and VR9 are protection zener diodesthat prevent the output voltage fromrising above -174 VDC. CR7 prevents theoutput from going positive and causingdamage to the tube. VR10 and VR11 arezener diodes that prevent voltage spikesabove +10 VDC or below -10 VDC fromentering the voltage metering circuit if anarc occurs in the tube or in the tubecavity assembly. VR6 and VR7 are zenerdiodes that prevent voltage spikes above+10 VDC or below -10 VDC from enteringthe current metering circuit if an arcoccurs in the tube or in the tube cavityassembly. If R4 opens, VR4 and VR5prevent the voltage on the floatingground from rising above a maximum of4 VDC.The 5 kΩ bias adjust pot R10 is locatedon the front, left-hand side of theamplifier assembly, behind the swing-outpanel. It connects to J2, pins 3, 5, and 6,on the board. The bias adjust pot setsthe bias (grid) voltage output level, -80VDC (typical). The bias is adjusted for1.5 amps of static plate current.Note: The static plate current isadjusted without RF drive applied tothe tube.R14 calibrates the bias voltage reading atJ2, pin 8, that is applied to the voltage
10-kW UHF Transmitter with Chapter 4, CircuitFeedforward Drive Descriptions840A, Rev. 0 4-27meter on the metering control panel. R6calibrates the bias (control grid) currentmeter reading at J2, pins 1 and 2, that isapplied to the current meter on themetering control panel. These metercalibration adjustments were set at thefactory for typical operation and shouldnot need adjustments at this time.4.2.2 Control and Bias Power SupplyAssemblyThe control and bias power supplyassembly (1181-1402) contains twoseparate power supplies. The controlpower supply consists of input terminalblock TB2; T1, a step-down transformer;(A1) a ±12 VDC power supply board(1092-1206; Appendix B); and TB4, anoutput terminal block. The bias powersupply consists of input terminal blockTB1; (A3) an isolation relay board(1002-1108; Appendix B); (A2) a biaspower supply board (1181-1001;Appendix B); and TB3, an outputterminal block.The 220 VAC main input to the controlpower supply connects to terminal blockTB2, terminals 1A and 3A (neutral) and4A (ground). VR3 and VR4 are metal-oxide varistors (MOVs) that protect thesupply from any AC input line surges.The 220 VAC is applied to the terminalblock as long as the control circuitbreaker on the AC control assembly isswitched on. The AC is directed to T1, astep-down transformer, that producestwo AC outputs. The two stepped-downAC outputs connect to J1, pins 1 and 4,and J1, pins 7 and 8, on (A1) the ±12VDC power supply board. The AC inputsare full-wave bridge rectified and filteredand regulated to produce the ±12 VDCoutputs at TB4 that connect to thecontrol circuits in the metering controlpanel. This also produces the +12 VDCthat is sent to the isolation relays in thepower supplies and the blowerassembly.The 220 VAC main input to the biaspower supply connects to terminal blockTB1, terminals 1A and 2A (neutral) and3A (ground). VR1 and VR2 are MOVsthat protect the supply from any ACinput line surges. The 220 VAC isapplied through the closed contacts of(A3) the isolation relay to (A2) the biaspower supply board as long as the biascircuit breaker on the AC controlassembly is switched on. The bias-oncommand is applied to TB1-6 and thecontrol power supply is on to producethe +12 VDC applied to TB1-5. The ACis connected to J1, pins 1 and 4, of (A2)the bias power supply board. The ACinput is full-wave bridge rectified andfiltered and regulated to produce thebias output at TB3-6 and TB3-7 thatconnect to the grid of the TH610diacrode tube (typically –80 VDC).4.2.3 Screen Power SupplyAssemblyThe (A6) screen power supply assembly,60 Hz (1293-1321), provides the 500VDC at 30 mA screen voltage to thetube mounted in the 10-kW diacrodeamplifier assembly. The automatic turn-on procedure applies the screen voltageto the tube after it has applied the highvoltage to prevent damage to the tube.The assembly consists of TB1, an inputterminal block; (A7) an isolation relayboard (1002-1108; Appendix B); (A8) aSola 60-Hz regulator assembly; T1, astep-up transformer; (A6-A1) a screenpower supply board (1293-1319;Appendix B); (A6-A3) a fan; and theoutput connections to the tube and themetering control panel.The 220 VAC main input to the screenpower supply connects to terminal blockTB1, terminals 1A and 2A and 3A(ground). VR1 and VR2 are metal-oxidevaristors (MOVs) that protect the supplyfrom any AC input line surges. The 220VAC is applied to the terminal block aslong as the screen circuit breaker on theAC control assembly is switched on. The(A6-A3) fan will operate as long as theAC is applied to the terminal block. Inaddition, the red LED DS1 will be lit.
10-kW UHF Transmitter with Chapter 4, CircuitFeedforward Drive Descriptions840A, Rev. 0 4-28The 220 VAC is applied through theclosed contacts of (A7) the isolationrelay board, to (A8) the Sola regulatorassembly, and to transformer T1 as longas the screen circuit breaker on the ACcontrol assembly is switched on. Thescreen-on command is applied to TB1-6and the control power supply is on toproduce the +12 VDC that is applied toTB1-5.The 220 VAC is connected to step-uptransformer T1 to produce anapproximately 540 VAC output that isapplied to J1, pins 1 and 4, of (A6-A1)the screen power supply board. The ACinput is full-wave bridge rectified, eachpath with four diodes in series; filteredby four 8-uF capacitors; and regulatedby the zener diodes to produce thescreen output at J3-1 and J3-5 thatconnects to the screen of the TH610tube (typically 500 VDC). SCR-1provides a crowbar protection circuitthat eliminates the screen voltage, if itincreases beyond the preset limit, toprevent damage to the tube. SCR-1 alsocauses a screen current fault conditionand sends this information to thetransmitter.4.2.3.1 Screen Power Supply Board(1293-1319; Appendix B)The screen power supply board providesthe screen voltage (nominal 500 VDC) tothe TH610 diacrode tube mounted in thecavity assembly of the 10-kW amplifier.The screen power supply board operateswhen the screen circuit breaker on theAC control assembly is switched on andthe (A7) isolation relay board, part of thescreen power supply assembly, isenergized by the screen-on command.The output of T1, the step-downtransformer that is part of the screenpower supply assembly, provides 550VAC to J1-1 and J1-4 of the screen powersupply board. The 550 VAC is applied toa full-wave bridge network that consistsof CR1 to CR16. The diodes are in sets offour per leg for high-current and over-voltage protection. The output of the full-wave rectifier connects to four capacitors,C1 and C14 to C16, that are used forfiltering. The filtered 780 VDC connectsthrough the loading resistors R5 and R24to the output regulating circuitry. If theoutput voltage increases aboveapproximately 750 VDC, SCR-1 willenergize and pull the output down toprotect the tube from damage.Zener diode VR21 prevents the outputvoltage from going negative. VR19 andVR20 protect the current metering circuitfrom damage in case of an arc in thetube or in the cavity assembly. VR22 andVR23 protect the voltage metering circuitfrom damage in case of overvoltage oran arc in the tube or in the cavityassembly. The voltage and currentregulated DC (nominal +500 VDC) outputof the board at J3, pins 1 and 5, is fed tothe screen input connector of the 10-kWtube cavity assembly.The screen voltage output can beadjusted by using variable resistor R14on the board. Together, U1A and Q1provide a voltage-regulator circuit for thescreen voltage. U1A acts as a comparatorthat monitors the voltage setting of R14at U1A, pin 12, and the voltage of theinput at U1A, pin 13. The voltage levelsthat are applied to U1A will determinethe amount of bias that is applied to Q1as well as the output voltage level.R20 can be adjusted and is used tocalibrate the screen voltage at J4, pins 4and 5, that connects to the voltage meteron the metering control panel. R9 can beadjusted and is used to calibrate thescreen current reading at J4, pins 1 and2, that connects to the current meter onthe metering control panel. Theseadjustments were calibrated at thefactory for typical operation and shouldnot be readjusted.
10-kW UHF Transmitter with Chapter 4, CircuitFeedforward Drive Descriptions840A, Rev. 0 4-294.2.4 Filament Power SupplyAssemblyThe filament power supply assembly(1299-1107) consists of input terminalblock TB2, status and control terminalblock TB1, the (A1) filament powersupply control board (1293-1304;Appendix B), and the (A2) programmablefilament power supply (1293-6302).The 220 VAC is supplied at TB2-1A andTB2-2A and ground at TB2-3A. There arethree MOVs (VR1 to VR3) mounted onthe terminal block to protect againstvoltage spikes and transients. The 220VAC is fed from TB2-1B, TB2-2B, andTB2-3B to (A2) the programmablefilament power supply at TB1-L, TB1-N,and TB1-GND. The output of the powersupply is fed to the filament of (A2-A1)the diacrode tube.4.2.4.1 (A1) Filament Power SupplyControl Board (1293-1304; Appendix B)The filament power supply control boardhas five functions:• Control and status of the threestates of filament voltage (float,ramp, and operate) for the filamentpower supply• Provide two on-board LEDs for statusindication• Provide adjustments to the operatevoltage• Monitor the operate status throughmonitoring the +12 VDC supply and220 VAC power• Adjust the front panel metering forthe filament voltage and the tuberun-time hour meter controlThese functions are controlled throughthe software programming in U4, aMotorola MC68 microcontroller.Filament ControlWhen the filament circuit breaker on thefront panel is activated, the filamentcontrol board sets the program controlat J3-1 to achieve an output from thepower supply of 1.5 VDC. The outputfrom U4 PA0-PA7 controls the DAC U3voltage output at pin 16, which isbuffered by U5 and sent to J3-1. Afterten minutes of valid power supplyoperation, the control board sends afilament-ready signal at J4-2 out to thetransmitter control board (1137-1003),allowing the transmitter to be placed inthe Operate mode. Once the Operateswitch has been enabled at the frontpanel, the power supply controllergradually increases the filamentoperating voltage. During the ramp-upphase, every 0.80 seconds the DACoutput at J3-1 to the filament powersupply is increased by one bit. Assumingno faults, the tube voltage reaches theoperating range three minutes afterclosure of the Operate switch. J4-2(filament OK) is a logic output to thetransmitter control board. Logic 1indicates that the filament power supplyis at the operate or ramp-down voltage(-5.0 VDC). Logic 0 indicates that thepower supply is at the float or ramp-upvoltage (- less than 5.0 VDC). Duringramp-down, this logic level is held highto direct the transmitter control board tokeep the blower operating. The blowerwill continue to operate for threeminutes after the float voltage level isreached.On-board LED indicatorsThe on-board visual indication of thecontroller state is provided by LED DS1.This LED is off if the power supply isdisabled; blinking at about 1 Hz if thefloat voltage is being held for tenminutes; blinking at about 2 Hz if thecontroller is ready to ramp up thefilament voltage; blinking at 4 Hz if thecontroller is ramping the voltage up ordown; and continuously on when thefilament is at operate voltage levels. The
10-kW UHF Transmitter with Chapter 4, CircuitFeedforward Drive Descriptions840A, Rev. 0 4-30control for DS1 is from U4, PLMA, pin20, to FET Q2.DS2 is the Output Verified LED. It isused to indicate system status and isactivated through pin 35 of U4 and FETQ3. Table 4-1 below lists the state,condition and flash-rate of the LED.Table 4-1. State, Condition, and Flash Rate of LED DS2STATE CONDITION LED FLASH RATENormal Condition --1.0 second on, 1.0 secondoff (0.5 Hz; 50% dutycycle)AC Fault J4-1 <4 VDC One flash (0.2 second on),then pause 5 secondsDC Fault J1-3 <9 VDC Two flashes (0.2 secondon), then pause 5 secondsDAC Fault DAC = 4.625 VoutDAC = 0.0 VoutThree flashes or fourflashes (0.2 second on),then pause 5 secondsPower Supply Fault Power supply not regulatingat float voltageFive flashes (0.2 secondon), then pause 5 secondsManual Operate Voltage AdjustmentAdjustment of the filament power supplyis a two-step process. The systemcalibration of DAC, U3, using variableresistor R6 must first be verified. Withthe ten-minute ramp-up time completeand the transmitter still in stand-by,place SW1-7 in the On position. Verifythat the output at J3-1 is 5.0 VDC; if itis not, adjust R6 until this voltage isachieved.Note: Do not make the aboveadjustments with the transmitter inthe Operate mode.Once the system calibration voltage hasbeen verified, monitor the output of thefilament power supply during full poweroperation. This value should be 5.0 VDC.Adjust R28 on the filament control boardto set this voltage.Power MonitoringBoth the +12 VDC and the 220 VACsupply voltages are monitored. If the220 VAC power is lost, the logic low atJ4-1 will go high. This logic high is seenat PD1 of U4, which directs themicrocontroller to ramp the filamentcontrol back to the float voltage. If the+12 VDC supply at J1-3 drops belownine volts, the filament control alsoramps back to the float voltage. The+12 VDC voltage is monitored at U4, pin3.Front Panel Metering ControlThe front panel metering adjustment iscontrolled by R15. Verify that themetering control rotary switch below theleft-hand meter on the front panel is setto Filament. Monitor the filament powersupply output and adjust R15 to obtainthe same reading. The current meteringadjustment on the control board is notused.Tube Run-Time Hour MeteringWhen the operator closes the operateswitch, J4-6 changes from a voltagelevel of twelve volts to approximatelytwo volts. With J4-6 at two volts, relayR1 on the controller board is closed. This
10-kW UHF Transmitter with Chapter 4, CircuitFeedforward Drive Descriptions840A, Rev. 0 4-31enables the tube hour counter that isconnected through connector J7-1 andJ7-5.Operational VoltagesThe +12 VDC needed to operate theboard enters at J1, pin 3, and is filteredby L1, C1, and C4 before it is fed to therest of the board.The -12 VDC needed to operate theboard enters at J1, pin 5, and is filteredby L2 and C21 and C22 before being fedto the rest of the board.The +5 VDC is supplied by 5-VDCregulator U1 and is filtered by C1 and C3before being fed to the rest of the board.C3 is used to maintain power on the +5-VDC line for short duration power losses.DIP Switch ConfigurationThe DIP switch configurations for theboard are shown in Table 4-2.Table 4-2. DIP Switch Configurations for the Filament Power Supply Control BoardPOSITION FUNCTIONSW1-1 Not connectedSW1-2 Accelerate timers: When set high, the ramp-up, ramp-down, and blowerdelay timers operate four times fasterSW1-3 Ten-minute by-pass: When set high, and all other DIP switch settings arelow except SW1-5, the ten-minute warm-up is skippedSW1-4 SCADA: When set high, SCADA interrupts will be processed(future development)SW1-5 Set DAC 0.0 VDC: When in the Standby mode, setting this switch highcauses the DAC to output 0.0 VDCSW1-6 Set DAC 4.625 VDC: When in the Standby mode, setting this switch highcauses the DAC to output 4.625 VDCSW1-7 Set DAC 5.0 VDC: When in the Standby mode, setting this switch highcauses the DAC to output 5.0 VDCSW1-8 Micro reset: When this is set high, the microcontroller is held in reset4.2.5 Metering Control PanelThe (A7) metering control panel (1293-1308) contains three meters: one forvoltages, one for currents, and one forpower output. The voltage meter displaysthe plate, screen, bias, and filamentvoltages that are applied to the tube. Thecurrent meter displays the plate, screen,and grid currents that are produced bythe tube. The power meter displays the% Aural Output power, % Visual Outputpower, and % Reflected Output power ofthe 10-kW amplifier. The meteringcontrol panel also provides the systemcontrol functions for the 10-kWtransmitter.The metering control panel consists of(A1) the control logic board (1137-1402),(A7) the transmitter control board (1137-1003), (A2 and A3) two differential bufferboards (1008-1017), (A4) fault sensingboard, diacrode (1293-1307), (A5) faultsensing board, inverting (1016-1401),and (A6) the fault sensing board, dualpolarity (1016-1402). The panel also has(M1) a front panel voltage meter with(S1) the meter control switch; (M2) afront panel current meter with (S2) themeter control switch and (S3) the meterreverse switch; and (M3) a front panelpower meter with (S4) the meter controlswitch. The panel has (S5) theOperate/Standby switch, (S6) theAuto/Manual Mode Select switch, (S7)the High-Voltage Enable/Disable switch,
10-kW UHF Transmitter with Chapter 4, CircuitFeedforward Drive Descriptions840A, Rev. 0 4-32(S10) the Driver Mode Normal/Testswitch, (S9) the Fault Reset switch, and(S8) the Power Output Raise/Lowerswitch.The ±12 VDC needed to operate theboards in the metering control panel areprovided to J2-1 (+12 VDC), J2-2 (±12VDC Return), and J1-50 (-12 VDC) bythe control section of (A5) the controland bias power supply assembly. The ±12VDC is applied to the metering controlpanel when the control circuit breaker isswitched on. The ±12 VDC connects toterminal block TB1 that, using jumpers,splits the ±12 VDC which is then fed tothe boards in the metering control panel.4.2.5.1 (A1) Control Logic Board (1137-1402; Appendix B)The control logic board in the meteringcontrol panel provides the circuitryneeded for the control of the automaticon/off sequence of the transmitter andthe monitoring of the operation of thetransmitter for fault conditions. AnOperate command and the interlocks forthe transmitter are also connected to theboard. The board monitors the Air-OnSense, the Filament-On Sense, the Bias-On Sense, the High Voltage-On Sense,and the Screen-On Sense commandsduring each step of the automatic turn-on procedure. The board provides the Oncommand outputs in the proper sequenceas well as the enables to the CommandStatus and Operating Status LEDs on thefront panel. The fault circuits monitor theoperation of the power supplies and thetube, the air flow to the tube, and thetemperature of the transmitter and willshut down the transmitter if any of thesefaults occur.The board supplies the Air-On, Filament-On, Bias-On, Screen-On, High Voltage-On, and RF-On commands to thetransmitter. The control logic board isconnected to the High VoltageEnable/Disable switch and provides thecommands to K1, the magnetic latchingrelay mounted on the board.Operation of the Control Logic BoardWhen the Operate/Standby switch on thefront panel of the metering control panelis switched to Operate, a Low Operatecommand from the transmitter controlboard is applied to J2-1 and lights theOperate LED connected to J12-1 and J12-2. The low at J2-1 is connected to theOR gate at U1-1. An external, total-shutdown interlock must be closed forthe transmitter to operate. The low of thetotal-shutdown interlock is wired to J2-3,and connects to the board-mountedTotal-Shutdown Interlock LED at J12-4and J12-5, which will light. The low isalso connected to OR gate U1-2 and, withboth U1-1 and U1-2 low, the output atU1-3 will be low. The low from U1-3connects to AND gates U2-1, U2-5, andU2-8. The low also connects to the ORgate U6-9. The IC U2, pins 1, 2, and 3, islocated in the Blower-On commandcircuit. The U2-1 low causes the outputat U2-3 to go low. This low connects toinverter IC U4, whose output at U4-2goes high. The high forward biases Q1,whose collector goes low and applies theLow Blower, Air, On command at J17-1 ofthe board. The Blower, Air, On commandconnects through the front panel-mounted Command Status LED DS8,which will light. The blower control relaythat energizes and turns on the blower iscontrolled by Q1. The operation of theblower causes air flow through the tubecavity assembly which is monitored by anair-flow switch mounted in the chimney.If the air flow is adequate, the switchcloses and applies a low, air-on sense, toJ2-5 of the board. This lights the frontpanel-mounted Operating Status BlowerLED DS16.The low, air-on sense at J2-5 connects toU1-5 in the Filament-On command circuitand lights the Blower, Air, On LEDconnected to J12-7 and J12-8. U2-5 islow and causes the output at U2-6 to below. U1-6 and U1-5 are both low, whichcauses the output to go low. The lowconnects to inverter U4, whose output at
10-kW UHF Transmitter with Chapter 4, CircuitFeedforward Drive Descriptions840A, Rev. 0 4-33pin 4 goes high. The high forward biasesQ2, whose collector goes low and appliesthe Low Filament-On command throughthe front panel-mounted CommandStatus Filament LED DS9, which willlight, to the Filament Control Relay. Thelow energizes the relay and turns On thefilament power supply. The outputvoltage from the filament power supply ismonitored and produces a low, filament-on sense input to the board at J2-7. Thisaction lights the front panel-mountedOperating Status Filament LED DS17.The low, filament-on sense at J2-7 isapplied to U8, a clock IC that times outat approximately two minutes to allowthe tube to preheat before the rest of thevoltages are applied. Moving jumper W1on J11 changes the timer from twominutes to approximately 18 seconds.When the timer clocks out, a high isapplied to inverter U7-5, whose output atU7-4 goes low and connects to U6-2 inthe Bias-On command circuit. As long asthe filament voltage stays above 3.5VDC, the filament under-voltage input atJ2-9 will be low and is applied to U6-3.U6-4 will be a low as long as thetransmitter is in Operate or the biasvoltage is present to the tube. Since U2is an AND gate, either input low willcause the output to be low. With allinputs to U6 low, the output at U6-1 willbe low. The low is connected to inverterU4-7, whose output at U4-6 goes high.The high is applied to Q3, which isforward biased, and causes the collectorto go low. The Low Bias-On commandoutput at J7-6 connects through the frontpanel-mounted Command Status BiasLED DS12, causing it to light, to the biascontrol relay, which energizes and turnson the bias power supply. The outputvoltage from the bias power supply ismonitored and produces a low, bias onsense input to the board at J3-3, whichlights the front panel-mounted OperatingStatus Bias LED DS18, connected to J13-1 and J13-2.The low, bias on sense at J3-3 is appliedto U3-3 in the High Voltage-On commandcircuit and to U2-6 in the Filament-Oncommand circuit. U3-4 connects to thefault circuit on the board and will be lowunless a fault occurs. U3-5 will be lowunless both the high voltage is disabledand the screen voltage is removed fromthe tube. With U3-3, U3-4, and U3-5 alllow, this causes a low at U3-6 that isconnected to inverter IC U4-9, whoseoutput at U4-10 goes high. The highforward biases Q4 and causes itscollector to go low and apply the HighVoltage-On command through the frontpanel-mounted Command Status HighVoltage LED DS11, which will light, to thehigh-voltage control relay. The relayenergizes and turns on the high-voltagepower supply. The output voltage fromthe high-voltage power supply ismonitored and produces a low, highvoltage-on sense input to the board atJ3-7 and lights the front panel-mountedOperating Status High Voltage LED DS19.The low, high voltage on sense at J3-7 isapplied to U21-6 in the Screen Voltage-On Command circuit and to U2-9 in theBias On command circuit. U21-5 will be alow if both the high voltage is enabled,U21-8 low, and the screen interlock isclosed, U21-9 low. When U21-5 and U21-6 are both low, this causes a low at U21-4 that is connected to inverter IC U13-3,whose output at U13-2 goes high. Thehigh forward biases Q5 and causes itscollector to go low, which applies theScreen-On command through the frontpanel-mounted Command Status ScreenLED DS12, causing it to light, to thescreen control relay. The relay energizesand turns on the screen power supply.This logic circuit prevents the screenpower supply from turning on unless thehigh voltage is present to the tube. Theoutput voltage from the screen powersupply is monitored and produces a low,screen on sense input to the board at J3-11, which lights the front panel-mountedOperating Status Screen LED DS20.The low, screen voltage-on sense at J3-11 is applied to U21-2 in the RF-Oncommand circuit and to U2-13 in the
10-kW UHF Transmitter with Chapter 4, CircuitFeedforward Drive Descriptions840A, Rev. 0 4-34High Voltage-On command circuit. U21-1, which connects to U21-10, will be alow if both the high voltage is enabled,U21-8 low, and the screen interlock isclosed, U21-9 low. When U21-1 and U21-2 are both low, this causes a low at U21-3, which is connected to inverter IC U13-5, and whose output at U13-4 goes high.The high forward biases Q7, causing itscollector at J9-11 to go low and apply theRF-On command to the exciter. J9-10also goes low and lights the front panel-mounted Command Status RF RequestLED DS13. The low at U21-3 is alsoconnected to the base of Q6, whichreverse biases it and removes the mutefrom the 3-watt amplifier tray.The transmitter should be fullyoperational at this time with an RFoutput.Operation of the Fault CircuitsThe control logic board monitors thermalswitch A11-S1, control grid I, cathode I,and the reflected power, VSWR, forfaults. If a fault occurs in any of thecircuits monitored, a low from thethermal switch and/or the cathodecurrent and/or a high from the controlgrid current, screen I, or VSWR is appliedto the board. The fault causes thetransmitter to reset itself three times,each time trying to go back on the air, tomake sure that the fault is real. Afterthree resets, the transmitter switches toStandby.If thermal switch A11-S1, mounted in theexhaust stack of the tube cavityassembly, closes due to overheating, alow is connected to J5-3. The lowconnects to inverter IC U7-11, whoseoutput at U11-12 goes high. The highconnects to pin 6, the S1 set input, toone of four quad R-S latches that makeup U16. The output of the latch at pin 9goes high and connects to U1-9 and alsoto the base of Q8. Q8 is forward biasedand its collector goes low, lighting theOvertemperature LED DS22 on the frontpanel. The output of the OR gate U1-10goes high and connects to U6-12. Theoutput of U6 goes high and removes thehigh voltage enable from the logic circuitthat removes the enables to the screenvoltage and the high-voltage powersupplies.If a problem occurs with the control gridcurrent, a high is connected to J5-5. Thefault high connects to pin 4 the S0 setinput to one of four quad R-S latches thatmake up U16. The output of the latch atpin 2 goes high and connects to U3-11,whose output at pin 10 goes high. Thehigh connects to U15-1, the three-faultcounter, and also to U19-8 and U19-9.U19-10 goes high and forward biases Q9,whose collector goes low, lighting theFault Indicator LED DS7 on the frontpanel.The fault high at J5-5 also connects tothe set S3 input at pin 14 to one of fourquad R-S latches that make up U20 andto U11-5. The output of the latch at U20-1 goes high and is inverted by U18. Thelow is applied to DS12, the Bias FaultLED, on the board, which will light.Because the input to U11 at pin 5 is high,the output of U11 at pin 1 goes high,which resets clock IC U9. The Q1 and Q0outputs of U9 go low during reset, thenback to high, and are applied to U14,whose output will be high when bothinputs are high. The high from U14-4 isconnected to U14-2 and, when U14-1goes high, the output at U14-3 goes highand resets three of the R-S latches thatmake up U16. The transmitter will resetthree times to confirm that a fault hasactually occurred and counter IC U15 willcount each time a high is applied to pin1. After the third fault, the U15 IC willlatch and produce a low at U7-15 thatconnects to the Three Fault LED DS11,causing it to light.If a problem occurs with reflected power,VSWR, a high is connected to J5-7. Thefault high connects to pin 14, the S3 setinput, to one of four quad R-S latchesthat make up U16. The output of thelatch at pin 1 goes high and connects to
10-kW UHF Transmitter with Chapter 4, CircuitFeedforward Drive Descriptions840A, Rev. 0 4-35U3-12, whose output at pin 10 goes high.The high connects to U15-1, the threefault counter IC, and also to U19-8 andU19-9. U19-10 goes high and forwardbiases Q9, whose collector goes low andlights the Fault Indicator LED DS7 on thefront panel. The fault high at J5-7 alsoconnects to the set S1 input at pin 6, toone of four quad R-S latches that makeup U20, and to U11-4. The output of thelatch at U20-9 goes high and is invertedby U18. The low is applied to DS13, theVSWR Fault LED on the board, which willlight. Because the input of U11 at pin 4 ishigh, the output of U11 at pin 1 goeshigh and resets clock IC U9. The Q1 andQ0 outputs of U9 go low during reset,then back to high, and are applied toU14, whose output will be high whenboth inputs are high. The high from U14-4 is connected to U14-2 and, when U14-1 also goes high, the output at U14-3goes high, resetting the three R-S latchesthat make up U16. The transmitter willreset three times to confirm that a faulthas actually occurred and counter IC U15will count each time a high is applied topin 1. After the third fault, the U15 IC willlatch and produce a low at U7-15, whichconnects to the Three Fault LED DS11,causing it to light.If a problem occurs with screen I, a highis connected to J6-1. The fault highconnects to pin 12 of U12, whose outputat pin 11 goes high. The high connects topin 12, the S2 set input of one of fourquad R-S latches that make up U16, andto U11-3. The output of the latch at pin10 goes high and connects to U3-13 andU3-4. The U3-4 high causes the output ofU3 at pin 6 to go high and be inverted byU4. The low output at pin 10 connects toQ4, which turns the transistor off andremoves the High Voltage-On command.With U3-13 high, the output of U3 at pin10 goes high. The high connects to U15-1, the three fault counter, and also toU19-8 and U19-9. U19-10 goes high andforward biases Q9, whose collector goeslow and lights the Fault Indicator LEDDS7 on the front panel. The fault high atJ6-1 also connects to the set S2 input atpin 12 and to one of four quad R-Slatches that make up U20. U20-10 goeshigh and is inverted by U18 and appliedto DS14, the Screen I Fault LED on theBoard, causing it to light.Because of the high on its input at U11-3, the output of U11 at pin 1 goes highand resets clock IC U9. The Q1 and Q0outputs of U9 go low during reset, thenback to high, and are applied to U14,whose output will be high when bothinputs are high. The high is connected toU14-2 and, when U14-1 goes high, theoutput at U14-3 also goes high andresets the three R-S latches that makeup U16. The transmitter will reset threetimes to confirm that a fault has actuallyoccurred and counter IC U15 will counteach time a high is applied to pin 1. Afterthe third fault, the U15 IC will latch. Itproduces a low at U7-15 and connects tothe Three Fault LED DS11, causing it tolight.If a problem occurs with cathode I, a lowis connected to J6-6. The fault low isinverted to a high by U18 and thenconnects to pin 13 of U12, whose outputat pin 11 goes high. The high connects topin 12, the S2 set input of one of fourquad R-S latches that make up U16, andto U11-3. The output of the latch at pin10 goes high and connects to U3-13 andto U3-4. When U3-4 is high, it causes theoutput of U3 at pin 6 to go high and beinverted by U4. The low output at pin 10connects to Q4; this turns the transistoroff and removes the High Voltage-Oncommand. A high on U3-13 causes theoutput at pin 10 to go high. The highconnects to U15-1, the three faultcounter, and to U19-8 and U19-9. U19-10 goes high and forward biases Q9,whose collector goes low and lights theFault Indicator LED DS7 on the frontpanel.The fault high from U18 connects to theset S0 input at pin 4 and to one of fourquad R-S latches that make up U20.U20-2 goes high and is inverted by U18;
10-kW UHF Transmitter with Chapter 4, CircuitFeedforward Drive Descriptions840A, Rev. 0 4-36this is applied to DS15, the Cathode IFault LED on the board, causing it tolight. Because of the high on its input atU11-3, the output of U11 at pin 1 goeshigh and resets clock IC U9. The Q1 andQ0 outputs of U9 go low during reset,then back to high, and are applied toU14, whose output will be high whenboth inputs are high. The high isconnected to U14-2 and, when U14-1goes high, the output at U14-3 also goeshigh and resets the three R-S latchesthat make up U16. The transmitter willreset three times, to confirm that a faulthas actually occurred, and counter ICU15 will count each time a high is appliedto pin 1. After the third fault, the U15 ICwill latch and produce a low at U7-15that connects to the Three Fault LEDDS11, causing it to light.After the problem that caused the fault iscorrected, the fault circuit is reset byswitching the front panel-mounted resetswitch S9. This places a low at J6-9 onthe board that is inverted by U18. Thehigh is connected to pin 7, the R1 resetinput of one of four quad R-S latches thatmake up U16, and to U12-8. The high atpin 7 of U16 resets the temperature faultcircuit. The high at U12-8 causes theoutput of U12 at pin 10 to go high andconnects to the reset input at pin 7 ofU15. U15 then resets the front panel-mounted fault indicator and the faultcircuits associated with U16. The three-fault indicator and the other faultindicators that are lit on the board arereset by switching S1.The +12 VDC needed for the operation ofthe board enters at jack J1, pin 1. C1, C2and C3, and L1 are for the filtering andisolation of the +12 VDC before it isapplied to the rest of the board.4.2.5.2 Transmitter Control Board (1137-1003; Appendix B)The transmitter control board in themetering control panel provides thesystem control functions for thetransmitter. The board supplies theinterlock to the exciter tray and alsoprovides the outputs to the functionindicator LEDs on the front panel of themetering control panel. The transmittercontrol board will switch the transmitterto Standby upon the loss of the videoinput from the modulator or from thereceiver tray, if present, when thetransmitter is in Automatic.When the Operate/Standby switch on thefront panel of the metering control panelis switched to Operate (J11-8 low), andthe Normal/Exciter Test switch is inNormal (K4 energized), K3 energizes andapplies a low to inverter U8F, causing itsoutput to go high. The low from K3 alsobiases off Q23 and Q24; this removes theStandby commands. The high output ofU8F, at pin 15, forward biases Q18 toQ22 and applies the Operate commandsto the control logic board. The low is alsoapplied through diode CR12 to pin 11 ofinverter U8E, causing its output to gohigh. The high forward biases Q26 andQ27; this causes the drains to go low andlights DS14, the front panel Normal LEDconnected to J14, pins 8 and 6. The highoutput of U8E also connects to pin 5, theinput to inverter U8B, causing the outputat pin 4 to go low. The low is applied toQ28 to Q33, biasing them off andremoving the exciter test functions.When the Operate/Standby switch on thefront panel of the metering control panelis switched to Standby (J11-2 low), andthe Normal/Exciter Test switch is inNormal (K4 energized), K3 de-energizesand applies a high to inverter U8F, pin14, and also to Q23 and Q24. As a result,Q23 and Q24 are forward biased; thisproduces a low at J12, pin 3, and lightsDS2, the front panel-mounted StandbyLED. The high on inverter U8F, pin 14,causes the output at pin 15 to go low.The low reverse biases Q18 to Q22 andremoves the Operate commands to thecontrol logic board and the amplifiertrays. The high from K3 is also applied todiode CR12, causing it to reverse bias.
10-kW UHF Transmitter with Chapter 4, CircuitFeedforward Drive Descriptions840A, Rev. 0 4-37When the Exciter Test switch is inNormal, with K4 energized, it applies alow to CR13 and then to inverter U8E,pin 11, whose output at pin 12 then goeshigh. The high also forward biases Q26and Q27 and lights DS14, the frontpanel-mounted Normal LED connected toJ14, pins 8 and 6. The high input toinverter U8B, pin 5, causes the output atpin 4 to go low. The low is applied to Q28to Q33, biasing them off and removingthe exciter test functions.The exciter can be operated withoutusing the 10-kW amplifier by switchingthe Normal/Exciter Test switch on thefront panel of the metering control panelto the Exciter Test position. With theswitch in this position, K4 is de-energizedand a high is applied to diode CR13,causing it to reverse bias. The high fromK4 is also applied to Q25, which forwardbiases it and produces a low at pin 4 ofthe K3 relay. The low at pin 4 de-energizes the relay and produces a highthat is applied to diode CR12, causing itto reverse bias. Both CR12 and CR13 arereverse biased; as a result, a high from+12 VDC and R61 is applied to pin 11 ofU8E and causes its output at pin 12 to golow. The low connects to Q26 and Q27and biases them off. The low is alsoapplied to inverter U8B, pin 5, whoseoutput at pin 4 goes high. The highconnects to Q28 to Q33, forward biasesthem, applies a low to the exciter tray,lights the Exciter Test LED, and sets upthe exciter to operate without the needfor the 10-kW amplifier.The Auto/Manual Test switch S6 on thefront panel controls K1, the magneticlatching relay, by connecting a low inputto the board at J2, pins 7 and 8, forManual or to J2, pins 4 and 3, forAutomatic. When the Test switch ismoved to the Auto position, a low isapplied to K1, pin 6, that energizes therelay and applies a low to U7F, pin 14,causing its output to go high. The high isapplied to Q5 and Q7, forward biasingthem, and produces a low at their drain.The low lights the front panel AutomaticLED. With the Test switch in the Manualposition, a low is applied to K1, pin 4;this de-energizes the relay and connectsa high from K1, pin 2, to Q6, forwardbiasing it and producing a low at itsdrain. The low lights the front panel-mounted Manual LED DS4. The highoutput of K1 is also applied to U7F, pin14, whose output goes low. The low isapplied to Q5 and Q7, which reversebiases them, and extinguishes the frontpanel Automatic LED.The board also supplies the option thatallows for the automatic switching of thetransmitter between a receiver tray or amodulator tray that is used as the inputtray based on the presence of video tothe modulator or the receiver tray. Areceiver tray, a modulator tray, and an IFrelay, to switch between the two outputs,must be present in the transmitter forthe automatic switching to take place.For automatic switching, jumper W2 onJ17 must be in Auto, between pins 1 and2. Jumper W1 on J18 determines whichtray will be in control. The modulator traywill be in control if W1 is between pins 1and 2.If a modulator and a receiver tray are inplace, the jumpers are set as statedabove, and the video input to themodulator is present, a high will bepresent at J2, pin 11. The high connectsto inverter U7B, pin 5, whose output atpin 4 goes low. The low turns off the redVideo Fault LED DS3. The high alsoconnects to timer U1A, pin 5, and directlyto NOR gate U5C, pin 9. The high at theNOR gate produces a low output at U5C,pin 10; this low is applied throughjumper W1 on J18 and jumper W2 on J17to the bases of Q8 to Q11. Q8 to Q11 arereversed biased and apply the disables tothe IF relay to keep the output of themodulator tray connected to the input ofthe upconverter tray. In addition,because Q11 is biased off, Q12 to Q14will have highs applied to their bases tobias them on. DS5, the green ModulatorOn LED, will be lit.
10-kW UHF Transmitter with Chapter 4, CircuitFeedforward Drive Descriptions840A, Rev. 0 4-38If the video input to the modulator isremoved, a video fault low is applied toJ2, pin 11. The low connects to inverterU7B, pin 5, whose output at pin 4 goeshigh. The high lights the red Video FaultLED DS3. The low connects to timer U1A,pin 5, and also connects directly to NORgate U5C, pin 9. After 5 seconds, enoughtime for the loss of video to bedetermined as permanent, the output ofU1A at pin 8 will go low; the low isapplied to U5C, pin 8. With U5C pins 8and 9 both low, the output of U5C at pin10 will go high. The high is appliedthrough jumper W1 on J18 and jumperW2 on J17 to the bases of Q8 to Q11. Q8to Q11 are forward biased and apply thelow enables to the IF relay to connect theoutput of the receiver tray to the input ofthe upconverter tray and also to thegreen Receiver On LED DS4 and theexternal Receiver On LED.During normal operation, there is novideo fault input from the exciter trayand there is a high at J16, pin 1. Thehigh is applied to inverter U7C, pin 7,whose output at pin 6 goes low andextinguishes the red Video Fault LEDDS2. The high is also applied to AND gateU6B, pin 6. Pin 5 of U6B will be a highduring normal operation. A high on pins 5and 6 of U6B produces a high output atpin 4. The high is applied immediately topin 6 of NOR gate U5B and to pin 11 ofcounter U1B. After approximately 6seconds, enough time to determine thata genuine fault has occurred, a high isapplied to pin 5 of U5B. The high on pin 5and pin 6 of U5B produces a low on pin4. The low is applied to NOR gate U5D,pin 12, and, if the Automatic/Manualswitch is in Auto, a low will also be onU5D, pin 13. Lows on pins 12 and 13 ofU5D will cause the output at pin 11 to gohigh and forward bias Q2. The drain ofQ2 will go low and is applied to J11, pin8, and then to Operate/Standby relay K3.The relay stays energized and inOperate. The low from pin 4 of U5B isalso fed through inverter U7E, whoseoutput at pin 12 is now high. The highconnects to NOR gate U5A, pin 2. Ifeither pin 1 or 2, or both pin 1 and 2, arehigh, a low is produced at the output ofU5A, pin 3. The low reverse biases Q3and removes the low from the drain andfrom J4, pin 4.If a video fault from the exciter trayoccurs due to the loss of video, J16, pin1, goes low. This low is applied toinverter U7C, pin 7, whose output at pin6 goes high and lights the red Video FaultLED DS2. The low video fault is alsoapplied to AND gate U6B, pin 6. The levelof the ALC voltage from the receiver trayis fed through op-amp U3D and producesa high output as long as the ALC levelfrom the receiver tray is above thereference set by R3. This normally highoutput from U3D connects to pin 5 ofAND gate U6B.If the ALC level drops below thethreshold set by R3, pin 5 of U6B will golow. A low on pin 5 or pin 6, or both pin 5and pin 6, will produce a low on U6B, pin4. The low is applied immediately to pin 6of NOR gate U5B and to pin 11 of counterU1B. After approximately 6 seconds,enough time to determine that a genuinefault has occurred, the low is applied topin 5 of U5B. The low on pin 5 and pin 6of NOR gate U5B produces a high outputon pin 4. The high is applied to NOR gateU5D, pin 12, and causes the output atpin 11 to go low and reverse bias Q2.The drain of Q2 will go high and the highis applied to J11, pin 8, and then to theOperate/Standby relay K3. The high frompin 4 of U5B is also fed through inverterU7E whose output at pin 12 is now low.The low connects to NOR gate U5A, pin2. If the Auto/Manual switch is in Auto,U5A, pin 1, will be low. When pins 1 and2 on U5A are both low, it produces a highat pin 3 that forward biases Q3. Thedrain of Q3 goes low and is applied toJ11, pin 2, and then to the Operate/Standby switch, which switches thetransmitter to Standby. If theAuto/Manual switch is in Manual, U5A,pin 1, will be high and the output of U5Aat pin 3 will be low; this does not affectthe operation of the transmitter.
10-kW UHF Transmitter with Chapter 4, CircuitFeedforward Drive Descriptions840A, Rev. 0 4-39A forward power sample of the RF outputof the transmitter is connected to J15,pin 7, of the board. The sample connectsto op-amp U3A, pin 3. If the inputsample level stays above the level set byR38, the output of U3A at pin 1 will behigh. The high forward biases Q15 andQ16 and causes their drains to go low.J14, pin 2, is low and connects to thefront panel RF Present LED DS21,causing it to light.A reflected power sample of the RFoutput of the transmitter is connected toJ15, pin 1, of the board. The sampleconnects to op-amp U3C, pin 10. If theinput sample level increases above thelevel set by R44, the output of U3C at pin8 will go high. The high is fed out of theboard at J16, pins 10 and 9, to the 3-watt tray. This cuts back the output ofthe tray and, in turn, the output power ofthe transmitter. The high is also fed tothe base of Q17 and forward biases thetransistor to produce a low at J16, pin 7.The low connects to the front panelVSWR Cutback LED DS23 and causes itto light.The +12 VDC needed for the operation ofthe board enters the board at jack J1, pin3. C18 and L1 are for the filtering andisolation of the +12 VDC before it isapplied to the rest of the board.4.2.5.3 (A2) Differential Buffer Board(1008-1017; Appendix B)The (A2) differential buffer board (1008-1017) takes the sample voltage readingsfrom the external power supplies andprovides readings to the voltage panelmeter and the metering control panelinterface for remote monitoring. Thedifferential buffer board also suppliesscreen-on sense and filament-on sensereadings to (A4) the fault sensing board,diacrode. The fault sensing board,inverting, supplies the high voltage-onsense, the screen-on sense, the filament-on sense, and the filament under-voltagereadings to the control logic board. Inaddition, the differential buffer boardsupplies a bias-on sense to (A5) the faultsensing board.The (A3) differential buffer board (1008-1017) takes the sample current readingsfrom the external power supplies andprovides readings to the current panelmeter and the metering control panelinterface for remote monitoring.The (A3) differential buffer board alsosupplies screen current and grid currentreadings to (A6) the fault sensing board,dual polarity. The fault sensing board,dual polarity, supplies the screen currentand grid current fault readings to thecontrol logic board. The (A3) differentialbuffer board supplies cathode-on sensereadings to (A5) the fault sensing board,inverting. The fault sensing board,inverting, supplies the cathode currentfault readings to the control logic board.4.2.5.4 Fault Sense Board, Diacrode(1293-1307; Appendix B)The fault sense board, diacrode, providesan inverted output for a sample input.All the circuits on the board are thesame. A filament-on sense sample isapplied to J1-8 of the board. This high,which indicates that the filament isoperating, is fed to comparator IC U1,pin 9, and is compared to a referencelevel set by R18. If the sample filamentvoltage level is greater than thisreference level, a high output from U1,pin 14, is connected to U2, pin 7, aninverting amplifier. The high is invertedto a low at U2, pin 6. The low output ofthe board at J4, pin 8, is connected tothe control logic board where it providesthe low filament-on sense to theautomatic on/off sequence. If the sampleinput is less than the reference set by thepot, a low output from U1, pin 14, isconnected to U2, pin 7, which is aninverting amplifier. The low is inverted toa high at U2, pin 6. The high output ofthe board at J4, pin 8, is connected tothe control logic board. The control logic
10-kW UHF Transmitter with Chapter 4, CircuitFeedforward Drive Descriptions840A, Rev. 0 4-40board removes the filament-on sense tothe automatic on/off sequence.The fault sense board is supplied by a+12VDC source at J3-3. The capacitorsC1 and C2 provide filtering.4.2.5.5 Inverting Fault Sense Board(1016-1401; Appendix B)The inverting fault sense board providesan inverted output for a sample input,generally from the differential bufferboard.For example, a filament-on sense sampleis applied to J1-8 of the board. This high,which indicates that the filament isoperating, is fed to comparator IC U1,pin 9, and compared to a reference levelset by R18. If the sample filamentvoltage level is greater than thisreference level, a high output from U1,pin 14, is connected to U2, pin 7, whichis an inverting amplifier. The high isinverted to a low at U2, pin 6. The lowoutput of the board at J4, pin 8, isconnected to the control logic boardwhere it provides the low filament-onsense to the automatic on/off sequence.If the sample input is less than thereference set by the pot, a low outputfrom U1, pin 14, is connected to U2, pin7, the inverting amplifier. The low isinverted to a high at U2, pin 6. The highoutput of the board at J4, pin 8, isconnected to the control logic board. Thecontrol logic board removes the filament-on sense to the automatic on/offsequence.The other inputs to the board arehandled in the same way.4.2.5.6 Dual Polarity Fault Sensing Board(1016-1402; Appendix B)The dual polarity fault sensing boardprovides a high-fault output or a low-normal output at J2-5 or J2-4 that istypically connected to the control logicboard. When this board is used in the 10-kW amplifier, J4-1 is jumpered to J4-4and J1-3 is jumpered to J1-6. Thejumpering provides an upper and lowerlimit circuit for the two current sampleinputs.A sample of the screen current is appliedto J4-2 on the board. From J4-2, thescreen current sample is connected tocomparator U1, pin 5. R6 sets the upperlimit trip point for this section of the IC.If the screen current remains below thisreference level, U1, pin 2, will go low andthe low is applied to NAND gate U2, pins1 and 2. U2, pin 3, will go high and thehigh is applied to NAND gate U2, pin 5.Because J4-1 is jumpered to J4-4, theinput sample of the screen current is alsoapplied to U1, pin 7. R12 sets the lowerlimit trip point for this section of the IC.If the screen current remains above thisreference level, U1, pin 1, will go highand the high is applied to NAND gate U2,pin 6. U2, pin 5, is high and U2, pin 6, isalso high during normal operation; thiscauses NAND gate U2, pin 4, to be low.During normal operation, there is a lowoutput on the board at J2, pin 5.If the screen current sample applied tocomparator U1, pin 5, increases abovethe upper limit trip point set by R6, U1,pin 2, will go high. The high is applied toNAND gate U2, pins 1 and 2. U2, pin 3,will go low and the low is applied toNAND gate U2, pin 5. Because J4-1 isjumpered to J4-4, the input sample ofthe screen current is also applied to U1,pin 7. R12 sets the lower limit trip pointfor this section of the IC. If the screencurrent remains above this referencelevel, U1, pin 1, will go high and the highis applied to NAND gate U2, pin 6. U2,pin 5, is now low and U2, pin 6, is high;this causes NAND gate U2, pin 4, to behigh. A high output of the board at J2,pin 5, is a screen current fault condition.The screen current sample is applied toJ4-2 of the board and jumpered to J4-4.From J4-2, the current sample isconnected to comparator U1, pin 5. R6sets the upper limit trip point for thissection of the IC. If the screen current
10-kW UHF Transmitter with Chapter 4, CircuitFeedforward Drive Descriptions840A, Rev. 0 4-41remains below this reference level, U1,pin 2, will go low and the low is appliedto NAND gate U2, pins 1 and 2. U2, pin3, will go high and the high is applied toNAND gate U2, pin 5. Because J4-1 isjumpered to J4-4, the input sample ofthe low screen current is also applied toU1, pin 7. R12 sets the lower limit trippoint for this section of the IC. If thescreen current decreases below thisreference level, U1, pin 1, will go low andthe low is applied to NAND gate U2, pin6. At this point, U2, pin 5, is high and U2,pin 6, is low, causing NAND gate U2, pin4, to be high. A high output from theboard at J2, pin 5, is a screen currentfault condition.A sample of the grid current is applied toJ1-4 of the board. From J1-4, the currentsample is connected to comparator U1,pin 9. R18 sets the upper limit trip pointfor this section of the IC. If the gridcurrent remains below this referencelevel, U1, pin 14, will go low and the lowis applied to NAND gate U2, pins 8 and 9.U2, pin 10, will go high and the high isapplied to NAND gate U2, pin 12.Because J1-3 is jumpered to J1-6, theinput sample of the grid current is alsoapplied to U1, pin 11. R25 sets the lowerlimit trip point for this section of the IC.If the grid current remains above thisreference level, U1, pin 13, will go highand the high is applied to NAND gate U2,pin 13. During normal operation, U2, pin12, and U2, pin 13, are both high. Thiscauses NAND gate U2, pin 11, to be low.A low output from the board at J2, pin 4,occurs during normal operation.If the grid current sample applied tocomparator U1, pin 9, increases abovethe upper limit trip point set by R18, U1,pin 14, will go high. The high is appliedto NAND gate U2, pins 8 and 9. U2, pin10, will go low and the low is applied toNAND gate U2, pin 12. Because J1-3 isjumpered to J1-6, the input sample ofthe grid current is also applied to U1, pin11. R25 sets the lower limit trip point forthis section of the IC. If the grid currentremains above this reference level, U1,pin 13, will go high and the high isapplied to NAND gate U2, pin 13. U2, pin12, is now low and U2, pin 13, is high;this causes NAND gate U2, pin 11, to behigh. A high output from the board at J2,pin 4, is a grid current fault condition.The grid current sample is applied to J1-4on the board and jumpered to J1-7. FromJ1-4, the current sample is connected tocomparator U1, pin 9. R18 sets the upperlimit trip point for this section of the IC.If the grid current remains below thisreference level, U1, pin 14, will go lowand the low is applied to NAND gate U2,pins 8 and 9. U2, pin 10, will go high andthe high is applied to NAND gate U2, pin12. Because J1-3 is jumpered to J1-6,the input sample of the low grid currentis also applied to U1, pin 11. R25 sets thelower limit trip point for this section ofthe IC. If the grid current decreasesbelow this reference level, U1, pin 13,will go low and the low is applied toNAND gate U2, pin 13. At this point, U2,pin 12, is high and U2, pin 13, is low,causing NAND gate U2, pin 11, to behigh. A high output from the board at J2,pin 4, is a grid current fault condition.4.3 (A3) High-Voltage Power SupplyAssembly, 208/240 VAC (1068022;Appendix A)4.3.1 Current Metering Board (1084-1205; Appendix B)The current metering board takes avoltage sample from an operating powersupply and provides an output level thatcan be used in a current metering circuit.The sample voltage input is applied at J1,pins 1 and 3, and is fed to a pi-attenuator network consisting of R1, R2,R3, and R4. The value of R1 can bechanged to increase or lower the value ofthe input voltage for the desired currentmeter reading. R3 can be adjusted tocalibrate the output level and display anaccurate meter reading of the currentvalue.
10-kW UHF Transmitter with Chapter 4, CircuitFeedforward Drive Descriptions840A, Rev. 0 4-42VR1 and VR2 are back-to-back 10 VDCzener diodes that protect the externalmetering circuits from a high-voltageproblem by shunting out the highervoltage and allowing only a maximum of±10 VDC to be present at the output.C1 is an AC bypass capacitor for thereduction of any AC ripple at the output.The external current metering circuitconnects to J2, pins 1 and 3.4.3.2 (A10 and A11) Power SupplyMetering Boards (1084-1213 and1016-1028; Appendix B)The power supply metering board takes avoltage sample from an operating powersupply and provides an output level thatis used in a metering circuit.The sample voltage input is applied at J1,pins 1 and 3, and is fed to a pi-attenuator network consisting of R1, R2,R3, and R4. The value of R1 can bechanged to increase or lower the value ofthe input voltage for the chosen outputmeter reading. R3 can be adjusted tocalibrate the output level to allow anaccurate meter reading of the value to bedisplayed.VR1 and VR2 are back-to-back 10-VDCzener diodes that protect the externalmetering circuits from a high-voltageproblem by shunting out the highervoltage and allowing only a maximum of±10 VDC to be present at the output.C1 is an AC bypass capacitor for thereduction of any AC ripple at the output.The external metering circuit connects toJ2, pins 1 and 3.4.3.3 (A5, A6, and A7) High-VoltageRectifier Board (1293-1101;Appendix B)The high-voltage rectifier board providesa full-wave rectifier for the AC input. Atotal of three high-voltage rectifierboards are used with a three-phase ACinput: one for each of the three 2.6 kVACoutput legs of the high-voltagetransformer.The high-voltage rectifier board has a 4-amp fuse mounted at the (E1) AC inputto protect the board from surges orspikes on the AC input line. The input ACis applied to two rows of diodes: one forpositive and one for negativerectification. Each row contains 17 diodesin series that provide for peak inversehi gh-voltage protection. Each diode has a1 MW/½-W resistor and a .001 mF/3-kVcapacitor, mounted in parallel, thatcreates equal distribution of the voltageacross each diode.The positive leg of diodes connects to theE2 (+) terminal. The negative leg ofdiodes connects to the E3 (-) terminal.The positive and negative outputs of onehigh-voltage rectifier board connects tothe positive and negative outputs of theother two high-voltage rectifier boards.

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