iRobot ALT240ROB Floor Cleaning, Mopping Robot User Manual Chipset Datasheet

iRobot Corporation Floor Cleaning, Mopping Robot Chipset Datasheet

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Chipset Datasheet

CC2541www.ti.comSWRS110D –JANUARY 2012–REVISED JUNE 20132.4-GHz Bluetooth™ low energy and Proprietary System-on-ChipCheck for Samples: CC25411FEATURES23• RF – High-Performance and Low-Power 8051Microcontroller Core With Code Prefetch– 2.4-GHz Bluetooth low energy Compliantand Proprietary RF System-on-Chip – In-System-Programmable Flash, 128- or256-KB– Supports 250-kbps, 500-kbps, 1-Mbps, 2-Mbps Data Rates – 8-KB RAM With Retention in All PowerModes– Excellent Link Budget, Enabling Long-Range Applications Without External Front – Hardware Debug SupportEnd – Extensive Baseband Automation, Including– Programmable Output Power up to 0 dBm Auto-Acknowledgment and AddressDecoding– Excellent Receiver Sensitivity (–94 dBm at1 Mbps), Selectivity, and Blocking – Retention of All Relevant Registers in AllPerformance Power Modes– Suitable for Systems Targeting Compliance • PeripheralsWith Worldwide Radio Frequency – Powerful Five-Channel DMARegulations: ETSI EN 300 328 and EN 300 – General-Purpose Timers (One 16-Bit, Two440 Class 2 (Europe), FCC CFR47 Part 15 8-Bit)(US), and ARIB STD-T66 (Japan) – IR Generation Circuitry• Layout – 32-kHz Sleep Timer With Capture– Few External Components – Accurate Digital RSSI Support– Reference Design Provided – Battery Monitor and Temperature Sensor– 6-mm × 6-mm QFN-40 Package – 12-Bit ADC With Eight Channels and– Pin-Compatible With CC2540 (When Not Configurable ResolutionUsing USB or I2C) – AES Security Coprocessor• Low Power – Two Powerful USARTs With Support for– Active-Mode RX Down to: 17.9 mA Several Serial Protocols– Active-Mode TX (0 dBm): 18.2 mA – 23 General-Purpose I/O Pins– Power Mode 1 (4-µs Wake-Up): 270 µA (21 × 4 mA, 2 × 20 mA)– Power Mode 2 (Sleep Timer On): 1 µA – I2C interface– Power Mode 3 (External Interrupts): 0.5 µA – 2 I/O Pins Have LED Driving Capabilities– Wide Supply-Voltage Range (2 V–3.6 V) – Watchdog Timer•TPS62730 Compatible Low Power in Active – Integrated High-Performance ComparatorMode • Development Tools– RX Down to: 14.7 mA (3-V supply) – CC2541 Evaluation Module Kit– TX (0 dBm): 14.3 mA (3-V supply) (CC2541EMK)White space – CC2541 Mini Development Kit (CC2541DK-White space MINI)White space – SmartRF™ SoftwareWhite space – IAR Embedded Workbench™ AvailableWhite spaceWhite space• Microcontroller1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.2Bluetooth is a trademark of Bluetooth SIG, Inc..3ZigBee is a registered trademark of ZigBee Alliance.PRODUCTION DATA information is current as of publication date. Copyright © 2012–2013, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
CC2541SWRS110D –JANUARY 2012–REVISED JUNE 2013www.ti.comSOFTWARE FEATURES CC2541 WITH TPS62730•Bluetooth v4.0 Compliant Protocol Stack for • TPS62730 is a 2-MHz Step-Down ConverterSingle-Mode BLE Solution With Bypass Mode– Complete Power-Optimized Stack, • Extends Battery Lifetime by up to 20%Including Controller and Host • Reduced Current in All Active Modes– GAP – Central, Peripheral, Observer, or • 30-nA Bypass Mode Current to Support Low-Broadcaster (Including Combination Power ModesRoles) • RF Performance Unchanged– ATT / GATT – Client and Server • Small Package Allows for Small Solution Size– SMP – AES-128 Encryption and • CC2541 ControllableDecryption– L2CAP DESCRIPTION– Sample Applications and Profiles The CC2541 is a power-optimized true system-on-chip (SoC) solution for both Bluetooth low energy and– Generic Applications for GAP Central proprietary 2.4-GHz applications. It enables robustand Peripheral Roles network nodes to be built with low total bill-of-material– Proximity, Accelerometer, Simple Keys, costs. The CC2541 combines the excellentand Battery GATT Services performance of a leading RF transceiver with an– More Applications Supported in BLE industry-standard enhanced 8051 MCU, in-systemprogrammable flash memory, 8-KB RAM, and manySoftware Stack other powerful supporting features and peripherals.– Multiple Configuration Options The CC2541 is highly suited for systems where– Single-Chip Configuration, Allowing ultralow power consumption is required. This isApplications to Run on CC2541 specified by various operating modes. Short transitiontimes between operating modes further enable low– Network Processor Interface for power consumption.Applications Running on an ExternalMicrocontroller The CC2541 is pin-compatible with the CC2540 inthe 6-mm × 6-mm QFN40 package, if the USB is not– BTool – Windows PC Application for used on the CC2540 and the I2C/extra I/O is not usedEvaluation, Development, and Test on the CC2541. Compared to the CC2540, theCC2541 provides lower RF current consumption. TheAPPLICATIONS CC2541 does not have the USB interface of the• 2.4-GHz Bluetooth low energy Systems CC2540, and provides lower maximum output powerin TX mode. The CC2541 also adds a HW I2C• Proprietary 2.4-GHz Systems interface.• Human-Interface Devices (Keyboard, Mouse,Remote Control) The CC2541 is pin-compatible with the CC2533RF4CE-optimized IEEE 802.15.4 SoC.• Sports and Leisure EquipmentThe CC2541 comes in two different versions:• Mobile Phone Accessories CC2541F128/F256, with 128 KB and 256 KB of flash• Consumer Electronics memory, respectively.For the CC2541 block diagram, see Figure 1.2Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments IncorporatedProduct Folder Links: CC2541
SFR bus SFR busMEMORYARBITRATOR8051 CPUCOREDMAFLASHSRAMFLASH CTRLDEBUGINTERFACERESETRESET_NP2_4P2_3P2_2P2_1P2_0P1_4P1_3P1_2P1_1P1_0P1_7P1_6P1_5P0_4P0_3P0_2P0_1P0_0P0_7P0_6P0_532.768-kHzCRYSTAL OSC32-MHZCRYSTAL OSCHIGH SPEEDRC-OSC32-kHzRC-OSCCLOCK MUX andCALIBRATIONRAMUSART 0USART 1TIMER 1 (16-Bit)TIMER 3 (8-bit)TIMER 2(BLE LL TIMER)TIMER 4 (8-bit)AESENCRYPTIONandDECRYPTIONWATCHDOG TIMERIRQCTRLFLASHUNIFIEDRF_P RF_NSYNTHMODULATORPOWER-ON RESETBROWN OUTRADIOREGISTERSPOWER MGT. CONTROLLERSLEEP TIMERPDATAXRAMIRAMSFRXOSC_Q2XOSC_Q1DS ADCAUDIO / DCDIGITALANALOGMIXEDVDD (2 V–3.6 V)DCOUPLON-CHIP VOLTAGEREGULATORLink Layer EngineFREQUENCYSYNTHESIZERI2CDEMODULATORRECEIVE TRANSMITOP-ANALOG COMPARATORI/O CONTROLLER1-KB SRAMRadio ArbiterFIFOCTRLSDASCLCC2541www.ti.comSWRS110D –JANUARY 2012–REVISED JUNE 2013This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled withappropriate precautions. Failure to observe proper handling and installation procedures can cause damage.ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be moresusceptible to damage because very small parametric changes could cause the device not to meet its published specifications.Figure 1. Block DiagramCopyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback 3Product Folder Links: CC2541
CC2541SWRS110D –JANUARY 2012–REVISED JUNE 2013www.ti.comABSOLUTE MAXIMUM RATINGS(1)over operating free-air temperature range (unless otherwise noted)MIN MAX UNITSupply voltage All supply pins must have the same voltage –0.3 3.9 VVoltage on any digital pin –0.3 VDD + 0.3 ≤3.9 VInput RF level 10 dBmStorage temperature range –40 125 °CAll pins, excluding pins 25 and 26, according to human-body 2 kVmodel, JEDEC STD 22, method A114All pins, according to human-body model, JEDEC STD 22,ESD(2) 1 kVmethod A114According to charged-device model, JEDEC STD 22, method 500 VC101(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under Recommended OperatingConditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2) CAUTION: ESD sesnsitive device. Precautions should be used when handling the device in order to prevent permanent damage.RECOMMENDED OPERATING CONDITIONSover operating free-air temperature range (unless otherwise noted)MIN NOM MAX UNITOperating ambient temperature range, TA–40 85 °COperating supply voltage 2 3.6 VELECTRICAL CHARACTERISTICSMeasured on Texas Instruments CC2541 EM reference design with TA= 25°C and VDD = 3 V,1 Mbps, GFSK, 250-kHz deviation, Bluetooth low energy mode, and 0.1% BERPARAMETER TEST CONDITIONS MIN TYP MAX UNITRX mode, standard mode, no peripherals active, low MCU 17.9activityRX mode, high-gain mode, no peripherals active, low MCU 20.2activity mATX mode, –20 dBm output power, no peripherals active, low 16.8MCU activityTX mode, 0 dBm output power, no peripherals active, low 18.2MCU activityPower mode 1. Digital regulator on; 16-MHz RCOSC and 32-Icore Core current consumption MHz crystal oscillator off; 32.768-kHz XOSC, POR, BOD and 270sleep timer active; RAM and register retentionPower mode 2. Digital regulator off; 16-MHz RCOSC and 32- µAMHz crystal oscillator off; 32.768-kHz XOSC, POR, and sleep 1timer active; RAM and register retentionPower mode 3. Digital regulator off; no clocks; POR active; 0.5RAM and register retentionLow MCU activity: 32-MHz XOSC running. No radio or 6.7 mAperipherals. Limited flash access, no RAM access.Timer 1. Timer running, 32-MHz XOSC used 90Timer 2. Timer running, 32-MHz XOSC used 90Peripheral current consumption Timer 3. Timer running, 32-MHz XOSC used 60 μAIperi (Adds to core current Icore for each Timer 4. Timer running, 32-MHz XOSC used 70peripheral unit activated)Sleep timer, including 32.753-kHz RCOSC 0.6ADC, when converting 1.2 mA4Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments IncorporatedProduct Folder Links: CC2541
CC2541www.ti.comSWRS110D –JANUARY 2012–REVISED JUNE 2013GENERAL CHARACTERISTICSMeasured on Texas Instruments CC2541 EM reference design with TA= 25°C and VDD = 3 VPARAMETER TEST CONDITIONS MIN TYP MAX UNITWAKE-UP AND TIMINGDigital regulator on, 16-MHz RCOSC and 32-MHz crystalPower mode 1 →Active 4 μsoscillator off. Start-up of 16-MHz RCOSCDigital regulator off, 16-MHz RCOSC and 32-MHz crystalPower mode 2 or 3 →Active 120 μsoscillator off. Start-up of regulator and 16-MHz RCOSCCrystal ESR = 16 Ω. Initially running on 16-MHz RCOSC, 500 μswith 32-MHz XOSC OFFActive →TX or RXWith 32-MHz XOSC initially on 180 μsProprietary auto mode 130RX/TX turnaround μsBLE mode 150RADIO PARTRF frequency range Programmable in 1-MHz steps 2379 2496 MHz2 Mbps, GFSK, 500-kHz deviation2 Mbps, GFSK, 320-kHz deviation1 Mbps, GFSK, 250-kHz deviationData rate and modulation format 1 Mbps, GFSK, 160-kHz deviation500 kbps, MSK250 kbps, GFSK, 160-kHz deviation250 kbps, MSKRF RECEIVE SECTIONMeasured on Texas Instruments CC2541 EM reference design with TA= 25°C, VDD = 3 V, fc= 2440 MHzPARAMETER TEST CONDITIONS MIN TYP MAX UNIT2 Mbps, GFSK, 500-kHz Deviation, 0.1% BERReceiver sensitivity –90 dBmSaturation BER < 0.1% –1 dBmCo-channel rejection Wanted signal at –67 dBm –9 dB±2 MHz offset, 0.1% BER, wanted signal –67 dBm –2In-band blocking rejection ±4 MHz offset, 0.1% BER, wanted signal –67 dBm 36 dB±6 MHz or greater offset, 0.1% BER, wanted signal –67 dBm 41Including both initial tolerance and drift. Sensitivity better than –67dBm,Frequency error tolerance(1) –300 300 kHz250 byte payload. BER 0.1%Symbol rate error Maximum packet length. Sensitivity better than–67dBm, 250 byte –120 120 ppmtolerance(2) payload. BER 0.1%2 Mbps, GFSK, 320-kHz Deviation, 0.1% BERReceiver sensitivity –86 dBmSaturation BER < 0.1% –7 dBmCo-channel rejection Wanted signal at –67 dBm –12 dB±2 MHz offset, 0.1% BER, wanted signal –67 dBm –1In-band blocking rejection ±4 MHz offset, 0.1% BER, wanted signal –67 dBm 34 dB±6 MHz or greater offset, 0.1% BER, wanted signal –67 dBm 39Including both initial tolerance and drift. Sensitivity better than –67 dBm,Frequency error tolerance(1) –300 300 kHz250 byte payload. BER 0.1%Symbol rate error Maximum packet length. Sensitivity better than –67 dBm, 250 byte –120 120 ppmtolerance(2) payload. BER 0.1%(1) Difference between center frequency of the received RF signal and local oscillator frequency(2) Difference between incoming symbol rate and the internally generated symbol rateCopyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback 5Product Folder Links: CC2541
CC2541SWRS110D –JANUARY 2012–REVISED JUNE 2013www.ti.comRF RECEIVE SECTION (continued)Measured on Texas Instruments CC2541 EM reference design with TA= 25°C, VDD = 3 V, fc= 2440 MHzPARAMETER TEST CONDITIONS MIN TYP MAX UNIT1 Mbps, GFSK, 250-kHz Deviation, Bluetooth low energy Mode, 0.1% BERHigh-gain mode –94Receiver sensitivity(3)(4) dBmStandard mode –88Saturation(4) BER < 0.1% 5 dBmCo-channel rejection(4) Wanted signal –67 dBm –6 dB±1 MHz offset, 0.1% BER, wanted signal –67 dBm –2±2 MHz offset, 0.1% BER, wanted signal –67 dBm 26In-band blocking rejection(4) dB±3 MHz offset, 0.1% BER, wanted signal –67 dBm 34>6 MHz offset, 0.1% BER, wanted signal –67 dBm 33Minimum interferer level < 2 GHz (Wanted signal –67 dBm) –21Out-of-band blocking Minimum interferer level [2 GHz, 3 GHz] (Wanted signal –67 dBm) –25 dBmrejection(4)Minimum interferer level > 3 GHz (Wanted signal –67 dBm) –7Intermodulation(4) Minimum interferer level –36 dBmIncluding both initial tolerance and drift. Sensitivity better than -67dBm,Frequency error tolerance(5) –250 250 kHz250 byte payload. BER 0.1%Symbol rate error Maximum packet length. Sensitivity better than –67 dBm, 250 byte –80 80 ppmtolerance(6) payload. BER 0.1%1 Mbps, GFSK, 160-kHz Deviation, 0.1% BERReceiver sensitivity(7) –91 dBmSaturation BER < 0.1% 0 dBmCo-channel rejection Wanted signal 10 dB above sensitivity level –9 dB±1-MHz offset, 0.1% BER, wanted signal –67 dBm 2±2-MHz offset, 0.1% BER, wanted signal –67 dBm 24In-band blocking rejection dB±3-MHz offset, 0.1% BER, wanted signal -–67 dBm 27>6-MHz offset, 0.1% BER, wanted signal –67 dBm 32Including both initial tolerance and drift. Sensitivity better than –67 dBm,Frequency error tolerance(5) –200 200 kHz250-byte payload. BER 0.1%Symbol rate error Maximum packet length. Sensitivity better than –67 dBm, 250-byte –80 80 ppmtolerance(6) payload. BER 0.1%500 kbps, MSK, 0.1% BERReceiver sensitivity(7) –99 dBmSaturation BER < 0.1% 0 dBmCo-channel rejection Wanted signal –67 dBm –5 dB±1-MHz offset, 0.1% BER, wanted signal –67 dBm 20In-band blocking rejection ±2-MHz offset, 0.1% BER, wanted signal –67 dBm 27 dB>2-MHz offset, 0.1% BER, wanted signal –67 dBm 28Including both initial tolerance and drift. Sensitivity better than –67 dBm,Frequency error tolerance –150 150 kHz250-byte payload. BER 0.1%Maximum packet length. Sensitivity better than –67 dBm, 250-byteSymbol rate error tolerance –80 80 ppmpayload. BER 0.1%(3) The receiver sensitivity setting is programmable using a TI BLE stack vendor-specific API command. The default value is standardmode.(4) Results based on standard-gain mode.(5) Difference between center frequency of the received RF signal and local oscillator frequency(6) Difference between incoming symbol rate and the internally generated symbol rate(7) Results based on high-gain mode.6Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments IncorporatedProduct Folder Links: CC2541
CC2541www.ti.comSWRS110D –JANUARY 2012–REVISED JUNE 2013RF RECEIVE SECTION (continued)Measured on Texas Instruments CC2541 EM reference design with TA= 25°C, VDD = 3 V, fc= 2440 MHzPARAMETER TEST CONDITIONS MIN TYP MAX UNIT250 kbps, GFSK, 160 kHz Deviation, 0.1% BERReceiver sensitivity (8) –98 dBmSaturation BER < 0.1% 0 dBmCo-channel rejection Wanted signal -67 dBm –3 dB±1-MHz offset, 0.1% BER, wanted signal –67 dBm 23In-band blocking rejection ±2-MHz offset, 0.1% BER, wanted signal –67 dBm 28 dB>2-MHz offset, 0.1% BER, wanted signal –67 dBm 29Including both initial tolerance and drift. Sensitivity better than –67 dBm,Frequency error tolerance(9) –150 150 kHz250-byte payload. BER 0.1%Symbol rate error Maximum packet length. Sensitivity better than –67 dBm, 250-byte –80 80 ppmtolerance(10) payload. BER 0.1%250 kbps, MSK, 0.1% BERReceiver sensitivity (11) –99 dBmSaturation BER < 0.1% 0 dBmCo-channel rejection Wanted signal -67 dBm –5 dB±1-MHz offset, 0.1% BER, wanted signal –67 dBm 20In-band blocking rejection ±2-MHz offset, 0.1% BER, wanted signal –67 dBm 29 dB>2-MHz offset, 0.1% BER, wanted signal –67 dBm 30Including both initial tolerance and drift. Sensitivity better than –67 dBm,Frequency error tolerance –150 150 kHz250-byte payload. BER 0.1%Maximum packet length. Sensitivity better than –67 dBm, 250-byteSymbol rate error tolerance –80 80 ppmpayload. BER 0.1%ALL RATES/FORMATSSpurious emission in RX. f < 1 GHz –67 dBmConducted measurementSpurious emission in RX. f > 1 GHz –57 dBmConducted measurement(8) Results based on standard-gain mode.(9) Difference between center frequency of the received RF signal and local oscillator frequency(10) Difference between incoming symbol rate and the internally generated symbol rate(11) Results based on high-gain mode.Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback 7Product Folder Links: CC2541
CC2541SWRS110D –JANUARY 2012–REVISED JUNE 2013www.ti.comRF TRANSMIT SECTIONMeasured on Texas Instruments CC2541 EM reference design with TA= 25°C, VDD = 3 V and fc= 2440 MHzPARAMETER TEST CONDITIONS MIN TYP MAX UNITDelivered to a single-ended 50-Ωload through a balun using 0maximum recommended output power settingOutput power dBmDelivered to a single-ended 50-Ωload through a balun using –23minimum recommended output power settingProgrammable output power Delivered to a single-ended 50-Ωload through a balun using 23 dBrange minimum recommended output power settingf < 1 GHz –52 dBmSpurious emission conducted f > 1 GHz –48 dBmmeasurement Suitable for systems targeting compliance with worldwide radio-frequency regulations ETSI EN 300 328 andEN 300 440 Class 2 (Europe), FCC CFR47 Part 15 (US), and ARIB STD-T66 (Japan)Differential impedance as seen from the RF port (RF_P and RF_N)Optimum load impedance 70 +j30 Ωtoward the antennaDesigns with antenna connectors that require conducted ETSI compliance at 64 MHz should insert an LCresonator in front of the antenna connector. Use a 1.6-nH inductor in parallel with a 1.8-pF capacitor. Connectboth from the signal trace to a good RF ground.CURRENT CONSUMPTION WITH TPS62730Measured on Texas Instruments CC2541 TPA62730 EM reference design with TA= 25°C, VDD = 3 V and fc= 2440 MHz,1 Mbsp, GFSK, 250-kHz deviation, Bluetooth™ low energy Mode, 1% BER(1)PARAMETER TEST CONDITIONS MIN TYP MAX UNITRX mode, standard mode, no peripherals active, low MCU activity, MCU 14.7at 1 MHzRX mode, high-gain mode, no peripherals active, low MCU activity, 16.7MCU at 1 MHzCurrent consumption mATX mode, –20 dBm output power, no peripherals active, low MCU activity, 13.1MCU at 1 MHzTX mode, 0 dBm output power, no peripherals active, low MCU activity, 14.3MCU at 1 MHz(1) 0.1% BER maps to 30.8% PER32-MHz CRYSTAL OSCILLATORMeasured on Texas Instruments CC2541 EM reference design with TA= 25°C and VDD = 3 VPARAMETER TEST CONDITIONS MIN TYP MAX UNITCrystal frequency 32 MHzCrystal frequency accuracy –40 40 ppmrequirement(1)ESR Equivalent series resistance 6 60 ΩC0Crystal shunt capacitance 1 7 pFCLCrystal load capacitance 10 16 pFStart-up time 0.25 msThe crystal oscillator must be in power down for a guardtime before it is used again. This requirement is valid forPower-down guard time 3 msall modes of operation. The need for power-down guardtime can vary with crystal type and load.(1) Including aging and temperature dependency, as specified by [1]8Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments IncorporatedProduct Folder Links: CC2541
CC2541www.ti.comSWRS110D –JANUARY 2012–REVISED JUNE 201332.768-kHz CRYSTAL OSCILLATORMeasured on Texas Instruments CC2541 EM reference design with TA= 25°C and VDD = 3 VPARAMETER TEST CONDITIONS MIN TYP MAX UNITCrystal frequency 32.768 kHzCrystal frequency accuracy requirement(1) –40 40 ppmESR Equivalent series resistance 40 130 kΩC0Crystal shunt capacitance 0.9 2 pFCLCrystal load capacitance 12 16 pFStart-up time 0.4 s(1) Including aging and temperature dependency, as specified by [1]32-kHz RC OSCILLATORMeasured on Texas Instruments CC2541 EM reference design with TA= 25°C and VDD = 3 V.PARAMETER TEST CONDITIONS MIN TYP MAX UNITCalibrated frequency(1) 32.753 kHzFrequency accuracy after calibration ±0.2%Temperature coefficient(2) 0.4 %/°CSupply-voltage coefficient(3) 3 %/VCalibration time(4) 2 ms(1) The calibrated 32-kHz RC oscillator frequency is the 32-MHz XTAL frequency divided by 977.(2) Frequency drift when temperature changes after calibration(3) Frequency drift when supply voltage changes after calibration(4) When the 32-kHz RC oscillator is enabled, it is calibrated when a switch from the 16-MHz RC oscillator to the 32-MHz crystal oscillatoris performed while SLEEPCMD.OSC32K_CALDIS is set to 0.16-MHz RC OSCILLATORMeasured on Texas Instruments CC2541 EM reference design with TA= 25°C and VDD = 3 VPARAMETER TEST CONDITIONS MIN TYP MAX UNITFrequency(1) 16 MHzUncalibrated frequency accuracy ±18%Calibrated frequency accuracy ±0.6%Start-up time 10 μsInitial calibration time(2) 50 μs(1) The calibrated 16-MHz RC oscillator frequency is the 32-MHz XTAL frequency divided by 2.(2) When the 16-MHz RC oscillator is enabled, it is calibrated when a switch from the 16-MHz RC oscillator to the 32-MHz crystal oscillatoris performed while SLEEPCMD.OSC_PD is set to 0.Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback 9Product Folder Links: CC2541
CC2541SWRS110D –JANUARY 2012–REVISED JUNE 2013www.ti.comRSSI CHARACTERISTICSMeasured on Texas Instruments CC2541 EM reference design with TA= 25°C and VDD = 3 VPARAMETER TEST CONDITIONS MIN TYP MAX UNIT2 Mbps, GFSK, 320-kHz Deviation, 0.1% BER and 2 Mbps, GFSK, 500-kHz Deviation, 0.1% BERReduced gain by AGC algorithm 64Useful RSSI range(1) dBHigh gain by AGC algorithm 64Reduced gain by AGC algorithm 79RSSI offset(1) dBmHigh gain by AGC algorithm 99Absolute uncalibrated accuracy(1) ±6 dBStep size (LSB value) 1 dBAll Other Rates/FormatsStandard mode 64Useful RSSI range(1) dBHigh-gain mode 64Standard mode 98RSSI offset(1) dBmHigh-gain mode 107Absolute uncalibrated accuracy(1) ±3 dBStep size (LSB value) 1 dB(1) Assuming CC2541 EM reference design. Other RF designs give an offset from the reported value.FREQUENCY SYNTHESIZER CHARACTERISTICSMeasured on Texas Instruments CC2541 EM reference design with TA= 25°C, VDD = 3 V and fc= 2440 MHzPARAMETER TEST CONDITIONS MIN TYP MAX UNITAt ±1-MHz offset from carrier –109Phase noise, unmodulated carrier At ±3-MHz offset from carrier –112 dBc/HzAt ±5-MHz offset from carrier –119ANALOG TEMPERATURE SENSORMeasured on Texas Instruments CC2541 EM reference design with TA= 25°C and VDD = 3 VPARAMETER TEST CONDITIONS MIN TYP MAX UNITOutput 1480 12-bitTemperature coefficient 4.5 / 1°CVoltage coefficient 1 0.1 VMeasured using integrated ADC, internal band-gap voltagereference, and maximum resolutionInitial accuracy without calibration ±10 °CAccuracy using 1-point calibration ±5 °CCurrent consumption when enabled 0.5 mACOMPARATOR CHARACTERISTICSTA= 25°C, VDD = 3 V. All measurement results are obtained using the CC2541 reference designs, post-calibration.PARAMETER TEST CONDITIONS MIN TYP MAX UNITCommon-mode maximum voltage VDD VCommon-mode minimum voltage –0.3Input offset voltage 1 mVOffset vs temperature 16 µV/°COffset vs operating voltage 4 mV/VSupply current 230 nAHysteresis 0.15 mV10 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments IncorporatedProduct Folder Links: CC2541
CC2541www.ti.comSWRS110D –JANUARY 2012–REVISED JUNE 2013ADC CHARACTERISTICSTA= 25°C and VDD = 3 VPARAMETER TEST CONDITIONS MIN TYP MAX UNITInput voltage VDD is voltage on AVDD5 pin 0 VDD VExternal reference voltage VDD is voltage on AVDD5 pin 0 VDD VExternal reference voltage differential VDD is voltage on AVDD5 pin 0 VDD VInput resistance, signal Simulated using 4-MHz clock speed 197 kΩFull-scale signal(1) Peak-to-peak, defines 0 dBFS 2.97 VSingle-ended input, 7-bit setting 5.7Single-ended input, 9-bit setting 7.5Single-ended input, 10-bit setting 9.3Single-ended input, 12-bit setting 10.3Differential input, 7-bit setting 6.5ENOB(1) Effective number of bits bitsDifferential input, 9-bit setting 8.3Differential input, 10-bit setting 10Differential input, 12-bit setting 11.510-bit setting, clocked by RCOSC 9.712-bit setting, clocked by RCOSC 10.9Useful power bandwidth 7-bit setting, both single and differential 0–20 kHzSingle ended input, 12-bit setting, –6 dBFS(1) –75.2THD Total harmonic distortion dBDifferential input, 12-bit setting, –6 dBFS(1) –86.6Single-ended input, 12-bit setting(1) 70.2Differential input, 12-bit setting(1) 79.3Signal to nonharmonic ratio dBSingle-ended input, 12-bit setting, –6 dBFS(1) 78.8Differential input, 12-bit setting, –6 dBFS(1) 88.9Differential input, 12-bit setting, 1-kHz sineCMRR Common-mode rejection ratio >84 dB(0 dBFS), limited by ADC resolutionSingle ended input, 12-bit setting, 1-kHz sineCrosstalk >84 dB(0 dBFS), limited by ADC resolutionOffset Midscale –3 mVGain error 0.68%12-bit setting, mean(1) 0.05DNL Differential nonlinearity LSB12-bit setting, maximum(1) 0.912-bit setting, mean(1) 4.612-bit setting, maximum(1) 13.3INL Integral nonlinearity LSB12-bit setting, mean, clocked by RCOSC 1012-bit setting, max, clocked by RCOSC 29Single ended input, 7-bit setting(1) 35.4Single ended input, 9-bit setting(1) 46.8Single ended input, 10-bit setting(1) 57.5Single ended input, 12-bit setting(1) 66.6SINAD Signal-to-noise-and-distortion dB(–THD+N) Differential input, 7-bit setting(1) 40.7Differential input, 9-bit setting(1) 51.6Differential input, 10-bit setting(1) 61.8Differential input, 12-bit setting(1) 70.87-bit setting 209-bit setting 36Conversion time μs10-bit setting 6812-bit setting 132(1) Measured with 300-Hz sine-wave input and VDD as reference.Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback 11Product Folder Links: CC2541
RESET_NPx.nT0299-011 2CC2541SWRS110D –JANUARY 2012–REVISED JUNE 2013www.ti.comADC CHARACTERISTICS (continued)TA= 25°C and VDD = 3 VPARAMETER TEST CONDITIONS MIN TYP MAX UNITPower consumption 1.2 mAInternal reference VDD coefficient 4 mV/VInternal reference temperature 0.4 mV/10°CcoefficientInternal reference voltage 1.24 VCONTROL INPUT AC CHARACTERISTICSTA= –40°C to 85°C, VDD = 2 V to 3.6 VPARAMETER TEST CONDITIONS MIN TYP MAX UNITThe undivided system clock is 32 MHz when crystal oscillator is used.System clock, fSYSCLK The undivided system clock is 16 MHz when calibrated 16-MHz RC 16 32 MHztSYSCLK = 1/ fSYSCLK oscillator is used.See item 1, Figure 2. This is the shortest pulse that is recognized asa complete reset pin request. Note that shorter pulses may beRESET_N low duration 1 µsrecognized but do not lead to complete reset of all modules within thechip.See item 2, Figure 2.This is the shortest pulse that is recognized asInterrupt pulse duration 20 nsan interrupt request.Figure 2. Control Input AC Characteristics12 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments IncorporatedProduct Folder Links: CC2541
SCKSSNMOSIMISOD0 D1XD0Xt2t4t6t7t5t3XT0478-01CC2541www.ti.comSWRS110D –JANUARY 2012–REVISED JUNE 2013SPI AC CHARACTERISTICSTA= –40°C to 85°C, VDD = 2 V to 3.6 VPARAMETER TEST CONDITIONS MIN TYP MAX UNITMaster, RX and TX 250t1SCK period nsSlave, RX and TX 250SCK duty cycle Master 50%Master 63t2SSN low to SCK nsSlave 63Master 63t3SCK to SSN high nsSlave 63t4MOSI early out Master, load = 10 pF 7 nst5MOSI late out Master, load = 10 pF 10 nst6MISO setup Master 90 nst7MISO hold Master 10 nsSCK duty cycle Slave 50% nst10 MOSI setup Slave 35 nst11 MOSI hold Slave 10 nst9MISO late out Slave, load = 10 pF 95 nsMaster, TX only 8Master, RX and TX 4Operating frequency MHzSlave, RX only 8Slave, RX and TX 4Figure 3. SPI Master AC CharacteristicsCopyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback 13Product Folder Links: CC2541
TimeDEBUG_CLKP2_2t1t21/fclk_dbgT0436-01T0479-01SCKSSNMOSIMISO D0 D1XD0Xt2t3Xt8t10 t11t9CC2541SWRS110D –JANUARY 2012–REVISED JUNE 2013www.ti.comFigure 4. SPI Slave AC CharacteristicsDEBUG INTERFACE AC CHARACTERISTICSTA= –40°C to 85°C, VDD = 2 V to 3.6 VPARAMETER TEST CONDITIONS MIN TYP MAX UNITfclk_dbg Debug clock frequency (see Figure 5) 12 MHzt1Allowed high pulse on clock (see Figure 5) 35 nst2Allowed low pulse on clock (see Figure 5) 35 nsEXT_RESET_N low to first falling edge on debug clock (seet3167 nsFigure 7)t4Falling edge on clock to EXT_RESET_N high (see Figure 7) 83 nst5EXT_RESET_N high to first debug command (see Figure 7) 83 nst6Debug data setup (see Figure 6) 2 nst7Debug data hold (see Figure 6) 4 nst8Clock-to-data delay (see Figure 6) Load = 10 pF 30 nsFigure 5. Debug Clock – Basic Timing14 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments IncorporatedProduct Folder Links: CC2541
TimeDEBUG_CLKP2_2DEBUG_DATA(to CC2541)P2_1DEBUG_DATA(from CC2541)P2_1t6t8t7RESET_NTimeDEBUG_CLKP2_2t3t4t5T0437-01CC2541www.ti.comSWRS110D –JANUARY 2012–REVISED JUNE 2013Figure 6. Debug Enable TimingFigure 7. Data Setup and Hold TimingTIMER INPUTS AC CHARACTERISTICSTA= –40°C to 85°C, VDD = 2 V to 3.6 VPARAMETER TEST CONDITIONS MIN TYP MAX UNITSynchronizers determine the shortest input pulse that can beInput capture pulse duration recognized. The synchronizers operate at the current system 1.5 tSYSCLKclock rate (16 MHz or 32 MHz).Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback 15Product Folder Links: CC2541
CC2541RHA Package(Top View)P0_1RESET_NP2_3 / OSC32K_Q2AVDD6NCR_BIASP0_2P0_0AVDD4P0_3AVDD1P0_4AVDD2P0_5RF_NP0_6RF_PP0_7AVDD3XOSC_Q1P1_0XOSC_Q2AVDD5P2_2P2_4 / OSC32K_Q1SCLP2_1SDAP2_0GNDP1_7P1_5P1_6P1_4DVDD1P1_3P1_1DCOUPLP1_2DVDD23012922832742652562422792321810 18 2033 3117 1934 32163515361437133812391140GNDGround PadCC2541SWRS110D –JANUARY 2012–REVISED JUNE 2013www.ti.comDC CHARACTERISTICSTA= 25°C, VDD = 3 VPARAMETER TEST CONDITIONS MIN TYP MAX UNITLogic-0 input voltage 0.5 VLogic-1 input voltage 2.4 VLogic-0 input current Input equals 0 V –50 50 nALogic-1 input current Input equals VDD –50 50 nAI/O-pin pullup and pulldown resistors 20 kΩLogic-0 output voltage, 4- mA pins Output load 4 mA 0.5 VLogic-1 output voltage, 4-mA pins Output load 4 mA 2.5 VLogic-0 output voltage, 20- mA pins Output load 20 mA 0.5 VLogic-1 output voltage, 20-mA pins Output load 20 mA 2.5 VDEVICE INFORMATIONPIN DESCRIPTIONSThe CC2541 pinout is shown in Figure 8 and a short description of the pins follows.NOTE: The exposed ground pad must be connected to a solid ground plane, as this is the ground connection for the chip.Figure 8. Pinout Top View16 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments IncorporatedProduct Folder Links: CC2541
CC2541www.ti.comSWRS110D –JANUARY 2012–REVISED JUNE 2013PIN DESCRIPTIONSPIN NAME PIN PIN TYPE DESCRIPTIONAVDD1 28 Power (analog) 2-V–3.6-V analog power-supply connectionAVDD2 27 Power (analog) 2-V–3.6-V analog power-supply connectionAVDD3 24 Power (analog) 2-V–3.6-V analog power-supply connectionAVDD4 29 Power (analog) 2-V–3.6-V analog power-supply connectionAVDD5 21 Power (analog) 2-V–3.6-V analog power-supply connectionAVDD6 31 Power (analog) 2-V–3.6-V analog power-supply connectionDCOUPL 40 Power (digital) 1.8-V digital power-supply decoupling. Do not use for supplying external circuits.DVDD1 39 Power (digital) 2-V–3.6-V digital power-supply connectionDVDD2 10 Power (digital) 2-V–3.6-V digital power-supply connectionGND 1 Ground pin Connect to GNDGND — Ground The ground pad must be connected to a solid ground plane.NC 4 Unused pins Not connectedP0_0 19 Digital I/O Port 0.0P0_1 18 Digital I/O Port 0.1P0_2 17 Digital I/O Port 0.2P0_3 16 Digital I/O Port 0.3P0_4 15 Digital I/O Port 0.4P0_5 14 Digital I/O Port 0.5P0_6 13 Digital I/O Port 0.6P0_7 12 Digital I/O Port 0.7P1_0 11 Digital I/O Port 1.0 – 20-mA drive capabilityP1_1 9 Digital I/O Port 1.1 – 20-mA drive capabilityP1_2 8 Digital I/O Port 1.2P1_3 7 Digital I/O Port 1.3P1_4 6 Digital I/O Port 1.4P1_5 5 Digital I/O Port 1.5P1_6 38 Digital I/O Port 1.6P1_7 37 Digital I/O Port 1.7P2_0 36 Digital I/O Port 2.0P2_1/DD 35 Digital I/O Port 2.1 / debug dataP2_2/DC 34 Digital I/O Port 2.2 / debug clockP2_3/ 33 Digital I/O, Analog I/O Port 2.3/32.768 kHz XOSCOSC32K_Q2P2_4/ 32 Digital I/O, Analog I/O Port 2.4/32.768 kHz XOSCOSC32K_Q1RBIAS 30 Analog I/O External precision bias resistor for reference currentRESET_N 20 Digital input Reset, active-lowRF_N 26 RF I/O Negative RF input signal to LNA during RXNegative RF output signal from PA during TXRF_P 25 RF I/O Positive RF input signal to LNA during RXPositive RF output signal from PA during TXSCL 2 I2C clock or digital I/O Can be used as I2C clock pin or digital I/O. Leave floating if not used. If groundeddisable pull upSDA 3 I2C clock or digital I/O Can be used as I2C data pin or digital I/O. Leave floating if not used. If groundeddisable pull upXOSC_Q1 22 Analog I/O 32-MHz crystal oscillator pin 1 or external clock inputXOSC_Q2 23 Analog I/O 32-MHz crystal oscillator pin 2Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback 17Product Folder Links: CC2541
SFR bus SFR busMEMORYARBITRATOR8051 CPUCOREDMAFLASHSRAMFLASH CTRLDEBUGINTERFACERESETRESET_NP2_4P2_3P2_2P2_1P2_0P1_4P1_3P1_2P1_1P1_0P1_7P1_6P1_5P0_4P0_3P0_2P0_1P0_0P0_7P0_6P0_532.768-kHzCRYSTAL OSC32-MHZCRYSTAL OSCHIGH SPEEDRC-OSC32-kHzRC-OSCCLOCK MUX andCALIBRATIONRAMUSART 0USART 1TIMER 1 (16-Bit)TIMER 3 (8-bit)TIMER 2(BLE LL TIMER)TIMER 4 (8-bit)AESENCRYPTIONandDECRYPTIONWATCHDOG TIMERIRQCTRLFLASHUNIFIEDRF_P RF_NSYNTHMODULATORPOWER-ON RESETBROWN OUTRADIOREGISTERSPOWER MGT. CONTROLLERSLEEP TIMERPDATAXRAMIRAMSFRXOSC_Q2XOSC_Q1DS ADCAUDIO / DCDIGITALANALOGMIXEDVDD (2 V–3.6 V)DCOUPLON-CHIP VOLTAGEREGULATORLink Layer EngineFREQUENCYSYNTHESIZERI2CDEMODULATORRECEIVE TRANSMITOP-ANALOG COMPARATORI/O CONTROLLER1-KB SRAMRadio ArbiterFIFOCTRLSDASCLCC2541SWRS110D –JANUARY 2012–REVISED JUNE 2013www.ti.comBLOCK DIAGRAMA block diagram of the CC2541 is shown in Figure 9. The modules can be roughly divided into one of threecategories: CPU-related modules; modules related to power, test, and clock distribution; and radio-relatedmodules. In the following subsections, a short description of each module is given.Figure 9. CC2541 Block Diagram18 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments IncorporatedProduct Folder Links: CC2541
CC2541www.ti.comSWRS110D –JANUARY 2012–REVISED JUNE 2013BLOCK DESCRIPTIONSA block diagram of the CC2541 is shown in Figure 9. The modules can be roughly divided into one of threecategories: CPU-related modules; modules related to power, test, and clock distribution; and radio-relatedmodules. In the following subsections, a short description of each module is given.CPU and MemoryThe 8051 CPU core is a single-cycle 8051-compatible core. It has three different memory access busses (SFR,DATA, and CODE/XDATA), a debug interface, and an 18-input extended interrupt unit.The memory arbiter is at the heart of the system, as it connects the CPU and DMA controller with the physicalmemories and all peripherals through the SFR bus. The memory arbiter has four memory-access points, accessof which can map to one of three physical memories: an SRAM, flash memory, and XREG/SFR registers. It isresponsible for performing arbitration and sequencing between simultaneous memory accesses to the samephysical memory.The SFR bus is drawn conceptually in Figure 9 as a common bus that connects all hardware peripherals to thememory arbiter. The SFR bus in the block diagram also provides access to the radio registers in the radioregister bank, even though these are indeed mapped into XDATA memory space.The 8-KB SRAM maps to the DATA memory space and to parts of the XDATA memory spaces. The SRAM isan ultralow-power SRAM that retains its contents even when the digital part is powered off (power mode 2 andmode 3).The 128/256 KB flash block provides in-circuit programmable non-volatile program memory for the device, andmaps into the CODE and XDATA memory spaces.PeripheralsWriting to the flash block is performed through a flash controller that allows page-wise erasure and 4-bytewiseprogramming. See User Guide for details on the flash controller.A versatile five-channel DMA controller is available in the system, accesses memory using the XDATA memoryspace, and thus has access to all physical memories. Each channel (trigger, priority, transfer mode, addressingmode, source and destination pointers, and transfer count) is configured with DMA descriptors that can belocated anywhere in memory. Many of the hardware peripherals (AES core, flash controller, USARTs, timers,ADC interface, etc.) can be used with the DMA controller for efficient operation by performing data transfersbetween a single SFR or XREG address and flash/SRAM.Each CC2541 contains a unique 48-bit IEEE address that can be used as the public device address for aBluetooth device. Designers are free to use this address, or provide their own, as described in the Bluetoothspecfication.The interrupt controller services a total of 18 interrupt sources, divided into six interrupt groups, each of whichis associated with one of four interrupt priorities. I/O and sleep timer interrupt requests are serviced even if thedevice is in a sleep mode (power modes 1 and 2) by bringing the CC2541 back to the active mode.The debug interface implements a proprietary two-wire serial interface that is used for in-circuit debugging.Through this debug interface, it is possible to erase or program the entire flash memory, control which oscillatorsare enabled, stop and start execution of the user program, execute instructions on the 8051 core, set codebreakpoints, and single-step through instructions in the code. Using these techniques, it is possible to perform in-circuit debugging and external flash programming elegantly.The I/O controller is responsible for all general-purpose I/O pins. The CPU can configure whether peripheralmodules control certain pins or whether they are under software control, and if so, whether each pin is configuredas an input or output and if a pullup or pulldown resistor in the pad is connected. Each peripheral that connectsto the I/O pins can choose between two different I/O pin locations to ensure flexibility in various applications.The sleep timer is an ultralow-power timer that can either use an external 32.768-kHz crystal oscillator or aninternal 32.753-kHz RC oscillator. The sleep timer runs continuously in all operating modes except power mode3. Typical applications of this timer are as a real-time counter or as a wake-up timer to get out of power mode 1or mode 2.A built-in watchdog timer allows the CC2541 to reset itself if the firmware hangs. When enabled by software,the watchdog timer must be cleared periodically; otherwise, it resets the device when it times out.Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback 19Product Folder Links: CC2541
CC2541SWRS110D –JANUARY 2012–REVISED JUNE 2013www.ti.comTimer 1 is a 16-bit timer with timer/counter/PWM functionality. It has a programmable prescaler, a 16-bit periodvalue, and five individually programmable counter/capture channels, each with a 16-bit compare value. Each ofthe counter/capture channels can be used as a PWM output or to capture the timing of edges on input signals. Itcan also be configured in IR generation mode, where it counts timer 3 periods and the output is ANDed with theoutput of timer 3 to generate modulated consumer IR signals with minimal CPU interaction.Timer 2 is a 40-bit timer. It has a 16-bit counter with a configurable timer period and a 24-bit overflow counterthat can be used to keep track of the number of periods that have transpired. A 40-bit capture register is alsoused to record the exact time at which a start-of-frame delimiter is received/transmitted or the exact time at whichtransmission ends. There are two 16-bit output compare registers and two 24-bit overflow compare registers thatcan be used to give exact timing for start of RX or TX to the radio or general interrupts.Timer 3 and timer 4 are 8-bit timers with timer/counter/PWM functionality. They have a programmable prescaler,an 8-bit period value, and one programmable counter channel with an 8-bit compare value. Each of the counterchannels can be used as PWM output.USART 0 and USART 1 are each configurable as either an SPI master/slave or a UART. They provide doublebuffering on both RX and TX and hardware flow control and are thus well suited to high-throughput full-duplexapplications. Each USART has its own high-precision baud-rate generator, thus leaving the ordinary timers freefor other uses. When configured as SPI slaves, the USARTs sample the input signal using SCK directly insteadof using some oversampling scheme, and are thus well-suited for high data rates.The AES encryption/decryption core allows the user to encrypt and decrypt data using the AES algorithm with128-bit keys. The AES core also supports ECB, CBC, CFB, OFB, CTR, and CBC-MAC, as well as hardwaresupport for CCM.The ADC supports 7 to 12 bits of resolution with a corresponding range of bandwidths from 30-kHz to 4-kHz,respectively. DC and audio conversions with up to eight input channels (I/O controller pins) are possible. Theinputs can be selected as single-ended or differential. The reference voltage can be internal, AVDD, or a single-ended or differential external signal. The ADC also has a temperature-sensor input channel. The ADC canautomate the process of periodic sampling or conversion over a sequence of channels.The I2Cmodule provides a digital peripheral connection with two pins and supports both master and slaveoperation. I2C support is compliant with the NXP I2C specification version 2.1 and supports standard mode (up to100 kbps) and fast mode (up to 400 kbps). In addition, 7-bit device addressing modes are supported, as well asmaster and slave modes.The ultralow-power analog comparator enables applications to wake up from PM2 or PM3 based on an analogsignal. Both inputs are brought out to pins; the reference voltage must be provided externally. The comparatoroutput is connected to the I/O controller interrupt detector and can be treated by the MCU as a regular I/O pininterrupt.20 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments IncorporatedProduct Folder Links: CC2541
1616.51717.51818.51919.5202 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6Voltage (V)Current (mA)1 Mbps GFSK 250 kHzStandard Gain SettingInput = −70 dBmTA = 25°CG005 1616.51717.51818.51919.5202 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 Voltage (V)Current (mA)TX Power Setting = 0 dBmTA = 25°CG006 −92−90−88−86−84−40 −20 0 20 40 60 80Temperature (°C)Level (dBm)1 Mbps GFSK 250 kHzStandard Gain SettingVCC = 3 VG003 −4.0−2.00.02.04.0−40 −20 0 20 40 60 80Temperature (°C)Level (dBm)TX Power Setting = 0 dBmVCC = 3 VG004 16.51717.51818.519−40 −20 0 20 40 60 80Temperature (°C)Current (mA)1 Mbps GFSK 250 kHzStandard Gain SettingInput = −70 dBmVCC = 3 VG001 1717.51818.51919.5−40 −20 0 20 40 60 80Temperature (°C)Current (mA)TX Power Setting = 0 dBmVCC = 3 VG002 CC2541www.ti.comSWRS110D –JANUARY 2012–REVISED JUNE 2013TYPICAL CHARACTERISTICSRX CURRENT TX CURRENTvs vsTEMPERATURE TEMPERATUREFigure 10. Figure 11.RX SENSITIVITY TX POWERvs vsTEMPERATURE TEMPERATUREFigure 12. Figure 13.RX CURRENT TX CURRENTvs vsSUPPLY VOLTAGE SUPPLY VOLTAGEFigure 14. Figure 15.Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback 21Product Folder Links: CC2541
−92−90−88−86−842400 2410 2420 2430 2440 2450 2460 2470 2480Frequency (MHz)Level (dBm)1 Mbps GFSK 250 kHzStandard Gain SettingTA = 25°CVCC = 3 VG009 −4−20242400 2410 2420 2430 2440 2450 2460 2470 2480Frequency (MHz)Level (dBm)TX Power Setting = 0 dBmTA = 25°CVCC = 3 VG010 −92−90−88−86−842 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6Voltage (V)Level (dBm)1 Mbps GFSK 250 kHz Standard Gain SettingTA = 25°CG007 −4−20242 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6Voltage (V)Level (dBm)TX Power Setting = 0 dBmTA = 25°CG008 CC2541SWRS110D –JANUARY 2012–REVISED JUNE 2013www.ti.comTYPICAL CHARACTERISTICS (continued)RX SENSITIVITY TX POWERvs vsSUPPLY VOLTAGE SUPPLY VOLTAGEFigure 16. Figure 17.RX SENSITIVITY TX POWERvs vsFREQUENCY FREQUENCYFigure 18. Figure 19.Table 1. Output Power(1)(2)TXPOWER Setting Typical Output Power (dBm)0xE1 00xD1 –20xC1 –40xB1 –60xA1 –80x91 –100x81 –120x71 –140x61 –160x51 –180x41 –200x31 –23(1) Measured on Texas Instruments CC2541 EM reference design with TA= 25°C, VDD = 3 V and fc= 2440 MHz. See SWRU191 forrecommended register settings.(2) 1 Mbsp, GFSK, 250-kHz deviation, Bluetooth™ low energy mode, 1% BER22 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments IncorporatedProduct Folder Links: CC2541
Current Consumption RX SGCLKCONMOD 0xBF0510152025Current (mA)0510152025303540Current Savings (%)2.1 2.4 2.7 3 3.3 3.6Supply (V)DC/DC OFFDC/DC ONCurrent SavingsCurrent Consumption TX 0 dBm02.1 2.4 2.7 3 3.3 3.6Supply (V)0510152025Current (mA)0510152025303540Current Savings (%)DC/DC OFFDC/DC ONCurrent SavingsCC2541www.ti.comSWRS110D –JANUARY 2012–REVISED JUNE 2013Table 2. Output Power and Current ConsumptionTypical Current Consumption Typical Current ConsumptionTypical Output Power (dBm) (mA)(1) With TPS62730 (mA)(2)0 18.2 14.3–20 16.8 13.1(1) Measured on Texas Instruments CC2541 EM reference design with TA= 25°C, VDD = 3 V and fc=2440 MHz. See SWRU191 for recommended register settings.(2) Measured on Texas Instruments CC2541 TPS62730 EM reference design with TA= 25°C, VDD = 3 Vand fc= 2440 MHz. See SWRU191 for recommended register settings.TYPICAL CURRENT SAVINGS WHEN USING TPS62730Figure 20. Current Savings in TX at Room Figure 21. Current Savings in RX at RoomTemperature TemperatureThe application note (SWRA365) has information regarding the CC2541 and TPS62730 combo board and thecurrent savings that can be achieved using the combo board.Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback 23Product Folder Links: CC2541
GNDSCLSDANCP1_5DVDD2P1_1P1_2P1_3P1_42-V to 3.6-V Power SupplyR301XTAL1C221 C231XTAL2C321C331C40132-kHz Crystal(1)CC2541DIE ATTACH PADRBIASAVDD4AVDD1AVDD2RF_NAVDD5XOSC_Q1XOSC_Q2AVDD3RF_PP1_0P0_7P0_6P0_5P0_4RESET_NP0_0P0_1P0_2P0_3DCOUPLDVDD1P1_6P1_7P2_0AVDD6P2_4/XOSC32K_Q1P2_3/XOSC32K_Q2P2_2P2_1Antenna(50 )W12345678910111213141516171819202122232425262728293031323334353637383940Power Supply Decoupling Capacitors are Not ShownDigital I/O Not ConnectedCC2541SWRS110D –JANUARY 2012–REVISED JUNE 2013www.ti.comAPPLICATION INFORMATIONFew external components are required for the operation of the CC2541. A typical application circuit is shown inFigure 22.(1) 32-kHz crystal is mandatory when running the BLE protocol stack in low-power modes, except if the link layer is inthe standby state (Vol. 6 Part B Section 1.1 in [1]).NOTE: Different antenna alternatives will be provided as reference designs.Figure 22. CC2541 Application CircuitTable 3. Overview of External Components (Excluding Supply Decoupling Capacitors)Component Description ValueC401 Decoupling capacitor for the internal 1.8-V digital voltage regulator 1 µFR301 Precision resistor ±1%, used for internal biasing 56 kΩInput/Output MatchingWhen using an unbalanced antenna such as a monopole, a balun should be used to optimize performance. Thebalun can be implemented using low-cost discrete inductors and capacitors. See reference design, CC2541EM,for recommended balun.24 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments IncorporatedProduct Folder Links: CC2541
L parasitic321 3311C C1 1C C= ++L parasitic221 2311C C1 1C C= ++CC2541www.ti.comSWRS110D –JANUARY 2012–REVISED JUNE 2013CrystalAn external 32-MHz crystal, XTAL1, with two loading capacitors (C221 and C231) is used for the 32-MHz crystaloscillator. See 32-MHz CRYSTAL OSCILLATOR for details. The load capacitance seen by the 32-MHz crystal isgiven by:(1)XTAL2 is an optional 32.768-kHz crystal, with two loading capacitors (C321 and C331) used for the 32.768-kHzcrystal oscillator. The 32.768-kHz crystal oscillator is used in applications where both very low sleep-currentconsumption and accurate wake-up times are needed. The load capacitance seen by the 32.768-kHz crystal isgiven by:(2)A series resistor may be used to comply with the ESR requirement.On-Chip 1.8-V Voltage Regulator DecouplingThe 1.8-V on-chip voltage regulator supplies the 1.8-V digital logic. This regulator requires a decoupling capacitor(C401) for stable operation.Power-Supply Decoupling and FilteringProper power-supply decoupling must be used for optimum performance. The placement and size of thedecoupling capacitors and the power supply filtering are very important to achieve the best performance in anapplication. TI provides a compact reference design that should be followed very closely.References1. Bluetooth® Core Technical Specification document, version 4.0http://www.bluetooth.com/SiteCollectionDocuments/Core_V40.zip2. CC253x System-on-Chip Solution for 2.4-GHz IEEE 802.15.4 and ZigBee®Applications/CC2541 System-on-Chip Solution for 2.4-GHz Bluetooth low energy Applications (SWRU191)3. Current Savings in CC254x Using the TPS62730 (SWRA365).Additional InformationTexas Instruments offers a wide selection of cost-effective, low-power RF solutions for proprietary and standard-based wireless applications for use in industrial and consumer applications. Our selection includes RFtransceivers, RF transmitters, RF front ends, and System-on-Chips as well as various software solutions for thesub-1- and 2.4-GHz frequency bands.In addition, Texas Instruments provides a large selection of support collateral such as development tools,technical documentation, reference designs, application expertise, customer support, third-party and universityprograms.The Low-Power RF E2E Online Community provides technical support forums, videos and blogs, and the chanceto interact with fellow engineers from all over the world.With a broad selection of product solutions, end application possibilities, and a range of technical support, TexasInstruments offers the broadest low-power RF portfolio. We make RF easy!The following subsections point to where to find more information.Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback 25Product Folder Links: CC2541
CC2541SWRS110D –JANUARY 2012–REVISED JUNE 2013www.ti.comTexas Instruments Low-Power RF Web Site• Forums, videos, and blogs• RF design help• E2E interactionJoin us today at www.ti.com/lprf-forum.Texas Instruments Low-Power RF Developer NetworkTexas Instruments has launched an extensive network of low-power RF development partners to help customersspeed up their application development. The network consists of recommended companies, RF consultants, andindependent design houses that provide a series of hardware module products and design services, including:• RF circuit, low-power RF, and ZigBee®design services• Low-power RF and ZigBee module solutions and development tools• RF certification services and RF circuit manufacturingNeed help with modules, engineering services or development tools?Search the Low-Power RF Developer Network tool to find a suitable partner.www.ti.com/lprfnetworkLow-Power RF eNewsletterThe Low-Power RF eNewsletter keeps you up-to-date on new products, news releases, developers’ news, andother news and events associated with low-power RF products from TI. The Low-Power RF eNewsletter articlesinclude links to get more online information.Sign up today onwww.ti.com/lprfnewsletterSpacerREVISION HISTORYChanges from Original (January 2012) to Revision A Page• Changed data sheet status from Product Preview to Production Data ................................................................................ 1Changes from Revision A (February 2012) to Revision B Page• Changed the Temperature coefficient Unit value From: mV/°C To: / 0.1°C ....................................................................... 10• Changed Figure 22 text From: Optional 32-kHz Crystal To: 32-kHz Crystal ..................................................................... 24Changes from Revision B (August 2012) to Revision C Page• Changed the "Internal reference voltage" TYP value From 1.15 V To: 1.24 V .................................................................. 12• Changed pin XOSC_Q1 Pin Type From Analog O To: Analog I/O, and changed the Pin Description .............................. 17• Changed pin XOSC_Q2 Pin Type From Analog O To: Analog I/O .................................................................................... 17Changes from Revision C (November 2012) to Revision D Page• Changed the RF TRANSMIT SECTION, Output power TYP value From: –20 To: –23 ....................................................... 8• Changed the RF TRANSMIT SECTION, Programmable output power range TYP value From: 20 To: 23 ........................ 8• Added row 0x31 to Table 1 ................................................................................................................................................. 2226 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments IncorporatedProduct Folder Links: CC2541
PACKAGE OPTION ADDENDUMwww.ti.com 23-Sep-2014Addendum-Page 1PACKAGING INFORMATIONOrderable Device Status(1)Package Type PackageDrawing Pins PackageQty Eco Plan(2)Lead/Ball Finish(6)MSL Peak Temp(3)Op Temp (°C) Device Marking(4/5)SamplesCC2541F128RHAR ACTIVE VQFN RHA 40 2500 Green (RoHS& no Sb/Br)CU NIPDAU Level-3-260C-168 HR -40 to 85 CC2541F128CC2541F128RHAT ACTIVE VQFN RHA 40 250 Green (RoHS& no Sb/Br)CU NIPDAU Level-3-260C-168 HR -40 to 85 CC2541F128CC2541F256RHAR ACTIVE VQFN RHA 40 2500 Green (RoHS& no Sb/Br)CU NIPDAU Level-3-260C-168 HR -40 to 85 CC2541F256CC2541F256RHAT ACTIVE VQFN RHA 40 250 Green (RoHS& no Sb/Br)CU NIPDAU Level-3-260C-168 HR -40 to 85 CC2541F256 (1) The marketing status values are defined as follows:ACTIVE: Product device recommended for new designs.LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availabilityinformation and additional product content details.TBD: The Pb-Free/Green conversion plan has not been defined.Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement thatlead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used betweenthe die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weightin homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuationof the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finishvalue exceeds the maximum column width.
PACKAGE OPTION ADDENDUMwww.ti.com 23-Sep-2014Addendum-Page 2Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on informationprovided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken andcontinues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF CC2541 :•Automotive: CC2541-Q1 NOTE: Qualified Version Definitions:•Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
TAPE AND REEL INFORMATION*All dimensions are nominalDevice PackageType PackageDrawing Pins SPQ ReelDiameter(mm)ReelWidthW1 (mm)A0(mm) B0(mm) K0(mm) P1(mm) W(mm) Pin1QuadrantCC2541F128RHAR VQFN RHA 40 2500 330.0 16.4 6.3 6.3 1.5 12.0 16.0 Q2CC2541F128RHAT VQFN RHA 40 250 180.0 16.4 6.3 6.3 1.5 12.0 16.0 Q2CC2541F256RHAR VQFN RHA 40 2500 330.0 16.4 6.3 6.3 1.5 12.0 16.0 Q2CC2541F256RHAT VQFN RHA 40 250 180.0 16.4 6.3 6.3 1.5 12.0 16.0 Q2PACKAGE MATERIALS INFORMATIONwww.ti.com 13-Nov-2014Pack Materials-Page 1
*All dimensions are nominalDevice Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)CC2541F128RHAR VQFN RHA 40 2500 336.6 336.6 28.6CC2541F128RHAT VQFN RHA 40 250 213.0 191.0 55.0CC2541F256RHAR VQFN RHA 40 2500 336.6 336.6 28.6CC2541F256RHAT VQFN RHA 40 250 213.0 191.0 55.0PACKAGE MATERIALS INFORMATIONwww.ti.com 13-Nov-2014Pack Materials-Page 2
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